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ILoveSpeccy/Aeon-Lite | cores/alf/src/ram/ram.vhd | 1 | 5,697 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram.vhd when simulating
-- the core, ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram;
ARCHITECTURE ram_a OF ram IS
-- synthesis translate_off
COMPONENT wrapped_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END ram_a;
| gpl-3.0 | a2f793b948a5b7d6e1858e62437a134d | 0.51571 | 3.931677 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05900_bad.vhd | 1 | 3,394 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05900_bad.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Range for integers: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_05900_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(7 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(7 downto 0) -- Counter (unsigned value)
);
end STD_05900_bad;
architecture Behavioral of STD_05900_bad is
signal Count : integer; -- Counter output signal
signal Count_Length : integer; -- Length input signal
begin
Count_Length <= to_integer(unsigned(i_Length));
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= 0;
elsif (rising_edge(i_Clock)) then
if (Count>=Count_Length) then -- Counter restarts from 0
Count <= 0;
elsif (i_Enable='1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(to_unsigned(Count, o_Count'length));
end Behavioral; | gpl-3.0 | 07e9efa11aef0598c5c9f75923ad2707 | 0.500589 | 4.561828 | false | false | false | false |
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| mit | 40088d02eeac172dfac6b794a16aafbc | 0.952396 | 1.817492 | false | false | false | false |
APastorG/APG | permutation/permutation_core.vhd | 1 | 11,087 |
--pragma translate off
--vhdl_comp_off
/*
--vhdl_comp_on
library aldec;
use aldec.matlab.all;
--vhdl_comp_off
*/
--vhdl_comp_on
--pragma translate on
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity permutation_core is
generic (
INPUT_INDEXES : integer_v;
OUTPUT_INDEXES : integer_v;
INPUT_HIGH : natural;
INPUT_LOW : natural
);
port(
Clk : in std_ulogic;
input : in sulv_v;
start : in std_ulogic;
output : out sulv_v(INPUT_HIGH downto INPUT_LOW);
finish : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture permutation_core_1 of permutation_core is
constant INPUT_LENGTH : positive := input'length;
constant CHECKS : boolean := permutation_checks(INPUT_LENGTH,
INPUT_INDEXES,
OUTPUT_INDEXES);
constant DIMENSIONS : positive := OUTPUT_INDEXES'length;
constant PARALLEL_DIMENSIONS : natural := integer(log2(real(INPUT_LENGTH)));
/* file constants */
/***********************************************************************************************/
constant FILE_PATH_M : string := DATA_FILE_DIRECTORY_M & "\\" & generate_perm_file_name(PARALLEL_DIMENSIONS,
INPUT_INDEXES,
OUTPUT_INDEXES); --for Matlab
constant FILE_PATH : string := DATA_FILE_DIRECTORY & "\"/*"*/ & generate_perm_file_name(PARALLEL_DIMENSIONS,
INPUT_INDEXES,
OUTPUT_INDEXES);
file solution_input : text;
--pragma translate off
--vhdl_comp_off
/*
--vhdl_comp_on
----------------------------------------------------------------------------------------------------
function execute_Matlab_script
return integer is
variable in_indexes_id : integer := 0;
variable out_indexes_id : integer := 0;
variable size_i : TDims(1 to 1) := (1 => DIMENSIONS);
begin
ml_setup(desktop => false);
--send data to Matlab: path name, number of parallel dimensions, input and output indexes
put_variable("file_path", FILE_PATH_M);
put_variable("p", PARALLEL_DIMENSIONS);
out_indexes_id := create_array("Po", 1, size_i);
for i in 1 to DIMENSIONS loop
put_item (OUTPUT_INDEXES(i-1), out_indexes_id, (1 => i));
end loop;
hdl2ml(out_indexes_id);
in_indexes_id := create_array("Pi", 1, size_i);
for i in 1 to DIMENSIONS loop
put_item (INPUT_INDEXES(i-1), in_indexes_id, (1 => i));
end loop;
hdl2ml(in_indexes_id);
ml_start_dir(ACTIVE_HDL_PROJECT_PATH & "\src");
eval_string("optPerm_interface");
destroy_array(in_indexes_id);
destroy_array(out_indexes_id);
return 0;
end function;
constant DUMMY : integer := execute_Matlab_script;
----------------------------------------------------------------------------------------------------
--vhdl_comp_off
*/
--vhdl_comp_on
--pragma translate on
--reads the number of elemental bit-exchange opertations in the solution that is in the file.
--Produces an error if the file doesn't exist and we are in synthesis trying to read it
impure function read_elemental_ops
return natural is
variable currentline : line;
variable currentchar : character;
variable solution : natural := 0;
begin
--read solution file
file_open(solution_input, FILE_PATH, READ_MODE);
if endfile(solution_input) then
assert false
report "The values needed to generate optimum permutations have not yet been " &
"generated. It is first required to launch the simulation in order to achieve this"
severity error;
end if;
if not endfile(solution_input) then
readline(solution_input, currentline);
for i in 1 to currentline'length loop
read(currentline, currentchar);
solution := 10*solution + (character'pos(currentchar)-character'pos('0'));
end loop;
end if;
file_close(solution_input);
return solution;
end function;
constant ELEMENTAL_OPS : natural := read_elemental_ops;
--reads the solution vertexes and returns a static structure with the data
impure function read_optimal_perm
return integer_vv is
variable result : integer_vv(1 to ELEMENTAL_OPS)(1 to 2);
variable currentline : line;
variable currentchar : character;
variable aux : natural := 0;
begin
file_open(solution_input, FILE_PATH, READ_MODE);
if not endfile(solution_input) then
readline(solution_input, currentline);--discard first line
if not endfile(solution_input) then
for i in 1 to ELEMENTAL_OPS loop
readline(solution_input, currentline);
for j in 1 to currentline'length loop
read(currentline, currentchar);
if currentchar = ' ' then
result(i)(1) := aux;
aux := 0;
else
aux := 10*aux + (character'pos(currentchar)-character'pos('0'));
end if;
end loop;
--add the last read member
result(i)(2) := aux;
aux := 0;
end loop;
end if;
end if;
file_close(solution_input);
return result;
end function;
constant OPTIMAL_PERM : integer_vv(1 to ELEMENTAL_OPS)(1 to 2) := read_optimal_perm;
/* signals */
/***********************************************************************************************/
signal inter : sulv_vv(0 to ELEMENTAL_OPS)(INPUT_LENGTH-1 downto 0)(input'element'length-1 downto 0);
signal start_delayed : std_ulogic_vector(0 to ELEMENTAL_OPS);
/*================================================================================================*/
/*================================================================================================*/
begin
check_if_permutations_are_needed:
if ELEMENTAL_OPS > 0 generate
begin
--control part
start_delayed(0) <= start;
finish <= start_delayed(ELEMENTAL_OPS);
--signal part
inter(0) <= input;
output <= inter(ELEMENTAL_OPS);
generate_elemental_operations:
for i in 1 to ELEMENTAL_OPS generate
begin
parallel_parallel:
if is_pp_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate
begin
perm_pp:
entity work.perm_pp
generic map(
indexes => OPTIMAL_PERM(i)
)
port map(
input => inter(i-1),
start => start_delayed(i-1),
output => inter(i),
finish => start_delayed(i)
);
end;
end generate;
serial_parallel:
if is_sp_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate
constant aux_left : natural := contiguous_ps_latency(OPTIMAL_PERM,
PARALLEL_DIMENSIONS,
i,
left => true);
constant aux_right : natural := contiguous_ps_latency(OPTIMAL_PERM,
PARALLEL_DIMENSIONS,
i,
left => false);
begin
perm_sp:
entity work.perm_sp
generic map(
dimensions => DIMENSIONS,
p_dimensions => PARALLEL_DIMENSIONS,
serial_dim => maximum(OPTIMAL_PERM(i)),
parallel_dim => minimum(OPTIMAL_PERM(i)),
left_ps_latency => aux_left,
right_ps_latency => aux_right
)
port map(
clk => clk,
input => inter(i-1),
start => start_delayed(i-1),
output => inter(i),
finish => start_delayed(i)
);
end;
end generate;
serial_serial:
if is_ss_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate
begin
perm_ss:
entity work.perm_ss
generic map(
indexes => OPTIMAL_PERM(i),
dimensions => DIMENSIONS
)
port map(
clk => clk,
input => inter(i-1),
start => start_delayed(i-1),
output => inter(i),
finish => start_delayed(i)
);
end;
end generate;
end;
end generate;
end;
else generate
begin
output <= input;
finish <= start;
end;
end generate;
end architecture;
| mit | 37c4ea6f9e9f395180cd1a04db24c34f | 0.419861 | 5.227251 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/video/video.vhd | 1 | 6,061 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 65MHz
RESET : in std_logic; -- Reset (active low)
VRAM_A : out std_logic_vector(13 downto 0);
VRAM_D : in std_logic_vector(7 downto 0);
COLORS : in std_logic_vector(6 downto 0);
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic; -- Ver. sync
HI_RES : in std_logic; -- PK-02 512 x 256 mode
BLANK_SCR : in std_logic -- PK-02 Blank Screen
);
end video;
architecture BEHAVIORAL of video is
-- VGA timing constants (XGA - 1024x768@60) (512x768@60)
-- HOR
constant HSIZE : INTEGER := 512; -- Visible area
constant HFP : INTEGER := 12; -- Front porch
constant HS : INTEGER := 68; -- HSync pulse
constant HB : INTEGER := 80; -- Back porch
constant HOFFSET : INTEGER := 0; -- HSync offset
-- VER
constant VSIZE : INTEGER := 768; -- Visible area
constant VFP : INTEGER := 3; -- Front porch
constant VS : INTEGER := 6; -- VSync pulse
constant VB : INTEGER := 29; -- Back porch
constant VOFFSET : INTEGER := 0; -- VSync offset
------------------------------------------------------------
signal H_COUNTER : UNSIGNED(9 downto 0); -- Horizontal Counter
signal V_COUNTER : UNSIGNED(9 downto 0); -- Vertical Counter
signal THREE_ROW_CNT : UNSIGNED(1 downto 0); -- 3 Row Counter
signal ROW_COUNTER : UNSIGNED(7 downto 0); -- Korvet Row Counter
signal PAPER : STD_LOGIC; -- Paper zone
signal PAPER_L : STD_LOGIC; -- Paper zone
signal COLOR_R : STD_LOGIC;
signal COLOR_G : STD_LOGIC;
signal COLOR_B : STD_LOGIC;
signal PIX0 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX1 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX : STD_LOGIC_VECTOR(7 downto 0);
signal COLOR : STD_LOGIC_VECTOR(1 downto 0);
begin
u_COLOR_MUX : entity work.clr_mux
port map(
color => COLOR,
portb => COLORS,
out_r => COLOR_R,
out_g => COLOR_G,
out_b => COLOR_B );
COLOR <= "00" when BLANK_SCR = '1' else
PIX1(3 - to_integer(H_COUNTER(2 downto 1))) & PIX0(3 - to_integer(H_COUNTER(2 downto 1))) when HI_RES = '0' else
PIX (7 - to_integer(H_COUNTER(2 downto 0))) & PIX (7 - to_integer(H_COUNTER(2 downto 0)));
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= (others=>'0');
else
if H_COUNTER = 544 then
if V_COUNTER < 768 then
THREE_ROW_CNT <= THREE_ROW_CNT + 1;
if THREE_ROW_CNT = 2 then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= ROW_COUNTER + 1;
end if;
else
ROW_COUNTER <= (others=>'0');
THREE_ROW_CNT <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
HSYNC <= '1';
VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HOFFSET + HFP) and H_COUNTER < (HSIZE + HOFFSET + HFP + HS) then
HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VOFFSET + VFP) and V_COUNTER < (VSIZE + VOFFSET + VFP + VS) then
VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" =>
VRAM_A <= std_logic_vector(ROW_COUNTER) & std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX0 <= VRAM_D(3 downto 0);
PIX1 <= VRAM_D(7 downto 4);
PIX <= VRAM_D(7 downto 0);
PAPER_L <= PAPER;
when OTHERS =>
null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_L = '1' then
if THREE_ROW_CNT = "01" then
R <= COLOR_R & COLOR_R & COLOR_R & COLOR_R;
G <= COLOR_G & COLOR_G & COLOR_G & COLOR_G;
B <= COLOR_B & COLOR_B & COLOR_B & COLOR_B;
else
R <= COLOR_R & "000";
G <= COLOR_G & "000";
B <= COLOR_B & "000";
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | d0479db00b8a3a6fd400ff6fffc858e3 | 0.448606 | 3.840938 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/plasma_if.vhd | 1 | 5,212 | ---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/6/02
-- FILENAME: plasma_if.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity divides the clock by two and interfaces to the
-- Altera EP20K200EFC484-2X FPGA board.
-- Xilinx Spartan-3 XC3S200FT256-4 FPGA.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use work.mlite_pack.all;
entity plasma_if is
port(clk_in : in std_logic;
reset : in std_logic;
uart_read : in std_logic;
uart_write : out std_logic;
ram_address : out std_logic_vector(31 downto 2);
ram_data : inout std_logic_vector(31 downto 0);
ram_ce1_n : out std_logic;
ram_ub1_n : out std_logic;
ram_lb1_n : out std_logic;
ram_ce2_n : out std_logic;
ram_ub2_n : out std_logic;
ram_lb2_n : out std_logic;
ram_we_n : out std_logic;
ram_oe_n : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma_if
architecture logic of plasma_if is
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
signal clk_reg : std_logic;
signal we_n_next : std_logic;
signal we_n_reg : std_logic;
signal mem_address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_reg : std_logic_vector(31 downto 0);
signal write_byte_enable : std_logic_vector(3 downto 0);
signal mem_pause_in : std_logic;
begin --architecture
--Divide 50 MHz clock by two
clk_div: process(reset, clk_in, clk_reg, we_n_next)
begin
if reset = '1' then
clk_reg <= '0';
elsif rising_edge(clk_in) then
clk_reg <= not clk_reg;
end if;
if reset = '1' then
we_n_reg <= '1';
data_reg <= (others => '0');
elsif falling_edge(clk_in) then
we_n_reg <= we_n_next or not clk_reg;
data_reg <= ram_data;
end if;
end process; --clk_div
mem_pause_in <= '0';
ram_address <= mem_address(31 downto 2);
ram_we_n <= we_n_reg;
--For Xilinx Spartan-3 Starter Kit
ram_control:
process(clk_reg, mem_address, write_byte_enable, data_write)
begin
if mem_address(30 downto 28) = "001" then --RAM
ram_ce1_n <= '0';
ram_ce2_n <= '0';
if write_byte_enable = "0000" then --read
ram_data <= (others => 'Z');
ram_ub1_n <= '0';
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
we_n_next <= '1';
ram_oe_n <= '0';
else --write
if clk_reg = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not write_byte_enable(3);
ram_lb1_n <= not write_byte_enable(2);
ram_ub2_n <= not write_byte_enable(1);
ram_lb2_n <= not write_byte_enable(0);
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
ram_data <= (others => 'Z');
ram_ce1_n <= '1';
ram_ub1_n <= '1';
ram_lb1_n <= '1';
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process; --ram_control
u1_plama: plasma
generic map (memory_type => "XILINX_16X",
log_file => "UNUSED")
PORT MAP (
clk => clk_reg,
reset => reset,
uart_write => uart_write,
uart_read => uart_read,
address => mem_address,
data_write => data_write,
data_read => data_reg,
write_byte_enable => write_byte_enable,
mem_pause_in => mem_pause_in,
gpio0_out => gpio0_out,
gpioA_in => gpioA_in);
end; --architecture logic
| gpl-3.0 | dbe1dfd9fadbe60a320461124ae00656 | 0.491558 | 3.476985 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/top.vhd | 1 | 13,333 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: top
--
-- Description:
--
-- Simple test for VGA control
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity top is
generic (
RES_TYPE : natural := 1;
TEXT_MEM_DATA_WIDTH : natural := 6;
GRAPH_MEM_DATA_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
-- vga
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
blank_o : out std_logic;
pix_clock_o : out std_logic;
psave_o : out std_logic;
sync_o : out std_logic;
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
-- direct_mode i display_mode za prekidace
direct_mode_i : in std_logic;
display_mode_i : in std_logic_vector(1 downto 0)
);
end top;
architecture rtl of top is
constant RES_NUM : natural := 6;
type t_param_array is array (0 to RES_NUM-1) of natural;
constant H_RES_ARRAY : t_param_array := ( 0 => 64, 1 => 640, 2 => 800, 3 => 1024, 4 => 1152, 5 => 1280, others => 0 );
constant V_RES_ARRAY : t_param_array := ( 0 => 48, 1 => 480, 2 => 600, 3 => 768, 4 => 864, 5 => 1024, others => 0 );
constant MEM_ADDR_WIDTH_ARRAY : t_param_array := ( 0 => 12, 1 => 14, 2 => 13, 3 => 14, 4 => 14, 5 => 15, others => 0 );
constant MEM_SIZE_ARRAY : t_param_array := ( 0 => 48, 1 => 4800, 2 => 7500, 3 => 12576, 4 => 15552, 5 => 20480, others => 0 );
constant H_RES : natural := H_RES_ARRAY(RES_TYPE);
constant V_RES : natural := V_RES_ARRAY(RES_TYPE);
constant MEM_ADDR_WIDTH : natural := MEM_ADDR_WIDTH_ARRAY(RES_TYPE);
constant MEM_SIZE : natural := MEM_SIZE_ARRAY(RES_TYPE);
component vga_top is
generic (
H_RES : natural := 640;
V_RES : natural := 480;
MEM_ADDR_WIDTH : natural := 32;
GRAPH_MEM_ADDR_WIDTH : natural := 32;
TEXT_MEM_DATA_WIDTH : natural := 32;
GRAPH_MEM_DATA_WIDTH : natural := 32;
RES_TYPE : integer := 1;
MEM_SIZE : natural := 4800
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
dir_pixel_column_o : out std_logic_vector(10 downto 0);
dir_pixel_row_o : out std_logic_vector(10 downto 0);
-- mode interface
display_mode_i : in std_logic_vector(1 downto 0); -- 00 - text mode, 01 - graphics mode, 01 - text & graphics
-- text mode interface
text_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
text_data_i : in std_logic_vector(TEXT_MEM_DATA_WIDTH-1 downto 0);
text_we_i : in std_logic;
-- graphics mode interface
graph_addr_i : in std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
graph_data_i : in std_logic_vector(GRAPH_MEM_DATA_WIDTH-1 downto 0);
graph_we_i : in std_logic;
--
font_size_i : in std_logic_vector(3 downto 0);
show_frame_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
-- vga
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
blank_o : out std_logic;
pix_clock_o : out std_logic;
vga_rst_n_o : out std_logic;
psave_o : out std_logic;
sync_o : out std_logic;
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0)
);
end component;
component ODDR2
generic(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
component counter IS
GENERIC (
WIDTH : positive := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cnt_rst_i : IN STD_LOGIC;
cnt_en_i : IN STD_LOGIC;
cnt_o : out std_logic_vector(WIDTH-1 downto 0)
);
END component;
constant update_period : std_logic_vector(31 downto 0) := conv_std_logic_vector(1, 32);
constant GRAPH_MEM_ADDR_WIDTH : natural := MEM_ADDR_WIDTH + 6;-- graphics addres is scales with minumum char size 8*8 log2(64) = 6
-- text
signal message_lenght : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
signal graphics_lenght : std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
signal direct_mode : std_logic;
--
signal font_size : std_logic_vector(3 downto 0);
signal show_frame : std_logic;
signal display_mode : std_logic_vector(1 downto 0); -- 01 - text mode, 10 - graphics mode, 11 - text & graphics
signal foreground_color : std_logic_vector(23 downto 0);
signal background_color : std_logic_vector(23 downto 0);
signal frame_color : std_logic_vector(23 downto 0);
signal char_we : std_logic;
signal char_address : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
signal char_value : std_logic_vector(5 downto 0);
signal pixel_address : std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
signal pixel_value : std_logic_vector(GRAPH_MEM_DATA_WIDTH-1 downto 0);
signal pixel_we : std_logic;
signal pix_clock_s : std_logic;
signal vga_rst_n_s : std_logic;
signal pix_clock_n : std_logic;
signal dir_red : std_logic_vector(7 downto 0);
signal dir_green : std_logic_vector(7 downto 0);
signal dir_blue : std_logic_vector(7 downto 0);
signal dir_pixel_column : std_logic_vector(10 downto 0);
signal dir_pixel_row : std_logic_vector(10 downto 0);
type color_array is array(0 to 7) of std_logic_vector(23 downto 0);
signal colors : color_array := (
x"ffffff", x"cccc00", x"00ccff", x"00cc00",
x"e600e6", x"ff0000", x"0000ff", x"000000" );
type char_array is array(0 to 6) of std_logic_vector(5 downto 0);
signal chars : char_array := ("000001", "000010", "000011", "000100", "000101", "000110", "000111");
signal cnt1 : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
signal cnt2 : std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
signal cnt_en_s : std_logic;
signal cnt1_rst : std_logic;
signal cnt2_rst : std_logic;
signal in_rectangle : std_logic;
constant CNT2_MAX : integer := H_RES/GRAPH_MEM_DATA_WIDTH*V_RES;
signal cnt_clk : std_logic;
begin
-- calculate message lenght from font size
message_lenght <= conv_std_logic_vector(MEM_SIZE/64, MEM_ADDR_WIDTH)when (font_size = 3) else -- note: some resolution with font size (32, 64) give non integer message lenght (like 480x640 on 64 pixel font size) 480/64= 7.5
conv_std_logic_vector(MEM_SIZE/16, MEM_ADDR_WIDTH)when (font_size = 2) else
conv_std_logic_vector(MEM_SIZE/4 , MEM_ADDR_WIDTH)when (font_size = 1) else
conv_std_logic_vector(MEM_SIZE , MEM_ADDR_WIDTH);
graphics_lenght <= conv_std_logic_vector(MEM_SIZE*8*8, GRAPH_MEM_ADDR_WIDTH);
-- removed to inputs pin
-- direct_mode <= '1';
-- display_mode <= "10"; -- 01 - text mode, 10 - graphics mode, 11 - text & graphics
direct_mode <= direct_mode_i;
display_mode <= display_mode_i;
font_size <= x"1";
show_frame <= '1';
foreground_color <= x"FFFFFF";
background_color <= x"000000";
frame_color <= x"FF0000";
clk5m_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE","C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map (
Q => pix_clock_o, -- 1-bit output data
C0 => pix_clock_s, -- 1-bit clock input
C1 => pix_clock_n, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
pix_clock_n <= not(pix_clock_s);
counter1 : counter
generic map(
WIDTH => MEM_ADDR_WIDTH
) port map (
clk_i => pix_clock_s,
rst_i => vga_rst_n_s,
cnt_rst_i => cnt1_rst,
cnt_en_i => cnt_en_s,
cnt_o => cnt1
);
counter2 : counter
generic map(
WIDTH => GRAPH_MEM_ADDR_WIDTH
) port map (
clk_i => pix_clock_s,
rst_i => vga_rst_n_s,
cnt_rst_i => cnt2_rst,
cnt_en_i => cnt_en_s,
cnt_o => cnt2
);
-- component instantiation
vga_top_i: vga_top
generic map(
RES_TYPE => RES_TYPE,
H_RES => H_RES,
V_RES => V_RES,
MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
GRAPH_MEM_ADDR_WIDTH => GRAPH_MEM_ADDR_WIDTH,
TEXT_MEM_DATA_WIDTH => TEXT_MEM_DATA_WIDTH,
GRAPH_MEM_DATA_WIDTH => GRAPH_MEM_DATA_WIDTH,
MEM_SIZE => MEM_SIZE
)
port map(
clk_i => clk_i,
reset_n_i => reset_n_i,
--
direct_mode_i => direct_mode,
dir_red_i => dir_red,
dir_green_i => dir_green,
dir_blue_i => dir_blue,
dir_pixel_column_o => dir_pixel_column,
dir_pixel_row_o => dir_pixel_row,
-- cfg
display_mode_i => display_mode, -- 01 - text mode, 10 - graphics mode, 11 - text & graphics
-- text mode interface
text_addr_i => char_address,
text_data_i => char_value,
text_we_i => char_we,
-- graphics mode interface
graph_addr_i => pixel_address,
graph_data_i => pixel_value,
graph_we_i => pixel_we,
-- cfg
font_size_i => font_size,
show_frame_i => show_frame,
foreground_color_i => foreground_color,
background_color_i => background_color,
frame_color_i => frame_color,
-- vga
vga_hsync_o => vga_hsync_o,
vga_vsync_o => vga_vsync_o,
blank_o => blank_o,
pix_clock_o => pix_clock_s,
vga_rst_n_o => vga_rst_n_s,
psave_o => psave_o,
sync_o => sync_o,
red_o => red_o,
green_o => green_o,
blue_o => blue_o
);
cnt1_rst <= '1';
-- cnt2_rst <= '1';
-- na osnovu signala iz vga_top modula dir_pixel_column i dir_pixel_row realizovati logiku koja genereise
--dir_red
--dir_green
--dir_blue
dir_red <= colors( conv_integer( dir_pixel_column(8 downto 6) ) )( 23 downto 16 );
dir_green <= colors( conv_integer( dir_pixel_column(8 downto 6) ) )( 15 downto 8 );
dir_blue <= colors( conv_integer( dir_pixel_column(8 downto 6) ) )( 7 downto 0 );
-- koristeci signale realizovati logiku koja pise po TXT_MEM
-- char_address
-- char_value
-- char_we
char_address <= cnt1 + 100;
char_value <= chars(conv_integer( cnt1 )) when cnt1 < chars'length else "100000";
char_we <= '1' when cnt1 < 500 else '0';
cnt_en_s <= '1' when direct_mode = '0' and display_mode /= "00" else '0';
-- koristeci signale realizovati logiku koja pise po GRAPH_MEM
-- pixel_address
-- pixel_value
-- pixel_we
cnt2_rst <= '0' when cnt2 >= CNT2_MAX-2 else '1';
in_rectangle <= '1' when dir_pixel_column > 4*H_RES/8 and dir_pixel_column < 6*H_RES/8 and
dir_pixel_row > 4*V_RES/8 and dir_pixel_row < 6*V_RES/8 else '0';
pixel_address <= cnt2 when cnt2 < CNT2_MAX else (others => '0');
pixel_value <= (others => '1') when in_rectangle = '1' else (others => '0');
pixel_we <= '1'; -- when in_rectangle = '1' and cnt2 < CNT2_MAX else '0';
end rtl;
| mit | 659ef18731bde0568834dc07f20b9454 | 0.533788 | 3.229111 | false | false | false | false |
APastorG/APG | butterfly/butterfly_s.vhd | 1 | 2,648 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ The input must have ranges of type (x to x+(2^n)-1)(high downto low)
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity butterfly_s is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
EXTEND_opt : boolean := true --default value
);
port(
clk : in std_ulogic;
input : in u_sfixed_v;
output : out u_sfixed_v
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture butterfly_s_1 of butterfly_s is
--signal inter : u_sfixed_v(input'range)(input'element'left+1 downto input'element'right);
constant LENGTH : positive := input'length;
/*================================================================================================*/
/*================================================================================================*/
begin
butterfly_core_s_1:
entity work.butterfly_core_s
generic map(
SPEED_opt => SPEED_opt,
EXTEND_opt => EXTEND_opt,
RANGE1_LEFT => input'left,
RANGE1_RIGHT => input'right,
RANGE2_LEFT => input'element'left,
RANGE2_RIGHT => input'element'right
)
port map(
clk => clk,
input => input,
output => output
);
end architecture; | mit | a7b3900041c6c3ca55b919194cb2de19 | 0.362663 | 4.79633 | false | false | false | false |
APastorG/APG | complex_const_multiplier/complex_const_mult_s.vhd | 1 | 3,326 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.complex_const_mult_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity complex_const_mult_s is
generic(
SPEED_opt : T_speed := t_exc;
ROUND_STYLE_opt : T_round_style := fixed_truncate;
ROUND_TO_BIT_opt : integer_exc := integer'low;
MAX_ERROR_PCT_opt : real_exc := real'low;
MIN_OUTPUT_BIT : integer := integer'low;
MULTIPLICAND_REAL : real;
MULTIPLICAND_IMAG : real
);
port(
clk : in std_ulogic;
input_real : in u_sfixed;
input_imag : in u_sfixed;
valid_input : in std_ulogic;
output_real : out u_sfixed;
output_imag : out u_sfixed;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture complex_const_mult_s_1 of complex_const_mult_s is
/*================================================================================================*/
/*================================================================================================*/
begin
complex_const_mult_core_s_1:
entity work.complex_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICAND_REAL => MULTIPLICAND_REAL,
MULTIPLICAND_IMAG => MULTIPLICAND_IMAG,
INPUT_HIGH => input_real'high,
INPUT_LOW => input_real'low
)
port map(
clk => clk,
input_real => input_real,
input_imag => input_imag,
valid_input => valid_input,
output_real => output_real,
output_imag => output_imag,
valid_output => valid_output
);
end architecture; | mit | 18d3afaea47d569b8fafab02e2e450b1 | 0.38305 | 4.478912 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/korvet.vhd | 1 | 37,472 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity korvet is
Port (
CLK50 : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CS : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic;
COMM_CSA : in std_logic;
COMM_CSD : in std_logic;
COMM_SCK : in std_logic;
COMM_MOSI : in std_logic;
COMM_MISO : out std_logic;
COMM_REQ : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end korvet;
architecture RTL of korvet is
-- Verilog Modules
----------------------------------------------------------
component k580wm80a is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
intr : in std_logic;
idata : in std_logic_vector(7 downto 0);
addr : out std_logic_vector(15 downto 0);
sync : out std_logic;
rd : out std_logic;
wr : out std_logic;
inta : out std_logic;
odata : out std_logic_vector(7 downto 0) );
end component;
-- component cpu8080 is
-- port(
-- addr : out std_logic_vector(15 downto 0);
-- data : in std_logic_vector(7 downto 0);
-- datao : out std_logic_vector(7 downto 0);
-- readmem : out std_logic;
-- writemem : out std_logic;
-- readio : out std_logic;
-- writeio : out std_logic;
-- intr : in std_logic;
-- inta : out std_logic;
-- waitr : in std_logic;
-- reset : in std_logic;
-- cke : in std_logic;
-- clock : in std_logic );
-- end component;
component k580wi53 is
port(
clk : in std_logic;
c0 : in std_logic;
c1 : in std_logic;
c2 : in std_logic;
g0 : in std_logic;
g1 : in std_logic;
g2 : in std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
addr : in std_logic_vector(1 downto 0);
rd : in std_logic;
we_n : in std_logic;
idata : in std_logic_vector(7 downto 0);
odata : out std_logic_vector(7 downto 0) );
end component;
-- Memory Mapper Values -------------------------------------
constant M_RAM : std_logic_vector(2 downto 0) := "000";
constant M_ROM : std_logic_vector(2 downto 0) := "001";
constant M_KEYBOARD : std_logic_vector(2 downto 0) := "010";
constant M_PORTBASE : std_logic_vector(2 downto 0) := "011";
constant M_REGBASE : std_logic_vector(2 downto 0) := "100";
constant M_CGRAM : std_logic_vector(2 downto 0) := "101";
constant M_VRAM : std_logic_vector(2 downto 0) := "110";
-------------------------------------------------------------
signal CLK : std_logic;
signal RESET : std_logic := '1';
signal TICK : unsigned(3 downto 0);
signal TICK2_0 : unsigned(1 downto 0);
signal TICK2_1 : unsigned(4 downto 0);
signal CPU_PAUSE : std_logic;
signal CPU_RESET : std_logic;
signal CPU_CLK : std_logic;
signal CPU_INTA : std_logic;
signal CPU_INTR : std_logic;
signal CPU_RD : std_logic;
signal CPU_SYNC : std_logic;
signal CPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal MAPPER_DO : std_logic_vector(2 downto 0);
signal KEYBOARD_DO : std_logic_vector(7 downto 0);
signal SYSREG : std_logic_vector(4 downto 0);
signal COLORREG : std_logic_vector(7 downto 0);
signal KB_SG_RESET : std_logic;
signal CHRAM_WR : std_logic;
signal CHRAM_DO : std_logic_vector(8 downto 0);
signal CHRAM_VA : std_logic_vector(9 downto 0);
signal CHRAM_VD : std_logic_vector(8 downto 0);
signal PPI1_WR : std_logic;
signal PPI1_DO : std_logic_vector(7 downto 0);
signal PPI1_PAI : std_logic_vector(7 downto 0);
signal PPI1_PAO : std_logic_vector(7 downto 0);
signal PPI1_PBI : std_logic_vector(7 downto 0);
signal PPI1_PBO : std_logic_vector(7 downto 0);
signal PPI1_PCI : std_logic_vector(7 downto 0);
signal PPI1_PCO : std_logic_vector(7 downto 0);
signal PPI2_WR : std_logic;
signal PPI2_DO : std_logic_vector(7 downto 0);
signal PPI2_PAI : std_logic_vector(7 downto 0);
signal PPI2_PAO : std_logic_vector(7 downto 0);
signal PPI2_PBI : std_logic_vector(7 downto 0);
signal PPI2_PBO : std_logic_vector(7 downto 0);
signal PPI2_PCI : std_logic_vector(7 downto 0);
signal PPI2_PCO : std_logic_vector(7 downto 0);
signal PPI3_WR : std_logic;
signal PPI3_DO : std_logic_vector(7 downto 0);
signal PPI3_PAI : std_logic_vector(7 downto 0);
signal PPI3_PAO : std_logic_vector(7 downto 0);
signal PPI3_PBI : std_logic_vector(7 downto 0);
signal PPI3_PBO : std_logic_vector(7 downto 0);
signal PPI3_PCI : std_logic_vector(7 downto 0);
signal PPI3_PCO : std_logic_vector(7 downto 0);
signal PIC_WR : std_logic;
signal PIC_DO : std_logic_vector(7 downto 0);
signal TIMER_RD : std_logic;
signal TIMER_WR : std_logic;
signal TIMER_DO : std_logic_vector(7 downto 0);
signal TIMER_C0 : std_logic;
signal TIMER_OUT0 : std_logic;
signal CDI : std_logic;
signal CDO : std_logic;
signal VBLANK : std_logic;
signal VBLANK_2 : std_logic;
signal VBLANK_TICK : unsigned(3 downto 0);
signal DRIVE : std_logic_vector(1 downto 0);
alias FLOPPY_SIDE : std_logic is PPI1_PBO(4);
alias DRV_SEL : std_logic_vector(3 downto 0) is PPI1_PBO(3 downto 0);
alias VRAM_PAGE : std_logic_vector(1 downto 0) is PPI1_PCO(7 downto 6);
alias INVON : std_logic is PPI1_PCO(5);
alias INVOFF : std_logic is PPI1_PCO(4);
alias WIDEFONT : std_logic is PPI1_PCO(3);
alias ALTFONT : std_logic is PPI1_PCO(2);
alias VIEW_PAGE : std_logic_vector(1 downto 0) is PPI1_PCO(1 downto 0);
alias TAPE_OUT0 : std_logic is PPI2_PCO(0);
alias TAPE_OUT1 : std_logic is PPI2_PCO(1);
alias SOUND_EN : std_logic is PPI2_PCO(3);
signal RAM_DO : std_logic_vector(7 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal VRAM_DO : std_logic_vector(7 downto 0);
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal LUT_A : std_logic_vector(3 downto 0);
signal LUT_D : std_logic_vector(3 downto 0);
signal FONTROM_A : std_logic_vector(11 downto 0);
signal FONTROM_DO : std_logic_vector(7 downto 0);
signal CACHE_AI : std_logic_vector(5 downto 0);
signal CACHE_DI : std_logic_vector(31 downto 0);
signal CACHE_WE : std_logic;
signal CACHE_AO : std_logic_vector(5 downto 0);
signal CACHE_DO : std_logic_vector(31 downto 0);
signal CACHE_SWAP : std_logic;
signal CACHE_CNT : unsigned(5 downto 0);
signal CACHE_RD : std_logic;
signal PLANE0 : std_logic_vector(7 downto 0); -- PLANEs - temporary data from VRAM for write to cache and read/write VRAM
signal PLANE1 : std_logic_vector(7 downto 0);
signal PLANE2 : std_logic_vector(7 downto 0);
signal SCANLINE : std_logic_vector(7 downto 0);
signal SOUND : std_logic;
-- signal SOUND_L : std_logic_vector(15 downto 0);
-- signal SOUND_R : std_logic_vector(15 downto 0);
signal TAPE_IN : std_logic;
signal FLOPPY_DO : std_logic_vector(7 downto 0);
signal PAUSE_ONESHOT : std_logic;
signal COMM_ADDR_O : std_logic_vector(7 downto 0);
signal COMM_ADDR_I : std_logic_vector(7 downto 0);
signal COMM_ADDR_REQ : std_logic;
signal COMM_ADDR_ACK : std_logic;
signal COMM_DATA_O : std_logic_vector(7 downto 0);
signal COMM_DATA_I : std_logic_vector(7 downto 0);
signal COMM_DATA_REQ : std_logic;
signal COMM_DATA_ACK : std_logic;
type LUT_T is array (0 to 15) of std_logic_vector(3 downto 0);
signal LUT : LUT_T;
-- Memory Controller Statemachine
type STATE_TYPE is (ST_IDLE, ST_RAMREAD, ST_RAMWRITE1, ST_RAMWRITE2, ST_CACHEREAD1, ST_CACHEREAD2, ST_CACHEREAD3, ST_CACHEREAD4,
ST_VRAMREAD1, ST_VRAMREAD2, ST_VRAMREAD3, ST_VRAMREAD4, ST_VRAMREAD5,
ST_VRAMWRITE1, ST_VRAMWRITE2, ST_VRAMWRITE3, ST_VRAMWRITE4, ST_VRAMWRITE5, ST_VRAMWRITE6, ST_VRAMWRITE7, ST_VRAMWRITE8,
ST_FLOPPY1, ST_FLOPPY2, ST_FLOPPY3 );
signal STATE : STATE_TYPE := ST_IDLE;
signal NSTATE : STATE_TYPE := ST_IDLE;
begin
-- PLL Make 32.5MHz Design Clock from 50MHz Oscillator
----------------------------------------------------------
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK );
-- Memory Mapper
----------------------------------------------------------
u_MAPPER : entity work.mapper
port map(
CLKA => CLK,
ADDRA => SYSREG & CPU_A(15 downto 8),
DOUTA => MAPPER_DO );
-- Memory Mapper
----------------------------------------------------------
u_ROM : entity work.rom
port map(
CLKA => CLK,
ADDRA => CPU_A(14 downto 0),
DOUTA => ROM_DO );
-- i8080 CPU
----------------------------------------------------------
u_CPU : k580wm80a
port map(
clk => CLK,
ce => CPU_CLK,
reset => CPU_RESET,
intr => CPU_INTR,
idata => CPU_DI,
addr => CPU_A,
sync => CPU_SYNC,
rd => CPU_RD,
wr => CPU_WR,
inta => CPU_INTA,
odata => CPU_DO );
-- Character RAM
----------------------------------------------------------
u_CHRAM : entity work.chram
port map (
CLK => CLK,
CHRAM_A => CPU_A(9 downto 0),
CHRAM_WR => CHRAM_WR,
CHRAM_DI => CDI & CPU_DO,
CHRAM_DO => CHRAM_DO,
CHRAM_VA => CHRAM_VA,
CHRAM_VD => CHRAM_VD );
-- VGA Video Controller
----------------------------------------------------------
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => RESET,
CACHE_SWAP => CACHE_SWAP,
CACHE_A => CACHE_AO,
CACHE_D => CACHE_DO,
CURRENT_LINE => SCANLINE,
LUT_A => LUT_A,
LUT_D => LUT_D,
VBLANK => VBLANK,
R => VGA_R,
G => VGA_G,
B => VGA_B,
HSYNC => VGA_HSYNC,
VSYNC => VGA_VSYNC );
-- Keyboard Controller
----------------------------------------------------------
u_KEYBOARD : entity work.keyboard
port map(
clk => CLK,
reset => RESET,
o_reset => KB_SG_RESET,
PS2_Clk => PS2_CLK,
PS2_Data => PS2_DATA,
Key_Addr => CPU_A(8 downto 0),
Key_Data => KEYBOARD_DO );
-- Font ROM
----------------------------------------------------------
u_FONTROM : ENTITY work.fontrom
PORT MAP(
ADDRA => FONTROM_A,
CLKA => CLK,
DOUTA => FONTROM_DO);
-- Video Scanline Cache
----------------------------------------------------------
u_CACHE : entity work.cache
port map (
CLK => CLK,
AI => CACHE_AI,
DI => CACHE_DI,
WE => CACHE_WE,
AO => CACHE_AO,
DO => CACHE_DO,
CACHE => CACHE_SWAP );
-- i8255 - PPI1 Controller
----------------------------------------------------------
u_PPI1 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI1_DO,
WR => PPI1_WR,
PAI => PPI1_PAI,
PAO => PPI1_PAO,
PBI => PPI1_PBI,
PBO => PPI1_PBO,
PCI => PPI1_PCI,
PCO => PPI1_PCO );
PPI1_PAI <= "1111" & CDI & '0' & VBLANK & not TAPE_IN;
PPI1_PBI <= "00000000";
PPI1_PCI <= "00000000";
-- i8255 - PPI2 Controller
----------------------------------------------------------
u_PPI2 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI2_DO,
WR => PPI2_WR,
PAI => PPI2_PAI,
PAO => PPI2_PAO,
PBI => PPI2_PBI,
PBO => PPI2_PBO,
PCI => PPI2_PCI,
PCO => PPI2_PCO );
PPI2_PAI <= "00000000";
PPI2_PBI <= "00000000";
PPI2_PCI <= "00000000";
-- i8255 - PPI3 Controller
----------------------------------------------------------
u_PPI3 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI3_DO,
WR => PPI3_WR,
PAI => PPI3_PAI,
PAO => PPI3_PAO,
PBI => PPI3_PBI,
PBO => PPI3_PBO,
PCI => PPI3_PCI,
PCO => PPI3_PCO );
PPI3_PAI <= "00000000";
PPI3_PBI <= "00000000";
PPI3_PCI <= "00000000";
-- i8259 - Programmable Interrupt Controller
----------------------------------------------------------
u_PIC : entity work.i8259
port map(
CLK => CLK,
RESET => CPU_RESET,
A0 => CPU_A(0),
WR => PIC_WR,
INTA => CPU_INTA,
INTR => CPU_INTR,
IRQ => "000" & (VBLANK and not PAUSE_ONESHOT) & "0000",
DI => CPU_DO,
DO => PIC_DO );
-- i8253 - Timer
----------------------------------------------------------
u_TIMER : k580wi53
port map (
clk => CLK,
c0 => TIMER_C0, -- 2MHz Clock for Sound Generation
c1 => '0', -- for RS232
c2 => '0', -- HBL 65.6 µS Period for Interrupt
g0 => '1',
g1 => '1',
g2 => '1',
out0 => TIMER_OUT0,
out1 => OPEN,
out2 => OPEN,
addr => CPU_A(1 downto 0),
rd => TIMER_RD,
we_n => not TIMER_WR,
idata => CPU_DO,
odata => TIMER_DO );
u_SPI : entity work.spi_comm
port map(
CLK => CLK,
RESET => RESET,
SPI_CS_A => COMM_CSA,
SPI_CS_D => COMM_CSD,
SPI_SCK => COMM_SCK,
SPI_DI => COMM_MOSI,
SPI_DO => COMM_MISO,
ADDR_O => COMM_ADDR_O,
ADDR_I => COMM_ADDR_I,
ADDR_REQ => COMM_ADDR_REQ,
ADDR_ACK => COMM_ADDR_ACK,
DATA_O => COMM_DATA_O,
DATA_I => COMM_DATA_I,
DATA_REQ => COMM_DATA_REQ,
DATA_ACK => COMM_DATA_ACK );
u_ONESHOT_RESET : entity work.oneshot
port map(
CLK => CLK,
RESET => RESET,
ONESHOT_IN => CPU_PAUSE,
ONESHOT_OUT => PAUSE_ONESHOT );
-- Select active Floppy Drive
----------------------------------------------------------
floppy_drive : process(DRV_SEL)
begin
case DRV_SEL is
when X"0" => DRIVE <= "00";
when X"1" => DRIVE <= "00";
when X"2" => DRIVE <= "01";
when X"3" => DRIVE <= "01";
when X"4" => DRIVE <= "10";
when X"5" => DRIVE <= "01";
when X"6" => DRIVE <= "10";
when X"7" => DRIVE <= "01";
when X"8" => DRIVE <= "11";
when X"9" => DRIVE <= "00";
when X"A" => DRIVE <= "01";
when X"B" => DRIVE <= "00";
when X"C" => DRIVE <= "00";
when X"D" => DRIVE <= "01";
when X"E" => DRIVE <= "00";
when X"F" => DRIVE <= "01";
when others => DRIVE <= "00";
end case;
end process;
-- Generate Global Reset and CPU Reset & Clock
----------------------------------------------------------
design_reset : process(CLK)
begin
if rising_edge(CLK) then
if KB_SG_RESET = '1' then
TICK <= "0000";
CPU_RESET <= '1';
CPU_CLK <= '0';
else
CPU_CLK <= '0';
if CPU_PAUSE = '0' then
TICK <= TICK + 1;
if TICK = 12 then
TICK <= "0000";
CPU_RESET <= '0';
RESET <= '0';
CPU_CLK <= '1';
end if;
end if;
end if;
end if;
end process;
-- Generate 2MHz Clock for Timer 0
----------------------------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
TICK2_0 <= "00";
TICK2_1 <= "00000";
else
if TICK2_1 < 8 then
TIMER_C0 <= '0';
else
TIMER_C0 <= '1';
end if;
TICK2_1 <= TICK2_1 + 1;
if (TICK2_0 = "00" and TICK2_1 = 17) or TICK2_1 = 16 then
TICK2_0 <= TICK2_0 + 1;
TICK2_1 <= "00000";
end if;
end if;
end if;
end process;
-- Character Inversion Logic
----------------------------------------------------------
inversion_logic : process(CLK)
begin
if rising_edge(CLK) then
if INVON = '0' and INVOFF = '1' then
CDI <= '1';
elsif INVON = '1' and INVOFF = '0' then
CDI <= '0';
elsif INVON = '1' and INVOFF = '1' then
CDI <= CDO;
end if;
if INVON = '1' and INVOFF = '1' then
CDO <= CHRAM_DO(8);
end if;
end if;
end process;
-- CPU Write
----------------------------------------------------------
CHRAM_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_CGRAM else '0';
PPI1_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "111" else '0';
PPI2_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "110" else '0';
PPI3_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "001" else '0';
PIC_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "101" else '0';
TIMER_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" else '0';
-- ########################################### TEST #####################################################
-- TIMER_RD <= '1' when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" else '0';
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
TIMER_RD <= '0';
else
TIMER_RD <= '0';
if TICK = 3 and CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" then
TIMER_RD <= '1';
end if;
end if;
end if;
end process;
-- ########################################### END TEST ################################################
-- CPU Read
----------------------------------------------------------
CPU_DI <= PIC_DO when CPU_INTA = '1' or (CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "101")
-- else FLASH_D when CPU_RD = '1' and MAPPER_DO = M_ROM
-- else RAM_DO when CPU_RD = '1' and (MAPPER_DO = M_RAM or MAPPER_DO = M_REGBASE)
else ROM_DO when CPU_RD = '1' and MAPPER_DO = M_ROM
else RAM_DO when CPU_RD = '1' and (MAPPER_DO = M_RAM or MAPPER_DO = M_REGBASE)
else PPI3_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "001"
else PPI2_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "110"
else PPI1_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "111"
else TIMER_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000"
else FLOPPY_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "011"
else CHRAM_DO(7 downto 0) when CPU_RD = '1' and MAPPER_DO = M_CGRAM
else VRAM_DO when CPU_RD = '1' and MAPPER_DO = M_VRAM
else KEYBOARD_DO when CPU_RD = '1' and MAPPER_DO = M_KEYBOARD
else "11111111";
-- SRAM Arbiter / Controller
----------------------------------------------------------
SRAM_DO <= SRAM_D;
SRAM_D <= SRAM_DI;
process(CLK)
begin
if rising_edge(CLK) then
if CPU_RESET = '1' then
STATE <= ST_IDLE;
SRAM_A <= (others => '0');
SRAM_DI <= (others => 'Z');
SRAM_CS <= '1';
SRAM_OE <= '1';
SRAM_WE <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
CACHE_WE <= '0';
CACHE_CNT <= "111111";
SYSREG <= "00000";
COLORREG <= "00000000";
CACHE_RD <= '0';
CPU_PAUSE <= '0';
COMM_REQ <= '0';
FLOPPY_DO <= "00000000";
COMM_ADDR_ACK <= '0';
COMM_DATA_ACK <= '0';
else
COMM_ADDR_ACK <= '0';
COMM_DATA_ACK <= '0';
CACHE_WE <= '0';
if CACHE_SWAP = '1' then
CACHE_RD <= '1';
CACHE_CNT <= "000000";
end if;
case STATE is
when ST_IDLE =>
if TICK = 3 then
if CPU_RD = '1' then
case MAPPER_DO is
when M_RAM | M_REGBASE =>
SRAM_A <= "00" & CPU_A;
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_CS <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
STATE <= ST_RAMREAD;
when M_VRAM =>
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_VRAMREAD1;
when M_PORTBASE =>
if CPU_A(5 downto 3) = "011" then -- Read from Floppy
COMM_REQ <= '1';
COMM_ADDR_I <= '0' & FLOPPY_SIDE & DRIVE & "00" & CPU_A(1 downto 0);
COMM_DATA_I <= X"FF";
CPU_PAUSE <= '1';
STATE <= ST_FLOPPY1;
end if;
when others =>
STATE <= ST_IDLE;
end case;
elsif CPU_WR = '1' then
case MAPPER_DO is
when M_RAM | M_ROM | M_KEYBOARD =>
SRAM_A <= "00" & CPU_A;
SRAM_WE <= '0';
SRAM_OE <= '1';
SRAM_CS <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_DI <= "ZZZZZZZZ" & CPU_DO;
STATE <= ST_RAMWRITE1;
when M_VRAM =>
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_VRAMWRITE1;
when M_REGBASE =>
if CPU_A(7) = '0' then
SYSREG <= CPU_DO(6 downto 2);
elsif CPU_A(6) = '0' then
COLORREG <= CPU_DO;
elsif CPU_A(2) = '0' then
LUT(to_integer(unsigned(CPU_DO(3 downto 0)))) <= CPU_DO(7 downto 4);
end if;
when M_PORTBASE =>
if CPU_A(5 downto 3) = "011" then -- Write to Floppy
COMM_REQ <= '1';
COMM_ADDR_I <= '1' & FLOPPY_SIDE & DRIVE & "00" & CPU_A(1 downto 0);
COMM_DATA_I <= CPU_DO;
CPU_PAUSE <= '1';
STATE <= ST_FLOPPY1;
end if;
when others =>
STATE <= ST_IDLE;
end case;
else
if CACHE_RD = '1' then
CHRAM_VA <= SCANLINE(7 downto 4) & std_logic_vector(CACHE_CNT);
SRAM_A <= "00" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_CACHEREAD1;
NSTATE <= ST_IDLE;
end if;
end if;
end if;
when ST_FLOPPY1 =>
if COMM_ADDR_REQ = '1' then
COMM_REQ <= '0';
COMM_ADDR_ACK <= '1';
elsif COMM_DATA_REQ = '1' then
COMM_DATA_ACK <= '1';
FLOPPY_DO <= COMM_DATA_O;
CPU_PAUSE <= '0';
STATE <= ST_FLOPPY3;
elsif CACHE_RD = '1' then
CHRAM_VA <= SCANLINE(7 downto 4) & std_logic_vector(CACHE_CNT);
SRAM_A <= "00" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_CACHEREAD1;
NSTATE <= ST_FLOPPY1;
end if;
when ST_FLOPPY3 =>
if CPU_RD = '0' and CPU_WR = '0' then
STATE <= ST_IDLE;
end if;
when ST_RAMREAD =>
RAM_DO <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
STATE <= ST_IDLE;
when ST_RAMWRITE1 =>
SRAM_WE <= '1';
STATE <= ST_RAMWRITE2;
when ST_RAMWRITE2 =>
SRAM_DI <= (OTHERS => 'Z');
SRAM_CS <= '1';
SRAM_LB <= '1';
STATE <= ST_IDLE;
when ST_CACHEREAD1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
STATE <= ST_CACHEREAD2;
when ST_CACHEREAD2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
FONTROM_A <= CHRAM_VD(7 downto 0) & SCANLINE(3 downto 0);
-- FONTROM_A <= ALTFONT & CHRAM_VD(7 downto 0) & SCANLINE(3 downto 0);
STATE <= ST_CACHEREAD3;
when ST_CACHEREAD3 =>
STATE <= ST_CACHEREAD4;
when ST_CACHEREAD4 =>
CACHE_AI <= std_logic_vector(CACHE_CNT(5 downto 0));
if CHRAM_VD(8) = '0' then
CACHE_DI <= FONTROM_DO & PLANE2 & PLANE1 & PLANE0;
else
CACHE_DI <= (not FONTROM_DO) & PLANE2 & PLANE1 & PLANE0;
end if;
CACHE_WE <= '1';
if CACHE_CNT = "111111" then
CACHE_RD <= '0';
else
CACHE_CNT <= CACHE_CNT + 1;
end if;
STATE <= NSTATE;
when ST_VRAMREAD1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
STATE <= ST_VRAMREAD2;
when ST_VRAMREAD2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_WE <= '1';
STATE <= ST_VRAMREAD3;
when ST_VRAMREAD3 =>
if COLORREG(7) = '1' then -- color mode
if COLORREG(4) = '0' then
PLANE0 <= PLANE0 xor "11111111";
end if;
if COLORREG(5) = '0' then
PLANE1 <= PLANE1 xor "11111111";
end if;
if COLORREG(6) = '0' then
PLANE2 <= PLANE2 xor "11111111";
end if;
else -- plane mode
if COLORREG(4) = '1' then
VRAM_DO <= PLANE0;
else
VRAM_DO <= "00000000";
end if;
end if;
STATE <= ST_VRAMREAD4;
when ST_VRAMREAD4 =>
if COLORREG(7) = '1' then
VRAM_DO <= (PLANE0 and PLANE1 and PLANE2) xor "11111111";
else
if COLORREG(5) = '1' then
VRAM_DO <= PLANE1;
end if;
end if;
STATE <= ST_VRAMREAD5;
when ST_VRAMREAD5 =>
if COLORREG(7) = '0' then
if COLORREG(6) = '1' then
VRAM_DO <= PLANE2;
end if;
end if;
STATE <= ST_IDLE;
when ST_VRAMWRITE1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
STATE <= ST_VRAMWRITE2;
when ST_VRAMWRITE2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE3;
when ST_VRAMWRITE3 =>
if COLORREG(7) = '1' then -- color mode
if COLORREG(1) = '1' then
PLANE0 <= PLANE0 or CPU_DO;
else
PLANE0 <= PLANE0 and not CPU_DO;
end if;
if COLORREG(2) = '1' then
PLANE1 <= PLANE1 or CPU_DO;
else
PLANE1 <= PLANE1 and not CPU_DO;
end if;
if COLORREG(3) = '1' then
PLANE2 <= PLANE2 or CPU_DO;
else
PLANE2 <= PLANE2 and not CPU_DO;
end if;
else -- plane mode
if COLORREG(0) = '1' then -- write 1
if COLORREG(1) = '0' then
PLANE0 <= PLANE0 or CPU_DO;
end if;
if COLORREG(2) = '0' then
PLANE1 <= PLANE1 or CPU_DO;
end if;
if COLORREG(3) = '0' then
PLANE2 <= PLANE2 or CPU_DO;
end if;
else -- write 0
if COLORREG(1) = '0' then
PLANE0 <= PLANE0 and not CPU_DO;
end if;
if COLORREG(2) = '0' then
PLANE1 <= PLANE1 and not CPU_DO;
end if;
if COLORREG(3) = '0' then
PLANE2 <= PLANE2 and not CPU_DO;
end if;
end if;
end if;
STATE <= ST_VRAMWRITE4;
when ST_VRAMWRITE4 =>
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_WE <= '0';
SRAM_CS <= '0';
SRAM_DI <= PLANE0 & "ZZZZZZZZ";
STATE <= ST_VRAMWRITE5;
when ST_VRAMWRITE5 =>
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE6;
when ST_VRAMWRITE6 =>
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_WE <= '0';
SRAM_DI <= PLANE1 & PLANE2;
STATE <= ST_VRAMWRITE7;
when ST_VRAMWRITE7 =>
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE8;
when ST_VRAMWRITE8 =>
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CS <= '1';
SRAM_OE <= '1';
SRAM_DI <= "ZZZZZZZZZZZZZZZZ";
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
LUT_D <= LUT(to_integer(unsigned(LUT_A)));
SOUND <= TIMER_OUT0 and SOUND_EN;
SOUND_L <= SOUND;
SOUND_R <= SOUND;
-- SOUND_L <= "000" & SOUND & "00" & TAPE_OUT0 & TAPE_IN & "00000000" when SWITCH(8) = '1' else "00" & TAPE_OUT0 & "0000000000000";
-- SOUND_R <= "000" & SOUND & "00" & TAPE_OUT0 & TAPE_IN & "00000000" when SWITCH(8) = '1' else "00" & TAPE_OUT0 & "0000000000000";
end RTL;
| gpl-3.0 | 0d8d0d111cfdbc3ce0f5fd74f46e03c1 | 0.389661 | 3.973174 | false | false | false | false |
APastorG/APG | adder/adder_s.vhd | 1 | 4,670 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_s is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_sfixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_s1 of adder_s is
constant P : positive := input'length(1);
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high,
input(1)'low);
/*================================================================================================*/
/*================================================================================================*/
begin
adder_core_s_1:
entity work.adder_core_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; | mit | 2afa8bcff45eb83a62dba1db8bc1bbbd | 0.429896 | 4.730612 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_dadd_3_full_dsp_64.vhd | 6 | 10,830 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dadd_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dadd_3_full_dsp_64_arch OF sin_taylor_series_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dadd_3_full_dsp_64_arch;
| mit | a0423f24ef69818e570184dacf819ba5 | 0.632595 | 3.20509 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/zpu_wishbone_intercon.vhdl | 1 | 4,823 | ------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Wishbone bridge ----
---- ----
---- Description: ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Koen Martens, gmc sonologic.nl ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c)
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit:
---- File name:
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA:
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools:
---- Text editor:
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.wishbone.all;
entity zpu_wishbone_intercon_tb is
end entity zpu_wishbone_intercon_tb;
architecture Behave of zpu_wishbone_intercon_tb is
constant ADR_MSB : natural:=31;
constant ADR_LSB : natural:=0;
constant PAGE_BIT : natural:=4;
constant NUNITS : natural:=8;
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
-- testbench
signal break : std_logic:='0';
signal clk : std_logic;
-- wishbone
signal wb_rst : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_adr_i : std_logic_vector(ADR_MSB downto ADR_LSB);
signal wb_adr_o : std_logic_vector(PAGE_BIT-1 downto 0);
signal stb : std_logic_vector(NUNITS-1 downto 0);
begin
INTERCON : zpu_wishbone_intercon
generic map(
ADR_MSB => ADR_MSB,
ADR_LSB => ADR_LSB,
PAGE_BIT => PAGE_BIT,
NUNITS => NUNITS
)
port map(
rst_i => wb_rst,
stb_i => wb_stb,
cyc_i => wb_cyc,
adr_i => wb_adr_i,
adr_o => wb_adr_o,
stb_o => stb
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
-- print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_sim:
process
begin
wb_rst <= '0';
wb_stb <= '0';
wb_cyc <= '0';
wait for 1 us;
wb_adr_i <= std_logic_vector(to_unsigned(10, 32));
wb_stb <= '1';
wb_cyc <= '1';
wait for 1 us;
wb_stb <= '0';
wait for 1 us;
wb_cyc <= '0';
wait for 1 us;
wb_adr_i <= std_logic_vector(to_unsigned(54, 32));
wb_stb <= '1';
wb_cyc <= '1';
wait for 1 us;
wb_stb <= '0';
wait for 1 us;
wb_cyc <= '0';
wait for 1 us;
end process do_sim;
end architecture Behave; -- Entity: zpu_wishbone_bridge_tb
| bsd-3-clause | ef6808dbe641def95eeea3fb1c30b4cd | 0.300435 | 5.225352 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pia.vhdl | 1 | 12,551 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pia IS
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
CA1 : IN STD_LOGIC;
CB1 : IN STD_LOGIC;
CA2_DIR_OUT : OUT std_logic;
CA2_OUT : OUT std_logic;
CA2_IN : IN STD_LOGIC;
CB2_DIR_OUT : OUT std_logic;
CB2_OUT : OUT std_logic;
CB2_IN : IN STD_LOGIC;
-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
IRQA_N : OUT STD_LOGIC;
IRQB_N : OUT STD_LOGIC
);
END pia;
ARCHITECTURE vhdl OF pia IS
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
signal addr_decoded : std_logic_vector(3 downto 0);
signal porta_output_next : std_logic_vector(7 downto 0);
signal porta_output_reg : std_logic_vector(7 downto 0);
signal porta_input_reg : std_logic_vector(7 downto 0);
signal porta_input_next : std_logic_vector(7 downto 0);
signal porta_direction_next : std_logic_vector(7 downto 0);
signal porta_direction_reg : std_logic_vector(7 downto 0);
signal porta_control_next : std_logic_vector(5 downto 0);
signal porta_control_reg : std_logic_vector(5 downto 0);
signal portb_output_next : std_logic_vector(7 downto 0);
signal portb_output_reg : std_logic_vector(7 downto 0);
signal portb_input_reg : std_logic_vector(7 downto 0);
signal portb_input_next : std_logic_vector(7 downto 0);
signal portb_direction_next : std_logic_vector(7 downto 0);
signal portb_direction_reg : std_logic_vector(7 downto 0);
signal portb_control_next : std_logic_vector(5 downto 0);
signal portb_control_reg : std_logic_vector(5 downto 0);
signal irqa_next : std_logic_vector(1 downto 0);
signal irqa_reg : std_logic_vector(1 downto 0);
signal irqb_next : std_logic_vector(1 downto 0);
signal irqb_reg : std_logic_vector(1 downto 0);
signal CA1_reg : std_logic;
signal CA2_reg : std_logic;
signal CB1_reg : std_logic;
signal CB2_reg : std_logic;
signal CA2_output_next : std_logic;
signal CA2_output_reg : std_logic;
signal CB2_output_next : std_logic;
signal CB2_output_reg : std_logic;
signal read_ora : std_logic;
signal read_orb : std_logic;
signal write_ora : std_logic;
signal write_orb : std_logic;
signal ca1_edge_next : std_logic;
signal ca1_edge_reg : std_logic;
signal ca2_edge_next : std_logic;
signal ca2_edge_reg : std_logic;
signal cb1_edge_next : std_logic;
signal cb1_edge_reg : std_logic;
signal cb2_edge_next : std_logic;
signal cb2_edge_reg : std_logic;
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
porta_output_reg <= (others=>'0');
porta_input_reg <= (others=>'0');
porta_direction_reg <= (others=>'0'); -- default to input
porta_control_reg <= (others=>'0');
portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
portb_input_reg <= (others=>'0');
portb_direction_reg <= (others=>'1'); -- default to ouput
portb_control_reg <= (others=>'0');
irqa_reg <= (others=>'0');
irqb_reg <= (others=>'0');
CA1_reg <= '0';
CA2_reg <= '0';
CB1_reg <= '0';
CB2_reg <= '0';
CA2_output_reg <= '0';
CB2_output_reg <= '0';
ca1_edge_reg <= '0';
ca2_edge_reg <= '0';
cb1_edge_reg <= '0';
cb2_edge_reg <= '0';
elsif (clk'event and clk='1') then
porta_output_reg <= porta_output_next;
porta_input_reg <= porta_input_next;
porta_direction_reg <= porta_direction_next;
porta_control_reg <= porta_control_next;
portb_output_reg <= portb_output_next;
portb_input_reg <= PORTB_input_next;
portb_direction_reg <= portb_direction_next;
portb_control_reg <= portb_control_next;
irqa_reg <= irqa_next;
irqb_reg <= irqb_next;
CA1_reg <= CA1;
CA2_reg <= CA2_in;
CB1_reg <= CB1;
CB2_reg <= CB2_in;
CA2_output_reg <= CA2_output_next;
CB2_output_reg <= CB2_output_next;
ca1_edge_reg <= ca1_edge_next;
ca2_edge_reg <= ca2_edge_next;
cb1_edge_reg <= cb1_edge_next;
cb2_edge_reg <= cb2_edge_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>2)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- Writes to registers
process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
begin
porta_output_next <= porta_output_reg;
portb_output_next <= portb_output_reg;
porta_direction_next <= porta_direction_reg;
portb_direction_next <= portb_direction_reg;
porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
write_ora <= '0';
write_orb <= '0';
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
if (porta_control_reg(2) = '1') then
porta_output_next <= cpu_data_in;
write_ora <= '1';
else
porta_direction_next <= cpu_data_in;
end if;
end if;
if(addr_decoded(1) = '1') then
if (portb_control_reg(2) = '1') then
portb_output_next <= cpu_data_in;
write_orb <= '1';
else
portb_direction_next <= cpu_data_in;
end if;
end if;
if(addr_decoded(2) = '1') then
porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
end if;
if(addr_decoded(3) = '1') then
portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
end if;
end if;
end process;
-- Read from registers
process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
begin
data_out <= X"FF";
read_ora <= '0';
read_orb <= '0';
if (EN = '1') then -- since reads have an effect here...
if (addr_decoded(0) = '1') then
if (porta_control_reg(2) = '1') then
data_out <= porta_input_reg;
read_ora <= '1';
else
data_out <= porta_direction_reg; -- can this be read?
end if;
end if;
if (addr_decoded(1) = '1') then
if (portb_control_reg(2) = '1') then
data_out <= portb_input_reg;
read_orb <= '1';
else
data_out <= portb_direction_reg; -- can this be read?
end if;
end if;
if (addr_decoded(2) = '1') then
data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
end if;
if (addr_decoded(3) = '1') then
data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
end if;
end if;
end process;
-- irq handing
-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
begin
irqa_next(1) <= irqa_reg(1) and not(read_ora);
irqa_next(0) <= irqa_reg(0) and not(read_ora);
ca2_output_next <= ca2_output_reg;
if (CA1 = '1' and CA1_reg = '0') then
irqa_next(1) <= ca1_edge_reg;
end if;
if (CA1 = '0' and CA1_reg = '1') then
irqa_next(1) <= not(ca1_edge_reg);
end if;
if (CA2_in = '1' and CA2_reg = '0') then
irqa_next(0) <= ca2_edge_reg;
end if;
if (CA2_in = '0' and CA2_reg = '1') then
irqa_next(0) <= not(ca2_edge_reg);
end if;
ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
if (porta_control_next(5) = '0') then -- CA2 is an input
else -- CA2 is an output
--irqa_next(0) <= '0';
case porta_control_next(4 downto 3) is
when "10" =>
ca2_output_next <= '0'; -- direct control
when "11" =>
ca2_output_next <= '1'; -- direct control
when "01" =>
if (read_ora = '1') then
ca2_output_next <= '0';
else
-- clock restore
ca2_output_next <= '1';
end if;
when "00" =>
if (read_ora = '1') then
ca2_output_next <= '0';
elsif (irqa_reg(1) = '1') then
-- ca1 restore
ca2_output_next <= '1';
end if;
when others =>
-- nop
end case;
end if;
end process;
process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
begin
irqb_next(1) <= irqb_reg(1) and not(read_orb);
irqb_next(0) <= irqb_reg(0) and not(read_orb);
cb2_output_next <= cb2_output_reg;
if (CB1 = '1' and CB1_reg = '0') then
irqb_next(1) <= cb1_edge_reg;
end if;
if (CB1 = '0' and CB1_reg = '1') then
irqb_next(1) <= not(cb1_edge_reg);
end if;
if (CB2_in = '1' and CB2_reg = '0') then
irqb_next(0) <= cb2_edge_reg;
end if;
if (CB2_in = '0' and CB2_reg = '1') then
irqb_next(0) <= not(cb2_edge_reg);
end if;
cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
if (portb_control_next(5) = '0') then -- CB2 is an input
else -- CB2 is an output
--irqb_next(0) <= '0';
case portb_control_next(4 downto 3) is
when "10" =>
cb2_output_next <= '0'; -- direct control
when "11" =>
cb2_output_next <= '1'; -- direct control
when "01" =>
if (write_orb = '1') then
cb2_output_next <= '0';
else
-- clock restore
cb2_output_next <= '1';
end if;
when "00" =>
if (write_orb = '1') then
cb2_output_next <= '0';
elsif (irqb_reg(1) = '1') then
-- cb1 restore
cb2_output_next <= '1';
end if;
when others =>
--nop
end case;
end if;
end process;
-- output
-- TODO - review if ca2 and cb2 are push pull or pull up...
--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
ca2_out <= CA2_output_reg;
ca2_dir_out <= porta_control_reg(5);
cb2_out <= CB2_output_reg;
cb2_dir_out <= portb_control_reg(5);
porta_out <= porta_output_reg;
porta_dir_out <= porta_direction_reg;
porta_input_next <= porta_in;
--portb_out <= portb_output_reg;
-- forced to 1 when in input mode - star raiders relies on this
portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';
portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';
portb_dir_out <= portb_direction_reg;
portb_input_next <= portb_in;
irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
end vhdl;
| gpl-3.0 | 07e3fd6c57c5aa987671f34c356a65a4 | 0.615967 | 2.709044 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/sram_statemachine.vhd | 1 | 6,568 | ---------------------------------------------------------------------------
-- SRAM memory controller
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sram_statemachine IS
PORT (
CLK : in std_logic;
RESET_N : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
ADDRESS_IN : in std_logic_vector(22 downto 0);
WRITE_EN : in std_logic;
REQUEST : in std_logic;
BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
COMPLETE : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE0_N : out std_logic;
SRAM_CE1_N : out std_logic );
END sram_statemachine;
ARCHITECTURE vhdl OF sram_statemachine IS
function REPEAT(N: natural; B: std_logic)
return std_logic_vector
is
variable RESULT: std_logic_vector(1 to N);
begin
for i in 1 to N loop
RESULT(i) := B;
end loop;
return RESULT;
end;
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal DATA_OUT_REG : std_logic_vector(31 downto 0);
signal MASK : std_logic_vector(3 downto 0);
signal ADDRESS_IN_NEXT : std_logic_vector(18 downto 0);
type STATES is (ST_IDLE, ST_READ0, ST_READ1, ST_READ2, ST_WRITE0, ST_WRITE1, ST_WRITE2);
signal STATE : STATES;
BEGIN
SRAM_DQ <= SRAM_DI;
SRAM_DO <= SRAM_DQ;
DATA_OUT <= DATA_OUT_REG;
ADDRESS_IN_NEXT <= std_logic_vector(unsigned(ADDRESS_IN(19 downto 1)) + 1);
COMPLETE <= '1' when STATE = ST_IDLE and REQUEST = '0' else '0';
process(CLK, RESET_N)
begin
if RESET_N = '0' then
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_CE0_N <= '1';
SRAM_CE1_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
STATE <= ST_IDLE;
else
if rising_edge(CLK) then
case STATE is
when ST_IDLE =>
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
if REQUEST = '1' then
MASK(0) <= (BYTE_ACCESS or WORD_ACCESS) and ADDRESS_IN(0); -- masked on misaligned byte or word
MASK(1) <= (BYTE_ACCESS) and not(address_in(0)); -- masked on aligned byte only
MASK(2) <= BYTE_ACCESS or (WORD_ACCESS and not(ADDRESS_IN(0))); -- masked on aligned word or byte
MASK(3) <= not(LONGWORD_ACCESS); -- masked for everything except long word access
SRAM_ADDR <= ADDRESS_IN(18 downto 1);
SRAM_CE0_N <= ADDRESS_IN(19);
SRAM_CE1_N <= not ADDRESS_IN(19);
if WRITE_EN = '1' then
STATE <= ST_WRITE0;
else
STATE <= ST_READ0;
end if;
end if;
when ST_WRITE0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_DI(7 downto 0) <= DATA_IN(7 downto 0);
SRAM_DI(15 downto 8) <= (DATA_IN(15 downto 8) and not(repeat(8,MASK(0)))) or (DATA_IN(7 downto 0) and repeat(8,MASK(0)));
SRAM_WE_N <= '0';
STATE <= ST_WRITE1;
when ST_WRITE1 =>
SRAM_WE_N <= '1';
STATE <= ST_WRITE2;
when ST_WRITE2 =>
SRAM_ADDR <= ADDRESS_IN_NEXT(17 downto 0);
SRAM_CE0_N <= ADDRESS_IN_NEXT(18);
SRAM_CE1_N <= not ADDRESS_IN_NEXT(18);
SRAM_DI(7 downto 0) <= (DATA_IN(23 downto 16) and not(repeat(8,MASK(0)))) or (DATA_IN(15 downto 8) and repeat(8,MASK(0)));
SRAM_DI(15 downto 8) <= DATA_IN(31 downto 24);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
SRAM_WE_N <= '0';
STATE <= ST_IDLE;
when ST_READ0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_OE_N <= '0';
STATE <= ST_READ1;
when ST_READ1 =>
DATA_OUT_REG(7 downto 0) <= (SRAM_DO(7 downto 0) and not(repeat(8,MASK(0)))) or (SRAM_DO(15 downto 8) and repeat(8,MASK(0)));
DATA_OUT_REG(15 downto 8) <= SRAM_DO(15 downto 8);
SRAM_ADDR <= ADDRESS_IN_NEXT(17 downto 0);
SRAM_CE0_N <= ADDRESS_IN_NEXT(18);
SRAM_CE1_N <= not ADDRESS_IN_NEXT(18);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
STATE <= ST_READ2;
when ST_READ2 =>
DATA_OUT_REG(15 downto 8 ) <= (SRAM_DO(7 downto 0) and repeat(8,MASK(0))) or (DATA_OUT_REG(15 downto 8) and not(repeat(8,MASK(0))));
DATA_OUT_REG(31 downto 16) <= SRAM_DO(15 downto 0);
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
END vhdl;
| gpl-3.0 | 41b9b32848b2f0383061794b7c7b9919 | 0.441839 | 3.750999 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/HeaterClockGenerator.vhd | 1 | 2,786 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity HeaterClockGenerator is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
CLK2X_OUT : out std_logic);
end HeaterClockGenerator;
architecture BEHAVIORAL of HeaterClockGenerator is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
signal GND_BUS_7 : std_logic_vector (6 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
begin
GND_BIT <= '0';
GND_BUS_7(6 downto 0) <= "0000000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK2x_BUFG_INST : BUFG
port map (I=>CLK2X_BUF,
O=>CLK2X_OUT);
DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE,
SIM_DEVICE => "VIRTEX5")
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IN,
DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
DCLK=>GND_BIT,
DEN=>GND_BIT,
DI(15 downto 0)=>GND_BUS_16(15 downto 0),
DWE=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>CLK2X_BUF,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>open,
PSDONE=>open);
end BEHAVIORAL; | mit | 8eb1449b79f426c27fc431074c8b8beb | 0.489591 | 3.704787 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/wide_delay_line.vhdl | 1 | 1,670 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY wide_delay_line IS
generic(COUNT : natural := 1; WIDTH : natural :=1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
END wide_delay_line;
ARCHITECTURE vhdl OF wide_delay_line IS
type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal shift_reg : shift_reg_type;
signal shift_next : shift_reg_type;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>(others=>'0'));
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,sync_reset)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= data_in&shift_reg(COUNT-1 downto 1);
end if;
if (sync_reset = '1') then
shift_next <= (others=>(others=>'0'));
end if;
end process;
-- output
gen_output:
for index in 0 to WIDTH-1 generate
data_out(index) <= shift_reg(0)(index);
end generate;
END vhdl;
| gpl-3.0 | 3b2b40e44ee20bb28cbea4bf619a384d | 0.614371 | 3.180952 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/atari800core_helloworld.vhd | 1 | 4,027 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
LIBRARY work;
-- Simple version that:
-- i) needs: CLK(58 or 28MHZ) joystick,PS2 keyboard
-- ii) provides: VIDEO,AUDIO,ROM,RAM
-- example...
-- KEEP THIS FILE SIMPLE!
ENTITY atari800core_helloworld is
GENERIC
(
-- use CLK of 1.79*cycle_length
-- I've tested 16 and 32 only, but 4 and 8 might work...
cycle_length : integer := 16; -- or 32...
video_bits : integer := 8;
internal_rom : integer :=1;
internal_ram : integer := 16384 -- at start of memory map
);
PORT
(
CLK : IN STD_LOGIC; -- cycle_length*1.79MHz
RESET_N : IN STD_LOGIC;
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VIDEO_VS : OUT STD_LOGIC;
VIDEO_HS : OUT STD_LOGIC;
VIDEO_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
AUDIO_L : OUT std_logic_vector(15 downto 0);
AUDIO_R : OUT std_logic_vector(15 downto 0);
-- JOYSTICK
JOY1_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
JOY2_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
-- KEYBOARD
PS2_CLK : IN STD_LOGIC;
PS2_DAT : IN STD_LOGIC;
-- video standard
PAL : in STD_LOGIC
);
end atari800core_helloworld;
ARCHITECTURE vhdl OF atari800core_helloworld IS
-- pokey keyboard
SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
-- gtia consol keys
SIGNAL CONSOL_START : std_logic;
SIGNAL CONSOL_SELECT : std_logic;
SIGNAL CONSOL_OPTION : std_logic;
-- 6502 throttling
SIGNAL THROTTLE_COUNT_6502 : std_logic_vector(5 downto 0);
BEGIN
-- PS2 to pokey
keyboard_map1 : entity work.ps2_to_atari800
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
PS2_CLK => ps2_clk,
PS2_DAT => ps2_dat,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION
-- TODO - reset!
);
-- THROTTLE
THROTTLE_COUNT_6502 <= "000001";
atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
GENERIC MAP
(
cycle_length => cycle_length,
internal_rom => internal_rom,
internal_ram =>internal_ram,
video_bits => video_bits
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N,
VIDEO_VS => VIDEO_VS,
VIDEO_HS => VIDEO_HS,
VIDEO_B => VIDEO_B,
VIDEO_G => VIDEO_G,
VIDEO_R => VIDEO_R,
VIDEO_BLANK => open,
VIDEO_BURST => open,
VIDEO_START_OF_FIELD => open,
VIDEO_ODD_LINE => open,
AUDIO_L => AUDIO_L,
AUDIO_R => AUDIO_R,
JOY1_n => JOY1_n,
JOY2_n => JOY2_n,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
SIO_COMMAND => open,
SIO_RXD => '1',
SIO_TXD => open,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => open,
SDRAM_REQUEST_COMPLETE => '1',
SDRAM_READ_ENABLE => open,
SDRAM_WRITE_ENABLE => open,
SDRAM_ADDR => open,
SDRAM_DO => (others=>'1'),
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
DMA_32BIT_WRITE_ENABLE => '0',
DMA_16BIT_WRITE_ENABLE => '0',
DMA_8BIT_WRITE_ENABLE => '0',
DMA_ADDR => (others=>'1'),
DMA_WRITE_DATA => (others=>'1'),
MEMORY_READY_DMA => open,
RAM_SELECT => (others=>'0'),
ROM_SELECT => "000001",
PAL => PAL,
HALT => '0',
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
);
end vhdl;
| gpl-3.0 | 05a295d4dc6988834825fe5bee7b4dec | 0.630246 | 2.890883 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/phi_io.vhdl | 1 | 11,548 | ------------------------------------------------------------------------------
---- ----
---- ZPU Phi I/O ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the minimum I/O devices ----
---- assumed by the libc. They are a timer and an UART.@p ----
---- Important! this is currently a simulation only model, no UART ----
---- provided and it unconditionally generates a log. ----
---- Important! not all peripherals implemented! ----
---- Important! The enable signals assumes this is mapped @ 0x80A00xx. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUPhiIO(Behave) (Entity and architecture) ----
---- File name: phi_io.vhdl ----
---- Note: None ----
---- Limitations: Only for simulation. ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- std.textio ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library zpu;
use zpu.zpupkg.timer;
use zpu.zpupkg.gpio;
use zpu.UART.all;
use zpu.txt_util.all;
entity ZPUPhiIO is
generic(
BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
ENA_LOG : boolean:=true; -- Enable log
LOG_FILE : string:="log.txt"); -- Name for the log file
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
busy_o : out std_logic; -- I/O is busy
we_i : in std_logic; -- Write Enable
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_i : in unsigned(2 downto 0); -- Address bits 4-2
--
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
br_clk_i : in std_logic; -- UART base clock (enable)
--
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end entity ZPUPhiIO;
architecture Behave of ZPUPhiIO is
constant LOW_BITS : unsigned(1 downto 0):=(others=>'0');
constant TX_FULL : std_logic:='0';
constant RX_EMPTY : std_logic:='1';
-- "000" 0x00 is CPU enable ... useful?
constant IO_DATA : unsigned(2 downto 0):="001"; -- 0x04
constant IO_DIR : unsigned(2 downto 0):="010"; -- 0x08
constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C
constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10
constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14
constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18
-- "111" 0x1C Unused
-- Unimplemented: Interrupt control and timer (not counter ...?)
signal timer_read : unsigned(31 downto 0);
signal timer_we : std_logic;
signal is_timer : std_logic;
-- UART
-- Rx
signal rx_br : std_logic; -- Rx timing
signal uart_read : std_logic; -- ZPU read the value
signal rx_avail : std_logic; -- Rx data available
signal rx_data : std_logic_vector(7 downto 0); -- Rx data
-- Tx
signal tx_br : std_logic; -- Tx timing
signal uart_write : std_logic; -- ZPU is writing
signal tx_busy : std_logic; -- Tx can't get a new value
-- GPIO
signal gpio_we : std_logic;
signal is_gpio : std_logic;
signal gpio_read : unsigned(31 downto 0);
file l_file : text open write_mode is LOG_FILE;
begin
-----------
-- Timer --
-----------
timerinst: Timer
port map(
clk_i => clk_i, reset_i => reset_i, we_i => timer_we,
data_i => data_i, addr_i => addr_i(1 downto 1),
data_o => timer_read);
busy_o <= we_i or re_i;
is_timer <= '1' when to_01(addr_i)=CNT_1 or to_01(addr_i)=CNT_2 else '0'; -- 0x80A0014/8
timer_we <= we_i and is_timer;
----------
-- UART --
----------
-- Rx section
rx_core : RxUnit
port map(
clk_i => clk_i, reset_i => reset_i, enable_i => rx_br,
read_i => uart_read, rxd_i => rs232_rx_i, rxav_o => rx_avail,
datao_o => rx_data);
uart_read <= '1' when re_i='1' and addr_i=UART_RX else '0';
-- Tx section
tx_core : TxUnit
port map(
clk_i => clk_i, reset_i => reset_i, enable_i => tx_br,
load_i => uart_write, txd_o => rs232_tx_o, busy_o => tx_busy,
datai_i => std_logic_vector(data_i(7 downto 0)));
uart_write <= '1' when we_i='1' and addr_i=UART_TX else '0';
-- Rx timing
rx_timer : BRGen
generic map(COUNT => BRDIVISOR)
port map(
clk_i => clk_i, reset_i => reset_i, ce_i => br_clk_i, o_o => rx_br);
-- Tx timing
tx_timer : BRGen -- 4 Divider for Tx
generic map(COUNT => 4)
port map(
clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br);
----------
-- GPIO --
----------
gpio_i0: gpio
port map(
clk_i => clk_i, -- : in std_logic;
reset_i => reset_i, -- : in std_logic;
--
we_i => gpio_we, -- : in std_logic;
data_i => data_i, -- : in unsigned(31 downto 0);
addr_i => addr_i(1 downto 1), -- : in unsigned( 0 downto 0);
data_o => gpio_read, -- : out unsigned(31 downto 0);
--
port_in => gpio_in, -- : std_logic_vector(31 downto 0);
port_out => gpio_out, -- : std_logic_vector(31 downto 0);
port_dir => gpio_dir -- : std_logic_vector(31 downto 0);
);
is_gpio <= '1' when to_01(addr_i) = IO_DATA or to_01(addr_i) = IO_DIR else '0'; -- 0x80A0004/8
gpio_we <= we_i and is_gpio;
do_io:
process(clk_i)
--synopsys translate off
variable line_out : line := new string'("");
variable char : character;
--synopsys translate on
begin
if rising_edge(clk_i) then
if reset_i/='1' then
--synopsys translate off
if we_i='1' then
if addr_i=UART_TX and ENA_LOG then -- 0x80a000c
-- Write to UART
print("- Write to UART Tx: 0x" &hstr(data_i)&" ("&
character'val(to_integer(data_i) mod 256)&")");
char := character'val(to_integer(data_i));
if char = lf then
std.textio.writeline(l_file, line_out);
else
std.textio.write(line_out, char);
end if;
elsif is_gpio = '1' and ENA_LOG then
print("- Write GPIO: 0x" & hstr(data_i));
elsif is_timer='1' and ENA_LOG then
print("- Write to TIMER: 0x" & hstr(data_i));
else
--print(l_file,character'val(to_integer(data_i)));
report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"&
hstr(x"80a00"&"000"&addr_i&"00") severity warning;
end if;
end if;
--synopsys translate on
data_o <= (others => '0');
if re_i='1' then
if is_gpio = '1' then
if ENA_LOG then
print("- Read GPIO: 0x" & hstr(gpio_read));
end if;
data_o <= gpio_read;
elsif addr_i=UART_TX then
--if ENA_LOG then
--print("- Read UART Tx");
--end if;
data_o(8) <= not(tx_busy); -- output fifo not full
elsif addr_i=UART_RX then
if ENA_LOG then
print("- Read UART Rx");
end if;
data_o(8) <= rx_avail; -- receiver not empty
data_o(7 downto 0) <= unsigned(rx_data);
elsif is_timer='1' then
if ENA_LOG then
print("- Read TIMER: 0x" & hstr(timer_read));
end if;
data_o <= timer_read;
else
report "Illegal IO data_o @0x"&
hstr(x"80a00"&"000"&addr_i&"00") severity warning;
end if;
end if; -- re_i='1'
end if; -- reset_i/='1'
end if; -- rising_edge(clk_i)
end process do_io;
end Behave;
| bsd-3-clause | ecda99020da021920fed13613ea8c33e | 0.396605 | 4.146499 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator.vhd | 1 | 8,142 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in sulv_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out std_ulogic_vector; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator1 of average_calculator is
constant P : positive := input'length(1);
constant NORM_IN_HIGH : integer := input(1)'high-SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input(1)'low-SULV_NEW_ZERO;
/* constant CHECKS : integer := average_calculator_CHECKS();*/
constant INTER_HIGH : integer := average_calculator_IH(S,
P,
NORM_IN_HIGH);
constant INTER_LOW : integer := average_calculator_IL(ROUND_TO_BIT_opt,
NORM_IN_LOW);
constant NORM_OUT_HIGH : integer := average_calculator_OH(UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant NORM_OUT_LOW : integer := average_calculator_OL(UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant OUT_HIGH : integer := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : integer := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_s : u_sfixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_u : u_ufixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_selection:
if UNSIGNED_2COMP_opt generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_u(i) <= to_ufixed(input(i), aux_input_u(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= std_ulogic_vector(aux_output_u);
average_calculator_u1:
entity work.average_calculator_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_u,
valid_input => valid_input,
start => start,
output => aux_output_u,
valid_output => valid_output
);
end;
else generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_s(i) <= to_sfixed(input(i), aux_input_s(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= std_ulogic_vector(aux_output_s);
average_calculator_s1:
entity work.average_calculator_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_s,
valid_input => valid_input,
start => start,
output => aux_output_s,
valid_output => valid_output
);
end;
end generate;
end architecture; | mit | 4e04e90999ae1dc570427c324eb0ef1c | 0.428836 | 4.678592 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03900_good.vhd | 1 | 5,023 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization trough reset for Raz, enable and Count_Length
-------------------------------------------------------------------------------------------------
-- File name : STD_03900_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: State machine type definition: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03900_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end STD_03900_good;
--CODE
architecture Behavioral of STD_03900_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
sm_State <= init;
Raz <= '0';
Enable <= '0';
Count_Length <= (others=>'0');
elsif (rising_edge(i_Clock)) then
case sm_State is
when init =>
-- Set the length value
Length <= c_Length;
sm_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
-- The counter has not finished, wait
Enable <= i_Start xor not i_Stop;
sm_State <= Enabled;
else
-- The counter has finished, nothing else to do
Enable <= '0';
sm_State <= finished;
end if;
when others =>
sm_State <= init;
end case;
end if;
end process;
end Behavioral;
--CODE | gpl-3.0 | 931df03de7baca59db9133e983d5ab36 | 0.476807 | 4.716432 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/lvov_with_cache.vhd | 1 | 14,039 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lvov is
Port (
CLK50 : IN STD_LOGIC;
RESET_BTN : IN STD_LOGIC;
PS2_CLK : in STD_LOGIC;
PS2_DATA : in STD_LOGIC;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CS : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
LED : OUT std_logic;
TAPE_IN : IN std_logic;
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC );
end lvov;
architecture Behavioral of lvov is
-- Verilog Modules
----------------------------------------------------------
component k580wm80a is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
intr : in std_logic;
idata : in std_logic_vector(7 downto 0);
addr : out std_logic_vector(15 downto 0);
sync : out std_logic;
rd : out std_logic;
wr_n : out std_logic;
inta_n : out std_logic;
odata : out std_logic_vector(7 downto 0);
inte_o : out std_logic );
end component;
----------------------------------------------------------
signal CLK : std_logic;
signal RESET : std_logic := '0';
signal TICK : std_logic_vector(3 downto 0) := "0000";
signal SRAM_DI : std_logic_vector(7 downto 0);
signal SRAM_DO : std_logic_vector(7 downto 0);
signal VRAM_CS : std_logic;
signal CACHE_SWAP : std_logic;
signal CACHE_WE : std_logic;
signal CACHE_A : std_logic_vector(5 downto 0);
signal CACHE_DI : std_logic_vector(7 downto 0);
signal CACHE_VA : std_logic_vector(5 downto 0);
signal CACHE_VD : std_logic_vector(7 downto 0);
signal SCANLINE : std_logic_vector(7 downto 0);
signal CACHE_RD : std_logic;
signal CACHE_CNT : std_logic_vector (5 downto 0);
signal KEYB_A : std_logic_vector(7 downto 0);
signal KEYB_D : std_logic_vector(7 downto 0);
signal KEYB_A2 : std_logic_vector(3 downto 0);
signal KEYB_D2 : std_logic_vector(3 downto 0);
signal COLORS : std_logic_vector(6 downto 0);
signal ROM_D : std_logic_vector(7 downto 0);
signal ROM_INIT : std_logic;
signal CPU_CLK : std_logic;
signal CPU_SYNC : std_logic;
signal CPU_RD : std_logic;
signal CPU_WR_N : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal IO_RD : std_logic;
signal IO_WR : std_logic;
signal MEM_RD : std_logic;
signal MEM_WR : std_logic;
signal XSD_EN : std_logic;
signal XSDROM_D : std_logic_vector(7 downto 0);
signal SD_CLK_R : std_logic;
signal SD_DATA : std_logic_vector(6 downto 0);
signal SD_O : std_logic_vector(7 downto 0);
-- FSM States
type STATE_TYPE is ( IDLE, RAMREAD1,
RAMWRITE1, RAMWRITE2,
CACHE1, CACHE2, CACHE3, CACHE4 );
signal STATE : STATE_TYPE := IDLE;
begin
u_CLOCK : entity work.clock
port map(
CLK_IN => CLK50,
CLK_OUT => CLK );
u_ROM : entity work.rom
port map(
CLKA => CLK,
ADDRA => CPU_A(13 downto 0),
DOUTA => ROM_D );
u_XSDROM : entity work.xsd_rom
port map(
CLKA => CLK,
ADDRA => CPU_A(10 downto 0),
DOUTA => XSDROM_D );
u_CPU : k580wm80a
port map(
clk => CLK,
ce => CPU_CLK,
reset => not RESET,
intr => '0',
idata => CPU_DI,
addr => CPU_A,
sync => CPU_SYNC,
rd => CPU_RD,
wr_n => CPU_WR_N,
inta_n => OPEN,
odata => CPU_DO,
inte_o => OPEN );
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => '1',
CACHE_SWAP => CACHE_SWAP,
CACHE_A => CACHE_VA,
CACHE_D => CACHE_VD,
CURRENT_LINE=> SCANLINE,
COLORS => COLORS,
R => VGA_R,
G => VGA_G,
B => VGA_B,
HSYNC => VGA_HSYNC,
VSYNC => VGA_VSYNC );
u_CACHE : entity work.cache
port map(
CLK => CLK,
AI => CACHE_A,
DI => CACHE_DI,
WE => CACHE_WE,
AO => CACHE_VA,
DO => CACHE_VD,
CACHE => CACHE_SWAP );
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
KEYB_A => KEYB_A,
KEYB_D => KEYB_D,
KEYB_A2 => KEYB_A2,
KEYB_D2 => KEYB_D2 );
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_D <= "ZZZZZZZZ" & SRAM_DI;
SRAM_DO <= SRAM_D(7 downto 0);
--
----------------------------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
else
if CPU_SYNC = '1' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
if CPU_DO(4) = '1' then
IO_WR <= '0';
elsif CPU_DO(6) = '1' then
IO_RD <= '0';
elsif CPU_DO(7) = '1' then
MEM_RD <= '0';
elsif CPU_DO(7) = '0' then
MEM_WR <= '0';
end if;
end if;
end if;
end if;
end process;
-- LED <= TAPE_IN;
-- reset & first ROM access
CLOCK : process(CLK)
begin
if rising_edge(CLK) then
if RESET_BTN = '0' then
TICK <= (others => '0');
RESET <= '0';
ROM_INIT <= '1';
else
TICK <= TICK + 1;
CPU_CLK <= '0';
if TICK = "1111" then -- Generate 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
CPU_CLK <= '1';
TICK <= (others => '0');
RESET <= '1';
if IO_WR = '0' or IO_RD = '0' then
ROM_INIT <= '0';
end if;
end if;
end if;
end if;
end process;
FSM : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_DI <= (others => 'Z');
CACHE_RD <= '0';
CACHE_CNT <= "000000";
XSD_EN <= '0';
LED <= '1';
else
CACHE_WE <= '1';
if CACHE_SWAP = '1' then
CACHE_RD <= '1';
CACHE_CNT <= "000000";
end if;
case STATE is
when IDLE =>
if TICK = 1 then
if MEM_RD = '0' and CPU_RD = '1' then ------------------------------------------------------------------------- Read from Memory
if (CPU_A(15) = '1' and CPU_A(14) = '1') or ROM_INIT = '1' then -- Read from ROM
CPU_DI <= ROM_D;
elsif CPU_A(15 downto 11) = "00000" and XSD_EN = '1' then
CPU_DI <= XSDROM_D;
else -- Read from RAM
if CPU_A(15) = '0' and VRAM_CS = '0' then
SRAM_A <= "01" & CPU_A;
else
SRAM_A <= "00" & CPU_A;
end if;
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= RAMREAD1;
end if;
elsif MEM_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to Memory
if CPU_A(15) = '0' and VRAM_CS = '0' then
SRAM_A <= "01" & CPU_A;
else
SRAM_A <= "00" & CPU_A;
end if;
SRAM_WE <= '0';
SRAM_CS <= '0';
SRAM_DI <= CPU_DO;
STATE <= RAMWRITE1;
elsif IO_RD = '0' and CPU_RD = '1' then ---------------------------------------------------------------------- Read from I/O-Ports
CPU_DI <= (others => '1');
if CPU_A(7 downto 0) = X"F1" then
CPU_DI <= SD_O;
elsif CPU_A(4) ='0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
CPU_DI <= "111" & TAPE_IN & "1111";
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
CPU_DI <= KEYB_D;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
CPU_DI <= KEYB_D2 & KEYB_A2;
end if;
elsif IO_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to I/O-Ports
if CPU_A(7 downto 0) = X"FF" then
XSD_EN <= CPU_DO(1);
LED <= '0';
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
COLORS <= CPU_DO(6 downto 0);
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
VRAM_CS <= CPU_DO(1);
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "00" then
KEYB_A <= CPU_DO;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
KEYB_A2 <= CPU_DO(3 downto 0);
end if;
else
if CACHE_RD = '1' then
SRAM_A <= "0101" & SCANLINE & CACHE_CNT;
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= CACHE1;
end if;
end if;
end if;
when CACHE1 =>
CACHE_A <= CACHE_CNT;
CACHE_DI <= SRAM_DO;
SRAM_OE <= '1';
SRAM_CS <= '1';
CACHE_WE <= '0';
if CACHE_CNT = "111111" then
CACHE_RD <= '0';
else
CACHE_CNT <= CACHE_CNT + '1';
end if;
STATE <= IDLE;
when RAMREAD1 =>
SRAM_OE <= '1';
SRAM_CS <= '1';
CPU_DI <= SRAM_DO;
STATE <= IDLE;
when RAMWRITE1 =>
SRAM_WE <= '1';
SRAM_CS <= '1';
STATE <= RAMWRITE2;
when RAMWRITE2 =>
SRAM_DI <= (others => 'Z');
STATE <= IDLE;
when OTHERS =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
--//////////////////// SD CARD ////////////////////
--reg sdcs;
--reg sdclk;
--reg sdcmd;
--reg[6:0] sddata;
--wire[7:0] sd_o = {sddata, SD_DAT};
--
--assign SD_DAT3 = ~sdcs;
--assign SD_CMD = sdcmd;
--assign SD_CLK = sdclk;
--
--always @(posedge clk50 or posedge reset) begin
-- if (reset) begin
-- sdcs <= 1'b0;
-- sdclk <= 1'b0;
-- sdcmd <= 1'h1;
-- end else begin
-- if (addrbus[4:0]==5'h1A && ~port_wr_n) sdcs <= cpu_o[0];
-- if (addrbus[4:0]==5'h1B && ~port_wr_n) begin
-- if (sdclk) sddata <= {sddata[5:0],SD_DAT};
-- sdcmd <= cpu_o[7];
-- sdclk <= 1'b0;
-- end
-- if (cpu_rd) sdclk <= 1'b1;
-- end
--end
SD_O <= SD_DATA & SD_MISO;
SD_SCK <= SD_CLK_R;
process(CLK)
begin
if RESET = '0' then
SD_CS <= '1';
SD_MOSI <= '1';
SD_CLK_R <= '0';
elsif rising_edge(CLK) then
if IO_WR = '0' and CPU_A(7 downto 0) = X"F0" then
SD_CS <= not CPU_DO(0);
elsif IO_WR = '0' and CPU_A(7 downto 0) = X"F1" then
if SD_CLK_R = '1' then
SD_DATA <= SD_DATA(5 downto 0) & SD_MISO;
end if;
SD_MOSI <= CPU_DO(7);
SD_CLK_R <= '0';
end if;
if IO_RD = '0' or MEM_RD = '0' then
SD_CLK_R <= '1';
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | a1784b2123bbecd7fb55afdbbd9d40e8 | 0.378375 | 3.679948 | false | false | false | false |
APastorG/APG | counter/counter.vhd | 1 | 5,574 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a counter an its content. It exists to
/ circumvent the impossibility of reading the attributes of an unconstrained port signal inside the
/ port declaration of an entity. (e.g. to declare an output's size, which depends on an input's
/ size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.counter_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity counter is
generic(
UNSIGNED_2COMP_opt : boolean := true; --default
OVERFLOW_BEHAVIOR_opt : T_overflow_behavior := t_wrap; --default
COUNT_MODE_opt : T_count_mode := t_up; --default
COUNTER_WIDTH_dep : positive_exc := 0; --exception : value not set
TARGET_MODE : boolean; --compulsory
TARGET_dep : integer_exc := integer'low; --exception : value not set
TARGET_WITH_COUNT_opt : boolean_exc := t_exc; --default
TARGET_BLOCKING_opt : boolean_exc := t_exc; --default
USE_SET : boolean; --compulsory
SET_TO_dep : integer_exc := integer'low; --exception : value not set
USE_RESET : boolean; --compulsory
SET_RESET_PRIORITY_opt : T_set_reset_priority := t_reset; --default
USE_LOAD : boolean --compulsory
);
port(
clk : in std_ulogic;
enable : in std_ulogic;
set : in std_ulogic := 'U';
reset : in std_ulogic := 'U';
load : in std_ulogic := 'U';
count_mode_signal : in std_ulogic := 'U';
value_to_load : in std_ulogic_vector:= (counter_CIW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
USE_SET,
SET_TO_dep) downto 1
=> 'U');
count : out std_ulogic_vector;
count_is_target : out std_ulogic_vector
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture counter1 of counter is
constant CHECKS : integer := counter_CHECKS(UNSIGNED_2COMP_opt,
TARGET_MODE,
USE_SET,
USE_RESET,
USE_LOAD,
TARGET_BLOCKING_opt,
TARGET_dep,
SET_TO_dep,
COUNTER_WIDTH_dep);
begin
counter_core1:
entity work.counter_core
generic map(
UNSIGNED_2COMP_opt => UNSIGNED_2COMP_opt,
OVERFLOW_BEHAVIOR_opt => OVERFLOW_BEHAVIOR_opt,
COUNT_MODE_opt => COUNT_MODE_opt,
COUNTER_WIDTH_dep => COUNTER_WIDTH_dep,
TARGET_MODE => TARGET_MODE,
TARGET_dep => TARGET_dep,
TARGET_WITH_COUNT_opt => TARGET_WITH_COUNT_opt,
TARGET_BLOCKING_opt => TARGET_BLOCKING_opt,
USE_SET => USE_SET,
SET_TO_dep => SET_TO_dep,
USE_RESET => USE_RESET,
SET_RESET_PRIORITY_opt => SET_RESET_PRIORITY_opt,
USE_LOAD => USE_LOAD
)
port map(
clk => clk,
enable => enable,
count_mode_signal => count_mode_signal,
set => set,
reset => reset,
load => load,
value_to_load => value_to_load,
count => count,
count_is_target => count_is_target
);
end architecture; | mit | 61e12b3d9b4517df9d6b12eee7847be3 | 0.378881 | 5.045537 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/antic.vhdl | 1 | 63,633 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.ceil;
USE ieee.math_real.log2;
use IEEE.STD_LOGIC_MISC.all;
ENTITY antic IS
GENERIC
(
cycle_length : integer := 16 -- or 32...
);
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
MEMORY_READY_ANTIC : IN STD_LOGIC;
MEMORY_READY_CPU : IN STD_LOGIC;
MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ANTIC_ENABLE_179 : IN std_logic;
PAL : IN STD_LOGIC;
lightpen : in std_logic;
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
NMI_N_OUT : OUT std_logic;
ANTIC_READY : OUT std_logic; -- taken low by wsync writes
-- GTIA interface
AN : OUT STD_LOGIC_VECTOR(2 downto 0);
COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
COLOUR_CLOCK_OUT : out std_logic;
HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
-- DMA fetch
dma_fetch_out : out std_logic;
dma_address_out : out std_logic_vector(15 downto 0);
-- refresh
refresh_out : out std_logic; -- used by sdram
-- for debugging
dma_clock_out : out std_logic;
hcount_out : out std_logic_vector(7 downto 0);
vcount_out : out std_logic_vector(8 downto 0)
);
END antic;
ARCHITECTURE vhdl OF antic IS
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
COMPONENT antic_dma_clock IS
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
enable_dma : IN STD_LOGIC;
playfield_start : in std_logic;
playfield_end : in std_logic;
vblank : in std_logic;
slow_dma : in std_logic;
medium_dma : in std_logic;
fast_dma : in std_logic;
dma_clock_out_0 : out std_logic;
dma_clock_out_1 : out std_logic;
dma_clock_out_2 : out std_logic;
dma_clock_out_3 : out std_logic
);
END component;
component antic_counter IS
generic
(
STORE_WIDTH : natural := 1;
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
);
END component;
component simple_counter IS
generic
(
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component wide_delay_line IS
generic(COUNT : natural := 1; WIDTH : natural :=1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
END component;
component reg_file IS
generic
(
BYTES : natural := 1;
WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
signal addr_decoded : std_logic_vector(15 downto 0);
signal enable_dma : std_logic;
signal dma_clock_character_name : std_logic;
signal dma_clock_character_inc : std_logic;
signal dma_clock_bitmap_data : std_logic;
signal dma_clock_character_data : std_logic;
signal wsync_next : std_logic;
signal wsync_reg : std_logic;
signal wsync_reset : std_logic;
signal wsync_write : std_logic;
signal wsync_delayed_write : std_logic;
signal nmi_next : std_logic;
signal nmi_reg : std_logic;
signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
signal nmist_reg : std_logic_vector(7 downto 5);
signal nmist_reset : std_logic;
signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
signal nmien_raw_reg : std_logic_vector(7 downto 6);
signal nmien_delayed_reg : std_logic_vector(7 downto 6);
signal dli_nmi_next : std_logic;
signal vbi_nmi_next : std_logic;
signal dli_nmi_reg : std_logic;
signal vbi_nmi_reg : std_logic;
signal nmi_reset : std_logic;
--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
--signal nmi_pending_reg : std_logic;
signal playfield_dma_start : std_logic;
signal playfield_dma_end : std_logic;
signal playfield_display_active_next : std_logic;
signal playfield_display_active_reg : std_logic;
signal dmactl_raw_next : std_logic_vector(6 downto 0);
signal dmactl_raw_reg : std_logic_vector(6 downto 0);
signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
signal dmactl_delayed_enabled : std_logic;
signal chactl_next : std_logic_vector(2 downto 0);
signal chactl_reg : std_logic_vector(2 downto 0);
-- dma is only allowed during certain portions of the display
signal allow_real_dma_next : std_logic;
signal allow_real_dma_reg : std_logic;
-- dma fetch handling
-- dma is scheduled one cycle before it happens, so that registers can directly drive output
signal dma_fetch_next : std_logic;
signal dma_fetch_reg : std_logic;
signal dma_address_next : std_logic_vector(15 downto 0);
signal dma_address_reg : std_logic_vector(15 downto 0);
signal dma_cache_next : std_logic_vector(7 downto 0);
signal dma_cache_reg : std_logic_vector(7 downto 0);
signal dma_cache_ready_next : std_logic;
signal dma_cache_ready_reg : std_logic;
constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
signal dma_fetch_request : std_logic;
signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
signal character_next : std_logic_vector(7 downto 0);
signal character_reg : std_logic_vector(7 downto 0);
signal displayed_character_next : std_logic_vector(7 downto 0);
signal displayed_character_reg : std_logic_vector(7 downto 0);
-- instruction decode
signal instruction_next : std_logic_vector(7 downto 0);
signal instruction_reg : std_logic_vector(7 downto 0);
signal first_line_of_instruction_next : std_logic;
signal first_line_of_instruction_reg: std_logic;
signal last_line_of_instruction_live : std_logic;
signal last_line_of_instruction_next : std_logic;
signal last_line_of_instruction_reg: std_logic;
signal force_final_row : std_logic;
signal instruction_blank_reg : std_logic;
signal instruction_blank_next : std_logic;
--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
--signal dma_speed_next : dma_speed_type;
--signal dma_speed_reg : dma_speed_type;
constant no_dma : std_logic_vector(1 downto 0) := "00";
constant slow_dma : std_logic_vector(1 downto 0) := "01";
constant medium_dma : std_logic_vector(1 downto 0) := "10";
constant fast_dma : std_logic_vector(1 downto 0) := "11";
signal dma_speed_next : std_logic_vector(1 downto 0);
signal dma_speed_reg : std_logic_vector(1 downto 0);
signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
--signal instruction_type_next : instruction_type;
--signal instruction_type_reg : instruction_type;
constant mode_character : std_logic_vector(2 downto 0) := "000";
constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
constant mode_jvb : std_logic_vector(2 downto 0) := "010";
constant mode_jump : std_logic_vector(2 downto 0) := "011";
constant mode_blank : std_logic_vector(2 downto 0) := "100";
signal instruction_type_next : std_logic_vector(2 downto 0);
signal instruction_type_reg : std_logic_vector(2 downto 0);
signal two_part_instruction_next : std_logic;
signal two_part_instruction_reg : std_logic;
-- e.g. if instruction is 8 lines long then the final row is 7
signal instruction_final_row_next : std_logic_vector(3 downto 0);
signal instruction_final_row_reg : std_logic_vector(3 downto 0);
--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
--signal shift_rate_next : shift_rate_type;
--signal shift_rate_reg : shift_rate_type;
constant slow_shift : std_logic_vector(1 downto 0) := "00";
constant medium_shift : std_logic_vector(1 downto 0) := "01";
constant fast_shift : std_logic_vector(1 downto 0) := "10";
signal shift_rate_next : std_logic_vector(1 downto 0);
signal shift_rate_reg : std_logic_vector(1 downto 0);
signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
signal shift_twobit_reg : std_logic;
signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
signal twopixel_reg : std_logic;
signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
signal single_colour_character_reg : std_logic;
signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
signal multi_colour_character_reg : std_logic;
signal twoline_character_next : std_logic; -- for antic 5/7
signal twoline_character_reg : std_logic;
signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
signal map_background_reg : std_logic;
signal dli_enabled_next : std_logic;
signal dli_enabled_reg : std_logic;
signal descenders_next : std_logic; -- for mode 3
signal descenders_reg : std_logic;
-- Shift register used to output to AN2-AN0
-- Can either be loaded from memory or from the line buffer
signal display_shift_next : std_logic_vector(7 downto 0);
signal display_shift_reg : std_logic_vector(7 downto 0);
signal delay_display_shift_next : std_logic_vector(24 downto 0);
signal delay_display_shift_reg : std_logic_vector(24 downto 0);
signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
signal load_display_shift_from_memory : std_logic;
signal load_display_shift_from_line_buffer : std_logic;
signal enable_shift : std_logic;
signal shiftclock_next : std_logic_vector(3 downto 0);
signal shiftclock_reg : std_logic_vector(3 downto 0);
signal playfield_reset : std_logic;
signal playfield_load : std_logic;
-- position in frame
signal hcount_next : std_logic_vector(7 downto 0);
signal hcount_reg : std_logic_vector(7 downto 0);
signal vcount_next : std_logic_vector(8 downto 0);
signal vcount_reg : std_logic_vector(8 downto 0);
signal vblank_next : std_logic;
signal vblank_reg : std_logic;
signal vsync_next : std_logic;
signal vsync_reg : std_logic;
signal hblank_next : std_logic;
signal hblank_reg : std_logic;
signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
signal hcount_reset : std_logic;
signal vcount_reset : std_logic;
signal vcount_increment : std_logic;
-- scrolling
signal hscrol_reg : std_logic_vector(3 downto 0);
signal hscrol_next : std_logic_vector(3 downto 0);
signal vscrol_raw_reg : std_logic_vector(3 downto 0);
signal vscrol_raw_next : std_logic_vector(3 downto 0);
signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
signal vscrol_enabled_reg : std_logic;
signal vscrol_enabled_next : std_logic;
signal vscrol_last_enabled_reg : std_logic;
signal vscrol_last_enabled_next : std_logic;
signal update_row_count : std_logic;
signal hscrol_enabled_reg : std_logic;
signal hscrol_enabled_next : std_logic;
-- refresh
signal refresh_pending_next : std_logic;
signal refresh_pending_reg : std_logic;
signal refresh_fetch_next : std_logic;
signal refresh_fetch_reg : std_logic;
-- Counter signals
signal increment_display_list_address : std_logic;
signal load_display_list_address : std_logic;
signal display_list_address_next : std_logic_vector(15 downto 0);
signal display_list_address_reg : std_logic_vector(15 downto 0);
signal load_display_list_address_cpu : std_logic;
signal load_display_list_address_dma : std_logic;
signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
signal display_list_address_next_dma : std_logic_vector(15 downto 0);
signal increment_memory_scan_address : std_logic;
signal load_memory_scan_address : std_logic;
signal memory_scan_address_next : std_logic_vector(15 downto 0);
signal memory_scan_address_reg : std_logic_vector(15 downto 0);
signal increment_line_buffer_address : std_logic;
signal load_line_buffer_address : std_logic;
signal line_buffer_address_next : std_logic_vector(7 downto 0);
signal line_buffer_address_reg : std_logic_vector(7 downto 0);
signal increment_row_count : std_logic;
signal load_row_count : std_logic;
signal row_count_next : std_logic_vector(3 downto 0);
signal row_count_reg : std_logic_vector(3 downto 0);
signal increment_refresh_count : std_logic;
signal load_refresh_count : std_logic;
signal refresh_count_next : std_logic_vector(3 downto 0);
signal refresh_count_reg : std_logic_vector(3 downto 0);
signal pmbase_reg : std_logic_vector(7 downto 2);
signal pmbase_next : std_logic_vector(7 downto 2);
signal chbase_raw_reg : std_logic_vector(7 downto 1);
signal chbase_raw_next : std_logic_vector(7 downto 1);
signal chbase_delayed_reg : std_logic_vector(7 downto 1);
signal line_buffer_write : std_logic;
signal line_buffer_data_in : std_logic_vector(7 downto 0);
signal line_buffer_data_out : std_logic_vector(7 downto 0);
-- output registers
signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
signal an_prev_reg : std_logic_vector(2 downto 0); -- previous - for hscrol
signal an_next : std_logic_vector(2 downto 0);
signal an_reg : std_logic_vector(2 downto 0);
-- light pendin
signal penv_next : std_logic_vector(7 downto 0);
signal penv_reg : std_logic_vector(7 downto 0);
signal penh_next : std_logic_vector(7 downto 0);
signal penh_reg : std_logic_vector(7 downto 0);
-- high res modes
signal colour_clock_8x : std_logic;
signal colour_clock_4x : std_logic;
signal colour_clock_2x : std_logic;
signal colour_clock_1x : std_logic;
signal colour_clock_half_x : std_logic;
signal colour_clock_selected : std_logic;
signal colour_clock_selected_highres : std_logic;
constant cycle_length_bits: integer := integer(ceil(log2(real(cycle_length))));
signal colour_clock_count_next : std_logic_vector(cycle_length_bits-1 downto 0);
signal colour_clock_count_reg : std_logic_vector(cycle_length_bits-1 downto 0);
signal colour_clock_count_reg_topthree : std_logic_vector(2 downto 0);
signal memory_ready_both : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
nmi_reg <= '0';
wsync_reg <= '0';
vcount_reg <= (others=>'0');
--hcount_reg <= X"01";
hcount_reg <= X"00";
dmactl_raw_reg <= (others=>'0');
chactl_reg <= (others=>'0');
vblank_reg <= '0';
vsync_reg <= '0';
pmbase_reg <= (others=>'0');
allow_real_dma_reg <= '0';
display_shift_reg <= (others=>'0');
chbase_raw_reg <= (others=>'0');
instruction_reg <= (others=>'0');
first_line_of_instruction_reg <= '0';
last_line_of_instruction_reg <= '0';
dma_speed_reg <= no_dma;
instruction_type_reg <= mode_blank;
instruction_final_row_reg <= (others=>'0');
shift_rate_reg <= slow_shift;
shift_twobit_reg <= '0';
twopixel_reg <= '0';
single_colour_character_reg <= '0';
multi_colour_character_reg <= '0';
twoline_character_reg <= '0';
map_background_reg <= '0';
dli_enabled_reg <= '0';
two_part_instruction_reg <= '0';
descenders_reg <='0';
hscrol_reg <= (others=>'0');
vscrol_raw_reg <= (others=>'0');
vscrol_enabled_reg <= '0';
vscrol_last_enabled_reg <= '0';
hscrol_enabled_reg <= '0';
shiftclock_reg <= (others=>'0');
hblank_reg <= '0';
an_reg <= (others=>'0');
an_prev_reg <= (others=>'0');
dma_fetch_reg <= '0';
dma_address_reg <= (others=>'0');
dma_cache_reg <= (others=>'0');
dma_cache_ready_reg <= '0';
dma_fetch_destination_reg <= dma_fetch_null;
playfield_display_active_reg <= '0';
instruction_blank_reg <= '0';
display_list_address_low_temp_reg <= (others=>'0');
character_reg <= (others=>'0');
displayed_character_reg <= (others=>'0');
refresh_pending_reg <= '0';
refresh_fetch_reg <= '0';
--nmi_pending_reg <= '0';
dli_nmi_reg <= '0';
vbi_nmi_reg <= '0';
nmien_raw_reg <= (others=>'0');
delay_display_shift_reg <= (others=>'0');
nmi_shiftreg_reg <= (others=>'1');
penh_reg <= (others=>'0');
penv_reg <= (others=>'0');
colour_clock_count_reg <= (others=>'0');
elsif (clk'event and clk='1') then
nmi_reg <= nmi_next;
wsync_reg <= wsync_next;
vcount_reg <= vcount_next;
hcount_reg <= hcount_next;
nmist_reg <= nmist_next;
dmactl_raw_reg <= dmactl_raw_next;
chactl_reg <= chactl_next;
vblank_reg <= vblank_next;
vsync_reg <= vsync_next;
pmbase_reg <= pmbase_next;
allow_real_dma_reg <= allow_real_dma_next;
display_shift_reg <= display_shift_next;
chbase_raw_reg <= chbase_raw_next;
instruction_reg <= instruction_next;
first_line_of_instruction_reg <= first_line_of_instruction_next;
last_line_of_instruction_reg <= last_line_of_instruction_next;
dma_speed_reg <= dma_speed_next;
instruction_type_reg <= instruction_type_next;
instruction_final_row_reg <= instruction_final_row_next;
shift_rate_reg <= shift_rate_next;
shift_twobit_reg <= shift_twobit_next;
twopixel_reg <= twopixel_next;
single_colour_character_reg <= single_colour_character_next;
multi_colour_character_reg <= multi_colour_character_next;
twoline_character_reg <= twoline_character_next;
map_background_reg <= map_background_next;
dli_enabled_reg <= dli_enabled_next;
two_part_instruction_reg <= two_part_instruction_next;
descenders_reg <= descenders_next;
hscrol_reg <= hscrol_next;
vscrol_raw_reg <= vscrol_raw_next;
vscrol_enabled_reg <= vscrol_enabled_next;
vscrol_last_enabled_reg <= vscrol_last_enabled_next;
hscrol_enabled_reg <= hscrol_enabled_next;
shiftclock_reg <= shiftclock_next;
hblank_reg <= hblank_next;
an_reg <= an_next;
an_prev_reg <= an_prev_next;
dma_fetch_reg <= dma_fetch_next;
dma_address_reg <= dma_address_next;
dma_cache_reg <= dma_cache_next;
dma_cache_ready_reg <= dma_cache_ready_next;
dma_fetch_destination_reg <= dma_fetch_destination_next;
playfield_display_active_reg <= playfield_display_active_next;
instruction_blank_reg <= instruction_blank_next;
display_list_address_low_temp_reg <= display_list_address_low_temp_next;
character_reg <= character_next;
displayed_character_reg <= displayed_character_next;
refresh_pending_reg <= refresh_pending_next;
refresh_fetch_reg <= refresh_fetch_next;
dli_nmi_reg <= dli_nmi_next;
vbi_nmi_reg <= vbi_nmi_next;
nmien_raw_reg <= nmien_raw_next;
delay_display_shift_reg <= delay_display_shift_next;
nmi_shiftreg_reg <= nmi_shiftreg_next;
penh_reg <= penh_next;
penv_reg <= penv_next;
colour_clock_count_reg <= colour_clock_count_next;
end if;
end process;
-- Colour clock (3.57MHz for PAL)
-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
colour_clock_count_reg_topthree <= colour_clock_count_reg(cycle_length_bits-1 downto cycle_length_bits-3);
process(colour_clock_count_reg, colour_clock_count_reg_topthree, ANTIC_ENABLE_179)
begin
colour_clock_half_x <= '0';
colour_clock_1x<='0';
colour_clock_2x<='0';
colour_clock_4x<='0';
colour_clock_8x<='0';
colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
if (ANTIC_ENABLE_179 = '1') then -- resync...
colour_clock_count_next <= std_logic_vector(to_unsigned(1,cycle_length_bits));
end if;
colour_clock_8x <= '1';
if (or_reduce(colour_clock_count_reg( cycle_length_bits-4 downto 0)) = '0') then
case colour_clock_count_reg_topthree is
when "000" =>
colour_clock_half_x <= '1';
colour_clock_1x <= '1';
colour_clock_2x <= '1';
colour_clock_4x <= '1';
when "001" =>
colour_clock_4x <= '1';
when "010" =>
colour_clock_2x <= '1';
colour_clock_4x <= '1';
when "011" =>
colour_clock_4x <= '1';
when "100" =>
colour_clock_1x <= '1';
colour_clock_2x <= '1';
colour_clock_4x <= '1';
when "101" =>
colour_clock_4x <= '1';
when "110" =>
colour_clock_2x <= '1';
colour_clock_4x <= '1';
when "111" =>
colour_clock_4x <= '1';
when others =>
-- nop
end case;
end if;
end process;
process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
begin
enable_dma <= colour_clock_half_x;
colour_clock_selected <= colour_clock_1x;
colour_clock_selected_highres <= colour_clock_2x;
dmactl_delayed_enabled <= '0';
case dmactl_delayed_reg(6 downto 5) is
when "01" =>
dmactl_delayed_enabled <= '1';
when "10" =>
enable_dma <= colour_clock_1x;
colour_clock_selected <= colour_clock_2x;
colour_clock_selected_highres <= colour_clock_4x;
dmactl_delayed_enabled <= '1';
when "11" =>
enable_dma <= colour_clock_2x;
colour_clock_selected <= colour_clock_4x;
colour_clock_selected_highres <= colour_clock_8x;
dmactl_delayed_enabled <= '1';
when others =>
--nop
end case;
end process;
-- Counters (memory address for data, memory address for display list)
antic_counter_memory_scan : antic_counter
generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
antic_counter_display_list : antic_counter
generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
antic_counter_line_buffer : simple_counter
generic map (COUNT_WIDTH=>8)
port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
antic_counter_row_count : simple_counter
generic map (COUNT_WIDTH=>4)
port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
antic_counter_refresh_count : simple_counter
generic map (COUNT_WIDTH=>4)
port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
-- Count position on screen
-- horizontal
process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
begin
hcount_next <= hcount_reg;
if (colour_clock_1x = '1') then
hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
if (colour_clock_half_x = '1') then
hcount_next(0) <= '1';
end if;
end if;
if (hcount_reset = '1') then
hcount_next <= (others=>'0');
end if;
end process;
-- vertical
process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
begin
vcount_next <= vcount_reg;
if (colour_clock_1x = '1') then
if (vcount_increment = '1') then
vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
end if;
if (vcount_reset = '1') then
vcount_next <= (others=>'0');
end if;
end if;
end process;
-- Actions done based on vertical position
process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
begin
vblank_next <= vblank_reg;
vsync_next <= vsync_reg;
vcount_reset <= '0';
if (colour_clock_1x='1') then
case vcount_reg is
when '0'&X"08" =>
vblank_next <= '0';
when '0'&X"F8" =>
vblank_next <= '1';
--when '1'&X"05" => (changed for testing galaxian!)
-- vblank_next <= '1';
-- PAL
when '1'&X"16" =>
vsync_next <= pal;
when '1'&X"19" =>
vsync_next <= '0';
when '1'&X"38" =>
vcount_reset <= '1'; -- Blip at 9c..., then wrap
-- NTSC
when '0'&X"FA" =>
vsync_next <= not(pal);
when '0'&X"FD" =>
vsync_next <= '0';
when '1'&X"06" =>
vcount_reset <= not(pal); -- Blip at 9c..., then wrap
when others =>
-- nothing
end case;
end if;
end process;
-- Calculate playfield start/end
process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
begin
playfield_dma_start_cycle <= (others=>'1');
playfield_dma_end_cycle <= (others=>'1');
playfield_display_start_cycle <= (others=>'1');
playfield_display_end_cycle <= (others=>'1');
-- DMA clock start/end
-- wide=3, normal=2, narrow=1
-- Playfield start is at (in colour clocks):
-- 68 + hscrol&FE - width*16
-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong...
-- e.g. if its 64 then we may be able to do something like base&width&
-- Playfield end is at (in colour clocks):
-- 164 + hscrol&FE + width*16
-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
-- hscrol interfers with playfield dma width (for dma purposes only!)
if (hscrol_enabled_reg='1') then
case dmactl_delayed_reg(1 downto 0) is
when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20 (10 in machine cycles)
playfield_dma_end_cycle <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
when "01" => -- narrow - traated as normal due to hscrol
playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36 (18 in machine cycles)
playfield_dma_end_cycle <= X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
when others =>
-- nothing
end case;
else
case dmactl_delayed_reg(1 downto 0) is
when "11" => -- wide
playfield_dma_start_cycle <= X"11";
playfield_dma_end_cycle <= X"D0";
when "10" => -- normal
playfield_dma_start_cycle <= X"21";
playfield_dma_end_cycle <= X"C0";
when "01" => -- narrow
playfield_dma_start_cycle <= X"31";
playfield_dma_end_cycle <= X"B0";
when others =>
-- nothing
end case;
end if;
-- background colour outside this area...
-- TODO - review these locations - should be clear due to garbage!
case dmactl_delayed_reg(1 downto 0) is
when "11" => -- wide
playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
if (hscrol_reg > X"C") then
playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol
end if;
playfield_display_end_cycle <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
when "10" => -- normal
playfield_display_start_cycle <= X"2F";
playfield_display_end_cycle <= X"CF";
when "01" => -- narrow
playfield_display_start_cycle <= X"3F";
playfield_display_end_cycle <= X"BF";
when others =>
-- nothing
end case;
end process;
-- Actions done based on horizontal position - notably dma!
process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg,displayed_character_reg)
begin
allow_real_dma_next <= allow_real_dma_reg;
playfield_dma_start <= '0';
playfield_dma_end <= '0';
playfield_display_active_next <= playfield_display_active_reg;
dma_fetch_request <= '0';
dma_address_next <= dma_address_reg;
dma_fetch_destination_next <= dma_fetch_destination_reg;
first_line_of_instruction_next <= first_line_of_instruction_reg;
last_line_of_instruction_next <= last_line_of_instruction_reg;
load_display_shift_from_line_buffer <= '0';
increment_memory_scan_address <= '0';
line_buffer_address_next <= (others=>'0');
load_line_buffer_address <= '0';
increment_line_buffer_address <= '0';
playfield_load <= '0';
hblank_next <= hblank_reg;
hcount_reset <= '0';
vcount_increment <= '0';
character_next <= character_reg;
displayed_character_next <= displayed_character_reg;
dli_nmi_next <= dli_nmi_reg;
vbi_nmi_next <= vbi_nmi_reg;
wsync_reset <= '0';
load_refresh_count <= '0';
refresh_count_next <= (others=>'0');
update_row_count <= '0';
vscrol_last_enabled_next <= vscrol_last_enabled_reg;
if (colour_clock_1x = '1') then
-- Playfield start/end
if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
playfield_dma_start <= '1';
load_line_buffer_address <= '1';
end if;
if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
playfield_dma_end <= '1';
end if;
if (hcount_reg = playfield_display_start_cycle) then
playfield_display_active_next <= '1';
end if;
if (hcount_reg = playfield_display_end_cycle) then
playfield_display_active_next <= '0';
end if;
if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
dma_fetch_request <= '1';
end if;
if (twoline_character_reg='1') then
if (single_colour_character_reg='1') then
dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
else
dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
end if;
else
if (single_colour_character_reg='1') then
dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
else
dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
end if;
end if;
displayed_character_next <= character_reg;
-- TODO
-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.
dma_fetch_destination_next <= dma_fetch_shiftreg;
load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);
increment_line_buffer_address <= '1';
end if;
case hcount_reg is
when X"00" => -- missile DMA, if missile or player DMA enabled
dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
dma_fetch_destination_next <= dma_fetch_null;
if (dmactl_delayed_reg(4) = '1') then -- single line resolution
dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
else
dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
end if;
when X"02" => -- display list dma if enabled
first_line_of_instruction_next <= '0';
if (instruction_type_reg = mode_jvb) then
-- suppress when waiting for vblank
first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
else
if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
dma_fetch_request <= dmactl_delayed_enabled;
dma_address_next <= display_list_address_reg;
dma_fetch_destination_next <= dma_fetch_instruction;
first_line_of_instruction_next <= '1';
vscrol_last_enabled_next <= vscrol_enabled_reg;
end if;
end if;
when X"05" =>
update_row_count <= '1'; -- done after instruction fetch...
when X"04"|X"06"|X"08"|X"0A" => -- player DMA, if enabled
dma_fetch_request <= dmactl_delayed_reg(3);
dma_fetch_destination_next <= dma_fetch_null;
if (dmactl_delayed_reg(4) = '1') then -- single line resolution
dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
else
dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
end if;
when X"0C" => -- lms lower byte dma if display list dma enabled?;
dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
dma_address_next <= display_list_address_reg;
dma_fetch_destination_next <= dma_fetch_list_low;
when X"0E" => -- lms upper byte dma if display list dma enabled?
dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
dma_address_next <= display_list_address_reg;
dma_fetch_destination_next <= dma_fetch_list_high;
if (instruction_type_reg = mode_jvb) then
-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
first_line_of_instruction_next <= '0';
end if;
dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
if (vcount_reg = '0'&X"F8") then
vbi_nmi_next <= '1';
end if;
when X"12" =>
dli_nmi_next <= '0';
vbi_nmi_next <= '0';
when X"21" =>
hblank_next <= '0';
when X"24" =>
playfield_load <= '1'; -- start the shift register
when X"31" => -- start refresh
load_refresh_count <= '1';
refresh_count_next <= (others=>'0');
when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
wsync_reset <= '1';
when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
allow_real_dma_next <= '0';
load_refresh_count <= '1';
refresh_count_next <= "1001";
when X"D8" => -- vscrol value checked at cycle 108
last_line_of_instruction_next <= last_line_of_instruction_live;
when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
vcount_increment <= '1';
when X"DD" =>
hblank_next <= '1';
when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
hcount_reset <= '1';
allow_real_dma_next <= not(vblank_reg);
when others =>
-- nothing
end case;
-- Playfield DMA
if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
dma_address_next <= memory_scan_address_reg;
dma_fetch_destination_next <= dma_fetch_line_buffer;
increment_memory_scan_address <= first_line_of_instruction_reg;
end if;
if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
character_next <= line_buffer_data_out;
increment_line_buffer_address <= '1';
end if;
if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data
dma_fetch_request <= dmactl_delayed_enabled;
dma_address_next <= memory_scan_address_reg;
dma_fetch_destination_next <= dma_fetch_line_buffer;
increment_memory_scan_address <= '1';
end if;
if (vblank_reg = '1') then
dma_fetch_request <= '0';
end if;
if (refresh_fetch_next = '1') then
dma_address_next <= (others=>'0');
end if;
end if;
end process;
-- refresh handling
process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, allow_real_dma_next)
begin
increment_refresh_count <= '0';
refresh_pending_next <= refresh_pending_reg;
refresh_fetch_next <= refresh_fetch_reg;
if (colour_clock_1x = '1' and hcount_reg(0) = '0') then
refresh_fetch_next <= '0';
-- do pending refresh once we have a spare cycle
if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0')) then
refresh_fetch_next <= '1';
refresh_pending_next <= '0';
end if;
-- do scheduled refresh - if block, enable pending one
if (hcount_reg(2 downto 1) = "01" and unsigned(refresh_count_reg)<9) then
increment_refresh_count <= '1';
refresh_fetch_next <= not(dma_fetch_next);
refresh_pending_next <= dma_fetch_next;
end if;
end if;
end process;
process(refresh_fetch_next)
begin
end process;
-- nmi handling
-- edge senstive, single cycle is enough (unless cpu disabled or clashes)
-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist... which is the goal.
nmien_delay : wide_delay_line
generic map (COUNT=>cycle_length,WIDTH=>2)
port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
begin
nmist_next(5) <= '0';
nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
end process;
-- dma clock
process(dma_speed_reg) -- XXX TODO - remove this process!
begin
slow_dma_s <= '0';
medium_dma_s <= '0';
fast_dma_s <= '0';
case dma_speed_reg is
when no_dma =>
-- nothing
when slow_dma =>
slow_dma_s <= '1';
when medium_dma =>
medium_dma_s <= '1';
when fast_dma =>
fast_dma_s <= '1';
when others =>
-- nothing
end case;
end process;
antic_dma_clock1 : antic_dma_clock
port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
-- line buffer
reg_file1 : reg_file
generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
-- vertical scrolling
-- load row count from vscrol must be done at time of instruction load
-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
vscrol_delay : wide_delay_line
generic map (COUNT=>cycle_length,WIDTH=>4)
port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));
process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count, force_final_row)
begin
load_row_count <= '0';
row_count_next <= (others=>'0');
increment_row_count <= '0';
last_line_of_instruction_live <= '0';
if (update_row_count = '1') then
if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
row_count_next <= vscrol_delayed_reg;
end if;
if (first_line_of_instruction_reg = '1') then
load_row_count <= '1';
else
increment_row_count <= '1';
end if;
end if;
if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
last_line_of_instruction_live <= '1';
end if;
else -- normal
if (row_count_reg = instruction_final_row_reg) then
last_line_of_instruction_live <= '1';
end if;
end if;
if (vblank_reg = '1' or force_final_row = '1') then
last_line_of_instruction_live <= '1';
end if;
end process;
-- chbase 2 cycle delay
chbase_delay : wide_delay_line
generic map (COUNT=>cycle_length*2,WIDTH=>7)
port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
-- decode instruction
process(instruction_reg)
begin
dma_speed_next <= no_dma;
instruction_type_next <= mode_blank;
shift_rate_next <= slow_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
single_colour_character_next <= '0';
multi_colour_character_next <= '0';
twoline_character_next <= '0';
map_background_next <= '0';
instruction_final_row_next <= (others=>'0');
two_part_instruction_next <= instruction_reg(6);
instruction_blank_next <= '0';
vscrol_enabled_next <= instruction_reg(5);
hscrol_enabled_next <= instruction_reg(4);
dli_enabled_next <= instruction_reg(7);
descenders_next <= '0';
force_final_row <= '0';
case instruction_reg(3 downto 0) is
when X"0" =>
instruction_type_next <= mode_blank;
instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
two_part_instruction_next <= '0';
instruction_blank_next <= '1';
vscrol_enabled_next <= '0';
hscrol_enabled_next <= '0';
when X"1" =>
instruction_type_next <= mode_jump;
instruction_final_row_next <= (others=>'0');
instruction_blank_next <= '1';
vscrol_enabled_next <= '0';
hscrol_enabled_next <= '0';
two_part_instruction_next <= '1';
if (instruction_reg(6) = '1') then
instruction_type_next <= mode_jvb;
force_final_row <= '1';
end if;
when X"2" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"7";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '1';
when X"3" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"9";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '1';
descenders_next <= '1';
when X"4" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"7";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
multi_colour_character_next <= '1';
when X"5" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"F";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
twoline_character_next <= '1';
multi_colour_character_next <= '1';
when X"6" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"7";
dma_speed_next <= medium_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
single_colour_character_next <= '1';
when X"7" =>
instruction_type_next <= mode_character;
instruction_final_row_next <= X"F";
dma_speed_next <= medium_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
single_colour_character_next <= '1';
twoline_character_next <= '1';
when X"8" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"7";
dma_speed_next <= slow_dma;
shift_rate_next <= slow_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
map_background_next <= '1';
when X"9" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"3";
dma_speed_next <= slow_dma;
shift_rate_next <= medium_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
map_background_next <= '1';
when X"A" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"3";
dma_speed_next <= medium_dma;
shift_rate_next <= medium_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
map_background_next <= '1';
when X"B" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"1";
dma_speed_next <= medium_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
map_background_next <= '1';
when X"C" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"0";
dma_speed_next <= medium_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '0';
twopixel_next <= '0';
map_background_next <= '1';
when X"D" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"1";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
map_background_next <= '1';
when X"E" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"0";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '0';
map_background_next <= '1';
when X"F" =>
instruction_type_next <= mode_bitmap;
instruction_final_row_next <= X"0";
dma_speed_next <= fast_dma;
shift_rate_next <= fast_shift;
shift_twobit_next <= '1';
twopixel_next <= '1';
when others =>
-- nothing
end case;
end process;
-- dma fetching
-- dma fetch - cache response until needed
-- we allow two colour clocks for each fetch...
process(memory_data_in,memory_ready_both,hcount_reg,dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,dma_cache_ready_reg,dma_cache_reg,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
begin
instruction_next <= instruction_reg;
display_list_address_next_dma <= display_list_address_reg;
load_display_list_address_dma <= '0';
memory_scan_address_next <= memory_scan_address_reg;
load_memory_scan_address <= '0';
increment_display_list_address <= '0';
load_display_shift_from_memory <= '0';
display_list_address_low_temp_next <= display_list_address_low_temp_reg;
line_buffer_data_in <= (others=>'0');
line_buffer_write <= '0';
dma_cache_next <= dma_cache_reg;
dma_cache_ready_next <= dma_cache_ready_reg;
dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
if (dma_fetch_reg = '1' and memory_ready_both = '1') then
dma_cache_next <= memory_data_in;
dma_cache_ready_next <= '1';
dma_fetch_next <= '0';
end if;
if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
instruction_next <= (others=>'0');
end if;
if (dma_cache_ready_reg='1' and hcount_reg(0)='0') then
--if (dma_cache_ready_reg='1') then
case dma_fetch_destination_reg is
when dma_fetch_line_buffer =>
line_buffer_data_in <= dma_cache_reg;
line_buffer_write <= '1';
when dma_fetch_shiftreg =>
load_display_shift_from_memory <= '1';
when dma_fetch_null =>
-- nothing (C/G/MTIA listens to bus)
when dma_fetch_instruction =>
instruction_next <= dma_cache_reg;
increment_display_list_address <= '1';
when dma_fetch_list_low =>
if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
--display_list_address_next_dma(7 downto 0) <= dma_cache_reg; Changing this so soon messes up next dma cycle
display_list_address_low_temp_next <= dma_cache_reg;
increment_display_list_address <= '1';
else
increment_display_list_address <= '1';
memory_scan_address_next(7 downto 0) <= dma_cache_reg;
load_memory_scan_address <= '1';
end if;
when dma_fetch_list_high =>
if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
display_list_address_next_dma <= dma_cache_reg&display_list_address_low_temp_reg;
load_display_list_address_dma <= '1';
else
increment_display_list_address <= '1';
memory_scan_address_next(15 downto 8) <= dma_cache_reg;
load_memory_scan_address <= '1';
end if;
when others =>
-- nothing
end case;
dma_cache_ready_next <= '0';
end if;
end process;
-- shift reg clock
playfield_reset <= hblank_reg;
process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
begin
shiftclock_next <= shiftclock_reg;
enable_shift <= '0';
if (colour_clock_selected = '1') then
shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
if (playfield_load='1') then
shiftclock_next <= "1000";
end if;
if (playfield_reset='1') then
shiftclock_next <= "0000";
end if;
--shiftclock_next(0) <= shiftclock_reg(1);
--shiftclock_next(1) <= shiftclock_reg(2);
--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;
case shift_rate_reg is
when slow_shift =>
enable_shift <= shiftclock_reg(0);
when medium_shift =>
enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
when fast_shift =>
enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
when others =>
-- nothing
end case;
end if;
end process;
-- shift reg
process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, dma_cache_reg, line_buffer_data_out)
begin
display_shift_next <= display_shift_reg;
if (enable_shift = '1') then
if (shift_twobit_reg = '1') then
display_shift_next <= display_shift_reg(5 downto 0)&"00";
else
display_shift_next <= display_shift_reg(6 downto 0)&"0";
end if;
end if;
if (load_display_shift_from_memory = '1') then
display_shift_next(7 downto 0) <= dma_cache_reg;
end if;
if (load_display_shift_from_line_buffer = '1') then
display_shift_next(7 downto 0) <= line_buffer_data_out;
end if;
end process;
-- delay shift reg output for n cycles, so we can match AN with antic output
process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg, instruction_type_reg)
begin
delay_display_shift_next <= delay_display_shift_reg;
if (colour_clock_selected = '1') then
-- TODO - RAM accesses are now processed in the 2nd colour clock
-- This is too late for character modes, so delay needs adjusting...
if (instruction_type_reg=mode_character) then
delay_display_shift_next <= displayed_character_reg(7 downto 5)&"00"&delay_display_shift_reg(24 downto 22)&display_shift_reg(7 downto 6)&delay_display_shift_reg(19 downto 5);
else
delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
end if;
end if;
end process;
-- ANO-2
-- XXX - clean up!
-- first process - AN with no blanking
process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
begin
an_current <= (others=>'0');
data_live <= (others=>'0');
if (shift_twobit_reg = '1') then
an_current(0) <= delay_display_shift_reg(0);
an_current(1) <= delay_display_shift_reg(1);
an_current(2) <= '1';
if (instruction_type_reg = mode_character) then
data_live(0) <= delay_display_shift_reg(0);
data_live(1) <= delay_display_shift_reg(1);
if (descenders_reg = '1') then
if (delay_display_shift_reg(3 downto 2) = "11") then
if (unsigned(row_count_reg)<2) then
data_live(1 downto 0) <= "00";
end if;
else
if (unsigned(row_count_reg)>=8) then
data_live(1 downto 0) <= "00";
end if;
end if;
end if;
if (delay_display_shift_reg(4)='1') then -- inverse/hidden
if (chactl_reg(1)='1') then
an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
else
an_current(0) <= data_live(0) and not(chactl_reg(0));
an_current(1) <= data_live(1) and not(chactl_reg(0));
end if;
else
an_current(0) <= data_live(0);
an_current(1) <= data_live(1);
end if;
end if;
if (multi_colour_character_reg = '1') then
case delay_display_shift_reg(1 downto 0) is
when "00" =>
an_current <= "000";
when "01" =>
an_current <= "100";
when "10" =>
an_current <= "101";
when "11" =>
an_current <= "11"&delay_display_shift_reg(4);
when others =>
-- nop
end case;
end if;
if (map_background_reg='1') then
case delay_display_shift_reg(1 downto 0) is
when "00" =>
an_current <= "000";
when "01" =>
an_current <= "100";
when "10" =>
an_current <= "101";
when "11" =>
an_current <= "110";
when others =>
-- nop
end case;
end if;
else
if (single_colour_character_reg = '1') then
-- i.e. antic 6,7
if (delay_display_shift_reg(1) = '1') then
an_current(0) <= delay_display_shift_reg(3);
an_current(1) <= delay_display_shift_reg(4);
an_current(2) <= '1';
else
an_current(0) <= '0';
an_current(1) <= '0';
an_current(2) <= '0';
end if;
end if;
if (map_background_reg='1') then
if (delay_display_shift_reg(1)='1') then
an_current <= "100";
else
an_current <= "000";
end if;
end if;
end if;
end process;
process(colour_clock_selected, an_current, an_prev_reg)
begin
an_prev_next <= an_prev_reg;
if (colour_clock_selected = '1') then
an_prev_next <= an_current;
end if;
end process;
process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
begin
an_next <= an_reg;
if (colour_clock_selected = '1') then
an_next <= an_current;
if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
an_next <= an_prev_reg;
end if;
if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
an_next <= "000";
end if;
if (vblank_reg = '1' or hblank_reg = '1') then
an_next(0) <= vsync_reg or twopixel_reg;
an_next(1) <= not(vsync_reg);
an_next(2) <= not(hblank_reg) and twopixel_reg;
--an_next <=
--(twopixel_reg and not(vsync_reg or hblank_reg))
--&((hblank_reg or vblank_reg) and not(vsync_reg))
--&(vsync_reg or twopixel_reg);
end if;
-- TODO this is too simplistic:
-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
-- + odd behaviour seen during high res bug
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- wsync write takes 1 cycle to assert rdy
-- TODO - revisit antic delays in terms of cpu cycles
wsync_delay : delay_line
generic map (COUNT=>cycle_length+cycle_length/2)
--generic map (COUNT=>cycle_length+cycle_length-2) -- TODO
port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
--dmactl_delay : wide_delay_line
-- generic map (COUNT=>cycle_length,WIDTH=>6)
-- port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
dmactl_delayed_reg <= dmactl_raw_next;
--dmactl_delayed_reg <= dmactl_raw_reg;
-- Writes to registers
process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
begin
nmien_raw_next <= nmien_raw_reg;
dmactl_raw_next <= dmactl_raw_reg;
chactl_next <= chactl_reg;
hscrol_next <= hscrol_reg;
vscrol_raw_next <= vscrol_raw_reg;
chbase_raw_next <= chbase_raw_reg;
pmbase_next <= pmbase_reg;
wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
nmist_reset <= '0';
wsync_write <= '0';
load_display_list_address_cpu <= '0';
display_list_address_next_cpu <= display_list_address_reg;
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
dmactl_raw_next <= cpu_data_in(6 downto 0);
end if;
if(addr_decoded(1) = '1') then
chactl_next <= cpu_data_in(2 downto 0);
end if;
if(addr_decoded(2) = '1') then
display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
load_display_list_address_cpu <= '1';
end if;
if(addr_decoded(3) = '1') then
display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
load_display_list_address_cpu <= '1';
end if;
if(addr_decoded(4) = '1') then
hscrol_next <= cpu_data_in(3 downto 0);
end if;
if(addr_decoded(5) = '1') then
vscrol_raw_next <= cpu_data_in(3 downto 0);
end if;
if(addr_decoded(7) = '1') then
pmbase_next <= cpu_data_in(7 downto 2);
end if;
if(addr_decoded(9) = '1') then
chbase_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(10) = '1') then
wsync_write <= '1';
end if;
if(addr_decoded(14) = '1') then
nmien_raw_next <= cpu_data_in(7 downto 6);
end if;
if(addr_decoded(15) = '1') then
nmist_reset <= '1';
end if;
end if;
end process;
-- Read from registers
process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
begin
data_out <= X"FF";
if (addr_decoded(8) = '1') then -- HCOUNT :-)
data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
end if;
if(addr_decoded(11) = '1') then --VCOUNT
data_out <= vcount_reg(8 downto 1);
end if;
if (addr_decoded(12) = '1') then -- PENH
data_out <= penh_reg;
end if;
if (addr_decoded(13) = '1') then -- PENV
data_out <= penv_reg;
end if;
if(addr_decoded(15) = '1') then --NMIST
data_out <= nmist_reg&"00000";
end if;
end process;
-- nmi delay
nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
-- light pen
process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
begin
penv_next <= penv_reg;
penh_next <= penh_reg;
if (lightpen = '0') then
penv_next <= vcount_reg(8 downto 1);
penh_next <= hcount_reg;
end if;
end process;
-- Use CPU data if virtual dma
MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
-- output
nmi_n_out <= nmi_shiftreg_reg(0);
dma_clock_out<=dma_clock_character_name;
AN <= an_reg;
antic_ready <= not(wsync_reg);
dma_fetch_out <= allow_real_dma_reg and dma_fetch_reg;
dma_address_out <= dma_address_reg;
refresh_out <= refresh_fetch_reg;
COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
COLOUR_CLOCK_OUT <= colour_clock_selected;
HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
vcount_out <= vcount_reg;
hcount_out <= hcount_reg;
END vhdl;
| gpl-3.0 | 5e1757aa8bf4aefdbe73415c64fcc1eb | 0.650512 | 2.90376 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult_pkg.vhd | 1 | 27,902 | /***************************************************************************************************
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains necessary types, constants, and functions for the parameterized
/ int_const_mult design.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package real_const_mult_pkg is
/* function used to check the consistency and correctness of generics 1 */
/**************************************************************************************************/
function real_const_mult_CHECKS(
data_high : integer;
data_low : integer;
unsigned_2comp_opt : boolean;
round_to_bit_opt : integer_exc;
max_error_pct : real_exc;
constants : real_v)
return integer;
/* functions for corrected generics and internal/external port signals 2 */
/**************************************************************************************************/
--returns a vector with the high index of each of the partial outputs
function calculate_high(
mult_fundamental : positive;
input_high : integer;
is_signed : boolean)
return integer;
--returns the output signals' low index, which is the lowest of the low indexes of the partial output signals
function real_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer;
--returns the output signals' high index, which is the highest of the high indexes of the partial output signals
function real_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer;
--applies the assigned parameters of round style, round to bit, and max error percentage to transform
--the constants to the correct fixed point form.
function fixed_from_real_constants(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return u_ufixed_v;
/* functions to obtain the integer factors from the real multiplicands 3 */
/**************************************************************************************************/
--returns true if all the values in the boolean vector are true
function all_positive(
vector : boolean_v)
return boolean;
--returns a boolean vector which indicates whether the constants are positive
function is_positive_vector_from_constants(
constants : real_v)
return boolean_v;
--calculates the needed shift to convert the fixed point constants to an odd natural number
function calculate_pre_vp_shift(
mult_fixed : u_ufixed_v)
return integer_v;
--calculates the positive odd numbers from the vector of fixed point ones
function calculate_mult_fundamental(
mult_fixed : u_ufixed_v;
pre_vp_shift : integer_v)
return positive_v;
/* function to generate file names 4 */
/**************************************************************************************************/
--generates a name from hashing the parameters of the module real_const_int to obtain different
--names for each instantiation
function generate_file_name(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : positive_v)
return string;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package body real_const_mult_pkg is
/********************************************************************************************** 1 */
function real_const_mult_CHECKS(
data_high : integer;
data_low : integer;
unsigned_2comp_opt : boolean;
round_to_bit_opt : integer_exc;
max_error_pct : real_exc;
constants : real_v)
return integer is
variable output_inter_w : positive;
variable output_w : positive;
begin
/*
--trying to multiply by 0
assert
report
" ILLEGAL PARAMETERS in entity const_multiplier: the absolute value of the " &
"constants must be greater than 1"
severity error;
--using unsigned but multiplicating by negative constant
assert not(constants<0 and unsigned_2comp_opt)
report
"ILLEGAL PARAMETERS in entity const_multiplier: the design is set to use unsigned" &
" format but the constants is negative. Whenever this happens the parameter "&
"unsigned_2comp_opt can only be false."
severity error;
output_inter_w := int_const_mult_OIW(data_width,
unsigned_2comp_opt,
constants);
output_w := int_const_mult_OW(data_width,
unsigned_2comp_opt,
output_width_opt,
constants);
--selected output width is not enough for the result
assert not(output_w < output_inter_w)
report
"ILLEGAL PARAMETERS in entity const_multiplier: The selected output width (" &
image(output_w) & ") is not enough to represent all possible " &
"results from the multiplication. At least " & image(output_inter_w) &
" bits are needed."
severity error;
*/
return 0;
end function;
/********************************************************************************************** 2 */
--used to calculate the output'high from each individual mult_fundamentals from the output'high
--of the previous fundamentals
function calculate_high(
mult_fundamental : positive;
input_high : integer;
is_signed : boolean)
return integer is
variable result : integer;
begin
if is_signed then
--(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below)
--example: -2(1,0)*-3(2,0)=6(3,0)
result := input_high + min_bits(mult_fundamental, is_signed) - 1;
--having one input(multiplicand) fixed and the other variable:
--when the multiplicand is 10...0 we have a special case in signed:
--the output will need 1 bit more than any other multiplicand which is representable in
-- the same (and not fewer) number of bits
--example: for an input of 3 bits:
--multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed
-- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12)
-- only needs 5 bits (01100)
if is_signed and ("mod"(log2(real(mult_fundamental)), 1.0) = 0.0) then
result := result + 1;
end if;
else
--(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below)
--example: 2(1,0)*3(1,0)=6(2,0)
result := input_high + min_bits(mult_fundamental, is_signed) - 1;
--having one input(multiplicand) fixed and the other variable:
--when the multiplicand is 11...1 we have a special case in unsigned:
--the output will need 1 bit less than any other multiplicand which is representable in
-- the same (and not fewer) number of bits
--example: for an input of 3 bits:
--multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned
-- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49)
-- needs 6 bits (110001)
if find_rightmost(unsigned(sulv_from_int(mult_fundamental)), '0') = integer'high + 1
then
result := result + 1;
end if;
end if;
return result;
end function;
function output_low(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer_v is
variable result : integer_v(constants'range);
variable u_sat : u_ufixed(75 downto -75);
variable s_sat : u_sfixed(75 downto -75);
begin
if round_to_bit_opt = integer'low then
for i in constants'range loop
u_sat := resize(to_ufixed(abs(constants(i)),
max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value
0.0,
max_error_pct_opt),
round_style => round_style_opt),
u_sat);
s_sat := resize(to_sfixed(constants(i),
max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value
0.0,
max_error_pct_opt),
round_style => round_style_opt),
s_sat);
if is_signed then
result(i) := sfixed_low(0, --irrelevant
input_low,
'*',
0, --irrelevant
maximum(find_rightmost(u_sat, '1'), -FRACTIONAL_LIMIT)
);
else
result(i) := ufixed_low(0, --irrelevant
input_low,
'*',
0, --irrelevant
maximum(find_rightmost(u_sat, '1'), FRACTIONAL_LIMIT)
);
end if;
end loop;
else
--result := (others => round_to_bit_opt);
for i in constants'range loop
u_sat := resize(to_ufixed(abs(constants(i)),
max_error_pct => 0.0,
round_style => round_style_opt),
u_sat);
u_sat := resize(to_ufixed(abs(constants(i)),
u_sat'high,
round_to_bit_opt,
round_style => round_style_opt),
u_sat);
s_sat := resize(to_sfixed(constants(i),
max_error_pct => 0.0,
round_style => round_style_opt),
s_sat);
s_sat := resize(to_sfixed(constants(i),
s_sat'high,
round_to_bit_opt,
round_style => round_style_opt),
s_sat);
if is_signed then
result(i) := sfixed_low(0, --irrelevant
input_low,
'*',
0, --irrelevant
find_rightmost(s_sat, '1')
);
else
result(i) := ufixed_low(0, --irrelevant
input_low,
'*',
0, --irrelevant
find_rightmost(u_sat, '1')
);
end if;
end loop;
end if;
return result;
end function;
function real_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer is
variable aux : integer_v(constants'range) := output_low(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_low,
is_signed);
variable result : integer := integer'high;
begin
for i in aux'range loop
if aux(i) < result then
result := aux(i);
end if;
end loop;
return result;
end function;
function output_high(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer_v is
variable result : integer_v(constants'range);
variable out_consants_low : integer_v(constants'range) := output_low(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_low,
is_signed);
variable u_sat : u_ufixed(75 downto -75);
variable s_sat : u_sfixed(75 downto -75);
begin
for i in constants'range loop
u_sat := resize(to_ufixed(abs(constants(i))), u_sat); --convert with ~0% error
s_sat := resize(to_sfixed(constants(i)), s_sat); --convert with ~0% error
if is_signed then
--(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below)
--example: -2(1,0)*-3(2,0)=6(3,0)
result(i) := input_high + find_leftmost(s_sat, ite(constants(i) < 0.0, '0', '1')) + 1;
--having one input(multiplicand) fixed and the other variable:
--when the multiplicand is 10...0 we have a special case in signed:
--the output will need 1 bit more than any other multiplicand which is representable in
-- the same (and not fewer) number of bits
--example: for an input of 3 bits:
--multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed
-- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12)
-- only needs 5 bits (01100)
if constants(i) < 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then
result(i) := result(i) + 1;
end if;
--when the multiplicand is the same special case as in unsigned:
--example: -2(1,0)*2(2,0)=-4(2,0)
if constants(i) > 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then
result(i) := result(i) - 1;
end if;
else
--(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below)
--example: 2(1,0)*3(1,0)=6(2,0)
result(i) := input_high + find_leftmost(u_sat, '1');
--having one input(multiplicand) fixed and the other variable:
--when the multiplicand is 11...1 we have a special case in unsigned:
--the output will need 1 bit less than any other multiplicand which is representable in
-- the same (and not fewer) number of bits
--example: for an input of 3 bits:
--multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned
-- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49)
-- needs 6 bits (110001)
if find_rightmost(resize(u_sat,
u_sat'high,
out_consants_low(i),
round_style => round_style_opt),
'0') = integer'high + 1
then
result(i) := result(i) + 1;
end if;
end if;
end loop;
return result;
end function;
function real_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer is
variable aux : integer_v(constants'range) := output_high(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_high,
input_low,
is_signed);
variable result : integer := integer'low;
begin
for i in aux'range loop
if aux(i) > result then
result := aux(i);
end if;
end loop;
return result;
end function;
function fixed_from_real_constants(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return u_ufixed_v is
constant max_error_pct : real := ite(max_error_pct_opt = real'low,
0.0,
max_error_pct_opt);
constant individual_highs : integer_v := output_high(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_high,
input_low,
is_signed);
constant individual_lows : integer_v := output_low(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_low,
is_signed);
constant result_high : integer := real_const_mult_OH(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_high,
input_low,
is_signed);
constant result_low : integer := real_const_mult_OL(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
input_low,
is_signed);
variable result : u_ufixed_v(1 to constants'length)(result_high downto result_low);
variable constant_high, constant_low : integer;
begin
for i in constants'range loop
--the transformation to the desired size range
constant_high := individual_highs(i) - input_high;
constant_low := individual_lows(i) - input_low;
--assert false
-- report "constant_high: " & image(constant_high)
-- severity warning;
--assert false
-- report "constant_low: " & image(constant_low)
-- severity warning;
result(i) := resize(to_ufixed(constants(i),
constant_high,
constant_low,
round_style => round_style_opt),
result_high,
result_low);
end loop;
return result;
end function;
/********************************************************************************************** 3 */
function all_positive(
vector : boolean_v)
return boolean is
begin
for i in vector'range loop
if not vector(i) then
return false;
end if;
end loop;
return true;
end function;
function is_positive_vector_from_constants(
constants : real_v)
return boolean_v is
variable result : boolean_v(constants'range);
begin
for i in constants'range loop
result(i) := constants(i) >= 0.0;
end loop;
return result;
end function;
function calculate_pre_vp_shift(
mult_fixed : u_ufixed_v)
return integer_v is
variable result : integer_v(mult_fixed'range);
begin
for i in mult_fixed'range loop
result(i) := -find_rightmost(mult_fixed(i), '1');
end loop;
return result;
end function;
function calculate_mult_fundamental(
mult_fixed : u_ufixed_v;
pre_vp_shift : integer_v)
return positive_v is
variable result : positive_v(1 to mult_fixed'length);
begin
for i in mult_fixed'range loop
result(i) := positive(to_real(scalb(mult_fixed(i), pre_vp_shift(i))));
end loop;
return result;
end function;
/********************************************************************************************** 4 */
--string used as this function should be static to work when called in synthesis and thus cannot
--contain line data types(which would more flexible as the size wouldn't need to be predefined)
function generate_file_name(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
constants : positive_v)
return string is
constant high : integer := 60;
constant low : integer := -10;
variable size_for_numeric_part, actual_numeric_part_size : positive;
variable accumulative : u_ufixed(high downto low) := to_ufixed(1, high, low);
variable aux : u_ufixed(high downto low) := to_ufixed(1, high, low);
variable result : string(1 to FILE_NAME_LENGTH);
variable temporal : positive;
variable counter : positive := 1;
begin
case round_style_opt is
when fixed_round => result(counter to counter+1) := "r_";
when fixed_truncate => result(counter to counter+1) := "t_";
end case;
counter := counter + 2;
if round_to_bit_opt = integer'low then
result(counter to counter+1) := "0_";
counter := counter + 2;
elsif round_to_bit_opt > 0 then
result(counter) := 'p'; --positive
counter := counter + 1;
temporal := integer(ceil(log10(real(round_to_bit_opt)+1)));
result(counter to counter+temporal-1) := image(round_to_bit_opt);
counter := counter + temporal;
result(counter) := '_'; --positive
counter := counter + 1;
else
result(counter) := 'n'; --negative
counter := counter + 1;
temporal := integer(ceil(log10(abs(real(round_to_bit_opt))+1)));
result(counter to counter+temporal-1) := image(abs(round_to_bit_opt));
counter := counter + temporal;
result(counter) := '_'; --positive
counter := counter + 1;
end if;
size_for_numeric_part := FILE_NAME_LENGTH - counter - 4; --the total length minus the already existing part minus 4 from ".txt"
for i in constants'range loop
if abs(constants(i))<1 then
accumulative := resize(accumulative * to_ufixed(1/abs(constants(i)), high, low),
accumulative);
else
accumulative := resize(accumulative * to_ufixed(abs(constants(i)), high, low),
accumulative);
end if;
end loop;
if max_error_pct_opt /= real'low then
accumulative := resize(accumulative + to_ufixed(1000*max_error_pct_opt, high, low),
accumulative);
end if;
accumulative := resize(accumulative*2**10, accumulative);
for i in 1 to size_for_numeric_part loop
aux := resize(aux * 10.0, aux);
end loop;
accumulative := modulo(accumulative, aux);
actual_numeric_part_size := integer(ceil(log10(to_real(accumulative)+1)));
if actual_numeric_part_size < size_for_numeric_part then
result(counter to counter + (size_for_numeric_part-actual_numeric_part_size) - 1) := (others => '0');
counter := counter + (size_for_numeric_part-actual_numeric_part_size);
end if;
result(counter to counter + actual_numeric_part_size - 1):= image(integer(to_real(accumulative)));
counter := counter + actual_numeric_part_size;
result(counter to counter + 3) := string'(".txt");
return result;
end function;
end package body;
| mit | 125904524c7ce24630fca733e8f0df81 | 0.458483 | 4.690793 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/reg_bank.vhd | 1 | 16,427 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--Uncomment following two lines for Xilinx RAM16X1D
library UNISIM; --Xilinx
use UNISIM.vcomponents.all; --Xilinx
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable tri_port_ram : ram_type;
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type;
variable dual_port_ram2 : ram_type;
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
begin
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end generate; --xilinx_16x1d
-- Option #4
-- Altera LPM_RAM_DP
-- Xilinx users may need to comment out this section!!!
altera_mem:
if memory_type = "ALTERA_LPM" generate
lpm_ram_dp_component1 : lpm_ram_dp
GENERIC MAP (
lpm_width => 32,
lpm_widthad => 5,
rden_used => "FALSE",
intended_device_family => "UNUSED",
lpm_indata => "REGISTERED",
lpm_wraddress_control => "REGISTERED",
lpm_rdaddress_control => "UNREGISTERED",
lpm_outdata => "UNREGISTERED",
use_eab => "ON",
lpm_type => "LPM_RAM_DP"
)
PORT MAP (
wren => write_enable,
wrclock => clk,
data => reg_dest_new,
rdaddress => addr_read1,
wraddress => addr_write,
q => data_out1
);
lpm_ram_dp_component2 : lpm_ram_dp
GENERIC MAP (
lpm_width => 32,
lpm_widthad => 5,
rden_used => "FALSE",
intended_device_family => "UNUSED",
lpm_indata => "REGISTERED",
lpm_wraddress_control => "REGISTERED",
lpm_rdaddress_control => "UNREGISTERED",
lpm_outdata => "UNREGISTERED",
use_eab => "ON",
lpm_type => "LPM_RAM_DP"
)
PORT MAP (
wren => write_enable,
wrclock => clk,
data => reg_dest_new,
rdaddress => addr_read2,
wraddress => addr_write,
q => data_out2
);
end generate; --altera_mem
-- Option #5
-- dual_port_mem_coregen:
-- if memory_type = "DUAL_PORT_XILINX" generate
-- reg_file_dp_ram_1: reg_file_dp_ram
-- port map (
-- addra => addr_read1,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out1,
-- web => write_enable);
--
-- reg_file_dp_ram_2: reg_file_dp_ram
-- port map (
-- addra => addr_read2,
-- addrb => addr_write,
-- clka => clk,
-- clkb => clk,
-- dinb => reg_dest_new,
-- douta => data_out2,
-- web => write_enable);
-- end generate; --dual_port_mem
-- dual_port_mem_xc4000xla: if memory_type = "DUAL_PORT_XILINX_XC4000XLA" generate
-- reg_file_dp_ram_1: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read1,
-- SPO => open,
-- DPO => data_out1);
--
-- reg_file_dp_ram_2: reg_file_dp_ram_xc4000xla
-- port map (
-- A => addr_write,
-- DI => reg_dest_new,
-- WR_EN => write_enable,
-- WR_CLK => clk,
-- DPRA => addr_read2,
-- SPO => open,
-- DPO => data_out2);
-- end generate; --dual_port_mem
-- Option #6
-- Generic Two-Port Synchronous RAM
-- generic_tpram can be obtained from:
-- http://www.opencores.org/cvsweb.shtml/generic_memories/
-- Supports ASICs (Artisan, Avant, and Virage) and Xilinx FPGA
-- generic_mem:
-- if memory_type = "OPENCORES_MEM" generate
-- bank1 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read1,
-- di_a => ZERO,
-- do_a => data_out1,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
--
-- bank2 : generic_tpram port map (
-- clk_a => clk,
-- rst_a => '0',
-- ce_a => '1',
-- we_a => '0',
-- oe_a => '1',
-- addr_a => addr_read2,
-- di_a => ZERO,
-- do_a => data_out2,
--
-- clk_b => clk,
-- rst_b => '0',
-- ce_b => '1',
-- we_b => write_enable,
-- oe_b => '0',
-- addr_b => addr_write,
-- di_a => reg_dest_new);
-- end generate; --generic_mem
-- Option #7
-- Xilinx mode using four 16x16 banks
-- xilinx_mem:
-- if memory_type = "XILINX" generate
-- bank1_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank1_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read1,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out1(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_high: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(31 downto 16),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(31 downto 16),
-- enb => sig_true,
-- web => write_enable);
--
-- bank2_low: ramb4_s16_s16 port map (
-- clka => clk,
-- rsta => sig_false,
-- addra => addr_read2,
-- dia => zero_sig,
-- ena => sig_true,
-- wea => sig_false,
-- doa => data_out2(15 downto 0),
--
-- clkb => clk,
-- rstb => sig_false,
-- addrb => addr_write,
-- dib => reg_dest_new(15 downto 0),
-- enb => sig_true,
-- web => write_enable);
-- end generate; --xilinx_mem
end; --architecture ram_block
| gpl-3.0 | 55cf2785b94593d75e8e062791243ac3 | 0.499178 | 3.396113 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/video/video.vhd | 1 | 5,834 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 65MHz
RESET : in std_logic; -- Reset (active low)
VRAM_A : out std_logic_vector(13 downto 0);
VRAM_D : in std_logic_vector(7 downto 0);
COLORS : in std_logic_vector(6 downto 0);
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
-- VGA timing constants (XGA - 1024x768@60) (512x768@60)
-- HOR
constant HSIZE : INTEGER := 512; -- Visible area
constant HFP : INTEGER := 12; -- Front porch
constant HS : INTEGER := 68; -- HSync pulse
constant HB : INTEGER := 80; -- Back porch
constant HOFFSET : INTEGER := 0; -- HSync offset
-- VER
constant VSIZE : INTEGER := 768; -- Visible area
constant VFP : INTEGER := 3; -- Front porch
constant VS : INTEGER := 6; -- VSync pulse
constant VB : INTEGER := 29; -- Back porch
constant VOFFSET : INTEGER := 0; -- VSync offset
------------------------------------------------------------
signal H_COUNTER : UNSIGNED(9 downto 0); -- Horizontal Counter
signal V_COUNTER : UNSIGNED(9 downto 0); -- Vertical Counter
signal THREE_ROW_CNT : UNSIGNED(1 downto 0); -- 3 Row Counter
signal ROW_COUNTER : UNSIGNED(7 downto 0); -- Korvet Row Counter
signal PAPER : STD_LOGIC; -- Paper zone
signal PAPER_L : STD_LOGIC; -- Paper zone
signal COLOR_R : STD_LOGIC;
signal COLOR_G : STD_LOGIC;
signal COLOR_B : STD_LOGIC;
signal PIX0 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX1 : STD_LOGIC_VECTOR(3 downto 0);
begin
u_COLOR_MUX : entity work.clr_mux
port map(
color => PIX1(3 - to_integer(H_COUNTER(2 downto 1))) & PIX0(3 - to_integer(H_COUNTER(2 downto 1))),
portb => COLORS,
out_r => COLOR_R,
out_g => COLOR_G,
out_b => COLOR_B );
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= (others=>'0');
else
if H_COUNTER = 544 then
if V_COUNTER < 768 then
THREE_ROW_CNT <= THREE_ROW_CNT + 1;
if THREE_ROW_CNT = 2 then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= ROW_COUNTER + 1;
end if;
else
ROW_COUNTER <= (others=>'0');
THREE_ROW_CNT <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
HSYNC <= '1';
VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HOFFSET + HFP) and H_COUNTER < (HSIZE + HOFFSET + HFP + HS) then
HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VOFFSET + VFP) and V_COUNTER < (VSIZE + VOFFSET + VFP + VS) then
VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" =>
VRAM_A <= std_logic_vector(ROW_COUNTER) & std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX0 <= VRAM_D(3 downto 0);
PIX1 <= VRAM_D(7 downto 4);
PAPER_L <= PAPER;
when OTHERS =>
null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_L = '1' then
if THREE_ROW_CNT = "01" then
R <= COLOR_R & COLOR_R & COLOR_R & COLOR_R;
G <= COLOR_G & COLOR_G & COLOR_G & COLOR_G;
B <= COLOR_B & COLOR_B & COLOR_B & COLOR_B;
else
R <= COLOR_R & "000";
G <= COLOR_G & "000";
B <= COLOR_B & "000";
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 7bc7ee0ff1635dab6f194962bbebcd5c | 0.424237 | 4.117149 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/rom/rom.vhd | 1 | 5,405 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32768,
c_read_depth_b => 32768,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32768,
c_write_depth_b => 32768,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
| gpl-3.0 | 47748c7dead2c8450203963a6c5dc2fb | 0.512673 | 3.980118 | false | false | false | false |
sonologic/gmzpu | vhdl/ZetaIO/timer/timer_pkg.vhdl | 1 | 1,943 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package tim is
component timer is
generic (
ADR_WIDTH : natural:=3;
DATA_WIDTH : natural:=32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
inc_i : in std_logic;
addr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
we_i : in std_logic;
en_i : in std_logic;
thresh_o: out std_logic
);
end component timer;
component timers is
generic (
DATA_WIDTH : natural:=32;
ADR_WIDTH : natural:=4;
N_TIMERS : natural:=4
);
port (
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic;
-- non wishbone
irq_o : out std_logic
);
end component timers;
end package tim;
| bsd-3-clause | 732eb5dd8070cbeac2cd8c973bc4438c | 0.468863 | 3.611524 | false | false | false | false |
sonologic/gmzpu | vhdl/zwishbone/test/zwishbone_controller_tb.vhdl | 1 | 13,135 | ------------------------------------------------------------------------------
---- ----
---- gmzpu zwc component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone.all;
entity zwishbone_controller_TB is
end entity zwishbone_controller_TB;
architecture Behave of zwishbone_controller_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant ADR_WIDTH : natural:=16;
constant BUSBIT_WIDTH : natural:=1;
constant CS_WIDTH : natural:=4;
constant DATA_WIDTH : natural:=32;
type sample is record
-- inputs
rst_i : std_logic;
adr_i : unsigned(ADR_WIDTH-1 downto 0);
re_i : std_logic;
we_i : std_logic;
dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_ack_i : std_logic;
wb_stall_i : std_logic;
wb_err_i : std_logic;
wb_rty_i : std_logic;
-- outputs
wb_cyc_o : std_logic;
wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
wb_we_o : std_logic;
wb_lock_o : std_logic;
busy_o : std_logic;
ready_o : std_logic;
dat_o : unsigned(DATA_WIDTH-1 downto 0);
irq_o : std_logic;
wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
wb_adr_o : unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- rst adr_i re we dat_i wb_dat_i ack stl err rty | cyc stb we lck bus rdy dat_o irq wb_dat_o wb_adr_o
('1',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write config
('0',X"0000",'0','1',X"12345678",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- read config
('0',X"0000",'1','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','1',X"00000001",'0',X"00000000","00000000000"),
-- bus write, stb 1 (device 0)
('0',X"8000",'0','1',X"87654321",X"00000000",'0','0','0','0', '1',X"0001",'1','0','1','0',X"00000000",'0',X"87654321","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'1','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, stb 2 (device 1)
('0',X"8803",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',X"0000",'0','0',X"00000000",X"9abcdef0",'1','0','0','0', '1',X"0000",'0','0','0','1',X"9abcdef0",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write timeout compare reg (set to 2)
('0',X"0008",'0','1',X"00000002",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, timeout
('0',X"8803",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'1',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
-- cancel timeout status (write 0 to status reg)
('0',X"0004",'0','1',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- terminate
('0',X"0000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000")
);
signal clk : std_logic;
-- inputs
signal rst_i : std_logic;
signal adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal re_i : std_logic;
signal we_i : std_logic;
signal dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_rty_i : std_logic;
signal wb_tgd_i : unsigned(DATA_WIDTH -1 downto 0);
-- outputs
signal wb_cyc_o : std_logic;
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_we_o : std_logic;
signal wb_lock_o : std_logic;
signal busy_o : std_logic;
signal ready_o : std_logic;
signal dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal irq_o : std_logic;
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgc_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_adr_o : unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_tga_o : unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
dut : zwishbone_controller
generic map(ADR_WIDTH => ADR_WIDTH, DATA_WIDTH => DATA_WIDTH, BUSBIT_WIDTH => BUSBIT_WIDTH, CS_WIDTH => CS_WIDTH)
port map(clk_i => clk, rst_i => rst_i,
busy_o => busy_o, ready_o => ready_o, adr_i => adr_i, re_i => re_i, we_i => we_i,
dat_i => dat_i, dat_o => dat_o, irq_o => irq_o,
wb_dat_i => wb_dat_i, wb_dat_o => wb_dat_o, wb_tgd_i => wb_tgd_i,
wb_ack_i => wb_ack_i, wb_adr_o => wb_adr_o, wb_cyc_o => wb_cyc_o,
wb_stall_i => wb_stall_i, wb_err_i => wb_err_i, wb_lock_o => wb_lock_o,
wb_rty_i => wb_rty_i, wb_sel_o => wb_sel_o, wb_stb_o => wb_stb_o,
wb_tga_o => wb_tga_o, wb_tgc_o => wb_tgc_o, wb_we_o => wb_we_o);
wb_dat_o <= (others => 'L');
wb_adr_o <= (others => 'L');
dat_o <= (others => 'L');
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
rst_i <= test_data(i).rst_i;
adr_i <= test_data(i).adr_i;
re_i <= test_data(i).re_i;
we_i <= test_data(i).we_i;
dat_i <= test_data(i).dat_i;
wb_dat_i <= test_data(i).wb_dat_i;
wb_tgd_i <= (others => 'Z'); --test_data(i).wb_tgd_i;
wb_ack_i <= test_data(i).wb_ack_i;
wb_stall_i <= test_data(i).wb_stall_i;
wb_err_i <= test_data(i).wb_err_i;
wb_rty_i <= test_data(i).wb_rty_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (dat_o = test_data(i).dat_o) report "dat_o output mismatch" severity error;
assert (busy_o = test_data(i).busy_o) report "busy_o output mismatch" severity error;
assert (ready_o = test_data(i).ready_o) report "ready_o output mismatch" severity error;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (wb_cyc_o = test_data(i).wb_cyc_o) report "wb_cyc_o output mismatch" severity error;
assert (wb_stb_o = test_data(i).wb_stb_o) report "wb_stb_o output mismatch" severity error;
assert (wb_we_o = test_data(i).wb_we_o) report "wb_we_o output mismatch" severity error;
assert (wb_adr_o = test_data(i).wb_adr_o) report "wb_adr_o output mismatch" severity error;
assert (wb_dat_o = test_data(i).wb_dat_o) report "wb_dat_o output mismatch" severity error;
--assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
--assert (wb_ack_o = test_data(i).wb_ack_o) report "ack_o output mismatch" severity error;
-- assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause | 9a864bd1ef7182de11bc6c213250836e | 0.441568 | 3.369677 | false | true | false | false |
APastorG/APG | real_const_mult/real_const_mult_u.vhd | 1 | 3,953 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a real_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_u is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MULTIPLICANDS : real_v --compulsory
);
port(
input : in u_ufixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_u_1 of real_const_mult_u is
constant CHECKS : integer := real_const_mult_CHECKS(input'high,
input'low,
true, --UNSIGNED_2COMP_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS);
constant MULTIPLICANDS_adjusted : real_v(1 to MULTIPLICANDS'length) := MULTIPLICANDS;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_u_1:
entity work.real_const_mult_core_u
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_adjusted,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | 6f76d25760806ba0e7d3f54ac69c16dc | 0.402399 | 4.756068 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/pll/pll.vhd | 1 | 6,511 | -- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLKIN : in std_logic;
-- Clock out ports
CLKOUT : out std_logic;
CLKOUT2 : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLKIN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 39,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 34,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 17,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLKOUT,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLKOUT2,
I => clkout1);
end xilinx;
| gpl-3.0 | 3de9ed032b54ad1458ac1f75fc46f556 | 0.578252 | 4.149777 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult.vhd | 1 | 7,227 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a real_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MULTIPLICANDS : real_v --compulsory
);
port(
input : in std_ulogic_vector;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out sulv_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_1 of real_const_mult is
constant NORM_IN_HIGH : integer := input'high-SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input'low-SULV_NEW_ZERO;
constant CHECKS : integer := real_const_mult_CHECKS(input'high,
input'low,
UNSIGNED_2COMP_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS);
constant NORM_OUT_HIGH : integer := real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS,
NORM_IN_HIGH,
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant NORM_OUT_LOW : integer := real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS,
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_s : u_sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_s : u_sfixed_v(1 to MULTIPLICANDS'length)(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_u : u_ufixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_u : u_ufixed_v(1 to MULTIPLICANDS'length)(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_debugging:
if DEBUGGING generate
msg_debug("real_const_mult : NORM_IN_HIGH: " & image(NORM_IN_HIGH));
msg_debug("real_const_mult : NORM_IN_LOW: " & image(NORM_IN_LOW));
msg_debug("real_const_mult : NORM_OUT_HIGH: " & image(NORM_OUT_HIGH));
msg_debug("real_const_mult : NORM_OUT_LOW: " & image(NORM_OUT_LOW));
end;
end generate;
generate_real_const_mult:
if UNSIGNED_2COMP_opt generate
constant MULTIPLICANDS_adjusted : real_v(1 to MULTIPLICANDS'length) := MULTIPLICANDS;
begin
aux_input_u <= to_ufixed(input, aux_input_u);
generate_output_members:
for i in 1 to MULTIPLICANDS'length generate
begin
output(i)(OUT_HIGH doWnto OUT_LOW) <= to_sulv(aux_output_u(i));
end generate;
real_const_mult_u_1:
entity work.real_const_mult_u
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => MULTIPLICANDS_adjusted
)
port map(
input => aux_input_u,
clk => clk,
valid_input => valid_input,
output => aux_output_u,
valid_output => valid_output
);
else generate
constant MULTIPLICANDS_adjusted : real_v(1 to MULTIPLICANDS'length) := MULTIPLICANDS;
begin
aux_input_s <= to_sfixed(input, aux_input_s);
generate_output_members:
for i in 1 to MULTIPLICANDS'length generate
begin
output(i)(OUT_HIGH doWnto OUT_LOW) <= to_sulv(aux_output_s(i));
end generate;
real_const_mult_s_1:
entity work.real_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => MULTIPLICANDS_adjusted
)
port map(
input => aux_input_s,
clk => clk,
valid_input => valid_input,
output => aux_output_s,
valid_output => valid_output
);
end generate;
end architecture; | mit | 110c6901c49bf28dbe7ca47893c84584 | 0.44307 | 4.404776 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/clock/clock.vhd | 1 | 6,674 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____56.000______0.000______50.0______557.143____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 28,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
| gpl-3.0 | 26e44d2dcad5b2a746e61107329b3e5b | 0.551993 | 4.240152 | false | false | false | false |
APastorG/APG | complex_const_multiplier/complex_const_mult_core_s.vhd | 1 | 13,521 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.complex_const_mult_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity complex_const_mult_core_s is
generic(
SPEED_opt : T_speed := t_exc;
ROUND_STYLE_opt : T_round_style := fixed_truncate;
ROUND_TO_BIT_opt : integer_exc := integer'low;
MAX_ERROR_PCT_opt : real_exc := real'low;
MIN_OUTPUT_BIT : integer := integer'low;
MAX_OUTPUT_BIT : integer := integer'low;
MULTIPLICAND_REAL : real;
MULTIPLICAND_IMAG : real;
INPUT_HIGH : integer;
INPUT_LOW : integer
);
port(
clk : in std_ulogic;
input_real : in u_sfixed;
input_imag : in u_sfixed;
valid_input : in std_ulogic;
output_real : out u_sfixed(complex_const_mult_OH(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
max_output_bit => MAX_OUTPUT_BIT,
constants(0 to 1) => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_high => INPUT_HIGH,
input_low => INPUT_LOW,
is_signed => true)
downto
complex_const_mult_OL(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
min_output_bit => MIN_OUTPUT_BIT,
constants(0 to 1) => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_low => INPUT_LOW,
is_signed => true)
);
output_imag : out u_sfixed(complex_const_mult_OH(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
max_output_bit => MAX_OUTPUT_BIT,
constants(0 to 1) => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_high => INPUT_HIGH,
input_low => INPUT_LOW,
is_signed => true)
downto
complex_const_mult_OL(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
min_output_bit => MIN_OUTPUT_BIT,
constants(0 to 1) => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_low => INPUT_LOW,
is_signed => true)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture complex_const_mult_core_s_1 of complex_const_mult_core_s is
signal inter : u_sfixed_v(1 to 4)(real_const_mult_OH(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
constants => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_high => INPUT_HIGH,
input_low => INPUT_LOW,
is_signed => true)
downto
real_const_mult_OL(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
constants => (MULTIPLICAND_REAL,
MULTIPLICAND_IMAG),
input_low => INPUT_LOW,
is_signed => true)
);
signal valid_input_inter : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("input_real'high: " & image(input_real'high));
msg_debug("input_real'low: " & image(input_real'low));
msg_debug("inter(1)'high: " & image(inter(1)'high));
msg_debug("inter(1)'low: " & image(inter(1)'low));
constants_are_zero_or_not:
if MULTIPLICAND_IMAG=0.0 and MULTIPLICAND_REAL=0.0 generate
begin
valid_output <= valid_input;
--output will be zero, so we leave both real_out and imag_out open
end;
elsif MULTIPLICAND_IMAG=0.0 xor MULTIPLICAND_REAL=0.0 generate
constant CONSTANTS : real_v := (1 => ite(MULTIPLICAND_REAL=0.0,
MULTIPLICAND_IMAG,
MULTIPLICAND_REAL));
begin
const_mult_real_part:
entity work.real_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => CONSTANTS
)
port map(
input => input_real,
clk => clk,
valid_input => valid_input,
output(1) => inter(1),
valid_output => valid_input_inter
);
const_mult_imag_part:
entity work.real_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => CONSTANTS
)
port map(
input => input_imag,
clk => clk,
valid_input => valid_input,
output(1) => inter(3),
valid_output => open
);
generate_addition:
if MULTIPLICAND_REAL=0.0 generate
begin
generate_output:
if is_pipelined(1, SPEED_opt, 1) generate
begin
process (clk) is
begin
if rising_edge(clk) then
output_imag <= resize(inter(1), output_imag);
output_real <= resize(-inter(3), output_real);
end if;
end process;
end;
else generate
begin
output_imag <= resize(inter(1), output_imag);
output_real <= resize(-inter(3), output_real);
end;
end generate;
control_logic:
entity work.pipelines
generic map(
LENGTH => number_of_pipelines(1, SPEED_opt)
)
port map(
clk => clk,
input => (1 => valid_input_inter),
output(1) => valid_output
);
end;
elsif MULTIPLICAND_IMAG=0.0 generate
begin
output_real <= resize(inter(1), output_real);
output_imag <= resize(inter(3), output_imag);
control_logic:
entity work.pipelines
generic map(
LENGTH => 0
)
port map(
clk => clk,
input => (1 => valid_input_inter),
output(1) => valid_output
);
end;
end generate;
end;
else generate
constant CONSTANTS : real_v := (MULTIPLICAND_REAL, MULTIPLICAND_IMAG);
begin
const_mult_real_part:
entity work.real_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => CONSTANTS
)
port map(
input => input_real,
clk => clk,
valid_input => valid_input,
output(1 to 2) => inter(1 to 2),
valid_output => valid_input_inter
);
const_mult_imag_part:
entity work.real_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => CONSTANTS
)
port map(
input => input_imag,
clk => clk,
valid_input => valid_input,
output => inter(3 to 4),
valid_output => open
);
generate_output:
if is_pipelined(1, SPEED_opt, 1) generate
begin
process (clk) is
begin
if rising_edge(clk) then
output_real <= resize(inter(1)-inter(4), output_real);
output_imag <= resize(inter(2)+inter(3), output_imag);
end if;
end process;
end;
else generate
begin
output_real <= resize(inter(1)-inter(4), output_real);
output_imag <= resize(inter(2)+inter(3), output_imag);
end;
end generate;
control_logic:
entity work.pipelines
generic map(
LENGTH => number_of_pipelines(1, SPEED_opt)
)
port map(
clk => clk,
input => (1 => valid_input_inter),
output(1) => valid_output
);
end;
end generate;
end architecture; | mit | 2f92983f77c5358395a5a74131c70e7a | 0.352339 | 5.231575 | false | false | false | false |
sonologic/gmzpu | vhdl/zwishbone/zwishbone.vhdl | 1 | 24,385 | ------------------------------------------------------------------------------
---- ----
---- ZWISHBONE gmZPU WISHBONE B4 controller ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- Interface between the gmZPU zpu core and the WISHBONE B4 bus. ----
---- ----
---- Author: ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_controller ----
---- File name: zwishbone.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: Yes ----
---- Synthesis tools: ModelSim ----
---- Simulation tools: ModelSim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=15;
DATA_WIDTH : natural:=32
);
port (
-- syscon
clk_i : in std_logic;
rst_i : in std_logic;
irq_o : out std_logic;
-- memory control
re_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- bus
to_inc_i : in std_logic;
to_rst_i : in std_logic;
to_o : out std_logic;
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0);
-- status register value (0x0004, from c_control / bus)
err_i : in std_logic;
rty_i : in std_logic
);
end entity zwishbone_c_regs;
architecture rtl of zwishbone_c_regs is
-- registers
signal reg_config : unsigned(DATA_WIDTH-1 downto 0); -- := (others => '0');
signal reg_status : unsigned(DATA_WIDTH-1 downto 0); -- := (others => '0');
signal reg_to_cmp : unsigned(DATA_WIDTH-1 downto 0); -- := (others => '0');
signal reg_to_val : unsigned(DATA_WIDTH-1 downto 0); -- := (others => '0');
-- reg_status signals
signal to_r : std_logic;
signal to_rst_r : std_logic;
-- reg_config bits
constant R_CFG_PIPELINE_BIT : natural:=0;
constant R_CFG_BLOCK_BIT : natural:=1;
constant R_CFG_RMW_BIT : natural:=2;
-- reg_status bits
constant R_STATUS_ERR : natural:=0;
constant R_STATUS_RTY : natural:=1;
constant R_STATUS_TO : natural:=2;
constant R_STATUS_UNUSED : natural:=3;
-- memory control
signal reading_r : std_logic;
--signal ready_r : std_logic;
begin
-- export CONFIG register value
cfg_o <= reg_config;
irq_o <= err_i or rty_i or to_r;
process(clk_i,rst_i,to_rst_i,to_rst_r)
begin
if rst_i='1' or to_rst_i='1' or to_rst_r='1' then
reg_to_val <= x"00000000";
to_r <= '0';
elsif rising_edge(clk_i) then
if to_rst_i='0' then
if reg_to_val = reg_to_cmp then
to_r <= '1';
elsif to_inc_i='1' then
reg_to_val <= reg_to_val + 1;
end if;
else
reg_to_val <= (others => '0');
to_r <= '0';
end if;
end if;
end process;
to_o <= to_r;
process(clk_i,rst_i)
begin
if rst_i='1' then
reg_config <= (others => '0');
reg_config(R_CFG_PIPELINE_BIT) <= '1';
dat_o <= (others => '0');
reading_r <= '0';
reg_to_cmp <= x"0000000f";
reg_status <= (others => '0');
to_rst_r <= '0';
elsif rising_edge(clk_i) then
-- clock in status register
reg_status(R_STATUS_ERR) <= err_i;
reg_status(R_STATUS_RTY) <= rty_i;
reg_status(R_STATUS_TO) <= to_r;
reg_status(DATA_WIDTH-1 downto R_STATUS_UNUSED) <= (others => '0');
to_rst_r <= '0';
if re_i='1' then
reading_r <= '1';
case adr_i(3 downto 2) is
-- adr 0x0 (0000) : CONFIG register
-- adr 0x4 (0100) : STATUS register
-- adr 0x8 (1000) : TO_CMP register
-- adr 0xc (1100) : TO_VAL register
-- only two msb are relevant
when "00" =>
dat_o <= reg_config;
when "01" =>
dat_o <= reg_status;
when "10" =>
dat_o <= reg_to_cmp;
when others =>
dat_o <= reg_to_val;
end case;
elsif we_i='1' then
dat_o <= (others => 'Z');
case adr_i(3 downto 2) is
when "00" =>
reg_config <= (others => '0');
reg_config(R_CFG_PIPELINE_BIT) <= '1';
when "01" =>
-- writing 0 to bit R_STATUS_TO in status resets timeout counter
if dat_i(R_STATUS_TO)='0' then
to_rst_r <= '1';
end if;
when "10" =>
reg_to_cmp <= dat_i;
when others =>
-- writing to val resets timeout counter
to_rst_r <= '1';
end case;
else
-- deassert reading_r on the rising clock after assertion
if reading_r='1' then
reading_r <= '0';
dat_o <= (others => 'Z');
end if;
end if;
end if;
end process;
end architecture rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
entity zwishbone_controller is
generic (
DATA_WIDTH : natural:=32; -- width of data bus
ADR_WIDTH : natural:=16;
BUSBIT_WIDTH: natural:=1;
CS_WIDTH : natural:=4
);
port (
-- SYSCON
clk_i : in std_logic;
rst_i : in std_logic;
-- zpu interface (non wishbone signal)
busy_o : out std_logic; -- controller busy
ready_o : out std_logic; -- read request ready
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
we_i : in std_logic;
re_i : in std_logic; -- enable wb controller
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
irq_o : out std_logic;
-- I/O decoder
--cs_o : out std_logic_vector(CS_WIDTH-1 downto 0);
-- wishbone bus
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_ack_i : in std_logic;
wb_adr_o : out unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
wb_cyc_o : out std_logic;
wb_stall_i : in std_logic;
wb_err_i : in std_logic;
wb_lock_o : out std_logic;
wb_rty_i : in std_logic;
wb_sel_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_o : out std_logic_vector((2**CS_WIDTH)-1 downto 0);
wb_tga_o : out unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
wb_tgc_o : out unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_o : out std_logic
);
end entity zwishbone_controller;
--
architecture rtl of zwishbone_controller is
component zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=15;
DATA_WIDTH : natural:=32
);
port (
-- syscon
clk_i : in std_logic;
rst_i : in std_logic;
irq_o : out std_logic;
-- memory control
re_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- bus
to_inc_i : in std_logic;
to_rst_i : in std_logic;
to_o : out std_logic;
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0);
-- status register value (0x0004, from c_control / bus)
err_i : in std_logic;
rty_i : in std_logic
);
end component zwishbone_c_regs;
-- fsm
type state_type is (
idle,
write_start,
write_cycle,
write_terminate,
read_start,
read_cycle,
read_ready,
write_reg,
read_reg,
read_reg_ready
);
signal state : state_type;
signal next_state : state_type;
-- register component
signal reg_re_r : std_logic;
signal reg_we_r : std_logic;
signal reg_adr_ir : unsigned(ADR_WIDTH-BUSBIT_WIDTH-1 downto 0);
signal reg_dat_ir : unsigned(DATA_WIDTH-1 downto 0);
signal reg_dat_or : unsigned(DATA_WIDTH-1 downto 0);
signal to_r : std_logic;
signal to_inc_r : std_logic;
signal to_rst_r : std_logic;
-- inputs to status reg
signal err_r : std_logic;
signal rty_r : std_logic;
-- config exported from regs
signal config_r : unsigned(DATA_WIDTH-1 downto 0);
begin
registers: zwishbone_c_regs
generic map ( ADR_WIDTH => ADR_WIDTH-BUSBIT_WIDTH, DATA_WIDTH => DATA_WIDTH )
port map ( clk_i => clk_i, rst_i => rst_i, irq_o => irq_o,
re_i => reg_re_r, we_i => reg_we_r,
adr_i => reg_adr_ir,
dat_i => reg_dat_ir, dat_o => reg_dat_or,
to_inc_i => to_inc_r, to_rst_i => to_rst_r, to_o => to_r,
cfg_o => config_r, err_i => err_r, rty_i => rty_r);
err_r <= '0';
rty_r <= '0';
-- registered
transition:
process(clk_i,rst_i)
begin
if rst_i='1' then
state <= idle;
elsif rising_edge(clk_i) then
case state is
when write_start =>
if wb_ack_i='1' then
state <= write_terminate;
else
state <= write_cycle;
end if;
when write_cycle =>
if to_r='1' then
state <= idle;
elsif wb_ack_i='1' then
state <= write_terminate;
else
state <= write_cycle;
end if;
when write_terminate =>
state <= idle;
when read_start =>
if wb_ack_i='1' then
state <= read_ready;
else
state <= read_cycle;
end if;
when read_cycle =>
if to_r='1' then
state <= idle;
elsif wb_ack_i='1' then
state <= read_ready;
else
state <= read_cycle;
end if;
when read_ready =>
state <= idle;
when write_reg =>
state <= idle;
when read_reg =>
state <= read_reg_ready;
--when read_reg_ready =>
-- state <= idle;
when others => -- also read_reg_ready
-- others includes state idle
state <= idle;
-- active when MSB is 1 (0 means register access)
if adr_i(ADR_WIDTH-1)='1' then
if re_i='1' then
state <= read_start;
elsif we_i='1' then
state <= write_start;
end if;
else
-- register access
if re_i='1' then
state <= read_reg;
elsif we_i='1' then
state <= write_reg;
end if;
end if;
end case;
end if;
end process transition;
-- irq_o !
-- unregistered (no registers, no latches!)
process(state,adr_i,dat_i,reg_dat_or,to_r)
variable bus_adr_v : unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
variable reg_adr_v : unsigned(ADR_WIDTH-BUSBIT_WIDTH-1 downto 0);
variable cs_v : unsigned(CS_WIDTH-1 downto 0);
begin
-- split address in bus address and chip select (=stb_o bit)
bus_adr_v := adr_i(bus_adr_v'left downto 0);
reg_adr_v := adr_i(reg_adr_v'left downto 0);
cs_v := adr_i(ADR_WIDTH-BUSBIT_WIDTH-1 downto ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH);
case state is
when write_start =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '1';
wb_dat_o <= dat_i;
wb_tgd_o <= (others => '0');
wb_adr_o <= bus_adr_v;
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_sel_o <= (others => '1');
wb_stb_o <= (others => '0');
wb_stb_o((2**to_integer(cs_v))-1) <= '1';
wb_tga_o <= (others => '0');
wb_tgc_o <= (others => '0');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= '0';
to_rst_r <= '1';
when write_cycle =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when write_terminate =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when read_start =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_adr_o <= bus_adr_v;
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_stb_o((2**to_integer(cs_v))-1) <= '1';
wb_tgd_o <= (others => '0');
wb_sel_o <= (others => '1');
wb_tga_o <= (others => '0');
wb_tgc_o <= (others => '0');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= '0';
to_rst_r <= '1';
when read_cycle =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= '1';
to_rst_r <= '0';
when read_ready =>
busy_o <= '0';
ready_o <= '1';
dat_o <= wb_dat_i;
--
wb_we_o <= '0';
wb_cyc_o <= '1';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when write_reg =>
busy_o <= '0';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '0';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '1';
reg_dat_ir <= dat_i;
reg_adr_ir <= reg_adr_v;
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when read_reg =>
busy_o <= '1';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_cyc_o <= '0';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '1';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when read_reg_ready =>
busy_o <= '0';
ready_o <= '1';
dat_o <= reg_dat_or;
--
wb_we_o <= '0';
wb_cyc_o <= '0';
wb_lock_o <= '0';
wb_adr_o <= (others => 'Z');
wb_dat_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tgd_o <= (others => 'Z');
wb_sel_o <= (others => 'Z');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= reg_adr_v;
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
when others =>
-- others includes state idle
busy_o <= '0';
ready_o <= '0';
dat_o <= (others => 'Z');
--
wb_we_o <= '0';
wb_dat_o <= (others => 'Z');
wb_tgd_o <= (others => 'Z');
wb_adr_o <= (others => 'Z');
wb_cyc_o <= '0';
wb_lock_o <= '0';
wb_sel_o <= (others => 'Z');
wb_stb_o <= (others => '0');
wb_tga_o <= (others => 'Z');
wb_tgc_o <= (others => 'Z');
--
reg_re_r <= '0';
reg_we_r <= '0';
reg_dat_ir <= (others => '0');
reg_adr_ir <= (others => '0');
--
to_inc_r <= to_r;
to_rst_r <= not to_r;
end case;
end process;
end architecture rtl;
| bsd-3-clause | 89c926b703db6c8117af778787181bee | 0.34267 | 4.083906 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/graphics_mem.vhd | 1 | 3,308 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: graphics_mem
--
-- Description:
--
-- Dual-port RAM for graphics
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity graphics_mem is
generic(
MEM_ADDR_WIDTH : natural := 32;
MEM_DATA_WIDTH : natural := 32;
MEM_SIZE : natural := 4800
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
wr_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- write address input
rd_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- read address input
wr_data_i : in std_logic_vector(MEM_DATA_WIDTH-1 downto 0); -- Write data output
we_i : in std_logic; -- 1 - write transaction
rd_data_o : out std_logic -- read data output
);
end entity;
architecture arc_graphics_mem of graphics_mem is
type t_graphics_mem is array (0 to MEM_SIZE/MEM_DATA_WIDTH-1) of std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
signal graphics_mem : t_graphics_mem := (
-- 0 => "000000",
-- 1 => "000001",
-- 2 => "000010",
others => (others => '0')
);
signal mem_up_addr : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
signal mem_lo_addr : std_logic_vector(5-1 downto 0);
signal rd_value : std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
signal index_0_t : natural;
signal index_0 : natural;
signal index_1_t : natural;
signal index_1 : natural;
signal index_2_t : natural;
signal index_2 : natural;
begin
-- get address for graphics mem based on memory format
mem_up_addr <= "000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 3) when (MEM_DATA_WIDTH = 8) else
"0000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 4) when (MEM_DATA_WIDTH = 16) else
"00000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 5);
mem_lo_addr <= "00" & rd_addr_i(3-1 downto 0) when (MEM_DATA_WIDTH = 8) else
'0' & rd_addr_i(4-1 downto 0) when (MEM_DATA_WIDTH = 16) else
rd_addr_i(5-1 downto 0);
DP_GRAPHICS_MEM : process (clk_i) begin
if (rising_edge(clk_i)) then
if (we_i = '1') then
graphics_mem(index_2) <= wr_data_i;
end if;
--rd_value <= graphics_mem(conv_integer(index_0));
end if;
end process;
DP_GRAPHICS_MEM_RD : process (clk_i) begin
if (rising_edge(clk_i)) then
rd_value <= graphics_mem(conv_integer(index_0));
end if;
end process;
rd_data_o <= rd_value(conv_integer(index_1));
index_0_t <= conv_integer(mem_up_addr);
index_0 <= index_0_t when (index_0_t < graphics_mem'length) else 0;
index_1_t <= conv_integer(mem_lo_addr);
index_1 <= index_1_t when (index_1_t < graphics_mem'length) else 0;
index_2_t <= conv_integer(wr_addr_i);
index_2 <= index_2_t when (index_2_t < graphics_mem'length) else 0;
end arc_graphics_mem; | mit | 265a3b92ad4cb1547949b5d21cc6312f | 0.548065 | 3.199226 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd | 20 | 168,945 | `protect begin_protected
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| mit | 361b627371eece967f7032b0debbe0a2 | 0.954322 | 1.812851 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/video/video_with_cache.vhd | 1 | 6,162 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; -- Active buffer
CACHE_A : out std_logic_vector(5 downto 0); -- Cache address
CACHE_D : in std_logic_vector(7 downto 0); -- Cache data
CURRENT_LINE : out std_logic_vector(7 downto 0); -- Current line to read in cache
COLORS : in std_logic_vector(6 downto 0);
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
-- VGA timing constants (XGA - 1024x768@60) (512x768@60)
-- HOR
constant HSIZE : INTEGER := 512; -- Visible area
constant HFP : INTEGER := 12; -- Front porch
constant HS : INTEGER := 68; -- HSync pulse
constant HB : INTEGER := 80; -- Back porch
constant HOFFSET : INTEGER := 0; -- HSync offset
-- VER
constant VSIZE : INTEGER := 768; -- Visible area
constant VFP : INTEGER := 3; -- Front porch
constant VS : INTEGER := 6; -- VSync pulse
constant VB : INTEGER := 29; -- Back porch
constant VOFFSET : INTEGER := 0; -- VSync offset
------------------------------------------------------------
signal H_COUNTER : UNSIGNED(9 downto 0); -- Horizontal Counter
signal V_COUNTER : UNSIGNED(9 downto 0); -- Vertical Counter
signal THREE_ROW_CNT : UNSIGNED(1 downto 0); -- 3 Row Counter
signal ROW_COUNTER : UNSIGNED(7 downto 0); -- Korvet Row Counter
signal PAPER : STD_LOGIC; -- Paper zone
signal PAPER_L : STD_LOGIC; -- Paper zone latched
signal COLOR_R : STD_LOGIC;
signal COLOR_G : STD_LOGIC;
signal COLOR_B : STD_LOGIC;
signal PIX0 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX1 : STD_LOGIC_VECTOR(3 downto 0);
begin
u_COLOR_MUX : entity work.clr_mux
port map(
color => PIX1(3 - to_integer(H_COUNTER(2 downto 1))) & PIX0(3 - to_integer(H_COUNTER(2 downto 1))),
portb => COLORS,
out_r => COLOR_R,
out_g => COLOR_G,
out_b => COLOR_B );
CURRENT_LINE <= std_logic_vector(ROW_COUNTER);
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= (others=>'0');
CACHE_SWAP <= '0';
else
CACHE_SWAP <= '0';
if H_COUNTER = 544 then
if V_COUNTER < 768 then
THREE_ROW_CNT <= THREE_ROW_CNT + 1;
if THREE_ROW_CNT = 2 then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= ROW_COUNTER + 1;
CACHE_SWAP <= '1';
end if;
else
ROW_COUNTER <= (others=>'0');
THREE_ROW_CNT <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
HSYNC <= '1';
VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HOFFSET + HFP) and H_COUNTER < (HSIZE + HOFFSET + HFP + HS) then
HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VOFFSET + VFP) and V_COUNTER < (VSIZE + VOFFSET + VFP + VS) then
VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" =>
CACHE_A <= std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX0 <= CACHE_D(3 downto 0);
PIX1 <= CACHE_D(7 downto 4);
PAPER_L <= PAPER;
when OTHERS =>
null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_L = '1' then
if THREE_ROW_CNT = "01" then
R <= COLOR_R & COLOR_R & COLOR_R & COLOR_R;
G <= COLOR_G & COLOR_G & COLOR_G & COLOR_G;
B <= COLOR_B & COLOR_B & COLOR_B & COLOR_B;
else
R <= COLOR_R & "000";
G <= COLOR_G & "000";
B <= COLOR_B & "000";
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 41f849bccd3684adce4216185023afa1 | 0.426972 | 4.13557 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/spi_master.vhd | 1 | 8,820 | --------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 7/23/2010 Scott Larson
-- Initial Public Release
-- Version 1.1 4/11/2013 Scott Larson
-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY spi_master IS
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2); --data bus width
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
END spi_master;
ARCHITECTURE logic OF spi_master IS
TYPE machine IS(ready, execute); --state machine data type
SIGNAL state : machine; --current state
SIGNAL slave : INTEGER; --slave selected for current transaction
SIGNAL clk_ratio : INTEGER; --current clk_div
SIGNAL count : INTEGER; --counter to trigger sclk from system clock
SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
SIGNAL continue : STD_LOGIC; --flag to continue transaction
SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
BEGIN
PROCESS(clock, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset system
busy <= '1'; --set busy signal
ss_n <= (OTHERS => '1'); --deassert all slave select lines
mosi <= 'Z'; --set master out to high impedance
rx_data <= (OTHERS => '0'); --clear receive data port
state <= ready; --go to ready state when reset is exited
ELSIF(clock'EVENT AND clock = '1') THEN
CASE state IS --state machine
WHEN ready =>
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave select outputs high
mosi <= 'Z'; --set mosi output high impedance
continue <= '0'; --clear continue flag
--user input to initiate transaction
IF(enable = '1') THEN
busy <= '1'; --set busy signal
IF(addr < slaves) THEN --check for valid slave address
slave <= addr; --clock in current slave selection if valid
ELSE
slave <= 0; --set to first slave if not valid
END IF;
IF(clk_div = 0) THEN --check for valid spi speed
clk_ratio <= 1; --set to maximum speed if zero
count <= 1; --initiate system-to-spi clock counter
ELSE
clk_ratio <= clk_div; --set to input selection if valid
count <= clk_div; --initiate system-to-spi clock counter
END IF;
sclk <= cpol; --set spi clock polarity
assert_data <= NOT cpha; --set spi clock phase
tx_buffer <= tx_data; --clock in data for transmit into buffer
clk_toggles <= 0; --initiate clock toggle counter
last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
state <= execute; --proceed to execute state
ELSE
state <= ready; --remain in ready state
END IF;
WHEN execute =>
busy <= '1'; --set busy signal
ss_n(slave) <= '0'; --set proper slave select output
--system clock to sclk ratio is met
IF(count = clk_ratio) THEN
count <= 1; --reset system-to-spi clock counter
assert_data <= NOT assert_data; --switch transmit/receive indicator
IF(clk_toggles = d_width*2 + 1) THEN
clk_toggles <= 0; --reset spi clock toggles counter
ELSE
clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
END IF;
--spi clock toggle needed
IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
sclk <= NOT sclk; --toggle spi clock
END IF;
--receive spi clock toggle
IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
END IF;
--transmit spi clock toggle
IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
mosi <= tx_buffer(d_width-1); --clock out data bit
tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
END IF;
--last data receive, but continue
IF(clk_toggles = last_bit_rx AND cont = '1') THEN
tx_buffer <= tx_data; --reload transmit buffer
clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
continue <= '1'; --set continue flag
END IF;
--normal end of transaction, but continue
IF(continue = '1') THEN
continue <= '0'; --clear continue flag
busy <= '0'; --clock out signal that first receive data is ready
rx_data <= rx_buffer; --clock out received data to output port
END IF;
--end of transaction
IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave selects high
mosi <= 'Z'; --set mosi output high impedance
rx_data <= rx_buffer; --clock out received data to output port
state <= ready; --return to ready state
ELSE --not end of transaction
state <= execute; --remain in execute state
END IF;
ELSE --system clock to sclk ratio not met
count <= count + 1; --increment counter
state <= execute; --remain in execute state
END IF;
END CASE;
END IF;
END PROCESS;
END logic;
| gpl-3.0 | 97cbde5e1cb32192db5173ccdaed3faf | 0.508617 | 4.59854 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/mult.vhd | 1 | 7,173 | ---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- MULTIPLICATION
-- long64 answer = 0
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0);
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO
and negate_reg = '1' else
upper_reg when mult_func = MULT_READ_HI else
ZERO;
pause_out <= '1' when (count_reg /= "000000") and
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
variable count : std_logic_vector(2 downto 0);
begin
count := "001";
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
elsif rising_edge(clk) then
case mult_func is
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
sign_reg <= a(31);
else
aa_reg <= a_neg;
bb_reg <= b_neg;
sign_reg <= a_neg(31);
end if;
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
when others =>
if count_reg /= "000000" then
if mode_reg = MODE_MULT then
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
count_reg(5 downto 2) /= "0000" then
upper_reg <= "0000" & upper_reg(31 downto 4);
lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
count := "100";
bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
else
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
count_reg <= count_reg - count;
end if; --count
end case;
end if;
end process;
end; --architecture logic
| gpl-3.0 | 17d4a9e6633becd8ef5bbcbb51a356fb | 0.436498 | 3.747649 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/rom/rom.vhd | 1 | 5,472 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
| gpl-3.0 | 2e6314e5bee32030ab41f74aa56e4165 | 0.51261 | 3.968093 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/rx_unit.vhdl | 1 | 5,790 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Rx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 rx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: RxUnit(Behaviour) (Entity and architecture) ----
---- File name: rx_unit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity RxUnit is
port(
clk_i : in std_logic; -- System clock signal
reset_i : in std_logic; -- Reset input (sync)
enable_i : in std_logic; -- Enable input (rate*4)
read_i : in std_logic; -- Received Byte Read
rxd_i : in std_logic; -- RS-232 data input
rxav_o : out std_logic; -- Byte available
datao_o : out std_logic_vector(7 downto 0)); -- Byte received
end entity RxUnit;
architecture Behaviour of RxUnit is
signal r_r : std_logic_vector(7 downto 0); -- Receive register
signal bavail_r : std_logic:='0'; -- Byte received
begin
rxav_o <= bavail_r;
-- Rx Process
RxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Position of the bit in the frame
variable samplecnt : integer range 0 to 3; -- Count from 0 to 3 in each bit
begin
if rising_edge(clk_i) then
if reset_i='1' then
bavail_r <= '0';
bitpos:=0;
else -- reset_i='0'
if read_i='1' then
bavail_r <= '0';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle
bavail_r <= '0';
if rxd_i='0' then -- Start Bit
samplecnt:=0;
bitpos:=1;
end if;
when 10 => -- Stop Bit
bitpos:=0; -- next is idle
bavail_r <= '1'; -- Indicate byte received
datao_o <= r_r; -- Store received byte
when others =>
if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1
r_r(bitpos-2) <= rxd_i; -- Deserialisation
end if;
if samplecnt=3 then -- Increment BitPos on 3
bitpos:=bitpos+1;
end if;
end case;
if samplecnt=3 then
samplecnt:=0;
else
samplecnt:=samplecnt+1;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process RxProc;
end architecture Behaviour;
| bsd-3-clause | 31afc5bdc12f6b4073d994654df20ac2 | 0.303972 | 5.63778 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/zpupkg.vhd | 1 | 15,050 | ------------------------------------------------------------------------------
---- ----
---- ZPU Package ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the package. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpupkg, UART (Package) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zpupkg is
constant OPCODE_W : integer:=8;
-- Debug structure, currently only for the trace module
type zpu_dbgo_t is record
b_inst : std_logic;
opcode : unsigned(OPCODE_W-1 downto 0);
pc : unsigned(31 downto 0);
sp : unsigned(31 downto 0);
stk_a : unsigned(31 downto 0);
stk_b : unsigned(31 downto 0);
end record;
component Trace is
generic(
LOG_FILE : string:="trace.txt"; -- Name of the trace file
ADDR_W : integer:=16; -- Address width
WORD_SIZE : integer:=32); -- 16/32
port(
clk_i : in std_logic;
dbg_i : in zpu_dbgo_t;
stop_i : in std_logic;
busy_i : in std_logic
);
end component Trace;
component ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end component ZPUSmallCore;
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end component ZPUMediumCore;
component Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end component Timer;
component gpio is
port(
clk_i : in std_logic;
reset_i : in std_logic;
--
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned( 0 downto 0);
data_o : out unsigned(31 downto 0);
--
port_in : in std_logic_vector(31 downto 0);
port_out : out std_logic_vector(31 downto 0);
port_dir : out std_logic_vector(31 downto 0)
);
end component gpio;
component ZPUPhiIO is
generic(
BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
ENA_LOG : boolean:=true; -- Enable log
LOG_FILE : string:="log.txt"); -- Name for the log file
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
busy_o : out std_logic; -- I/O is busy
we_i : in std_logic; -- Write Enable
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_i : in unsigned(2 downto 0); -- Address bits 4-2
--
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
br_clk_i : in std_logic; -- UART base clock (enable)
--
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0)
);
end component ZPUPhiIO;
-- Opcode decode constants
-- Note: these are the basic opcodes, always implemented using hardware.
constant OPCODE_IM : unsigned(7 downto 7):="1";
constant OPCODE_STORESP : unsigned(7 downto 5):="010";
constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
constant OPCODE_ADD : unsigned(3 downto 0):="0101";
constant OPCODE_AND : unsigned(3 downto 0):="0110";
constant OPCODE_OR : unsigned(3 downto 0):="0111";
constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
constant OPCODE_NOT : unsigned(3 downto 0):="1001";
constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
constant OPCODE_NOP : unsigned(3 downto 0):="1011";
constant OPCODE_STORE : unsigned(3 downto 0):="1100";
constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
-- The following instructions are emulated in the small version and
-- implemented as hardware in the full version.
-- The constants correpond to the "emulated" instruction number.
-- Enabled by the ENA_LEVEL0 generic:
constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
-- Enabled by the ENA_LEVEL1 generic:
constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
-- Enabled by the ENA_LEVEL2 generic:
constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
-- Enabled by the ENA_LSHR generic:
constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
-- The following opcodes are always emulated.
constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
end package zpupkg;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package UART is
----------------------
-- Very simple UART --
----------------------
component RxUnit is
port(
clk_i : in std_logic; -- System clock signal
reset_i : in std_logic; -- Reset input (sync)
enable_i : in std_logic; -- Enable input (rate*4)
read_i : in std_logic; -- Received Byte Read
rxd_i : in std_logic; -- RS-232 data input
rxav_o : out std_logic; -- Byte available
datao_o : out std_logic_vector(7 downto 0)); -- Byte received
end component RxUnit;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component BRGen is
generic(
COUNT : integer range 0 to 65535);-- Count revolution
port (
clk_i : in std_logic; -- Clock
reset_i : in std_logic; -- Reset input
ce_i : in std_logic; -- Chip Enable
o_o : out std_logic); -- Output
end component BRGen;
end package UART;
| gpl-3.0 | f3d9d8c8cccccce6d82d2ecf46c7bf4f | 0.488602 | 4.070057 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/hello.vhdl | 1 | 66,252 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cdec0c",
3 => x"3a0b0b80",
4 => x"c5e80400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
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2879 => x"00002cf4",
2880 => x"00002cf4",
2881 => x"00002cfc",
2882 => x"00002cfc",
2883 => x"00002d04",
2884 => x"00002d04",
2885 => x"00002d0c",
2886 => x"00002d0c",
2887 => x"00002d14",
2888 => x"00002d14",
2889 => x"00002d1c",
2890 => x"00002d1c",
2891 => x"00002d24",
2892 => x"00002d24",
2893 => x"00002d2c",
2894 => x"00002d2c",
2895 => x"00002d34",
2896 => x"00002d34",
2897 => x"00002d3c",
2898 => x"00002d3c",
2899 => x"00002d44",
2900 => x"00002d44",
2901 => x"00002d4c",
2902 => x"00002d4c",
2903 => x"00002d54",
2904 => x"00002d54",
2905 => x"00002d5c",
2906 => x"00002d5c",
2907 => x"00002d64",
2908 => x"00002d64",
2909 => x"00002d6c",
2910 => x"00002d6c",
2911 => x"00002d74",
2912 => x"00002d74",
2913 => x"00002d7c",
2914 => x"00002d7c",
2915 => x"00002d84",
2916 => x"00002d84",
2917 => x"00002d8c",
2918 => x"00002d8c",
2919 => x"00002d94",
2920 => x"00002d94",
2921 => x"00002d9c",
2922 => x"00002d9c",
2923 => x"00002da4",
2924 => x"00002da4",
2925 => x"00002dac",
2926 => x"00002dac",
2927 => x"00002db4",
2928 => x"00002db4",
2929 => x"00002dbc",
2930 => x"00002dbc",
2931 => x"00002dc4",
2932 => x"00002dc4",
2933 => x"00002dcc",
2934 => x"00002dcc",
2935 => x"00002dd4",
2936 => x"00002dd4",
2937 => x"00002ddc",
2938 => x"00002ddc",
2939 => x"00002de4",
2940 => x"00002de4",
2941 => x"00002dec",
2942 => x"00002dec",
2943 => x"00002df4",
2944 => x"00002df4",
2945 => x"00002dfc",
2946 => x"00002dfc",
2947 => x"00002e04",
2948 => x"00002e04",
2949 => x"00002e0c",
2950 => x"00002e0c",
2951 => x"00002e14",
2952 => x"00002e14",
2953 => x"00002e1c",
2954 => x"00002e1c",
2955 => x"00002e24",
2956 => x"00002e24",
2957 => x"00002e2c",
2958 => x"00002e2c",
2959 => x"00002e34",
2960 => x"00002e34",
2961 => x"00002e3c",
2962 => x"00002e3c",
2963 => x"00002e44",
2964 => x"00002e44",
2965 => x"00002e4c",
2966 => x"00002e4c",
2967 => x"00002e54",
2968 => x"00002e54",
2969 => x"00002e5c",
2970 => x"00002e5c",
2971 => x"00002e64",
2972 => x"00002e64",
2973 => x"00002e6c",
2974 => x"00002e6c",
2975 => x"00002e74",
2976 => x"00002e74",
2977 => x"00002e7c",
2978 => x"00002e7c",
2979 => x"00002e84",
2980 => x"00002e84",
2981 => x"00002e8c",
2982 => x"00002e8c",
2983 => x"00002e94",
2984 => x"00002e94",
2985 => x"00002e9c",
2986 => x"00002e9c",
2987 => x"00002ea4",
2988 => x"00002ea4",
2989 => x"00002eac",
2990 => x"00002eac",
2991 => x"000026dc",
2992 => x"ffffffff",
2993 => x"00000000",
2994 => x"ffffffff",
2995 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | 5fc0de5ea32ccbb662ace3d6e317bc28 | 0.592012 | 2.281169 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/address_decoder.vhdl | 1 | 27,380 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_MISC.all;
ENTITY address_decoder IS
GENERIC
(
low_memory : integer := 1 -- if 0, we assume 8MB SDRAM, if 1, we assume 1MB 'SDRAM'.
);
PORT
(
CLK : IN STD_LOGIC;
-- bus masters - either CPU or antic
-- antic has priority and is slected when ANTIC_FETCH high
CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CPU_FETCH : in std_logic;
CPU_WRITE_N : IN STD_LOGIC;
CPU_WRITE_DATA : in std_logic_vector(7 downto 0);
ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
ANTIC_FETCH : IN STD_LOGIC;
DMA_ADDR : in std_logic_vector(23 downto 0);
DMA_FETCH : in std_logic;
DMA_READ_ENABLE : in std_logic;
DMA_32BIT_WRITE_ENABLE : in std_logic; -- common case
DMA_16BIT_WRITE_ENABLE : in std_logic; -- for sram
DMA_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs
DMA_WRITE_DATA : in std_logic_vector(31 downto 0);
-- sources of data
ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0); -- flash rom
GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
CART_ROM_DATA : in std_logic_Vector(7 downto 0);
-- completion flags
RAM_REQUEST_COMPLETE : IN STD_LOGIC;
ROM_REQUEST_COMPLETE : IN STD_LOGIC;
CART_REQUEST_COMPLETE : IN STD_LOGIC;
-- configuration options
PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
reset_n : in std_logic;
rom_in_ram : in std_logic;
rom_select : in std_logic_vector(5 downto 0);
cart_select : in std_logic_vector(6 downto 0);
cart_activate : in std_logic;
ram_select : in std_logic_vector(2 downto 0);
CART_RD4 : in std_logic;
CART_RD5 : in std_logic;
use_sdram : in std_logic;
-- Memory read mux output
MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
-- Allow us to say we're not ready for a cycle
MEMORY_READY_ANTIC : OUT STD_LOGIC;
MEMORY_READY_DMA : OUT STD_LOGIC;
MEMORY_READY_CPU : out std_logic;
-- Each chip does not have whole address bus, so several are addressed at once
-- For reads not an issue, but for writes we need to only write to a single place!
-- these all take 1 cycle, so fine to leave device selected in general
GTIA_WR_ENABLE : OUT STD_LOGIC;
POKEY_WR_ENABLE : OUT STD_LOGIC;
POKEY2_WR_ENABLE : OUT STD_LOGIC;
ANTIC_WR_ENABLE : OUT STD_LOGIC;
PIA_WR_ENABLE : OUT STD_LOGIC;
PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
RAM_WR_ENABLE : OUT STD_LOGIC;
PBI_WR_ENABLE : OUT STD_LOGIC;
D6_WR_ENABLE : OUT STD_LOGIC;
-- ROM and RAM have extended address busses to allow for bank switching etc.
ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
PBI_ADDR : out std_logic_vector(15 downto 0);
RAM_REQUEST : out std_logic;
ROM_REQUEST : out std_logic;
CART_REQUEST : out std_logic;
CART_S4_n : out std_logic;
CART_S5_n : out std_logic;
CART_CCTL_n : out std_logic;
-- width of access
WIDTH_8bit_ACCESS : out std_logic;
WIDTH_16bit_ACCESS : out std_logic;
WIDTH_32bit_ACCESS : out std_logic;
-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
SDRAM_WRITE_EN : out std_logic;
--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
SDRAM_REQUEST : out std_logic; -- Usual pattern
--SDRAM_REPLY : in std_logic; -- This matches the request once complete
SDRAM_REQUEST_COMPLETE : in std_logic;
SDRAM_DATA : in std_logic_vector(31 downto 0);
WRITE_DATA : out std_logic_vector(31 downto 0)
);
END address_decoder;
ARCHITECTURE vhdl OF address_decoder IS
signal ADDR_next : std_logic_vector(23 downto 0);
signal ADDR_reg : std_logic_vector(23 downto 0);
signal DATA_WRITE_next : std_logic_vector(31 downto 0);
signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
signal width_8bit_next : std_logic;
signal width_16bit_next : std_logic;
signal width_32bit_next : std_logic;
signal write_enable_next : std_logic;
signal width_8bit_reg : std_logic;
signal width_16bit_reg : std_logic;
signal width_32bit_reg : std_logic;
signal write_enable_reg : std_logic;
signal request_complete : std_logic;
signal notify_antic : std_logic;
signal notify_DMA : std_logic;
signal notify_cpu : std_logic;
signal start_request : std_logic;
signal extended_access_addr : std_logic;
signal extended_access_cpu_or_antic : std_logic;
signal extended_access_antic : std_logic;
signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
signal extended_self_test : std_logic;
signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
signal state_next : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(1 downto 0);
constant state_idle : std_logic_vector(1 downto 0) := "00";
constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
constant state_waiting_DMA : std_logic_vector(1 downto 0) := "10";
constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
signal ram_chip_select : std_logic;
signal sdram_chip_select : std_logic;
-- signal sdram_request_next : std_logic;
-- signal sdram_request_reg : std_logic;
-- signal SDRAM_REQUEST_COMPLETE : std_logic;
signal fetch_priority : std_logic_vector(2 downto 0);
signal fetch_wait_next : std_logic_vector(8 downto 0);
signal fetch_wait_reg : std_logic_vector(8 downto 0);
signal antic_fetch_real_next : std_logic;
signal antic_fetch_real_reg : std_logic;
signal cpu_fetch_real_next : std_logic;
signal cpu_fetch_real_reg : std_logic;
signal SDRAM_CART_ADDR : std_logic_vector(22 downto 0);
signal SDRAM_BASIC_ROM_ADDR : std_logic_vector(22 downto 0);
signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
signal sdram_only_bank : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n='0') then
addr_reg <= (others=>'0');
state_reg <= state_idle;
width_8bit_reg <= '0';
width_16bit_reg <= '0';
width_32bit_reg <= '0';
write_enable_reg <= '0';
data_write_reg <= (others=> '0');
--sdram_request_reg <= '0';
fetch_wait_reg <= (others=>'0');
cpu_fetch_real_reg <= '0';
antic_fetch_real_reg <= '0';
elsif (clk'event and clk='1') then
addr_reg <= addr_next;
state_reg <= state_next;
width_8bit_reg <= width_8bit_next;
width_16bit_reg <= width_16bit_next;
width_32bit_reg <= width_32bit_next;
write_enable_reg <= write_enable_next;
data_write_reg <= data_WRITE_next;
--sdram_request_reg <= sdram_request_next;
fetch_wait_reg <= fetch_wait_next;
cpu_fetch_real_reg <= cpu_fetch_real_next;
antic_fetch_real_reg <= antic_fetch_real_next;
end if;
end process;
-- ANTIC FETCH
-- concept
-- bus master sends request - antic or cpu
-- antic has priority
-- cpu may be idle
-- once request complete MEMORY_READY is set
-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
-- so
-- memory_ready <= device_ready;
-- problem
-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
-- state machine
-- state machine impl
fetch_priority <= ANTIC_FETCH&DMA_FETCH&CPU_FETCH;
process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, DMA_addr, cpu_addr, request_complete, DMA_8bit_write_enable,DMA_16bit_write_enable,DMA_32bit_write_enable,DMA_read_enable, cpu_write_n, CPU_WRITE_DATA, DMA_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
begin
start_request <= '0';
notify_antic <= '0';
notify_cpu <= '0';
notify_DMA <= '0';
state_next <= state_reg;
fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
addr_next <= addr_reg;
data_WRITE_next <= data_WRITE_reg;
width_8bit_next <= width_8bit_reg;
width_16bit_next <= width_16bit_reg;
width_32bit_next <= width_32bit_reg;
write_enable_next <= write_enable_reg;
antic_fetch_real_next <= antic_fetch_real_reg;
cpu_fetch_real_next <= cpu_fetch_real_reg;
case state_reg is
when state_idle =>
fetch_wait_next <= (others=>'0');
write_enable_next <= '0';
width_8bit_next <= '0';
width_16bit_next <= '0';
width_32bit_next <= '0';
data_WRITE_next <= (others => '0');
addr_next <= DMA_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);
case fetch_priority is
when "100"|"101"|"110"|"111" => -- antic wins
start_request <= '1';
addr_next <= "00000000"&antic_ADDR;
width_8bit_next <= '1';
if (request_complete = '1') then
notify_antic <= '1';
else
state_next <= state_waiting_antic;
end if;
antic_fetch_real_next <= '1';
when "010"|"011" => -- DMA wins (DMA usually accesses own ROM memory - this is NOT a DMA_fetch)
-- TODO, lower priority than 6502, except on first request in block...
start_request <= '1';
addr_next <= DMA_ADDR;
data_WRITE_next <= DMA_WRITE_DATA;
width_8bit_next <= DMA_8BIT_WRITE_ENABLE or (DMA_READ_ENABLE and (DMA_addr(0) or DMA_addr(1)));
width_16bit_next <= DMA_16BIT_WRITE_ENABLE;
width_32bit_next <= DMA_32BIT_WRITE_ENABLE or (DMA_READ_ENABLE and not(DMA_addr(0) or DMA_addr(1))); -- narrower devices just return 8 bits on read
write_enable_next <= not(DMA_READ_ENABLE);
if (request_complete = '1') then
notify_DMA <= '1';
else
state_next <= state_waiting_DMA;
end if;
when "001" => -- 6502 wins
start_request <= '1';
addr_next <= "00000000"&cpu_ADDR;
data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
width_8bit_next <= '1';
write_enable_next <= not(cpu_WRITE_N);
if (request_complete = '1') then
notify_cpu <= '1';
else
state_next <= state_waiting_cpu;
end if;
cpu_fetch_real_next <= '1';
when "000" =>
-- no requests
when others =>
-- nop
end case;
when state_waiting_antic =>
if (request_complete = '1') then
notify_antic <= '1';
state_next <= state_idle;
end if;
when state_waiting_DMA =>
if (request_complete = '1') then
notify_DMA <= '1';
state_next <= state_idle;
end if;
when state_waiting_cpu =>
if (request_complete = '1') then
notify_cpu <= '1';
state_next <= state_idle;
end if;
when others =>
-- NOP
end case;
end process;
-- output
MEMORY_READY_ANTIC <= notify_antic;
MEMORY_READY_DMA <= notify_DMA;
MEMORY_READY_CPU <= notify_cpu;
RAM_REQUEST <= ram_chip_select;
SDRAM_REQUEST <= sdram_chip_select;
--SDRAM_REQUEST <= sdram_request_next;
SDRAM_READ_EN <= not(write_enable_next);
SDRAM_WRITE_EN <= write_enable_next;
WIDTH_8bit_ACCESS <= width_8bit_next;
WIDTH_16bit_ACCESS <= width_16bit_next;
WIDTH_32bit_ACCESS <= width_32bit_next;
WRITE_DATA <= DATA_WRITE_next;
-- a little sdram glue - move to sdram wrapper? TODO
--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
--sdram_request_next <= sdram_request_reg xor sdram_chip_select;
-- Calculate which memory area to use
extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
extended_access_either <= extended_access_addr and not(portb(4));
sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
begin
extended_bank <= "0000000"&addr_next(15 downto 14);
extended_self_test <= '1';
case ram_select is
when "000" => -- 64k
-- default
when "001" => -- 128k
if (extended_access_cpu_or_antic='1') then
extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
end if;
when "010" => -- 320k compy shop
if (extended_access_cpu_or_antic='1') then
extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
extended_self_test <= '0';
end if;
when "011" => -- 320k rambo
if (extended_access_either='1')then
extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
end if;
when "100" => -- 576k compy shop
if (extended_access_cpu_or_antic='1') then
extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
extended_self_test <= '0';
end if;
when "101" => -- 576k rambo
if (extended_access_either='1') then
extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
end if;
when "110" => -- 1088k rambo
if (extended_access_either='1') then
extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
extended_self_test <= '0';
end if;
when "111" => -- 4MB!
if (extended_access_addr='1') then
extended_bank(7 downto 0) <= portb(7 downto 0);
extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
extended_self_test <= and_reduce(portb(6 downto 4)); -- which means self-test is in the middle of half the banks - euuugh, oh well!
end if;
when others =>
-- TODO - portc!
end case;
end process;
gen_normal_memory : if low_memory=0 generate
-- SRAM memory map (512k)
-- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
-- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
-- SDRAM memory map (8MB)
-- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
-- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
-- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
-- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
-- SCRATCH - 4MB+64k-5MB
-- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
-- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
-- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
end generate;
gen_low_memory : if low_memory=1 generate
-- SRAM memory map (1024k) for Aeon Lite
SDRAM_CART_ADDR <= "000" & "111" & cart_select(3 downto 0) & "0000000000000";
SDRAM_BASIC_ROM_ADDR <= "000" & "110" & "00000000000000000";
SDRAM_OS_ROM_ADDR <= "000" & "110" & rom_select(2 downto 0) & "00000000000000";
end generate;
process(
-- address and writing absolutely points us at a device
ADDR_next,WRITE_enable_next,
-- except for these additional special address bits
portb,
antic_fetch,
rom_select,
ram_select,cart_rd4,cart_rd5,
use_sdram,
-- input data from n sources
GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
-- input data from n sources complete?
-- hardware regs take 1 cycle, so always complete
ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
-- on new access this is set - we must select the appropriate device - for this cycle only
start_request,
rom_in_ram,
-- SDRAM base addresses
extended_self_test,extended_bank,sdram_only_bank,
SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
)
begin
MEMORY_DATA <= (others => '1');
ROM_ADDR <= (others=>'0');
RAM_ADDR <= addr_next(18 downto 0);
SDRAM_ADDR <= addr_next(22 downto 0);
PBI_ADDR <= ADDR_next(15 downto 0);
request_complete <= '0';
GTIA_WR_ENABLE <= '0';
POKEY_WR_ENABLE <= '0';
POKEY2_WR_ENABLE <= '0';
ANTIC_WR_ENABLE <= '0';
PIA_WR_ENABLE <= '0';
PIA_RD_ENABLE <= '0';
PBI_WR_ENABLE <= '0';
D6_WR_ENABLE <= '0';
RAM_WR_ENABLE <= write_enable_next;
SDRAM_WRITE_EN <= write_enable_next;
CART_S4_n <= '1';
CART_S5_n <= '1';
CART_CCTL_n <= '1';
rom_request <= '0';
cart_request <= '0';
ram_chip_select <= '0';
sdram_chip_select <= '0';
-- if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
SDRAM_ADDR(22 downto 14) <= extended_bank;
RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
if ((use_sdram or sdram_only_bank)='1') then
MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
sdram_chip_select <= start_request;
request_complete <= sdram_request_COMPLETE;
else
MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
ram_chip_select <= start_request;
request_complete <= ram_request_COMPLETE;
end if;
case addr_next(15 downto 8) is
-- GTIA
when X"D0" =>
GTIA_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= GTIA_DATA;
MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
request_complete <= '1';
sdram_chip_select <= '0';
ram_chip_select <= '0';
-- POKEY
when X"D2" =>
if (addr_next(4) = '0') then
POKEY_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= POKEY_DATA;
MEMORY_DATA(15 downto 8) <= CACHE_POKEY_DATA;
else
POKEY2_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
end if;
request_complete <= '1';
sdram_chip_select <= '0';
ram_chip_select <= '0';
-- PIA
when X"D3" =>
PIA_WR_ENABLE <= write_enable_next;
PIA_RD_ENABLE <= '1';
MEMORY_DATA(7 downto 0) <= PIA_DATA;
request_complete <= '1';
sdram_chip_select <= '0';
ram_chip_select <= '0';
-- ANTIC
when X"D4" =>
ANTIC_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
request_complete <= '1';
sdram_chip_select <= '0';
ram_chip_select <= '0';
-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
when X"D5" =>
sdram_chip_select <= '0';
ram_chip_select <= '0';
if ((CART_RD4 or CART_RD5) = '1') then
PBI_WR_ENABLE <= write_enable_next;
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
cart_request <= start_request;
CART_CCTL_n <= '0';
request_complete <= CART_REQUEST_COMPLETE;
else
MEMORY_DATA(7 downto 0) <= X"FF";
request_complete <= '1';
end if;
when X"D6" =>
D6_WR_ENABLE <= write_enable_next;
-- TODO - should this still have RAM with covox here?
-- SELF TEST ROM 0x5000->0x57ff and XE RAM
when
X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
sdram_chip_select <= '0';
ram_chip_select <= '0';
if (rom_in_ram = '1') then
MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
else
MEMORY_DATA(7 downto 0) <= ROM_DATA;
end if;
if (write_enable_next = '1') then
request_complete <= '1';
else
if (rom_in_ram = '1') then
request_complete <= sdram_request_COMPLETE;
sdram_chip_select <= start_request;
else
request_complete <= rom_request_COMPLETE;
rom_request <= start_request;
end if;
end if;
--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
end if;
-- 0x80 cart
when
X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
if (cart_rd4 = '1') then
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
rom_request <= start_request;
CART_S4_n <= '0';
request_complete <= CART_REQUEST_COMPLETE;
sdram_chip_select <= '0';
ram_chip_select <= '0';
end if;
-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
when
X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
if (cart_rd5 = '1') then
MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
cart_request <= start_request;
CART_S5_n <= '0';
request_complete <= CART_REQUEST_COMPLETE;
sdram_chip_select <= '0';
ram_chip_select <= '0';
else
if (portb(1) = '0') then
sdram_chip_select <= '0';
ram_chip_select <= '0';
--request_complete <= ROM_REQUEST_COMPLETE;
--MEMORY_DATA(7 downto 0) <= ROM_DATA;
--rom_request <= start_request;
if (rom_in_ram = '1') then
MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
else
MEMORY_DATA(7 downto 0) <= ROM_DATA;
end if;
if (write_enable_next = '1') then
request_complete <= '1';
else
if (rom_in_ram = '1') then
request_complete <= sdram_request_COMPLETE;
sdram_chip_select <= start_request;
else
request_complete <= rom_request_COMPLETE;
rom_request <= start_request;
end if;
end if;
ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k
end if;
end if;
-- OS ROM 0xc00->0xcff
-- OS ROM d800->0xfff
when
X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
if (portb(0) = '1') then
sdram_chip_select <= '0';
ram_chip_select <= '0';
--request_complete <= ROM_REQUEST_COMPLETE;
--MEMORY_DATA(7 downto 0) <= ROM_DATA;
--rom_request <= start_request;
if (rom_in_ram = '1') then
MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
else
MEMORY_DATA(7 downto 0) <= ROM_DATA;
end if;
if (write_enable_next = '1') then
request_complete <= '1';
else
if (rom_in_ram = '1') then
request_complete <= sdram_request_COMPLETE;
sdram_chip_select <= start_request;
else
request_complete <= rom_request_COMPLETE;
rom_request <= start_request;
end if;
end if;
ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
end if;
when others =>
end case;
else
sdram_chip_select <= '0';
ram_chip_select <= '0';
case addr_next(23 downto 21) is
when "000" =>
-- internal area for zpu, never happens!
when "001" => -- sram, 512K
MEMORY_DATA(15 downto 0) <= RAM_DATA;
ram_chip_select <= start_request;
request_complete <= ram_request_COMPLETE;
RAM_ADDR <= addr_next(18 downto 0);
when "010"|"011" => -- flash rom, 4MB
request_complete <= ROM_REQUEST_COMPLETE;
MEMORY_DATA(7 downto 0) <= ROM_DATA;
rom_request <= start_request;
ROM_ADDR <= addr_next(21 downto 0);
when "100"|"101"|"110"|"111" => -- sdram, 8MB
MEMORY_DATA <= SDRAM_DATA;
sdram_chip_select <= start_request;
request_complete <= sdram_request_COMPLETE;
SDRAM_ADDR <= addr_next(22 downto 0);
when others =>
-- NOP
end case;
end if;
-- case addr_next(15 downto 0) is
-- when X"FFFC" =>
-- MEMORY_DATA(7 downto 0) <= X"00";
-- when X"FFFD" =>
-- MEMORY_DATA(7 downto 0) <= X"06";
-- when X"0600" => --JSR 0610
-- MEMORY_DATA(7 downto 0) <= X"20";
-- when X"0601" =>
-- MEMORY_DATA(7 downto 0) <= X"10";
-- when X"0602" =>
-- MEMORY_DATA(7 downto 0) <= X"06";
-- when X"0603" => --JMP
-- MEMORY_DATA(7 downto 0) <= X"4C";
-- when X"0604" =>
-- MEMORY_DATA(7 downto 0) <= X"00";
-- when X"0605" =>
-- MEMORY_DATA(7 downto 0) <= X"06";
-- when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
-- MEMORY_DATA(7 downto 0) <= X"AD";
-- when X"0611" =>
-- MEMORY_DATA(7 downto 0) <= X"0A";
-- when X"0612" =>
-- MEMORY_DATA(7 downto 0) <= X"D2";
-- when X"0613" =>
-- MEMORY_DATA(7 downto 0) <= X"85";
-- when X"0614" =>
-- MEMORY_DATA(7 downto 0) <= X"10";
-- when X"0615" =>
-- MEMORY_DATA(7 downto 0) <= X"44";
-- when X"0616" =>
-- MEMORY_DATA(7 downto 0) <= X"10";
-- when X"0617" =>
-- MEMORY_DATA(7 downto 0) <= X"60";
-- when others =>
-- end case;
end process;
END vhdl;
| gpl-3.0 | 89353e31a7892a32ab5f4bae7c8327b8 | 0.609569 | 2.855057 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/t80-latest/T80_MCode.vhd | 1 | 53,999 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RLD <= '1';
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RRD <= '1';
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
-- note B is decremented AFTER being put on the bus
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
--IncDec_16 <= "0010";
IncDec_16 <= "0110";
else
--IncDec_16 <= "1010";
IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
-- note B is decremented BEFORE being put on the bus.
-- mikej fix for hl inc
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- mikej
else
IncDec_16 <= "1110"; -- mikej
end if;
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 8ac96798219a1ccde85d8ced55a917a2 | 0.508954 | 3.046144 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/internalromram.vhd | 1 | 3,597 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY internalromram IS
GENERIC
(
internal_rom : integer := 1;
internal_ram : integer := 16384
);
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
ROM_REQUEST_COMPLETE : out STD_LOGIC;
ROM_REQUEST : in std_logic;
ROM_DATA : out std_logic_vector(7 downto 0);
RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
RAM_WR_ENABLE : in std_logic;
RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RAM_REQUEST_COMPLETE : out STD_LOGIC;
RAM_REQUEST : in std_logic;
RAM_DATA : out std_logic_vector(7 downto 0)
);
END internalromram;
architecture vhdl of internalromram is
signal rom_request_reg : std_logic;
signal ram_request_reg : std_logic;
signal ROM16_DATA : std_logic_vector(7 downto 0);
signal ROM8_DATA : std_logic_vector(7 downto 0);
signal ROM2_DATA : std_logic_vector(7 downto 0);
signal BASIC_DATA : std_logic_vector(7 downto 0);
begin
process(clock,reset_n)
begin
if (reset_n ='0') then
rom_request_reg <= '0';
ram_request_reg <= '0';
elsif (clock'event and clock='1') then
rom_request_reg <= rom_request;
ram_request_reg <= ram_request;
end if;
end process;
gen_internal_os_b : if internal_rom=3 generate
-- d800 to dfff (2k)
rom2 : entity work.os2
PORT MAP(clock => clock,
address => rom_addr(10 downto 0),
q => ROM2_data
);
-- e000 to ffff (8k)
rom10 : entity work.os8
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => ROM8_data
);
process(rom_addr)
begin
case rom_addr(13 downto 11) is
when "011" =>
ROM_DATA <= ROM2_data;
when "100"|"101"|"110"|"111" =>
ROM_DATA <= ROM8_data;
when others=>
ROM_DATA <= x"ff";
end case;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os_loop : if internal_rom=2 generate
rom16a : entity work.os16_loop
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
ROM_DATA <= ROM16_DATA;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os : if internal_rom=1 generate
rom16a : entity work.os16
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
basic1 : entity work.basic
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => BASIC_data
);
process(rom16_data,basic_data, rom_addr(15 downto 0))
begin
ROM_DATA <= ROM16_DATA;
if (rom_addr(15)='1') then
ROM_DATA <= BASIC_DATA;
end if;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_no_internal_os : if internal_rom=0 generate
ROM16_data <= (others=>'0');
rom_request_complete <= '0';
end generate;
gen_internal_ram: if internal_ram>0 generate
ramint1 : entity work.generic_ram_infer
generic map
(
ADDRESS_WIDTH => 19,
SPACE => internal_ram,
DATA_WIDTH =>8
)
PORT MAP(clock => clock,
address => ram_addr,
data => ram_data_in(7 downto 0),
we => RAM_WR_ENABLE,
q => ram_data
);
ram_request_complete <= ram_request_reg;
end generate;
gen_no_internal_ram : if internal_ram=0 generate
ram_request_complete <='1';
ram_data <= (others=>'1');
end generate;
end vhdl;
| gpl-3.0 | 514400c8ead20e5a44765c82cd64151a | 0.604671 | 3.048305 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/zpucore.vhd | 1 | 6,750 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
ENTITY zpucore IS
GENERIC
(
platform : integer := 1; -- So ROM can detect which type of system...
spi_clock_div : integer := 4 -- see notes on zpu_config_regs
);
PORT
(
-- standard...
CLK : in std_logic;
RESET_N : in std_logic;
-- dma bus master (with many waitstates...)
ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0);
ZPU_DATA_OUT : out std_logic_vector(31 downto 0);
ZPU_FETCH : out std_logic;
ZPU_32BIT_WRITE_ENABLE : out std_logic;
ZPU_16BIT_WRITE_ENABLE : out std_logic;
ZPU_8BIT_WRITE_ENABLE : out std_logic;
ZPU_READ_ENABLE : out std_logic;
ZPU_MEMORY_READY : in std_logic;
ZPU_MEMORY_DATA : in std_logic_vector(31 downto 0);
-- rom bus master
-- data on next cycle after addr
ZPU_ADDR_ROM : out std_logic_vector(15 downto 0);
ZPU_ROM_DATA : in std_logic_vector(31 downto 0);
ZPU_ROM_WREN : out std_logic;
-- spi master
-- Too painful to bit bang spi from zpu, so we have a hardware master in here
ZPU_SD_DAT0 : IN STD_LOGIC;
ZPU_SD_CLK : OUT STD_LOGIC;
ZPU_SD_CMD : OUT STD_LOGIC;
ZPU_SD_DAT3 : OUT STD_LOGIC;
-- SIO
-- Ditto for speaking to Atari, we have a built in Pokey
ZPU_POKEY_ENABLE : in std_logic; -- if run at 1.79MHz we can use standard dividers...
ZPU_SIO_TXD : out std_logic;
ZPU_SIO_RXD : in std_logic;
ZPU_SIO_COMMAND : in std_logic;
-- external control
-- switches etc. sector DMA blah blah.
ZPU_IN1 : in std_logic_vector(31 downto 0);
ZPU_IN2 : in std_logic_vector(31 downto 0);
ZPU_IN3 : in std_logic_vector(31 downto 0);
ZPU_IN4 : in std_logic_vector(31 downto 0);
-- ouputs - e.g. Atari system control, halt, throttle, rom select
ZPU_OUT1 : out std_logic_vector(31 downto 0);
ZPU_OUT2 : out std_logic_vector(31 downto 0);
ZPU_OUT3 : out std_logic_vector(31 downto 0);
ZPU_OUT4 : out std_logic_vector(31 downto 0)
);
END zpucore;
ARCHITECTURE vhdl OF zpucore IS
signal ZPU_PAUSE : std_logic;
signal ZPU_RESET : std_logic;
signal ZPU_DO : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM_RAM : std_logic_vector(15 downto 0);
signal ZPU_RAM_DATA : std_logic_vector(31 downto 0);
signal ZPU_STACK_WRITE : std_logic_vector(3 downto 0);
signal ZPU_CONFIG_DO : std_logic_vector(31 downto 0);
signal ZPU_CONFIG_WRITE_ENABLE : std_logic;
signal ZPU_SD_DMA_ADDR : std_logic_vector(15 downto 0);
signal ZPU_SD_DMA_DATA : std_logic_vector(7 downto 0);
signal ZPU_SD_DMA_WRITE : std_logic;
signal ZPU_SD_DMA_WRITE_BITS : std_logic_vector(3 downto 0);
signal ZPU_ADDR_ROM_RAM_DMA : std_logic_vector(15 downto 0);
signal ZPU_DO_DMA : std_logic_vector(31 downto 0);
signal ZPU_STACK_WRITE_DMA : std_logic_vector(3 downto 0);
BEGIN
ZPU_RESET <= not(reset_n);
zpu_and_glue : entity work.zpu_glue
PORT MAP(CLK => CLK,
RESET => ZPU_RESET,
PAUSE => ZPU_PAUSE,
MEMORY_READY => ZPU_MEMORY_READY,
ZPU_CONFIG_DI => ZPU_CONFIG_DO,
ZPU_DI => ZPU_MEMORY_DATA,
ZPU_RAM_DI => ZPU_RAM_DATA,
ZPU_ROM_DI => ZPU_ROM_DATA,
MEMORY_FETCH => ZPU_FETCH,
ZPU_READ_ENABLE => ZPU_READ_ENABLE,
ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
ZPU_DO => ZPU_DO,
ZPU_STACK_WRITE => ZPU_STACK_WRITE,
ZPU_ROM_WREN => ZPU_ROM_WREN);
config_regs : entity work.zpu_config_regs
GENERIC MAP (
platform => platform,
spi_clock_div => spi_clock_div
)
PORT MAP (
CLK => CLK,
RESET_N => RESET_N,
POKEY_ENABLE => ZPU_POKEY_ENABLE,
ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
CPU_DATA_IN => ZPU_DO,
WR_EN => ZPU_CONFIG_WRITE_ENABLE,
IN1 => ZPU_IN1,
IN2 => ZPU_IN2,
IN3 => ZPU_IN3,
IN4 => ZPU_IN4,
OUT1 => ZPU_OUT1,
OUT2 => ZPU_OUT2,
OUT3 => ZPU_OUT3,
OUT4 => ZPU_OUT4,
SDCARD_DAT => ZPU_SD_DAT0,
SDCARD_CLK => ZPU_SD_CLK,
SDCARD_CMD => ZPU_SD_CMD,
SDCARD_DAT3 => ZPU_SD_DAT3,
SIO_DATA_IN => ZPU_SIO_TXD,
SIO_DATA_OUT => ZPU_SIO_RXD,
SIO_COMMAND => ZPU_SIO_COMMAND,
sd_addr => ZPU_SD_DMA_ADDR,
sd_data => ZPU_SD_DMA_DATA,
sd_write => ZPU_SD_DMA_WRITE,
DATA_OUT => ZPU_CONFIG_DO,
PAUSE_ZPU => ZPU_PAUSE
);
decode_addr1 : entity work.complete_address_decoder
generic map(width=>2)
port map (addr_in=>ZPU_SD_DMA_ADDR(1 downto 0), addr_decoded=>ZPU_SD_DMA_WRITE_BITS);
process(ZPU_DO, ZPU_ADDR_ROM_RAM, ZPU_STACK_WRITE, ZPU_SD_DMA_ADDR, ZPU_SD_DMA_DATA, ZPU_SD_DMA_WRITE, ZPU_SD_DMA_WRITE_BITS)
begin
ZPU_DO_DMA <= ZPU_DO;
ZPU_ADDR_ROM_RAM_DMA <= ZPU_ADDR_ROM_RAM;
ZPU_STACK_WRITE_DMA <= ZPU_STACK_WRITE;
if (ZPU_SD_DMA_WRITE = '1') then
ZPU_DO_DMA <= ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA&ZPU_SD_DMA_DATA;
ZPU_ADDR_ROM_RAM_DMA <= ZPU_SD_DMA_ADDR(15 downto 2)&"00";
ZPU_STACK_WRITE_DMA <= ZPU_SD_DMA_WRITE_BITS(0)&ZPU_SD_DMA_WRITE_BITS(1)&ZPU_SD_DMA_WRITE_BITS(2)&ZPU_SD_DMA_WRITE_BITS(3);
end if;
end process;
ram_31_24 : entity work.generic_ram_infer
GENERIC MAP
(
ADDRESS_WIDTH => 10,
SPACE => 1024,
DATA_WIDTH => 8
)
PORT MAP
(
we => ZPU_STACK_WRITE_DMA(3),
clock => CLK,
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(31 DOWNTO 24),
q => ZPU_RAM_DATA(31 DOWNTO 24)
);
ram23_16 : entity work.generic_ram_infer
GENERIC MAP
(
ADDRESS_WIDTH => 10,
SPACE => 1024,
DATA_WIDTH => 8
)
PORT MAP
(
we => ZPU_STACK_WRITE_DMA(2),
clock => CLK,
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(23 DOWNTO 16),
q => ZPU_RAM_DATA(23 DOWNTO 16)
);
ram_15_8 : entity work.generic_ram_infer
GENERIC MAP
(
ADDRESS_WIDTH => 10,
SPACE => 1024,
DATA_WIDTH => 8
)
PORT MAP
(
we => ZPU_STACK_WRITE_DMA(1),
clock => CLK,
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(15 DOWNTO 8),
q => ZPU_RAM_DATA(15 DOWNTO 8)
);
ram_7_0 : entity work.generic_ram_infer
GENERIC MAP
(
ADDRESS_WIDTH => 10,
SPACE => 1024,
DATA_WIDTH => 8
)
PORT MAP
(
we => ZPU_STACK_WRITE_DMA(0),
clock => CLK,
address => ZPU_ADDR_ROM_RAM_DMA(11 DOWNTO 2),
data => ZPU_DO_DMA(7 DOWNTO 0),
q => ZPU_RAM_DATA(7 DOWNTO 0)
);
-- OUTPUT
ZPU_ADDR_ROM <= ZPU_ADDR_ROM_RAM;
ZPU_DATA_OUT <= ZPU_DO;
end vhdl;
| gpl-3.0 | 30ff522e072a98b0ad77d12c29a051e5 | 0.646074 | 2.565564 | false | false | false | false |
sonologic/gmzpu | vhdl/gmzpu/zwc.vhdl | 1 | 5,205 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone.all;
library zetaio;
use zetaio.pic.all;
use zetaio.tim.all;
entity zwc is
generic (
DATA_WIDTH : natural:=32;
ADR_WIDTH : natural:=16;
CS_WIDTH : natural:=4
);
port (
-- SYSCON
clk_i : in std_logic;
rst_i : in std_logic;
-- zpu interface (non wishbone signal)
busy_o : out std_logic; -- controller busy
ready_o : out std_logic; -- read request ready
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
re_i : in std_logic;
we_i : in std_logic;
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
int_i : in std_logic; -- external int
-- interrupts
-- wishbone controller int
irq_o : out std_logic
);
end entity zwc;
architecture rtl of zwc is
-- wishbone bus
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_adr_o : unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
signal wb_cyc_o : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_lock_o : std_logic;
signal wb_rty_i : std_logic;
signal wb_sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_tga_o : unsigned(ADR_WIDTH-CS_WIDTH-2 downto 0);
signal wb_tgc_o : unsigned(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we_o : std_logic;
-- interrupt lines
signal int_ctrl_r : std_logic;
signal int_pic_r : std_logic;
signal int_timer_r : std_logic;
signal int_r : std_logic_vector(DATA_WIDTH-1 downto 0);
-- PIC interrupt mapping
constant PIC_INT_EXT : natural:=0;
constant PIC_INT_ZWC : natural:=1;
constant PIC_INT_TIMER : natural:=2;
constant PIC_INT_UNUSED : natural:=3;
-- devices on the bus
constant WB_CS_PIC : natural:=0;
constant WB_CS_TIM : natural:=1;
begin
-- unused interrupt lines
int_r(DATA_WIDTH-1 downto PIC_INT_UNUSED) <= (others => '0');
-- external interrupt line
int_r(PIC_INT_EXT) <= int_i;
-- master
controller: zwishbone_controller
generic map(
DATA_WIDTH => DATA_WIDTH, ADR_WIDTH => ADR_WIDTH, CS_WIDTH => CS_WIDTH
)
port map(
-- syscon
clk_i => clk_i, rst_i => rst_i, busy_o => busy_o, ready_o => ready_o,
-- interrupt
irq_o => int_r(PIC_INT_ZWC),
adr_i => adr_i, re_i => re_i, we_i => we_i, dat_i => dat_i, dat_o => dat_o,
-- chip select
wb_stb_o => wb_stb_o,
-- wishbone bus (master)
wb_dat_i => wb_dat_i, wb_dat_o => wb_dat_o,
wb_tgd_i => wb_tgd_i, wb_tgd_o => wb_tgd_o,
wb_ack_i => wb_ack_i, wb_adr_o => wb_adr_o,
wb_cyc_o => wb_cyc_o, wb_stall_i => wb_stall_i, wb_err_i => wb_err_i, wb_lock_o => wb_lock_o, wb_rty_i => wb_rty_i,
wb_sel_o => wb_sel_o,
wb_tga_o => wb_tga_o,
wb_tgc_o => wb_tgc_o,
wb_we_o => wb_we_o
);
-- slave 0: PIC
pic: interrupt_controller
generic map(ADR_WIDTH => ADR_WIDTH-CS_WIDTH-1, DATA_WIDTH => DATA_WIDTH, N_BANKS => 1)
port map(
-- syscon
rst_i => rst_i, clk_i => clk_i,
-- interrupt
int_i => int_r,
irq_o => irq_o,
-- chip select
wb_stb_i => wb_stb_o(WB_CS_PIC),
-- wishbone
wb_dat_o => wb_dat_i, wb_dat_i => wb_dat_o, wb_tgd_o => wb_tgd_i, wb_tgd_i => wb_tgd_o,
wb_ack_o => wb_ack_i, wb_adr_i => wb_adr_o, wb_cyc_i => wb_cyc_o,
wb_stall_o => wb_stall_i, wb_err_o => wb_err_i, wb_lock_i => wb_lock_o, wb_rty_o => wb_rty_i,
wb_sel_i => wb_sel_o,
wb_tga_i => wb_tga_o, wb_tgc_i => wb_tgc_o,
wb_we_i => wb_we_o
);
-- slave 1: TIMER
timrs: timers
generic map(DATA_WIDTH => DATA_WIDTH, ADR_WIDTH => ADR_WIDTH-CS_WIDTH-1, N_TIMERS => 4)
port map(
-- syscon
rst_i => rst_i, clk_i => clk_i,
-- interrupt
irq_o => int_r(PIC_INT_TIMER),
-- chip select
wb_stb_i => wb_stb_o(WB_CS_TIM),
-- wishbone
wb_dat_o => wb_dat_i, wb_dat_i => wb_dat_o, wb_tgd_o => wb_tgd_i, wb_tgd_i => wb_tgd_o,
wb_ack_o => wb_ack_i, wb_adr_i => wb_adr_o, wb_cyc_i => wb_cyc_o,
wb_stall_o => wb_stall_i, wb_err_o => wb_err_i, wb_lock_i => wb_lock_o, wb_rty_o => wb_rty_i,
wb_sel_i => wb_sel_o,
wb_tga_i => wb_tga_o, wb_tgc_i => wb_tgc_o,
wb_we_i => wb_we_o
);
end architecture rtl;
| bsd-3-clause | a9f6523801aaa2a1d35f2eb7a8815a09 | 0.509126 | 2.974286 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/sdram_statemachine.vhdl | 1 | 21,602 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY sdram_statemachine IS
generic
(
ADDRESS_WIDTH : natural := 22;
ROW_WIDTH : natural := 12;
AP_BIT : natural := 10;
COLUMN_WIDTH : natural := 8
);
PORT
(
CLK_SYSTEM : IN STD_LOGIC;
CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
RESET_N : in STD_LOGIC;
-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
DATA_IN : in std_logic_vector(31 downto 0);
ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
WRITE_EN : in std_logic;
REQUEST : in std_logic; -- set true to request
BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
REFRESH : in std_logic;
COMPLETE : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
-- sdram itself
SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_BA0 : out std_logic;
SDRAM_BA1 : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_N : out std_logic;
SDRAM_RAS_N : out std_logic;
SDRAM_CAS_N : out std_logic;
SDRAM_WE_N : out std_logic;
SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
SDRAM_udqm : out std_logic;
reset_client_n : out std_logic
);
END sdram_statemachine;
ARCHITECTURE vhdl OF sdram_statemachine IS
function repeat(N: natural; B: std_logic)
return std_logic_vector
is
variable result: std_logic_vector(1 to N);
begin
for i in 1 to N loop
result(i) := B;
end loop;
return result;
end;
-- bits are: CS_n, RAS_n, CAS_n,WE_n
constant sdram_command_inhibit : std_logic_vector(3 downto 0) := "1000";
constant sdram_command_no_operation : std_logic_vector(3 downto 0) := "0111";
constant sdram_command_device_burst_stop : std_logic_vector(3 downto 0) := "0110";
constant sdram_command_read : std_logic_vector(3 downto 0) := "0101";
constant sdram_command_write : std_logic_vector(3 downto 0) := "0100";
constant sdram_command_bank_activate : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
constant sdram_command_precharge : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
constant sdram_command_mode_register : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
constant sdram_command_refresh : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
signal command_next : std_logic_vector(3 downto 0);
-- constant bank_state_idle : std_logic_vector(3 downto 0) := "0000";
-- constant bank_state_row_active : std_logic_vector(3 downto 0) := "0001";
-- constant bank_state_read : std_logic_vector(3 downto 0) := "0010";
-- constant bank_state_write : std_logic_vector(3 downto 0) := "0011";
-- constant bank_state_read_pre : std_logic_vector(3 downto 0) := "0100";
-- constant bank_state_write_pre : std_logic_vector(3 downto 0) := "0101";
-- constant bank_state_precharging : std_logic_vector(3 downto 0) := "0111";
-- constant bank_state_row_activating : std_logic_vector(3 downto 0) := "1000";
-- constant bank_state_write_recovering : std_logic_vector(3 downto 0) := "1001";
-- constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
-- constant bank_state_refresh : std_logic_vector(3 downto 0) := "1011";
-- constant bank_state_mode_access : std_logic_vector(3 downto 0) := "1100";
-- constant bank_state_init : std_logic_vector(3 downto 0) := "1101";
-- Banks each have their own state, but since read/write lines are shared they are not truly independent
-- Also for auto-refresh all banks must be in idle state
constant sdram_state_powerup : std_logic_vector(2 downto 0) := "000"; -- requires standard init
constant sdram_state_init : std_logic_vector(2 downto 0) := "001"; -- requires standard init
constant sdram_state_idle : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
constant sdram_state_refresh : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
constant sdram_state_read : std_logic_vector(2 downto 0) := "100"; -- processing a read request
constant sdram_state_write : std_logic_vector(2 downto 0) := "101"; -- processing a write request
constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
signal sdram_state_next : std_logic_vector(2 downto 0);
signal sdram_state_reg : std_logic_vector(2 downto 0);
signal delay_next : std_logic_vector(13 downto 0);
signal delay_reg : std_logic_vector(13 downto 0);
signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
signal refresh_pending_next : std_logic_vector(11 downto 0);
signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
signal suggest_refresh : std_logic; -- i.e. do we have any pending?
signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time
signal refreshing_now : std_logic;
signal idle_priority : std_logic_vector(3 downto 0);
signal data_out_next : std_logic_vector(31 downto 0);
signal data_out_reg : std_logic_vector(31 downto 0);
signal reply_next : std_logic;
signal reply_reg : std_logic;
-- track the active bank
-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
-- CAS,NOP,NOP,DATA
-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
-- capture inputs
signal DATA_IN_snext : std_logic_vector(31 downto 0);
signal DATA_IN_sreg : std_logic_vector(31 downto 0);
signal ADDRESS_IN_snext : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal ADDRESS_IN_sreg : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal READ_EN_snext : std_logic; -- if no reads pending may be a good time to do a refresh
signal READ_EN_sreg : std_logic; -- if no reads pending may be a good time to do a refresh
signal WRITE_EN_snext : std_logic;
signal WRITE_EN_sreg : std_logic;
signal dqm_mask_snext : std_logic_vector(3 downto 0);
signal dqm_mask_sreg : std_logic_vector(3 downto 0);
signal request_snext : std_logic;
signal request_sreg : std_logic;
signal refresh_snext : std_logic;
signal refresh_sreg : std_logic;
-- slow clock output regs
signal DATA_OUT_snext : std_logic_vector(31 downto 0);
signal DATA_OUT_sreg : std_logic_vector(31 downto 0);
signal reply_snext : std_logic;
signal reply_sreg : std_logic;
-- sdram output registers
signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
signal dq_out_next : std_logic_vector(15 downto 0);
signal dq_output_next : std_logic;
signal dq_in_next : std_logic_vector(15 downto 0);
signal ba_next : std_logic_vector(1 downto 0);
signal cs_n_next : std_logic;
signal ras_n_next : std_logic;
signal cas_n_next : std_logic;
signal we_n_next : std_logic;
signal ldqm_next : std_logic;
signal udqm_next : std_logic;
signal cke_next : std_logic;
signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
signal dq_out_reg : std_logic_vector(15 downto 0);
signal dq_output_reg : std_logic;
signal ba_reg : std_logic_vector(1 downto 0);
signal cs_n_reg : std_logic;
signal ras_n_reg : std_logic;
signal cas_n_reg : std_logic;
signal we_n_reg : std_logic;
signal ldqm_reg : std_logic;
signal udqm_reg : std_logic;
signal cke_reg : std_logic;
signal sdram_request_reg : std_logic;
signal sdram_request_next : std_logic;
signal reset_client_n_reg : std_logic;
signal reset_client_n_next : std_logic;
BEGIN
-- register
process(CLK_SDRAM,reset_n)
begin
if (reset_N = '0') then
sdram_state_reg <= sdram_state_init;
delay_reg <= (others=>'0');
refresh_pending_reg <= (others=>'0');
cycles_since_refresh_reg <= (others=>'0');
data_out_reg <= (others=>'0');
reply_reg <= '0';
addr_reg <= (others => '0');
dq_out_reg <= (others=> '0');
dq_output_reg <= '0';
ba_reg <= (others=>'0');
cs_n_reg <= '0';
ras_n_reg <= '0';
cas_n_reg <= '0';
we_n_reg <= '0';
ldqm_reg <= '0';
udqm_reg <= '0';
cke_reg <= '0';
--bank_row_reg <= (others=>(others=>'0'));
elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
sdram_state_reg <= sdram_state_next;
delay_reg <= delay_next;
refresh_pending_reg <= refresh_pending_next;
cycles_since_refresh_reg <= cycles_since_refresh_next;
data_out_reg <= data_out_next;
reply_reg <= reply_next;
addr_reg <= addr_next;
dq_out_reg <= dq_out_next;
dq_output_reg <= dq_output_next;
ba_reg <= ba_next;
cs_n_reg <= cs_n_next;
ras_n_reg <= ras_n_next;
cas_n_reg <= cas_n_next;
we_n_reg <= we_n_next;
ldqm_reg <=ldqm_next;
udqm_reg <= udqm_next;
cke_reg <= cke_next;
--bank_row_reg <= bank_row_next;
end if;
end process;
-- register request
process(CLK_SYSTEM,reset_n)
begin
if (reset_N = '0') then
data_in_sreg <= (others=>'0');
address_in_sreg <= (others=>'0');
read_en_sreg <= '0';
write_en_sreg <= '0';
request_sreg <= '0';
dqm_mask_sreg <= (others=>'1');
refresh_sreg <= '0';
data_out_sreg <= (others=>'0');
reply_sreg <= '0';
sdram_request_reg <= '0';
reset_client_n_reg <= '0';
elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
data_in_sreg <= data_in_snext;
address_in_sreg <= address_in_snext;
read_en_sreg <= read_en_snext;
write_en_sreg <= write_en_snext;
request_sreg <= request_snext;
dqm_mask_sreg <= dqm_mask_snext;
refresh_sreg <= refresh_snext;
data_out_sreg <= data_out_snext;
reply_sreg <= reply_snext;
sdram_request_reg <= sdram_request_next;
reset_client_n_reg <= reset_client_n_next;
end if;
end process;
-- Inputs - NB, clocked at a smaller multiple
process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, sdram_request_next, byte_access, word_access, longword_access, refresh)
begin
data_in_snext <= data_in_sreg;
address_in_snext <= address_in_sreg;
read_en_snext <= read_en_sreg;
write_en_snext <= write_en_sreg;
request_snext <= request_sreg;
dqm_mask_snext <= dqm_mask_sreg;
refresh_snext <= refresh; -- independent of memory requests
-- only snap inputs on new request
-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
if ((sdram_request_next xor request_sreg) = '1') then
data_in_snext <= data_in;
address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
read_en_snext <= read_en;
write_en_snext <= write_en;
request_snext <= sdram_request_next;
dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
end if;
end process;
-- refresh counters
process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
begin
cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
refresh_pending_next <= refresh_pending_reg;
suggest_refresh <= '0';
force_refresh <= '0';
if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
suggest_refresh <= '1';
end if;
if (refresh_pending_reg = X"FFF") then
force_refresh <= '1';
end if;
require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
if (refreshing_now = '1') then
-- refreshing right now
cycles_since_refresh_next <= (others=>'0');
-- This is one of our pending refreshes (if we have any)
if (suggest_refresh = '1') then
refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
end if;
else
if (cycles_since_refresh_reg = "11111111111") then
refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
cycles_since_refresh_next <= (others=>'0');
end if;
end if;
end process;
--
process(reset_client_n_reg,sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
begin
idle_priority <= (others=>'0');
refreshing_now <= '0';
reset_client_n_next <= reset_client_n_reg;
sdram_state_next <= sdram_state_reg;
command_next <= sdram_command_no_operation;
delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
data_out_next <= data_out_reg;
reply_next <= reply_reg;
-- Set some default for when we're sending NOP
dq_out_next <= (others=>'0');
dq_output_next <= '0';
cke_next <= '1';
ldqm_next <= '1';
udqm_next <= '1';
ba_next <= (others=>'0');
addr_next <= (others=>'1');
-- TODO - use bank states!!
-- TODO - MUCH MORE SMART STUFF!
-- Lets do them once we have Hello World running...
case sdram_state_reg is
when sdram_state_powerup =>
-- wait 100us (min)
if (delay_reg(13) = '1') then
sdram_state_next <= sdram_state_init_precharge;
delay_next <= (others=>'0');
end if;
when sdram_state_init =>
case delay_reg(5 downto 3)&delay_reg(0) is
when "0001" =>
command_next <= sdram_command_precharge;
addr_next(AP_BIT) <= '1'; --all banks
when "0010" =>
command_next <= sdram_command_refresh;
-- cke still high, so auto refresh
when "0100" =>
command_next <= sdram_command_refresh;
-- cke still high, so auto refresh
when "1000" =>
command_next <= sdram_command_mode_register;
--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
addr_next(3) <= '0'; -- sequential
addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
addr_next(8 downto 7) <= "00"; -- standard operation
addr_next(9) <= '0'; -- programmed burst access - of single cycle!
addr_next(11 downto 10) <= "00"; -- reserved
when "1010" =>
sdram_state_next <= sdram_state_idle;
delay_next <= (others=>'0');
when others =>
-- nop
end case;
when sdram_state_idle =>
reset_client_n_next <= '1';
delay_next <= (others=>'0');
idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
case idle_priority is -- priority encoder...
when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
sdram_state_next <= sdram_state_refresh;
when "1010"|"1011" =>
sdram_state_next <= sdram_state_write;
when "1001" =>
sdram_state_next <= sdram_state_read;
when others =>
-- stay here
end case;
when sdram_state_read =>
-- TODO - if same bank we can save some time... ?
-- Only do precharge on switching bank?
case delay_reg(3 downto 0) is
when X"0" =>
command_next <= sdram_command_bank_activate;
ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
command_next <= sdram_command_read;
ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
addr_next(AP_BIT) <= '1'; -- auto-precharge
when X"4" => -- command actually sent now
ldqm_next <= dqm_mask_sreg(0); -- for first read
udqm_next <= dqm_mask_sreg(1);
when X"5" => -- dqm for 1st read is sent
ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
udqm_next <= dqm_mask_sreg(3);
when X"7" =>
data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
data_out_next(15 downto 8) <= dq_in_next(15 downto 8);
when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
reply_next <= request_sreg;
sdram_state_next <= sdram_state_idle;
-- after 3 cycles we can do the next ACT (21 ns psc)
-- TODO - directly switch to next action so as not to waste a cycle
when others =>
end case;
when sdram_state_write =>
case delay_reg(3 downto 0) is
when X"0" =>
command_next <= sdram_command_bank_activate;
ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
command_next <= sdram_command_write;
ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
addr_next(AP_BIT) <= '1'; -- auto-precharge
dq_output_next <= '1';
dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
ldqm_next <= dqm_mask_sreg(0);
udqm_next <= dqm_mask_sreg(1);
when X"4" =>
dq_output_next <= '1';
dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
ldqm_next <= dqm_mask_sreg(2);
udqm_next <= dqm_mask_sreg(3);
reply_next <= request_sreg;
when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
sdram_state_next <= sdram_state_idle;
-- TODO - directly switch to next action to match read
when others =>
end case;
when sdram_state_refresh =>
case delay_reg(3 downto 0) is
when X"0" =>
command_next <= sdram_command_refresh;
-- cke still high, so auto refresh
refreshing_now <= '1';
when X"8" =>
sdram_state_next <= sdram_state_idle;
when others =>
end case;
when others =>
sdram_state_next <= sdram_state_init;
end case;
end process;
-- command_next directly translates to lines to send
-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
process(command_next)
begin
cs_n_next <= command_next(3);
ras_n_next <= command_next(2);
cas_n_next <= command_next(1);
we_n_next <= command_next(0);
end process;
-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
SDRAM_ADDR <= addr_reg;
SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
SDRAM_BA0 <= ba_reg(0);
SDRAM_BA1 <= ba_reg(1);
SDRAM_CS_N <= cs_n_reg;
SDRAM_RAS_N <= ras_n_reg;
SDRAM_CAS_N <= cas_n_reg;
SDRAM_WE_N <= we_n_reg;
SDRAM_ldqm <= ldqm_reg;
SDRAM_udqm <= udqm_reg;
SDRAM_CKE <= cke_reg;
-- inputs from SDRAM
dq_in_next <= SDRAM_DQ;
-- back to slower clock
reply_snext <= reply_reg;
data_out_snext <= data_out_reg;
-- outputs to rest of system
--REPLY <= reply_sreg;
DATA_OUT <= DATA_OUT_sreg;
-- a little sdram glue - move to sdram wrapper?
COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
sdram_request_next <= sdram_request_reg xor request;
reset_client_n <= reset_client_n_reg;
END vhdl;
| gpl-3.0 | 16fa87cb2a6f163f5234605a26d0d9cc | 0.64707 | 3.018304 | false | false | false | false |
APastorG/APG | adder/adder_core_s.vhd | 1 | 30,691 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a design of a parameterized adder which allows the addition of signed numbers
/ with high fexibility and control over the way data is introduced and the level of pipelining it
/ will be used
/ ┌ ┌───────┐
/ │ │ i e a │
/ input: P│ │ j f b │ _______
/ │ │ k g c │ ----> | adder | ----> result
/ │ │ l h d │ ───────
/ └ └───────┘
/ └───────┘
/ S
/ The clock cycles it takes to produce a result from the input can also be specified with the
/ SPEED_opt parameter. The higher this parameter, the shorter, in general, the delay path
/ between each register and thus, the higher the frequency the design is able to reach.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.counter_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_core_s is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive; --compulsory
P : positive; --compulsory
input_high : integer;
input_low : integer
);
port(
input : in u_sfixed_v(1 to P); --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed(adder_OH(MAX_POSSIBLE_BIT_opt,
S,
P,
input_high)
downto
adder_OL(TRUNCATE_TO_BIT_opt,
input_low)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_core_s_1 of adder_core_s is
/* corrected generics and internal/external ports' sizes */
/**************************************************************************************************/
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high,
input(1)'low);
constant DATA_WIDTH : positive := input(1)'length;
constant DATA_HIGH : integer := input(1)'high;
constant DATA_LOW : integer := input(1)'low;
constant OUTPUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt,
S,
P,
DATA_HIGH);
constant OUTPUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt,
DATA_LOW);
constant DATA_IMM_AFTER_START : boolean := DATA_IMM_AFTER_START_opt;
constant MAX_POSSIBLE_BIT : integer := ite(MAX_POSSIBLE_BIT_opt=integer'low,
integer'high - SULV_NEW_ZERO,
MAX_POSSIBLE_BIT_opt);
constant ADD_LEVELS : positive := 1 + log2ceil(P);
constant PIPELINE_POSITIONS : natural := ite(S = 1,
ADD_LEVELS,
ADD_LEVELS + 1);
constant PIPELINES_2_INTRODUCE : natural := number_of_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
constant CONDITION_EXC : boolean := (not DATA_IMM_AFTER_START)
and
((S = 1 and PIPELINES_2_INTRODUCE=0)
or
PIPELINES_2_INTRODUCE < 2);
function is_pipelines_exc(
s : positive;
pipeline_positions : natural)
return boolean_v is
variable result : boolean_v(1 to pipeline_positions) := (others => false);
begin
result(ite(s = 1,
pipeline_positions,
pipeline_positions-1)) := true;
return result;
end function;
constant IS_PIPELINED_EXC : boolean_v := is_pipelines_exc(S,
PIPELINE_POSITIONS);
constant IS_PIPELINED : boolean_v := ite(CONDITION_EXC,
IS_PIPELINED_EXC,
generate_pipelines(PIPELINE_POSITIONS,
SPEED_opt)
);
constant OUTPUT_BUFFER : boolean := ite(S = 1,
false,
ite(CONDITION_EXC,
false,
IS_PIPELINED(PIPELINE_POSITIONS))
);
constant ACC_PIPELINES : natural := S - 1;
constant ADD_PIPELINES : natural := ite(CONDITION_EXC,
1,
PIPELINES_2_INTRODUCE - ite(OUTPUT_BUFFER, 1, 0)
);
constant PIPELINES : natural := ADD_PIPELINES + ACC_PIPELINES + ite(OUTPUT_BUFFER,
1,
0);
/* other constants */
/**************************************************************************************************/
constant INTER_HIGH : integer := minimum(DATA_HIGH + log2ceil(P),
MAX_POSSIBLE_BIT);
/* data signals */
/**************************************************************************************************/
signal input_resolved : sfixed_v(1 to P)(input(1)'range); --where the input is converted to resolved
signal inter : u_sfixed(INTER_HIGH downto DATA_LOW);
signal output_inter : u_sfixed(OUTPUT_HIGH downto DATA_LOW);
signal start_sh : std_ulogic_vector(1 to ADD_PIPELINES);
signal valid_input_sh : std_ulogic_vector(1 to ADD_PIPELINES);
/* control signals */
/**************************************************************************************************/
signal start_delayed : std_ulogic;
signal valid_input_delayed : std_ulogic;
signal counter_out : std_ulogic;
/* structures to store and manipulate data of the adder tree (ADD) */
/**************************************************************************************************/
function T_ADD_state_data_high(
index : natural)
return integer is
begin
if DATA_HIGH+index > MAX_POSSIBLE_BIT then
return MAX_POSSIBLE_BIT;
else
return DATA_HIGH + index;
end if;
end function;
type T_ADD_state is record
level0 : sfixed_v(1 to signals_per_level(P, 0 ))(T_ADD_state_data_high(0) downto DATA_LOW);
level1 : sfixed_v(1 to signals_per_level(P, 1 ))(T_ADD_state_data_high(1) downto DATA_LOW);
level2 : sfixed_v(1 to signals_per_level(P, 2 ))(T_ADD_state_data_high(2) downto DATA_LOW);
level3 : sfixed_v(1 to signals_per_level(P, 3 ))(T_ADD_state_data_high(3) downto DATA_LOW);
level4 : sfixed_v(1 to signals_per_level(P, 4 ))(T_ADD_state_data_high(4) downto DATA_LOW);
level5 : sfixed_v(1 to signals_per_level(P, 5 ))(T_ADD_state_data_high(5) downto DATA_LOW);
level6 : sfixed_v(1 to signals_per_level(P, 6 ))(T_ADD_state_data_high(6) downto DATA_LOW);
level7 : sfixed_v(1 to signals_per_level(P, 7 ))(T_ADD_state_data_high(7) downto DATA_LOW);
level8 : sfixed_v(1 to signals_per_level(P, 8 ))(T_ADD_state_data_high(8) downto DATA_LOW);
level9 : sfixed_v(1 to signals_per_level(P, 9 ))(T_ADD_state_data_high(9) downto DATA_LOW);
level10 : sfixed_v(1 to signals_per_level(P, 10))(T_ADD_state_data_high(10)downto DATA_LOW);
level11 : sfixed_v(1 to signals_per_level(P, 11))(T_ADD_state_data_high(11)downto DATA_LOW);
end record;
-- in Vivado and ModelSim
-- this constant is used because even driving only one member of a structure implies driving the
-- whole structure. So with resolved signals the analysis takes places without problems and the
-- subsequent synthesis generates the desired structure.
constant ADD_Z : T_ADD_state:=(level0 => (others=>(others=>'Z')),
level1 => (others=>(others=>'Z')),
level2 => (others=>(others=>'Z')),
level3 => (others=>(others=>'Z')),
level4 => (others=>(others=>'Z')),
level5 => (others=>(others=>'Z')),
level6 => (others=>(others=>'Z')),
level7 => (others=>(others=>'Z')),
level8 => (others=>(others=>'Z')),
level9 => (others=>(others=>'Z')),
level10 => (others=>(others=>'Z')),
level11 => (others=>(others=>'Z')));
-- ADD_in stores the signals entering the levels of the adder tree
-- ADD_out stores the signals leaving
signal ADD_in : T_ADD_state := ADD_Z;
signal ADD_out : T_ADD_state := ADD_Z;
/* functions to read and procedures to write from/to T_ADD_state */
/**************************************************************************************************/
function T_ADD_state_read(
state : T_ADD_state;
level : natural)
return sfixed_v is
begin
case level is
when 0 => return state.level0;
when 1 => return state.level1;
when 2 => return state.level2;
when 3 => return state.level3;
when 4 => return state.level4;
when 5 => return state.level5;
when 6 => return state.level6;
when 7 => return state.level7;
when 8 => return state.level8;
when 9 => return state.level9;
when 10 => return state.level10;
when others => return state.level11;
end case;
end function;
function T_ADD_state_read(
state : T_ADD_state;
level : natural;
signal_number : integer)
return u_sfixed is
begin
case level is
when 0 => return state.level0(signal_number);
when 1 => return state.level1(signal_number);
when 2 => return state.level2(signal_number);
when 3 => return state.level3(signal_number);
when 4 => return state.level4(signal_number);
when 5 => return state.level5(signal_number);
when 6 => return state.level6(signal_number);
when 7 => return state.level7(signal_number);
when 8 => return state.level8(signal_number);
when 9 => return state.level9(signal_number);
when 10 => return state.level10(signal_number);
when others => return state.level11(signal_number);
end case;
end function;
procedure T_ADD_state_write(
signal state : inout T_ADD_state;
constant level : in natural;
constant new_value : in sfixed_v) is
begin
--for loop introduced because of obscure error in Active-HDL:
--Error DAGGEN_0700: Fatal error : INTERNAL CODE GENERATOR ERROR
for i in new_value'range loop
case level is
when 0 => state.level0(i) <= new_value(i);
when 1 => state.level1(i) <= new_value(i);
when 2 => state.level2(i) <= new_value(i);
when 3 => state.level3(i) <= new_value(i);
when 4 => state.level4(i) <= new_value(i);
when 5 => state.level5(i) <= new_value(i);
when 6 => state.level6(i) <= new_value(i);
when 7 => state.level7(i) <= new_value(i);
when 8 => state.level8(i) <= new_value(i);
when 9 => state.level9(i) <= new_value(i);
when 10 => state.level10(i) <= new_value(i);
when others => state.level11(i) <= new_value(i);
end case;
end loop;
end procedure;
procedure T_ADD_state_write(
signal state : inout T_ADD_state;
constant level : in natural;
constant signal_number : in integer;
constant new_value : in sfixed) is
begin
case level is
when 0 => state.level0(signal_number) <= new_value;
when 1 => state.level1(signal_number) <= new_value;
when 2 => state.level2(signal_number) <= new_value;
when 3 => state.level3(signal_number) <= new_value;
when 4 => state.level4(signal_number) <= new_value;
when 5 => state.level5(signal_number) <= new_value;
when 6 => state.level6(signal_number) <= new_value;
when 7 => state.level7(signal_number) <= new_value;
when 8 => state.level8(signal_number) <= new_value;
when 9 => state.level9(signal_number) <= new_value;
when 10 => state.level10(signal_number) <= new_value;
when others => state.level11(signal_number) <= new_value;
end case;
end procedure;
procedure T_ADD_state_copy(
signal from_state : in T_ADD_state;
signal to_state : inout T_ADD_state;
constant level : in natural) is
begin
case level is
when 0 => to_state.level0 <= from_state.level0;
when 1 => to_state.level1 <= from_state.level1;
when 2 => to_state.level2 <= from_state.level2;
when 3 => to_state.level3 <= from_state.level3;
when 4 => to_state.level4 <= from_state.level4;
when 5 => to_state.level5 <= from_state.level5;
when 6 => to_state.level6 <= from_state.level6;
when 7 => to_state.level7 <= from_state.level7;
when 8 => to_state.level8 <= from_state.level8;
when 9 => to_state.level9 <= from_state.level9;
when 10 => to_state.level10 <= from_state.level10;
when others => to_state.level11 <= from_state.level11;
end case;
end procedure;
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("adder_core_s : OUTPUT_HIGH: " & image(OUTPUT_HIGH));
msg_debug("adder_core_s : OUTPUT_LOW: " & image(OUTPUT_LOW));
msg_debug("adder_core_s : DATA_HIGH: " & image(DATA_HIGH));
msg_debug("adder_core_s : DATA_LOW: " & image(DATA_LOW));
msg_debug("adder_core_s : MAX_POSSIBLE_BIT_opt: " & image(MAX_POSSIBLE_BIT_opt));
msg_debug("adder_core_s : MAX_POSSIBLE_BIT: " & image(MAX_POSSIBLE_BIT));
/* Introduction of the input to the ADD structure, and extraction of the signal inter from it */
/**************************************************************************************************/
generate_input_resolved_signal:
for i in 1 to P generate
begin
input_resolved(i) <= input(i);
end;
end generate;
T_ADD_state_write(ADD_in, 0, input_resolved);
inter <= T_ADD_state_read(ADD_out, ADD_LEVELS-1, 1);
/* Generation and management of the control signals */
/**************************************************************************************************/
generate_start_control:
if ADD_PIPELINES>0 generate
begin
start_delayed <= start_sh(ADD_PIPELINES);
process (clk) is
begin
if rising_edge(clk) then
start_sh(1) <= start;
if ADD_PIPELINES>1 then
start_sh(2 to ADD_PIPELINES) <= start_sh(1 to ADD_PIPELINES-1);
end if;
end if;
end process;
end;
else generate
begin
start_delayed <= start;
end;
end generate;
generate_valid_input_control:
if DATA_IMM_AFTER_START=false generate
begin
when_ADD_PIPELINES_is_0:
if ADD_PIPELINES=0 generate
begin
valid_input_delayed<= valid_input;
end;
else generate
begin
valid_input_delayed <= valid_input_sh(ADD_PIPELINES);
process (clk) is
begin
if rising_edge(clk) then
valid_input_sh(1) <= valid_input;
if ADD_PIPELINES>1 then
valid_input_sh(2 to ADD_PIPELINES) <= valid_input_sh(1 to ADD_PIPELINES-1);
end if;
end if;
end process;
end;
end generate;
end;
end generate;
when_ACC_PIPELINES_greater_than_0:
if S>1 generate
begin
generate_counter:
if DATA_IMM_AFTER_START generate
signal aux : std_ulogic;
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
ACC_PIPELINES, --TARGET_dep,
true, --TARGET_WITH_COUNT_opt = t_true,
true, --USE_SET,
1) --SET_TO_dep)
downto 1);
begin
aux <= unsigned(count) ?/= 0;
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_wrap,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => ACC_PIPELINES,
TARGET_WITH_COUNT_opt => t_true,
TARGET_BLOCKING_opt => t_false,
USE_SET => true,
SET_TO_dep => 1,
USE_RESET => true,
SET_RESET_PRIORITY_opt => t_set,
USE_LOAD => false
)
port map(
clk => clk,
enable => aux,
set => start_delayed,
reset => counter_out,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count,
count_is_TARGET(1) => counter_out
);
end;
else generate
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
ACC_PIPELINES, --TARGET_dep,
false, --TARGET_WITH_COUNT_opt = t_true,
true, --USE_SET,
1) --SET_TO_dep)
downto 1);
begin
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_saturate,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => ACC_PIPELINES,
TARGET_WITH_COUNT_opt => t_false,
TARGET_BLOCKING_opt => t_true,
USE_SET => true,
SET_TO_dep => 1,
USE_RESET => true,
SET_RESET_PRIORITY_opt => t_set,
USE_LOAD => false
)
port map(
clk => clk,
enable => valid_input_delayed,
set => start_delayed,
reset => counter_out and valid_input_delayed,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count, --not used
count_is_TARGET(1) => counter_out
);
end;
end generate;
end;
elsif DATA_IMM_AFTER_START generate
begin
counter_out <= start_delayed;
end;
else generate
begin
counter_out <= valid_input_delayed;
end;
end generate;
generate_valid_output:
if OUTPUT_BUFFER generate
begin
process (clk) is
begin
if rising_edge(clk) then
if DATA_IMM_AFTER_START then
valid_output <= counter_out;
else
valid_output <= counter_out and valid_input_delayed;
end if;
end if;
end process;
end;
elsif DATA_IMM_AFTER_START generate
begin
valid_output <= counter_out;
end;
else generate
begin
valid_output <= counter_out and valid_input_delayed;
end;
end generate;
/* Generation of the adder tree */
/**************************************************************************************************/
generate_ADD_PIPELINES:
for level in 0 to ADD_LEVELS-1 generate
begin
except_in_first_level:
if level > 0 generate
begin
when_more_than_two_signals:
if signals_per_level(P, level-1) > 1 generate
begin
add_pairs:
for i in 1 to integer(floor(real(signals_per_level(P, level-1))/2.0)) generate
begin
T_ADD_state_write(ADD_in,
level,
i,
resize(T_ADD_state_read(ADD_out,
level-1,
2*i-1)
+
T_ADD_state_read(ADD_out,
level-1,
2*i),
minimum(DATA_HIGH+level,
MAX_POSSIBLE_BIT),
DATA_LOW));
end;
end generate;
end;
end generate;
transport_last_signal_when_odd_number_of_signals:
if (signals_per_level(P, level-1) mod 2)=1 generate
begin
T_ADD_state_write(ADD_in,
level,
signals_per_level(P, level),
resize(T_ADD_state_read(ADD_out,
level-1,
signals_per_level(P, level-1)),
minimum(DATA_HIGH+level,
MAX_POSSIBLE_BIT),
DATA_LOW));
end;
end generate;
end;
end generate;
generate_pipelines_or_connect_cables:
if IS_PIPELINED(level+1) generate
begin
process (clk) is
begin
if rising_edge(clk) then
T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level);
end if;
end process;
end;
else generate
begin
T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level);
end;
end generate;
end;
end generate;
/* Generation of the accumulator */
/**************************************************************************************************/
generate_accumulator:
if S>1 generate
signal previous_output_inter : u_sfixed(output_inter'range);
signal inter_resized : u_sfixed(output_inter'range);
signal addition : u_sfixed(output_inter'range);
signal selector : std_ulogic;
begin
inter_resized <= resize(inter, output_inter);
addition <= resize(previous_output_inter + inter_resized, addition);
output_inter <= addition when selector='0' else
inter_resized when selector='1' else
(others => 'X');
selector <= start_delayed;
process (clk) is
begin
if rising_edge(clk) then
if DATA_IMM_AFTER_START=false then
if valid_input_delayed = '1' then
previous_output_inter <= output_inter;
end if;
else
previous_output_inter <= output_inter;
end if;
end if;
end process;
end;
else generate
begin
output_inter <= inter;
end;
end generate;
/* Generation of the output pipeline */
/**************************************************************************************************/
generate_output_pipeline:
if OUTPUT_BUFFER generate
begin
process (clk)
begin
if rising_edge(clk) then
if OUTPUT_LOW<DATA_LOW then
output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW);
else
output <= (OUTPUT_HIGH downto OUTPUT_LOW =>
output_inter(OUTPUT_HIGH downto OUTPUT_LOW));
end if;
end if;
end process;
end;
else generate
begin
generate_no_output_pipeline:
if OUTPUT_LOW<DATA_LOW generate
begin
output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW);
end;
else generate
begin
output <= (OUTPUT_HIGH downto OUTPUT_LOW =>
output_inter(OUTPUT_HIGH downto OUTPUT_LOW));
end;
end generate;
end;
end generate;
end architecture;
| mit | 69fdbfa80a2b5d0f80c729b3b77e1da5 | 0.404012 | 4.886633 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey.vhdl | 1 | 37,114 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Problem - UART on the DE1 does not have all pins connected. Need to use...
ENTITY pokey IS
PORT
(
CLK : IN STD_LOGIC;
ENABLE_179 :in std_logic;
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
-- keyboard interface
-- KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
-- KEY_HELD : IN STD_LOGIC;
-- SHIFT_PRESSED : IN STD_LOGIC;
-- BREAK_PRESSED : IN STD_LOGIC;
-- KEY_INTERRUPT : IN STD_LOGIC;
keyboard_scan : out std_logic_vector(5 downto 0);
keyboard_response : in std_logic_vector(1 downto 0);
-- pots - go high as capacitor charges
POT_IN : in std_logic_vector(7 downto 0);
-- sio interface
SIO_IN1 : IN std_logic;
SIO_IN2 : IN std_logic;
SIO_IN3 : IN std_logic;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
IRQ_N_OUT : OUT std_logic;
SIO_OUT1 : OUT std_logic;
SIO_OUT2 : OUT std_logic;
SIO_OUT3 : OUT std_logic;
SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
POT_RESET : out std_logic
);
END pokey;
ARCHITECTURE vhdl OF pokey IS
component synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END component;
component syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
syncreset : in std_logic;
reset_n : in std_logic;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END component;
component pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_noise_filter IS
PORT
(
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END component;
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
shift_pressed : out std_logic;
control_pressed : out std_logic;
break_pressed : out std_logic;
key_held : out std_logic;
keycode : out std_logic_vector(5 downto 0);
other_key_irq : out std_logic
);
end component;
--signal enable_179 : std_logic;
signal enable_64 : std_logic;
signal enable_15 : std_logic;
signal audf0_reg : std_logic_vector(7 downto 0);
signal audc0_reg : std_logic_vector(7 downto 0);
signal audf1_reg : std_logic_vector(7 downto 0);
signal audc1_reg : std_logic_vector(7 downto 0);
signal audf2_reg : std_logic_vector(7 downto 0);
signal audc2_reg : std_logic_vector(7 downto 0);
signal audf3_reg : std_logic_vector(7 downto 0);
signal audc3_reg : std_logic_vector(7 downto 0);
signal audctl_reg : std_logic_vector(7 downto 0);
signal audf0_next : std_logic_vector(7 downto 0);
signal audc0_next : std_logic_vector(7 downto 0);
signal audf1_next : std_logic_vector(7 downto 0);
signal audc1_next : std_logic_vector(7 downto 0);
signal audf2_next : std_logic_vector(7 downto 0);
signal audc2_next : std_logic_vector(7 downto 0);
signal audf3_next : std_logic_vector(7 downto 0);
signal audc3_next : std_logic_vector(7 downto 0);
signal audctl_next : std_logic_vector(7 downto 0);
signal audf0_pulse : std_logic;
signal audf1_pulse : std_logic;
signal audf2_pulse : std_logic;
signal audf3_pulse : std_logic;
signal audf0_reload : std_logic;
signal audf1_reload : std_logic;
signal audf2_reload : std_logic;
signal audf3_reload : std_logic;
signal stimer_write : std_logic;
signal stimer_write_delayed : std_logic;
signal audf0_pulse_noise : std_logic;
signal audf1_pulse_noise : std_logic;
signal audf2_pulse_noise : std_logic;
signal audf3_pulse_noise : std_logic;
signal audf0_enable : std_logic;
signal audf1_enable : std_logic;
signal audf2_enable : std_logic;
signal audf3_enable : std_logic;
signal chan0_output_next : std_logic;
signal chan1_output_next : std_logic;
signal chan2_output_next : std_logic;
signal chan3_output_next : std_logic;
signal chan0_output_reg : std_logic;
signal chan1_output_reg : std_logic;
signal chan2_output_reg : std_logic;
signal chan3_output_reg : std_logic;
signal highpass0_next : std_logic;
signal highpass1_next : std_logic;
signal highpass0_reg : std_logic;
signal highpass1_reg : std_logic;
signal volume_channel_0_next : std_logic_vector(3 downto 0);
signal volume_channel_1_next : std_logic_vector(3 downto 0);
signal volume_channel_2_next : std_logic_vector(3 downto 0);
signal volume_channel_3_next : std_logic_vector(3 downto 0);
signal volume_channel_0_reg : std_logic_vector(3 downto 0);
signal volume_channel_1_reg : std_logic_vector(3 downto 0);
signal volume_channel_2_reg : std_logic_vector(3 downto 0);
signal volume_channel_3_reg : std_logic_vector(3 downto 0);
signal addr_decoded : std_logic_vector(15 downto 0);
signal noise_4 : std_logic;
signal noise_5 : std_logic;
signal noise_large : std_logic;
signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
signal initmode : std_logic;
signal irqen_next : std_logic_vector(7 downto 0);
signal irqen_reg : std_logic_vector(7 downto 0);
signal irqst_next : std_logic_vector(7 downto 0);
signal irqst_reg : std_logic_vector(7 downto 0);
signal irq_n_next : std_logic;
signal irq_n_reg : std_logic; -- for output
-- serial ports!
signal serial_ip_ready_interrupt : std_logic;
signal serial_ip_framing_next : std_logic;
signal serial_ip_framing_reg : std_logic;
signal serial_ip_overrun_next : std_logic;
signal serial_ip_overrun_reg : std_logic;
signal serial_op_needed_interrupt : std_logic;
signal skctl_next : std_logic_vector(7 downto 0);
signal skctl_reg : std_logic_vector(7 downto 0);
signal serin_shift_next : std_logic_vector(9 downto 0);
signal serin_shift_reg : std_logic_vector(9 downto 0);
signal serin_next : std_logic_vector(7 downto 0);
signal serin_reg : std_logic_vector(7 downto 0);
signal serin_bitcount_next : std_logic_vector(3 downto 0);
signal serin_bitcount_reg : std_logic_vector(3 downto 0);
signal sio_in1_reg : std_logic;
signal sio_in2_reg : std_logic;
signal sio_in3_reg : std_logic;
signal sio_in_next : std_logic;
signal sio_in_reg : std_logic;
signal sio_out_next : std_logic;
signal sio_out_reg : std_logic;
signal serial_out_next : std_logic;
signal serial_out_reg : std_logic;
signal serout_shift_next : std_logic_vector(9 downto 0);
signal serout_shift_reg : std_logic_vector(9 downto 0);
signal serout_holding_full_next : std_logic;
signal serout_holding_full_reg : std_logic;
signal serout_holding_next : std_logic_vector(7 downto 0);
signal serout_holding_reg : std_logic_vector(7 downto 0);
signal serout_holding_load : std_logic;
signal serout_bitcount_next : std_logic_vector(3 downto 0);
signal serout_bitcount_reg : std_logic_vector(3 downto 0);
signal serout_active_next : std_logic;
signal serout_active_reg : std_logic;
signal serial_reset : std_logic;
signal serout_sync_reset : std_logic;
signal skrest_write : std_logic;
signal serout_enable : std_logic;
signal serout_enable_delayed : std_logic;
signal serin_enable : std_logic;
signal async_serial_reset : std_logic;
signal waiting_for_start_bit : std_logic;
signal serin_clock_next : std_logic;
signal serin_clock_reg : std_logic;
signal serin_clock_last_next : std_logic;
signal serin_clock_last_reg : std_logic;
signal serout_clock_next : std_logic;
signal serout_clock_reg : std_logic;
signal serout_clock_last_next : std_logic;
signal serout_clock_last_reg : std_logic;
signal twotone_reset : std_logic;
signal twotone_next : std_logic;
signal twotone_reg : std_logic;
signal clock_next : std_logic;
signal clock_reg : std_logic;
signal clock_sync_next : std_logic;
signal clock_sync_reg : std_logic;
signal clock_input : std_logic;
-- keyboard
signal keyboard_overrun_next : std_logic;
signal keyboard_overrun_reg : std_logic;
signal shift_pressed : std_logic;
signal control_pressed : std_logic;
signal break_pressed : std_logic;
signal key_held : std_logic;
signal other_key_irq : std_logic;
signal kbcode : std_logic_vector(5 downto 0);
-- pots
signal pot0_next : std_logic_vector(7 downto 0);
signal pot0_reg : std_logic_vector(7 downto 0);
signal pot1_next : std_logic_vector(7 downto 0);
signal pot1_reg : std_logic_vector(7 downto 0);
signal pot2_next : std_logic_vector(7 downto 0);
signal pot2_reg : std_logic_vector(7 downto 0);
signal pot3_next : std_logic_vector(7 downto 0);
signal pot3_reg : std_logic_vector(7 downto 0);
signal pot4_next : std_logic_vector(7 downto 0);
signal pot4_reg : std_logic_vector(7 downto 0);
signal pot5_next : std_logic_vector(7 downto 0);
signal pot5_reg : std_logic_vector(7 downto 0);
signal pot6_next : std_logic_vector(7 downto 0);
signal pot6_reg : std_logic_vector(7 downto 0);
signal pot7_next : std_logic_vector(7 downto 0);
signal pot7_reg : std_logic_vector(7 downto 0);
signal pot_counter_next : std_logic_vector(7 downto 0);
signal pot_counter_reg : std_logic_vector(7 downto 0);
signal potgo_write : std_logic;
signal pot_reset_next : std_logic;
signal pot_reset_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
audf0_reg <= X"00";
audc0_reg <= X"00";
audf1_reg <= X"00";
audc1_reg <= X"00";
audf2_reg <= X"00";
audc2_reg <= X"00";
audf3_reg <= X"00";
audc3_reg <= X"00";
audctl_reg <= X"00";
irqen_reg <= X"00";
irqst_reg <= X"FF";
irq_n_reg <= '1';
skctl_reg <= X"00";
highpass0_reg <= '0';
highpass1_reg <= '0';
chan0_output_reg <= '0';
chan1_output_reg <= '0';
chan2_output_reg <= '0';
chan3_output_reg <= '0';
volume_channel_0_reg <= (others=>'0');
volume_channel_1_reg <= (others=>'0');
volume_channel_2_reg <= (others=>'0');
volume_channel_3_reg <= (others=>'0');
serin_reg <= (others=>'0');
serin_shift_reg <= (others=>'0');
serin_bitcount_reg <= (others=>'0');
serout_shift_reg <= (others=>'0');
serout_holding_reg <= (others=>'0');
serout_holding_full_reg <= '0';
serout_active_reg <= '0';
sio_out_reg <= '1';
serial_out_reg <= '1';
serial_ip_framing_reg <= '0';
serial_ip_overrun_reg <= '0';
clock_reg <= '0';
clock_sync_reg <= '0';
keyboard_overrun_reg <= '0';
serin_clock_reg <= '0';
serin_clock_last_reg <= '0';
serout_clock_reg <= '0';
serout_clock_last_reg <= '0';
twotone_reg <= '0';
sio_in_reg <= '0';
pot0_reg <= (others=>'0');
pot1_reg <= (others=>'0');
pot2_reg <= (others=>'0');
pot3_reg <= (others=>'0');
pot4_reg <= (others=>'0');
pot5_reg <= (others=>'0');
pot6_reg <= (others=>'0');
pot7_reg <= (others=>'0');
pot_counter_reg <= (others=>'0');
pot_reset_reg <= '1';
elsif (clk'event and clk='1') then
audf0_reg <= audf0_next;
audc0_reg <= audc0_next;
audf1_reg <= audf1_next;
audc1_reg <= audc1_next;
audf2_reg <= audf2_next;
audc2_reg <= audc2_next;
audf3_reg <= audf3_next;
audc3_reg <= audc3_next;
audctl_reg <= audctl_next;
irqen_reg <= irqen_next;
irqst_reg <= irqst_next;
irq_n_reg <= irq_n_next;
skctl_reg <= skctl_next;
highpass0_reg <= highpass0_next;
highpass1_reg <= highpass1_next;
chan0_output_reg <= chan0_output_next;
chan1_output_reg <= chan1_output_next;
chan2_output_reg <= chan2_output_next;
chan3_output_reg <= chan3_output_next;
volume_channel_0_reg<= volume_channel_0_next;
volume_channel_1_reg<= volume_channel_1_next;
volume_channel_2_reg<= volume_channel_2_next;
volume_channel_3_reg<= volume_channel_3_next;
serin_reg <= serin_next;
serin_shift_reg <= serin_shift_next;
serin_bitcount_reg <= serin_bitcount_next;
serout_shift_reg <= serout_shift_next;
serout_bitcount_reg <= serout_bitcount_next;
serout_holding_reg<=serout_holding_next;
serout_holding_full_reg<=serout_holding_full_next;
serout_active_reg <= serout_active_next;
sio_out_reg <= sio_out_next;
serial_out_reg <= serial_out_next;
serial_ip_framing_reg <= serial_ip_framing_next;
serial_ip_overrun_reg <= serial_ip_overrun_next;
clock_reg <= clock_next;
clock_sync_reg <= clock_sync_next;
keyboard_overrun_reg <= keyboard_overrun_next;
serin_clock_reg <= serin_clock_next;
serin_clock_last_reg <= serin_clock_last_next;
serout_clock_reg <= serout_clock_next;
serout_clock_last_reg <= serout_clock_last_next;
twotone_reg <= twotone_next;
sio_in_reg <= sio_in_next;
pot0_reg <= pot0_next;
pot1_reg <= pot1_next;
pot2_reg <= pot2_next;
pot3_reg <= pot3_next;
pot4_reg <= pot4_next;
pot5_reg <= pot5_next;
pot6_reg <= pot6_next;
pot7_reg <= pot7_next;
pot_counter_reg <= pot_counter_next;
pot_reset_reg <= pot_reset_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- clock selection
process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
begin
audf0_enable <= enable_64;
audf1_enable <= enable_64;
audf2_enable <= enable_64;
audf3_enable <= enable_64;
if (audctl_reg(0) = '1') then
audf0_enable <= enable_15;
audf1_enable <= enable_15;
audf2_enable <= enable_15;
audf3_enable <= enable_15;
end if;
if (audctl_reg(6) = '1') then
audf0_enable <= enable_179;
end if;
if (audctl_reg(5) = '1') then
audf2_enable <= enable_179;
end if;
if(audctl_reg(4) = '1') then
audf1_enable <= audf0_pulse;
end if;
if(audctl_reg(3) = '1') then
audf3_enable <= audf2_pulse;
end if;
end process;
-- Instantiate timers
timer0 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
timer1 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
timer2 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
timer3 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);
-- Timer reloading
process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
begin
audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
end process;
-- Writes to registers
process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
begin
audf0_next <= audf0_reg;
audc0_next <= audc0_reg;
audf1_next <= audf1_reg;
audc1_next <= audc1_reg;
audf2_next <= audf2_reg;
audc2_next <= audc2_reg;
audf3_next <= audf3_reg;
audc3_next <= audc3_reg;
audctl_next <= audctl_reg;
irqen_next <= irqen_reg;
skctl_next <= skctl_reg;
stimer_write <= '0';
serout_holding_load <= '0';
serout_holding_next <= serout_holding_reg;
serial_reset <= '0';
skrest_write <= '0';
potgo_write <= '0';
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
audf0_next <= data_in;
end if;
if(addr_decoded(1) = '1') then
audc0_next <= data_in;
end if;
if(addr_decoded(2) = '1') then
audf1_next <= data_in;
end if;
if(addr_decoded(3) = '1') then
audc1_next <= data_in;
end if;
if(addr_decoded(4) = '1') then
audf2_next <= data_in;
end if;
if(addr_decoded(5) = '1') then
audc2_next <= data_in;
end if;
if(addr_decoded(6) = '1') then
audf3_next <= data_in;
end if;
if(addr_decoded(7) = '1') then
audc3_next <= data_in;
end if;
if(addr_decoded(8) = '1') then
audctl_next <= data_in;
end if;
if (addr_decoded(9) = '1') then --STIMER
stimer_write <= '1';
end if;
if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
skrest_write <= '1';
end if;
if (addr_decoded(11) = '1') then -- POTGO - start POT scan
potgo_write <= '1';
end if;
if (addr_decoded(13) = '1') then --SEROUT
serout_holding_next <= data_in;
serout_holding_load <= '1';
end if;
if (addr_decoded(14) = '1') then --IRQEN
irqen_next <= data_in;
end if;
if (addr_decoded(15) = '1') then --SKCTL
skctl_next <= data_in;
if (data_in(6 downto 4)="000") then
serial_reset <= '1';
end if;
end if;
end if;
end process;
-- Read from registers
process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
data_out <= X"FF";
if(addr_decoded(0) = '1') then --POT0
data_out <= pot0_reg;
end if;
if(addr_decoded(1) = '1') then --POT1
data_out <= pot1_reg;
end if;
if(addr_decoded(2) = '1') then --POT2
data_out <= pot2_reg;
end if;
if(addr_decoded(3) = '1') then --POT3
data_out <= pot3_reg;
end if;
if(addr_decoded(4) = '1') then --POT4
data_out <= pot4_reg;
end if;
if(addr_decoded(5) = '1') then --POT5
data_out <= pot5_reg;
end if;
if(addr_decoded(6) = '1') then --POT6
data_out <= pot6_reg;
end if;
if(addr_decoded(7) = '1') then --POT7
data_out <= pot7_reg;
end if;
if(addr_decoded(8) = '1') then --ALLPOT
data_out <= not(pot_in);
end if;
if(addr_decoded(9) = '1') then --KBCODE
data_out <= control_pressed&shift_pressed&kbcode;
end if;
if(addr_decoded(10) = '1') then -- RANDOM
data_out <= RAND_OUT;
end if;
if (addr_decoded(13) = '1') then --SERIN
data_out <= serin_reg;
end if;
if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
data_out <= IRQST_REG;
--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
end if;
if (addr_decoded(15) = '1') then --SKSTAT
data_out <= not(serial_ip_framing_reg)¬(keyboard_overrun_reg)¬(serial_ip_overrun_reg)&sio_in_reg¬(SHIFT_PRESSED)¬(KEY_HELD)&waiting_for_start_bit&"1";
end if;
end process;
-- Fire interrupts
process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
begin
-- clear interrupts
irqst_next <= irqst_reg or not(irqen_reg);
irq_n_next <= '0';
if ((irqst_reg or "0000"¬(irqen_reg(3))&"000") = X"FF") then
irq_n_next <= '1';
end if;
-- set interrupts
if (audf0_pulse = '1') then
irqst_next(0) <= not(irqen_reg(0));
end if;
if (audf1_pulse = '1') then
irqst_next(1) <= not(irqen_reg(1));
end if;
if (audf3_pulse = '1') then
irqst_next(2) <= not(irqen_reg(2));
end if;
if (other_key_irq = '1') then
irqst_next(6) <= not(irqen_reg(6));
end if;
if (break_pressed = '1') then
irqst_next(7) <= not(irqen_reg(7));
end if;
if (serial_ip_ready_interrupt = '1') then
irqst_next(5) <= not(irqen_reg(5));
end if;
irqst_next(3) <= serout_active_reg;
if (serial_op_needed_interrupt = '1') then
irqst_next(4) <= not(irqen_reg(4));
end if;
end process;
-- Instantiate delay for stimer reload_request
stimer_delay : delay_line
generic map (count=>3)
port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
--stimer_write_delayed <= stimer_write;
-- Instantiate audio noise filters
pokey_noise_filter0 : pokey_noise_filter
port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter1 : pokey_noise_filter
port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter2 : pokey_noise_filter
port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter3 : pokey_noise_filter
port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
-- Audio output stage
process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
begin
chan0_output_next <= chan0_output_reg;
chan1_output_next <= chan1_output_reg;
chan2_output_next <= chan2_output_reg;
chan3_output_next <= chan3_output_reg;
if (audf0_pulse_noise = '1') then
chan0_output_next <= not(chan0_output_reg);
end if;
if (audf1_pulse_noise = '1') then
chan1_output_next <= not(chan1_output_reg);
end if;
if (audf2_pulse_noise = '1') then
chan2_output_next <= not(chan2_output_reg);
end if;
if (audf3_pulse_noise = '1') then
chan3_output_next <= not(chan3_output_reg);
end if;
end process;
-- High pass filters
process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
begin
highpass0_next <= highpass0_reg;
highpass1_next <= highpass1_reg;
if (audctl_reg(2) = '1') then
if (audf2_pulse = '1') then
highpass0_next <= chan0_output_reg;
end if;
else
highpass0_next <= '1';
end if;
if (audctl_reg(1) = '1') then
if (audf3_pulse = '1') then
highpass1_next <= chan1_output_reg;
end if;
else
highpass1_next <= '1';
end if;
end process;
-- Instantiate key pokey clocks
-- ~1.79MHz - from 25MHz/14
-- ~64KHz - from 1.79MHz/28
-- ~15KHz - from 1.79MHz/114
--enable_179_div : enable_divider
-- generic map (COUNT=>14)
-- port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
-- resetcount 6/33
enable_64_div : syncreset_enable_divider
generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
enable_15_div : syncreset_enable_divider
generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
-- Instantiate pokey noise circuits (lfsr)
initmode <= skctl_next(1) nor skctl_next(0);
poly_17_19_lfsr : pokey_poly_17_9
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
poly_5_lfsr : pokey_poly_5
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
poly_4_lfsr : pokey_poly_4
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
begin
volume_channel_0_next <= "0000";
volume_channel_1_next <= "0000";
volume_channel_2_next <= "0000";
volume_channel_3_next <= "0000";
if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
volume_channel_0_next <= audc0_reg(3 downto 0);
end if;
if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
volume_channel_1_next <= audc1_reg(3 downto 0);
end if;
if ((chan2_output_reg or audc2_reg(4)) = '1') then
volume_channel_2_next <= audc2_reg(3 downto 0);
end if;
if ((chan3_output_reg or audc3_reg(4)) = '1') then
volume_channel_3_next <= audc3_reg(3 downto 0);
end if;
end process;
-- serial port output
-- urghhh
serout_sync_reset <= serial_reset or stimer_write_delayed;
serout_clock_delay : delay_line
generic map (count=>2)
port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
begin
serout_clock_next <= serout_clock_reg;
serout_clock_last_next <= serout_clock_reg;
serout_shift_next <= serout_shift_reg;
serout_bitcount_next <= serout_bitcount_reg;
serout_holding_full_next <= serout_holding_full_reg;
serout_active_next <= serout_active_reg;
serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
sio_out_next <= serial_out_reg;
-- two tone output
twotone_next <= twotone_reg;
twotone_reset <= '0';
if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
twotone_next <= not(twotone_reg);
twotone_reset <= skctl_reg(3);
end if;
if (skctl_reg(3) = '1') then
sio_out_next <= twotone_reg;
end if;
-- force break
if (skctl_reg(7) = '1') then
sio_out_next <= '0';
end if;
serial_op_needed_interrupt <= '0';
-- generate clock from enable signals
if (serout_enable_delayed = '1') then
serout_clock_next <= not(serout_clock_reg);
end if;
-- output bits over sio
if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then
serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
-- reload
if (serout_bitcount_reg = X"0") then
if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
serout_shift_next <= '1'&serout_holding_reg&'0';
serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
serout_holding_full_next <= '0';
serial_op_needed_interrupt <= '1'; -- more data please!
serout_active_next <= '1';
else
serout_active_next <= '0';
serial_out_next <= '1'; -- remove blip!
end if;
else
serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
end if;
end if;
-- register to load has been written too, update our state to reflect that it is full
if (serout_holding_load = '1') then
serout_holding_full_next <= '1';
end if;
if (serial_reset = '1') then
twotone_next <= '0';
serout_bitcount_next <= (others=>'0');
serout_shift_next <= (others=>'0');
serout_holding_full_next <= '0';
serout_clock_next <= '0';
serout_clock_last_next <= '0';
serout_active_next <= '0';
end if;
end process;
-- serial port input
sio_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);
sio_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);
sio_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);
sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
begin
serin_clock_next <= serin_clock_reg;
serin_clock_last_next <= serin_clock_reg;
serin_shift_next <= serin_shift_reg;
serin_bitcount_next <= serin_bitcount_reg;
serin_next <= serin_reg;
serial_ip_overrun_next <= serial_ip_overrun_reg;
serial_ip_framing_next <= serial_ip_framing_reg;
serial_ip_ready_interrupt <= '0';
async_serial_reset <= '0';
-- generate clock from enable signals
if (serin_enable = '1') then
serin_clock_next <= not(serin_clock_reg);
end if;
-- resync clock on receipt of start bit
if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
async_serial_reset <= '1';
serin_clock_next <= '1';
end if;
-- receive bits into shift reg
if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge
if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then
serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
if (serin_bitcount_reg = X"0") then -- full byte
serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
-- irq to alert new data avilable
serial_ip_ready_interrupt <= '1';
-- flag up overrun
if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
serial_ip_overrun_next <= '1';
end if;
-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
if (sio_in_reg='0') then
serial_ip_framing_next <= '1';
end if;
else
serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
end if;
end if;
end if;
if (skrest_write = '1') then
serial_ip_overrun_next <= '0';
serial_ip_framing_next <= '0';
end if;
if (serial_reset = '1') then
serin_clock_next <= '0';
serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
serin_shift_next <= (others=>'0');
end if;
end process;
-- serial clocks
process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
begin
clock_next <= sio_clock;
clock_sync_next <= clock_reg;
serout_enable <= '0';
serin_enable <= '0';
clock_input <= '1'; -- when output, outputs channel 4
case skctl_reg(6 downto 4) is
when "000" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "001" =>
serin_enable <= audf3_pulse;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "010" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
clock_input <= '0';
when "011" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "100" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= audf3_pulse;
when "101" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "110" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
clock_input <= '0';
when "111" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
when others =>
-- nop
end case;
end process;
-- keyboard overrun (i.e. second key pressed before interrupt cleared)
process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
begin
keyboard_overrun_next <= keyboard_overrun_reg;
if (other_key_irq='1' and irqst_reg(6)='0') then
keyboard_overrun_next <= '1';
end if;
if (skrest_write = '1') then
keyboard_overrun_next <= '0';
end if;
end process;
-- keyboard scan
pokey_keyboard_scanner1 : pokey_keyboard_scanner
port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);
-- POT scan
process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
pot0_next <= pot0_reg;
pot1_next <= pot1_reg;
pot2_next <= pot2_reg;
pot3_next <= pot3_reg;
pot4_next <= pot4_reg;
pot5_next <= pot5_reg;
pot6_next <= pot6_reg;
pot7_next <= pot7_reg;
pot_reset_next <= pot_reset_reg;
pot_counter_next <= pot_counter_reg;
if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
if (pot_counter_reg = X"E4") then
pot_reset_next <= '1'; -- turn on pot dump transistors
end if;
if (pot_reset_reg = '0') then
if (pot_in(0) = '0') then -- pot now high, latch
pot0_next <= pot_counter_reg;
end if;
if (pot_in(1) = '0') then -- pot now high, latch
pot1_next <= pot_counter_reg;
end if;
if (pot_in(2) = '0') then -- pot now high, latch
pot2_next <= pot_counter_reg;
end if;
if (pot_in(3) = '0') then -- pot now high, latch
pot3_next <= pot_counter_reg;
end if;
if (pot_in(4) = '0') then -- pot now high, latch
pot4_next <= pot_counter_reg;
end if;
if (pot_in(5) = '0') then -- pot now high, latch
pot5_next <= pot_counter_reg;
end if;
if (pot_in(6) = '0') then -- pot now high, latch
pot6_next <= pot_counter_reg;
end if;
if (pot_in(7) = '0') then -- pot now high, latch
pot7_next <= pot_counter_reg;
end if;
end if;
end if;
if (potgo_write = '1') then
pot_counter_next <= (others=>'0');
pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
end if;
end process;
-- Outputs
irq_n_out <= irq_n_reg;
CHANNEL_0_OUT <= volume_channel_0_reg;
CHANNEL_1_OUT <= volume_channel_1_reg;
CHANNEL_2_OUT <= volume_channel_2_reg;
CHANNEL_3_OUT <= volume_channel_3_reg;
sio_out1 <= sio_out_reg;
sio_out2 <= sio_out_reg;
sio_out3 <= sio_out_reg;
sio_clock <= audf3_pulse when clock_input='0' else 'Z';
pot_reset <= pot_reset_reg;
END vhdl;
| gpl-3.0 | 63bccd1a2e0fb2c21c0c81446df13023 | 0.650482 | 2.669304 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/example_design/fontrom_top.vhd | 1 | 4,308 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fontrom_top IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END fontrom_top;
ARCHITECTURE xilinx OF fontrom_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT fontrom IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : fontrom
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 78f43b7583ef2fb4bae385be94b03dd4 | 0.575673 | 4.818792 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/BINARYZACJA/example_design/BINARYZACJA_prod_exdes.vhd | 4 | 5,325 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity BINARYZACJA_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end BINARYZACJA_exdes;
architecture xilinx of BINARYZACJA_exdes is
SIGNAL CLK_i : std_logic;
component BINARYZACJA is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : BINARYZACJA
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
| gpl-2.0 | 0cf60b07bc3ed01b715a7c19ccb6e45c | 0.504225 | 4.72913 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/soc.vhd | 1 | 14,464 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mips_soc is
port (
-- CLOCK
CPU_CLK : in std_logic; -- 32.5 Mhz
VGA_CLK : in std_logic; -- VGA_CLK 25Mhz
CPU_RESET : in std_logic;
-- VGA
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : buffer std_logic;
VGA_HSYNC : out std_logic;
-- SRAM
MEM_A : out std_logic_vector(31 downto 2);
MEM_DI : out std_logic_vector(31 downto 0);
MEM_DO : in std_logic_vector(31 downto 0);
MEM_MASK : out std_logic_vector(3 downto 0);
MEM_WR : out std_logic;
MEM_REQ : out std_logic;
MEM_BUSY : in std_logic;
-- Keyboard
KEYB_DATA : in std_logic_vector(7 downto 0);
-- Sound
MIPS_BEEPER : out std_logic;
-- SD Card
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
-- FDC Ports
VG93_CLK : in std_logic;
VG93_nCLR : in std_logic;
VG93_IRQ : out std_logic;
VG93_DRQ : out std_logic;
VG93_A : in std_logic_vector(1 downto 0);
VG93_D_IN : in std_logic_vector(7 downto 0);
VG93_D_OUT : out std_logic_vector(7 downto 0);
VG93_nCS : in std_logic;
VG93_nRD : in std_logic;
VG93_nWR : in std_logic;
VG93_nDDEN : in std_logic;
VG93_HRDY : in std_logic;
FDC_DRIVE : in std_logic_vector(1 downto 0);
FDC_nSIDE : in std_logic;
TST : out std_logic
);
end mips_soc;
architecture mips_soc_arch of mips_soc is
signal CPU_A : std_logic_vector(31 downto 0);
signal CPU_DI : std_logic_vector(31 downto 0);
signal CPU_DO : std_logic_vector(31 downto 0);
signal CPU_SEL : std_logic_vector(3 downto 0);
signal CPU_WE : std_logic;
signal CPU_INT : std_logic;
signal CPU_A_L : std_logic_vector(31 downto 0);
-- VGA
signal POS_X : unsigned(6 downto 0);
signal POS_Y : unsigned(4 downto 0);
signal VA : std_logic_vector(11 downto 0);
signal VDI : std_logic_vector(7 downto 0);
signal VDO : std_logic_vector(15 downto 0);
signal VWR : std_logic;
signal VATTR : std_logic_vector(7 downto 0);
signal VRG : std_logic_vector(7 downto 0);
-- HW timer: Frame counter
signal VGA_FRAMES : std_logic_vector(31 downto 0);
signal FR_LOCK : std_logic;
-- HW timer: CPU CLK counter
signal CPU_CLK_COUNTER : std_logic_vector(31 downto 0);
type STATES is (ST_IDLE, ST_INC, ST_SET_FRAMES, ST_SET_CC_COUNTER);
signal STATE : STATES;
-- SD Card
signal counter : unsigned(4 downto 0);
-- Shift register has an extra bit because we write on the
-- falling edge and read on the rising edge
signal shift_reg : std_logic_vector(8 downto 0);
signal in_reg : std_logic_vector(7 downto 0);
signal SD_BUSY : std_logic;
-- VG93 Reg
signal VG93_STATUS : std_logic_vector(7 downto 0);
signal VG93_TRACK_R : std_logic_vector(7 downto 0);
signal VG93_SECTOR_R : std_logic_vector(7 downto 0);
signal VG93_DATA_R : std_logic_vector(7 downto 0);
signal VG93_CONTROL : std_logic_vector(7 downto 0);
signal VG93_TRACK : std_logic_vector(7 downto 0);
signal VG93_SECTOR : std_logic_vector(7 downto 0);
signal VG93_DATA : std_logic_vector(7 downto 0);
signal VG93_CONTROL_READY_M : std_logic;
signal VG93_DATA_READY_M : std_logic;
signal VG93_CONTROL_READY : std_logic;
signal VG93_DATA_READY : std_logic;
signal VG93_IRQ_B : std_logic := '0';
signal VG93_DRQ_B : std_logic := '0';
signal SET_IRQ_DRQ : std_logic := '0';
signal RES_VG93_IRQ : std_logic;
signal RES_VG93_DRQ : std_logic;
signal RES_CR : std_logic := '0';
signal RES_DR : std_logic := '0';
signal idx_cnt : std_logic_vector(22 downto 0);
signal FDC_IDX : std_logic;
signal VG93_TYPE_1_CMD_SET : std_logic;
signal VG93_TYPE_1_CMD : std_logic;
begin
cpu: entity work.mlite_cpu
port map (
clk => CPU_CLK,
reset_in => CPU_RESET,
intr_in => CPU_INT,
mem_address => CPU_A,
mem_data_w => CPU_DO,
mem_data_r => CPU_DI,
mem_byte_we => CPU_SEL,
mem_pause => MEM_BUSY or SD_BUSY
);
u_MIPS_VIDEO : entity work.mips_video
port map(
CLK => CPU_CLK,
VGA_CLK => VGA_CLK,
RESET => CPU_RESET,
VA => VA,
VDI => VDI,
VDO => VDO,
VWR => VWR,
VATTR => VATTR,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
CPU_WE <= CPU_SEL(0) or CPU_SEL(1) or CPU_SEL(2) or CPU_SEL(3);
CPU_DI <= x"000000" & VRG when CPU_A_L = x"80000000" else
x"000000" & VATTR when CPU_A_L = x"80000010" else
x"0000" & VDO when CPU_A_L = x"80000020" or CPU_A_L = x"80000030" else
x"000000" & '0' & std_logic_vector(POS_X) when CPU_A_L = x"80000040" else
x"000000" & "000" & std_logic_vector(POS_Y) when CPU_A_L = x"80000050" else
VGA_FRAMES when CPU_A_L = x"80000060" else
CPU_CLK_COUNTER when CPU_A_L = x"80000064" else
x"000000" & in_reg when CPU_A_L = x"80000070" else
x"000000" & KEYB_DATA when CPU_A_L = x"80000090" else
x"000000" & "1" & VG93_nDDEN & "1" & FDC_nSIDE & VG93_HRDY & VG93_nCLR & FDC_DRIVE
when CPU_A_L = x"80000E40" else
x"000000" & VG93_CONTROL when CPU_A_L = x"80000E00" else
x"000000" & VG93_TRACK when CPU_A_L = x"80000E10" else
x"000000" & VG93_SECTOR when CPU_A_L = x"80000E20" else
x"000000" & VG93_DATA when CPU_A_L = x"80000E30" else
x"0000000" & "00" & VG93_DATA_READY & VG93_CONTROL_READY
when CPU_A_L = x"80000E50" else
MEM_DO;
VA <= std_logic_vector(POS_Y) & std_logic_vector(POS_X);
SD_CS <= '1' when CPU_RESET = '1' else
CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000080";
MIPS_BEEPER <= CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000FE0";
-- Main State Machine
process(CPU_CLK)
begin
if rising_edge(CPU_CLK) then
if CPU_RESET = '1' then
MEM_REQ <= '0';
POS_X <= "0000000";
POS_Y <= "00000";
STATE <= ST_IDLE;
VWR <= '0';
VRG <= "00000001";
FR_LOCK <= '0';
CPU_INT <= '0';
else
MEM_REQ <= '0';
MEM_WR <= '0';
VWR <= '0';
if VGA_VSYNC = '0' then
FR_LOCK <= '0';
end if;
case STATE is
when ST_INC =>
POS_X <= POS_X + 1;
if POS_X = 79 then
POS_X <= "0000000";
POS_Y <= POS_Y + 1;
if POS_Y = 29 then
POS_Y <= "00000";
end if;
end if;
STATE <= ST_IDLE;
when ST_SET_FRAMES =>
STATE <= ST_IDLE;
when ST_SET_CC_COUNTER =>
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
if FR_LOCK = '0' and VGA_VSYNC = '1' and STATE /= ST_SET_FRAMES then
FR_LOCK <= '1';
VGA_FRAMES <= VGA_FRAMES + 1;
CPU_INT <= '1';
STATE <= ST_IDLE;
end if;
if STATE /= ST_SET_CC_COUNTER then
CPU_CLK_COUNTER <= CPU_CLK_COUNTER +1;
end if;
if MEM_BUSY = '0' and CPU_RESET = '0' then
CPU_A_L <= CPU_A;
if (CPU_A = x"80000020" or CPU_A = x"80000030") and VRG(0) = '1' then
STATE <= ST_INC;
end if;
-- Plasma ISR Vector
if CPU_A = x"0000003C" then
CPU_INT <= '0';
end if;
if CPU_A(31) = '1' and CPU_WE = '1' then
case CPU_A is
when x"80000000" => -- Video Mode
VRG <= CPU_DO(7 downto 0);
when x"80000010" => -- Video Set Attr
VATTR <= CPU_DO(7 downto 0);
if VRG(2) = '1' then
STATE <= ST_INC;
end if;
when x"80000020" => -- Video Write Char
VDI <= CPU_DO(7 downto 0);
VWR <= '1';
when x"80000030" => -- Video Write Char & Attr
VATTR <= CPU_DO(15 downto 8);
VDI <= CPU_DO(7 downto 0);
VWR <= '1';
when x"80000040" => -- Video Set X Pos
POS_X <= unsigned(CPU_DO(6 downto 0));
when x"80000050" => -- Video Set Y Pos
POS_Y <= unsigned(CPU_DO(4 downto 0));
when x"80000060" =>
VGA_FRAMES <= CPU_DO;
STATE <= ST_SET_FRAMES;
when x"80000064" =>
CPU_CLK_COUNTER <= CPU_DO;
STATE <= ST_SET_CC_COUNTER;
when OTHERS =>
STATE <= ST_IDLE;
end case;
-- CPU Mem Access
elsif CPU_A(31) = '0' then
MEM_A <= '0' & CPU_A(30 downto 2);
MEM_DI <= CPU_DO;
MEM_WR <= CPU_WE;
MEM_MASK <= CPU_SEL;
MEM_REQ <= '1';
end if;
end if;
end if;
end if;
end process;
-- SD Card Serializer
-- SD CLK = CPU_CLK / 2
-- MMC/SDC can work at the clock frequency upto 20/25 MHz.
process(CPU_CLK)
begin
if rising_edge(CPU_CLK) then
if CPU_RESET = '1' then
shift_reg <= (others => '1');
in_reg <= (others => '1');
counter <= "10000"; -- Idle
else
case counter is
when "10000" =>
if MEM_BUSY = '0' and CPU_A = x"80000070" then
if CPU_WE = '0' then
shift_reg <= (others => '1');
else
shift_reg <= CPU_DO(7 downto 0) & '1';
end if;
counter <= "00000";
end if;
when "01111" =>
in_reg <= shift_reg(7 downto 0);
counter <= "10000";
when OTHERS =>
counter <= counter + 1;
if counter(0) = '0' then
shift_reg(0) <= SD_MISO;
else
shift_reg <= shift_reg(7 downto 0) & '1';
end if;
end case;
end if;
end if;
end process;
SD_BUSY <= not counter(4);
TST <= counter(0);
SD_SCK <= counter(0);
SD_MOSI <= shift_reg(8);
-- VG93 Reg Read
VG93_D_OUT <= VG93_STATUS(7 downto 2) & FDC_IDX & VG93_STATUS(0)
when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "00" and VG93_TYPE_1_CMD = '1' else
VG93_STATUS when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "00" else
VG93_TRACK_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "01" else
VG93_SECTOR_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "10" else
VG93_DATA_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "11" else
"11111111";
-- VG93 Status set to BUSY when Command received
VG93_STATUS <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E00" else
"00000001" when VG93_CONTROL_READY_M = '1';
VG93_TRACK_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E10";
VG93_SECTOR_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E20";
VG93_DATA_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E30";
-- VG93 Reg Write
VG93_CONTROL <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "00" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_TRACK <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "01" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_SECTOR <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "10" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_DATA <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "11" and VG93_nWR = '0' and falling_edge(VG93_CLK);
-- Buffers. IRQ and DRQ are send on VG93 status write
VG93_IRQ_B <= CPU_DO(1) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E40";
VG93_DRQ_B <= CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E40";
-- One shoot
SET_IRQ_DRQ <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E00" else '0';
-- One shoot
RES_VG93_IRQ <= '1' when VG93_nCS = '0' and VG93_A = "00" and rising_edge(CPU_CLK) else '0';
RES_VG93_DRQ <= '1' when VG93_nCS = '0' and VG93_A = "11" and rising_edge(CPU_CLK) else '0';
-- IRQ is cleard if VG93 Status Reg read or VG92 Control Reg written
IRQ_TR: entity work.D_Flip_Flop PORT MAP(
rst => RES_VG93_IRQ,
pre => '0',
ce => SET_IRQ_DRQ,
d => VG93_IRQ_B,
q => VG93_IRQ
);
-- DRQ is cleared if VG93 Data Reg accessed
DRQ_TR: entity work.D_Flip_Flop PORT MAP(
rst => RES_VG93_DRQ,
pre => '0',
ce => SET_IRQ_DRQ,
d => VG93_DRQ_B,
q => VG93_DRQ
);
CR_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_CONTROL_READY_M,
ce => RES_CR,
d => '0',
q => VG93_CONTROL_READY
);
-- One Shoot
VG93_CONTROL_READY_M <= '1' when VG93_nCS = '0' and VG93_A = "00" and VG93_nWR = '0' and falling_edge(VG93_CLK) else '0';
RES_CR <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '0' and CPU_A = x"80000E00" else '0';
DR_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_DATA_READY_M,
ce => RES_DR,
d => '0',
q => VG93_DATA_READY
);
VG93_DATA_READY_M <= '1' when VG93_A = "11" and VG93_nCS = '0' and falling_edge(VG93_CLK) else '0';
RES_DR <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_A = x"80000E30" else '0';
IDX_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_TYPE_1_CMD_SET,
ce => VG93_CONTROL_READY_M,
d => '0',
q => VG93_TYPE_1_CMD
);
VG93_TYPE_1_CMD_SET <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E10" else '0';
-- FDC Index pulse generator
-- 5 Hz for 300 RPM, Pulse width 8ms
process (CPU_CLK)
begin
if rising_edge(CPU_CLK) then
idx_cnt <= idx_cnt + 1;
if idx_cnt = 260000 then
FDC_IDX <= '0';
end if;
if idx_cnt = 6132076 then
idx_cnt <= (others => '0');
FDC_IDX <= '1';
end if;
end if;
end process;
end mips_soc_arch; | gpl-3.0 | 04b4dc6d4234b30cd8f95c8e20d85036 | 0.555241 | 2.55142 | false | false | false | false |
freecores/lq057q3dc02 | design/image_gen_bram.vhd | 1 | 8,627 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: image_gen_bram.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
--
-- Description: This file controls the BRAM components for each color.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.components.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY image_gen_bram IS
generic (
C_BIT_DEPTH,
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE,
C_BRAM_ADDR_WIDTH,
C_IMAGE_WIDTH,
C_IMAGE_HEIGHT : POSITIVE
);
port(
RSTx,
CLK_LCD : IN std_logic;
LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
R,
G,
B : OUT std_logic_vector(C_BIT_DEPTH/3-1 downto 0)
);
END ENTITY image_gen_bram;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE image_gen_bram_arch OF image_gen_bram IS
constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD
--Connecting signal wires between components
signal SINIT_wire : std_logic := '0';
signal ADDR_wire : std_logic_vector(C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0');
begin
--//////////////////////////--
-- COMPONENT INSTANTIATIONS --
--//////////////////////////--
--You can't simply instantiate one XCO BRAM component 3 times because all
--three components are initialized with 3 different COE files!
image_RED_data : image_gen_bram_red
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => R
);
image_GREEN_data : image_gen_bram_green
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => G
);
image_BLUE_data : image_gen_bram_blue
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => B
);
------------------------------------------------------------------
-- Process Description:
-- This process controls the BRAM's SINIT signal which sets the
-- DOUT pins of the BRAM to the value defined at the time of
-- the Xilinx core customization. The SINIT signal is enabled
-- b/w every line and b/w every new frame. This value is recommended
-- to be zero to conserver power but it doesn't really matter what
-- it is. In this design it is not connected but feel free to connect
-- it up yourself - everything should work exactly the same.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- SINIT_wire
--
-- Notes:
-- N/A
------------------------------------------------------------------
image_gen_bram_sinit_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
SINIT_wire <= '0';
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( CLK_LCD_CYC_NUM >= (C_ENAB_THE - 2) -- start of image... Change from -1 to -2 to enable one clock earlier
and
CLK_LCD_CYC_NUM < (C_IMAGE_WIDTH - 1 + C_ENAB_THE - 1)
and
LINE_NUM < (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
SINIT_wire <= '1'; --allow output to change based on ADDR
else
SINIT_wire <= '0';--reset output pins back to user-defined initial value (should be 0h to conserve power)
end if;
end if;
end process image_gen_bram_sinit_cntrl_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process controls the address value input to the BRAMs.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- ADDR_wire
--
-- Notes:
-- This process causes the Xilinx BRAM IP cores (instantiated
-- above for each color) to generate warnings saying "Memory
-- address is out of range" during simulation. This is only
-- because ADDR_wire is 76800 for a few clocks after it finishes
-- drawing the last pixel on the screen. The allowable range
-- is only 0 - 76799, but driving 76800 doesn't cause any issues.
-- I could fix it, but I'm too lazy. :-)
------------------------------------------------------------------
image_gen_bram_addr_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
ADDR_wire <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
--this condition signifies the start and end of each line
if( CLK_LCD_CYC_NUM >= (C_ENAB_THE - 1)
and
CLK_LCD_CYC_NUM < (C_IMAGE_WIDTH + C_ENAB_THE - 1)
and
LINE_NUM < (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
ADDR_wire <= ADDR_wire + 1;
--reset address back to zero once a complete image has been drawn
--(+ TVS timespec of course). We only have to do this in case the
--number of addressable image data bytes is less than
--2^#BRAM_ADDR_bits (i.e. the number of addressable BRAM bytes).
--This is almost always likely to be the case since the chances of
--Xilinx automatically generating a BRAM block the _exact_ same size
--as your image is highly unlikey. This conditional statement will work
--in either case. :-)
elsif( LINE_NUM >= (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
ADDR_wire <= (others => '0');
--if data should not be sent then just wait for the next line before
--incrementing the address again
else
ADDR_wire <= ADDR_wire;
end if; --end data OK TO SEND check
end if; --end CLK'event and CLK = '1'
end process image_gen_bram_addr_cntrl_PROC;
END ARCHITECTURE image_gen_bram_arch;
| gpl-2.0 | 3a01826b51a37022dc921e6be597c2d0 | 0.511186 | 4.03508 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/boot_backup.vhd | 1 | 8,924 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity boot is
port (
CLK50 : in std_logic;
BUTTON1 : in std_logic;
BUTTON2 : in std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
SRAM_A : out std_logic_vector(18 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
COMM_CSA : in std_logic;
COMM_CSD : in std_logic;
COMM_SCK : in std_logic;
COMM_SDI : in std_logic;
COMM_SDO : out std_logic;
COMM_READY : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic
);
end boot;
architecture rtl of boot is
-- SPI COMMANDS
constant CMD_SET_ATTR : std_logic_vector(6 downto 0) := "0000000";
constant CMD_SET_X : std_logic_vector(6 downto 0) := "0000001";
constant CMD_SET_Y : std_logic_vector(6 downto 0) := "0000010";
constant CMD_WRITE_CHAR : std_logic_vector(6 downto 0) := "0000011";
constant CMD_H_ADDR : std_logic_vector(6 downto 0) := "0000100";
constant CMD_M_ADDR : std_logic_vector(6 downto 0) := "0000101";
constant CMD_L_ADDR : std_logic_vector(6 downto 0) := "0000110";
constant CMD_DATA_WR : std_logic_vector(6 downto 0) := "0000111";
constant CMD_DATA_RD : std_logic_vector(6 downto 0) := "0001000";
signal CLK : std_logic;
signal VGA_CLK : std_logic;
signal RESET : std_logic;
signal LOCKED : std_logic;
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal VA : std_logic_vector(11 downto 0);
signal VDI : std_logic_vector(7 downto 0);
signal VWR : std_logic;
signal VATTR : std_logic_vector(7 downto 0);
signal COMM_AO : std_logic_vector(7 downto 0);
signal COMM_AI : std_logic_vector(7 downto 0);
signal COMM_A_REQ : std_logic;
signal COMM_A_ACK : std_logic;
signal COMM_DO : std_logic_vector(7 downto 0);
signal COMM_DI : std_logic_vector(7 downto 0);
signal COMM_D_REQ : std_logic;
signal COMM_D_ACK : std_logic;
signal COMM_RG : std_logic_vector(7 downto 0);
signal COMM_MA : std_logic_vector(19 downto 0);
type STATES is (ST_IDLE, ST_READ1, ST_READ2, ST_WRITE1);
signal STATE : STATES;
begin
LED1 <= BUTTON1;
LED2 <= not BUTTON1 and not BUTTON2;
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK,
VGA_CLK => VGA_CLK,
LOCKED => LOCKED );
-- ###########################
RESET <= not LOCKED;
u_VIDEO : entity work.video
port map(
CLK => CLK,
VGA_CLK => VGA_CLK,
RESET => RESET,
VA => VA,
VDI => VDI,
VWR => VWR,
VATTR => VATTR,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
u_COMM_SPI : entity work.spi_comm
port map(
CLK => CLK,
RESET => RESET,
SPI_CS_A => COMM_CSA,
SPI_CS_D => COMM_CSD,
SPI_SCK => COMM_SCK,
SPI_DI => COMM_SDI,
SPI_DO => COMM_SDO,
ADDR_O => COMM_AO,
ADDR_I => COMM_AI,
ADDR_REQ => COMM_A_REQ,
ADDR_ACK => COMM_A_ACK,
DATA_O => COMM_DO,
DATA_I => COMM_DI,
DATA_REQ => COMM_D_REQ,
DATA_ACK => COMM_D_ACK );
p_state_machine : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= ST_IDLE;
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
COMM_READY <= '0';
VWR <= '0';
else
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
VWR <= '0';
case STATE is
when ST_IDLE =>
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
if COMM_A_REQ = '1' then
COMM_A_ACK <= '1';
COMM_RG <= COMM_AO;
if COMM_AO(7) = '0' then -- ### READ ###
case (COMM_AO(6 downto 0)) is
when CMD_DATA_RD =>
SRAM_A <= '0' & COMM_MA(17 downto 0);
SRAM_OE <= '0';
if COMM_MA(18) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if COMM_MA(19) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
STATE <= ST_READ1;
when OTHERS =>
NULL;
end case;
end if;
elsif COMM_D_REQ = '1' then
COMM_D_ACK <= '1';
if COMM_RG(7) = '1' then -- ### WRITE ###
case (COMM_RG(6 downto 0)) is
when CMD_SET_ATTR =>
VATTR <= COMM_DO;
when CMD_SET_X =>
VA <= VA(11 downto 7) & COMM_DO(6 downto 0);
when CMD_SET_Y =>
VA <= COMM_DO(4 downto 0) & VA(6 downto 0);
when CMD_WRITE_CHAR =>
VDI <= COMM_DO;
VWR <= '1';
when CMD_H_ADDR =>
COMM_MA(19 downto 16) <= COMM_DO(3 downto 0);
when CMD_M_ADDR =>
COMM_MA(15 downto 8) <= COMM_DO;
when CMD_L_ADDR =>
COMM_MA(7 downto 0 ) <= COMM_DO;
when CMD_DATA_WR =>
SRAM_A <= '0' & COMM_MA(17 downto 0);
SRAM_DI <= COMM_DO & COMM_DO;
SRAM_WE <= '0';
if COMM_MA(18) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if COMM_MA(19) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
STATE <= ST_WRITE1;
when OTHERS =>
NULL;
end case;
end if;
end if;
when ST_READ1 =>
if COMM_MA(19) = '0' then
COMM_DI <= SRAM_DO(7 downto 0);
else
COMM_DI <= SRAM_DO(15 downto 8);
end if;
STATE <= ST_READ2;
when ST_READ2 =>
if COMM_D_REQ = '1' then
COMM_D_ACK <= '1';
STATE <= ST_IDLE;
end if;
when ST_WRITE1 =>
SRAM_WE <= '1';
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
SRAM_D <= SRAM_DI;
SRAM_DO <= SRAM_D;
end rtl;
| gpl-3.0 | c476e2948c78b34f79fb35e898804dd3 | 0.378418 | 3.948673 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd | 1 | 2,948 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:15 09/10/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Stepper
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestStepper IS
END TestStepper;
ARCHITECTURE behavior OF TestStepper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Stepper
PORT(
iac_pulse : IN std_logic;
iac_clockwise : IN std_logic;
iac_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal iac_pulse : std_logic := '0';
signal iac_clockwise : std_logic := '0';
--Outputs
signal iac_out : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Stepper PORT MAP (
iac_pulse => iac_pulse,
iac_clockwise => iac_clockwise,
iac_out => iac_out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
iac_clockwise <= '1';
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
wait;
end process;
END;
| bsd-3-clause | ddeb6d0281419d1133a66f37af18726c | 0.567164 | 3.626076 | false | true | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/ps2_keyboard.vhdl | 1 | 8,121 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code
-- KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed
-- SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held
-- CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held
-- BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers)
ENTITY ps2_keyboard IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
PS2_CLK : IN STD_LOGIC;
PS2_DAT : IN STD_LOGIC;
KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
KEY_EXTENDED : OUT STD_LOGIC; -- valid on event, if scan code extended
KEY_UP : OUT STD_LOGIC -- value on event, if key released
);
END ps2_keyboard;
ARCHITECTURE vhdl OF ps2_keyboard IS
component enable_divider IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
-- PS2 keyboard sends on its own clock high->low transition
-- start, 8 data bits, parity, stop
-- Codes are either 1 bytes or 2 bytes (extended) on press
-- XX
-- EX YY
-- Codes are eighter 2 bytes or 3 bytes (extended) on release
-- F0 XX
-- EX F0 YY
-- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77
-- LSB first
-- Start bit 0
-- Stop bit 1
-- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7))
-- e.g.
-- '0 1100 0010 0 1'
-- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0
-- Receive raw data from ps2 serial interface
signal ps2_shiftreg_next : std_logic_vector(10 downto 0);
signal ps2_shiftreg_reg : std_logic_vector(10 downto 0);
signal idle_next : std_logic_vector(3 downto 0);
signal idle_reg : std_logic_vector(3 downto 0);
signal bitcount_next : std_logic_vector(3 downto 0);
signal bitcount_reg : std_logic_vector(3 downto 0);
signal enable_ps2 : std_logic;
signal last_ps2_clk_next : std_logic;
signal last_ps2_clk_reg : std_logic;
signal ps2_clk_reg : std_logic;
signal ps2_dat_reg : std_logic;
signal parity : std_logic;
-- Once we have whole parity checked bytes
signal byte_next : std_logic_vector(7 downto 0);
signal byte_reg : std_logic_vector(7 downto 0);
signal byte_received_next : std_logic;
signal byte_received_reg : std_logic;
-- Decode if they are press(or repeat)/release or extended
signal pending_extended_next : std_logic;
signal pending_extended_reg : std_logic;
signal pending_keyup_next : std_logic;
signal pending_keyup_reg : std_logic;
-- To eventually get the code itself
signal key_event_next : std_logic;
signal key_event_reg : std_logic;
signal key_value_next : std_logic_vector(9 downto 0);
signal key_value_reg : std_logic_vector(9 downto 0);
-- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard
signal key_value_last_next : std_logic_vector(9 downto 0);
signal key_value_last_reg : std_logic_vector(9 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
ps2_clk_reg <= '0';
ps2_dat_reg <= '0';
-- Convert to bytes/verify
last_ps2_clk_reg <= '0';
ps2_shiftreg_reg<= (others=>'0');
idle_reg <= (others=>'0');
bitcount_reg <= (others=>'0');
byte_received_reg <= '0';
byte_reg <= (others=>'0');
-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
pending_extended_reg <= '0';
pending_keyup_reg <= '0';
-- Output registers
key_event_reg <= '0';
key_value_reg <= (others=>'0');
key_value_last_reg <= (others=>'0');
elsif (clk'event and clk='1') then
-- Raw interface
-- async - do we need some form of synchronizer?
ps2_clk_reg <= ps2_clk;
ps2_dat_reg <= ps2_dat;
-- Convert to bytes/verify
last_ps2_clk_reg <= last_ps2_clk_next;
ps2_shiftreg_reg<= ps2_shiftreg_next;
idle_reg <= idle_next;
bitcount_reg <= bitcount_next;
byte_received_reg <= byte_received_next;
byte_reg <= byte_next;
-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
pending_extended_reg <= pending_extended_next;
pending_keyup_reg <= pending_keyup_next;
-- Output registers
key_event_reg <= key_event_next;
key_value_reg <= key_value_next;
key_value_last_reg <= key_value_last_next;
end if;
end process;
-- Divide clock by 256 to get approx 4*ps2 clock
enable_div : enable_divider
generic map (COUNT=>256)
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2);
-- capture bytes from ps2
parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1));
process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity)
begin
ps2_shiftreg_next <= ps2_shiftreg_reg;
last_ps2_clk_next <= last_ps2_clk_reg;
bitcount_next <= bitcount_reg;
idle_next <= idle_reg;
byte_received_next <= '0';
byte_next <= (others=>'0');
if (enable_ps2 = '1') then
last_ps2_clk_next <= ps2_clk_reg;
-- sample on falling edge
if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then
ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1);
bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1);
end if;
-- output to next stage when done
if (bitcount_reg = X"B") then
byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10);
byte_next <= ps2_shiftreg_reg(8 downto 1);
bitcount_next <= (others=>'0');
end if;
-- reset if both high for a time period
idle_next <= std_logic_vector(unsigned(idle_reg) +1);
if (idle_reg = X"F") then
ps2_shiftreg_next <= (others=>'0');
bitcount_next <= (others=>'0');
end if;
if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then
idle_next <= X"0";
end if;
end if;
end process;
-- process bytes
process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg)
begin
pending_extended_next <= pending_extended_reg;
pending_keyup_next <= pending_keyup_reg;
key_event_next <= '0';
key_value_next <= (others =>'0');
key_value_last_next <= key_value_last_reg;
if (byte_received_reg = '1') then
case byte_reg is
when X"E0" =>
pending_extended_next <= '1';
when X"E1" =>
pending_extended_next <= '1';
when X"F0" =>
pending_keyup_next <= '1';
when others =>
pending_extended_next <= '0';
pending_keyup_next <= '0';
if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then
key_event_next <= '1';
key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
end if;
end case;
end if;
end process;
-- Output
key_event <= key_event_reg;
key_value <= key_value_reg(7 downto 0);
key_extended <= key_value_reg(8);
key_up <= key_value_reg(9);
END vhdl;
| gpl-3.0 | b7854a529a83b20f55fb37692f2094af | 0.640931 | 2.954165 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dadd_3_full_dsp_64/synth/sin_taylor_series_ap_dadd_3_full_dsp_64.vhd | 4 | 12,855 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dadd_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dadd_3_full_dsp_64_arch OF sin_taylor_series_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dadd_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dadd_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dadd_3_full_dsp_64_arch;
| mit | 06405bd2b74a5b996508c88fb6b70424 | 0.651575 | 3.005611 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dmul_4_max_dsp_64/synth/sin_taylor_series_ap_dmul_4_max_dsp_64.vhd | 4 | 12,844 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dmul_4_max_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dmul_4_max_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dmul_4_max_dsp_64_arch OF sin_taylor_series_ap_dmul_4_max_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dmul_4_max_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dmul_4_max_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FM" &
"S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0," &
"C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dmul_4_max_dsp_64_arch;
| mit | 5b2f79bf44ab5463f1a2cd67c9ab8a64 | 0.651277 | 3.00304 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04000_bad.vhd | 1 | 4,941 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization trough reset for Raz, enable and Count_Length
-------------------------------------------------------------------------------------------------
-- File name : STD_04000_bad.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: State machine case enumeration completion: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_04000_bad is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end STD_04000_bad;
--CODE
architecture Behavioral of STD_04000_bad is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Count_Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter : Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Count_Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
sm_State <= init;
Raz <= '0';
Enable <= '0';
Count_Length <= (others=>'0');
elsif (rising_edge(i_Clock)) then
case sm_State is
when init =>
-- Set the length value
Count_Length <= c_Length;
sm_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count = '0') then
-- The counter has not finished, wait
Enable <= i_Start xor not i_Stop;
sm_State <= Enabled;
else
-- The counter has finished, nothing else to do
Enable <= '0';
sm_State <= finished;
end if;
--*** MISSING finished state of the FSM ***--
end case;
end if;
end process;
end Behavioral;
--CODE
| gpl-3.0 | dcd59e4988f73975253bd8e076ad2cf9 | 0.490387 | 4.639437 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/speccy.vhd | 1 | 12,951 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity speccy is
Port (
CLK50 : in std_logic;
MCU_READY : in std_logic;
KEYB_CLK : in std_logic;
KEYB_DATA : in std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end speccy;
architecture rtl of speccy is
signal CLK : std_logic;
signal VGA_CLK : std_logic;
signal LOCKED : std_logic;
signal RESET : std_logic;
signal TICK : unsigned(3 downto 0);
signal CLC_TICK : std_logic;
signal CPU_CLK : std_logic;
signal CPU_RESET : std_logic;
signal CPU_INT : std_logic;
signal CPU_NMI : std_logic;
signal CPU_MREQ : std_logic;
signal CPU_IORQ : std_logic;
signal CPU_M1 : std_logic;
signal CPU_RD : std_logic;
signal CPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal DIVROM_DO : std_logic_vector(7 downto 0);
signal RAM_A : std_logic_vector(19 downto 0);
signal RAM_DO : std_logic_vector(7 downto 0);
signal RAM_RW : std_logic;
signal RAM_REQ : std_logic;
signal VRAM_WR : std_logic_vector(0 downto 0);
signal VRAM_A : std_logic_vector(13 downto 0);
signal VRAM_VA : std_logic_vector(12 downto 0);
signal VRAM_VD : std_logic_vector(7 downto 0);
signal BORDERCOLOR : std_logic_vector(2 downto 0);
signal KEYB_DO : std_logic_vector(4 downto 0);
signal RESET_TICK : std_logic;
signal RESET_ONESHOT: std_logic;
signal NMI_TICK : std_logic;
signal NMI_ONESHOT : std_logic;
signal BEEPER : std_logic;
signal CLC : std_logic;
signal AY_CS : std_logic;
signal AY_DO : std_logic_vector(7 downto 0);
signal AY_A : std_logic_vector(7 downto 0);
signal AY_B : std_logic_vector(7 downto 0);
signal AY_C : std_logic_vector(7 downto 0);
signal AUDIO_L : std_logic_vector(9 downto 0);
signal AUDIO_R : std_logic_vector(9 downto 0);
------------------------- 128K -------------------------
signal PAGE : std_logic_vector(2 downto 0) := "000";
signal SCREEN : std_logic := '0';
signal ROMSEL : std_logic := '0';
signal DISABLE : std_logic := '0';
------------------------ DIVMMC ------------------------
signal BANK : std_logic_vector(5 downto 0) := "000000";
signal CONMEM : std_logic := '0';
signal MAPRAM : std_logic := '0';
signal MAPCOND : std_logic := '0';
signal AUTOMAP : std_logic := '0';
signal counter : unsigned(3 downto 0);
-- Shift register has an extra bit because we write on the
-- falling edge and read on the rising edge
signal shift_reg : std_logic_vector(8 downto 0);
signal in_reg : std_logic_vector(7 downto 0);
begin
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK,
VGA_CLK => VGA_CLK,
LOCKED => LOCKED );
u_VIDEO : entity work.video
port map(
VGA_CLK => VGA_CLK,
RESET => '0',
BORDERCOLOR => BORDERCOLOR,
INT => CPU_INT,
VA => VRAM_VA,
VD => VRAM_VD,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
u_ROM : entity work.rom
port map(
clka => CLK,
addra => ROMSEL & CPU_A(13 downto 0),
douta => ROM_DO );
u_DIVROM : entity work.divrom
port map(
clka => CLK,
addra => CPU_A(12 downto 0),
douta => DIVROM_DO );
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WR,
addra => VRAM_A,
dina => CPU_DO,
clkb => VGA_CLK,
addrb => SCREEN & VRAM_VA,
doutb => VRAM_VD );
u_CPU : entity work.T80se
port map(
RESET_n => CPU_RESET, --not RESET,
CLK_n => CLK,
CLKEN => CPU_CLK,
WAIT_n => '1',
INT_n => CPU_INT,
NMI_n => CPU_NMI,
BUSRQ_n => '1',
M1_n => CPU_M1,
MREQ_n => CPU_MREQ,
IORQ_n => CPU_IORQ,
RD_n => CPU_RD,
WR_n => CPU_WR,
RFSH_n => OPEN,
HALT_n => OPEN,
BUSAK_n => OPEN,
A => CPU_A,
DI => CPU_DI,
DO => CPU_DO );
u_RAM : entity work.memctrl
port map(
CLK => CLK,
RESET => RESET,
MEM_A => RAM_A,
MEM_DI => CPU_DO,
MEM_DO => RAM_DO,
MEM_RW => RAM_RW,
MEM_REQ => RAM_REQ,
MEM_ACK => open,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
SRAM_CE0 => SRAM_CE0,
SRAM_CE1 => SRAM_CE1,
SRAM_OE => SRAM_OE,
SRAM_WE => SRAM_WE,
SRAM_UB => SRAM_UB,
SRAM_LB => SRAM_LB );
u_KEYBOARD: entity work.keyboard
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => KEYB_CLK,
PS2_DATA => KEYB_DATA,
KEYB_ADDR => CPU_A(15 downto 8),
KEYB_DATA => KEYB_DO,
RESET_TICK => RESET_TICK,
NMI_TICK => NMI_TICK );
u_ONESHOT_RESET : entity work.oneshot
port map(
CLK => CLK,
RESET => RESET,
ONESHOT_IN => RESET_TICK,
ONESHOT_OUT => RESET_ONESHOT );
u_ONESHOT_NMI : entity work.oneshot
port map(
CLK => CLK,
RESET => RESET,
ONESHOT_IN => NMI_TICK,
ONESHOT_OUT => NMI_ONESHOT );
u_AY8910 : entity work.ay8910
port map(
CLK => CLK,
CLC => CLC,
RESET => CPU_RESET,
BDIR => not CPU_WR,
CS => AY_CS,
BC => CPU_A(14),
DI => CPU_DO,
DO => AY_DO,
OUT_A => AY_A,
OUT_B => AY_B,
OUT_C => AY_C );
u_DAC_L : entity work.dac
port map(
clk_i => CLK,
res_n_i => CPU_RESET,
dac_i => AUDIO_L,
dac_o => SOUND_L );
u_DAC_R : entity work.dac
port map(
clk_i => CLK,
res_n_i => CPU_RESET,
dac_i => AUDIO_R,
dac_o => SOUND_R );
AUDIO_L <= std_logic_vector(unsigned('0' & AY_A & '0') + unsigned('0' & BEEPER & AY_B));
AUDIO_R <= std_logic_vector(unsigned('0' & AY_C & '0') + unsigned('0' & BEEPER & AY_B));
CPU_RESET <= not RESET_ONESHOT;
reset_and_clock : process(CLK)
begin
if rising_edge(CLK) then
if LOCKED = '0' or MCU_READY = '0' then
TICK <= "0000";
RESET <= '1';
CPU_CLK <= '0';
CLC <= '0';
CLC_TICK <= '0';
else
CPU_CLK <= '0';
CLC <= '0';
TICK <= TICK + 1;
if TICK = "1111" then
CPU_CLK <= '1';
RESET <= '0';
CLC_TICK <= not CLC_TICK;
if CLC_TICK = '1' then
CLC <= '1';
end if;
end if;
end if;
end if;
end process;
CPU_DI <= ROM_DO when CPU_A(15 downto 14) = "00" and CPU_MREQ = '0' and AUTOMAP = '0' and CONMEM = '0'
else DIVROM_DO when CPU_A(15 downto 13) = "000" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1')
else RAM_DO when CPU_A(15 downto 13) = "001" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1')
else RAM_DO when CPU_A(15 downto 14) /= "00" and CPU_MREQ = '0'
else AY_DO when AY_CS = '0'
else in_reg when CPU_A(7 downto 0) = X"EB" and CPU_IORQ = '0'
else "111" & KEYB_DO when CPU_A(0) = '0' and CPU_IORQ = '0'
else "11111111";
VRAM_WR <= "1" when ((CPU_A(15 downto 13) = "010") or (CPU_A(15 downto 13) = "110" and PAGE(2) = '1' and PAGE(0) = '1')) and CPU_MREQ = '0' and CPU_WR = '0' else "0";
VRAM_A <= '0' & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "010" else PAGE(1) & CPU_A(12 downto 0);
RAM_A <= '1' & BANK & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1')
else "000" & PAGE & CPU_A(13 downto 0) when CPU_A(15 downto 14) = "11"
else "000" & CPU_A(14) & CPU_A;
RAM_RW <= '1' when CPU_MREQ = '0' and CPU_WR = '0' and (CPU_A(15 downto 14) /= "00" or (CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1'))) else '0';
RAM_REQ <= '1' when TICK = "0100" else '0';
AY_CS <= '0' when CPU_A(15) = '1' and CPU_A(13) = '1' and CPU_A(1) = '0' and CPU_M1 = '1' and CPU_IORQ = '0' else '1';
process(CLK)
begin
if rising_edge(CLK) then
if CPU_RESET = '0' then
SD_CS <= '1';
PAGE <= "000";
SCREEN <= '0';
ROMSEL <= '0';
DISABLE <= '0';
elsif TICK = "0011" then
if CPU_MREQ = '0' then
if CPU_M1 = '0' and CPU_A(15 downto 3) = "0001111111111" then
MAPCOND <= '0';
elsif (CPU_M1 = '0' and (CPU_A = X"0000" or CPU_A = X"0008" or CPU_A = X"0038" or CPU_A = X"0066" or CPU_A = X"04C6" or CPU_A = X"0562")) or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then
MAPCOND <= '1';
end if;
if MAPCOND = '1' or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then
AUTOMAP <= '1';
else
AUTOMAP <= '0';
end if;
end if;
if CPU_IORQ = '0' and CPU_WR = '0' then
if CPU_A(7 downto 0) = X"E7" then -- Port #E7
SD_CS <= CPU_DO(0);
elsif CPU_A(7 downto 0) = X"E3" then -- Port #E3
BANK <= CPU_DO(5 downto 0);
CONMEM <= CPU_DO(7);
MAPRAM <= CPU_DO(6) or MAPRAM;
elsif CPU_A(15) = '0' and CPU_A(1) = '0' then -- Port #7FFD
if DISABLE = '0' then -- not locked in 48K-mode
PAGE <= CPU_DO(2 downto 0);
SCREEN <= CPU_DO(3);
ROMSEL <= CPU_DO(4);
DISABLE <= CPU_DO(5);
end if;
elsif CPU_A(0) = '0' then -- Port #FE
BORDERCOLOR <= CPU_DO(2 downto 0);
BEEPER <= CPU_DO(4);
end if;
end if;
end if;
end if;
end process;
CPU_NMI <= '0' when NMI_ONESHOT = '1' and MAPCOND = '0' else '1';
sd_card : process(CLK)
begin
if rising_edge(CLK) then
if CPU_RESET = '0' then
shift_reg <= (others => '1');
in_reg <= (others => '1');
counter <= "1111"; -- Idle
elsif TICK = "0011" then
if counter = "1111" then
in_reg <= shift_reg(7 downto 0);
if CPU_IORQ = '0' and CPU_A(7 downto 0) = X"EB" then
if CPU_WR = '1' then
shift_reg <= (others => '1');
else
shift_reg <= CPU_DO & '1';
end if;
counter <= "0000";
end if;
else
counter <= counter + 1;
if counter(0) = '0' then
shift_reg(0) <= SD_MISO;
else
shift_reg <= shift_reg(7 downto 0) & '1';
end if;
end if;
end if;
end if;
end process;
SD_SCK <= counter(0);
SD_MOSI <= shift_reg(8);
end rtl;
| gpl-3.0 | 6cceae7beb16dadabfba346f8195c99b | 0.446298 | 3.276246 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_keyboard_scanner.vhdl | 1 | 5,609 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
shift_pressed : out std_logic;
control_pressed : out std_logic;
break_pressed : out std_logic;
key_held : out std_logic;
keycode : out std_logic_vector(5 downto 0);
other_key_irq : out std_logic
);
end pokey_keyboard_scanner;
architecture vhdl of pokey_keyboard_scanner is
signal bincnt_next : std_logic_vector(5 downto 0);
signal bincnt_reg : std_logic_vector(5 downto 0);
signal break_pressed_next : std_logic;
signal break_pressed_reg : std_logic;
signal shift_pressed_next : std_logic;
signal shift_pressed_reg : std_logic;
signal control_pressed_next : std_logic;
signal control_pressed_reg : std_logic;
signal compare_latch_next : std_logic_vector(5 downto 0);
signal compare_latch_reg : std_logic_vector(5 downto 0);
signal keycode_latch_next : std_logic_vector(5 downto 0);
signal keycode_latch_reg : std_logic_vector(5 downto 0);
signal irq_next : std_logic;
signal irq_reg : std_logic;
signal key_held_next : std_logic;
signal key_held_reg : std_logic;
signal my_key : std_logic;
signal state_next : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(1 downto 0);
constant state_wait_key : std_logic_vector(1 downto 0) := "00";
constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
constant state_valid_key : std_logic_vector(1 downto 0) := "10";
constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
bincnt_reg <= (others=>'0');
break_pressed_reg <= '0';
shift_pressed_reg <= '0';
control_pressed_reg <= '0';
compare_latch_reg <= (others=>'0');
keycode_latch_reg <= (others=>'1');
key_held_reg <= '0';
state_reg <= state_wait_key;
irq_reg <= '0';
elsif (clk'event and clk = '1') then
bincnt_reg <= bincnt_next;
state_reg <= state_next;
break_pressed_reg <= break_pressed_next;
shift_pressed_reg <= shift_pressed_next;
control_pressed_reg <= control_pressed_next;
compare_latch_reg <= compare_latch_next;
keycode_latch_reg <= keycode_latch_next;
key_held_reg <= key_held_next;
state_reg <= state_next;
irq_reg <= irq_next;
end if;
end process;
process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
begin
bincnt_next <= bincnt_reg;
state_next <= state_reg;
compare_latch_next <= compare_latch_reg;
irq_next <= '0';
break_pressed_next <= break_pressed_reg;
shift_pressed_next <= shift_pressed_reg;
control_pressed_next <= control_pressed_reg;
keycode_latch_next <= keycode_latch_reg;
key_held_next <= key_held_reg;
my_key <= '0';
if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
my_key <= '1';
end if;
if (enable = '1' and scan_enable='1') then
bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
key_held_next<= '0';
case state_reg is
when state_wait_key =>
if (keyboard_response(0) = '0') then -- detected key press
state_next <= state_key_bounce;
compare_latch_next <= bincnt_reg;
end if;
when state_key_bounce =>
if (keyboard_response(0) = '0') then -- detected key press
if (my_key = '1') then -- same key
keycode_latch_next <= compare_latch_reg;
irq_next <= '1';
key_held_next<= '1';
state_next <= state_valid_key;
else -- different key (multiple keys pressed)
state_next <= state_wait_key;
end if;
else -- key not pressed
if (my_key = '1') then -- same key, no longer pressed
state_next <= state_wait_key;
end if;
end if;
when state_valid_key =>
key_held_next<= '1';
if (my_key = '1') then -- only response to my key
if (keyboard_response(0) = '1') then -- no longer pressed
state_next <= state_key_debounce;
end if;
end if;
when state_key_debounce =>
if (my_key = '1') then
state_next <= state_wait_key;
end if;
when others=>
state_next <= state_wait_key;
end case;
if (bincnt_reg(3 downto 0) = "0000") then
case bincnt_reg(5 downto 4) is
when "11" =>
break_pressed_next <= not(keyboard_response(1)); --0x30
when "01" =>
shift_pressed_next <= not(keyboard_response(1)); --0x10
when "00" =>
control_pressed_next <= not(keyboard_response(1)); -- 0x00
when others =>
--
end case;
end if;
end if;
end process;
-- outputs
keyboard_scan <= not(bincnt_reg);
key_held <= key_held_reg;
keycode <= keycode_latch_reg;
break_pressed <= break_pressed_reg;
shift_pressed <= shift_pressed_reg;
control_pressed <= control_pressed_reg;
other_key_irq <= irq_reg;
end vhdl;
| gpl-3.0 | ebf18e809da7579c6bb3619438e325f5 | 0.636655 | 3.04506 | false | false | false | false |
dqydj/PaperBack_EPaper_Display | firmware_VGA/FPGA/converter_firmware.vhd | 1 | 5,772 | library IEEE;
use IEEE.std_logic_1164.all;
entity converter_firmware is
port (
CLK0: inout std_logic;
-- Power Lines
NEG_CTRL: out std_logic;
POS_CTRL: out std_logic;
SMPS_CTRL: out std_logic; -- Active low
-- Control Lines
CKV: out std_logic;
SPV: out std_logic;
GMODE: out std_logic;
SPH: out std_logic;
OE: out std_logic;
-- Clocks/Edges
CL: out std_logic;
LE: out std_logic;
DATA: out std_logic_vector(7 downto 0);
-- Memory
ADDR: out std_logic_vector(18 downto 0);
IO: inout std_logic_vector(7 downto 0);
MEM_OE: out std_logic; -- Active low
MEM_WE: inout std_logic; -- Active low
MEM_CE: out std_logic; -- Active low
-- VGA Capture
DCK: in std_logic;
HSYNC: in std_logic;
VSYNC: in std_logic;
RED: in std_logic_vector(7 downto 4);
GREEN: in std_logic_vector(7 downto 4);
BLUE: in std_logic_vector(7 downto 4);
-- SWITCH Capture
SW: inout std_logic_vector(3 downto 1);
--VGA Debug
MEM_WE2: inout std_logic;
DCK_OUT: out std_logic;
HS_OUT: out std_logic;
VS_OUT: out std_logic;
-- SWITCH Debug
SW1: out std_logic := '0';
SW2: out std_logic := '0';
SW3: out std_logic := '0'
);
end converter_firmware;
architecture Behavioral of converter_firmware is
COMPONENT FrameWriter
port(
-- Input from above
CLK0: in std_logic;
-- User switches
SW: in std_logic_vector(3 downto 1);
-- Power Lines
NEG_CTRL: out std_logic := '0';
POS_CTRL: out std_logic := '0';
SMPS_CTRL: out std_logic := '1'; -- Active low
-- Control Lines
CKV: out std_logic := '1';
SPV: out std_logic := '0';
GMODE: out std_logic := '0';
SPH: out std_logic := '0';
OE: out std_logic := '0';
-- Clocks/Edges
CL: out std_logic := '0';
LE: out std_logic := '0';
-- Data
DATA: out std_logic_vector(7 downto 0) := "00000000";
-- Memory
ADDR: out std_logic_vector(18 downto 0);
IO: inout std_logic_vector(7 downto 0);
MEM_OE: out std_logic := '1'; -- Active low
MEM_WE: out std_logic := '1'; -- Active low
MEM_CE: out std_logic := '1'; -- Active low
-- Control State
FRAME_GRAB_DONE: in std_logic;
FRAME_WRITE_DONE: out std_logic;
READY_WRITE: inout std_logic
);
END COMPONENT;
COMPONENT FrameGrabber
port(
-- Memory
ADDR: out std_logic_vector(18 downto 0);
IO: inout std_logic_vector(7 downto 0);
MEM_OE: out std_logic := '1'; -- Active low
MEM_WE: out std_logic := '1'; -- Active low
MEM_CE: out std_logic := '1'; -- Active low
-- VGA
HSYNC: in std_logic;
VSYNC: in std_logic;
DCLK: in std_logic;
--RED: in std_logic_vector(7 downto 4);
GREEN: in std_logic_vector(7 downto 4);
--BLUE: in std_logic_vector(7 downto 4);
-- Control State
FRAME_GRAB_DONE: out std_logic;
FRAME_WRITE_DONE: in std_logic
);
END COMPONENT;
COMPONENT OSCC
PORT (
OSC:OUT std_logic
);
END COMPONENT;
-- Mux Memory Signals for Grabber
signal MEM_WE_GRAB, MEM_CE_GRAB, MEM_OE_GRAB : std_logic;
signal ADDR_GRAB : std_logic_vector(18 downto 0);
signal IO_GRAB : std_logic_vector(7 downto 0);
-- Mux Memory Signals for ePD
signal MEM_WE_WRITE, MEM_CE_WRITE, MEM_OE_WRITE : std_logic;
signal ADDR_WRITE : std_logic_vector(18 downto 0);
signal IO_WRITE : std_logic_vector(7 downto 0);
-- State
signal FRAME_GRAB_DONE, FRAME_WRITE_DONE, READY_WRITE : std_logic;
begin
-- Internal FPGA Clock
OSCInst0: OSCC PORT MAP (
OSC => CLK0
);
-- User switch. Doesn't really need to be in a process...
Switcher: process(
SW
)
begin
SW1 <= SW(1);
SW2 <= SW(2);
SW3 <= SW(3);
end process;
-- Control which process has the memory...
MemoryController: process(
READY_WRITE,
ADDR_WRITE,
MEM_OE_WRITE,
MEM_WE_WRITE,
MEM_CE_WRITE,
IO_GRAB,
ADDR_GRAB,
MEM_OE_GRAB,
MEM_WE_GRAB,
MEM_CE_GRAB,
IO
)
begin
if (READY_WRITE = '1') then
IO <= "ZZZZZZZZ";
IO_WRITE <= IO;
ADDR <= ADDR_WRITE;
MEM_OE <= MEM_OE_WRITE;
MEM_WE <= '1'; -- We should never change this in here.
--MEM_WE <= MEM_WE_WRITE;
MEM_CE <= MEM_CE_WRITE;
else
IO <= IO_GRAB;
ADDR <= ADDR_GRAB;
MEM_OE <= '1'; -- We should never change this in here.
--MEM_OE <= MEM_OE_GRAB;
MEM_WE <= MEM_WE_GRAB;
MEM_CE <= MEM_CE_GRAB;
end if;
end process; -- End MemoryController
-- The Frame writing logic...
Inst_FrameWriter: FrameWriter PORT MAP(
-- Internal Clock
CLK0 => CLK0,
-- User Switches
SW => SW,
-- EPD Lines
NEG_CTRL => NEG_CTRL,
POS_CTRL => POS_CTRL,
SMPS_CTRL => SMPS_CTRL,
CKV => CKV,
SPV => SPV,
GMODE => GMODE,
SPH => SPH,
OE => OE,
CL => CL,
LE => LE,
DATA => DATA,
-- Muxed
ADDR => ADDR_WRITE,
IO => IO_WRITE,
MEM_OE => MEM_OE_WRITE,
MEM_WE => MEM_WE_WRITE,
MEM_CE => MEM_CE_WRITE,
-- State
FRAME_GRAB_DONE => FRAME_GRAB_DONE,
FRAME_WRITE_DONE => FRAME_WRITE_DONE,
READY_WRITE => READY_WRITE
);
-- The Frame grabbing logic from VGA...
-- Compatible with Analog Devices 9883 or MST 9883
-- or others in this family.
Inst_FrameGrabber: FrameGrabber PORT MAP(
-- Muxed
ADDR => ADDR_GRAB,
IO => IO_GRAB,
MEM_OE => MEM_OE_GRAB,
MEM_WE => MEM_WE_GRAB,
MEM_CE => MEM_CE_GRAB,
-- Direct
HSYNC => HSYNC,
VSYNC => VSYNC,
DCLK => DCK,
--RED => RED,
GREEN => GREEN,
--BLUE => BLUE,
-- State
FRAME_GRAB_DONE => FRAME_GRAB_DONE,
FRAME_WRITE_DONE => FRAME_WRITE_DONE
);
-- Debugging signals (will probably hide these behind a switch)
DCK_OUT <= DCK;
HS_OUT <= HSYNC;
VS_OUT <= VSYNC;
MEM_WE2 <= MEM_WE;
end Behavioral; | mit | 716a7fa93bd339891c27d652e34edd52 | 0.596154 | 2.628415 | false | false | false | false |
dqydj/PaperBack_EPaper_Display | firmware_VGA/FPGA/draw_screen.vhd | 1 | 23,350 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity FrameWriter is
port(
-- Input from above
CLK0: in std_logic;
-- Input from User
SW: in std_logic_vector(3 downto 1);
-- Power Lines
NEG_CTRL: out std_logic := '0';
POS_CTRL: out std_logic := '0';
SMPS_CTRL: out std_logic := '1'; -- Active low
-- Control Lines
CKV: out std_logic := '1';
SPV: out std_logic := '0';
GMODE: out std_logic := '0';
SPH: out std_logic := '0';
OE: out std_logic := '0';
-- Clocks/Edges
CL: out std_logic := '0';
LE: out std_logic := '0';
-- Data
DATA: out std_logic_vector(7 downto 0);
-- Memory
ADDR: out std_logic_vector(18 downto 0);
IO: in std_logic_vector(7 downto 0);
MEM_OE: out std_logic := '1'; -- Active low
MEM_WE: out std_logic := '1'; -- Active low
MEM_CE: out std_logic := '1'; -- Active low
-- Control State
FRAME_GRAB_DONE: in std_logic;
FRAME_WRITE_DONE: out std_logic;
READY_WRITE: inout std_logic
);
end FrameWriter;
architecture Behavioral of FrameWriter is
-- Screen Constants
constant SCREEN_WIDTH : integer := 800;
constant SCREEN_HEIGHT : integer := 600;
constant SCREEN_OVERSCAN : integer := (800*600)+10000;
constant SCREEN_OVERSCAN_FLAG : integer := SCREEN_OVERSCAN-100;
-- CONTRAST CONSTANTS
constant CONTRAST_START_DARK: integer := 5;
constant CONTRAST_END_DARK: integer := 13;
constant CONTRAST_END_FLASH: integer := 22;
constant CONTRAST_BP_HI: integer:=25;
constant CONTRAST_BP_MD: integer:=27;
constant CONTRAST_BP_LO: integer:=28;
signal CONTRAST_CYCLES : unsigned(0 to 5) := to_unsigned(29, 6);
-- Return a full address based on our contrast cycle
function getAddress (
ADDR_MSB : in UNSIGNED(16 downto 0);
CURR_COUNT : in UNSIGNED(5 downto 0)
) return STD_LOGIC_VECTOR IS
variable tempAddress : STD_LOGIC_VECTOR(18 downto 0);
begin
if (CURR_COUNT <= to_unsigned(CONTRAST_BP_HI, CURR_COUNT'length)) then
tempAddress := std_logic_vector(ADDR_MSB) & "00";
elsif (CURR_COUNT > to_unsigned(CONTRAST_BP_HI, CURR_COUNT'length) and CURR_COUNT <= to_unsigned(CONTRAST_BP_MD, CURR_COUNT'length)) then
tempAddress := std_logic_vector(ADDR_MSB) & "01";
elsif (CURR_COUNT > to_unsigned(CONTRAST_BP_MD, CURR_COUNT'length) and CURR_COUNT <= to_unsigned(CONTRAST_BP_LO, CURR_COUNT'length)) then
tempAddress := std_logic_vector(ADDR_MSB) & "10";
else
tempAddress := std_logic_vector(ADDR_MSB) & "11";
end if;
return tempAddress;
end getAddress;
-- HARD TIMING CONSTANTS
signal ROLLOVER_SCREEN: integer:= 96000000; -- Controls refresh rate. See logic below.
constant SAFE_REFRESH: integer:= 35000;
-- CYCLE TIMING
constant POWERON_SMPS_LO: integer:=1;
constant POWERON_NEG_HI: integer:=1201;
constant POWERON_POS_HI: integer:=13201;
constant POWERON_SPV_SPH_LO: integer:=13441;
constant OUTER_GMODE_HI: integer:=13451;
constant OUTER_SPV_HI: integer:=23051;
constant OUTER_CKV_LO: integer:=23099;
constant OUTER_CKV_HI: integer:=23147;
constant OUTER_SPV_LO: integer:=23195;
constant OUTER_CKV_LO_2: integer:=23243;
constant OUTER_CKV_HI_2: integer:=23291;
constant OUTER_SPV_HI_2: integer:=23339;
constant OUTER_CKV_LO_3: integer:=23387;
constant OUTER_CKV_HI_3: integer:=23435;
constant INNER_OE_HI_SPH_LO_MEM_ON: integer:=23459;
constant PIXEL_GET_MEMORY: integer:=23460;
constant PIXEL_CL_HI: integer:=23460;
constant PIXEL_CL_LO: integer:=23461;
constant INNER_SPH_HI_MEM_OFF: integer:=23509;
constant INNER_CL_HI: integer:=23557;
constant INNER_CL_LO: integer:=23605;
constant INNER_CL_HI_2: integer:=23653;
constant INNER_CL_LO_2: integer:=23701;
constant INNER_OE_HI_CKV_HI: integer:=23749;
constant INNER_CKV_LO: integer:=23797;
constant INNER_OE_LO: integer:=23845;
constant INNER_CL_HI_3: integer:=23893;
constant INNER_CL_LO_3: integer:=23941;
constant INNER_CL_HI_4: integer:=23989;
constant INNER_CL_LO_4: integer:=24037;
constant INNER_CKV_HI: integer:=24085;
constant INNER_LE_HI: integer:=24133;
constant INNER_CL_HI_5: integer:=24181;
constant INNER_CL_LO_5: integer:=24229;
constant INNER_CL_HI_6: integer:=24277;
constant INNER_CL_LO_6: integer:=24325;
constant INNER_LE_LO: integer:=24373;
constant INNER_CL_HI_7: integer:=24421;
constant INNER_CL_LO_7: integer:=24469;
constant INNER_CL_HI_8: integer:=24517;
constant INNER_CL_LO_8: integer:=24565;
constant OUTER_OE_HI_SPH_LO: integer:=24613;
constant PIXEL2_CL_HI: integer:=24614;
constant PIXEL2_CL_LO: integer:=24615;
constant OUTER_SPH_HI: integer:=24663;
constant OUTER_CL_HI: integer:=24711;
constant OUTER_CL_LO: integer:=24759;
constant OUTER_CL_HI_2: integer:=24807;
constant OUTER_CL_LO_2: integer:=24855;
constant OUTER_OE_HI_CKV_HI: integer:=24903;
constant OUTER_CKV_LO_4: integer:=24951;
constant OUTER_OE_LO: integer:=24999;
constant OUTER_CL_HI_3: integer:=25047;
constant OUTER_CL_LO_3: integer:=25095;
constant OUTER_CL_HI_4: integer:=25143;
constant OUTER_CL_LO_4: integer:=25191;
constant OUTER_OE_LO_CKV_LO: integer:=25239;
constant OUTER_CKV_HI_5: integer:=26199;
constant OUTER_CKV_LO_5: integer:=27159;
constant OUTER_GMODE_LO: integer:=27207;
constant POWEROFF_POS_LO: integer:=27255;
constant POWEROFF_NEG_LO: integer:=27495;
constant POWEROFF_SMPS_HI: integer:=29895;
-- LOOP CONSTANTS
constant START_INNER_LOOP: integer:= OUTER_CKV_HI_3 +1;
constant END_INNER_LOOP: integer:= INNER_CL_LO_8 +1;
constant START_PIXEL_LOOP: integer:= INNER_OE_HI_SPH_LO_MEM_ON +1;
constant END_PIXEL_LOOP: integer:= PIXEL_CL_LO +1;
constant START_PIXEL2_LOOP: integer:= OUTER_OE_HI_SPH_LO +1;
constant END_PIXEL2_LOOP: integer:= PIXEL2_CL_LO +1;
constant START_OUTER_LOOP: integer:= POWERON_SPV_SPH_LO +1;
constant END_OUTER_LOOP: integer:= OUTER_GMODE_LO +1;
-- Other Signals
signal reset_clk: unsigned(0 to 2) := (others => '0');
signal timer: unsigned(0 to 27) := (others => '0');
signal cycle: std_logic := '0';
-- Loop Counters
signal COLUMN: unsigned(0 to 9) := (others => '0');
signal ROW: unsigned(0 to 9) := (others => '0');
signal CONTRAST: unsigned(0 to 5) := (others => '0');
signal MEM_ADDR: unsigned(16 downto 0) := (others => '0');
signal FULL_ADDR: unsigned(18 downto 0) := (others => '0');
-- State Frame Write
signal CHECK_GRAB_DONE: std_logic := '0';
begin
-- Internal FPGA Clock Logic
process(CLK0)
begin
if(rising_edge(CLK0)) then -- Do stuff on clock
-----------------------------------------------------------------------
if (reset_clk /= "111") then
reset_clk <= reset_clk + 1;
end if;
if (reset_clk = "001") then
-- Reset everything to safe
SMPS_CTRL <= '1';
NEG_CTRL <= '0';
POS_CTRL <= '0';
CKV <= '1';
SPV <= '0';
GMODE <= '0';
SPH <= '0';
OE <= '0';
CL <= '0';
LE <= '0';
-- Flags
CHECK_GRAB_DONE <= '0';
READY_WRITE <= '0';
FRAME_WRITE_DONE <= '1';
MEM_ADDR <= to_unsigned(0, MEM_ADDR'length);
end if;
if (READY_WRITE = '0') then -- Start screen write
READY_WRITE <= CHECK_GRAB_DONE;
CHECK_GRAB_DONE <= FRAME_GRAB_DONE;
else
if (timer = to_unsigned(0, timer'length)) then
-- Reset everything to safe
SMPS_CTRL <= '1';
NEG_CTRL <= '0';
POS_CTRL <= '0';
CKV <= '1';
SPV <= '0';
GMODE <= '0';
SPH <= '0';
OE <= '0';
CL <= '0';
LE <= '0';
--DATA <= "00000000";
MEM_ADDR <= to_unsigned(0, MEM_ADDR'length);
FRAME_WRITE_DONE <= '0';
CHECK_GRAB_DONE <= '0';
MEM_CE <= '1';
MEM_WE <= '1';
MEM_OE <= '1';
ADDR <= (others => 'Z');
-- Set the refresh rate and color depth
-- (Todo: move these magic numbers)
case SW is
when "000" =>
CONTRAST_CYCLES <= to_unsigned(29, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 240000000;
when "001" =>
CONTRAST_CYCLES <= to_unsigned(29, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 120000000;
when "010" =>
CONTRAST_CYCLES <= to_unsigned(26, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 240000000;
when "011" =>
CONTRAST_CYCLES <= to_unsigned(26, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 120000000;
when "100" =>
CONTRAST_CYCLES <= to_unsigned(26, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 15000000;
when "101" =>
CONTRAST_CYCLES <= to_unsigned(24, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 240000000;
when "110" =>
CONTRAST_CYCLES <= to_unsigned(24, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 60000000;
when others =>
CONTRAST_CYCLES <= to_unsigned(24, CONTRAST_CYCLES'length);
ROLLOVER_SCREEN <= 15000000;
end case;
end if;
-- Start cycle, SMPS On
if (timer = to_unsigned(POWERON_SMPS_LO, timer'length)) then
SMPS_CTRL <= '0';
end if;
-- NEG Voltage On
if (timer = to_unsigned(POWERON_NEG_HI, timer'length)) then
NEG_CTRL <= '1';
end if;
-- POS Voltage On
if (timer = to_unsigned(POWERON_POS_HI, timer'length)) then
POS_CTRL <= '1';
end if;
-- SPV/SPH On
if (timer = to_unsigned(POWERON_SPV_SPH_LO, timer'length)) then
SPV <= '1';
SPH <= '1';
end if;
-------------------------------------------------------------------
-- Outer Loop Start
-------------------------------------------------------------------
------------------------------------------------------- VSCAN Start
if (timer = to_unsigned(OUTER_GMODE_HI, timer'length)) then
GMODE <= '1';
end if;
-- SPV High
if (timer = to_unsigned(OUTER_SPV_HI, timer'length)) then
SPV <= '1';
end if;
-- CKV Low
if (timer = to_unsigned(OUTER_CKV_LO, timer'length)) then
CKV <= '0';
end if;
-- CKV Hi
if (timer = to_unsigned(OUTER_CKV_HI, timer'length)) then
CKV <= '1';
end if;
-- SPV Low
if (timer = to_unsigned(OUTER_SPV_LO, timer'length)) then
SPV <= '0';
end if;
-- CKV Low
if (timer = to_unsigned(OUTER_CKV_LO_2, timer'length)) then
CKV <= '0';
end if;
-- CKV Hi
if (timer = to_unsigned(OUTER_CKV_HI_2, timer'length)) then
CKV <= '1';
end if;
-- SPV High
if (timer = to_unsigned(OUTER_SPV_HI_2, timer'length)) then
SPV <= '1';
end if;
-- CKV Low
if (timer = to_unsigned(OUTER_CKV_LO_3, timer'length)) then
CKV <= '0';
end if;
-- CKV Hi
if (timer = to_unsigned(OUTER_CKV_HI_3, timer'length)) then
CKV <= '1';
end if;
--------------------------------------------------- END VSCAN Start
---------------------------------------------------------------
-- Start Inner Loop
---------------------------------------------------------------
--------------------------------------------------- HSCAN Start
-- OE Hi, SPH low, MEM On & Output & not write
if (timer = to_unsigned(INNER_OE_HI_SPH_LO_MEM_ON, timer'length)) then
OE <= '1';
SPH <= '0';
MEM_OE <= '0';
MEM_WE <= '1';
MEM_CE <= '0';
--DATA <= "01010101";
DATA <= "ZZZZZZZZ";
end if;
----------------------------------------------- END HSCAN Start
-----------------------------------------------------------
-- Start Pixel Loop
-----------------------------------------------------------
-- PIXEL_GET_MEMORY
if (timer = to_unsigned(PIXEL_GET_MEMORY, timer'length)) then
ADDR <= getAddress(MEM_ADDR, CONTRAST);
if (CONTRAST >= CONTRAST_END_FLASH) then -- >
DATA <= IO;
else
if (CONTRAST >= CONTRAST_START_DARK and CONTRAST <= CONTRAST_END_DARK) then
DATA <= "01010101";
else
DATA <= "10101010";
end if;
end if;
end if;
-- CL Hi
if (timer = to_unsigned(PIXEL_CL_HI, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(PIXEL_CL_LO, timer'length)) then
CL <= '0';
end if;
-- Do all the columns
if (timer = to_unsigned(END_PIXEL_LOOP, timer'length)) then
if (COLUMN < SCREEN_WIDTH) then
timer <= to_unsigned(START_PIXEL_LOOP, timer'length);
COLUMN <= COLUMN + to_unsigned(4, COLUMN'length);
MEM_ADDR <= MEM_ADDR + 1;
else
timer <= timer + 1;
end if;
end if;
-----------------------------------------------------------
-- End Pixel Loop
-----------------------------------------------------------
--------------------------------------------------- HSCAN End
-- SPH Hi
if (timer = to_unsigned(INNER_SPH_HI_MEM_OFF, timer'length)) then
SPH <= '1';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_2, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_2, timer'length)) then
CL <= '0';
end if;
----------------------------------------------- END HSCAN End
-------------------------------------------- Output Row Start
----- Output the row first
-- OE Hi, CKV Hi
if (timer = to_unsigned(INNER_OE_HI_CKV_HI, timer'length)) then
OE <= '1';
CKV <= '1';
end if;
-- CKV Lo
if (timer = to_unsigned(INNER_CKV_LO, timer'length)) then
CKV <= '0';
end if;
-- OE Lo
if (timer = to_unsigned(INNER_OE_LO, timer'length)) then
OE <= '0';
end if;
----- Now start the next row
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_3, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_3, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_4, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_4, timer'length)) then
CL <= '0';
end if;
-- CKV Hi
if (timer = to_unsigned(INNER_CKV_HI, timer'length)) then
CKV <= '1';
end if;
---------------------------------------------- Output Row End
---------------------------------------------- Latch Row Start
-- LE Hi
if (timer = to_unsigned(INNER_LE_HI, timer'length)) then
LE <= '1';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_5, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_5, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_6, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_6, timer'length)) then
CL <= '0';
end if;
-- LE Lo
if (timer = to_unsigned(INNER_LE_LO, timer'length)) then
LE <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_7, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_7, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(INNER_CL_HI_8, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(INNER_CL_LO_8, timer'length)) then
CL <= '0';
end if;
------------------------------------------------ Latch Row End
-- Do all the rows
if (timer = to_unsigned(END_INNER_LOOP, timer'length)) then
if (ROW < SCREEN_HEIGHT) then
timer <= to_unsigned(START_INNER_LOOP, timer'length);
ROW <= ROW + to_unsigned(1, ROW'length);
-- RESET Column Counter
COLUMN <= (others => '0');
else
timer <= timer + 1;
end if;
end if;
---------------------------------------------------------------
-- End Inner Loop
---------------------------------------------------------------
--------------------------------------------------- VSCAN END Start
-- VSCAN END Start
----------------------------------------------------- HSCAN Start 2
-- OE Hi, SPH low
if (timer = to_unsigned(OUTER_OE_HI_SPH_LO, timer'length)) then
OE <= '1';
SPH <= '0';
MEM_OE <= '1';
-- RESET Column Counter
COLUMN <= (others => '0');
end if;
------------------------------------------------- END HSCAN Start 2
---------------------------------------------------------------
-- Start Pixel Loop2
-- This is for the row off the end of the screen.
---------------------------------------------------------------
-- CL Hi
if (timer = to_unsigned(PIXEL2_CL_HI, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(PIXEL2_CL_LO, timer'length)) then
CL <= '0';
end if;
-- Do all the columns
if (timer = to_unsigned(END_PIXEL2_LOOP, timer'length)) then
if (COLUMN < SCREEN_WIDTH) then
timer <= to_unsigned(START_PIXEL2_LOOP, timer'length);
COLUMN <= COLUMN + 4; --to_unsigned(4, COLUMN'length);
else
timer <= timer + 1;
end if;
end if;
---------------------------------------------------------------
-- End Pixel Loop2
---------------------------------------------------------------
-------------------------------------------------------- HSCAN End2
-- SPH Hi
if (timer = to_unsigned(OUTER_SPH_HI, timer'length)) then
SPH <= '1';
end if;
-- CL Hi
if (timer = to_unsigned(OUTER_CL_HI, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(OUTER_CL_LO, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(OUTER_CL_HI_2, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(OUTER_CL_LO_2, timer'length)) then
CL <= '0';
end if;
---------------------------------------------------- END HSCAN End2
-- This point in the C++ we'd turn interrupts and finish off this
-- particular cycle. OE, CKV, GMODE all get flipped.
-- OE, CKV Hi
if (timer = to_unsigned(OUTER_OE_HI_CKV_HI, timer'length)) then
OE <= '1';
CKV <= '1';
end if;
-- CKV Lo
if (timer = to_unsigned(OUTER_CKV_LO_4, timer'length)) then
CKV <= '0';
end if;
-- OE Lo
if (timer = to_unsigned(OUTER_OE_LO, timer'length)) then
OE <= '0';
end if;
-- Then we would reenable interrupts here and run the clock.
-- CL Hi
if (timer = to_unsigned(OUTER_CL_HI_3, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(OUTER_CL_LO_3, timer'length)) then
CL <= '0';
end if;
-- CL Hi
if (timer = to_unsigned(OUTER_CL_HI_4, timer'length)) then
CL <= '1';
end if;
-- CL Lo
if (timer = to_unsigned(OUTER_CL_LO_4, timer'length)) then
CL <= '0';
end if;
-- OE, CKV Double Sure of Low (!)
if (timer = to_unsigned(OUTER_OE_LO_CKV_LO, timer'length)) then
OE <= '0';
CKV <= '0';
end if;
-- CKV Hi
if (timer = to_unsigned(OUTER_CKV_HI_5, timer'length)) then
CKV <= '1';
end if;
-- CKV Lo
if (timer = to_unsigned(OUTER_CKV_LO_5, timer'length)) then
CKV <= '0';
end if;
-- GMODE Lo
if (timer = to_unsigned(OUTER_GMODE_LO, timer'length)) then
GMODE <= '0';
end if;
----------------------------------------------------- VSCAN END end
-------------------------------------------------------------------
-- End Outer Loop
-------------------------------------------------------------------
if (timer = to_unsigned(END_OUTER_LOOP, timer'length)) then
if (CONTRAST < CONTRAST_CYCLES) then
COLUMN <= to_unsigned(0, COLUMN'length);
ROW <= to_unsigned(0, ROW'length);
timer <= to_unsigned(START_OUTER_LOOP, timer'length);
CONTRAST <= CONTRAST + 1;
MEM_ADDR <= to_unsigned(0, MEM_ADDR'length);
else
timer <= timer + 1;
end if;
end if;
-- Power Off.
-- End cycle, POS Voltage Off
if (timer = to_unsigned(POWEROFF_POS_LO, timer'length)) then
POS_CTRL <= '0';
end if;
-- NEG Voltage Off
if (timer = to_unsigned(POWEROFF_NEG_LO, timer'length)) then
NEG_CTRL <= '0';
end if;
-- SMPS Off, End of Cycle
if (timer = to_unsigned(POWEROFF_SMPS_HI, timer'length)) then
SMPS_CTRL <= '1';
end if;
if (timer = to_unsigned(SAFE_REFRESH, timer'length)) then
-- Reset everything to safe in case we missed one
SMPS_CTRL <= '1';
NEG_CTRL <= '0';
POS_CTRL <= '0';
CKV <= '1';
SPV <= '0';
GMODE <= '0';
SPH <= '0';
OE <= '0';
CL <= '0';
LE <= '0';
-- Data Cycles
cycle <= not cycle;
COLUMN <= to_unsigned(0, COLUMN'length);
ROW <= to_unsigned(0, ROW'length);
CONTRAST <= to_unsigned(0, CONTRAST'length);
DATA <= "00000000";
MEM_ADDR <= to_unsigned(0, MEM_ADDR'length);
MEM_CE <= '1';
-- Flags
CHECK_GRAB_DONE <= '0';
FRAME_WRITE_DONE <= '0';
end if;
-- Dirty hack!
if (
timer /= to_unsigned(END_INNER_LOOP, timer'length) and
timer /= to_unsigned(END_PIXEL_LOOP, timer'length) and
timer /= to_unsigned(END_PIXEL2_LOOP, timer'length) and
timer /= to_unsigned(END_OUTER_LOOP, timer'length) and
timer /= to_unsigned(ROLLOVER_SCREEN, timer'length)
) then
timer <= timer + 1; -- Increase timer.
end if;
if (timer = to_unsigned(ROLLOVER_SCREEN-100, timer'length)) then
FRAME_WRITE_DONE <= '1';
end if;
-- Roll over when we tell you to (Assuming 18-24 MHz.)
if (timer = to_unsigned(ROLLOVER_SCREEN, timer'length)) then
timer <= to_unsigned(0, timer'length);
COLUMN <= to_unsigned(0, COLUMN'length);
ROW <= to_unsigned(0, ROW'length);
MEM_ADDR <= to_unsigned(0, MEM_ADDR'length);
CHECK_GRAB_DONE <= '0';
READY_WRITE <= '0';
-- Done with our thing, see you after the next frame grab!
end if;
end if; -- End Global State '1'
end if; -- End Rising Edge CLK0
end process;
end Behavioral; | mit | e83c721f23648f7090d483593436a8bb | 0.511006 | 3.210946 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05400_good.vhd | 1 | 2,921 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05400_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of internal tristate: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05400_good is
port (
i_A : in std_logic_vector(3 downto 0); -- Input data of tristate block
i_Sel : in std_logic_vector(3 downto 0); -- Mux select
o_B : out std_logic -- Single module output
);
end STD_05400_good;
architecture Behavioral of STD_05400_good is
signal B : std_logic; -- Module output
begin
-- Simple Mux asynchronous process, output depends on Mux select
P_Mux:process(i_A, i_Sel)
begin
if (i_Sel="00") then
B <= i_A(0);
elsif (i_Sel="01") then
B <= i_A(1);
elsif (i_Sel="10") then
B <= i_A(2);
else
B <= i_A(3);
end if;
end process;
o_B <= B;
end Behavioral;
--CODE | gpl-3.0 | 5479cf3a408a2ba3b45ac4aa9c0aef5d | 0.482027 | 4.480061 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult_tb.vhd | 1 | 6,347 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the real_const_mult.
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.tb_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_tb1 of real_const_mult_tb is
/* generics' constants 1 */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true); --default
constant SPEED_opt : T_speed_tb := (t_min, true); --exception: value not set
constant ROUND_STYLE_opt : T_round_style_tb := (fixed_round, true);--default
constant ROUND_TO_BIT_opt : integer_exc_tb := (-13, true); --exception: value not set
constant MAX_ERROR_PCT_opt : real_exc_tb := (0.01, false); --exception: value not set
constant MULTIPLICANDS : real_v := (44.0, 130.0, 172.0); --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_ROUND_STYLE_opt : T_round_style := value_used(ROUND_STYLE_opt, fixed_truncate);
constant used_ROUND_TO_BIT_opt : integer_exc := value_used(ROUND_TO_BIT_opt);
constant used_MAX_ERROR_PCT_opt : real_exc := value_used(MAX_ERROR_PCT_opt);
constant used_MULTIPLICANDS : real_v := MULTIPLICANDS;
/* constants 2 */
/**************************************************************************************************/
constant NORM_IN_HIGH : integer := 0;
constant NORM_IN_LOW : integer := -5;
constant IN_HIGH : integer := NORM_IN_HIGH + SULV_NEW_ZERO;
constant IN_LOW : integer := NORM_IN_LOW + SULV_NEW_ZERO;
constant NORM_OUT_HIGH : integer := real_const_mult_OH(used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS,
NORM_IN_HIGH,
NORM_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant NORM_OUT_LOW : integer := real_const_mult_OL(used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS,
NORM_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant OUT_HIGH : integer := SULV_NEW_ZERO + NORM_OUT_HIGH;
constant OUT_LOW : integer := SULV_NEW_ZERO + NORM_OUT_LOW;
/* signals 3 */
/**************************************************************************************************/
--IN
signal input : std_ulogic_vector(IN_HIGH DOWNTO IN_LOW);
signal clk : std_ulogic := '1';
signal valid_input : std_ulogic := '1';
--OUT
signal output : sulv_v(1 to MULTIPLICANDS'length)(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_1:
entity work.real_const_mult
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
SPEED_opt => used_SPEED_opt,
ROUND_STYLE_opt => used_ROUND_STYLE_opt,
ROUND_TO_BIT_opt => used_ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => used_MAX_ERROR_PCT_opt,
MULTIPLICANDS => used_MULTIPLICANDS)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
--pragma translate off
--synthesis translate_off
process (clk)
begin
clk <= not clk after 2 ps;
end process;
process
begin
valid_input <= '0';
input <= (others => '0');
wait for 10 ps;
valid_input <= '1';
input <= (SULV_NEW_ZERO => '1', others => '0');
wait for 4 ps;
valid_input <= '0';
input <= (others => '0');
wait;
end process;
--pragma translate on
--synthesis translate_on
end architecture; | mit | 4f6779b9be67ed6d3e3e416f18423255 | 0.387296 | 4.74305 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/gtia.vhdl | 1 | 57,191 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia IS
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ANTIC_FETCH : in std_logic;
CPU_ENABLE_ORIGINAL : in std_logic; -- on cycle data is ready
RESET_N : IN STD_LOGIC;
PAL : IN STD_LOGIC;
-- ANTIC interface
COLOUR_CLOCK_ORIGINAL : in std_logic;
COLOUR_CLOCK : in std_logic;
COLOUR_CLOCK_HIGHRES : in std_logic;
AN : IN STD_LOGIC_VECTOR(2 downto 0);
-- keyboard interface
CONSOL_START : IN STD_LOGIC;
CONSOL_SELECT : IN STD_LOGIC;
CONSOL_OPTION : IN STD_LOGIC;
-- keyboard interface
TRIG0 : IN STD_LOGIC;
TRIG1 : IN STD_LOGIC;
TRIG2 : IN STD_LOGIC;
TRIG3 : IN STD_LOGIC;
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- TO scandoubler...
COLOUR_out : out std_logic_vector(7 downto 0);
VSYNC : out std_logic;
HSYNC : out std_logic;
BLANK : out std_logic;
BURST : out std_logic;
START_OF_FIELD : out std_logic;
ODD_LINE : out std_logic;
-- To speaker
sound : out std_logic
);
END gtia;
ARCHITECTURE vhdl OF gtia IS
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
component simple_counter IS
generic
(
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component wide_delay_line IS
generic(COUNT : natural := 1; WIDTH : natural :=1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
END component;
component gtia_player IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : in std_logic;
COLOUR_ENABLE : IN STD_LOGIC;
LIVE_POSITION : in std_logic_vector(7 downto 0); -- counter ticks as display is drawn
PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
SIZE : in std_logic_vector(1 downto 0);
bitmap : in std_logic_vector(7 downto 0);
output : out std_logic
);
END component;
component gtia_priority IS
PORT
(
CLK : in std_logic;
colour_enable : in std_logic;
PRIOR : in std_logic_vector(7 downto 0);
P0 : in std_logic;
P1 : in std_logic;
P2 : in std_logic;
P3 : in std_logic;
PF0 : in std_logic;
PF1 : in std_logic;
PF2 : in std_logic;
PF3 : in std_logic;
BK : in std_logic;
P0_OUT : out std_logic;
P1_OUT : out std_logic;
P2_OUT : out std_logic;
P3_OUT : out std_logic;
PF0_OUT : out std_logic;
PF1_OUT : out std_logic;
PF2_OUT : out std_logic;
PF3_OUT : out std_logic;
BK_OUT : out std_logic
);
END component;
signal addr_decoded : std_logic_vector(31 downto 0);
signal hposp0_raw_next : std_logic_vector(7 downto 0);
signal hposp0_raw_reg : std_logic_vector(7 downto 0);
signal hposp1_raw_next : std_logic_vector(7 downto 0);
signal hposp1_raw_reg : std_logic_vector(7 downto 0);
signal hposp2_raw_next : std_logic_vector(7 downto 0);
signal hposp2_raw_reg : std_logic_vector(7 downto 0);
signal hposp3_raw_next : std_logic_vector(7 downto 0);
signal hposp3_raw_reg : std_logic_vector(7 downto 0);
signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
signal hposm0_raw_next : std_logic_vector(7 downto 0);
signal hposm0_raw_reg : std_logic_vector(7 downto 0);
signal hposm1_raw_next : std_logic_vector(7 downto 0);
signal hposm1_raw_reg : std_logic_vector(7 downto 0);
signal hposm2_raw_next : std_logic_vector(7 downto 0);
signal hposm2_raw_reg : std_logic_vector(7 downto 0);
signal hposm3_raw_next : std_logic_vector(7 downto 0);
signal hposm3_raw_reg : std_logic_vector(7 downto 0);
signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
signal hposm3_delayed_reg : std_logic_vector(7 downto 0);
signal sizep0_raw_next : std_logic_vector(1 downto 0);
signal sizep0_raw_reg : std_logic_vector(1 downto 0);
signal sizep1_raw_next : std_logic_vector(1 downto 0);
signal sizep1_raw_reg : std_logic_vector(1 downto 0);
signal sizep2_raw_next : std_logic_vector(1 downto 0);
signal sizep2_raw_reg : std_logic_vector(1 downto 0);
signal sizep3_raw_next : std_logic_vector(1 downto 0);
signal sizep3_raw_reg : std_logic_vector(1 downto 0);
signal sizem_raw_next : std_logic_vector(7 downto 0);
signal sizem_raw_reg : std_logic_vector(7 downto 0);
signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
signal sizem_delayed_reg : std_logic_vector(7 downto 0);
signal grafp0_next : std_logic_vector(7 downto 0);
signal grafp0_reg : std_logic_vector(7 downto 0);
signal grafp1_next : std_logic_vector(7 downto 0);
signal grafp1_reg : std_logic_vector(7 downto 0);
signal grafp2_next : std_logic_vector(7 downto 0);
signal grafp2_reg : std_logic_vector(7 downto 0);
signal grafp3_next : std_logic_vector(7 downto 0);
signal grafp3_reg : std_logic_vector(7 downto 0);
signal grafm_next : std_logic_vector(7 downto 0);
signal grafm_reg : std_logic_vector(7 downto 0);
signal grafm_reg10_extended : std_logic_vector(7 downto 0);
signal grafm_reg32_extended : std_logic_vector(7 downto 0);
signal grafm_reg54_extended : std_logic_vector(7 downto 0);
signal grafm_reg76_extended : std_logic_vector(7 downto 0);
signal colpm0_raw_next : std_logic_vector(7 downto 1);
signal colpm0_raw_reg : std_logic_vector(7 downto 1);
signal colpm1_raw_next : std_logic_vector(7 downto 1);
signal colpm1_raw_reg : std_logic_vector(7 downto 1);
signal colpm2_raw_next : std_logic_vector(7 downto 1);
signal colpm2_raw_reg : std_logic_vector(7 downto 1);
signal colpm3_raw_next : std_logic_vector(7 downto 1);
signal colpm3_raw_reg : std_logic_vector(7 downto 1);
signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
signal colpf0_raw_next : std_logic_vector(7 downto 1);
signal colpf0_raw_reg : std_logic_vector(7 downto 1);
signal colpf1_raw_next : std_logic_vector(7 downto 1);
signal colpf1_raw_reg : std_logic_vector(7 downto 1);
signal colpf2_raw_next : std_logic_vector(7 downto 1);
signal colpf2_raw_reg : std_logic_vector(7 downto 1);
signal colpf3_raw_next : std_logic_vector(7 downto 1);
signal colpf3_raw_reg : std_logic_vector(7 downto 1);
signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
signal colbk_raw_next : std_logic_vector(7 downto 1);
signal colbk_raw_reg : std_logic_vector(7 downto 1);
signal colbk_delayed_reg : std_logic_vector(7 downto 1);
signal prior_raw_next : std_logic_vector(7 downto 0);
signal prior_raw_reg : std_logic_vector(7 downto 0);
signal prior_delayed_reg : std_logic_vector(7 downto 0);
signal prior_delayed2_reg : std_logic_vector(7 downto 6);
signal vdelay_next : std_logic_vector(7 downto 0);
signal vdelay_reg : std_logic_vector(7 downto 0);
signal gractl_next : std_logic_vector(2 downto 0);
signal gractl_reg : std_logic_vector(2 downto 0);
signal consol_output_next : std_logic_vector(3 downto 0);
signal consol_output_reg : std_logic_vector(3 downto 0);
signal trig0_next : std_logic;
signal trig0_reg : std_logic;
signal trig1_next : std_logic;
signal trig1_reg : std_logic;
signal trig2_next : std_logic;
signal trig2_reg : std_logic;
signal trig3_next : std_logic;
signal trig3_reg : std_logic;
-- collisions
signal hitclr_write : std_logic;
signal m0pf_next : std_logic_vector(3 downto 0);
signal m0pf_reg : std_logic_vector(3 downto 0);
signal m1pf_next : std_logic_vector(3 downto 0);
signal m1pf_reg : std_logic_vector(3 downto 0);
signal m2pf_next : std_logic_vector(3 downto 0);
signal m2pf_reg : std_logic_vector(3 downto 0);
signal m3pf_next : std_logic_vector(3 downto 0);
signal m3pf_reg : std_logic_vector(3 downto 0);
signal m0pl_next : std_logic_vector(3 downto 0);
signal m0pl_reg : std_logic_vector(3 downto 0);
signal m1pl_next : std_logic_vector(3 downto 0);
signal m1pl_reg : std_logic_vector(3 downto 0);
signal m2pl_next : std_logic_vector(3 downto 0);
signal m2pl_reg : std_logic_vector(3 downto 0);
signal m3pl_next : std_logic_vector(3 downto 0);
signal m3pl_reg : std_logic_vector(3 downto 0);
signal p0pf_next : std_logic_vector(3 downto 0);
signal p0pf_reg : std_logic_vector(3 downto 0);
signal p1pf_next : std_logic_vector(3 downto 0);
signal p1pf_reg : std_logic_vector(3 downto 0);
signal p2pf_next : std_logic_vector(3 downto 0);
signal p2pf_reg : std_logic_vector(3 downto 0);
signal p3pf_next : std_logic_vector(3 downto 0);
signal p3pf_reg : std_logic_vector(3 downto 0);
signal p0pl_next : std_logic_vector(3 downto 0);
signal p0pl_reg : std_logic_vector(3 downto 0);
signal p1pl_next : std_logic_vector(3 downto 0);
signal p1pl_reg : std_logic_vector(3 downto 0);
signal p2pl_next : std_logic_vector(3 downto 0);
signal p2pl_reg : std_logic_vector(3 downto 0);
signal p3pl_next : std_logic_vector(3 downto 0);
signal p3pl_reg : std_logic_vector(3 downto 0);
-- priority
signal set_p0 : std_logic;
signal set_p1 : std_logic;
signal set_p2 : std_logic;
signal set_p3 : std_logic;
signal set_pf0 : std_logic;
signal set_pf1 : std_logic;
signal set_pf2 : std_logic;
signal set_pf3 : std_logic;
signal set_bk : std_logic;
-- ouput/sync
signal COLOUR_NEXT : std_logic_vector(7 downto 0);
signal COLOUR_REG : std_logic_vector(7 downto 0);
signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
signal vsync_next : std_logic;
signal vsync_reg : std_logic;
signal hsync_next : std_logic;
signal hsync_reg : std_logic;
signal hsync_start : std_logic;
signal hsync_end : std_logic;
signal burst_next : std_logic;
signal burst_reg : std_logic;
signal burst_start : std_logic;
signal burst_end : std_logic;
signal hblank_next : std_logic;
signal hblank_reg : std_logic;
-- visible region (no collision detection outside this)
signal visible_live : std_logic;
-- antic input decode
signal an_prev3_next : std_logic_vector(2 downto 0);
signal an_prev3_reg : std_logic_vector(2 downto 0);
signal an_prev2_next : std_logic_vector(2 downto 0);
signal an_prev2_reg : std_logic_vector(2 downto 0);
signal an_prev_next : std_logic_vector(2 downto 0);
signal an_prev_reg : std_logic_vector(2 downto 0);
signal active_bk_modify_next : std_logic_vector(7 downto 0);
signal active_bk_modify_reg : std_logic_vector(7 downto 0);
signal active_bk_valid_next : std_logic_vector(7 downto 0);
signal active_bk_valid_reg : std_logic_vector(7 downto 0);
signal active_bk_live : std_logic;
signal active_pf0_live : std_logic;
signal active_pf1_live : std_logic;
signal active_pf2_live : std_logic;
signal active_pf2_collision_live : std_logic;
signal active_pf3_live : std_logic;
signal active_pf3_collision_live : std_logic;
signal active_pm0_live : std_logic;
signal active_pm1_live : std_logic;
signal active_pm2_live : std_logic;
signal active_pm3_live : std_logic;
signal active_p0_live : std_logic;
signal active_p1_live : std_logic;
signal active_p2_live : std_logic;
signal active_p3_live : std_logic;
signal active_m0_live : std_logic;
signal active_m1_live : std_logic;
signal active_m2_live : std_logic;
signal active_m3_live : std_logic;
signal active_hr_next : std_logic_vector(1 downto 0);
signal active_hr_reg : std_logic_vector(1 downto 0);
signal highres_next : std_logic;
signal highres_reg : std_logic;
-- horizontal position counter
signal hpos_reg : std_logic_vector(7 downto 0);
signal reset_counter : std_logic;
signal counter_load_value : std_logic_vector(7 downto 0);
-- sub colour clock highres mode
signal trigger_secondhalf : std_logic;
-- pmg dma
signal grafm_dma_load : std_logic;
signal grafm_dma_next : std_logic_vector(7 downto 0);
signal grafp0_dma_load : std_logic;
signal grafp0_dma_next : std_logic_vector(7 downto 0);
signal grafp1_dma_load : std_logic;
signal grafp1_dma_next : std_logic_vector(7 downto 0);
signal grafp2_dma_load : std_logic;
signal grafp2_dma_next : std_logic_vector(7 downto 0);
signal grafp3_dma_load : std_logic;
signal grafp3_dma_next : std_logic_vector(7 downto 0);
signal odd_scanline_next : std_logic;
signal odd_scanline_reg : std_logic;
signal pmg_dma_state_next : std_logic_vector(2 downto 0);
signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
constant pmg_dma_done : std_logic_vector(2 downto 0) := "101";
constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
hposp0_raw_reg <= (others=>'0');
hposp1_raw_reg <= (others=>'0');
hposp2_raw_reg <= (others=>'0');
hposp3_raw_reg <= (others=>'0');
hposm0_raw_reg <= (others=>'0');
hposm1_raw_reg <= (others=>'0');
hposm2_raw_reg <= (others=>'0');
hposm3_raw_reg <= (others=>'0');
sizep0_raw_reg <= (others=>'0');
sizep1_raw_reg <= (others=>'0');
sizep2_raw_reg <= (others=>'0');
sizep3_raw_reg <= (others=>'0');
sizem_raw_reg <= (others=>'0');
grafp0_reg <= (others=>'0');
grafp1_reg <= (others=>'0');
grafp2_reg <= (others=>'0');
grafp3_reg <= (others=>'0');
grafm_reg <= (others=>'0');
colpm0_raw_reg <= (others=>'0');
colpm1_raw_reg <= (others=>'0');
colpm2_raw_reg <= (others=>'0');
colpm3_raw_reg <= (others=>'0');
colpf0_raw_reg <= (others=>'0');
colpf1_raw_reg <= (others=>'0');
colpf2_raw_reg <= (others=>'0');
colpf3_raw_reg <= (others=>'0');
colbk_raw_reg <= (others=>'0');
prior_raw_reg <= (others=>'0');
vdelay_reg <= (others=>'0');
gractl_reg <= (others=>'0');
consol_output_reg <= (others=>'1');
COLOUR_REG <= (OTHERS=>'0');
HRCOLOUR_REG <= (OTHERS=>'0');
vsync_reg <= '0';
hsync_reg <= '0';
burst_reg <= '0';
hblank_reg <= '0';
an_prev_reg <= (others=>'0');
an_prev2_reg <= (others=>'0');
an_prev3_reg <= (others=>'0');
highres_reg <= '0';
active_hr_reg <= (others=>'0');
trig0_reg <= '0';
trig1_reg <= '0';
trig2_reg <= '0';
trig3_reg <= '0';
odd_scanline_reg <= '0';
pmg_dma_state_reg <= pmg_dma_done;
m0pf_reg <= (others=>'0');
m1pf_reg <= (others=>'0');
m2pf_reg <= (others=>'0');
m3pf_reg <= (others=>'0');
m0pl_reg <= (others=>'0');
m1pl_reg <= (others=>'0');
m2pl_reg <= (others=>'0');
m3pl_reg <= (others=>'0');
p0pf_reg <= (others=>'0');
p1pf_reg <= (others=>'0');
p2pf_reg <= (others=>'0');
p3pf_reg <= (others=>'0');
p0pl_reg <= (others=>'0');
p1pl_reg <= (others=>'0');
p2pl_reg <= (others=>'0');
p3pl_reg <= (others=>'0');
active_bk_modify_reg <= (others=>'0');
active_bk_valid_reg <= (others=>'0');
elsif (clk'event and clk='1') then
hposp0_raw_reg <= hposp0_raw_next;
hposp1_raw_reg <= hposp1_raw_next;
hposp2_raw_reg <= hposp2_raw_next;
hposp3_raw_reg <= hposp3_raw_next;
hposm0_raw_reg <= hposm0_raw_next;
hposm1_raw_reg <= hposm1_raw_next;
hposm2_raw_reg <= hposm2_raw_next;
hposm3_raw_reg <= hposm3_raw_next;
sizep0_raw_reg <= sizep0_raw_next;
sizep1_raw_reg <= sizep1_raw_next;
sizep2_raw_reg <= sizep2_raw_next;
sizep3_raw_reg <= sizep3_raw_next;
sizem_raw_reg <= sizem_raw_next;
grafp0_reg <= grafp0_next;
grafp1_reg <= grafp1_next;
grafp2_reg <= grafp2_next;
grafp3_reg <= grafp3_next;
grafm_reg <= grafm_next;
colpm0_raw_reg <= colpm0_raw_next;
colpm1_raw_reg <= colpm1_raw_next;
colpm2_raw_reg <= colpm2_raw_next;
colpm3_raw_reg <= colpm3_raw_next;
colpf0_raw_reg <= colpf0_raw_next;
colpf1_raw_reg <= colpf1_raw_next;
colpf2_raw_reg <= colpf2_raw_next;
colpf3_raw_reg <= colpf3_raw_next;
colbk_raw_reg <= colbk_raw_next;
prior_raw_reg <= prior_raw_next;
vdelay_reg <= vdelay_next;
gractl_reg <= gractl_next;
consol_output_reg <= consol_output_next;
COLOUR_REG <= colour_next;
HRCOLOUR_REG <= hrcolour_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
burst_reg <= burst_next;
hblank_reg <= hblank_next;
an_prev_reg <= an_prev_next;
an_prev2_reg <= an_prev2_next;
an_prev3_reg <= an_prev3_next;
highres_reg <= highres_next;
active_hr_reg <= active_hr_next;
trig0_reg <= trig0_next;
trig1_reg <= trig1_next;
trig2_reg <= trig2_next;
trig3_reg <= trig3_next;
odd_scanline_reg <= odd_scanline_next;
pmg_dma_state_reg <= pmg_dma_state_next;
m0pf_reg <= m0pf_next;
m1pf_reg <= m1pf_next;
m2pf_reg <= m2pf_next;
m3pf_reg <= m3pf_next;
m0pl_reg <= m0pl_next;
m1pl_reg <= m1pl_next;
m2pl_reg <= m2pl_next;
m3pl_reg <= m3pl_next;
p0pf_reg <= p0pf_next;
p1pf_reg <= p1pf_next;
p2pf_reg <= p2pf_next;
p3pf_reg <= p3pf_next;
p0pl_reg <= p0pl_next;
p1pl_reg <= p1pl_next;
p2pl_reg <= p2pl_next;
p3pl_reg <= p3pl_next;
active_bk_modify_reg <= active_bk_modify_next;
active_bk_valid_reg <= active_bk_valid_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>5)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- decode antic input
process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
begin
hblank_next <= hblank_reg;
reset_counter <= '0';
counter_load_value <= (others=>'0');
vsync_next <= vsync_reg;
odd_scanline_next <= odd_scanline_reg;
start_of_field <= '0';
-- NB high res mode gives pf2 - which is or of the two pixels
highres_next <= highres_reg;
-- for gtia modes
an_prev_next <= an_prev_reg;
an_prev2_next <= an_prev2_reg;
an_prev3_next <= an_prev3_reg;
-- decoded AN
visible_live <= '0';
active_hr_next <= active_hr_reg;
active_bk_modify_next <= active_bk_modify_reg;
active_bk_valid_next <= active_bk_valid_reg;
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
active_pm0_live <= '0';
active_pm1_live <= '0';
active_pm2_live <= '0';
active_pm3_live <= '0';
if (COLOUR_CLOCK = '1') then
visible_live <= '1';
vsync_next <= '0';
hblank_next <= '0';
an_prev_next <= an;
an_prev2_next <= an_prev_reg;
an_prev3_next <= an_prev2_reg;
active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));
active_bk_modify_next <= (others=>'0');
active_bk_valid_next <= (others=>'1');
active_hr_next <= (others=>'0');
-- 000 background colour
-- 001 vsync
-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
-- 1XX colour 0 to colour 3
-- in gtia modes then we listen for 2 colour clocks to get one pixels
-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
-- 1XV
if (highres_reg = '1') then
if (an(2) = '1') then
active_hr_next <= AN(1 downto 0);
end if;
active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= an(2);
active_pf2_collision_live <= an(2) and (an(1) or an(0));
active_pf3_collision_live <= '0';
else
-- gtia modes
case prior_delayed_reg(7 downto 6) is
when "00" =>
-- normal mode
active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
active_pf0_live <= an(2) and not(an(1)) and not(an(0));
active_pf1_live <= an(2) and not(an(1)) and an(0);
active_pf2_live <= an(2) and an(1) and not(an(0));
active_pf2_collision_live <= an(2) and an(1) and not(an(0));
active_pf3_collision_live <= an(2) and an(1) and an(0);
when "01" =>
-- 1 colour/16 luminance
-- no playfield collisions
-- 5th player gets my luminance
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
active_bk_live <= '1';
if (hpos_reg(0) = '1') then
active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
else
active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
end if;
when "10" =>
-- 9 colour
-- playfield collisions
-- no missile/player collisions from 'playfield' data though
-- offset by 1 colour clock...
if (hpos_reg(0) = '1') then
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
case an_prev_reg(1 downto 0)&an(1 downto 0) is
when "0000" =>
active_pm0_live <= '1';
when "0001" =>
active_pm1_live <= '1';
when "0010" =>
active_pm2_live <= '1';
when "0011" =>
active_pm3_live <= '1';
when "0100"|"1100" =>
active_pf0_live <= an(2);
active_bk_live <= not(an(2));
when "0101"|"1101" =>
active_pf1_live <= an(2);
active_bk_live <= not(an(2));
when "0110"|"1110" =>
active_pf2_live <= an(2);
active_pf2_collision_live <= an(2);
active_bk_live <= not(an(2));
when "0111"|"1111" =>
active_pf3_collision_live <= an(2);
active_bk_live <= not(an(2));
when others =>
active_bk_live <= '1';
end case;
else
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
when "0000" =>
active_pm0_live <= '1';
when "0001" =>
active_pm1_live <= '1';
when "0010" =>
active_pm2_live <= '1';
when "0011" =>
active_pm3_live <= '1';
when "0100"|"1100" =>
active_pf0_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0101"|"1101" =>
active_pf1_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0110"|"1110" =>
active_pf2_live <= an_prev_reg(2);
active_pf2_collision_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when "0111"|"1111" =>
active_pf3_collision_live <= an_prev_reg(2);
active_bk_live <= not(an_prev_reg(2));
when others =>
active_bk_live <= '1';
end case;
end if;
when "11" =>
-- 16 colour/1 luminance
-- no playfield collisions
-- 5th player gets our luminance
active_bk_live <= '1';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_collision_live <= '0';
if (hpos_reg(0) = '1') then
active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
else
active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
end if;
if (active_bk_modify_next(7 downto 4) = "0000") then
active_bk_valid_next(3 downto 0) <= "0000";
end if;
when others =>
-- nop
end case;
end if;
if (prior_delayed_reg(4) = '1') then
active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
else
active_pf3_live <= active_pf3_collision_live;
end if;
if (not (prior_delayed2_reg(7 downto 6) = "00")) then
-- force off flip flop when in gtia mode
highres_next <= '0';
end if;
-- hblank
if (an_prev_reg(2 downto 1) = "01") then
hblank_next <= '1';
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
highres_next <= an_prev_reg(0);
if (COLOUR_CLOCK_ORIGINAL='1') then
if (hblank_reg = '0' and vsync_reg = '0') then
reset_counter <= '1';
counter_load_value <= X"E0"; -- 2 lower than antic
odd_scanline_next <= not(odd_scanline_reg);
end if;
end if;
end if;
if (an(2 downto 1) = "01") then
visible_live <= '0';
end if;
-- vsync
if (an_prev_reg = "001") then
active_bk_live <= '0';
active_pf0_live <= '0';
active_pf1_live <= '0';
active_pf2_live <= '0';
active_pf2_collision_live <= '0';
active_pf3_live <= '0';
active_pf3_collision_live <= '0';
vsync_next <= '1';
odd_scanline_next <= '0';
visible_live <= '0';
start_of_field <= not(vsync_reg);
end if;
-- during vblank we reset our own counter - since Antic does not clear hblank_reg
if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
reset_counter <= '1';
counter_load_value <= X"00";
end if;
end if;
end process;
-- hpos
counter_hpos : simple_counter
generic map (COUNT_WIDTH=>8)
port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
-- visible region
-- process(hpos_reg,vpos_reg)
-- begin
-- visible_live <= '1';
--
---- if (unsigned(vpos_reg) < to_unsigned(8,9)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(vpos_reg) > to_unsigned(247,9)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
---- visible_live <= '0';
---- end if;
----
---- if (unsigned(hpos_reg) > to_unsigned(221,8)) then
---- visible_live <= '0';
---- end if;
-- end process;
-- generate hsync
process(hpos_reg, hsync_reg, hsync_end, burst_reg, burst_end, vsync_reg, vsync_next)
begin
hsync_start <= '0';
hsync_next <= hsync_reg;
burst_start <= '0';
burst_next <= burst_reg;
if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
hsync_start <= '1';
hsync_next <= '1';
end if;
if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
hsync_start <= '1';
hsync_next <= '1';
end if;
if (unsigned(hpos_reg) = X"14" and vsync_reg = '0' ) then
burst_start <= '1';
burst_next <= '1';
end if;
if (hsync_end = '1') then
hsync_next <= '0';
end if;
if (burst_end = '1') then
burst_next <= '0';
end if;
if (vsync_next = '0' and vsync_reg = '1') then
hsync_next <= '0';
end if;
end process;
hsync_delay : delay_line
generic map (COUNT=>15)
port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);
burst_delay : delay_line
generic map (COUNT=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>burst_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>burst_end);
-- pmg dma
process(CPU_ENABLE_ORIGINAL,antic_fetch,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
begin
pmg_dma_state_next <= pmg_dma_state_reg;
grafm_dma_load <= '0';
grafm_dma_next <= grafm_reg;
grafp0_dma_load <= '0';
grafp0_dma_next <= (others=>'0');
grafp1_dma_load <= '0';
grafp1_dma_next <= (others=>'0');
grafp2_dma_load <= '0';
grafp2_dma_next <= (others=>'0');
grafp3_dma_load <= '0';
grafp3_dma_next <= (others=>'0');
-- pull pmg data from bus
if (hpos_reg = X"E1") then
pmg_dma_state_next <= pmg_dma_missile;
end if;
-- we start from the first antic fetch
-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
case pmg_dma_state_reg is
when pmg_dma_missile =>
if (antic_fetch = '1' and cpu_enable_original = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
-- here we have the missile0
grafm_dma_load <= gractl_reg(0);
if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
end if;
if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
end if;
if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
end if;
if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
end if;
pmg_dma_state_next <= pmg_dma_instruction;
end if;
when pmg_dma_instruction =>
if (CPU_ENABLE_ORIGINAL = '1') then
pmg_dma_state_next <= pmg_dma_player0;
end if;
when pmg_dma_player0 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player0
grafp0_dma_next <= memory_data_in;
grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
pmg_dma_state_next <= pmg_dma_player1;
end if;
when pmg_dma_player1 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp1_dma_next <= memory_data_in;
grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
pmg_dma_state_next <= pmg_dma_player2;
end if;
when pmg_dma_player2 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp2_dma_next <= memory_data_in;
grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
pmg_dma_state_next <= pmg_dma_player3;
end if;
when pmg_dma_player3 =>
if (CPU_ENABLE_ORIGINAL = '1') then
-- here we have player1
grafp3_dma_next <= memory_data_in;
grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
pmg_dma_state_next <= pmg_dma_done;
end if;
when others =>
-- nop
end case;
end process;
-- pmg display - same for all pmgs
-- TODO: priority
player0 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);
player1 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);
player2 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);
player3 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);
grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
missile0 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
missile1 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
missile2 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
missile3 : gtia_player
port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
-- calculate atari colour
priority_rules : gtia_priority
port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);
trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
begin
colour_next <= colour_reg;
hrcolour_next <= hrcolour_reg;
if (trigger_secondhalf = '1') then
if (highres_reg = '1') then
colour_next <= hrcolour_reg;
end if;
end if;
if (colour_clock = '1') then
colour_next <=
(
((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
);
hrcolour_next <= -- SAME FIXME
(
((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
);
-- finally high-res mode overrides the luma
if (set_bk = '0' and highres_reg = '1') then
if (active_hr_reg(1) = '1') then
colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
end if;
if (active_hr_reg(0) = '1') then
hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
end if;
end if;
if (visible_live = '0') then
colour_next <= X"00";
hrcolour_next <= X"00";
end if;
end if;
end process;
-- collision detection
process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
begin
m0pf_next <= m0pf_reg;
m1pf_next <= m1pf_reg;
m2pf_next <= m2pf_reg;
m3pf_next <= m3pf_reg;
m0pl_next <= m0pl_reg;
m1pl_next <= m1pl_reg;
m2pl_next <= m2pl_reg;
m3pl_next <= m3pl_reg;
p0pf_next <= p0pf_reg;
p1pf_next <= p1pf_reg;
p2pf_next <= p2pf_reg;
p3pf_next <= p3pf_reg;
p0pl_next <= p0pl_reg;
p1pl_next <= p1pl_reg;
p2pl_next <= p2pl_reg;
p3pl_next <= p3pl_reg;
if (hitclr_write = '1') then
m0pf_next <= (others=>'0');
m1pf_next <= (others=>'0');
m2pf_next <= (others=>'0');
m3pf_next <= (others=>'0');
m0pl_next <= (others=>'0');
m1pl_next <= (others=>'0');
m2pl_next <= (others=>'0');
m3pl_next <= (others=>'0');
p0pf_next <= (others=>'0');
p1pf_next <= (others=>'0');
p2pf_next <= (others=>'0');
p3pf_next <= (others=>'0');
p0pl_next <= (others=>'0');
p1pl_next <= (others=>'0');
p2pl_next <= (others=>'0');
p3pl_next <= (others=>'0');
else
if (visible_live = '1' and colour_clock = '1') then
m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0' and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0' &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p2pl_next <= p2pl_reg or (active_p2_live&'0' &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p3pl_next <= p3pl_reg or ('0' &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
end if;
end if;
end process;
-- Writes to registers
process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
begin
hposp0_raw_next <= hposp0_raw_reg;
hposp1_raw_next <= hposp1_raw_reg;
hposp2_raw_next <= hposp2_raw_reg;
hposp3_raw_next <= hposp3_raw_reg;
hposm0_raw_next <= hposm0_raw_reg;
hposm1_raw_next <= hposm1_raw_reg;
hposm2_raw_next <= hposm2_raw_reg;
hposm3_raw_next <= hposm3_raw_reg;
sizep0_raw_next <= sizep0_raw_reg;
sizep1_raw_next <= sizep1_raw_reg;
sizep2_raw_next <= sizep2_raw_reg;
sizep3_raw_next <= sizep3_raw_reg;
sizem_raw_next <= sizem_raw_reg;
grafp0_next <= grafp0_reg;
grafp1_next <= grafp1_reg;
grafp2_next <= grafp2_reg;
grafp3_next <= grafp3_reg;
grafm_next <= grafm_reg;
colpm0_raw_next <= colpm0_raw_reg;
colpm1_raw_next <= colpm1_raw_reg;
colpm2_raw_next <= colpm2_raw_reg;
colpm3_raw_next <= colpm3_raw_reg;
colpf0_raw_next <= colpf0_raw_reg;
colpf1_raw_next <= colpf1_raw_reg;
colpf2_raw_next <= colpf2_raw_reg;
colpf3_raw_next <= colpf3_raw_reg;
colbk_raw_next <= colbk_raw_reg;
prior_raw_next <= prior_raw_reg;
vdelay_next <= vdelay_reg;
gractl_next <= gractl_reg;
consol_output_next <= consol_output_reg;
hitclr_write <= '0';
if (grafm_dma_load = '1') then
grafm_next <= grafm_dma_next;
end if;
if (grafp0_dma_load = '1') then
grafp0_next <= grafp0_dma_next;
end if;
if (grafp1_dma_load = '1') then
grafp1_next <= grafp1_dma_next;
end if;
if (grafp2_dma_load = '1') then
grafp2_next <= grafp2_dma_next;
end if;
if (grafp3_dma_load = '1') then
grafp3_next <= grafp3_dma_next;
end if;
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
hposp0_raw_next <= cpu_data_in;
end if;
if(addr_decoded(1) = '1') then
hposp1_raw_next <= cpu_data_in;
end if;
if(addr_decoded(2) = '1') then
hposp2_raw_next <= cpu_data_in;
end if;
if(addr_decoded(3) = '1') then
hposp3_raw_next <= cpu_data_in;
end if;
if(addr_decoded(4) = '1') then
hposm0_raw_next <= cpu_data_in;
end if;
if(addr_decoded(5) = '1') then
hposm1_raw_next <= cpu_data_in;
end if;
if(addr_decoded(6) = '1') then
hposm2_raw_next <= cpu_data_in;
end if;
if(addr_decoded(7) = '1') then
hposm3_raw_next <= cpu_data_in;
end if;
if(addr_decoded(8) = '1') then
sizep0_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(9) = '1') then
sizep1_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(10) = '1') then
sizep2_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(11) = '1') then
sizep3_raw_next <= cpu_data_in(1 downto 0);
end if;
if(addr_decoded(12) = '1') then
sizem_raw_next <= cpu_data_in;
end if;
if(addr_decoded(13) = '1') then
grafp0_next <= cpu_data_in;
end if;
if(addr_decoded(14) = '1') then
grafp1_next <= cpu_data_in;
end if;
if(addr_decoded(15) = '1') then
grafp2_next <= cpu_data_in;
end if;
if(addr_decoded(16) = '1') then
grafp3_next <= cpu_data_in;
end if;
if(addr_decoded(17) = '1') then
grafm_next <= cpu_data_in;
end if;
if(addr_decoded(18) = '1') then
colpm0_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(19) = '1') then
colpm1_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(20) = '1') then
colpm2_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(21) = '1') then
colpm3_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(22) = '1') then
colpf0_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(23) = '1') then
colpf1_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(24) = '1') then
colpf2_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(25) = '1') then
colpf3_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(26) = '1') then
colbk_raw_next <= cpu_data_in(7 downto 1);
end if;
if(addr_decoded(27) = '1') then
prior_raw_next <= cpu_data_in;
end if;
if(addr_decoded(28) = '1') then
vdelay_next <= cpu_data_in;
end if;
if(addr_decoded(29) = '1') then
gractl_next <= cpu_data_in(2 downto 0);
end if;
if(addr_decoded(30) = '1') then
-- clear the collision regs
hitclr_write <= '1';
end if;
if(addr_decoded(31) = '1') then
consol_output_next <= cpu_data_in(3 downto 0);
end if;
end if;
end process;
-- delays...
-- TODO - needs more attention ...
-- The prior behaviour here in real hardware is all over the place...
-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
prior_short_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>6)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
prior_long_delay : wide_delay_line
generic map (COUNT=>3, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
prior_longer_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));
colbk_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));
colpm0_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));
colpm1_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));
colpm2_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));
colpm3_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));
colpf0_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));
colpf1_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));
colpf2_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));
colpf3_delay : wide_delay_line
generic map (COUNT=>2, WIDTH=>7)
port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));
hposp0_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));
hposp1_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));
hposp2_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));
hposp3_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));
hposm0_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));
hposm1_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));
hposm2_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));
hposm3_delay : wide_delay_line
generic map (COUNT=>5, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));
sizep0_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));
sizep1_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));
sizep2_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));
sizep3_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>2)
port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));
sizem_delay : wide_delay_line
generic map (COUNT=>4, WIDTH=>8)
port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));
-- joystick
process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
begin
trig0_next <= trig0;
trig1_next <= trig1;
trig2_next <= trig2;
trig3_next <= trig3;
if (gractl_reg(2) = '1') then
trig0_next <= trig0_reg and trig0;
trig1_next <= trig1_reg and trig1;
trig2_next <= trig2_reg and trig2;
trig3_next <= trig3_reg and trig3;
end if;
end process;
-- Read from registers
process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
begin
data_out <= X"0F";
if (addr_decoded(0) = '1') then
data_out <= "0000"&m0pf_reg;
end if;
if (addr_decoded(1) = '1') then
data_out <= "0000"&m1pf_reg;
end if;
if (addr_decoded(2) = '1') then
data_out <= "0000"&m2pf_reg;
end if;
if (addr_decoded(3) = '1') then
data_out <= "0000"&m3pf_reg;
end if;
if (addr_decoded(4) = '1') then
data_out <= "0000"&p0pf_reg;
end if;
if (addr_decoded(5) = '1') then
data_out <= "0000"&p1pf_reg;
end if;
if (addr_decoded(6) = '1') then
data_out <= "0000"&p2pf_reg;
end if;
if (addr_decoded(7) = '1') then
data_out <= "0000"&p3pf_reg;
end if;
if (addr_decoded(8) = '1') then
data_out <= "0000"&m0pl_reg;
end if;
if (addr_decoded(9) = '1') then
data_out <= "0000"&m1pl_reg;
end if;
if (addr_decoded(10) = '1') then
data_out <= "0000"&m2pl_reg;
end if;
if (addr_decoded(11) = '1') then
data_out <= "0000"&m3pl_reg;
end if;
if (addr_decoded(12) = '1') then
data_out <= "0000"&p0pl_reg;
end if;
if (addr_decoded(13) = '1') then
data_out <= "0000"&p1pl_reg;
end if;
if (addr_decoded(14) = '1') then
data_out <= "0000"&p2pl_reg;
end if;
if (addr_decoded(15) = '1') then
data_out <= "0000"&p3pl_reg;
end if;
if (addr_decoded(16) = '1') then
data_out <= "0000000"&trig0_reg;
end if;
if (addr_decoded(17) = '1') then
data_out <= "0000000"&trig1_reg;
end if;
if (addr_decoded(18) = '1') then
data_out <= "0000000"&trig2_reg;
end if;
if (addr_decoded(19) = '1') then
data_out <= "0000000"&trig3_reg;
end if;
if (addr_decoded(20) = '1') then
data_out <= "0000"¬(pal&pal&pal)&'1';
end if;
if (addr_decoded(31) = '1') then
data_out <= "0000"&('0'¬(CONSOL_OPTION)¬(CONSOL_SELECT)¬(CONSOL_START) and (not consol_output_reg));
end if;
end process;
-- output
colour_out <= colour_reg;
vsync<=vsync_reg;
hsync<=hsync_reg;
blank<=hblank_reg or vsync_reg;
burst<=burst_reg;
odd_line<=odd_scanline_reg;
sound <= consol_output_reg(3);
end vhdl;
| gpl-3.0 | dbb09d7963f91a1b90aa2c6c4ee5dfbd | 0.641587 | 2.547029 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/FeqDiv.vhd | 1 | 906 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FeqDiv is
Generic( width : integer );
Port( clkIn : in STD_LOGIC;
clkOut : out STD_LOGIC);
end FeqDiv;
architecture Behavioral of FeqDiv is
signal inner : STD_LOGIC_VECTOR(1 to width);
attribute KEEP : string;
attribute KEEP of clkIn: signal is "TRUE";
attribute KEEP of clkOut: signal is "TRUE";
attribute KEEP of inner: signal is "TRUE";
begin
chain:
for D in 1 to width generate
begin
chainBegin: if D = 1 generate
begin
process(clkIn)
begin
if rising_edge(clkIn) then
inner(D) <= not inner(D);
end if;
end process;
end generate;
chainRest: if D /= 1 generate
begin
process(inner(D-1))
begin
if rising_edge(inner(D-1)) then
inner(D) <= not inner(D);
end if;
end process;
end generate;
end generate;
clkOut <= inner(width);
end Behavioral;
| mit | 5fca756d1a7623be7404a03ffadc62dc | 0.666667 | 3.02 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/fact.vhd | 4 | 19,741 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of fact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal result_int_reg_38 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_50 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_73_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_reg_95 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond_fu_79_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_reg_100 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_89_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_2_reg_109 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal grp_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_114 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal grp_fu_61_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal i_phi_fu_54_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal grp_fu_66_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_fu_69_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriescud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_x_U4 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_38,
din1 => tmp_s_reg_114,
ce => ap_const_logic_1,
dout => grp_fu_61_p2);
sin_taylor_seriescud_U5 : component sin_taylor_seriescud
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_66_p0,
ce => ap_const_logic_1,
dout => grp_fu_66_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_50_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_50 <= i_2_reg_109;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_50 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_38_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_reg_100 = ap_const_lv1_0))) then
result_int_reg_38 <= grp_fu_61_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_38 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_reg_100 <= exitcond_reg_100;
exitcond_reg_100 <= exitcond_fu_79_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
i_2_reg_109 <= i_2_fu_89_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_3_reg_95 <= tmp_3_fu_73_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (exitcond_reg_100 = ap_const_lv1_0))) then
tmp_s_reg_114 <= grp_fu_66_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_fu_79_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_fu_79_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if (((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(7);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_fu_79_p2)
begin
if ((exitcond_fu_79_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state14)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_38;
exitcond_fu_79_p2 <= "1" when (i_phi_fu_54_p4 = tmp_3_reg_95) else "0";
grp_fu_66_p0 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_phi_fu_54_p4),32));
i_2_fu_89_p2 <= std_logic_vector(unsigned(i_phi_fu_54_p4) + unsigned(ap_const_lv6_1));
i_phi_fu_54_p4_assign_proc : process(i_reg_50, exitcond_reg_100, ap_CS_fsm_pp0_stage0, i_2_reg_109, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_reg_100 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_54_p4 <= i_2_reg_109;
else
i_phi_fu_54_p4 <= i_reg_50;
end if;
end process;
tmp_3_fu_73_p2 <= std_logic_vector(unsigned(tmp_cast_fu_69_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_69_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x),6));
end behav;
| mit | afcc410224994b9ed3667389c84472e2 | 0.592067 | 2.95701 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/atari800core_simple_sdram.vhd | 1 | 11,083 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
LIBRARY work;
-- Simple version that:
-- i) needs: CLK(58 or 28MHZ) SDRAM,joystick,keyboard
-- ii) provides: VIDEO,AUDIO
-- iii) passes upstream: DMA port, for attaching ZPU for SDCARD/drive emulation
-- THIS SHOULD DO FOR ALL PLATFORMS EXCEPT THOSE USING GPIO FOR PBI etc
ENTITY atari800core_simple_sdram is
GENERIC
(
-- use CLK of 1.79*cycle_length
-- I've tested 16 and 32 only, but 4 and 8 might work...
cycle_length : integer := 16; -- or 32...
-- how many bits for video
video_bits : integer := 8;
palette : integer :=1; -- 0:gtia colour on VIDEO_B, 1:altirra, 2:laoo
-- For initial port may help to have no
internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
internal_ram : integer := 16384 -- at start of memory map
);
PORT
(
CLK : IN STD_LOGIC; -- cycle_length*1.79MHz
RESET_N : IN STD_LOGIC;
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VIDEO_VS : OUT STD_LOGIC;
VIDEO_HS : OUT STD_LOGIC;
VIDEO_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- These ones are probably only needed for e.g. svideo
VIDEO_BLANK : out std_logic;
VIDEO_BURST : out std_logic;
VIDEO_START_OF_FIELD : out std_logic;
VIDEO_ODD_LINE : out std_logic;
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
AUDIO_L : OUT std_logic_vector(15 downto 0);
AUDIO_R : OUT std_logic_vector(15 downto 0);
-- JOYSTICK
JOY1_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
JOY2_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
-- Pokey keyboard matrix
-- Standard component available to connect this to PS2
KEYBOARD_RESPONSE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
KEYBOARD_SCAN : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- SIO
SIO_COMMAND : out std_logic;
SIO_RXD : in std_logic;
SIO_TXD : out std_logic;
-- GTIA consol
CONSOL_OPTION : IN STD_LOGIC;
CONSOL_SELECT : IN STD_LOGIC;
CONSOL_START : IN STD_LOGIC;
-----------------------
-- After here all FPGA implementation specific
-- e.g. need to write up RAM/ROM
-- we can dma from memory space
-- etc.
-- External RAM/ROM - adhere to standard memory map
-- TODO - lower/upper memory split defined by generic
-- (TODO SRAM lower ram, SDRAM upper ram - no overlap?)
---- SDRAM memory map (8MB) (lower 512k if USE_SDRAM=1)
---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
---- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
---- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
---- SCRATCH - 4MB+64k-5MB
---- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
--SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
---- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
--SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
--SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
---- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
-- TODO - review if we need to pass out so many of these
-- Perhaps we can simplify address decoder and have an external layer?
SDRAM_REQUEST : OUT std_logic;
SDRAM_REQUEST_COMPLETE : IN std_logic;
SDRAM_READ_ENABLE : out STD_LOGIC;
SDRAM_WRITE_ENABLE : out std_logic;
SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SDRAM_DI : out STD_LOGIC_VECTOR(31 DOWNTO 0);
SDRAM_32BIT_WRITE_ENABLE : out std_logic;
SDRAM_16BIT_WRITE_ENABLE : out std_logic;
SDRAM_8BIT_WRITE_ENABLE : out std_logic;
SDRAM_REFRESH : out std_logic;
-- DMA memory map differs
-- e.g. some special addresses to read behind hardware registers
-- 0x0000-0xffff: Atari registers + 3 mirrors (bit 16/17)
-- 23 downto 21:
-- 001 : SRAM,512k
-- 010|011 : ROM, 4MB
-- 10xx : SDRAM, 8MB (If you have more, its unmapped for now... Can bank switch! Atari can't access this much anyway...)
DMA_FETCH : in STD_LOGIC; -- we want to read/write
DMA_READ_ENABLE : in std_logic;
DMA_32BIT_WRITE_ENABLE : in std_logic;
DMA_16BIT_WRITE_ENABLE : in std_logic;
DMA_8BIT_WRITE_ENABLE : in std_logic;
DMA_ADDR : in std_logic_vector(23 downto 0);
DMA_WRITE_DATA : in std_logic_vector(31 downto 0);
MEMORY_READY_DMA : out std_logic; -- op complete
DMA_MEMORY_DATA : out std_logic_vector(31 downto 0);
-- Special config params
RAM_SELECT : in std_logic_vector(2 downto 0); -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB
ROM_SELECT : in std_logic_vector(5 downto 0); -- 16KB ROM Bank - 0 is illegal (slot used for BASIC!)
PAL : in STD_LOGIC;
HALT : in std_logic;
THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0) -- standard speed is cycle_length-1
);
end atari800core_simple_sdram;
ARCHITECTURE vhdl OF atari800core_simple_sdram IS
-- PIA
SIGNAL CA1_IN : STD_LOGIC;
SIGNAL CB1_IN: STD_LOGIC;
SIGNAL CA2_OUT : STD_LOGIC;
SIGNAL CA2_DIR_OUT: STD_LOGIC;
SIGNAL CB2_OUT : STD_LOGIC;
SIGNAL CB2_DIR_OUT: STD_LOGIC;
SIGNAL CA2_IN: STD_LOGIC;
SIGNAL CB2_IN: STD_LOGIC;
SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- GTIA
signal GTIA_TRIG : std_logic_vector(3 downto 0);
-- ANTIC
signal ANTIC_LIGHTPEN : std_logic;
-- CARTRIDGE ACCESS
SIGNAL CART_RD4 : STD_LOGIC;
SIGNAL CART_RD5 : STD_LOGIC;
-- PBI
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
-- INTERNAL ROM/RAM
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RAM_REQUEST : STD_LOGIC;
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ROM_REQUEST : STD_LOGIC;
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
-- CONFIG
SIGNAL USE_SDRAM : STD_LOGIC;
SIGNAL ROM_IN_RAM : STD_LOGIC;
BEGIN
-- PIA mapping
CA1_IN <= '1';
CB1_IN <= '1';
CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
SIO_COMMAND <= CB2_OUT;
PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
PORTB_IN <= PORTB_OUT;
-- ANTIC lightpen
ANTIC_LIGHTPEN <= JOY2_n(4) and JOY1_n(4);
-- GTIA triggers
GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
-- Cartridge not inserted
CART_RD4 <= '0';
CART_RD5 <= '0';
-- Since we're not exposing PBI, expose a few key parts needed for SDRAM
SDRAM_DI <= PBI_WRITE_DATA;
-- Internal rom/ram
internalromram1 : entity work.internalromram
GENERIC MAP
(
internal_rom => internal_rom,
internal_ram => internal_ram
)
PORT MAP (
clock => CLK,
reset_n => RESET_N,
ROM_ADDR => ROM_ADDR,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
ROM_REQUEST => ROM_REQUEST,
ROM_DATA => ROM_DO,
RAM_ADDR => RAM_ADDR,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_REQUEST => RAM_REQUEST,
RAM_DATA => RAM_DO(7 downto 0)
);
USE_SDRAM <= '1' when internal_ram=0 else '0';
ROM_IN_RAM <= '1' when internal_rom=0 else '0';
atari800xl : entity work.atari800core
GENERIC MAP
(
cycle_length => cycle_length,
video_bits => video_bits,
palette => palette
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N,
VIDEO_VS => VIDEO_VS,
VIDEO_HS => VIDEO_HS,
VIDEO_B => VIDEO_B,
VIDEO_G => VIDEO_G,
VIDEO_R => VIDEO_R,
VIDEO_BLANK => VIDEO_BLANK,
VIDEO_BURST => VIDEO_BURST,
VIDEO_START_OF_FIELD => VIDEO_START_OF_FIELD,
VIDEO_ODD_LINE => VIDEO_ODD_LINE,
AUDIO_L => AUDIO_L,
AUDIO_R => AUDIO_R,
CA1_IN => CA1_IN,
CB1_IN => CB1_IN,
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CA2_DIR_OUT => CA2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
PORTA_IN => PORTA_IN,
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => open,--PORTB_DIR_OUT,
PORTB_OUT => PORTB_OUT,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => "00000000",
POT_RESET => open,
-- PBI
PBI_ADDR => open,
PBI_WRITE_ENABLE => open,
PBI_SNOOP_DATA => DMA_MEMORY_DATA,
PBI_WRITE_DATA => PBI_WRITE_DATA,
PBI_WIDTH_8bit_ACCESS => SDRAM_8BIT_WRITE_ENABLE,
PBI_WIDTH_16bit_ACCESS => SDRAM_16BIT_WRITE_ENABLE,
PBI_WIDTH_32bit_ACCESS => SDRAM_32BIT_WRITE_ENABLE,
PBI_ROM_DO => "11111111",
PBI_REQUEST => open,
PBI_REQUEST_COMPLETE => '1',
CART_RD4 => CART_RD4,
CART_RD5 => CART_RD5,
CART_S4_n => open,
CART_S5_N => open,
CART_CCTL_N => open,
SIO_RXD => SIO_RXD,
SIO_TXD => SIO_TXD,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START=> CONSOL_START,
GTIA_TRIG => GTIA_TRIG,
ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
ANTIC_REFRESH => SDRAM_REFRESH,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
RAM_ADDR => RAM_ADDR,
RAM_DO => RAM_DO,
RAM_REQUEST => RAM_REQUEST,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
ROM_ADDR => ROM_ADDR,
ROM_DO => ROM_DO,
ROM_REQUEST => ROM_REQUEST,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
DMA_FETCH => DMA_FETCH,
DMA_READ_ENABLE => DMA_READ_ENABLE,
DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
DMA_ADDR => DMA_ADDR,
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_DMA => MEMORY_READY_DMA,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
CART_EMULATION_SELECT => "0000000",
CART_EMULATION_ACTIVATE => '0',
PAL => PAL,
USE_SDRAM => USE_SDRAM,
ROM_IN_RAM => ROM_IN_RAM,
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
HALT => HALT
);
end vhdl;
| gpl-3.0 | 7eece019c6e3c5203ce5a65fe3906ee0 | 0.649192 | 2.790282 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/keyboard/keyboard.vhd | 1 | 10,537 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CONTROL : out std_logic_vector(7 downto 0);
KEYB_A : in std_logic_vector(7 downto 0);
KEYB_A2 : in std_logic_vector(3 downto 0);
KEYB_D : out std_logic_vector(7 downto 0);
KEYB_D2 : out std_logic_vector(3 downto 0));
end keyboard;
architecture Behavioral of keyboard is
signal CODE : std_logic_vector(7 downto 0);
signal DONE : std_logic;
signal ERROR : std_logic;
signal KEY_REL : std_logic;
signal KEY_EXT : std_logic;
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix : Matrix_Image(0 to 7);
type Matrix2_Image is array (natural range <>) of std_logic_vector(3 downto 0);
signal Matrix2 : Matrix2_Image(0 to 3);
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => not RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
DECODER : process(CLK)
variable KEY : std_logic_vector(10 downto 0);
variable KEY2 : std_logic_vector(5 downto 0);
begin
if rising_edge(CLK) then
if RESET = '0' then
Matrix <= (others => (others => '0'));
KEY_REL <= '0';
KEY_EXT <= '0';
CONTROL <= "00000000";
else
CONTROL <= "00000000";
if DONE = '1' then -- ScanCode Readed
if CODE = X"F0" then -- Key Released
KEY_REL <= '1';
elsif CODE = X"E0" then -- Extended Key
KEY_EXT <= '1';
else
KEY := (others => '0');
KEY2 := (others => '0');
case CODE is
when x"1C" => KEY := "11000010000"; -- A
when x"32" => KEY := "01100000010"; -- B
when x"21" => KEY := "10110000000"; -- C
when x"23" => KEY := "01010000000"; -- D
when x"24" => KEY := "10100010000"; -- E
when x"2B" => KEY := "11010000000"; -- F
when x"34" => KEY := "00100000001"; -- G
when x"33" => KEY := "00101000000"; -- H
when x"43" => KEY := "11100100000"; -- I
when x"3B" => KEY := "10100000100"; -- J
when x"42" => KEY := "10100100000"; -- K
when x"4B" => KEY := "01000000100"; -- L
when x"3A" => KEY := "11101000000"; -- M
when x"31" => KEY := "10100001000"; -- N
when x"44" => KEY := "01000000010"; -- O
when x"4D" => KEY := "11000001000"; -- P
when x"15" => KEY := "11100000010"; -- Q
when x"2D" => KEY := "01000000001"; -- R
when x"1B" => KEY := "11110000000"; -- S
when x"2C" => KEY := "11100010000"; -- T
when x"3C" => KEY := "10101000000"; -- U
when x"2A" => KEY := "01001000000"; -- V
when x"1D" => KEY := "11000100000"; -- W
when x"22" => KEY := "11100001000"; -- X
when x"35" => KEY := "11001000000"; -- Y
when x"1A" => KEY := "00110000000"; -- Z
when x"16" => KEY := "10010000000"; -- 1
when x"1E" => KEY := "10001000000"; -- 2
when x"26" => KEY := "10000100000"; -- 3
when x"25" => KEY := "10000010000"; -- 4
when x"2E" => KEY := "10000001000"; -- 5
when x"36" => KEY := "00000000001"; -- 6
when x"3D" => KEY := "00000000010"; -- 7
when x"3E" => KEY := "00000000100"; -- 8
when x"46" => KEY := "00010000000"; -- 9
when x"45" => KEY := "00001000000"; -- 0
when x"29" => KEY := "01100000001"; -- SPACE
when x"66" => KEY := "01000001000"; -- PACKSPACE | ZB
when x"5A" => KEY := "00100001000"; -- ENTER | WK
when x"58" => KEY := "11000000100"; -- CAPS LOCK | SU
when x"12" => KEY := "11100000001"; -- LEFT SHIFT | NR
when x"59" => KEY := "01100001000"; -- RIGHT SHIFT | WR
when x"0D" => KEY := "00000010000"; -- TAB
when x"41" => KEY := "01110000000"; -- ,
when x"49" => KEY := "01000010000"; -- .
when x"4E" => KEY := "00000100000"; -- -
when x"5D" => KEY := "01000100000"; -- \
when x"55" => KEY := "11100000100"; -- = | ^
when x"0E" => KEY := "00100100000"; -- ' | :
when x"54" => KEY := "00100000010"; -- [
-- when x"76" => KEY := "10000000001"; -- | STR
-- when x"76" => KEY := "10000000001"; -- | @
when x"5B" => KEY := "00100000100"; -- ]
when x"4C" => KEY := "11000000001"; -- ;
when x"4A" => KEY := "01101000000"; -- /
when x"0B" => KEY := "10000000010"; -- F6 | [G]
when x"83" => KEY := "10000000100"; -- F7 | [B]
when x"11" =>
if KEY_EXT = '1' then
KEY := "00100010000"; -- RIGHT ALT | PS
else
KEY := "00000001000"; -- LEFT ALT | GT
end if;
when x"14" =>
if KEY_EXT = '1' then
KEY := "01100100000"; -- RIGHT CTRL | LAT
else
KEY := "11000000010"; -- LEFT CTRL | RUS
end if;
when x"76" => KEY2 := "010010"; -- ESC | F0
when x"05" => KEY2 := "010100"; -- F1
when x"06" => KEY2 := "011000"; -- F2
when x"04" => KEY2 := "101000"; -- F3
when x"0C" => KEY2 := "100100"; -- F4
when x"03" => KEY2 := "100010"; -- F5
when x"0A" => KEY2 := "001000"; -- F8 | [R]
when x"01" => KEY2 := "000100"; -- F9 | DIN
when x"09" => KEY2 := "000010"; -- F10 | CD
when x"78" => KEY2 := "000001"; -- F11 | P4
when x"07" => KEY2 := "010001"; -- F12 | P/D
when x"74" =>
if KEY_EXT = '1' then
KEY2 := "110001"; -- RIGHT
end if;
when x"75" =>
if KEY_EXT = '1' then
KEY2 := "110010"; -- UP
end if;
when x"6B" =>
if KEY_EXT = '1' then
KEY2 := "110100"; -- LEFT
end if;
when x"72" =>
if KEY_EXT = '1' then
KEY2 := "111000"; -- DOWN
end if;
when x"71" =>
if KEY_EXT = '1' then
KEY2 := "100001"; -- DEL | DIA
end if;
when x"7e" =>
if KEY_REL = '0' then
CONTROL(0) <= '1';
end if;
when OTHERS => NULL;
end case;
if KEY_REL = '0' then
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) or
std_logic_vector(unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) or
std_logic_vector(unsigned(KEY2(3 downto 0)));
else
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) and
std_logic_vector(not unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) and
std_logic_vector(not unsigned(KEY2(3 downto 0)));
end if;
KEY_REL <= '0';
KEY_EXT <= '0';
end if;
end if;
end if;
end if;
end process;
KEYB_D <= not Matrix(0) when KEYB_A(0) = '0' else
not Matrix(1) when KEYB_A(1) = '0' else
not Matrix(2) when KEYB_A(2) = '0' else
not Matrix(3) when KEYB_A(3) = '0' else
not Matrix(4) when KEYB_A(4) = '0' else
not Matrix(5) when KEYB_A(5) = '0' else
not Matrix(6) when KEYB_A(6) = '0' else
not Matrix(7) when KEYB_A(7) = '0' else
"11111111";
KEYB_D2<= not Matrix2(0) when KEYB_A2(0) = '0' else
not Matrix2(1) when KEYB_A2(1) = '0' else
not Matrix2(2) when KEYB_A2(2) = '0' else
not Matrix2(3) when KEYB_A2(3) = '0' else
"1111";
end Behavioral;
| gpl-3.0 | ba610a095769e2f6aefd031cf398350a | 0.360919 | 4.148425 | false | false | false | false |
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| mit | 142ba56831d7a8816f6d13ef51cc5d69 | 0.952142 | 1.816155 | false | false | false | false |
APastorG/APG | butterfly/butterfly_core_s.vhd | 1 | 3,556 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity butterfly_core_s is
generic(
SPEED_opt : T_speed;
EXTEND_opt : boolean;
RANGE1_LEFT : positive;
RANGE1_RIGHT : positive;
RANGE2_LEFT : integer;
RANGE2_RIGHT : integer
);
port(
clk : in std_ulogic;
input : in u_sfixed_v;
output : out u_sfixed_v(RANGE1_LEFT to RANGE1_RIGHT)(ite(EXTEND_opt,
RANGE2_LEFT+1,
RANGE2_LEFT)
downto
RANGE2_RIGHT)
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture butterfly_core_s_1 of butterfly_core_s is
/*================================================================================================*/
/*================================================================================================*/
begin
assert integer(2.0**log2(real(input'length))) = 2**integer(log2(real(input'length)))
report "ERROR in module butterfly: the size of the input signal is not a power of 2"
severity error;
generate_butterfly:
for i in output'low to output'low+input'length/2-1 generate
begin
generate_pipeline:
if is_pipelined(positions => 1,
speed => SPEED_opt,
position => 1) generate
begin
process (clk) is
begin
if rising_edge(clk) then
output(i) <= resize(input(i) + input(i+input'length/2), output(i));
output(i+input'length/2) <= resize(input(i) - input(i+input'length/2), output(i));
end if;
end process;
end;
else generate
begin
output(i) <= resize(input(i) + input(i+input'length/2), output(i));
output(i+input'length/2) <= resize(input(i) - input(i+input'length/2), output(i));
end;
end generate;
end;
end generate;
end architecture; | mit | 4cb51bfde48e74db26fa1ae0a935480d | 0.364566 | 4.918994 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/color/clr_mux.vhd | 2 | 1,319 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY clr_mux IS
PORT
(
color : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
portb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
out_r : OUT STD_LOGIC;
out_g : OUT STD_LOGIC;
out_b : OUT STD_LOGIC
);
END clr_mux;
ARCHITECTURE bdf_type OF clr_mux IS
signal i0 : std_logic;
signal i1 : std_logic;
signal i2 : std_logic;
signal i3 : std_logic;
signal D591 : std_logic;
signal D592 : std_logic;
signal D593 : std_logic;
signal D594 : std_logic;
signal D601 : std_logic;
signal D602 : std_logic;
signal D603 : std_logic;
signal D604 : std_logic;
signal D611 : std_logic;
signal D612 : std_logic;
signal D613 : std_logic;
BEGIN
i0 <= color(1) or color(0);
i1 <= color(1) or not color(0);
i2 <= not color(1) or color(0);
i3 <= not color(1) or not color(0);
D591 <= portb(0) or i1;
D592 <= portb(1) or i3;
D593 <= portb(2) or i0;
D594 <= portb(3) or i0;
D601 <= D604 and i3;
D602 <= D592 and i2;
D603 <= D593 and i1;
D604 <= D591 and D594;
D611 <= portb(4) xor D601;
D612 <= portb(5) xor D602;
D613 <= portb(6) xor D603;
out_r <= not D611;
out_g <= not D612;
out_b <= not D613;
END bdf_type; | gpl-3.0 | e80253b782b7dd284630719548c8daf6 | 0.568613 | 2.653924 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06100_good.vhd | 1 | 3,448 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06100_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Range direction for std_logic_vector: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_06100_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06100_good;
architecture Behavioral of STD_06100_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
--CODE
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
| gpl-3.0 | 7e1e74e772606071d9f17ebc2929e7d6 | 0.510441 | 4.513089 | false | false | false | false |
APastorG/APG | adder/adder_pkg.vhd | 1 | 13,819 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains necessary types, constants, and functions for the parameterized adder
/ design.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package adder_pkg is
/* function used to check the consistency and correctness of generics 1 */
/**************************************************************************************************/
function adder_CHECKS (
max_possible_bit_opt : integer_exc;
truncate_to_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer;
data_low : integer)
return integer;
/* functions for corrected generics and internal/external port signals 2 */
/**************************************************************************************************/
function adder_OH(
max_possible_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer)
return integer;
function adder_OL(
truncate_to_bit_opt : integer_exc;
data_low : integer)
return integer;
/* structures and functions to store and read pipeline positions 3 */
/**************************************************************************************************/
-- PIPELINE_POSITIONS stores the desired position for the pipelines in the adder tree,
-- accumulator and output_buffer.
-- It depends on:
-- 1. total number of possible pipeline positions = ADD_LEVELS + 1(output buffer)
-- 2. the number of desired pipelines
-- 3. '1' or '0' to indicate the presence of a pipeline on that level
/*
type T_pipeline is record
P1 : sulv_v(0 to 1)(1 to 1);
P2 : sulv_v(0 to 2)(1 to 2);
P3 : sulv_v(0 to 3)(1 to 3);
P4 : sulv_v(0 to 4)(1 to 4);
P5 : sulv_v(0 to 5)(1 to 5);
P6 : sulv_v(0 to 6)(1 to 6);
P7 : sulv_v(0 to 7)(1 to 7);
P8 : sulv_v(0 to 8)(1 to 8);
P9 : sulv_v(0 to 9)(1 to 9);
P10: sulv_v(0 to 10)(1 to 10);
P11: sulv_v(0 to 11)(1 to 11);
P12: sulv_v(0 to 12)(1 to 12); -- P12 limit => implies a maximum of 1024 parallel inputs.
-- For PX, limit is 2**(X-2)
end record;
constant PIPELINE_POSITIONS: T_pipeline:=
(P1 => (0 => "0",
1 => "1"),
P2 => (0 => "00",
1 => "01",
2 => "11"),
P3 => (0 => "000",
1 => "001",
2 => "101",
3 => "111"),
P4 => (0 => "0000",
1 => "0001",
2 => "0101",------->4 (P4) possible positions: 2 pipelines wanted=> 2nd and 4th
3 => "1011",
4 => "1111"),
P5 => (0 => "00000",
1 => "00001",
2 => "00101",
3 => "10101",
4 => "10111",
5 => "11111"),
P6 => (0 => "000000",
1 => "000001",
2 => "001001",
3 => "010101",----->6 (P6) possible positions: 3 pipelines wanted=> 2nd, 4th and 6th
4 => "101011",
5 => "101111",
6 => "111111"),
P7 => (0 => "0000000",
1 => "0000001",
2 => "0001001",
3 => "0010101",
4 => "1010101",
5 => "1010111",
6 => "1011111",
7 => "1111111"),
P8 => (0 => "00000000",
1 => "00000001",
2 => "00010001",
3 => "00100101",
4 => "01010101",
5 => "10101011",
6 => "10101111",
7 => "10111111",
8 => "11111111"),
P9 => (0 => "000000000",
1 => "000000001",
2 => "000010001",
3 => "001001001",
4 => "001010101",
5 => "101010101",
6 => "101010111",
7 => "101011111",
8 => "101111111",
9 => "111111111"),
P10 => (0 => "0000000000",
1 => "0000000001",
2 => "0000100001",
3 => "0001001001",
4 => "0010010101",
5 => "0101010101",
6 => "1010101011",
7 => "1010101111",
8 => "1010111111",
9 => "1011111111",
10 => "1111111111"),
P11 => (0 => "00000000000",
1 => "00000000001",
2 => "00000100001",
3 => "00010001001",
4 => "00100100101",
5 => "00101010101",
6 => "10101010101",
7 => "10101010111",
8 => "10101011111",
9 => "10101111111",
10 => "10111111111",
11 => "11111111111"),
P12 => (0 => "000000000000",
1 => "000000000001",
2 => "000001000001",
3 => "000100010001",
4 => "001001001001",
5 => "000101010101",
6 => "010101010101",
7 => "101010101011",
8 => "101010101111",
9 => "101010111111",
10 => "101011111111",
11 => "101111111111",
12 => "111111111111")
);
--function used to read PIPELINE_POSITIONS
function pipeline_is_present(
possible_positions : positive;
pipelines : natural;
level : natural)
return boolean;
--used to get a numerical reference to T_pipeline members, for example pipeline_positions_ref(1)
-- returns PIPELINE_POSITIONS.P1
function pipeline_positions_ref(
number : positive)
return sulv_v;
*/
/* Other functions 4 */
/**************************************************************************************************/
--returns the number of signals in a specific level of the tree adder
function signals_per_level(
P, level : natural)
return natural;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body adder_pkg is
/********************************************************************************************** 1 */
function adder_CHECKS(
max_possible_bit_opt : integer_exc;
truncate_to_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer;
data_low : integer)
return integer is
constant output_h : integer := adder_OH(max_possible_bit_opt,
s,
p,
data_high);
begin
--Errors-----------------------------------------------------------------------------------------
--trying to limit to a bit which is below the data range
assert not(max_possible_bit_opt /= integer'low and max_possible_bit_opt<data_low)
report "(3) " &
"ILLEGAL PARAMETERS in entity adder: MAX_POSSIBLE_BIT_opt set to " &
image(max_possible_bit_opt) & " but the result range is: (" & image(output_h) &
" downto " & image(data_low) & ")."
severity error;
--trying to truncate to a value higher than norm_out_high
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt>output_h)
report "(4) " &
"ILLEGAL PARAMETERS in entity adder: TRUNCATE_TO_BIT_opt set to " &
image(truncate_to_bit_opt) & " but the result range is: (" & image(output_h) &
" downto " & image(data_low) & ")."
severity error;
--trying to truncate to a value higher than the bit limitation (duplicated with 4)
assert not(max_possible_bit_opt /= integer'low and truncate_to_bit_opt /= integer'low and
truncate_to_bit_opt>max_possible_bit_opt)
report "(5) " &
"ILLEGAL PARAMETERS in entity adder: TRUNCATE_TO_BIT_opt cannot have a value higher " &
"than MAX_POSSIBLE_BIT_opt"
severity error;
--Notes------------------------------------------------------------------------------------------
--defined as warning so they appear in the report after synthesis
--note when truncating
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt>data_low)
report "(1) " &
"NOTE in entity adder: truncating to bit " & image(truncate_to_bit_opt) & ". " &
"The bottom " & image(truncate_to_bit_opt-data_low) &
ite(truncate_to_bit_opt-data_low>1," bits are"," bit is") & " being ignored."
severity warning;
--note when truncation adds bits to the right
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt<data_low)
report "(2) " &
"NOTE in entity adder: truncating to bit " & image(truncate_to_bit_opt) & ". " &
image(data_low-truncate_to_bit_opt) &
ite(data_low-truncate_to_bit_opt>1," bits are"," bit is") & " being added to the right."
severity warning;
--note when limiting the number of bits
assert not(max_possible_bit_opt /= integer'low and output_h<(data_high+log2ceil(s*p)))
report "(3) " &
"NOTE in entity adder: limiting the result of the addition to bit " &
image(max_possible_bit_opt) & ". The top " & image((data_high+log2ceil(s*p))-output_h) &
ite((data_high+log2ceil(s*p))-output_h>1," bits are"," bit is") & " not generated."
severity warning;
return 0;
end function;
/********************************************************************************************** 2 */
function adder_OH(
max_possible_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer)
return integer is
begin
if max_possible_bit_opt = integer'low then
return data_high+log2ceil(s*p);
else
return minimum(max_possible_bit_opt, data_high+log2ceil(s*p));
end if ;
end function;
function adder_OL(
truncate_to_bit_opt : integer_exc;
data_low : integer)
return integer is
begin
if truncate_to_bit_opt = integer'low then
return data_low;
else
return truncate_to_bit_opt;
end if ;
end function;
/********************************************************************************************** 3 */
/*
function pipeline_is_present(
possible_positions : positive;
pipelines : natural;
level : natural)
return boolean is
begin
return ite(pipeline_positions_ref(possible_positions)(pipelines)(level)='1', true, false);
end function;
function pipeline_positions_ref(
number: positive)
return sulv_v is
begin
case number is
when 1 => return PIPELINE_POSITIONS.P1;
when 2 => return PIPELINE_POSITIONS.P2;
when 3 => return PIPELINE_POSITIONS.P3;
when 4 => return PIPELINE_POSITIONS.P4;
when 5 => return PIPELINE_POSITIONS.P5;
when 6 => return PIPELINE_POSITIONS.P6;
when 7 => return PIPELINE_POSITIONS.P7;
when 8 => return PIPELINE_POSITIONS.P8;
when 9 => return PIPELINE_POSITIONS.P9;
when 10 => return PIPELINE_POSITIONS.P10;
when 11 => return PIPELINE_POSITIONS.P11;
when 12 => return PIPELINE_POSITIONS.P12;
when others => assert false
report "tried to access nonexistent member of PIPELINE_POSITIONS"
severity failure;
return PIPELINE_POSITIONS.P12;
end case;
end function;
*/
/********************************************************************************************** 4 */
function signals_per_level(
P, level : natural)
return natural is
begin
if level=0 then
return P;
else
return signals_per_level(natural(ceil(real(P)/2.0)), level-1);
end if;
end function signals_per_level;
end package body; | mit | f01973b50157b2be6fd29194a15ec92b | 0.430686 | 4.415439 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 20 | 142,619 | `protect begin_protected
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`protect end_protected
| mit | c3d6eecf19577f308a279f9dd484f737 | 0.954137 | 1.811127 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/thermometersLogic.vhd | 1 | 6,186 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity thermometersLogic is
generic(
termNumber : natural := 128
);
port(
rsTxBusy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
clk3kHz : in std_logic;
rsDataOut : out std_logic_vector(7 downto 0);
rsTxStart : out std_logic;
led : out std_logic_vector(7 downto 0)
);
end thermometersLogic;
architecture Behavioral of thermometersLogic is
component DummyRO
port(
clk : IN std_logic;
osc_out : OUT std_logic
);
end component;
COMPONENT toplevel
PORT(
clk : IN std_logic;
Vccint : OUT std_logic_vector(15 downto 0);
temint : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic;
alarm : OUT std_logic
);
END COMPONENT;
constant THERM_NUMBER_SYSMON_Temp : integer := 2;
constant THERM_NUMBER_SYSMON_Vcc : integer := 3;
signal chosenTermometr : integer range 0 to termNumber;
signal termometrCounter : integer range 0 to 2**16-1;
type state_type is (Start, Numer, Czekaj1, Wartosc1, Czekaj2, Wartosc0);
signal state, next_state : state_type;
signal rsTxStart_i : std_logic;
signal rsDataOut_i : std_logic_vector(7 downto 0);
signal termometrRegister : std_logic_vector(15 downto 0);
signal termometr : std_logic_vector(termNumber downto 0);
signal termometrEnable : std_logic_vector(termNumber downto 0);
signal selectedTermometr : std_logic;
signal nextTerm : std_logic;
signal clk3kHzD : std_logic;
signal clk3kHzD2 : std_logic;
signal sysmon_vcc : std_logic_vector(15 downto 0);
signal sysmon_tem : std_logic_vector(15 downto 0);
attribute keep : string;
attribute keep of termometr : signal is "true";
attribute keep of termometrEnable : signal is "true";
attribute keep of nextTerm : signal is "true";
attribute keep of termometrRegister : signal is "true";
attribute keep of selectedTermometr : signal is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of DummyRO: component is "true";
attribute s: string;
attribute s of termometr: signal is "yes";
attribute s of termometrEnable: signal is "yes";
begin
Inst_toplevel: toplevel PORT MAP(
clk => clk50Mhz,
Vccint => sysmon_vcc,
temint => sysmon_tem,
busy => open,
alarm => open
);
led <= X"55";
Termometers:
for I in 1 to termNumber generate
Inst_DummyRO: DummyRO PORT MAP(
osc_out => termometr(I),
clk => clk50Mhz
);
end generate;
Termometr_Counter:
process (selectedTermometr, nextTerm, clk50Mhz)
begin
if nextTerm = '1' and clk50Mhz = '0' then
termometrCounter <= 0;
elsif selectedTermometr'event and selectedTermometr = '1' then
termometrCounter <= termometrCounter + 1;
end if;
end process;
process (chosenTermometr, termometr)
begin
selectedTermometr <= termometr(chosenTermometr);
end process;
process (nextTerm, rst)
begin
if rst='1' then
termometrRegister <= (others => '0');
elsif nextTerm'event and nextTerm = '1' then
termometrRegister <= std_logic_vector(to_unsigned(termometrCounter,16));
end if;
end process;
Chosen_Termometr:
process (clk3kHz, rst, chosenTermometr)
begin
if rst='1' or chosenTermometr = termNumber then
chosenTermometr <= 0;
termometrEnable <= (others => '0');
elsif clk3kHz='1' and clk3kHz'event then
chosenTermometr <= chosenTermometr + 1;
for I in 1 to termNumber loop
if I = chosenTermometr+1 then
termometrEnable(I) <= '1';
else
termometrEnable(I) <= '0';
end if;
end loop;
end if;
end process;
Next_Term1:
process (clk50Mhz)
begin
if clk50Mhz'event and clk50Mhz='1' then
clk3kHzD <= clk3kHz;
end if;
end process;
Next_Term2:
process (clk50Mhz)
begin
if clk50Mhz'event and clk50Mhz='1' then
clk3kHzD2 <= clk3kHzD;
end if;
end process;
nextTerm <= (not clk3kHzD2) and clk3kHzD;
Synchro:
process (clk50Mhz, rst)
begin
if (rst = '1') then
state <= Start;
rsDataOut <= X"00";
rsTxStart <= '0';
else
if (clk50Mhz'event and clk50Mhz = '1') then
state <= next_state;
rsDataOut <= rsDataOut_i;
rsTxStart <= rsTxStart_i;
end if;
end if;
end process;
Output:
process (state, rsTxBusy, termometrRegister, chosenTermometr)
begin
if (state = Numer and rsTxBusy = '0') then
rsDataOut_i <= std_logic_vector(to_unsigned(chosenTermometr - 1,8));
rsTxStart_i <= '1';
elsif (state = Wartosc1 and rsTxBusy = '0') then
if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then
rsDataOut_i <= sysmon_tem(15 downto 8);
elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then
rsDataOut_i <= sysmon_vcc(15 downto 8);
else
rsDataOut_i <= termometrRegister(15 downto 8);
end if;
rsTxStart_i <= '1';
elsif (state = Wartosc0 and rsTxBusy = '0') then
if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then
rsDataOut_i <= sysmon_tem(7 downto 0);
elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then
rsDataOut_i <= sysmon_vcc(7 downto 0);
else
rsDataOut_i <= termometrRegister(7 downto 0);
end if;
rsTxStart_i <= '1';
else
rsDataOut_i <= X"00";
rsTxStart_i <= '0';
end if;
end process;
Next_stage:
process (state, rsTxBusy, nextTerm)
begin
next_state <= state;
case (state) is
when Start =>
if nextTerm = '1' then
next_state <= Numer;
end if;
when Numer =>
if rsTxBusy = '1' then
next_state <= Czekaj1;
end if;
when Czekaj1 =>
if rsTxBusy = '0' then
next_state <= Wartosc1;
end if;
when Wartosc1 =>
if rsTxBusy = '1' then
next_state <= Czekaj2;
end if;
when Czekaj2 =>
if rsTxBusy = '0' then
next_state <= Wartosc0;
end if;
when Wartosc0 =>
if rsTxBusy = '1' then
next_state <= Start;
end if;
when others =>
next_state <= Start;
end case;
end process;
end Behavioral;
| mit | 92c86134324f7d193ec18bd561999d57 | 0.641125 | 3.073025 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_sitodp_4_no_dsp_32.vhd | 6 | 10,532 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
| mit | 3123dc83a78a490212a5841b5685eac6 | 0.629985 | 3.212935 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult_core_u.vhd | 1 | 26,892 | /***************************************************************************************************
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ 3 space tabs are used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This design of a parameterized real constant multiplier implements the multiplierless multiple
/ constants multiplier by Voronenko-Püschel.
/ The input signal is multiplied by the multiplicands and the result is sent to the output on
/ each clk cycle.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_core_u is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
CONSTANTS : real_v; --compulsory
input_high : integer;
input_low : integer
);
port(
input : in u_ufixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed_v(1 to CONSTANTS'length)
(real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => false)
downto
real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => false)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_core_u_1 of real_const_mult_core_u is
/* corrected generics and internal/external ports' signals */
/***********************************************************************************************/
constant CHECKS : integer := real_const_mult_CHECKS(input_high,
input_low,
false, --unsigned_2comp_opt
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS);
/* constants for the calculation of port sizes */
/***********************************************************************************************/
--the common output size
constant OUT_HIGH : integer := real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => false);
constant OUT_LOW : integer := real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => false);
/* constants related to the multiplicands */
/***********************************************************************************************/
--vector to preserve the sign of each constant
constant MULT_SIGN_POSITIVE : boolean_v := is_positive_vector_from_constants(CONSTANTS);
--vector with the values of the constants in fixed point (applying parameters of error percentage,
--round style and bit to which to round)
constant NO_NEGATIONS : boolean := all_positive(MULT_SIGN_POSITIVE);
constant MULT_FIXED : u_ufixed_v := fixed_from_real_constants(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
abs(CONSTANTS),
input_high,
input_low,
is_signed => false);
--vector with the left shift needed(possibly negative) to transform the constants to odd natural values
constant PRE_VP_SHIFT : integer_v := calculate_pre_vp_shift(MULT_FIXED);
--maximum left shift needed
constant MAX_PRE_VP_SHIFT : integer := maximum(PRE_VP_SHIFT);
--vector with the constants in positive odd form, ready for the Voronenko-Püschel algorithm
constant MULT_FUNDAMENTAL : positive_v := calculate_mult_fundamental(MULT_FIXED, PRE_VP_SHIFT);
constant INTER_LOW : integer := input_low - MAX_PRE_VP_SHIFT;
/* file constants */
/***********************************************************************************************/
constant FILE_NAME : string := generate_file_name(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULT_FUNDAMENTAL);
constant FILE_PATH : string := DATA_FILE_DIRECTORY & "\" /*"*/ & FILE_NAME; --comment inserted to prevent nonsense syntax highlighting on sublime text 3
file solution_input : text;
/* constants obtained from files */
/***********************************************************************************************/
--carries out the Voronenko_Püschel algorithm and saves the solution to a file
procedure generate_solutions_file
is
--pragma translate off
--synthesis translate_off
package mmcm is new work.mmcm_pkg
generic map(
MAX_TARGET => maximum(MULT_FUNDAMENTAL),
FILE_PATH => FILE_PATH
);
--pragma translate on
--synthesis translate_on
begin
--pragma translate off
--synthesis translate_off
mmcm.VorPus(MULT_FUNDAMENTAL);
--pragma translate on
--synthesis translate_on
end procedure;
--reads the number of vertexes in the solution that is in the file. Additionally, as it is the first
--function that is called in the module, the file with the solutions is also generated, or produces
--an error if the file doesn't exist and we are in synthesis trying to read it
impure function read_number_of_vertexes
return natural is
variable currentline : line;
variable currentchar : character;
variable solution : natural := 0;
variable exists : file_open_status;
begin
--pragma translate off
--synthesis translate_off
file_open(solution_input, FILE_PATH, WRITE_MODE);
file_close(solution_input);
generate_solutions_file;
--pragma translate on
--synthesis translate_on
file_open(solution_input, FILE_PATH, READ_MODE);
if endfile(solution_input) then
assert false
report "The values needed to generate multiplication/divisions have not yet been " &
"generated. It is first required to launch the simulation in order to achieve this"
severity error;
end if;
if not endfile(solution_input) then
readline(solution_input, currentline);
for i in 1 to currentline'length loop
read(currentline, currentchar);
solution := 10*solution + (character'pos(currentchar)-character'pos('0'));
end loop;
end if;
file_close(solution_input);
return solution;
end function;
constant NUMBER_OF_VERTEXES : natural := read_number_of_vertexes;
type T_solutions is record
fundamental : positive;
u : positive;
l1 : natural;
v : positive;
l2 : natural;
s : boolean; --true: v is positive, false: v is negative
is_target : boolean;
flevel : natural;
max_child_flevel : natural;
high : integer;
end record;
type T_solutions_v is array(natural range <>) of T_solutions;
procedure insert(
vector : inout T_solutions_v;
index : in positive;
member : in natural;
value : in natural)
is
begin
case member is
when 0 => vector(index).fundamental := value;
when 1 => vector(index).u := value;
when 2 => vector(index).l1 := value;
when 3 => vector(index).v := value;
when 4 => vector(index).l2 := value;
when others => vector(index).s := ite(value=1, true, false);
end case;
end procedure;
function contains(
vector : positive_v;
number : positive)
return boolean is
begin
for i in vector'range loop
if vector(i) = number then
return true;
end if;
end loop;
return false;
end function;
function index_from_fund(
vertexes : T_solutions_v;
fund : positive)
return natural is
variable result : natural := 0;
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).fundamental = fund then
return i;
end if;
end loop;
return result;
end function;
function calculate_max_flevel(
vertexes : T_solutions_v)
return natural is
variable vertex : T_solutions_v(vertexes'range) := vertexes;
variable max_f : natural := 0;
variable aux : natural;
begin
--calculate max_flevel
if NUMBER_OF_VERTEXES > 0 then
vertex(1).flevel := 0;
end if;
if NUMBER_OF_VERTEXES > 1 then
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertex(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertex(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertex(i).flevel := aux;
max_f := maximum(max_f, aux);
end loop;
end if;
return max_f;
end function;
procedure populate_vertexes(
vertexes : inout T_solutions_v;
max_flevel : in natural)
is
variable aux : natural;
variable lowest_child_flevel : natural_v(1 to NUMBER_OF_VERTEXES) := (others => natural'high);
begin
if NUMBER_OF_VERTEXES>0 then
vertexes(1).flevel := 0;
vertexes(1).high := OUT_LOW + input_high - input_low;
end if;
if NUMBER_OF_VERTEXES>1 then
--generate high values for all fundamentals but the first
for i in 2 to NUMBER_OF_VERTEXES loop
vertexes(i).high := calculate_high(vertexes(i).fundamental,
vertexes(1).high,
is_signed => false);
end loop;
--assign values of flevel for all fundamentals' parents but the first
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertexes(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertexes(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertexes(i).flevel := aux;
end loop;
--increase the flevel value of each fundamental to the highest possible(so as to delay the
--operations the most and reduce the registers used in the pipelining)
for j in 1 to NUMBER_OF_VERTEXES loop
--update the lowest flevel of the children for each vertex
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
end loop;
--then increase the flevel when possible
for i in NUMBER_OF_VERTEXES downto 2 loop
if lowest_child_flevel(i) = natural'high then
vertexes(i).flevel := max_flevel;
else
vertexes(i).flevel := lowest_child_flevel(i) - 1;
end if;
end loop;
end loop;
--assign values to max_child_flevel for all fundamentals
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
end loop;
--if the fundamental is a target increase the max_child_flevel to max_flevel
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).is_target then
vertexes(i).max_child_flevel := max_flevel + 1;
end if;
end loop;
end if;
end procedure;
--reads the solution vertexes and returns a static structure with the data
impure function read_vertexes
return T_solutions_v is
variable result : T_solutions_v(1 to NUMBER_OF_VERTEXES);
variable currentline : line;
variable currentchar : character;
variable aux : natural := 0;
variable member : natural := 0;
variable max_f : natural;
begin
file_open(solution_input, FILE_PATH, READ_MODE);
if not endfile(solution_input) then
readline(solution_input, currentline);--discard first line
if not endfile(solution_input) then
for i in 1 to NUMBER_OF_VERTEXES loop
readline(solution_input, currentline);
member := 0;
for j in 1 to currentline'length loop
read(currentline, currentchar);
if currentchar = ' ' then
insert(result, i, member, aux);
aux := 0;
member := member + 1;
else
aux := 10*aux + (character'pos(currentchar)-character'pos('0'));
end if;
end loop;
--add the last read member
insert(result, i, member, aux);
--add whether the actual fundamental is a target (which is not read from the file)
result(i).is_target := contains(MULT_FUNDAMENTAL, result(i).fundamental);
aux := 0;
end loop;
end if;
end if;
file_close(solution_input);
max_f := calculate_max_flevel(result);
populate_vertexes(result, max_f);
return result;
end function;
constant VERTEXES : T_solutions_v(1 to NUMBER_OF_VERTEXES) := read_vertexes;
--same as before but referred directly to the constant VERTEXES
function index_from_fund(
fund : positive)
return natural is
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if VERTEXES(i).fundamental = fund then
return i;
end if;
end loop;
return 0; --when not found return 0
end function;
constant MAX_FLEVEL : natural := calculate_max_flevel(VERTEXES);
/* constants related to pipelines */
/***********************************************************************************************/
--number of possible positions to place pipelines
constant PIPELINE_POSITIONS : natural := MAX_FLEVEL + 1;
--boolean vector which indicates whether a pipeline is placed or not on each possible position
constant IS_PIPELINED : boolean_v(0 to PIPELINE_POSITIONS-1) := generate_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
--number of pipelines
constant PIPELINES : natural := number_of_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
/* signals */
/***********************************************************************************************/
signal fundamental_signals : u_ufixed_vv(1 to NUMBER_OF_VERTEXES)(0 to MAX_FLEVEL)(OUT_HIGH downto INTER_LOW);
signal valid_input_sh : std_ulogic_vector(1 to PIPELINES);
signal pre_output : u_ufixed_v(1 to MULT_FUNDAMENTAL'length)(OUT_HIGH downto OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_valid_output:
if PIPELINES > 0 generate
begin
valid_output <= valid_input_sh(PIPELINES);
process(clk) is
begin
if rising_edge(clk) then
valid_input_sh <= valid_input_sh srl 1;
valid_input_sh(1) <= valid_input;
end if;
end process;
end;
else generate
begin
valid_output <= valid_input;
end;
end generate;
msg_debug("real_const_mult_core_u FILE_PATH: " & string'(FILE_PATH));
msg_debug("real_const_mult_core_u NUMBER_OF_VERTEXES: " & image(NUMBER_OF_VERTEXES));
msg_debug("real_const_mult_core_u OUT_HIGH: " & image(OUT_HIGH));
msg_debug("real_const_mult_core_u OUT_LOW: " & image(OUT_LOW));
generate_each_constant:
for i in 1 to CONSTANTS'length generate
begin
msg_debug("real_const_mult_core_u CONSTANTS(" & image(i) & "): " & image(CONSTANTS(i)));
msg_debug("real_const_mult_core_u MULT_FUNDAMENTAL(" & image(i) & "): " & image(MULT_FUNDAMENTAL(i)));
msg_debug("real_const_mult_core_u PRE_VP_SHIFT(" & image(i) & "): " & image(PRE_VP_SHIFT(i)));
end generate;
pipeline_or_connection_of_input:
if IS_PIPELINED(0) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end if;
end process;
end;
else generate
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end generate;
if_max_child_of_input_is_higher_than_1:
if VERTEXES(1).max_child_flevel > 1 generate
generate_pipelines_fundamental_for_1_for_each_flevel:
for j in 1 to VERTEXES(1).max_child_flevel - 1 generate
constant high : integer := VERTEXES(1).high;
begin
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end generate;
end;
end generate;
end generate;
generate_pipelines_for_other_fundamentals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant first : natural := VERTEXES(i).flevel;
constant last : natural := VERTEXES(i).max_child_flevel - 1;
constant high : integer := vertexes(i).high;
begin
if_last_greater_than_first:
if last > first generate
for_each_flevel:
for j in first+1 to last generate
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end generate;
end generate;
end generate;
end;
end generate;
generate_fundamental_signals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant current : T_solutions := VERTEXES(i);
constant u : positive := current.u;
constant l1 : natural := current.l1;
constant v : positive := current.v;
constant l2 : natural := current.l2;
constant s : boolean := current.s;
constant flevel : natural := current.flevel;
constant high : integer := current.high;
constant u_high : integer := vertexes(index_from_fund(u)).high;
constant v_high : integer := vertexes(index_from_fund(v)).high;
signal signal1 : u_ufixed(u_high downto OUT_LOW);
signal signal2 : u_ufixed(v_high downto OUT_LOW);
signal signal3 : u_ufixed(u_high+1 downto OUT_LOW);
signal aux1 : u_ufixed(high downto OUT_LOW);
signal aux2 : u_ufixed(high downto OUT_LOW);
signal aux3 : u_ufixed(high+1 downto OUT_LOW);
signal result1 : u_ufixed(high downto OUT_LOW);
signal result2 : u_ufixed(high+1 downto OUT_LOW);
begin
signal1 <= fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW);
signal2 <= fundamental_signals(index_from_fund(v))(flevel-1)(v_high downto OUT_LOW);
signal3 <= resize(fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW), signal3);
aux1 <= resize(signal1, aux1) sll l1;
aux2 <= resize(signal2, aux2) sll l2;
aux3 <= resize(signal3, aux3) sll l1;
result1 <= resize(aux1 + aux2, result1);
result2 <= resize(aux3 - resize(aux2, aux3), result2);
pipeline_or_connection:
if IS_PIPELINED(flevel) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW) when s else
result2(high downto OUT_LOW);
end if;
end process;
end;
else generate
begin
positive_or_negative:
if s generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW);
else generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result2(high downto OUT_LOW);
end generate;
end;
end generate;
end;
end generate;
invert_output:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
signal aux : u_ufixed(high downto OUT_LOW);
signal result1 : u_ufixed(high downto OUT_LOW);
begin
aux <= fundamental_signals(index)(MAX_FLEVEL)(high downto OUT_LOW);
result1 <= resize(aux, result1);
pre_output(i)(result1'range) <= result1;
end;
end generate;
generate_output_shifts:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
constant adjustment : integer := -PRE_VP_SHIFT(i) - (OUT_LOW - input_low);
begin
depending_on_adjustment_value:
if adjustment > 0 generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sll
adjustment;
else generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sra
abs(adjustment); --to introduce the leftmost bit when shifting to the right
end generate;
end;
end generate;
end architecture; | mit | 09498f2ca25f6dce35f3f07f5c12e252 | 0.491529 | 4.528668 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04900_good.vhd | 1 | 3,184 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_04900_good.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Edge detection best practice: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Sig_re: Rising edge detection of My_Signal
-- My_Sig_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_04900_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_A : in std_logic; -- Signal on which detect edges
o_A_re : out std_logic; -- Rising edge of A
o_A_fe : out std_logic; -- Falling edge of A
o_A_ae : out std_logic -- Any edge of A
);
end STD_04900_good;
architecture Behavioral of STD_04900_good is
signal A_r1 : std_logic; -- i_A registered 1 time
signal A_r2 : std_logic; -- i_A registered 2 times
begin
--CODE
-- Registration process to be able to detect edges of signal A
P_Registration : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
A_r1 <= '0';
A_r2 <= '0';
elsif (rising_edge(i_Clock)) then
A_r1 <= i_A;
A_r2 <= A_r1;
end if;
end process;
-- Assign the outputs of the module:
o_A_re <= A_r1 and not A_r2;
o_A_fe <= not A_r1 and A_r2;
o_A_ae <= A_r1 xor A_r2;
end Behavioral;
--CODE
| gpl-3.0 | b5dae8c47af3f5ad52bb9d6d345d24a9 | 0.479271 | 4.189474 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/sysmon_v2.vhd | 1 | 3,560 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity toplevel is
Port (clk : in STD_LOGIC;
Vccint : out STD_LOGIC_VECTOR (15 downto 0);
temint : out STD_LOGIC_VECTOR (15 downto 0);
busy : out STD_LOGIC;
alarm : out STD_LOGIC);
end toplevel;
architecture Behavioral of toplevel is
signal dobus : std_logic_vector(15 downto 0);
signal vccint_temp : std_logic_vector(15 downto 0);
signal temint_temp : std_logic_vector(15 downto 0);
signal vccint_temp_next : std_logic_vector(15 downto 0);
signal temint_temp_next : std_logic_vector(15 downto 0);
signal addr : std_logic_vector(6 downto 0);
signal addr_next : std_logic_vector(6 downto 0);
signal alm: std_logic_vector(2 downto 0);
signal eos: std_logic;
signal rdy: std_logic;
type state_type is (read_vcc, store_vcc, read_tem, store_tem);
signal currState, nextState : state_type;
begin
process(clk)
begin
if rising_edge(clk) then
currState <= nextState;
vccint_temp <= vccint_temp_next;
temint_temp <= temint_temp_next;
addr <= addr_next;
end if;
end process;
process(currState, dobus, vccint_temp, temint_temp)
begin
case currState is
when read_vcc =>
nextState <= store_vcc;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000001";
when store_vcc =>
if rdy = '1' then
nextState <= read_tem;
vccint_temp_next <= "000000" & dobus(15 downto 6);
else
nextState <= store_vcc;
vccint_temp_next <= vccint_temp;
end if;
temint_temp_next <= temint_temp;
addr_next <= "0000001";
when read_tem =>
nextState <= store_tem;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000000";
when store_tem =>
if rdy = '1' then
nextState <= read_vcc;
temint_temp_next <= "000000" & dobus(15 downto 6);
else
nextState <= store_tem;
temint_temp_next <= temint_temp;
end if;
vccint_temp_next <= vccint_temp;
addr_next <= "0000000";
when others =>
nextState <= read_vcc;
vccint_temp_next <= vccint_temp;
temint_temp_next <= temint_temp;
addr_next <= "0000000";
end case;
end process;
vccint <= vccint_temp;
temint <= temint_temp;
-- Connect ALM[2] (Vccaux alarm) to output
alarm <= alm(2);
my_sysmon : SYSMON
generic map(
INIT_40 => X"0000",
INIT_41 => X"20C7",
INIT_42 => X"0A00",
INIT_43 => X"0000",
INIT_44 => X"0000",
INIT_45 => X"0000",
INIT_46 => X"0000",
INIT_47 => X"0000",
INIT_48 => X"0301",
INIT_49 => X"0000",
INIT_4A => X"0000", -- Sequence register 2
INIT_4B => X"0000", -- Sequence register 3
INIT_4C => X"0000", -- Sequence register 4
INIT_4D => X"0000", -- Sequence register 5
INIT_4E => X"0000", -- Sequence register 6
INIT_4F => X"0000", -- Sequence register 7
INIT_50 => X"0000", -- Alarm limit register 0
INIT_51 => X"0000", -- Alarm limit register 1
INIT_52 => X"E000", -- Alarm limit register 2
INIT_53 => X"0000", -- Alarm limit register 3
INIT_54 => X"0000", -- Alarm limit register 4
INIT_55 => X"0000", -- Alarm limit register 5
INIT_56 => X"CAAA", -- Alarm limit register 6
INIT_57 => X"0000", -- Alarm limit register 7
SIM_MONITOR_FILE => "vccaux_alarm.txt" --Stimulus file for analog simulation
)
port map (
DCLK => clk,
DWE => '0',
DEN => eos,
DRDY => rdy,
DADDR => addr,
DO => dobus,
CHANNEL => open,
EOS => eos,
BUSY => busy,
ALM => alm,
RESET=> '0',
CONVST => '0',
CONVSTCLK => '0',
DI => "0000000000000000",
VAUXN => "0000000000000000",
VAUXP=> "0000000000000000",
VN => '0',
VP => '0'
);
end Behavioral;
| mit | ed8e8aec7fb4cea79d65dd77500ed34c | 0.661517 | 2.882591 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05700_good.vhd | 1 | 3,495 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05700_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of gated clocks: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_05700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_Data : in std_logic; -- Input data
o_Data : out std_logic; -- Output data
o_Gated_Clock : out std_logic -- Gated clock
);
end STD_05700_good;
architecture Behavioral of STD_05700_good is
signal Enable_r : std_logic;
signal Data_r : std_logic; -- Data signal registered
signal Data_r2 : std_logic; -- Data signal registered twice
begin
DFF_En : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_Enable,
o_Q => Enable_r,
o_Q_n => open
);
-- Make the Flip-Flop work when Enable signal is at 1
-- Enable signal on D Flip-flop
P_Sync_Data : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Data_r <= '0';
Data_r2 <= '0';
elsif (rising_edge(i_Clock)) then
if (Enable_r = '1') then
Data_r <= i_Data;
Data_r2 <= Data_r;
end if;
end if;
end process;
o_Data <= Data_r2;
end Behavioral;
--CODE
| gpl-3.0 | acbc8ffab07f7f5aa4135567b1e0293c | 0.480114 | 4.267399 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/cpu/T80.vhd | 2 | 32,378 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 | bccd5735ddfe4f75abd323551d47aba2 | 0.495923 | 3.04935 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/text_mem.vhd | 1 | 2,009 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: text_mem
--
-- Description:
--
-- Dual-port RAM for Text (cahar address in char_rom)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity text_mem is
generic(
MEM_ADDR_WIDTH : natural := 32;
MEM_DATA_WIDTH : natural := 32;
MEM_SIZE : natural := 4800
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
wr_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- Slave address input
rd_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- Slave address input
wr_data_i : in std_logic_vector(MEM_DATA_WIDTH-1 downto 0); -- Write data output
we_i : in std_logic; -- 1-write transaction
rd_data_o : out std_logic_vector(MEM_DATA_WIDTH-1 downto 0) -- read data output
);
end entity;
architecture arc_text_mem of text_mem is
type t_text_mem is array (0 to MEM_SIZE-1) of std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
signal index_t : natural;
signal index : natural;
signal text_mem : t_text_mem := (
-- 0 => "000000",
-- 1 => "000001",
-- 2 => "000010",
others => (others => '0')
);
begin
DP_TEXT_MEM : process (clk_i) begin
if (rising_edge(clk_i)) then
if (we_i = '1') then
text_mem(conv_integer(wr_addr_i)) <= wr_data_i; -- update img_mem from out_mem
end if;
rd_data_o <= text_mem(conv_integer(index));
end if;
end process;
index_t <= conv_integer(rd_addr_i);
index <= index_t when (index_t < text_mem'length) else 0;
end arc_text_mem; | mit | 44891381b096834a88e52655b0fe97df | 0.519164 | 3.342762 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/dac.vhd | 1 | 1,150 | library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 15
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;
| gpl-3.0 | 82f9322add49a2487843ed6edc278452 | 0.55913 | 2.738095 | false | false | false | false |
APastorG/APG | pipelines/pipelines_core.vhd | 1 | 2,743 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines_core is
generic(
LENGTH : natural;
INPUT_HIGH : integer;
INPUT_LOW : integer
);
port(
clk : in std_ulogic;
input : in std_ulogic_vector;
output : out std_ulogic_vector
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_core_1 of pipelines_core is
/*================================================================================================*/
/*================================================================================================*/
begin
generate_pipelines:
if LENGTH = 0 generate
begin
output <= input;
end;
elsif LENGTH = 1 generate
signal aux : std_ulogic_vector(input'range);
begin
process (clk) is
begin
if rising_edge(clk) then
aux <= input;
output <= aux;
end if;
end process;
end;
else generate
signal aux : sulv_v(1 to LENGTH)(input'range);
begin
process (clk) is
begin
if rising_edge(clk) then
aux(1) <= input;
aux(2 to LENGTH) <= aux(1 to LENGTH-1);
output <= aux(LENGTH);
end if;
end process;
end;
end generate;
end architecture; | mit | bc99d18440867a4c5bcd3f6f8da3c258 | 0.336286 | 5.239845 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06000_good.vhd | 1 | 3,264 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06000_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Range direction for arrays: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06000_good is
generic(
g_Data_Width : positive := 4;
g_Pipeline_Length : positive := 4
);
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_Data : in std_logic_vector(g_Data_Width-1 downto 0); -- Incoming data to write
o_Data : out std_logic_vector(g_Data_Width-1 downto 0) -- Data read
);
end STD_06000_good;
--CODE
architecture Behavioral of STD_06000_good is
type t_Pipeline is array (0 to g_Pipeline_Length-1) of std_logic_vector(g_Data_Width-1 downto 0); -- Array for signal registration
signal D : t_Pipeline; -- Actual signal
begin
P_Register_Bank : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
D <= (others => (others => '0'));
elsif (rising_edge(i_Clock)) then
D(0) <= i_Data;
for i in 1 to g_Pipeline_Length-1 loop
D(i) <= D(i-1);
end loop;
end if;
end process;
o_Data <= D(g_Pipeline_Length-1);
end Behavioral;
--CODE
| gpl-3.0 | d5a63da4d9c77798b7dc5f9875416dcd | 0.494792 | 4.352 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_serieseOg.vhd | 4 | 3,084 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 0ed37b617b206f935df034536a091d4c | 0.480545 | 3.654028 | false | false | false | false |
APastorG/APG | pipelines/pipelines_s.vhd | 1 | 2,171 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines_s is
generic(
LENGTH : natural
);
port(
clk : in std_ulogic;
input : in u_sfixed;
output : out u_sfixed
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_s_1 of pipelines_s is
signal input_aux : std_ulogic_vector(input'length-1 downto 0);
signal output_aux : std_ulogic_vector(input'length-1 downto 0);
begin
pipelines_core_1:
entity work.pipelines_core
generic map(
LENGTH => LENGTH,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input_aux,
output => output_aux
);
output <= to_sfixed(output_aux, input'high, input'low);
input_aux <= std_ulogic_vector(input);
end architecture; | mit | ac51700cdd158c73842e2551760229ac | 0.36453 | 4.79148 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/vga_sync.vhd | 1 | 14,759 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: vga_sync
--
-- Description:
--
-- Implementation of VGA synchronization
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga_sync is
generic (
HORIZONTAL_RES : natural := 800;
VERTICAL_RES : natural := 600;
FRAME_SIZE : natural := 4
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
show_frame_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
--
active_pixel_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
pixel_row_o : out std_logic_vector (10 downto 0);
pixel_column_o : out std_logic_vector (10 downto 0);
horiz_sync_o : out std_logic;
vert_sync_o : out std_logic;
psave_o : out std_logic;
blank_o : out std_logic;
pix_clk_o : out std_logic;
sync_o : out std_logic
);
end vga_sync;
architecture rtl of vga_sync is
signal horiz_sync_r : std_logic;
signal vert_sync_r : std_logic;
signal enable_s : std_logic;
signal h_count_r : std_logic_vector( 10 downto 0 );
signal v_count_r : std_logic_vector( 10 downto 0 );
signal horiz_sync_out_d_r : std_logic;
signal vert_sync_out_d_r : std_logic;
signal psave_d_r : std_logic;
signal blank_d_r : std_logic;
signal sync_d_r : std_logic;
-- signali za registrovanje izlaza
signal red_r : std_logic_vector(7 downto 0);
signal green_r : std_logic_vector(7 downto 0);
signal blue_r : std_logic_vector(7 downto 0);
signal horiz_sync_out_r : std_logic;
signal vert_sync_out_r : std_logic;
signal pixel_row_r : std_logic_vector(10 downto 0);
signal pixel_column_r : std_logic_vector(10 downto 0);
signal psave_r : std_logic;
signal blank_r : std_logic;
signal sync_r : std_logic;
-- konstatne horizontalne sinhronizacije
signal h_pixels : integer range 0 to 2047;
signal h_frontporch : integer range 0 to 2047;
signal h_sync_time : integer range 0 to 2047;
signal h_backporch : integer range 0 to 2047;
-- konstatne vertikalne sinhronizacije
signal v_lines : integer range 0 to 2047;
signal v_frontporch : integer range 0 to 2047;
signal v_sync_time : integer range 0 to 2047;
signal v_backporch : integer range 0 to 2047;
signal active_frame : std_logic;
begin
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- definisanje parametara potrebnih za sihronizacione signale
-- ovi parametri zavise od rezolucije
res_0 : if ( HORIZONTAL_RES = 64 and VERTICAL_RES = 48 ) generate
h_pixels <= 64;
h_frontporch <= 2 ;
h_sync_time <= 2 ;
h_backporch <= 2 ;
v_lines <= 48;
v_frontporch <= 2 ;
v_sync_time <= 2 ;
v_backporch <= 2 ;
end generate res_0;
res_1 : if ( HORIZONTAL_RES = 640 and VERTICAL_RES = 480 ) generate
h_pixels <= 640;
h_frontporch <= 16 ;
h_sync_time <= 96 ;
h_backporch <= 40 ;
v_lines <= 480;
v_frontporch <= 11 ;
v_sync_time <= 2 ;
v_backporch <= 31 ;
end generate res_1;
res_2 : if ( HORIZONTAL_RES = 800 and VERTICAL_RES = 600 ) generate
h_pixels <= 800;
h_frontporch <= 56 ;
h_sync_time <= 120;
h_backporch <= 64 ;
v_lines <= 600;
v_frontporch <= 37 ;
v_sync_time <= 6 ;
v_backporch <= 23 ;
end generate res_2;
res_3 : if ( HORIZONTAL_RES = 1024 and VERTICAL_RES = 768 ) generate
h_pixels <= 1024;
h_frontporch <= 24 ;
h_sync_time <= 136 ;
h_backporch <= 144 ;
v_lines <= 768 ;
v_frontporch <= 3 ;
v_sync_time <= 6 ;
v_backporch <= 29 ;
end generate res_3;
res_4 : if ( HORIZONTAL_RES = 1152 and VERTICAL_RES = 864 ) generate
h_pixels <= 1152;
h_frontporch <= 64 ;
h_sync_time <= 128 ;
h_backporch <= 256 ;
v_lines <= 864 ;
v_frontporch <= 1 ;
v_sync_time <= 3 ;
v_backporch <= 32 ;
end generate res_4;
res_5 : if ( HORIZONTAL_RES = 1280 and VERTICAL_RES = 1024 ) generate
h_pixels <= 1280;
h_frontporch <= 48 ;
h_sync_time <= 112 ;
h_backporch <= 248 ;
v_lines <= 1024;
v_frontporch <= 1 ;
v_sync_time <= 3 ;
v_backporch <= 38 ;
end generate res_5;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
--
-- |<--- active region --->|<----------- blanking region ---------->|<--- active region --->|<----------- blanking region ---------->|
-- | (pixels) | | (pixels) | |
-- | (lines) | | (lines) | |
-- | | | | |
-- ----+---------- ... --------+------------- --------------+---------- ... --------+------------- --------------+--
-- | | | | | | | | | |
-- | | |<--front |<---sync |<---back | |<--front |<---sync |<---back |
-- | | | porch-->| time--->| porch--->| | porch-->| time--->| porch--->|
------ | | --------------- | | --------------- |
-- | | | | |
-- |<------------------- period ----------------------------------->|<------------------- period ----------------------------------->|
--
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- broji od nule do pune velicine linije
process(clk_i)
begin
if ( clk_i'event and clk_i = '1' ) then
if ( rst_n_i = '0' ) then h_count_r <= (others => '0');
else
if ( h_count_r < ( h_sync_time + h_pixels + h_frontporch + h_backporch) ) then h_count_r <= h_count_r + 1;
else h_count_r <= (others => '0');
end if;
end if;
end if;
end process;
-- generise hsyncb : nula je nad hor sync_o
process(clk_i)
begin
if ( clk_i'event and clk_i = '1') then
if ( rst_n_i = '0') then horiz_sync_r <= '1';
else
if ( (h_count_r >= (h_frontporch + h_pixels)) and (h_count_r < (h_pixels + h_frontporch + h_sync_time) )) then horiz_sync_r <= '0';
else horiz_sync_r <= '1';
end if;
end if;
end if;
end process;
-- uvecava vcnt na rastucu ivicu hor sync_o
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( rst_n_i = '0' ) then v_count_r <= (others => '0');
else
if ( h_count_r = h_pixels + h_frontporch + h_sync_time ) then
if ( v_count_r < (v_sync_time + v_lines + v_frontporch + v_backporch) ) then v_count_r <= v_count_r + 1;
else v_count_r <= (others => '0');
end if;
end if;
end if;
end if;
end process;
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( rst_n_i = '0' ) then vert_sync_r <= '1';
else
if ( h_count_r = h_pixels + h_frontporch + h_sync_time ) then
if (v_count_r >= (v_lines + v_frontporch) and v_count_r < (v_lines + v_frontporch + v_sync_time)) then vert_sync_r <= '0';
else vert_sync_r <= '1';
end if;
end if;
end if;
end if;
end process;
process (h_count_r,v_count_r,h_pixels, v_lines)
begin
if ( (h_count_r >= h_pixels) or (v_count_r >= v_lines) ) then enable_s <= '0';
else enable_s <= '1';
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- registrovanje signala
reg_outputs_1:process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_n_i = '0') then
horiz_sync_out_r <= '0';
vert_sync_out_r <= '0';
psave_r <= '0';
blank_r <= '0';
sync_r <= '0';
horiz_sync_out_d_r <= '0';
vert_sync_out_d_r <= '0';
psave_d_r <= '0';
blank_d_r <= '0';
sync_d_r <= '0';
else
horiz_sync_out_d_r <= horiz_sync_r ;
vert_sync_out_d_r <= vert_sync_r ;
psave_d_r <= '1' ;
blank_d_r <= enable_s ;
sync_d_r <= vert_sync_r and horiz_sync_r;
horiz_sync_out_r <= horiz_sync_out_d_r;
vert_sync_out_r <= vert_sync_out_d_r ;
psave_r <= psave_d_r ;
blank_r <= blank_d_r ;
sync_r <= sync_d_r ;
end if;
end if;
end process reg_outputs_1;
reg_outputs_2:process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_n_i = '0') then
red_r <= (others => '0');
green_r <= (others => '0');
blue_r <= (others => '0');
else
if ( enable_s = '1' ) then
if (direct_mode_i = '1') then
red_r <= dir_red_i;
green_r <= dir_green_i;
blue_r <= dir_blue_i;
elsif (show_frame_i = '1' and active_frame = '1') then
red_r <= frame_color_i(23 downto 16);
green_r <= frame_color_i(15 downto 8);
blue_r <= frame_color_i(7 downto 0);
elsif (active_pixel_i = '1') then
red_r <= foreground_color_i(23 downto 16);
green_r <= foreground_color_i(15 downto 8);
blue_r <= foreground_color_i(7 downto 0);
else
red_r <= background_color_i(23 downto 16);
green_r <= background_color_i(15 downto 8);
blue_r <= background_color_i(7 downto 0);
end if;
end if;
end if;
end if;
end process reg_outputs_2;
process (v_count_r,h_count_r)begin
if (--okvir
v_count_r < FRAME_SIZE or
v_count_r > (VERTICAL_RES - FRAME_SIZE-1) or
h_count_r < FRAME_SIZE or
h_count_r > (HORIZONTAL_RES - FRAME_SIZE-1)) then
active_frame <= '1';
else
active_frame <= '0';
end if;
end process;
-- povezivanje signala na izlaz
red_o <= red_r ;
green_o <= green_r ;
blue_o <= blue_r ;
horiz_sync_o <= horiz_sync_out_r;
vert_sync_o <= vert_sync_out_r ;
pixel_row_o <= v_count_r ;
pixel_column_o <= h_count_r ;
psave_o <= psave_r ;
blank_o <= blank_r ;
pix_clk_o <= clk_i ;
sync_o <= sync_r ;
end rtl;
| mit | 5eb72a208b0a801e5aa62680407b24f8 | 0.363643 | 3.983536 | false | false | false | false |
APastorG/APG | butterfly/butterfly.vhd | 1 | 2,872 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ The input must have ranges of type for example (0 to 7)(high downto low)
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity butterfly is
generic(
SPEED_opt : T_speed;
EXTEND_opt : boolean
);
port(
clk : in std_ulogic;
input : in sulv_v;
output : out sulv_v
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture butterfly_1 of butterfly is
signal aux_in : u_sfixed_v(input'range)
(input'element'high downto input'element'low);
signal aux_out : u_sfixed_v(input'range)
(input'element'high+1 downto input'element'low);
/*================================================================================================*/
/*================================================================================================*/
begin
butterfly_core_s_1:
entity work.butterfly_core_s
generic map(
SPEED_opt => SPEED_opt,
EXTEND_opt => EXTEND_opt,
RANGE1_LEFT => input'left,
RANGE1_RIGHT => input'right,
RANGE2_LEFT => input'element'left,
RANGE2_RIGHT => input'element'right
)
port map(
clk => clk,
input => aux_in,
output => aux_out
);
generate_ports:
for i in input'range generate
begin
aux_in(i) <= to_sfixed(input(i), aux_in(i));
output(i) <= to_sulv(aux_out(i));
end;
end generate;
end architecture; | mit | f1d9ee491be91918506d979367fff292 | 0.366455 | 4.714286 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/pic_tb.vhdl | 2 | 13,625 | ------------------------------------------------------------------------------
---- ----
---- gmzpu programmable interrupt controller (pic) testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the PIC ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: pic_TB ----
---- File name: pic_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.pic;
entity pic_TB is
end entity pic_TB;
architecture Behave of pic_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant DATA_WIDTH : natural:=16;
constant ADR_WIDTH : natural:=16;
constant N_BANKS : natural:=2;
component interrupt_controller is
generic(
-- address width (truncated to DATA_WIDTH)
ADR_WIDTH : natural:=4;
-- data bus width
DATA_WIDTH : natural:=32;
-- number of interrupt banks (each bank is DATA_WIDTH interrupt lines)
N_BANKS : natural:=2
);
port (
irq_o : out std_logic;
-- interrupt lines
int_i : in std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic
);
end component interrupt_controller;
type sample is record
-- inputs
int_i : std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
rst_i : std_logic;
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : std_logic;
wb_lock_i : std_logic;
wb_sel_i : std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : std_logic;
wb_tga_i : unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : unsigned(DATA_WIDTH-1 downto 0);
wb_we_i : std_logic;
-- outputs
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- int_i rst wb_dat_i wb_tgd_i wb_adr_i cyc lock wb_sel_i stb wb_tga_i wb_tgc_i we
-- reset
(X"00000000", '1', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '1', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- write IMR0 <= X"FFFF"
(X"00000000", '0', X"FFFF", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"FFFF", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read IMR0 (X"FFFF")
(X"00000000", '0', X"0000", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0001", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read IMR1 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0005", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0005", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- raise interrupt in bank 0
(X"00000100", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR0 (X"0100")
-- int_i rst wb_dat_i wb_tgd_i wb_adr_i cyc lock wb_sel_i stb wb_tga_i wb_tgc_i we
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR1 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- reset ICR0 (X"0000")
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '1', '0', X"0000", '1', X"0000", X"0000", '1'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- raise interrupt in bank 1
(X"00200000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- read ICR1 (X"0020"), pipelined mode
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '1', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0004", '1', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0'),
-- term
(X"00000000", '0', X"0000", X"0000", X"0000", '0', '0', X"0000", '0', X"0000", X"0000", '0')
);
signal clk : std_logic;
signal irq_o : std_logic;
-- interrupt lines
signal int_i : std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
signal rst_i : std_logic;
signal clk_i : std_logic;
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgd_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_o : std_logic;
signal wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal wb_cyc_i : std_logic;
signal wb_stall_o : std_logic;
signal wb_err_o : std_logic;
signal wb_lock_i : std_logic;
signal wb_rty_o : std_logic;
signal wb_sel_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb_i : std_logic;
signal wb_tga_i : unsigned(ADR_WIDTH-1 downto 0);
signal wb_tgc_i : unsigned(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we_i : std_logic;
begin
pic : interrupt_controller
generic map(
DATA_WIDTH => DATA_WIDTH, N_BANKS => N_BANKS, ADR_WIDTH => ADR_WIDTH
)
port map(irq_o => irq_o, int_i => int_i, rst_i => rst_i, clk_i => clk,
wb_dat_o => wb_dat_o, wb_dat_i => wb_dat_i, wb_tgd_o => wb_tgd_o,
wb_tgd_i => wb_tgd_i, wb_ack_o => wb_ack_o, wb_adr_i => wb_adr_i,
wb_cyc_i => wb_cyc_i, wb_stall_o => wb_stall_o, wb_err_o => wb_err_o,
wb_lock_i => wb_lock_i, wb_rty_o => wb_rty_o, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_tga_i => wb_tga_i, wb_tgc_i => wb_tgc_i,
wb_we_i => wb_we_i);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
clk <= '0';
wait for CLK_S_PER;
int_i <= test_data(i).int_i;
rst_i <= test_data(i).rst_i;
wb_dat_i <= test_data(i).wb_dat_i;
wb_tgd_i <= test_data(i).wb_tgd_i;
wb_adr_i <= test_data(i).wb_adr_i;
wb_cyc_i <= test_data(i).wb_cyc_i;
wb_lock_i <= test_data(i).wb_lock_i;
wb_sel_i <= test_data(i).wb_sel_i;
wb_stb_i <= test_data(i).wb_stb_i;
wb_tga_i <= test_data(i).wb_tga_i;
wb_tgc_i <= test_data(i).wb_tgc_i;
wb_we_i <= test_data(i).wb_we_i;
clk <= '1';
wait for CLK_S_PER;
--assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity failure;
--assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause | decc6c4e1223c4f0b3e1aca12b8767e8 | 0.397798 | 3.347666 | false | true | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/divrom/divrom.vhd | 1 | 5,434 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file divrom.vhd when simulating
-- the core, divrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY divrom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END divrom;
ARCHITECTURE divrom_a OF divrom IS
-- synthesis translate_off
COMPONENT wrapped_divrom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_divrom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "divrom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 8192,
c_read_depth_b => 8192,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 8192,
c_write_depth_b => 8192,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_divrom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END divrom_a;
| gpl-3.0 | c534914f74dfd3538cbb7d4c86dc7dfb | 0.515274 | 3.969321 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03800_good.vhd | 1 | 3,011 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03800_good.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Synchronous elements initialization: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03800_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end STD_03800_good;
--CODE
architecture Behavioral of STD_03800_good is
signal Q : std_logic; -- D Flip-Flop output
signal Q_n : std_logic; -- Same as Q, inverted
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
Q_n <= '1';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
Q_n <= not i_D;
end if;
end process;
o_Q <= Q;
o_Q_n <= Q_n;
end Behavioral;
--CODE
| gpl-3.0 | ee780c8cbb60acbc13ab8a49327716b6 | 0.47094 | 4.427941 | false | false | false | false |
APastorG/APG | adder/adder_u.vhd | 1 | 4,647 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_u is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_ufixed_v;
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_u1 of adder_u is
constant P : positive := input'length(1);
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high,
input(1)'low);
/*================================================================================================*/
/*================================================================================================*/
begin
adder_core_u_1:
entity work.adder_core_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; | mit | fcba3567da7c732f672f6cee35123ee0 | 0.428138 | 4.721597 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03000_good.vhd | 1 | 2,944 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03000_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Comments for objects declaration statements: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03000_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03000_good;
--CODE
architecture Behavioral of STD_03000_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable = '1') then -- D Flip-Flop enabled
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
| gpl-3.0 | 52a0cc3a7e504d3592cf43ef731fc24c | 0.475204 | 4.550232 | false | false | false | false |
Subsets and Splits