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stringlengths 6
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int64 1
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
sonologic/gmzpu | roms/vhdl/footer.vhdl | 1 | 458 | others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | 92d3638441732289f56a810ba02db122 | 0.574236 | 3.343066 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb_agen.vhd | 6 | 4,308 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUT_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END LUT_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 9fb053dad5cfc955b95b2603e9aa7fc0 | 0.594475 | 4.455016 | false | false | false | false |
223323/lab2 | HDL/source/coregen/dcm25MHz.vhd | 1 | 6,535 | -- file: dcm25MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____25.000______0.000______50.0______999.999____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________27____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm25MHz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm25MHz;
architecture xilinx of dcm25MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm25MHz,clk_wiz_v3_6,{component_name=dcm25MHz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 27,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 37.037,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | da4c692977ad7dd8de52f00e979b70e1 | 0.55899 | 4.282438 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_dmul_4_max_dsp_64.vhd | 6 | 10,824 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dmul_4_max_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dmul_4_max_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dmul_4_max_dsp_64_arch OF sin_taylor_series_ap_dmul_4_max_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dmul_4_max_dsp_64_arch;
| mit | cfdaf0a00bdd6b53a04798c098bb712e | 0.632391 | 3.203315 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05900_good.vhd | 1 | 3,405 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05900_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Range for integers: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05900_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(7 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(7 downto 0) -- Counter (unsigned value)
);
end STD_05900_good;
architecture Behavioral of STD_05900_good is
signal Count : integer range 0 to 255; -- Counter output signal
signal Count_Length : integer range 0 to 255; -- Length input signal
begin
--CODE
Count_Length <= to_integer(unsigned(i_Length));
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= 0;
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= 0;
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(to_unsigned(Count, o_Count'length));
end Behavioral;
| gpl-3.0 | 9d34233a835883eaa9913f3fa632f539 | 0.509251 | 4.498018 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/lvov.vhd | 1 | 12,585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lvov is
Port (
CLK50 : IN STD_LOGIC;
PS2_CLK : in STD_LOGIC;
PS2_DATA : in STD_LOGIC;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CS : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC );
end lvov;
architecture Behavioral of lvov is
component k580wm80a is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
intr : in std_logic;
idata : in std_logic_vector(7 downto 0);
addr : out std_logic_vector(15 downto 0);
sync : out std_logic;
rd : out std_logic;
wr_n : out std_logic;
inta_n : out std_logic;
odata : out std_logic_vector(7 downto 0);
inte_o : out std_logic );
end component;
signal CLK : std_logic;
signal RESET : std_logic := '0';
signal TICK : std_logic_vector(3 downto 0) := "0000";
signal SRAM_DI : std_logic_vector(7 downto 0);
signal SRAM_DO : std_logic_vector(7 downto 0);
signal KEYB_A : std_logic_vector(7 downto 0);
signal KEYB_D : std_logic_vector(7 downto 0);
signal KEYB_A2 : std_logic_vector(3 downto 0);
signal KEYB_D2 : std_logic_vector(3 downto 0);
signal KEYB_CTRL : std_logic_vector(7 downto 0);
signal COLORS : std_logic_vector(6 downto 0);
signal ROM_D : std_logic_vector(7 downto 0);
signal ROM_INIT : std_logic;
signal CPU_CLK : std_logic;
signal CPU_SYNC : std_logic;
signal CPU_RD : std_logic;
signal CPU_WR_N : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal IO_RD : std_logic;
signal IO_WR : std_logic;
signal MEM_RD : std_logic;
signal MEM_WR : std_logic;
signal XSD_EN : std_logic;
signal XSDROM_D : std_logic_vector(7 downto 0);
signal XSDRAM_DO : std_logic_vector(7 downto 0);
signal XSDRAM_WE : std_logic_vector(0 downto 0);
signal SD_CLK_R : std_logic;
signal SD_DATA : std_logic_vector(6 downto 0);
signal SD_O : std_logic_vector(7 downto 0);
signal VRAM_DO : std_logic_vector(7 downto 0);
signal VRAM_WE : std_logic_vector(0 downto 0);
signal VRAM_VA : std_logic_vector(13 downto 0);
signal VRAM_VD : std_logic_vector(7 downto 0);
signal VRAM_CS : std_logic;
-- FSM States
type STATE_TYPE is ( IDLE, RAMREAD1, RAMWRITE1, RAMWRITE2 );
signal STATE : STATE_TYPE := IDLE;
begin
u_CLOCK : entity work.clock
port map(
CLK_IN => CLK50,
CLK_OUT => CLK );
u_ROM : entity work.rom
port map(
CLKA => CLK,
ADDRA => CPU_A(13 downto 0),
DOUTA => ROM_D );
u_XSDROM : entity work.xsd_rom
port map(
CLKA => CLK,
ADDRA => CPU_A(10 downto 0),
DOUTA => XSDROM_D );
u_XSDRAM : entity work.xsd_ram
port map(
CLKA => CLK,
WEA => XSDRAM_WE,
ADDRA => CPU_A(10 downto 0),
DINA => CPU_DO,
DOUTA => XSDRAM_DO );
u_CPU : k580wm80a
port map(
clk => CLK,
ce => CPU_CLK,
reset => not RESET,
intr => '0',
idata => CPU_DI,
addr => CPU_A,
sync => CPU_SYNC,
rd => CPU_RD,
wr_n => CPU_WR_N,
inta_n => OPEN,
odata => CPU_DO,
inte_o => OPEN );
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => '1',
VRAM_A => VRAM_VA,
VRAM_D => VRAM_VD,
COLORS => COLORS,
R => VGA_R,
G => VGA_G,
B => VGA_B,
HSYNC => VGA_HSYNC,
VSYNC => VGA_VSYNC );
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WE,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => VRAM_DO,
clkb => CLK,
web => "0",
addrb => VRAM_VA,
dinb => "11111111",
doutb => VRAM_VD );
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CONTROL => KEYB_CTRL,
KEYB_A => KEYB_A,
KEYB_D => KEYB_D,
KEYB_A2 => KEYB_A2,
KEYB_D2 => KEYB_D2 );
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_A <= "00" & CPU_A;
SRAM_D <= "ZZZZZZZZ" & SRAM_DI;
SRAM_DO <= SRAM_D(7 downto 0);
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
else
if CPU_SYNC = '1' then
MEM_WR <= '1';
MEM_RD <= '1';
IO_WR <= '1';
IO_RD <= '1';
if CPU_DO(4) = '1' then
IO_WR <= '0';
elsif CPU_DO(6) = '1' then
IO_RD <= '0';
elsif CPU_DO(7) = '1' then
MEM_RD <= '0';
elsif CPU_DO(7) = '0' then
MEM_WR <= '0';
end if;
end if;
end if;
end if;
end process;
CLOCK : process(CLK)
begin
if rising_edge(CLK) then
if KEYB_CTRL(0) = '1' then
TICK <= (others => '0');
RESET <= '0';
else
TICK <= TICK + 1;
CPU_CLK <= '0';
if TICK = "1111" then -- Generate 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
CPU_CLK <= '1';
TICK <= (others => '0');
RESET <= '1';
end if;
end if;
end if;
end process;
FSM : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_DI <= (others => 'Z');
XSD_EN <= '0';
VRAM_WE <= "0";
XSDRAM_WE <= "0";
ROM_INIT <= '1';
else
VRAM_WE <= "0";
XSDRAM_WE <= "0";
case STATE is
when IDLE =>
if TICK = 1 then
if MEM_RD = '0' and CPU_RD = '1' then ------------------------------------------------------------------------- Read from Memory
if CPU_A(15 downto 11) = "11000" and XSD_EN = '1' then
CPU_DI <= XSDRAM_DO;
elsif (CPU_A(15) = '1' and CPU_A(14) = '1') or ROM_INIT = '1' then -- Read from ROM
CPU_DI <= ROM_D;
elsif CPU_A(15 downto 11) = "00000" and XSD_EN = '1' then
CPU_DI <= XSDROM_D;
else -- Read from RAM
if CPU_A(15) = '0' and VRAM_CS = '0' then
CPU_DI <= VRAM_DO;
end if;
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= RAMREAD1;
end if;
elsif MEM_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to Memory
if CPU_A(15) = '0' and VRAM_CS = '0' then
VRAM_WE <= "1";
end if;
if CPU_A(15 downto 11) = "11000" and XSD_EN = '1' then
XSDRAM_WE <= "1";
end if;
SRAM_WE <= '0';
SRAM_CS <= '0';
SRAM_DI <= CPU_DO;
STATE <= RAMWRITE1;
elsif IO_RD = '0' and CPU_RD = '1' then ---------------------------------------------------------------------- Read from I/O-Ports
CPU_DI <= (others => '1');
ROM_INIT <= '0';
if CPU_A(7 downto 0) = X"F1" then
CPU_DI <= SD_O;
-- elsif CPU_A(4) ='0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
-- CPU_DI <= "111" & TAPE_IN & "1111";
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
CPU_DI <= KEYB_D;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
CPU_DI <= KEYB_D2 & KEYB_A2;
end if;
elsif IO_WR = '0' and CPU_WR_N = '0' then ---------------------------------------------------------------------- Write to I/O-Ports
ROM_INIT <= '0';
if CPU_A(7 downto 0) = X"FF" then
XSD_EN <= CPU_DO(1);
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "01" then
COLORS <= CPU_DO(6 downto 0);
elsif CPU_A(4) = '0' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
VRAM_CS <= CPU_DO(1);
SOUND_L <= CPU_DO(0);
SOUND_R <= CPU_DO(0);
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "00" then
KEYB_A <= CPU_DO;
elsif CPU_A(4) = '1' and CPU_A(3) = '0' and CPU_A(1 downto 0) = "10" then
KEYB_A2 <= CPU_DO(3 downto 0);
end if;
end if;
end if;
when RAMREAD1 =>
SRAM_OE <= '1';
SRAM_CS <= '1';
CPU_DI <= SRAM_DO;
STATE <= IDLE;
when RAMWRITE1 =>
SRAM_WE <= '1';
SRAM_CS <= '1';
STATE <= RAMWRITE2;
when RAMWRITE2 =>
SRAM_DI <= (others => 'Z');
STATE <= IDLE;
when OTHERS =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
--//////////////////// SD CARD ////////////////////
SD_O <= SD_DATA & SD_MISO;
SD_SCK <= SD_CLK_R;
process(CLK)
begin
if RESET = '0' then
SD_CS <= '1';
SD_MOSI <= '1';
SD_CLK_R <= '0';
elsif rising_edge(CLK) then
if IO_WR = '0' and CPU_A(7 downto 0) = X"F0" then
SD_CS <= not CPU_DO(0);
elsif IO_WR = '0' and CPU_A(7 downto 0) = X"F1" then
if SD_CLK_R = '1' then
SD_DATA <= SD_DATA(5 downto 0) & SD_MISO;
end if;
SD_MOSI <= CPU_DO(7);
SD_CLK_R <= '0';
end if;
if IO_RD = '0' or MEM_RD = '0' then
SD_CLK_R <= '1';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | cc02373fcf0b2eb10666519826d39517 | 0.383393 | 3.674453 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/reg_file.vhdl | 1 | 2,033 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY reg_file IS
generic
(
BYTES : natural := 1;
WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END reg_file;
ARCHITECTURE vhdl OF reg_file IS
component complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
signal digit_next : reg_file_type;
signal digit_reg : reg_file_type;
signal addr_decoded : std_logic_vector(2**width-1 downto 0);
BEGIN
complete_address_decoder1 : complete_address_decoder
generic map (width => WIDTH)
port map (addr_in => addr, addr_decoded => addr_decoded);
-- next state logic
process(digit_reg,addr_decoded,data_in,WR_EN)
begin
digit_next <= digit_reg;
if (WR_EN = '1') then
comp_gen:
for i in 0 to (BYTES-1) loop
if (addr_decoded(i) = '1') then
digit_next(i) <= data_in;
end if;
end loop;
end if;
end process;
-- register
process(clk)
begin
if (clk'event and clk='1') then
digit_reg <= digit_next;
end if;
end process;
-- output
process(addr_decoded,digit_reg)
begin
data_out <= X"FF";
comp_gen:
for i in 0 to (BYTES-1) loop
if (addr_decoded(i) = '1') then
data_out <= digit_reg(i);
end if;
end loop;
end process;
END vhdl; | gpl-3.0 | d5c3729c5fa001cff077e5db48d1efcb | 0.611904 | 3.075643 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/video/video_changed_for_test_only_chars.vhd | 1 | 8,188 | -- XGA Signal 1024 x 768 @ 60 Hz timing
-- General timing
-- Screen refresh rate 60 Hz
-- Vertical refresh 48.363095238095 kHz
-- Pixel freq. 65.0 MHz
-- Horizontal timing (line)
-- Polarity of horizontal sync pulse is negative.
-- Scanline part Pixels Time [µs]
-- Visible area 1024 15.753846153846
-- Front porch 24 0.36923076923077
-- Sync pulse 136 2.0923076923077
-- Back porch 160 2.4615384615385
-- Whole line 1344 20.676923076923
-- Vertical timing (frame)
-- Polarity of vertical sync pulse is negative.
-- Frame part Lines Time [ms]
-- Visible area 768 15.879876923077
-- Front porch 3 0.062030769230769
-- Sync pulse 6 0.12406153846154
-- Back porch 29 0.59963076923077
-- Whole frame 806 16.6656
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; -- Active buffer
CACHE_A : out std_logic_vector(5 downto 0); -- Cache address
CACHE_D : in std_logic_vector(31 downto 0); -- Cache data
CURRENT_LINE : out std_logic_vector(7 downto 0); -- Current line to read in cache
LUT_A : out std_logic_vector(3 downto 0); -- LUT address
LUT_D : in std_logic_vector(3 downto 0); -- LUT data
VBLANK : out std_logic;
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
constant H_TICKS : natural := 679;
constant V_TICKS : natural := 805;
constant H_SIZE : natural := 512;
constant V_SIZE : natural := 768;
constant HSYNC_B : natural := 531;
constant HSYNC_E : natural := 600;
constant VSYNC_B : natural := 770;
constant VSYNC_E : natural := 800;
------------------------------------------------------------
signal H_COUNTER : unsigned(9 downto 0); -- Horizontal Counter
signal V_COUNTER : unsigned(9 downto 0); -- Vertical Counter
signal THREE_TICK : unsigned(1 downto 0); -- Three Rows Tick
signal SCANLINE : unsigned(7 downto 0); -- Current Scanline for Video Output
signal FLIP_CACHE : std_logic;
signal PAPER : std_logic; -- Paper Area
signal PAPER_L : std_logic; -- Paper zone
signal PAPER_LL : std_logic; -- Paper zone
signal VBLANK_TICK : unsigned(9 downto 0);
signal PIX_R : std_logic_vector(7 downto 0); -- Red byte latch
signal PIX_G : std_logic_vector(7 downto 0); -- Green byte latch
signal PIX_B : std_logic_vector(7 downto 0); -- Blue byte latch
signal PIX_C : std_logic_vector(7 downto 0); -- Char byte latch
type palette_t is array(0 to 15) of std_logic_vector(23 downto 0);
constant color_palette : palette_t := ( "000000000000000000000000", -- 0
"000000000110000000001010", -- 1
"000001100000000010100000", -- 2
"000001100110000010101010", -- 3
"011000000000101000000000", -- 4
"011000000110101000001010", -- 5
"011001100000101010100000", -- 6
"011001100110101010101010", -- 7
"001100110011010101010101", -- 8
"001100111001010101011111", -- 9
"001110010011010111110101", -- 10
"001110011001010111111111", -- 11
"100100110011111101010101", -- 12
"100100111001111101011111", -- 13
"100110010011111111110101", -- 14
"100110011001111111111111");-- 15
begin
CURRENT_LINE <= std_logic_vector(SCANLINE);
CACHE_SWAP <= FLIP_CACHE;
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
H_COUNTER <= (others => '0');
V_COUNTER <= (others => '0');
THREE_TICK <= "00";
SCANLINE <= "00000001";
FLIP_CACHE <= '0';
PAPER <= '0';
HSYNC <= '1';
VSYNC <= '1';
VBLANK <= '0';
VBLANK_TICK <= (others => '0');
else
PAPER <= '0';
HSYNC <= '1';
VSYNC <= '1';
VBLANK <= '0';
FLIP_CACHE <= '0';
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = H_TICKS then
H_COUNTER <= (others => '0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = V_TICKS then
V_COUNTER <= (others => '0');
end if;
VBLANK_TICK <= VBLANK_TICK + 1;
if VBLANK_TICK = 994 then
VBLANK_TICK <= (others => '0');
end if;
end if;
if H_COUNTER < H_SIZE and V_COUNTER < V_SIZE then
PAPER <= '1';
end if;
if H_COUNTER > HSYNC_B and H_COUNTER < HSYNC_E then
HSYNC <= '0';
end if;
if VBLANK_TICK < 6 then
VBLANK <= '1';
end if;
if V_COUNTER > VSYNC_B and V_COUNTER < VSYNC_E then
VSYNC <= '0';
end if;
if H_COUNTER = H_TICKS - 16 and V_COUNTER < V_SIZE then
THREE_TICK <= THREE_TICK + 1;
if THREE_TICK = 2 then
THREE_TICK <= "00";
SCANLINE <= SCANLINE + 1;
FLIP_CACHE <= '1';
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" => CACHE_A <= std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX_C <= CACHE_D(31 downto 24);
PIX_R <= CACHE_D(23 downto 16);
PIX_G <= CACHE_D(15 downto 8);
PIX_B <= CACHE_D(7 downto 0);
PAPER_L <= PAPER;
when others => null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
LUT_A <= PIX_C(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_R(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_G(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_B(7 - to_integer(H_COUNTER(2 downto 0)));
PAPER_LL <= PAPER_L;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
if PAPER_L = '1' then
R <= PIX_C(7 - to_integer(H_COUNTER(2 downto 0))) & "000";
G <= PIX_C(7 - to_integer(H_COUNTER(2 downto 0))) & "000";
B <= PIX_C(7 - to_integer(H_COUNTER(2 downto 0))) & "000";
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 6c60d6ce1df0d2bdf70dc4d36ca3bdd9 | 0.44534 | 4.264063 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_series.vhd | 4 | 12,640 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
| mit | 7507629fa5c2eed331800d9a5224574c | 0.621519 | 2.850056 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04500_good.vhd | 1 | 3,507 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_04500_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Clock reassignment: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_04500_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
-- D Flip-flop 3 stages pipeline
-- D Flip-Flop A
i_DA : in std_logic; -- Input signal
o_QA : out std_logic; -- Output signal
-- D Flip-flop B
o_QB : out std_logic; -- Output signal
-- D Flip-Flop C
o_QC : out std_logic -- Output signal
);
end STD_04500_good;
architecture Behavioral of STD_04500_good is
signal QA : std_logic;
signal QB : std_logic;
begin
-- First Flip-Flop
DFF1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_DA,
o_Q => QA,
o_Q_n => open
);
-- Second Flip-Flop
DFF2 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => QA,
o_Q => QB,
o_Q_n => open
);
-- Third Flip-Flop
DFF3 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => QB,
o_Q => o_QC,
o_Q_n => open
);
o_QA <= QA;
o_QB <= QB;
end Behavioral;
--CODE
| gpl-3.0 | 5872a3fcd6df3772ea639a95d4296168 | 0.453094 | 4.282051 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05600_good.vhd | 1 | 3,378 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05600_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of combinational feedbacks: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity STD_05600_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_A : in std_logic; -- First Mux input
i_B : in std_logic; -- Second Mux input
i_Sel : in std_logic; -- Mux selector
o_O : out std_logic -- Mux output
);
end STD_05600_good;
architecture Behavioral of STD_05600_good is
signal Mux_Sel : std_logic; -- Combinational select
signal Mux_Sel_r : std_logic; -- Synchronized select
signal O : std_logic; -- Module output
begin
Mux_Sel <= i_Sel and O;
-- Synchronizes the Mux_Sel signal to avoid combinational feedback
DFF : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => Mux_Sel,
o_Q => Mux_Sel_r
);
-- Combinational Mux selecting A or B depending on Mux_Sel_r value
Mux1 : Mux
port map (
i_A => i_A,
i_B => i_B,
i_S => Mux_Sel_r,
o_O => O
);
o_O <= O;
end Behavioral;
--CODE
| gpl-3.0 | a222c13e54ca39a422acf4ce1369faa1 | 0.479574 | 4.404172 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb_stim_gen.vhd | 6 | 10,507 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| gpl-2.0 | da9fee94caa9c2fdb2580ee295c13819 | 0.591415 | 3.732504 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/delayLineBRAM/simulation/delayLineBRAM_synth.vhd | 2 | 7,913 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY delayLineBRAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE delayLineBRAM_synth_ARCH OF delayLineBRAM_synth IS
COMPONENT delayLineBRAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 17,
READ_WIDTH => 17 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: delayLineBRAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 | fe907cb433f7dd09c0f1976a278d18f6 | 0.567294 | 3.807988 | false | false | false | false |
APastorG/APG | permutation/perm_sp.vhd | 1 | 2,649 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.counter_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity perm_sp is
generic(
dimensions : positive;
p_dimensions : positive;
serial_dim : natural;
parallel_dim : natural;
left_ps_latency : natural;
right_ps_latency : natural
);
port(
clk : in std_ulogic;
start : in std_ulogic;
input : in sulv_v;
finish : out std_ulogic;
output : out sulv_v
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture perm_sp_1 of perm_sp is
/*================================================================================================*/
/*================================================================================================*/
begin
perm_sp_core:
entity work.perm_sp_core
generic map(
dimensions => dimensions,
p_dimensions => p_dimensions,
serial_dim => serial_dim,
parallel_dim => parallel_dim,
left_ps_latency => left_ps_latency,
right_ps_latency => right_ps_latency,
input_high => input'high,
input_low => input'low
)
port map(
clk => clk,
start => start,
input => input,
finish => finish,
output => output
);
end architecture; | mit | d7ff1b04720b07fae0edc9d93696904c | 0.34608 | 4.869646 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/example_design/mips_vram_prod.vhd | 1 | 10,538 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY mips_vram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END mips_vram_prod;
ARCHITECTURE xilinx OF mips_vram_prod IS
COMPONENT mips_vram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : mips_vram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-3.0 | 5c5a348637e0b9928d6e71e752ad9d27 | 0.4907 | 3.84318 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_noise_filter.vhdl | 1 | 1,346 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_noise_filter IS
PORT
(
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END pokey_noise_filter;
ARCHITECTURE vhdl OF pokey_noise_filter IS
signal pulse_noise_a : std_logic;
signal pulse_noise_b : std_logic;
BEGIN
process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
begin
pulse_noise_a <= noise_large;
pulse_noise_b <= noise_5 and pulse_in;
if (NOISE_SELECT(1) = '1') then
pulse_noise_a <= noise_4;
end if;
if (NOISE_SELECT(2) = '1') then
pulse_noise_b <= pulse_in;
end if;
PULSE_OUT <= pulse_noise_a and pulse_noise_b;
if (NOISE_SELECT(0) = '1') then
PULSE_OUT <= pulse_noise_b;
end if;
end process;
end vhdl; | gpl-3.0 | 4cc1e91408d766348db168ab08aed004 | 0.607727 | 3.159624 | false | false | false | false |
223323/lab2 | HDL/source/coregen/char_rom/char_rom_def.vhd | 1 | 4,440 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file char_rom_def.vhd when simulating
-- the core, char_rom_def. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY char_rom_def IS
port (
addr: IN std_logic_VECTOR(8 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
END char_rom_def;
ARCHITECTURE char_rom_def_a OF char_rom_def IS
-- synthesis translate_off
component wrapped_char_rom_def
port (
addr: IN std_logic_VECTOR(8 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_char_rom_def use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
generic map(
c_sinit_value => "0",
c_has_en => 0,
c_reg_inputs => 0,
c_yclk_is_rising => 1,
c_ysinit_is_high => 1,
c_ywe_is_high => 1,
c_yprimitive_type => "16kx1",
c_ytop_addr => "1024",
c_yhierarchy => "hierarchy1",
c_has_limit_data_pitch => 0,
c_has_rdy => 0,
c_write_mode => 0,
c_width => 8,
c_yuse_single_primitive => 0,
c_has_nd => 0,
c_has_we => 0,
c_enable_rlocs => 0,
c_has_rfd => 0,
c_has_din => 0,
c_ybottom_addr => "0",
c_pipe_stages => 0,
c_yen_is_high => 1,
c_depth => 512,
c_has_default_data => 0,
c_limit_data_pitch => 18,
c_has_sinit => 0,
c_mem_init_file => "char_rom_def.mif",
c_yydisable_warnings => 1,
c_default_data => "0",
c_ymake_bmm => 0,
c_addr_width => 9);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_char_rom_def
port map (
addr => addr,
clk => clk,
dout => dout);
-- synthesis translate_on
END char_rom_def_a;
| mit | 89c9ef604640362e2fac0af677048457 | 0.539189 | 3.974933 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/dmips_med1_tb.vhdl | 1 | 6,644 | ------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Medium connection to the FPGA ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a testbench to simulate the ZPU_Med1 core as used in the ----
---- dmips_med1.vhdl ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: DMIPS_Med1_TB(Behave) (Entity and architecture) ----
---- File name: dmips_med1_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
library work;
use work.zpu_memory.all;
entity DMIPS_Med1_TB is
end entity DMIPS_Med1_TB;
architecture Behave of DMIPS_Med1_TB is
constant WORD_SIZE : natural:=32; -- 32 bits data path
constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant BRATE : positive:=115200;
component ZPU_Med1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='X'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=9600; -- RS232 baudrate
ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
interrupt_i: in std_logic; -- Interrupt
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component ZPU_Med1;
signal clk : std_logic;
signal reset : std_logic:='1';
signal interrupt : std_logic:='0';
signal break : std_logic;
signal dbg : zpu_dbgo_t; -- Debug info
signal rs232_tx : std_logic;
signal rs232_rx : std_logic;
begin
zpu : ZPU_Med1
generic map(
WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, interrupt_i => interrupt, rs232_tx_o => rs232_tx,
rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
gpio_in => (others => '0'));
trace_mod : Trace
generic map(
ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
LOG_FILE => "dmips_med1.log")
port map(
clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_intr:
process
begin
wait for 2 ms;
interrupt <= '1';
wait for 4 us;
interrupt <= '0';
wait for 20 ms;
end process do_intr;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
end architecture Behave; -- Entity: DMIPS_Med1_TB
| bsd-3-clause | 5e040aa5f53224add9c66473d9bd5331 | 0.358669 | 4.659187 | false | false | false | false |
223323/lab2 | HDL/source/tb/vhdl/SRL16.vhd | 1 | 1,590 | -- $Header: $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 12.1
-- \ \ Description : Xilinx Functional Simulation Library Component
-- / / 16-Bit Shift Register Look-Up-Table (Discontinue in 13.1)
-- /___/ /\ Filename : SRL16.vhd
-- \ \ / \ Timestamp : Thu Oct 14 11:06:42 PDT 2010
-- \___\/\___\
--
-- Revision:
-- 10/14/10 - Initial version.
-- 11/28/11 - Change bit attribute to std_logic (CR591750)
-- 01/16/12 - 591750, 586884 - revert change severe IP impact.
-- 08/09/12 - 669069 change retarget from SRLC16E to SRL16E
-- End Revision:
----- CELL SRL16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VPKG.all;
use unisim.VCOMPONENTS.all;
entity SRL16 is
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end SRL16;
architecture SRL16_V of SRL16 is
begin
S0 : SRL16E
generic map(
INIT => INIT
)
port map (
Q => Q,
A0 => A0,
A1 => A1,
A2 => A2,
A3 => A3,
CE => '1',
CLK => CLK,
D => D
);
end SRL16_V;
| mit | 06636545dabc4a05d4c0c741f1c5b29e | 0.454717 | 3.390192 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/simple_counter.vhdl | 1 | 1,628 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
ENTITY simple_counter IS
generic
(
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
);
END simple_counter;
ARCHITECTURE vhdl OF simple_counter IS
signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
value_reg <= (others=>'0');
elsif (clk'event and clk='1') then
value_reg <= value_next;
end if;
end process;
-- next state
process(increment, value_reg, load, load_value)
begin
value_next <= value_reg;
if (increment = '1') then
value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
end if;
if (load = '1') then
value_next <= load_value;
end if;
end process;
-- output
current_value <= value_reg;
END vhdl;
| gpl-3.0 | 85ef0923433b1d1da19e9b1faf5f3e63 | 0.628378 | 3.329243 | false | false | false | false |
freecores/lq057q3dc02 | design/dcm_sys_to_lcd.vhd | 1 | 3,179 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.2.04i
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm_sys_to_lcd.vhd
-- /___/ /\ Timestamp : 11/06/2008 18:34:59
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle -synthesis dcm_sys_to_lcd.xaw
--Design Name: dcm_sys_to_lcd
--Device: xc2vp30-7ff896
--
-- Module dcm_sys_to_lcd
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_INST = 0.02 UI
-- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.85 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm_sys_to_lcd is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end dcm_sys_to_lcd;
architecture BEHAVIORAL of dcm_sys_to_lcd is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 8.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => TRUE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => TRUE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>CLKDV_BUF,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-2.0 | 89782060a9649be757ccd4d24b2428ad | 0.468701 | 3.705128 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/shared_enable.vhdl | 1 | 4,664 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.ceil;
USE ieee.math_real.log2;
-- TODO - review this whole scheme
-- Massively overcomplex and turbo doesn't even work with it right now!
ENTITY shared_enable IS
GENERIC
(
cycle_length : integer := 16 -- or 32...
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ANTIC_REFRESH : IN STD_LOGIC;
MEMORY_READY_CPU : IN STD_LOGIC; -- during memory wait states keep CPU awake
MEMORY_READY_ANTIC : IN STD_LOGIC; -- during memory wait states keep CPU awake
PAUSE_6502 : in std_logic;
THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
ANTIC_ENABLE_179 : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle early
oldcpu_enable : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle only, when memory is ready...
CPU_ENABLE_OUT : OUT STD_LOGIC -- for compatibility run at 1.79MHz, for speed run as fast as we can
-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by cycle_length-1 cycles vs CPU_ENABLE (when in 1.79MHz mode)
);
END shared_enable;
ARCHITECTURE vhdl OF shared_enable IS
component enable_divider IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
signal enable_179 : std_logic;
signal enable_179_early : std_logic;
signal cpu_enable : std_logic;
signal cpu_extra_enable_next : std_logic;
signal cpu_extra_enable_reg : std_logic;
signal speed_shift_next : std_logic_vector(cycle_length-1 downto 0);
signal speed_shift_reg : std_logic_vector(cycle_length-1 downto 0);
-- TODO - clean up
signal oldcpu_pending_next : std_logic;
signal oldcpu_pending_reg : std_logic;
signal oldcpu_go : std_logic;
signal memory_ready : std_logic;
constant cycle_length_bits: integer := integer(ceil(log2(real(cycle_length))));
begin
-- instantiate some clock calcs
enable_179_clock_div : enable_divider
generic map (COUNT=>cycle_length)
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
process(THROTTLE_COUNT_6502, speed_shift_reg, enable_179)
variable speed_shift : std_logic;
variable speed_shift_temp : std_logic_vector(cycle_length-1 downto 0);
begin
if (enable_179 = '1') then -- synchronize
speed_shift_temp(cycle_length-1 downto 1) := (others=>'0');
speed_shift_temp(0) := '1';
else
speed_shift_temp := speed_shift_reg;
end if;
speed_shift_next(cycle_length-1 downto 1) <= speed_shift_temp(cycle_length-2 downto 0);
speed_shift := '0';
for i in 0 to cycle_length_bits loop
speed_shift := speed_shift or (speed_shift_temp(cycle_length/(2**i)-1) and throttle_count_6502(i));
end loop;
speed_shift_next(0) <= speed_shift;
end process;
delay_line_phase : delay_line
generic map (COUNT=>cycle_length-1)
port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);
-- registers
process(clk,reset_n)
begin
if (reset_n = '0') then
cpu_extra_enable_reg <= '0';
oldcpu_pending_reg <= '0';
speed_shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
cpu_extra_enable_reg <= cpu_extra_enable_next;
oldcpu_pending_reg <= oldcpu_pending_next;
speed_shift_reg <= speed_shift_next;
end if;
end process;
-- next state
memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
cpu_enable <= (speed_shift_reg(0) or cpu_extra_enable_reg or enable_179) and not(pause_6502 or antic_refresh);
cpu_extra_enable_next <= cpu_enable and not(memory_ready);
oldcpu_pending_next <= (oldcpu_pending_reg or enable_179) and not(memory_ready or antic_refresh);
oldcpu_go <= (oldcpu_pending_reg or enable_179) and (memory_ready or antic_refresh);
-- output
oldcpu_enable <= oldcpu_go;
ANTIC_ENABLE_179 <= enable_179_early;
CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
end vhdl;
| gpl-3.0 | c5c4312df3880c33bef5905d9a2e254d | 0.667667 | 3.082617 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/sim_tb/vhdl/sin_taylor_series.autotb.vhd | 2 | 39,230 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_sin_taylor_series_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_x : STRING := "./c.sin_taylor_series.autotvin_x.dat";
AUTOTB_TVIN_x_out_wrapc : STRING := "./rtl.sin_taylor_series.autotvin_x.dat";
AUTOTB_TVOUT_ap_return : STRING := "./c.sin_taylor_series.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "sin_taylor_series.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "sin_taylor_series.performance.result.transaction.xml";
LENGTH_x : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 19
);
end apatb_sin_taylor_series_top;
architecture behav of apatb_sin_taylor_series_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal x : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal ap_clk : STD_LOGIC;
signal ap_rst : STD_LOGIC;
signal ap_return : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal ap_done : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC);
end component;
-- The signal of port x
shared variable AESL_REG_x : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
function esl_equal_std_lv (lv1 : STD_LOGIC_VECTOR; lv2 : STD_LOGIC_VECTOR) return BOOLEAN is
variable len : INTEGER;
variable i : INTEGER;
begin
if (lv1'length > lv2'length) then
len := lv2'length;
for i in lv1'length - 1 downto lv2'length loop
if(lv1(i) = '1') then
return false;
end if;
end loop;
else
len := lv1'length;
for i in lv2'length - 1 downto lv1'length loop
if(lv2(i) = '1') then
return false;
end if;
end loop;
end if;
for i in len - 1 downto 0 loop
if (lv1(i) = '1' and lv2(i) /= '1') or (lv1(i) = '0' and lv2(i) /= '0') then
return false;
end if;
end loop;
return true;
end function;
procedure post_check (file fp1 : TEXT; file fp2 : TEXT) is
variable token_line1 : LINE;
variable token_line2 : LINE;
variable token1 : STRING(1 to 152);
variable token2 : STRING(1 to 152);
variable golden : STD_LOGIC_VECTOR(151 downto 0);
variable result : STD_LOGIC_VECTOR(151 downto 0);
variable l1 : INTEGER;
variable l2 : INTEGER;
begin
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
if(token1(1 to 13) /= "[[[runtime]]]" or token2(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
while(token1(1 to 14) /= "[[[/runtime]]]" and token2(1 to 14) /= "[[[/runtime]]]") loop
if(token1(1 to 15) /= "[[transaction]]" and token2(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1); -- Skip transaction number
esl_read_token(fp2, token_line2, token2); -- Skip transaction number
esl_read_token(fp1, token_line1, token1, l1);
esl_read_token(fp2, token_line2, token2, l2);
while(token1(1 to 16) /= "[[/transaction]]" and token2(1 to 16) /= "[[/transaction]]") loop
golden := esl_str2lv_hex(token1, 152 );
result := esl_str2lv_hex(token2, 152 );
if(esl_equal_std_lv(golden, result) = false) then
report token1(1 to l1) & " (expected) vs. " & token2(1 to l2) & " (actual) - mismatch";
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
end procedure post_check;
begin
AESL_inst_sin_taylor_series : sin_taylor_series port map (
x => x,
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_return => ap_return,
ap_done => ap_done,
ap_start => ap_start,
ap_ready => ap_ready,
ap_idle => ap_idle
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst <= AESL_reset;
AESL_reset <= rst;
AESL_done <= ap_done;
ap_start <= AESL_start;
AESL_start <= start;
AESL_ready <= ap_ready;
AESL_idle <= ap_idle;
AESL_ce <= ce;
AESL_continue <= continue;
gen_check_strlSignal_AESL_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
NULL;
else
if ( AESL_done /= '1' and AESL_done /= '0' ) then
assert false report "Control signal AESL_done is invalid!" severity failure;
end if;
end if;
end if;
end process;
gen_check_strlSignal_AESL_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
NULL;
else
if ( AESL_ready /= '1' and AESL_ready /= '0' ) then
assert false report "Control signal AESL_ready is invalid!" severity failure;
end if;
end if;
end if;
end process;
gen_assign_x_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
x <= AESL_REG_x;
end process;
read_file_process_x : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 152);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable transaction_idx : INTEGER:= 0;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_x, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_x & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_x := esl_str2lv_hex(token, 64 );
esl_read_token(fp, token_line, token);
end if;
wait until AESL_clock'event and AESL_clock = '1';
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
write_file_process_ap_return : process
file fp : TEXT;
file fp_size : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 152);
variable str : STRING(1 to 40);
variable transaction_idx : INTEGER;
variable ap_return_count : INTEGER;
variable hls_stream_size : INTEGER;
variable i : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
transaction_idx := 0;
while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(ap_return));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '1') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
file fp1 : TEXT;
file fp2 : TEXT;
variable fstatus1 : FILE_OPEN_STATUS;
variable fstatus2 : FILE_OPEN_STATUS;
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus1, fp1, "./rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE);
file_open(fstatus2, fp2, "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE);
if(fstatus1 /= OPEN_OK) then
assert false report string'("Open file rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note;
elsif(fstatus2 /= OPEN_OK) then
assert false report string'("Open file impl_rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note;
else
report string'("Comparing rtl.sin_taylor_series.autotvout_ap_return.dat with impl_rtl.sin_taylor_series.autotvout_ap_return.dat");
post_check(fp1, fp2);
end if;
file_close(fp1);
file_close(fp2);
report "Simulation Passed.";
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '1';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '0';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '0';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '1') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
elsif (reported_stuck = '0' and reported_stuck_cnt < 4) then
if ( AESL_mLatCnterIn_addr > AESL_mLatCnterOut_addr ) then
if ( AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10000 and AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10 * 1156 ) then
report "WARNING: The latency is much larger than expected. Simulation may stuck.";
reported_stuck <= '1';
reported_stuck_cnt := reported_stuck_cnt + 1;
end if;
end if;
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
elsif (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '0');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
| mit | 70d3198dbfa0940bd1a241299b636601 | 0.512032 | 3.707239 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/char_rom.vhd | 1 | 3,624 | -----------------------------------------------------------------------------------
-- Odsek za racunarsku tehniku i medjuracunarske komunikacije --
-- Copyright © 2009 All Rights Reserved --
-- --
-- Projekat: LabVezba2 --
-- Ime modula: char_rom.vhd --
-- Autori: LPRS2 TIM 2009/2010 <[email protected]> --
-- --
-- Opis: --
-- Char_rom generise tekst na ekranu. --
-- Znak se predstavlja matricom 8x8 tacaka. --
-- Oblici znakova se nalaze u datoteci char_rom_def_mem.coe --
-- --
-----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY char_rom IS PORT (
clk_i : IN STD_LOGIC; -- takt SIGNAL
character_address_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- adresa karaktera
font_row_i : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- ispis reda
font_col_i : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- ispis kolone
rom_mux_output_o : OUT STD_LOGIC -- izlazni SIGNAL iz char_rom-a
);
END char_rom;
ARCHITECTURE Behavioral OF char_rom IS
SIGNAL rom_data : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); -- prosledjuje izlaz iz char_rom-a na ulaz u VGA
SIGNAL rom_address : STD_LOGIC_VECTOR( 8 DOWNTO 0 ); -- preuzima character_address_i i font_row_i
COMPONENT char_rom_def IS PORT (
clk : IN STD_LOGIC; -- takt
addr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); -- adresa znaka
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- izlaz
);
END COMPONENT;
BEGIN
-- Oblici znakova se nalaze u datoteci char_rom_def_mem.coe
BRAM_MEM_I: char_rom_def PORT MAP (
clk => clk_i ,
addr => rom_address,
dout => rom_data
);
------------------|----------
-- ADDRESS | OFFSET |
------------------|----------
rom_address <= character_address_i & font_row_i;
PROCESS(font_col_i, rom_data) BEGIN
CASE(font_col_i) IS
WHEN "000" => rom_mux_output_o <= rom_data(7);
WHEN "001" => rom_mux_output_o <= rom_data(6);
WHEN "010" => rom_mux_output_o <= rom_data(5);
WHEN "011" => rom_mux_output_o <= rom_data(4);
WHEN "100" => rom_mux_output_o <= rom_data(3);
WHEN "101" => rom_mux_output_o <= rom_data(2);
WHEN "110" => rom_mux_output_o <= rom_data(1);
WHEN "111" => rom_mux_output_o <= rom_data(0);
WHEN OTHERS => rom_mux_output_o <= '0';
END CASE;
END PROCESS;
END Behavioral;
| mit | c55255e11a37366555701a9e9876140a | 0.377759 | 4.293839 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriesfYi.vhd | 4 | 3,087 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_seriesfYi is
generic (
ID : integer := 12;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_seriesfYi is
--------------------- Component ---------------------
component sin_taylor_series_ap_dsub_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_dsub_3_full_dsp_64_u : component sin_taylor_series_ap_dsub_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 6f3ef9229d501dbe75f489f75897d3e7 | 0.48105 | 3.675 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/bios/bios.vhd | 1 | 5,479 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bios.vhd when simulating
-- the core, bios. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bios IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END bios;
ARCHITECTURE bios_a OF bios IS
-- synthesis translate_off
COMPONENT wrapped_bios
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bios USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "bios.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 8192,
c_read_depth_b => 8192,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 8192,
c_write_depth_b => 8192,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bios
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END bios_a;
| gpl-3.0 | 9a35adfe69c276897444c40b7577cf2f | 0.513232 | 3.941727 | false | false | false | false |
APastorG/APG | counter/counter_pkg.vhd | 1 | 11,431 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains necessary types, constants, and functions for the parameterized counter
/ design.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package counter_pkg is
/* types and related functions 1 */
/**************************************************************************************************/
type T_count_mode is (t_up, t_down, t_input_signal);
type T_overflow_behavior is (t_saturate, t_wrap);
type T_target_count_behavior is (t_blocking, t_non_blocking);
type T_set_reset_priority is (t_set, t_reset);
function ite(
cond : boolean;
if_true, if_false : T_count_mode)
return T_count_mode;
function ite(
cond : boolean;
if_true, if_false : T_overflow_behavior)
return T_overflow_behavior;
function ite(
cond : boolean;
if_true, if_false : T_target_count_behavior)
return T_target_count_behavior;
function ite(
cond : boolean;
if_true, if_false : T_set_reset_priority)
return T_set_reset_priority;
/* function to check the consistency and correctness of generics 2 */
/**************************************************************************************************/
function counter_CHECKS (
unsigned_2comp_opt, target_mode, use_set, use_reset, use_load: boolean;
target_blocking_opt : boolean_exc;
target_dep, set_to_dep: integer_exc;
counter_width_dep: positive_exc)
return natural;
/* functions for corrected generics and internal/external port signals 3 */
/**************************************************************************************************/
function counter_MWCG(
unsigned_2comp_opt : boolean;
target_dep : integer_exc;
use_set : boolean;
set_to_dep : integer_exc)
return positive;
function counter_CIW(
unsigned_2comp_opt : boolean;
counter_width_dep : positive_exc;
target_mode : boolean;
target_dep : integer_exc;
use_set : boolean;
set_to_dep : integer_exc)
return positive;
function counter_CW(
unsigned_2comp_opt : boolean;
counter_width_dep : positive_exc;
target_mode : boolean;
target_dep : integer_exc;
target_with_count : boolean;
use_set : boolean;
set_to_dep : integer_exc)
return natural;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package body counter_pkg is
/********************************************************************************************** 1 */
function ite(
cond : boolean;
if_true, if_false : T_count_mode)
return T_count_mode is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(
cond : boolean;
if_true, if_false : T_overflow_behavior)
return T_overflow_behavior is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(
cond : boolean;
if_true, if_false : T_target_count_behavior)
return T_target_count_behavior is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(
cond : boolean;
if_true, if_false : T_set_reset_priority)
return T_set_reset_priority is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
/********************************************************************************************** 2 */
function counter_CHECKS (
unsigned_2comp_opt, target_mode, use_set, use_reset, use_load: boolean;
target_blocking_opt : boolean_exc;
target_dep, set_to_dep: integer_exc;
counter_width_dep: positive_exc)
return natural is
constant target : integer := integer(target_dep);
constant set_to : integer := integer(set_to_dep);
constant counter_width : integer := integer(counter_width_dep);
variable target_min_bits : positive;
variable set_to_min_bits : positive;
variable counter_w : natural;
begin
--error: target mode but target not set
assert not(target_mode and target=integer'low)
report "(1) " &
"ILLEGAL PARAMETERS in entity counter: in target mode (target_MODE=true) the parameter " &
"target_dep must be assigned a value."
severity error;
--error: negative target in an unsigned counter
assert not (target_mode and unsigned_2comp_opt and target<0)
report "(2) " &
"ILLEGAL PARAMETERS in entity counter: cannot have a negative number as the target " &
"in an unsigned counter. Generic UNSIGNED_2COMP should be false."
severity error;
--error: negative set_to in an unsigned counter
assert not (unsigned_2comp_opt and use_set and set_to<0)
report "(3) " &
"ILLEGAL PARAMETERS in entity counter: cannot have a negative number as the value" &
" to set the counter to when set='1'. Generic UNSIGNED_2COMP should be false."
severity error;
counter_w := counter_CIW(unsigned_2comp_opt,
counter_width_dep,
target_mode,
target_dep,
use_set,
set_to_dep);
--error: COUNTER_WIDTH is not set when in normal mode
assert not(not target_mode and counter_width=0)
report "(4) " &
"MISSING PARAMETERS in entity counter: when in normal mode (target_MODE = false) " &
"the value of the generic COUNTER_WIDTH must be set."
severity error;
--error: SET_TO_dep is not set when USE_SET is true
assert not(use_set and set_to=integer'low)
report "(5) " &
"MISSING PARAMETERS in entity counter: when using set (USE_SET = true) " &
"the value of the generic SET_TO_dep must be set."
severity error;
if target_mode then
target_min_bits:= min_bits(target, not unsigned_2comp_opt);
else
target_min_bits := 1;
end if;
--error: the width of the counter is not enough for target
assert not(target_mode and counter_w<target_min_bits)
report "(6) " &
"ILLEGAL PARAMETERS in entity counter: the specified counter width (" &
image(counter_w) & ") is not enough for the stated target (" &
image(target_dep) & "). At least " & image(target_min_bits) &
" bits are necessary."
severity error;
if use_set then
set_to_min_bits := min_bits(set_to, not unsigned_2comp_opt);
else
set_to_min_bits := 1;
end if;
--error: the width of the counter is not enough for set_to
assert not(use_set and counter_w<set_to_min_bits)
report "(7) " &
"ILLEGAL PARAMETERS in entity counter: the specified counter width (" &
image(counter_w) & ") is not enough for the stated set_to (" &
image(set_to) & "). At least " & image(set_to_min_bits) &
" bits are necessary."
severity error;
--warning: target blocking but neither set, reset, nor load (permanent block)
assert not(target_mode and target_blocking_opt=t_true and
not(use_set or use_reset or use_load))
report "(11) " &
"With the specified parameters, the counter module will reach a permanent block "&
"once it reaches the target"
severity warning;
return 0;
end function;
/********************************************************************************************** 3 */
function counter_MWCG(
unsigned_2comp_opt : boolean;
target_dep : integer_exc;
use_set : boolean;
set_to_dep : integer_exc)
return positive is
begin
if use_set then
return maximum(min_bits(target_dep, not unsigned_2comp_opt),
min_bits(set_to_dep, not unsigned_2comp_opt));
else
return min_bits(target_dep, not unsigned_2comp_opt);
end if;
end function;
function counter_CIW(
unsigned_2comp_opt : boolean;
counter_width_dep : positive_exc;
target_mode : boolean;
target_dep : integer_exc;
use_set : boolean;
set_to_dep : integer_exc)
return positive is
begin
if target_mode then
if counter_width_dep = 0 then
return counter_MWCG(unsigned_2comp_opt,
target_dep,
use_set,
set_to_dep);
else
return positive(counter_width_dep);
end if;
else
return positive(counter_width_dep);
end if;
end function;
function counter_CW(
unsigned_2comp_opt : boolean;
counter_width_dep : positive_exc;
target_mode : boolean;
target_dep : integer_exc;
target_with_count : boolean;
use_set : boolean;
set_to_dep : integer_exc)
return natural is
begin
if target_mode then
if target_with_count then
if counter_width_dep = 0 then
return counter_MWCG(unsigned_2comp_opt,
target_dep,
use_set,
set_to_dep);
else
return natural(counter_width_dep);
end if;
else
return 0;
end if;
else
return natural(counter_width_dep);
end if;
end function;
end package body;
| mit | fda8e084591a3dc1aa2cccbdb5fb26ca | 0.491182 | 4.478193 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_countdown_timer.vhdl | 1 | 2,555 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END pokey_countdown_timer;
ARCHITECTURE vhdl OF pokey_countdown_timer IS
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
signal count_reg : std_logic_vector(7 downto 0);
signal count_next: std_logic_vector(7 downto 0);
signal underflow : std_logic;
signal count_command : std_logic_vector(1 downto 0);
signal underflow_command: std_logic_vector(1 downto 0);
BEGIN
-- Instantiate delay (provides output)
underflow0_delay : delay_line
generic map (COUNT=>UNDERFLOW_DELAY)
port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
count_reg <= (others=>'0');
elsif (clk'event and clk='1') then
count_reg <= count_next;
end if;
end process;
-- count down on enable
process(count_reg,enable,wr_en,count_command,data_in)
begin
count_command <= enable&wr_en;
case count_command is
when "10" =>
count_next <= std_logic_vector(unsigned(count_reg) -1);
when "01"|"11" =>
count_next <= data_in;
when others =>
count_next <= count_reg;
end case;
end process;
-- underflow
process(count_reg,enable,underflow_command)
begin
underflow_command <= enable & To_Std_Logic(count_reg = X"00");
case underflow_command is
when "11" =>
underflow <= '1';
when others =>
underflow <= '0';
end case;
end process;
END vhdl;
| gpl-3.0 | 8c77e8e959fbf2a24fccd87d564da5c2 | 0.637182 | 3.123472 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/memctrl/memctrl.vhd | 1 | 3,854 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memctrl is
Port (
CLK : in std_logic;
RESET : in std_logic;
MEM_A : in std_logic_vector(19 downto 0);
MEM_DI : in std_logic_vector(7 downto 0);
MEM_DO : out std_logic_vector(7 downto 0);
MEM_RW : in std_logic;
MEM_REQ : in std_logic;
MEM_ACK : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
SRAM_OE : out std_logic;
SRAM_WE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic );
end memctrl;
architecture Behavioral of memctrl is
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
-- STATEMACHINE
type STATE_TYPE is (IDLE, READ1, WRITE1, WRITE2, DONE);
signal STATE : STATE_TYPE := IDLE;
begin
SRAM_D <= SRAM_DI;
SRAM_DO <= SRAM_D;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
SRAM_A <= (others=>'0');
SRAM_DI <= (others=>'Z');
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
SRAM_WE <= '1';
SRAM_UB <= '1';
SRAM_LB <= '1';
MEM_DO <= "11111111";
MEM_ACK <= '0';
else
MEM_ACK <= '0';
case STATE is
when IDLE =>
if MEM_REQ = '1' then
SRAM_A <= MEM_A(18 downto 1);
if MEM_A(19) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if MEM_A(0) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
if MEM_RW = '0' then
SRAM_OE <= '0';
STATE <= READ1;
else
SRAM_DI <= MEM_DI & MEM_DI;
SRAM_WE <= '0';
STATE <= WRITE1;
end if;
end if;
when READ1 =>
if MEM_A(0) = '0' then
MEM_DO <= SRAM_DO(7 downto 0);
else
MEM_DO <= SRAM_DO(15 downto 8);
end if;
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
MEM_ACK <= '1';
STATE <= DONE;
when WRITE1 =>
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_WE <= '1';
STATE <= WRITE2;
when WRITE2 =>
SRAM_DI <= (others=>'Z');
MEM_ACK <= '1';
STATE <= DONE;
when DONE =>
STATE <= IDLE;
when others =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | b7dce1bd6521aaf9078066d136d8fedc | 0.331085 | 4.424799 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/gmzpu_tb.vhdl | 1 | 6,219 | ------------------------------------------------------------------------------
---- ----
---- gmZPU testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core. ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: gmZPU_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
library work;
use work.zpu_memory.all;
entity gmZPU_TB is
end entity gmZPU_TB;
architecture Behave of gmZPU_TB is
constant WORD_SIZE : natural:=32; -- 32 bits data path
constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant BRATE : positive:=115200;
component gmZPU is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='X'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=9600; -- RS232 baudrate
ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
interrupt_i: in std_logic; -- Interrupt
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component gmZPU;
signal clk : std_logic;
signal reset : std_logic:='1';
signal interrupt : std_logic:='0';
signal break : std_logic;
signal dbg : zpu_dbgo_t; -- Debug info
signal rs232_tx : std_logic;
signal rs232_rx : std_logic;
begin
soc : gmZPU
generic map(
WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, interrupt_i => interrupt, rs232_tx_o => rs232_tx,
rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
gpio_in => (others => '0'));
trace_mod : Trace
generic map(
ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
LOG_FILE => "dmips_med1.log")
port map(
clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_intr:
process
begin
wait for 2 ms;
interrupt <= '1';
wait for 4 us;
interrupt <= '0';
wait for 5 ms;
end process do_intr;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
end architecture Behave; -- Entity: gmZPU_TB
| bsd-3-clause | 0302bec87d35b3fd5612e6f61db9bdd1 | 0.362277 | 4.672427 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/alf/src/keyboard/keyboard.vhd | 1 | 2,771 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_DATA : out std_logic_vector(4 downto 0);
RESET_TICK : out std_logic);
end keyboard;
architecture rtl of keyboard is
signal CODE : std_logic_vector(7 downto 0); -- Scancode recieved from keyboard
signal DONE : std_logic; -- Current scancode valid
signal ERROR : std_logic; -- Current scancode corrupted
signal RELEASED_KEY : std_logic;
signal EXTENDED_KEY : std_logic;
signal KEYB_DATA_TEMP : std_logic_vector(4 downto 0);
begin
keyb_data <= KEYB_DATA_TEMP;
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
main : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
RESET_TICK <= '0';
KEYB_DATA_TEMP <= "00000";
else
RESET_TICK <= '0';
if ERROR = '1' then
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
elsif DONE = '1' then
if CODE = X"F0" then
RELEASED_KEY <= '1';
elsif CODE = X"E0" then
EXTENDED_KEY <= '1';
elsif CODE = X"07" and RELEASED_KEY = '1' then
RESET_TICK <= '1';
else
if EXTENDED_KEY = '1' then
if CODE = X"75" then
KEYB_DATA_TEMP(3) <= not RELEASED_KEY; -- up
elsif CODE = X"72" then
KEYB_DATA_TEMP(2) <= not RELEASED_KEY; -- down
elsif CODE = X"6B" then
KEYB_DATA_TEMP(1) <= not RELEASED_KEY; -- left
elsif CODE = X"74" then
KEYB_DATA_TEMP(0) <= not RELEASED_KEY; -- right
end if;
else
if CODE = X"29" or CODE = X"5A" then
KEYB_DATA_TEMP(4) <= not RELEASED_KEY; -- space/enter for fire
end if;
end if;
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
end if;
end if;
end if;
end if;
end process;
end; | gpl-3.0 | 82f916a0ddd3e9bef784514eb23d0b17 | 0.425839 | 3.924929 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/SPISlave.vhd | 1 | 1,531 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:21:33 05/14/2015
-- Design Name:
-- Module Name: SPISlave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity SPISlave is
port(
sck : in std_logic := '0';
mosi : in std_logic;
miso : out std_logic := 'Z';
ssel : in std_logic;
in_data : in std_logic_vector(7 downto 0);
out_data : out std_logic_vector(7 downto 0)
);
end SPISlave;
architecture Behavioral of SPISlave is
signal first: boolean := true;
signal reg: std_logic_vector(6 downto 0) := (others => '0');
signal mosi_cache: std_logic := '0';
begin
process(sck, ssel, reg, mosi_cache, in_data) begin
if (rising_edge(ssel)) then
out_data <= reg(6 downto 0) & mosi_cache;
end if;
if (ssel = '1') then
first <= true;
miso <= 'Z';
else
if (rising_edge(sck)) then
mosi_cache <= mosi;
end if;
if (falling_edge(sck)) then
if (first) then
first <= false;
miso <= in_data(7);
reg <= in_data(6 downto 0);
else
miso <= reg(6);
reg <= reg(5 downto 0) & mosi_cache;
end if;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | 2fbaf55c5a6af008364ab7de88c0bb5c | 0.559765 | 3.086694 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05700_bad.vhd | 1 | 3,512 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05700_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of gated clocks: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_05700_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_Data : in std_logic; -- Input data
o_Data : out std_logic; -- Output data
o_Gated_Clock : out std_logic -- Gated clock
);
end STD_05700_bad;
architecture Behavioral of STD_05700_bad is
signal Enable_r : std_logic;
signal Gated_Clock : std_logic;
signal Data_r : std_logic; -- Data signal registered
signal Data_r2 : std_logic; -- Data signal registered twice
begin
DFF_En : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_Enable,
o_Q => Enable_r,
o_Q_n => open
);
-- Make the Flip-Flop work when Enable signal is at 1
-- Enable signal on clock path
Gated_Clock <= i_Clock and Enable_r;
P_Sync_Data : process(i_Reset_n, Gated_Clock)
begin
if (i_Reset_n = '0') then
Data_r <= '0';
Data_r2 <= '0';
elsif (rising_edge(Gated_Clock)) then
Data_r <= i_Data;
Data_r2 <= Data_r;
end if;
end process;
o_Data <= Data_r2;
end Behavioral;
--CODE
| gpl-3.0 | 2fc860feefb93838501c4bd1f1d61c3a | 0.487472 | 4.251816 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/oneshot/oneshot.vhd | 1 | 1,959 | -- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity oneshot is
generic (SIZE : positive := 12);
port(
CLK : in std_logic;
RESET : in std_logic;
ONESHOT_IN : in std_logic;
ONESHOT_OUT : out std_logic );
end oneshot;
architecture rtl of oneshot is
signal COUNTER : unsigned(SIZE-1 downto 0);
signal ONES : unsigned(SIZE-1 downto 0);
signal LOCK : std_logic;
begin
ONES <= (others=>'1');
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
LOCK <= '0';
COUNTER <= (others=>'0');
else
if ONESHOT_IN = '1' then
LOCK <= '1';
end if;
if LOCK = '1' then
if COUNTER /= ONES then
COUNTER <= COUNTER + 1;
else
LOCK <= '0';
COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
ONESHOT_OUT <= LOCK;
end rtl;
| gpl-3.0 | ecb3eb51aeb0db7abbae0b0f7d2ce793 | 0.257785 | 3.818713 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriescud.vhd | 4 | 2,551 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_seriescud is
generic (
ID : integer := 5;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_seriescud is
--------------------- Component ---------------------
component sin_taylor_series_ap_sitodp_4_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_sitodp_4_no_dsp_32_u : component sin_taylor_series_ap_sitodp_4_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
end if;
end if;
end process;
end architecture;
| mit | e96149a2f93ef960d210976ea540b991 | 0.470404 | 3.841867 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_core_s.vhd | 1 | 7,788 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_core_s is
generic(
DATA_IMM_AFTER_START_opt : boolean;
SPEED_opt : T_speed;
ROUND_STYLE_opt : T_round_style;
ROUND_TO_BIT_opt : integer_exc;
MAX_ERROR_PCT_opt : real_exc;
S : positive;
P : positive;
input_high : integer;
input_low : integer
);
port(
input : in u_sfixed_v(1 to P);
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed(average_calculator_OH(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
downto
average_calculator_OL(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_core_s1 of average_calculator_core_s is
constant INTER_HIGH : integer := average_calculator_IH(S,
P,
input_high);
constant INTER_LOW : integer := average_calculator_IL(ROUND_TO_BIT_opt,
input_low);
constant OUT_HIGH : integer := average_calculator_OH(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
constant OUT_LOW : integer := average_calculator_OL(false, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
signal inter : u_sfixed(INTER_HIGH downto INTER_LOW);
signal valid_output_inter : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
check_if_1:
if P = 1 generate
begin
output <= input(1);
valid_output <= valid_input; --need update when implementing pipelines
end;
else generate
begin
adder_s1:
entity work.adder_s
generic map(
--DATA_IMM_AFTER_START_opt => ,
--SPEED_opt => , --to do
--MAX_POSSIBLE_BIT_opt => ,
TRUNCATE_TO_BIT_opt => ROUND_TO_BIT_opt,
S => S
)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => inter,
valid_output => valid_output_inter
);
real_const_mult_s1:
entity work.real_const_mult_s
generic map(
--SPEED_opt => SPEED_opt, --to do
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => (1 => 1.0/(S*P))
)
port map(
input => inter,
clk => clk,
valid_input => valid_output_inter,
output(1) => output,
valid_output => valid_output
);
end;
end generate;
end architecture; | mit | efb363acdef6558e3a5ca95faf0bef61 | 0.360975 | 5.441404 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06500_bad.vhd | 1 | 3,430 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06500_bad.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Counters end of counting: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06500_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06500_bad;
--CODE
architecture Behavioral of STD_06500_bad is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count = Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
| gpl-3.0 | 968b30c0285fd47dfb2917e6ef5906b3 | 0.508746 | 4.513158 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_u.vhd | 1 | 4,557 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_u is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_ufixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_u1 of average_calculator_u is
constant P : positive := input'length;
/* constant CHECKS : integer := average_calculator_CHECKS();*/
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_core_u1:
entity work.average_calculator_core_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; | mit | 44b24adf67739b1072471c63993db9eb | 0.454566 | 4.577935 | false | false | false | false |
freecores/lq057q3dc02 | design/lq057q3dc02_top.vhd | 1 | 14,821 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: lq057q3dc02_top.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- Top level file for the lq057q3dc02 pcore. The lq057q3dc02 supports QVGA
-- (320x240) mode only!
--
-- LCD Handling Cautions: You should make sure that you always power off the
-- LCD before turning on the FPGA controller board with the control cable
-- connected.
--
-- One useful piece of info for this 320x240x18bpp screen is that the
-- largest amount of image data it can support with all color bits used
-- is 1,382,400 bits = 172,800 bytes. The Virtex-II Pro has enough BRAM
-- space to support 306KB = 313,344 bytes. So you could not possible
-- fill up the BRAM with a single image.
--
-- NOTE! You can EASILY mistake success for failure when viewing a test
-- image because the resolution of this LCD is soooooo low. Be sure to look
-- VERY carefully at the test image before you assume your algorithms are
-- incorrect!
--
-- Important Terms:
-- 1 Pixel = 1 [RGB] element on the screen
-- BPP = Bits/Pixel = "Color Depth" = "Bit Depth"
-- BPP/3colors_per_pixel = #BPC = #Bits Per Color
-- 2 color = 1 bpp
-- 16 color = 4 bpp
-- 256 color = 8 bpp
-- 262,144 color = 18 bpp = 6 bpc = this is the same as the lq057q3dc02
-- 16.7 million color (True Color) = 24 bpp
-- A bitmap file that has anything lower than true color stores it's image
-- data as look-up locations to a color pallete. The color pallete is
-- referenced from the Windows system the bitmap is being viewed on. Remember,
-- "bitmap" is a Microsoft file format!
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02_top.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE work.components.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY lq057q3dc02_top IS
-----------------------------------------------------------------
-- Generic Descriptions:
--
-- C_BIT_DEPTH -- Bit depth of this LCD
--
-- Video Controller (passed thru from top-level to component)
-- C_RL_STATUS -- Value to use for the RL port
-- C_UD_STATUS -- Value to use for the UD port
-- C_VQ_STATUS -- Value to use for the VQ port
--
-- VSYNCx Controller (passed thru from top-level to component)
-- C_VSYNC_TV -- VSYNCx cycle time (in lines)
-- C_VSYNC_TVP -- VSYNCx pulse width (in lines)
-- C_VSYNC_TVS -- VSYNCx start position (in lines) - We can't start
-- -- sending data until at least 7 lines have passed
-- -- (i.e. start sending data on the 8th line).
-- C_LINE_NUM_WIDTH -- Width of register that stores current line number
-- -- (need at least 9 bits to hold maximum TV
-- -- timespec value of 280)
--
-- HSYNCx Controller (passed thru from top-level to component)
-- C_HSYNC_TH -- HSYNCx cycle time (in clocks)
-- C_HSYNC_THP -- HSYNCx pulse width (in clocks) (maximum pulse width is
-- -- best b/c it will conserver the most power)
-- C_NUM_CLKS_WIDTH -- Width of register that stores current number of
-- -- clock cycles that have occurred.
-- -- (need at least 9 bits to hold maximum TH
-- -- timespec value of 450)
--
-- CLK_LCD Cycle Counter (passed thru from top-level to component)
-- C_CLK_LCD_CYC_NUM_WIDTH -- Width of register that stores current number
-- -- of clock cycles that have occurred.
-- -- (need at least 9 bits to hold maximum timespec
-- -- value of full screen image width (320 clocks)
-- -- + maximum timespec value of C_ENAB_THE
-- -- ([C_ENAB_TH_max - 340] clocks) = 430)
-- ENAB Controller (passed thru from top-level to component)
-- C_ENAB_TEP -- ENAB pulse width (in clocks)
-- C_ENAB_THE -- HSYNCx-ENAB phase difference (in clocks)
--
-- Image Generator (passed thru from top-level to component)
-- Change these when changing the image
-- Also, cleanup all project files, and delete all auto-generated
-- image_gen_bram files.
-- C_BRAM_ADDR_WIDTH -- address width required to access all bytes in
-- -- BRAM image (e.g. a full screen image of 320x240
-- -- pixels would require an address width of 17)
-- C_IMAGE_WIDTH -- image width (in pixels)
-- C_IMAGE_HEIGHT -- image height (in pixels)
-----------------------------------------------------------------
GENERIC (
C_BIT_DEPTH : POSITIVE := 18;
C_RL_STATUS : STD_LOGIC := '0';
C_UD_STATUS : STD_LOGIC := '1';
C_VQ_STATUS : STD_LOGIC := '0';
C_VSYNC_TV : POSITIVE := 255;
C_VSYNC_TVP : POSITIVE := 3;
C_VSYNC_TVS : POSITIVE := 7;
C_LINE_NUM_WIDTH : POSITIVE := 9;
C_HSYNC_TH : POSITIVE := 400;
C_HSYNC_THP : POSITIVE := 10;
C_NUM_CLKS_WIDTH : POSITIVE := 9;
C_CLK_LCD_CYC_NUM_WIDTH : POSITIVE := 9;
C_ENAB_TEP : POSITIVE := 320;
C_ENAB_THE : POSITIVE := 8;
C_BRAM_ADDR_WIDTH : POSITIVE := 17;
C_IMAGE_WIDTH : POSITIVE := 320;
C_IMAGE_HEIGHT : POSITIVE := 240
);
-----------------------------------------------------------------
-- Port Descriptions:
-- INPUTS
-- --Clocks/Resets--
-- RSTx -- System Reset
-- CLK100_PAD -- 100MHz Input Clock from On-board XTAL
--
-- OUTPUTS
-- --LCD Control Signals--
-- CLK_LCD -- 6.25MHz LCD Clock
-- HSYNCx -- Horizontal Sync Strobe
-- VSYNCx -- Vertical Sync Strobe
-- ENAB -- Enable Signal for LCD's shift registers
-- RL -- LCD Image Right/Left Orientation
-- UD -- LCD Image Up/Down Orientation
-- VQ -- VGA (640x480) or QVGA (320x240) mode
--
-- --LCD Data Signals--
-- R,G,B -- Red/Green/Blue Color Data
-----------------------------------------------------------------
PORT (
-- <PORT_NAME> : <MODE> <DATA_TYPE>;
RSTx,
CLK_100M_PAD : IN std_logic;
CLK_LCD,
HSYNCx,
VSYNCx,
ENAB,
RL,
UD,
VQ : OUT std_logic;
R,
G,
B : OUT std_logic_vector(C_BIT_DEPTH/3-1 downto 0)
);
END ENTITY lq057q3dc02_top;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE lq057q3dc02_top_arch OF lq057q3dc02_top IS
--Connecting wires to carry signals b/w components
signal CLK_LCD_wire : std_logic := '0';
signal HSYNCx_wire : std_logic := '1';
signal VSYNCx_wire : std_logic := '1';
signal LINE_NUM_wire : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0');
signal CLK_LCD_CYC_NUM_wire : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0');
begin
--///////////////////--
-- ASSERT STATEMENTS --
--///////////////////--
-- LQ057Q3DC02 Datasheet Timing Parameter Checks
--TODO: is a check for C_BIT_DEPTH needed? If colors, will just be truncated then that would be kewl. Too high might want to be checked in any case as the colors will not display exactly the same on the LCD.
ASSERT C_VQ_STATUS = '0'
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_VQ_STATUS (must be '0', lq057q3dc02 only supports QVGA (320x240) mode)"
SEVERITY FAILURE;
ASSERT C_VSYNC_TV >= 251 and C_VSYNC_TV <= 280
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_VSYNC_TV (must be >= 251 and <= 280)"
SEVERITY FAILURE;
ASSERT C_VSYNC_TVP >= 2 and C_VSYNC_TVP <= 34
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_VSYNC_TVP (must be >= 2 and <= 34)"
SEVERITY FAILURE;
ASSERT C_VSYNC_TVS = 7
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_VSYNC_TVS (must be 7)"
SEVERITY FAILURE;
ASSERT C_LINE_NUM_WIDTH = 9
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_LINE_NUM_WIDTH (must be 9 to hold maximum TV timespec value of 280"
SEVERITY FAILURE;
ASSERT C_HSYNC_TH >= 360 and C_HSYNC_TH <= 450
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_HSYNC_TH (must be >= 360 and <= 450)"
SEVERITY FAILURE;
ASSERT C_HSYNC_THP >= 2 and C_HSYNC_THP <= 200
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_HSYNC_THP (must be >= 2 and <= 200)"
SEVERITY FAILURE;
ASSERT C_NUM_CLKS_WIDTH = 9
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_NUM_CLKS_WIDTH (must be 9 to hold maximum TH timespec value of 450"
SEVERITY FAILURE;
ASSERT C_CLK_LCD_CYC_NUM_WIDTH = 9
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_CLK_LCD_CYC_NUM_WIDTH (must be 9 to hold maximum TH timespec value of 430"
SEVERITY FAILURE;
ASSERT C_ENAB_TEP >= 2 and C_ENAB_TEP <= (C_HSYNC_TH - 10)
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_ENAB_TEP (must be >= 2 and <= (C_HSYNC_TH - 10))"
SEVERITY FAILURE;
ASSERT C_ENAB_THE >= 2 and C_ENAB_THE <= (C_HSYNC_TH - 340)
REPORT "ERROR - lq057q3dc02_top: Invalid value for generic C_ENAB_THE (must be >= 2 and <= (C_HSYNC_TH - 340))"
SEVERITY FAILURE;
--///////////////////////--
-- CONCURRENT STATEMENTS --
--///////////////////////--
CLK_LCD <= CLK_LCD_wire;
HSYNCx <= HSYNCx_wire;
VSYNCx <= VSYNCx_wire;
--//////////////////////////--
-- COMPONENT INSTANTIATIONS --
--//////////////////////////--
-- DCM creates 6.25MHz LCD clock from 100MHz system clock.
-- DCM creates 25.0MHz clock for Logic Analyzer debugging.
-- Xilinx does not allow CLK0_OUT to be removed
-- This DCM was created with the Xilinx architecture wizard,
-- therefore the .xaw file MUST be included in the project.
DCM_LCD_CLK : dcm_sys_to_lcd
PORT MAP (
RST_IN => "not"(RSTx),
CLKIN_IN => CLK_100M_PAD,
CLKIN_IBUFG_OUT => OPEN, -- 100MHz clock if you need it (attach to BUFG)
CLK0_OUT => OPEN, -- 50MHz clock
CLKDV_OUT => CLK_LCD_wire, -- 6.25MHz LCD Clock
CLKFX_OUT => OPEN -- Attach this 25MHz clock to an output port for a logic analyzer
);
V_C : video_controller
GENERIC MAP (
--Video Controller
C_RL_STATUS => C_RL_STATUS,
C_UD_STATUS => C_UD_STATUS,
C_VQ_STATUS => C_VQ_STATUS,
--VSYNCx Controller
C_VSYNC_TV => C_VSYNC_TV,
C_VSYNC_TVP => C_VSYNC_TVP,
C_VSYNC_TVS => C_VSYNC_TVS,
C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH,
--HSYNCx Controller
C_HSYNC_TH => C_HSYNC_TH,
C_HSYNC_THP => C_HSYNC_THP,
C_NUM_CLKS_WIDTH => C_NUM_CLKS_WIDTH,
--CLK_LCD Cycle Counter
C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH,
--ENAB Controller
C_ENAB_TEP => C_ENAB_TEP,
C_ENAB_THE => C_ENAB_THE
)
PORT MAP (
RSTx => RSTx,
CLK_LCD => CLK_LCD_wire,
CLK_LCD_CYC_NUM => CLK_LCD_CYC_NUM_wire,
-- OUTPUTS
LINE_NUM => LINE_NUM_wire,
HSYNCx => HSYNCx_wire,
VSYNCx => VSYNCx_wire,
ENAB => ENAB,
RL => RL,
UD => UD,
VQ => VQ
);
IMAGE : image_gen_bram
GENERIC MAP (
C_BIT_DEPTH => C_BIT_DEPTH,
C_VSYNC_TVS => C_VSYNC_TVS,
C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP => C_ENAB_TEP,
C_ENAB_THE => C_ENAB_THE,
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH,
C_IMAGE_WIDTH => C_IMAGE_WIDTH,
C_IMAGE_HEIGHT => C_IMAGE_HEIGHT
)
PORT MAP (
RSTx => RSTx,
CLK_LCD => CLK_LCD_wire,
LINE_NUM => LINE_NUM_wire,
CLK_LCD_CYC_NUM => CLK_LCD_CYC_NUM_wire,
--OUTPUTS
R => R,
G => G,
B => B
);
END ARCHITECTURE lq057q3dc02_top_arch;
| gpl-2.0 | a2db6153b5fb72b73dcd06290a62e30e | 0.53883 | 3.653192 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/spi/spi_comm.vhd | 1 | 2,701 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spi_comm is
port(
CLK : in std_logic;
RESET : in std_logic;
SPI_CS_A : in std_logic;
SPI_CS_D : in std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
ADDR_O : out std_logic_vector(7 downto 0);
ADDR_I : in std_logic_vector(7 downto 0);
ADDR_REQ : out std_logic;
ADDR_ACK : in std_logic;
DATA_O : out std_logic_vector(7 downto 0);
DATA_I : in std_logic_vector(7 downto 0);
DATA_REQ : out std_logic;
DATA_ACK : in std_logic );
end spi_comm;
architecture RTL of spi_comm is
signal ADDR_IN : std_logic_vector (7 downto 0);
signal DATA_IN : std_logic_vector (7 downto 0);
signal ADDR_OUT : std_logic_vector (7 downto 0);
signal DATA_OUT : std_logic_vector (7 downto 0);
signal CS_A_LAST : std_logic_vector (1 downto 0);
signal CS_D_LAST : std_logic_vector (1 downto 0);
begin
process (SPI_SCK)
begin
if rising_edge(SPI_SCK) then
if SPI_CS_A = '0' then
ADDR_IN <= ADDR_IN (6 downto 0) & SPI_DI;
elsif SPI_CS_D = '0' then
DATA_IN <= DATA_IN (6 downto 0) & SPI_DI;
end if;
end if;
end process;
process (CLK) is
begin
if rising_edge(CLK) then
if RESET = '1' then
CS_A_LAST <= "11";
CS_D_LAST <= "11";
ADDR_REQ <= '0';
DATA_REQ <= '0';
else
if ADDR_ACK = '1' then
ADDR_REQ <= '0';
end if;
if DATA_ACK = '1' then
DATA_REQ <= '0';
end if;
CS_A_LAST <= CS_A_LAST(0) & SPI_CS_A;
CS_D_LAST <= CS_D_LAST(0) & SPI_CS_D;
if CS_D_LAST = "01" then
DATA_O <= DATA_IN;
DATA_REQ <= '1';
end if;
if CS_A_LAST = "01" then
ADDR_O <= ADDR_IN;
ADDR_REQ <= '1';
end if;
end if;
end if;
end process;
process (SPI_SCK, ADDR_I, SPI_CS_A, DATA_I, SPI_CS_D)
begin
if SPI_CS_A = '1' then
ADDR_OUT <= ADDR_I;
elsif falling_edge(SPI_SCK) then
ADDR_OUT <= ADDR_OUT(6 downto 0) & '0';
end if;
if SPI_CS_D = '1' then
DATA_OUT <= DATA_I;
elsif falling_edge(SPI_SCK) then
DATA_OUT <= DATA_OUT(6 downto 0) & '0';
end if;
end process;
SPI_DO <= ADDR_OUT(7) when SPI_CS_A = '0' else DATA_OUT(7) when SPI_CS_D = '0' else 'Z';
end RTL;
| gpl-3.0 | 6ac218799d900a268cf6a0ec57d39ff5 | 0.481673 | 3.133411 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/AESL_sim_pkg.vhd | 2 | 8,743 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
| mit | 5248318dc3fb21a080e26a072ed0c12f | 0.496969 | 3.954319 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/DFlipFlop.vhd | 2 | 2,907 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : DFlipFlop2Out.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Simple D Flip-Flop with two outputs
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DFlipFlop is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end DFlipFlop;
architecture Behavioral of DFlipFlop is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
o_Q <= Q;
o_Q_n <= not Q;
end Behavioral;
| gpl-3.0 | 759c36f1a5bb383570212338353cef79 | 0.474028 | 4.592417 | false | false | false | false |
APastorG/APG | permutation/permutation_pkg.vhd | 1 | 12,673 |
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
package permutation_pkg is
function permutation_checks(
input_length : integer;
input_indexes : integer_v;
output_indexes : integer_v)
return boolean;
function is_pp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function is_sp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function is_ss_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean;
function contiguous_ps_latency(
optimal_perm : integer_vv;
parallel_dimensions : positive;
i : natural;
left : boolean)
return natural;
function calculate_indexes(
i : integer;
P : natural;
K : natural;
offset : natural)
return natural;
function generate_perm_file_name(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return string;
end package;
package body permutation_pkg is
function permutation_checks(
input_length : integer;
input_indexes : integer_v;
output_indexes : integer_v)
return boolean is
variable dimensions : integer := output_indexes'length;
variable par_dimensions : real := log2(real(input_length));
variable par_dimensions_int : integer := integer(par_dimensions);
begin
--The number of inputs is not a power of 2
assert (integer(par_dimensions) mod 1) = 0
report "(1) " &
"ERROR in module permutation: The number of inputs(" &
image(input_length) & ") must be a power of 2 " & image(par_dimensions mod 1.0)
severity error;
--The generic OUTPUT_INDEXES and the number of inputs do not agree, as the value of dimensions
--is smaller than the parallel dimensions
assert dimensions >= par_dimensions_int
report "(2) " &
"ERROR in module permutation: For the length of the assigned output indexes (" &
image(dimensions) & ") the number of inputs (" & image(input_length) & ") " &
"cannot be greater than (" & image(integer(2.0**dimensions)) & ")"
severity error;
--The generics INPUT_INDEXES and OUTPUT_INDEXES don't have the same size
assert output_indexes'length >= input_indexes'length
report "(3) " &
"ERROR in module permutation: The sizes of the parameters INPUT_INDEXES(" &
image(integer'(input_indexes'length)) & ") and OUTPUT_INDEXES(" &
image(integer'(output_indexes'length)) &
") must be equal."
severity error;
--The input_indexes vector doesn't contain all the indexes from 0 to dimensions-1
ext_loop_in: for i in 0 to dimensions - 1 loop
for j in 0 to dimensions - 1 loop
if input_indexes(j) = i then
next ext_loop_in;
end if;
end loop;
assert false
report "(4) " &
"ERROR in module permutation: The values of INPUT_INDEXES must contain the " &
"values from 0 to " & image(dimensions-1) & " but " & image(i) & " is missing"
severity error;
end loop;
--The output_indexes vector doesn't contain all the indexes from 0 to dimensions-1
ext_loop_out: for i in 0 to dimensions - 1 loop
for j in 0 to dimensions - 1 loop
if output_indexes(j) = i then
next ext_loop_out;
end if;
end loop;
assert false
report "(5) " &
"ERROR in module permutation: The values of OUTPUT_INDEXES must contain the " &
"values from 0 to " & image(dimensions-1) & " but " & image(i) & " is missing"
severity error;
end loop;
return true;
end function;
function is_parallel(
index : natural;
parallel_dimensions : natural)
return boolean is
begin
return index < parallel_dimensions;
end function;
function is_pp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_pp called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return is_parallel(elem_bit_exchange(1), parallel_dimensions)
and
is_parallel(elem_bit_exchange(2), parallel_dimensions);
end function;
function is_sp_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_sp called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return is_parallel(elem_bit_exchange(1), parallel_dimensions)
xor
is_parallel(elem_bit_exchange(2), parallel_dimensions);
end function;
function is_ss_perm(
elem_bit_exchange : integer_v;
parallel_dimensions : natural)
return boolean is
begin
assert elem_bit_exchange'length = 2
report "ERROR in module permutation: function is_ss called with parameter " &
"elem_bit_exchange of illegal length (" & image(integer'(elem_bit_exchange'length)) &")."
severity error;
return not(is_parallel(elem_bit_exchange(1), parallel_dimensions)
or
is_parallel(elem_bit_exchange(2), parallel_dimensions));
end function;
function contiguous_ps_latency(
optimal_perm : integer_vv;
parallel_dimensions : positive;
i : natural;
left : boolean)
return natural is
begin
if left and i > 1 then
if is_sp_perm(optimal_perm(i-1), parallel_dimensions) then --previous elementary bit exchange is serial-parallel
if minimum(optimal_perm(i-1)) = minimum(optimal_perm(i)) then --they share the lowest dimension(the parallel one)
return (2**maximum(optimal_perm(i-1)))/(2**parallel_dimensions); --return latency of previous ps permutation block
end if;
end if;
elsif (not left) and (i < optimal_perm'length) then
if is_sp_perm(optimal_perm(i+1), parallel_dimensions) then --next elementary bit exchange is serial-parallel
if minimum(optimal_perm(i+1)) = minimum(optimal_perm(i)) then --they share the lowest dimension(the parallel one)
return (2**maximum(optimal_perm(i+1)))/(2**parallel_dimensions); --return latency of next ps permutation block
end if;
end if;
end if;
return 0;
end function;
function calculate_indexes(
i : integer;
P : natural;
K : natural;
offset : natural)
return natural is
variable aux : std_ulogic_vector(P-1 downto 0);
begin
aux := std_ulogic_vector(to_unsigned(abs(i), P));
aux := aux sll 1;
if K > 0 then
aux(K-1 downto 0) := aux(K downto 1);
end if;
aux(K) := '1' when offset = 1 else
'0';
return to_integer(unsigned(aux));
end function;
--designed for at most 99 indexes
function calculate_file_name_length(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return positive is
constant number_of_indexes : positive := input_indexes'length;
constant one_digit_indexes : natural := minimum(10, number_of_indexes);
constant two_digit_indexes : natural := ite(number_of_indexes > 10,
number_of_indexes-10,
0);
variable is_input_in_order : boolean := true;
variable is_output_in_order : boolean := true;
variable result : natural := 0;
begin
if parallel_dimensions > 9 then --"10_"
result := result + 3;
elsif parallel_dimensions > 0 then --"9_"
result := result + 2;
end if;
floop1:
for i in 0 to number_of_indexes-1 loop
if input_indexes(i) /= number_of_indexes-1-i then
is_input_in_order := false;
exit floop1;
end if;
end loop;
floop2:
for i in 0 to number_of_indexes-1 loop
if output_indexes(i) /= number_of_indexes-1-i then
is_output_in_order := false;
exit floop2;
end if;
end loop;
if is_input_in_order then
result := result + 2; --"00"
else
result := result + one_digit_indexes; --"1"
result := result + 2*two_digit_indexes; --"a1" (11)
end if;
result := result + 1; --"_"
if is_output_in_order then
result := result + 2; --"00"
else
result := result + one_digit_indexes; --"1"
result := result + 2*two_digit_indexes; --"a1" (11)
end if;
result := result + 4; --".txt"
return result;
end function;
--string used as this function should be static to work when called in synthesis and thus cannot
--contain line data types(which would more flexible as the size wouldn't need to be predefined)
--designed for at most 99 indexes
function generate_perm_file_name(
parallel_dimensions : positive;
input_indexes : integer_v;
output_indexes : integer_v)
return string is
constant letters : string(1 to 9) := "abcdefghi";
constant file_name_length : positive := calculate_file_name_length(parallel_dimensions,
input_indexes,
output_indexes);
variable is_input_in_order : boolean := true;
variable is_output_in_order : boolean := true;
variable counter : natural := 1;
variable result : string(1 to file_name_length);
begin
if parallel_dimensions > 9 then
result(counter to counter+1) := image(parallel_dimensions);
counter := counter + 2;
elsif parallel_dimensions > 0 then
result(counter to counter) := image(parallel_dimensions);
counter := counter + 1;
end if;
result(counter to counter) := "_";
counter := counter + 1;
floop1:
for i in 0 to input_indexes'length-1 loop
if input_indexes(i) /= input_indexes'length-1-i then
is_input_in_order := false;
exit floop1;
end if;
end loop;
floop2:
for i in 0 to output_indexes'length-1 loop
if output_indexes(i) /= output_indexes'length-1-i then
is_output_in_order := false;
exit floop2;
end if;
end loop;
if is_input_in_order then
result(counter to counter+1) := "00";
counter := counter + 2;
else
for i in 0 to input_indexes'length-1 loop
if input_indexes(i)>9 then
result(counter) := letters(integer(real(input_indexes(i))/10.0));
counter := counter + 1;
end if;
result(counter) := integer'image(input_indexes(i) rem 10)(1);
counter := counter + 1;
end loop;
end if;
result(counter) := '_';
counter := counter + 1;
if is_output_in_order then
result(counter to counter+1) := "00";
counter := counter + 2;
else
for i in 0 to output_indexes'length-1 loop
if output_indexes(i)>9 then
result(counter) := letters(integer(real(output_indexes(i))/10.0));
counter := counter + 1;
end if;
result(counter) := integer'image(output_indexes(i) rem 10)(1);
counter := counter + 1;
end loop;
end if;
result(counter to counter + 3) := string'(".txt");
return result;
end function;
end package body; | mit | b5e31266f4ac3f61a939ae3e8963d465 | 0.573582 | 4.107942 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/video_backup.vhd | 1 | 5,537 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
port (
CLK : in std_logic;
VGA_CLK : in std_logic;
RESET : in std_logic;
VA : in std_logic_vector(11 downto 0);
VDI : in std_logic_vector(7 downto 0);
VWR : in std_logic;
VATTR : in std_logic_vector(7 downto 0);
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic
);
end video;
architecture Behavioral of video is
signal V_COUNTER : unsigned(9 downto 0); -- Vertical Counter
signal H_COUNTER : unsigned(11 downto 0); -- Horizontal Counter
signal PAPER : std_logic;
signal PAPER_ENA : std_logic;
signal PIX : std_logic_vector(7 downto 0);
signal PIX_LT : std_logic_vector(7 downto 0);
signal ATTR : std_logic_vector(7 downto 0);
signal ATTR_LT : std_logic_vector(7 downto 0);
constant HSIZE : integer := 640; -- Paper H_size --1024
constant VSIZE : integer := 480; -- Paper V_size --768
constant HFP : integer := 16; --24;
constant HS : integer := 96; --136;
constant HB : integer := 48; --160;
constant VFP : integer := 19; --3;
constant VS : integer := 2; --6;
constant VB : integer := 33; --29;
signal FONTROM_A : std_logic_vector(11 downto 0);
signal FONTROM_DO : std_logic_vector(7 downto 0);
signal VRAM_WR : std_logic_vector(0 downto 0);
signal VRAM_RA : std_logic_vector(11 downto 0);
signal VRAM_RDO : std_logic_vector(15 downto 0);
begin
--##########################
VRAM_WR <= "1" when VWR = '1' else "0";
u_FONTROM : entity work.fontrom
port map(
clka => VGA_CLK,
addra => FONTROM_A,
douta => FONTROM_DO );
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WR,
addra => VA,
dina => VATTR & VDI,
clkb => VGA_CLK,
addrb => VRAM_RA,
doutb => VRAM_RDO );
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if RESET = '1' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
VGA_HSYNC <= '1';
VGA_VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HFP) and H_COUNTER < (HSIZE + HFP + HS)then
VGA_HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VFP) and V_COUNTER < (VSIZE + VFP + VS)then
VGA_VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
case H_COUNTER(2 downto 0) is
when "000" =>
VRAM_RA <= std_logic_vector(V_COUNTER(8 downto 4)) & std_logic_vector(H_COUNTER(9 downto 3));
when "010" =>
FONTROM_A <= VRAM_RDO(7 downto 0) & std_logic_vector(V_COUNTER(3 downto 0));
ATTR <= VRAM_RDO(15 downto 8);
when "100" =>
PIX <= FONTROM_DO;
when "111" =>
PAPER_ENA <= PAPER;
PIX_LT <= PIX;
ATTR_LT <= ATTR;
when others => NULL;
end case;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if PAPER_ENA = '1' then
if PIX_LT(7 - to_integer(H_COUNTER(2 downto 0))) = '1' then
VGA_R(3) <= ATTR_LT(0);
VGA_R(2) <= ATTR_LT(0) and ATTR_LT(3);
VGA_R(1) <= ATTR_LT(0) and ATTR_LT(3);
VGA_R(0) <= ATTR_LT(0);
VGA_G(3) <= ATTR_LT(1);
VGA_G(2) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(1) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(0) <= ATTR_LT(1);
VGA_B(3) <= ATTR_LT(2);
VGA_B(2) <= ATTR_LT(2) and ATTR_LT(3);
VGA_B(1) <= ATTR_LT(2) and ATTR_LT(3);
VGA_B(0) <= ATTR_LT(2);
else
VGA_R(3) <= ATTR_LT(4);
VGA_R(2) <= ATTR_LT(4) and ATTR_LT(7);
VGA_R(1) <= ATTR_LT(4) and ATTR_LT(7);
VGA_R(0) <= ATTR_LT(4);
VGA_G(3) <= ATTR_LT(5);
VGA_G(2) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(1) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(0) <= ATTR_LT(5);
VGA_B(3) <= ATTR_LT(6);
VGA_B(2) <= ATTR_LT(6) and ATTR_LT(7);
VGA_B(1) <= ATTR_LT(6) and ATTR_LT(7);
VGA_B(0) <= ATTR_LT(6);
end if;
else
VGA_G <= "0000";
VGA_R <= "0000";
VGA_B <= "0000";
end if;
end if;
end process;
--process (VGA_CLK)
--begin
-- if rising_edge(VGA_CLK) then
-- VGA_R <= "0000";
-- VGA_G <= "0000";
-- VGA_B <= "0000";
-- if PAPER = '1' then
-- VGA_B <= "1111";
-- end if;
-- end if;
--end process;
end Behavioral;
| gpl-3.0 | 21a3f134fa660ab96d501de47b7137f6 | 0.470652 | 3.089844 | false | false | false | false |
APastorG/APG | general/fixed_generic_pkg.vhd | 1 | 281,150 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: #1 $
-- Date : $Date: 2015/12/22 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fixed_float_types.all;
package fixed_generic_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_truncate;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_wrap;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (true
);
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright 2008 by IEEE. All rights reserved.";
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
alias U_ufixed is UNRESOLVED_ufixed;
alias U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is (resolved) UNRESOLVED_ufixed;
subtype sfixed is (resolved) UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed;
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNRESOLVED_UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
end package fixed_generic_pkg;
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_generic_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report --fixed_generic_pkg'instance_name &
" Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report --fixed_generic_pkg'instance_name &
" Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report --fixed_generic_pkg'instance_name &
" Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNRESOLVED_UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : UNRESOLVED_SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNRESOLVED_UNSIGNED
is
subtype t is UNRESOLVED_UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return UNRESOLVED_SIGNED
is
subtype t is UNRESOLVED_SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNRESOLVED_UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : UNRESOLVED_SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
assert no_warning
report --fixed_generic_pkg'instance_name &
"TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNRESOLVED_UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
assert no_warning
report --fixed_generic_pkg'instance_name &
"TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => UNRESOLVED_SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_UNSIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_SIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report --fixed_generic_pkg'instance_name &
"DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
assert no_warning
report --fixed_generic_pkg'instance_name &
"DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report --fixed_generic_pkg'instance_name &
"remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-- End reduction operators
function "?=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
function "?=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
""">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
assert NO_WARNING report --fixed_generic_pkg'instance_name &
"TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report --fixed_generic_pkg'instance_name &
"TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report --fixed_generic_pkg'instance_name &
"TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report --fixed_generic_pkg'instance_name &
"TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report --fixed_generic_pkg'instance_name &
"TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNRESOLVED_UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(arg);--cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(arg);--cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL
is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNRESOLVED_UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : UNRESOLVED_SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report --fixed_generic_pkg'instance_name &
"READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report --fixed_generic_pkg'instance_name &
"READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report --fixed_generic_pkg'instance_name &
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report --fixed_generic_pkg'instance_name &
"OREAD(sfixed) "
& mess
severity error;
else
report --fixed_generic_pkg'instance_name &
"OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report --fixed_generic_pkg'instance_name &
"OREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report --fixed_generic_pkg'instance_name &
"OREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report --fixed_generic_pkg'instance_name &
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Routines common to the HREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report --fixed_generic_pkg'instance_name &
"HREAD(sfixed) "
& mess
severity error;
else
report --fixed_generic_pkg'instance_name &
"HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report --fixed_generic_pkg'instance_name &
"HREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report --fixed_generic_pkg'instance_name &
"HREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report --fixed_generic_pkg'instance_name &
"HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
-- To_string functions. Useful in "report" statements.
-- Example: report "result was " & to_string(result);
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(std_ulogic(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report --fixed_generic_pkg'instance_name &
"from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report --fixed_generic_pkg'instance_name &
"Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report --fixed_generic_pkg'instance_name &
"Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
end package body fixed_generic_pkg;
| mit | 5da044db148f56498426d9b601030b2b | 0.575405 | 4.008526 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/antic_dma_clock.vhdl | 1 | 2,214 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY antic_dma_clock IS
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
enable_dma : IN STD_LOGIC;
playfield_start : in std_logic;
playfield_end : in std_logic;
vblank : in std_logic;
slow_dma : in std_logic;
medium_dma : in std_logic;
fast_dma : in std_logic;
dma_clock_out_0 : out std_logic;
dma_clock_out_1 : out std_logic;
dma_clock_out_2 : out std_logic;
dma_clock_out_3 : out std_logic
);
END antic_dma_clock;
ARCHITECTURE vhdl OF antic_dma_clock IS
signal dma_shiftreg_next : std_logic_vector(7 downto 0);
signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
signal tick : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
dma_shiftreg_reg <= (others=>'0');
elsif (clk'event and clk='1') then
dma_shiftreg_reg <= dma_shiftreg_next;
end if;
end process;
-- next state
tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
begin
dma_shiftreg_next <= dma_shiftreg_reg;
if (enable_dma = '1') then
dma_shiftreg_next <=
not((playfield_start nor tick)
or playfield_end or vblank)
&dma_shiftreg_reg(7 downto 1);
end if;
if (playfield_start = '1') then
dma_shiftreg_next(7) <= not((playfield_start nor tick) or playfield_end or vblank);
end if;
end process;
-- output
dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
END vhdl;
| gpl-3.0 | 67fd64bee2de8c83eb5ced2bbc5f15dd | 0.639115 | 2.983827 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03700_good.vhd | 1 | 3,115 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03700_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset assertion and deassertion: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_03700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_Input_n : in std_logic; -- Reset input
o_Main_Reset_n : out std_logic -- Global reset signal active low
);
end STD_03700_good;
architecture Behavioral of STD_03700_good is
signal Main_Reset_n : std_logic; -- Internal signal between FlipFlops
signal Main_Reset_n_r : std_logic; -- Assertion block output
begin
P_Reset_Assert : process(i_Reset_Input_n, i_Clock)
begin
if (i_Reset_Input_n = '0') then
Main_Reset_n <= '0'; -- Output reset signal is active low
Main_Reset_n_r <= '0';
elsif rising_edge(i_Clock) then
Main_Reset_n <= '1'; -- Reset is deasserted. Since it is active low, the inactive value is 1
Main_Reset_n_r <= Main_Reset_n;
end if;
end process;
o_Main_Reset_n <= Main_Reset_n_r;
end Behavioral;
--CODE
| gpl-3.0 | 6160cb0b33552198fdbef874644b64f7 | 0.504655 | 4.412181 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/uart.vhd | 1 | 6,245 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(8 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(7 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2)
constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
"0110110010"; --25MHz/57600Hz = 0x1b2
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
read_value_reg <= ONES(7 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(8 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
data_save_reg <= '1' & data_read_reg;
elsif enable_read = '1' then
data_save_reg(8) <= '0'; --data_available
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000" and log_file = "UNUSED" then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line had to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
end; --architecture logic
| gpl-3.0 | 4d9ab412929b5270ef3a5d62efec7a3a | 0.551321 | 3.542258 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom.vhd | 1 | 5,390 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cham_rom.vhd when simulating
-- the core, cham_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cham_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END cham_rom;
ARCHITECTURE cham_rom_a OF cham_rom IS
-- synthesis translate_off
COMPONENT wrapped_cham_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cham_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "cham_rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cham_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END cham_rom_a;
| gpl-3.0 | a981ebaf4f93d17b0d17823b35eec9eb | 0.528571 | 3.969072 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/dmips_dbram.vhdl | 1 | 105,913 | ------------------------------------------------------------------------------
---- ----
---- Dual Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: DualPortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end entity DualPortRAM;
architecture Xilinx of DualPortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
shared variable ram : ram_type:=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80f8ec0c",
3 => x"3a0b0b80",
4 => x"e7ea0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80e8b72d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80f8",
162 => x"d8738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b80ce",
171 => x"b62d5050",
172 => x"80085688",
173 => x"0c840c80",
174 => x"0c510400",
175 => x"00000000",
176 => x"80088408",
177 => x"88087575",
178 => x"0b0b80cf",
179 => x"e82d5050",
180 => x"80085688",
181 => x"0c840c80",
182 => x"0c510400",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80f8e80c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83803f80",
257 => x"e2953f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"ff3d0d0b",
281 => x"0b8188e0",
282 => x"08527108",
283 => x"70882a81",
284 => x"32708106",
285 => x"51515170",
286 => x"f1387372",
287 => x"0c833d0d",
288 => x"0480f8e8",
289 => x"08802ea4",
290 => x"3880f8ec",
291 => x"08822ebd",
292 => x"38838080",
293 => x"0b0b0b81",
294 => x"88e00c82",
295 => x"a0800b81",
296 => x"88e40c82",
297 => x"90800b81",
298 => x"88e80c04",
299 => x"f8808080",
300 => x"a40b0b0b",
301 => x"8188e00c",
302 => x"f8808082",
303 => x"800b8188",
304 => x"e40cf880",
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3641 => x"65206173",
3642 => x"2061626f",
3643 => x"76650a00",
3644 => x"496e745f",
3645 => x"315f4c6f",
3646 => x"633a2020",
3647 => x"20202020",
3648 => x"20202020",
3649 => x"2025640a",
3650 => x"00000000",
3651 => x"496e745f",
3652 => x"325f4c6f",
3653 => x"633a2020",
3654 => x"20202020",
3655 => x"20202020",
3656 => x"2025640a",
3657 => x"00000000",
3658 => x"496e745f",
3659 => x"335f4c6f",
3660 => x"633a2020",
3661 => x"20202020",
3662 => x"20202020",
3663 => x"2025640a",
3664 => x"00000000",
3665 => x"456e756d",
3666 => x"5f4c6f63",
3667 => x"3a202020",
3668 => x"20202020",
3669 => x"20202020",
3670 => x"2025640a",
3671 => x"00000000",
3672 => x"5374725f",
3673 => x"315f4c6f",
3674 => x"633a2020",
3675 => x"20202020",
3676 => x"20202020",
3677 => x"2025730a",
3678 => x"00000000",
3679 => x"20202020",
3680 => x"20202020",
3681 => x"73686f75",
3682 => x"6c642062",
3683 => x"653a2020",
3684 => x"20444852",
3685 => x"5953544f",
3686 => x"4e452050",
3687 => x"524f4752",
3688 => x"414d2c20",
3689 => x"31275354",
3690 => x"20535452",
3691 => x"494e470a",
3692 => x"00000000",
3693 => x"5374725f",
3694 => x"325f4c6f",
3695 => x"633a2020",
3696 => x"20202020",
3697 => x"20202020",
3698 => x"2025730a",
3699 => x"00000000",
3700 => x"20202020",
3701 => x"20202020",
3702 => x"73686f75",
3703 => x"6c642062",
3704 => x"653a2020",
3705 => x"20444852",
3706 => x"5953544f",
3707 => x"4e452050",
3708 => x"524f4752",
3709 => x"414d2c20",
3710 => x"32274e44",
3711 => x"20535452",
3712 => x"494e470a",
3713 => x"00000000",
3714 => x"55736572",
3715 => x"2074696d",
3716 => x"653a2025",
3717 => x"640a0000",
3718 => x"4d696372",
3719 => x"6f736563",
3720 => x"6f6e6473",
3721 => x"20666f72",
3722 => x"206f6e65",
3723 => x"2072756e",
3724 => x"20746872",
3725 => x"6f756768",
3726 => x"20446872",
3727 => x"7973746f",
3728 => x"6e653a20",
3729 => x"00000000",
3730 => x"2564200a",
3731 => x"00000000",
3732 => x"44687279",
3733 => x"73746f6e",
3734 => x"65732070",
3735 => x"65722053",
3736 => x"65636f6e",
3737 => x"643a2020",
3738 => x"20202020",
3739 => x"20202020",
3740 => x"20202020",
3741 => x"20202020",
3742 => x"20202020",
3743 => x"00000000",
3744 => x"56415820",
3745 => x"4d495053",
3746 => x"20726174",
3747 => x"696e6720",
3748 => x"2a203130",
3749 => x"3030203d",
3750 => x"20256420",
3751 => x"0a000000",
3752 => x"50726f67",
3753 => x"72616d20",
3754 => x"636f6d70",
3755 => x"696c6564",
3756 => x"20776974",
3757 => x"686f7574",
3758 => x"20277265",
3759 => x"67697374",
3760 => x"65722720",
3761 => x"61747472",
3762 => x"69627574",
3763 => x"650a0000",
3764 => x"4d656173",
3765 => x"75726564",
3766 => x"2074696d",
3767 => x"6520746f",
3768 => x"6f20736d",
3769 => x"616c6c20",
3770 => x"746f206f",
3771 => x"62746169",
3772 => x"6e206d65",
3773 => x"616e696e",
3774 => x"6766756c",
3775 => x"20726573",
3776 => x"756c7473",
3777 => x"0a000000",
3778 => x"506c6561",
3779 => x"73652069",
3780 => x"6e637265",
3781 => x"61736520",
3782 => x"6e756d62",
3783 => x"6572206f",
3784 => x"66207275",
3785 => x"6e730a00",
3786 => x"44485259",
3787 => x"53544f4e",
3788 => x"45205052",
3789 => x"4f475241",
3790 => x"4d2c2033",
3791 => x"27524420",
3792 => x"53545249",
3793 => x"4e470000",
3794 => x"00010202",
3795 => x"03030303",
3796 => x"04040404",
3797 => x"04040404",
3798 => x"05050505",
3799 => x"05050505",
3800 => x"05050505",
3801 => x"05050505",
3802 => x"06060606",
3803 => x"06060606",
3804 => x"06060606",
3805 => x"06060606",
3806 => x"06060606",
3807 => x"06060606",
3808 => x"06060606",
3809 => x"06060606",
3810 => x"07070707",
3811 => x"07070707",
3812 => x"07070707",
3813 => x"07070707",
3814 => x"07070707",
3815 => x"07070707",
3816 => x"07070707",
3817 => x"07070707",
3818 => x"07070707",
3819 => x"07070707",
3820 => x"07070707",
3821 => x"07070707",
3822 => x"07070707",
3823 => x"07070707",
3824 => x"07070707",
3825 => x"07070707",
3826 => x"08080808",
3827 => x"08080808",
3828 => x"08080808",
3829 => x"08080808",
3830 => x"08080808",
3831 => x"08080808",
3832 => x"08080808",
3833 => x"08080808",
3834 => x"08080808",
3835 => x"08080808",
3836 => x"08080808",
3837 => x"08080808",
3838 => x"08080808",
3839 => x"08080808",
3840 => x"08080808",
3841 => x"08080808",
3842 => x"08080808",
3843 => x"08080808",
3844 => x"08080808",
3845 => x"08080808",
3846 => x"08080808",
3847 => x"08080808",
3848 => x"08080808",
3849 => x"08080808",
3850 => x"08080808",
3851 => x"08080808",
3852 => x"08080808",
3853 => x"08080808",
3854 => x"08080808",
3855 => x"08080808",
3856 => x"08080808",
3857 => x"08080808",
3858 => x"43000000",
3859 => x"64756d6d",
3860 => x"792e6578",
3861 => x"65000000",
3862 => x"00ffffff",
3863 => x"ff00ffff",
3864 => x"ffff00ff",
3865 => x"ffffff00",
3866 => x"00000000",
3867 => x"00000000",
3868 => x"00000000",
3869 => x"00004458",
3870 => x"0000000a",
3871 => x"00000000",
3872 => x"00000032",
3873 => x"00000000",
3874 => x"00000000",
3875 => x"00000000",
3876 => x"00000000",
3877 => x"00000000",
3878 => x"00000000",
3879 => x"00000000",
3880 => x"00000000",
3881 => x"00000000",
3882 => x"00000000",
3883 => x"00000000",
3884 => x"00000000",
3885 => x"ffffffff",
3886 => x"00000000",
3887 => x"00020000",
3888 => x"00000000",
3889 => x"00000000",
3890 => x"00003cc0",
3891 => x"00003cc0",
3892 => x"00003cc8",
3893 => x"00003cc8",
3894 => x"00003cd0",
3895 => x"00003cd0",
3896 => x"00003cd8",
3897 => x"00003cd8",
3898 => x"00003ce0",
3899 => x"00003ce0",
3900 => x"00003ce8",
3901 => x"00003ce8",
3902 => x"00003cf0",
3903 => x"00003cf0",
3904 => x"00003cf8",
3905 => x"00003cf8",
3906 => x"00003d00",
3907 => x"00003d00",
3908 => x"00003d08",
3909 => x"00003d08",
3910 => x"00003d10",
3911 => x"00003d10",
3912 => x"00003d18",
3913 => x"00003d18",
3914 => x"00003d20",
3915 => x"00003d20",
3916 => x"00003d28",
3917 => x"00003d28",
3918 => x"00003d30",
3919 => x"00003d30",
3920 => x"00003d38",
3921 => x"00003d38",
3922 => x"00003d40",
3923 => x"00003d40",
3924 => x"00003d48",
3925 => x"00003d48",
3926 => x"00003d50",
3927 => x"00003d50",
3928 => x"00003d58",
3929 => x"00003d58",
3930 => x"00003d60",
3931 => x"00003d60",
3932 => x"00003d68",
3933 => x"00003d68",
3934 => x"00003d70",
3935 => x"00003d70",
3936 => x"00003d78",
3937 => x"00003d78",
3938 => x"00003d80",
3939 => x"00003d80",
3940 => x"00003d88",
3941 => x"00003d88",
3942 => x"00003d90",
3943 => x"00003d90",
3944 => x"00003d98",
3945 => x"00003d98",
3946 => x"00003da0",
3947 => x"00003da0",
3948 => x"00003da8",
3949 => x"00003da8",
3950 => x"00003db0",
3951 => x"00003db0",
3952 => x"00003db8",
3953 => x"00003db8",
3954 => x"00003dc0",
3955 => x"00003dc0",
3956 => x"00003dc8",
3957 => x"00003dc8",
3958 => x"00003dd0",
3959 => x"00003dd0",
3960 => x"00003dd8",
3961 => x"00003dd8",
3962 => x"00003de0",
3963 => x"00003de0",
3964 => x"00003de8",
3965 => x"00003de8",
3966 => x"00003df0",
3967 => x"00003df0",
3968 => x"00003df8",
3969 => x"00003df8",
3970 => x"00003e00",
3971 => x"00003e00",
3972 => x"00003e08",
3973 => x"00003e08",
3974 => x"00003e10",
3975 => x"00003e10",
3976 => x"00003e18",
3977 => x"00003e18",
3978 => x"00003e20",
3979 => x"00003e20",
3980 => x"00003e28",
3981 => x"00003e28",
3982 => x"00003e30",
3983 => x"00003e30",
3984 => x"00003e38",
3985 => x"00003e38",
3986 => x"00003e40",
3987 => x"00003e40",
3988 => x"00003e48",
3989 => x"00003e48",
3990 => x"00003e50",
3991 => x"00003e50",
3992 => x"00003e58",
3993 => x"00003e58",
3994 => x"00003e60",
3995 => x"00003e60",
3996 => x"00003e68",
3997 => x"00003e68",
3998 => x"00003e70",
3999 => x"00003e70",
4000 => x"00003e78",
4001 => x"00003e78",
4002 => x"00003e80",
4003 => x"00003e80",
4004 => x"00003e88",
4005 => x"00003e88",
4006 => x"00003e90",
4007 => x"00003e90",
4008 => x"00003e98",
4009 => x"00003e98",
4010 => x"00003ea0",
4011 => x"00003ea0",
4012 => x"00003ea8",
4013 => x"00003ea8",
4014 => x"00003eb0",
4015 => x"00003eb0",
4016 => x"00003eb8",
4017 => x"00003eb8",
4018 => x"00003ec0",
4019 => x"00003ec0",
4020 => x"00003ec8",
4021 => x"00003ec8",
4022 => x"00003ed0",
4023 => x"00003ed0",
4024 => x"00003ed8",
4025 => x"00003ed8",
4026 => x"00003ee0",
4027 => x"00003ee0",
4028 => x"00003ee8",
4029 => x"00003ee8",
4030 => x"00003ef0",
4031 => x"00003ef0",
4032 => x"00003ef8",
4033 => x"00003ef8",
4034 => x"00003f00",
4035 => x"00003f00",
4036 => x"00003f08",
4037 => x"00003f08",
4038 => x"00003f10",
4039 => x"00003f10",
4040 => x"00003f18",
4041 => x"00003f18",
4042 => x"00003f20",
4043 => x"00003f20",
4044 => x"00003f28",
4045 => x"00003f28",
4046 => x"00003f30",
4047 => x"00003f30",
4048 => x"00003f38",
4049 => x"00003f38",
4050 => x"00003f40",
4051 => x"00003f40",
4052 => x"00003f48",
4053 => x"00003f48",
4054 => x"00003f50",
4055 => x"00003f50",
4056 => x"00003f58",
4057 => x"00003f58",
4058 => x"00003f60",
4059 => x"00003f60",
4060 => x"00003f68",
4061 => x"00003f68",
4062 => x"00003f70",
4063 => x"00003f70",
4064 => x"00003f78",
4065 => x"00003f78",
4066 => x"00003f80",
4067 => x"00003f80",
4068 => x"00003f88",
4069 => x"00003f88",
4070 => x"00003f90",
4071 => x"00003f90",
4072 => x"00003f98",
4073 => x"00003f98",
4074 => x"00003fa0",
4075 => x"00003fa0",
4076 => x"00003fa8",
4077 => x"00003fa8",
4078 => x"00003fb0",
4079 => x"00003fb0",
4080 => x"00003fb8",
4081 => x"00003fb8",
4082 => x"00003fc0",
4083 => x"00003fc0",
4084 => x"00003fc8",
4085 => x"00003fc8",
4086 => x"00003fd0",
4087 => x"00003fd0",
4088 => x"00003fd8",
4089 => x"00003fd8",
4090 => x"00003fe0",
4091 => x"00003fe0",
4092 => x"00003fe8",
4093 => x"00003fe8",
4094 => x"00003ff0",
4095 => x"00003ff0",
4096 => x"00003ff8",
4097 => x"00003ff8",
4098 => x"00004000",
4099 => x"00004000",
4100 => x"00004008",
4101 => x"00004008",
4102 => x"00004010",
4103 => x"00004010",
4104 => x"00004018",
4105 => x"00004018",
4106 => x"00004020",
4107 => x"00004020",
4108 => x"00004028",
4109 => x"00004028",
4110 => x"00004030",
4111 => x"00004030",
4112 => x"00004038",
4113 => x"00004038",
4114 => x"00004040",
4115 => x"00004040",
4116 => x"00004048",
4117 => x"00004048",
4118 => x"00004050",
4119 => x"00004050",
4120 => x"00004058",
4121 => x"00004058",
4122 => x"00004060",
4123 => x"00004060",
4124 => x"00004068",
4125 => x"00004068",
4126 => x"00004070",
4127 => x"00004070",
4128 => x"00004078",
4129 => x"00004078",
4130 => x"00004080",
4131 => x"00004080",
4132 => x"00004088",
4133 => x"00004088",
4134 => x"00004090",
4135 => x"00004090",
4136 => x"00004098",
4137 => x"00004098",
4138 => x"000040a0",
4139 => x"000040a0",
4140 => x"000040a8",
4141 => x"000040a8",
4142 => x"000040b0",
4143 => x"000040b0",
4144 => x"000040b8",
4145 => x"000040b8",
4146 => x"000040cc",
4147 => x"00000000",
4148 => x"00004334",
4149 => x"00004390",
4150 => x"000043ec",
4151 => x"00000000",
4152 => x"00000000",
4153 => x"00000000",
4154 => x"00000000",
4155 => x"00000000",
4156 => x"00000000",
4157 => x"00000000",
4158 => x"00000000",
4159 => x"00000000",
4160 => x"00003c48",
4161 => x"00000000",
4162 => x"00000000",
4163 => x"00000000",
4164 => x"00000000",
4165 => x"00000000",
4166 => x"00000000",
4167 => x"00000000",
4168 => x"00000000",
4169 => x"00000000",
4170 => x"00000000",
4171 => x"00000000",
4172 => x"00000000",
4173 => x"00000000",
4174 => x"00000000",
4175 => x"00000000",
4176 => x"00000000",
4177 => x"00000000",
4178 => x"00000000",
4179 => x"00000000",
4180 => x"00000000",
4181 => x"00000000",
4182 => x"00000000",
4183 => x"00000000",
4184 => x"00000000",
4185 => x"00000000",
4186 => x"00000000",
4187 => x"00000000",
4188 => x"00000000",
4189 => x"00000001",
4190 => x"330eabcd",
4191 => x"1234e66d",
4192 => x"deec0005",
4193 => x"000b0000",
4194 => x"00000000",
4195 => x"00000000",
4196 => x"00000000",
4197 => x"00000000",
4198 => x"00000000",
4199 => x"00000000",
4200 => x"00000000",
4201 => x"00000000",
4202 => x"00000000",
4203 => x"00000000",
4204 => x"00000000",
4205 => x"00000000",
4206 => x"00000000",
4207 => x"00000000",
4208 => x"00000000",
4209 => x"00000000",
4210 => x"00000000",
4211 => x"00000000",
4212 => x"00000000",
4213 => x"00000000",
4214 => x"00000000",
4215 => x"00000000",
4216 => x"00000000",
4217 => x"00000000",
4218 => x"00000000",
4219 => x"00000000",
4220 => x"00000000",
4221 => x"00000000",
4222 => x"00000000",
4223 => x"00000000",
4224 => x"00000000",
4225 => x"00000000",
4226 => x"00000000",
4227 => x"00000000",
4228 => x"00000000",
4229 => x"00000000",
4230 => x"00000000",
4231 => x"00000000",
4232 => x"00000000",
4233 => x"00000000",
4234 => x"00000000",
4235 => x"00000000",
4236 => x"00000000",
4237 => x"00000000",
4238 => x"00000000",
4239 => x"00000000",
4240 => x"00000000",
4241 => x"00000000",
4242 => x"00000000",
4243 => x"00000000",
4244 => x"00000000",
4245 => x"00000000",
4246 => x"00000000",
4247 => x"00000000",
4248 => x"00000000",
4249 => x"00000000",
4250 => x"00000000",
4251 => x"00000000",
4252 => x"00000000",
4253 => x"00000000",
4254 => x"00000000",
4255 => x"00000000",
4256 => x"00000000",
4257 => x"00000000",
4258 => x"00000000",
4259 => x"00000000",
4260 => x"00000000",
4261 => x"00000000",
4262 => x"00000000",
4263 => x"00000000",
4264 => x"00000000",
4265 => x"00000000",
4266 => x"00000000",
4267 => x"00000000",
4268 => x"00000000",
4269 => x"00000000",
4270 => x"00000000",
4271 => x"00000000",
4272 => x"00000000",
4273 => x"00000000",
4274 => x"00000000",
4275 => x"00000000",
4276 => x"00000000",
4277 => x"00000000",
4278 => x"00000000",
4279 => x"00000000",
4280 => x"00000000",
4281 => x"00000000",
4282 => x"00000000",
4283 => x"00000000",
4284 => x"00000000",
4285 => x"00000000",
4286 => x"00000000",
4287 => x"00000000",
4288 => x"00000000",
4289 => x"00000000",
4290 => x"00000000",
4291 => x"00000000",
4292 => x"00000000",
4293 => x"00000000",
4294 => x"00000000",
4295 => x"00000000",
4296 => x"00000000",
4297 => x"00000000",
4298 => x"00000000",
4299 => x"00000000",
4300 => x"00000000",
4301 => x"00000000",
4302 => x"00000000",
4303 => x"00000000",
4304 => x"00000000",
4305 => x"00000000",
4306 => x"00000000",
4307 => x"00000000",
4308 => x"00000000",
4309 => x"00000000",
4310 => x"00000000",
4311 => x"00000000",
4312 => x"00000000",
4313 => x"00000000",
4314 => x"00000000",
4315 => x"00000000",
4316 => x"00000000",
4317 => x"00000000",
4318 => x"00000000",
4319 => x"00000000",
4320 => x"00000000",
4321 => x"00000000",
4322 => x"00000000",
4323 => x"00000000",
4324 => x"00000000",
4325 => x"00000000",
4326 => x"00000000",
4327 => x"00000000",
4328 => x"00000000",
4329 => x"00000000",
4330 => x"00000000",
4331 => x"00000000",
4332 => x"00000000",
4333 => x"00000000",
4334 => x"00000000",
4335 => x"00000000",
4336 => x"00000000",
4337 => x"00000000",
4338 => x"00000000",
4339 => x"00000000",
4340 => x"00000000",
4341 => x"00000000",
4342 => x"00000000",
4343 => x"00000000",
4344 => x"00000000",
4345 => x"00000000",
4346 => x"00000000",
4347 => x"00000000",
4348 => x"00000000",
4349 => x"00000000",
4350 => x"00000000",
4351 => x"00000000",
4352 => x"00000000",
4353 => x"00000000",
4354 => x"00000000",
4355 => x"00000000",
4356 => x"00000000",
4357 => x"00000000",
4358 => x"00000000",
4359 => x"00000000",
4360 => x"00000000",
4361 => x"00000000",
4362 => x"00000000",
4363 => x"00000000",
4364 => x"00000000",
4365 => x"00000000",
4366 => x"00000000",
4367 => x"00000000",
4368 => x"00000000",
4369 => x"00000000",
4370 => x"00003c4c",
4371 => x"ffffffff",
4372 => x"00000000",
4373 => x"ffffffff",
4374 => x"00000000",
4375 => x"00000000",
others => x"00000000"
);
begin
do_port_a:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
report "DualPortRAM write collision" severity failure;
end if;
iaddr:=to_integer(a_addr_i);
if a_we_i='1' then
ram(iaddr):=a_write_i;
-- Write First mode
a_read_o <= a_write_i;
else
a_read_o <= ram(iaddr);
end if;
end if;
end process do_port_a;
do_port_b:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
iaddr:=to_integer(b_addr_i);
if b_we_i='1' then
ram(iaddr):=b_write_i;
b_read_o <= b_write_i;
else
b_read_o <= ram(iaddr);
end if;
end if;
end process do_port_b;
end architecture Xilinx; -- Entity: DualPortRAM
| bsd-3-clause | 6d434d8b6358653e1c5ec1f59415e478 | 0.543314 | 2.292787 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/cpu/T80sed.vhd | 2 | 5,503 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 8a3d74a1a1f2adc5a8d9e53148903d54 | 0.581319 | 3.262004 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/Loop_sum_loop_proc.vhd | 4 | 29,010 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_sum_loop_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Loop_sum_loop_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (37 downto 0) := "00000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (37 downto 0) := "00000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (37 downto 0) := "00000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (37 downto 0) := "00000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (37 downto 0) := "00000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (37 downto 0) := "00000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (37 downto 0) := "00001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (37 downto 0) := "00010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (37 downto 0) := "00100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (37 downto 0) := "01000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (37 downto 0) := "10000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal tmp_5_i_fu_122_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_i_reg_157 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_i_fu_116_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_130_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_163 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_power_fu_81_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_power_fu_81_ap_done : STD_LOGIC;
signal grp_fact_fu_70_ap_done : STD_LOGIC;
signal grp_power_fu_88_ap_done : STD_LOGIC;
signal grp_fact_fu_76_ap_done : STD_LOGIC;
signal ap_block_state3_on_subcall_done : BOOLEAN;
signal grp_fact_fu_70_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_power_fu_88_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fact_fu_76_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_104_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_i_reg_188 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal grp_fu_110_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_i_reg_193 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_94_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state38 : signal is "none";
signal grp_fu_99_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fact_fu_70_ap_start : STD_LOGIC;
signal grp_fact_fu_70_ap_idle : STD_LOGIC;
signal grp_fact_fu_70_ap_ready : STD_LOGIC;
signal grp_fact_fu_76_ap_start : STD_LOGIC;
signal grp_fact_fu_76_ap_idle : STD_LOGIC;
signal grp_fact_fu_76_ap_ready : STD_LOGIC;
signal grp_power_fu_81_ap_start : STD_LOGIC;
signal grp_power_fu_81_ap_idle : STD_LOGIC;
signal grp_power_fu_81_ap_ready : STD_LOGIC;
signal grp_power_fu_88_ap_start : STD_LOGIC;
signal grp_power_fu_88_ap_idle : STD_LOGIC;
signal grp_power_fu_88_ap_ready : STD_LOGIC;
signal sum_positive_0_loc_l_reg_34 : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_reg_46 : STD_LOGIC_VECTOR (63 downto 0);
signal i_0_i_i_reg_58 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_grp_fact_fu_70_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_fact_fu_76_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_power_fu_81_ap_start : STD_LOGIC := '0';
signal ap_reg_grp_power_fu_88_ap_start : STD_LOGIC := '0';
signal ap_CS_fsm_state34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
signal grp_fu_104_ce : STD_LOGIC;
signal ap_CS_fsm_state35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
signal ap_CS_fsm_state36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal ap_CS_fsm_state37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
signal grp_fu_110_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (37 downto 0);
component fact IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component power IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
y : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_seriesdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component sin_taylor_serieseOg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
grp_fact_fu_70 : component fact
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_fact_fu_70_ap_start,
ap_done => grp_fact_fu_70_ap_done,
ap_idle => grp_fact_fu_70_ap_idle,
ap_ready => grp_fact_fu_70_ap_ready,
x => i_0_i_i_reg_58,
ap_return => grp_fact_fu_70_ap_return);
grp_fact_fu_76 : component fact
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_fact_fu_76_ap_start,
ap_done => grp_fact_fu_76_ap_done,
ap_idle => grp_fact_fu_76_ap_idle,
ap_ready => grp_fact_fu_76_ap_ready,
x => tmp_5_i_reg_157,
ap_return => grp_fact_fu_76_ap_return);
grp_power_fu_81 : component power
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_power_fu_81_ap_start,
ap_done => grp_power_fu_81_ap_done,
ap_idle => grp_power_fu_81_ap_idle,
ap_ready => grp_power_fu_81_ap_ready,
x => x,
y => i_0_i_i_reg_58,
ap_return => grp_power_fu_81_ap_return);
grp_power_fu_88 : component power
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_power_fu_88_ap_start,
ap_done => grp_power_fu_88_ap_done,
ap_idle => grp_power_fu_88_ap_idle,
ap_ready => grp_power_fu_88_ap_ready,
x => x,
y => tmp_5_i_reg_157,
ap_return => grp_power_fu_88_ap_return);
sin_taylor_seriesdEe_U7 : component sin_taylor_seriesdEe
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => sum_positive_0_loc_l_reg_34,
din1 => tmp_3_i_reg_188,
ce => ap_const_logic_1,
dout => grp_fu_94_p2);
sin_taylor_seriesdEe_U8 : component sin_taylor_seriesdEe
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => sum_negative_0_loc_l_reg_46,
din1 => tmp_8_i_reg_193,
ce => ap_const_logic_1,
dout => grp_fu_99_p2);
sin_taylor_serieseOg_U9 : component sin_taylor_serieseOg
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_power_fu_81_ap_return,
din1 => grp_fact_fu_70_ap_return,
ce => grp_fu_104_ce,
dout => grp_fu_104_p2);
sin_taylor_serieseOg_U10 : component sin_taylor_serieseOg
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_power_fu_88_ap_return,
din1 => grp_fact_fu_76_ap_return,
ce => grp_fu_110_ce,
dout => grp_fu_110_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_grp_fact_fu_70_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_fact_fu_70_ap_ready)) then
ap_reg_grp_fact_fu_70_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_fact_fu_76_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_fact_fu_76_ap_ready)) then
ap_reg_grp_fact_fu_76_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_power_fu_81_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_power_fu_81_ap_ready)) then
ap_reg_grp_power_fu_81_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_power_fu_88_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_power_fu_88_ap_ready)) then
ap_reg_grp_power_fu_88_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_0_i_i_reg_58_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
i_0_i_i_reg_58 <= i_reg_163;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
i_0_i_i_reg_58 <= ap_const_lv5_1;
end if;
end if;
end process;
sum_negative_0_loc_l_reg_46_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
sum_negative_0_loc_l_reg_46 <= grp_fu_99_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
sum_negative_0_loc_l_reg_46 <= ap_const_lv64_0;
end if;
end if;
end process;
sum_positive_0_loc_l_reg_34_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
sum_positive_0_loc_l_reg_34 <= grp_fu_94_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
sum_positive_0_loc_l_reg_34 <= ap_const_lv64_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_1))) then
i_reg_163 <= i_fu_130_p2;
tmp_5_i_reg_157 <= tmp_5_i_fu_122_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
tmp_3_i_reg_188 <= grp_fu_104_p2;
tmp_8_i_reg_193 <= grp_fu_110_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_i_fu_116_p2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_block_state3_on_subcall_done = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state34 <= ap_CS_fsm(33);
ap_CS_fsm_state35 <= ap_CS_fsm(34);
ap_CS_fsm_state36 <= ap_CS_fsm(35);
ap_CS_fsm_state37 <= ap_CS_fsm(36);
ap_CS_fsm_state38 <= ap_CS_fsm(37);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_on_subcall_done_assign_proc : process(grp_power_fu_81_ap_done, grp_fact_fu_70_ap_done, grp_power_fu_88_ap_done, grp_fact_fu_76_ap_done)
begin
ap_block_state3_on_subcall_done <= ((ap_const_logic_0 = grp_power_fu_81_ap_done) or (ap_const_logic_0 = grp_fact_fu_70_ap_done) or (ap_const_logic_0 = grp_power_fu_88_ap_done) or (ap_const_logic_0 = grp_fact_fu_76_ap_done));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state2, tmp_i_fu_116_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_i_fu_116_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_116_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_0 <= sum_positive_0_loc_l_reg_34;
ap_return_1 <= sum_negative_0_loc_l_reg_46;
grp_fact_fu_70_ap_start <= ap_reg_grp_fact_fu_70_ap_start;
grp_fact_fu_76_ap_start <= ap_reg_grp_fact_fu_76_ap_start;
grp_fu_104_ce_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done, ap_CS_fsm_state38, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state34) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_boolean_1 = ap_block_state3_on_subcall_done)) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state37))) then
grp_fu_104_ce <= ap_const_logic_0;
else
grp_fu_104_ce <= ap_const_logic_1;
end if;
end process;
grp_fu_110_ce_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_block_state3_on_subcall_done, ap_CS_fsm_state38, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state34) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_boolean_1 = ap_block_state3_on_subcall_done)) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state37))) then
grp_fu_110_ce <= ap_const_logic_0;
else
grp_fu_110_ce <= ap_const_logic_1;
end if;
end process;
grp_power_fu_81_ap_start <= ap_reg_grp_power_fu_81_ap_start;
grp_power_fu_88_ap_start <= ap_reg_grp_power_fu_88_ap_start;
i_fu_130_p2 <= std_logic_vector(unsigned(i_0_i_i_reg_58) + unsigned(ap_const_lv5_4));
tmp_5_i_fu_122_p2 <= std_logic_vector(unsigned(i_0_i_i_reg_58) + unsigned(ap_const_lv5_2));
tmp_i_fu_116_p2 <= "1" when (unsigned(i_0_i_i_reg_58) < unsigned(ap_const_lv5_15)) else "0";
end behav;
| mit | 0d80a73015ae7d998b2cebffd20dc36c | 0.583454 | 3.098035 | false | false | false | false |
APastorG/APG | pipelines/pipelines_u.vhd | 1 | 2,173 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines_u is
generic(
LENGTH : natural
);
port(
clk : in std_ulogic;
input : in u_ufixed;
output : out u_ufixed
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_u_1 of pipelines_u is
signal input_aux : std_ulogic_vector(input'length-1 downto 0);
signal output_aux : std_ulogic_vector(input'length-1 downto 0);
begin
pipelines_core_1:
entity work.pipelines_core
generic map(
LENGTH => LENGTH,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input_aux,
output => output_aux
);
output <= to_ufixed(output_aux, input'high, input'low);
input_aux <= std_ulogic_vector(input);
end architecture; | mit | 48dbd7ff146ffb1671e3486c99c5f78c | 0.364189 | 4.774554 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/simulation/bmg_stim_gen.vhd | 1 | 15,700 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(16,16);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(4096,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(11 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(11 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH => 16,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH =>16 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 | a01a54aa66ad486490e4aabf85a8faaf | 0.57535 | 3.21392 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/int_test.vhdl | 1 | 68,352 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80d0f80c",
3 => x"3a0b0b80",
4 => x"c8d40400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80d0",
162 => x"94738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"0b0b0b88",
169 => x"f8040000",
170 => x"00000000",
171 => x"00000000",
172 => x"00000000",
173 => x"00000000",
174 => x"00000000",
175 => x"00000000",
176 => x"0b0b0b88",
177 => x"e0040000",
178 => x"00000000",
179 => x"00000000",
180 => x"00000000",
181 => x"00000000",
182 => x"00000000",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80d0f40c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83853f80",
257 => x"c7e23f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"b008b408",
281 => x"b8087575",
282 => x"90822d50",
283 => x"50b00856",
284 => x"b80cb40c",
285 => x"b00c5104",
286 => x"b008b408",
287 => x"b8087575",
288 => x"8ed02d50",
289 => x"50b00856",
290 => x"b80cb40c",
291 => x"b00c5104",
292 => x"b008b408",
293 => x"b8088bb6",
294 => x"2db80cb4",
295 => x"0cb00c04",
296 => x"fe3d0d0b",
297 => x"0b80e0e4",
298 => x"08538413",
299 => x"0870882a",
300 => x"70810651",
301 => x"52527080",
302 => x"2ef03871",
303 => x"81ff06b0",
304 => x"0c843d0d",
305 => x"04ff3d0d",
306 => x"0b0b80e0",
307 => x"e4085271",
308 => x"0870882a",
309 => x"81327081",
310 => x"06515151",
311 => x"70f13873",
312 => x"720c833d",
313 => x"0d0480d0",
314 => x"f408802e",
315 => x"a43880d0",
316 => x"f808822e",
317 => x"bd388380",
318 => x"800b0b0b",
319 => x"80e0e40c",
320 => x"82a0800b",
321 => x"80e0e80c",
322 => x"8290800b",
323 => x"80e0ec0c",
324 => x"04f88080",
325 => x"80a40b0b",
326 => x"0b80e0e4",
327 => x"0cf88080",
328 => x"82800b80",
329 => x"e0e80cf8",
330 => x"80808480",
331 => x"0b80e0ec",
332 => x"0c0480c0",
333 => x"a8808c0b",
334 => x"0b0b80e0",
335 => x"e40c80c0",
336 => x"a880940b",
337 => x"80e0e80c",
338 => x"80d0a40b",
339 => x"80e0ec0c",
340 => x"04ff3d0d",
341 => x"80e0f033",
342 => x"5170a738",
343 => x"80d18008",
344 => x"70085252",
345 => x"70802e94",
346 => x"38841280",
347 => x"d1800c70",
348 => x"2d80d180",
349 => x"08700852",
350 => x"5270ee38",
351 => x"810b80e0",
352 => x"f034833d",
353 => x"0d040480",
354 => x"3d0d0b0b",
355 => x"80e0e008",
356 => x"802e8e38",
357 => x"0b0b0b0b",
358 => x"800b802e",
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2402 => x"8c3d0d04",
2403 => x"771a568a",
2404 => x"76348118",
2405 => x"588d51ff",
2406 => x"beab3f8a",
2407 => x"51ffbea5",
2408 => x"3f7756ff",
2409 => x"be39fb3d",
2410 => x"0d80e0f8",
2411 => x"08705654",
2412 => x"73883874",
2413 => x"b00c873d",
2414 => x"0d047753",
2415 => x"8352873d",
2416 => x"fc0551ff",
2417 => x"bcfc3fb0",
2418 => x"085482f1",
2419 => x"3f75b008",
2420 => x"0c73b00c",
2421 => x"873d0d04",
2422 => x"fa3d0d80",
2423 => x"e0f80880",
2424 => x"2ea3387a",
2425 => x"55795478",
2426 => x"53865288",
2427 => x"3dfc0551",
2428 => x"ffbccf3f",
2429 => x"b0085682",
2430 => x"c43f76b0",
2431 => x"080c75b0",
2432 => x"0c883d0d",
2433 => x"0482b63f",
2434 => x"9d0bb008",
2435 => x"0cff0bb0",
2436 => x"0c883d0d",
2437 => x"04fb3d0d",
2438 => x"77795656",
2439 => x"80705454",
2440 => x"7375259f",
2441 => x"38741010",
2442 => x"10f80552",
2443 => x"72167033",
2444 => x"70742b76",
2445 => x"078116f8",
2446 => x"16565656",
2447 => x"51517473",
2448 => x"24ea3873",
2449 => x"b00c873d",
2450 => x"0d04fc3d",
2451 => x"0d767855",
2452 => x"55bc5380",
2453 => x"527351f5",
2454 => x"be3f8452",
2455 => x"7451ffb5",
2456 => x"3fb00874",
2457 => x"23845284",
2458 => x"1551ffa9",
2459 => x"3fb00882",
2460 => x"15238452",
2461 => x"881551ff",
2462 => x"9c3fb008",
2463 => x"84150c84",
2464 => x"528c1551",
2465 => x"ff8f3fb0",
2466 => x"08881523",
2467 => x"84529015",
2468 => x"51ff823f",
2469 => x"b0088a15",
2470 => x"23845294",
2471 => x"1551fef5",
2472 => x"3fb0088c",
2473 => x"15238452",
2474 => x"981551fe",
2475 => x"e83fb008",
2476 => x"8e152388",
2477 => x"529c1551",
2478 => x"fedb3fb0",
2479 => x"0890150c",
2480 => x"863d0d04",
2481 => x"e93d0d6a",
2482 => x"80e0f808",
2483 => x"57577593",
2484 => x"3880c080",
2485 => x"0b84180c",
2486 => x"75ac180c",
2487 => x"75b00c99",
2488 => x"3d0d0489",
2489 => x"3d70556a",
2490 => x"54558a52",
2491 => x"993dffbc",
2492 => x"0551ffba",
2493 => x"cd3fb008",
2494 => x"77537552",
2495 => x"56fecb3f",
2496 => x"bc3f77b0",
2497 => x"080c75b0",
2498 => x"0c993d0d",
2499 => x"04fc3d0d",
2500 => x"815480e0",
2501 => x"f8088838",
2502 => x"73b00c86",
2503 => x"3d0d0476",
2504 => x"5397b952",
2505 => x"863dfc05",
2506 => x"51ffba96",
2507 => x"3fb00854",
2508 => x"8c3f74b0",
2509 => x"080c73b0",
2510 => x"0c863d0d",
2511 => x"0480d188",
2512 => x"08b00c04",
2513 => x"f73d0d7b",
2514 => x"80d18808",
2515 => x"82c81108",
2516 => x"5a545a77",
2517 => x"802e80da",
2518 => x"38818818",
2519 => x"841908ff",
2520 => x"0581712b",
2521 => x"59555980",
2522 => x"742480ea",
2523 => x"38807424",
2524 => x"b5387382",
2525 => x"2b781188",
2526 => x"05565681",
2527 => x"80190877",
2528 => x"06537280",
2529 => x"2eb63878",
2530 => x"16700853",
2531 => x"53795174",
2532 => x"0853722d",
2533 => x"ff14fc17",
2534 => x"fc177981",
2535 => x"2c5a5757",
2536 => x"54738025",
2537 => x"d6387708",
2538 => x"5877ffad",
2539 => x"3880d188",
2540 => x"0853bc13",
2541 => x"08a53879",
2542 => x"51f9df3f",
2543 => x"74085372",
2544 => x"2dff14fc",
2545 => x"17fc1779",
2546 => x"812c5a57",
2547 => x"57547380",
2548 => x"25ffa838",
2549 => x"d1398057",
2550 => x"ff933972",
2551 => x"51bc1308",
2552 => x"53722d79",
2553 => x"51f9b33f",
2554 => x"ff3d0d80",
2555 => x"e0d40bfc",
2556 => x"05700852",
2557 => x"5270ff2e",
2558 => x"9138702d",
2559 => x"fc127008",
2560 => x"525270ff",
2561 => x"2e098106",
2562 => x"f138833d",
2563 => x"0d0404ff",
2564 => x"babf3f04",
2565 => x"00ffffff",
2566 => x"ff00ffff",
2567 => x"ffff00ff",
2568 => x"ffffff00",
2569 => x"00000040",
2570 => x"30313233",
2571 => x"34353637",
2572 => x"38396162",
2573 => x"63646566",
2574 => x"00000000",
2575 => x"476f7420",
2576 => x"696e7465",
2577 => x"72727570",
2578 => x"740a0000",
2579 => x"633a0000",
2580 => x"733a0000",
2581 => x"4e6f2069",
2582 => x"6e746572",
2583 => x"72757074",
2584 => x"0a000000",
2585 => x"43000000",
2586 => x"64756d6d",
2587 => x"792e6578",
2588 => x"65000000",
2589 => x"00000000",
2590 => x"00000000",
2591 => x"00000000",
2592 => x"0000305c",
2593 => x"00002828",
2594 => x"0000288c",
2595 => x"00000000",
2596 => x"00002af4",
2597 => x"00002b50",
2598 => x"00002bac",
2599 => x"00000000",
2600 => x"00000000",
2601 => x"00000000",
2602 => x"00000000",
2603 => x"00000000",
2604 => x"00000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"00002864",
2609 => x"00000000",
2610 => x"00000000",
2611 => x"00000000",
2612 => x"00000000",
2613 => x"00000000",
2614 => x"00000000",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"00000000",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000001",
2638 => x"330eabcd",
2639 => x"1234e66d",
2640 => x"deec0005",
2641 => x"000b0000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000000",
2654 => x"00000000",
2655 => x"00000000",
2656 => x"00000000",
2657 => x"00000000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"00000000",
2704 => x"00000000",
2705 => x"00000000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00000000",
2709 => x"00000000",
2710 => x"00000000",
2711 => x"00000000",
2712 => x"00000000",
2713 => x"00000000",
2714 => x"00000000",
2715 => x"00000000",
2716 => x"00000000",
2717 => x"00000000",
2718 => x"00000000",
2719 => x"00000000",
2720 => x"00000000",
2721 => x"00000000",
2722 => x"00000000",
2723 => x"00000000",
2724 => x"00000000",
2725 => x"00000000",
2726 => x"00000000",
2727 => x"00000000",
2728 => x"00000000",
2729 => x"00000000",
2730 => x"00000000",
2731 => x"00000000",
2732 => x"00000000",
2733 => x"00000000",
2734 => x"00000000",
2735 => x"00000000",
2736 => x"00000000",
2737 => x"00000000",
2738 => x"00000000",
2739 => x"00000000",
2740 => x"00000000",
2741 => x"00000000",
2742 => x"00000000",
2743 => x"00000000",
2744 => x"00000000",
2745 => x"00000000",
2746 => x"00000000",
2747 => x"00000000",
2748 => x"00000000",
2749 => x"00000000",
2750 => x"00000000",
2751 => x"00000000",
2752 => x"00000000",
2753 => x"00000000",
2754 => x"00000000",
2755 => x"00000000",
2756 => x"00000000",
2757 => x"00000000",
2758 => x"00000000",
2759 => x"00000000",
2760 => x"00000000",
2761 => x"00000000",
2762 => x"00000000",
2763 => x"00000000",
2764 => x"00000000",
2765 => x"00000000",
2766 => x"00000000",
2767 => x"00000000",
2768 => x"00000000",
2769 => x"00000000",
2770 => x"00000000",
2771 => x"00000000",
2772 => x"00000000",
2773 => x"00000000",
2774 => x"00000000",
2775 => x"00000000",
2776 => x"00000000",
2777 => x"00000000",
2778 => x"00000000",
2779 => x"00000000",
2780 => x"00000000",
2781 => x"00000000",
2782 => x"00000000",
2783 => x"00000000",
2784 => x"00000000",
2785 => x"00000000",
2786 => x"00000000",
2787 => x"00000000",
2788 => x"00000000",
2789 => x"00000000",
2790 => x"00000000",
2791 => x"00000000",
2792 => x"00000000",
2793 => x"00000000",
2794 => x"00000000",
2795 => x"00000000",
2796 => x"00000000",
2797 => x"00000000",
2798 => x"00000000",
2799 => x"00000000",
2800 => x"00000000",
2801 => x"00000000",
2802 => x"00000000",
2803 => x"00000000",
2804 => x"00000000",
2805 => x"00000000",
2806 => x"00000000",
2807 => x"00000000",
2808 => x"00000000",
2809 => x"00000000",
2810 => x"00000000",
2811 => x"00000000",
2812 => x"00000000",
2813 => x"00000000",
2814 => x"00000000",
2815 => x"00000000",
2816 => x"00000000",
2817 => x"00000000",
2818 => x"00000000",
2819 => x"00000000",
2820 => x"00000000",
2821 => x"00000000",
2822 => x"00000000",
2823 => x"00000000",
2824 => x"00000000",
2825 => x"00000000",
2826 => x"00000000",
2827 => x"00000000",
2828 => x"00000000",
2829 => x"00000000",
2830 => x"ffffffff",
2831 => x"00000000",
2832 => x"00020000",
2833 => x"00000000",
2834 => x"00000000",
2835 => x"00002c44",
2836 => x"00002c44",
2837 => x"00002c4c",
2838 => x"00002c4c",
2839 => x"00002c54",
2840 => x"00002c54",
2841 => x"00002c5c",
2842 => x"00002c5c",
2843 => x"00002c64",
2844 => x"00002c64",
2845 => x"00002c6c",
2846 => x"00002c6c",
2847 => x"00002c74",
2848 => x"00002c74",
2849 => x"00002c7c",
2850 => x"00002c7c",
2851 => x"00002c84",
2852 => x"00002c84",
2853 => x"00002c8c",
2854 => x"00002c8c",
2855 => x"00002c94",
2856 => x"00002c94",
2857 => x"00002c9c",
2858 => x"00002c9c",
2859 => x"00002ca4",
2860 => x"00002ca4",
2861 => x"00002cac",
2862 => x"00002cac",
2863 => x"00002cb4",
2864 => x"00002cb4",
2865 => x"00002cbc",
2866 => x"00002cbc",
2867 => x"00002cc4",
2868 => x"00002cc4",
2869 => x"00002ccc",
2870 => x"00002ccc",
2871 => x"00002cd4",
2872 => x"00002cd4",
2873 => x"00002cdc",
2874 => x"00002cdc",
2875 => x"00002ce4",
2876 => x"00002ce4",
2877 => x"00002cec",
2878 => x"00002cec",
2879 => x"00002cf4",
2880 => x"00002cf4",
2881 => x"00002cfc",
2882 => x"00002cfc",
2883 => x"00002d04",
2884 => x"00002d04",
2885 => x"00002d0c",
2886 => x"00002d0c",
2887 => x"00002d14",
2888 => x"00002d14",
2889 => x"00002d1c",
2890 => x"00002d1c",
2891 => x"00002d24",
2892 => x"00002d24",
2893 => x"00002d2c",
2894 => x"00002d2c",
2895 => x"00002d34",
2896 => x"00002d34",
2897 => x"00002d3c",
2898 => x"00002d3c",
2899 => x"00002d44",
2900 => x"00002d44",
2901 => x"00002d4c",
2902 => x"00002d4c",
2903 => x"00002d54",
2904 => x"00002d54",
2905 => x"00002d5c",
2906 => x"00002d5c",
2907 => x"00002d64",
2908 => x"00002d64",
2909 => x"00002d6c",
2910 => x"00002d6c",
2911 => x"00002d74",
2912 => x"00002d74",
2913 => x"00002d7c",
2914 => x"00002d7c",
2915 => x"00002d84",
2916 => x"00002d84",
2917 => x"00002d8c",
2918 => x"00002d8c",
2919 => x"00002d94",
2920 => x"00002d94",
2921 => x"00002d9c",
2922 => x"00002d9c",
2923 => x"00002da4",
2924 => x"00002da4",
2925 => x"00002dac",
2926 => x"00002dac",
2927 => x"00002db4",
2928 => x"00002db4",
2929 => x"00002dbc",
2930 => x"00002dbc",
2931 => x"00002dc4",
2932 => x"00002dc4",
2933 => x"00002dcc",
2934 => x"00002dcc",
2935 => x"00002dd4",
2936 => x"00002dd4",
2937 => x"00002ddc",
2938 => x"00002ddc",
2939 => x"00002de4",
2940 => x"00002de4",
2941 => x"00002dec",
2942 => x"00002dec",
2943 => x"00002df4",
2944 => x"00002df4",
2945 => x"00002dfc",
2946 => x"00002dfc",
2947 => x"00002e04",
2948 => x"00002e04",
2949 => x"00002e0c",
2950 => x"00002e0c",
2951 => x"00002e14",
2952 => x"00002e14",
2953 => x"00002e1c",
2954 => x"00002e1c",
2955 => x"00002e24",
2956 => x"00002e24",
2957 => x"00002e2c",
2958 => x"00002e2c",
2959 => x"00002e34",
2960 => x"00002e34",
2961 => x"00002e3c",
2962 => x"00002e3c",
2963 => x"00002e44",
2964 => x"00002e44",
2965 => x"00002e4c",
2966 => x"00002e4c",
2967 => x"00002e54",
2968 => x"00002e54",
2969 => x"00002e5c",
2970 => x"00002e5c",
2971 => x"00002e64",
2972 => x"00002e64",
2973 => x"00002e6c",
2974 => x"00002e6c",
2975 => x"00002e74",
2976 => x"00002e74",
2977 => x"00002e7c",
2978 => x"00002e7c",
2979 => x"00002e84",
2980 => x"00002e84",
2981 => x"00002e8c",
2982 => x"00002e8c",
2983 => x"00002e94",
2984 => x"00002e94",
2985 => x"00002e9c",
2986 => x"00002e9c",
2987 => x"00002ea4",
2988 => x"00002ea4",
2989 => x"00002eac",
2990 => x"00002eac",
2991 => x"00002eb4",
2992 => x"00002eb4",
2993 => x"00002ebc",
2994 => x"00002ebc",
2995 => x"00002ec4",
2996 => x"00002ec4",
2997 => x"00002ecc",
2998 => x"00002ecc",
2999 => x"00002ed4",
3000 => x"00002ed4",
3001 => x"00002edc",
3002 => x"00002edc",
3003 => x"00002ee4",
3004 => x"00002ee4",
3005 => x"00002eec",
3006 => x"00002eec",
3007 => x"00002ef4",
3008 => x"00002ef4",
3009 => x"00002efc",
3010 => x"00002efc",
3011 => x"00002f04",
3012 => x"00002f04",
3013 => x"00002f0c",
3014 => x"00002f0c",
3015 => x"00002f14",
3016 => x"00002f14",
3017 => x"00002f1c",
3018 => x"00002f1c",
3019 => x"00002f24",
3020 => x"00002f24",
3021 => x"00002f2c",
3022 => x"00002f2c",
3023 => x"00002f34",
3024 => x"00002f34",
3025 => x"00002f3c",
3026 => x"00002f3c",
3027 => x"00002f44",
3028 => x"00002f44",
3029 => x"00002f4c",
3030 => x"00002f4c",
3031 => x"00002f54",
3032 => x"00002f54",
3033 => x"00002f5c",
3034 => x"00002f5c",
3035 => x"00002f64",
3036 => x"00002f64",
3037 => x"00002f6c",
3038 => x"00002f6c",
3039 => x"00002f74",
3040 => x"00002f74",
3041 => x"00002f7c",
3042 => x"00002f7c",
3043 => x"00002f84",
3044 => x"00002f84",
3045 => x"00002f8c",
3046 => x"00002f8c",
3047 => x"00002f94",
3048 => x"00002f94",
3049 => x"00002f9c",
3050 => x"00002f9c",
3051 => x"00002fa4",
3052 => x"00002fa4",
3053 => x"00002fac",
3054 => x"00002fac",
3055 => x"00002fb4",
3056 => x"00002fb4",
3057 => x"00002fbc",
3058 => x"00002fbc",
3059 => x"00002fc4",
3060 => x"00002fc4",
3061 => x"00002fcc",
3062 => x"00002fcc",
3063 => x"00002fd4",
3064 => x"00002fd4",
3065 => x"00002fdc",
3066 => x"00002fdc",
3067 => x"00002fe4",
3068 => x"00002fe4",
3069 => x"00002fec",
3070 => x"00002fec",
3071 => x"00002ff4",
3072 => x"00002ff4",
3073 => x"00002ffc",
3074 => x"00002ffc",
3075 => x"00003004",
3076 => x"00003004",
3077 => x"0000300c",
3078 => x"0000300c",
3079 => x"00003014",
3080 => x"00003014",
3081 => x"0000301c",
3082 => x"0000301c",
3083 => x"00003024",
3084 => x"00003024",
3085 => x"0000302c",
3086 => x"0000302c",
3087 => x"00003034",
3088 => x"00003034",
3089 => x"0000303c",
3090 => x"0000303c",
3091 => x"00002868",
3092 => x"ffffffff",
3093 => x"00000000",
3094 => x"ffffffff",
3095 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | 2d567e03e35364bee547a4c6fb8a393f | 0.592843 | 2.272643 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/zwc_int_test.vhdl | 1 | 67,575 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cfe40c",
3 => x"3a0b0b80",
4 => x"c7ba0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80ce",
162 => x"f4738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"0b0b0b88",
169 => x"f8040000",
170 => x"00000000",
171 => x"00000000",
172 => x"00000000",
173 => x"00000000",
174 => x"00000000",
175 => x"00000000",
176 => x"0b0b0b88",
177 => x"e0040000",
178 => x"00000000",
179 => x"00000000",
180 => x"00000000",
181 => x"00000000",
182 => x"00000000",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80cfe00c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83853f80",
257 => x"c6c03f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"b008b408",
281 => x"b8087575",
282 => x"8ee82d50",
283 => x"50b00856",
284 => x"b80cb40c",
285 => x"b00c5104",
286 => x"b008b408",
287 => x"b8087575",
288 => x"8db62d50",
289 => x"50b00856",
290 => x"b80cb40c",
291 => x"b00c5104",
292 => x"b008b408",
293 => x"b8088bb6",
294 => x"2db80cb4",
295 => x"0cb00c04",
296 => x"fe3d0d0b",
297 => x"0b80dfd0",
298 => x"08538413",
299 => x"0870882a",
300 => x"70810651",
301 => x"52527080",
302 => x"2ef03871",
303 => x"81ff06b0",
304 => x"0c843d0d",
305 => x"04ff3d0d",
306 => x"0b0b80df",
307 => x"d0085271",
308 => x"0870882a",
309 => x"81327081",
310 => x"06515151",
311 => x"70f13873",
312 => x"720c833d",
313 => x"0d0480cf",
314 => x"e008802e",
315 => x"a43880cf",
316 => x"e408822e",
317 => x"bd388380",
318 => x"800b0b0b",
319 => x"80dfd00c",
320 => x"82a0800b",
321 => x"80dfd40c",
322 => x"8290800b",
323 => x"80dfd80c",
324 => x"04f88080",
325 => x"80a40b0b",
326 => x"0b80dfd0",
327 => x"0cf88080",
328 => x"82800b80",
329 => x"dfd40cf8",
330 => x"80808480",
331 => x"0b80dfd8",
332 => x"0c0480c0",
333 => x"a8808c0b",
334 => x"0b0b80df",
335 => x"d00c80c0",
336 => x"a880940b",
337 => x"80dfd40c",
338 => x"80cf840b",
339 => x"80dfd80c",
340 => x"04ff3d0d",
341 => x"80dfdc33",
342 => x"5170a738",
343 => x"80cfec08",
344 => x"70085252",
345 => x"70802e94",
346 => x"38841280",
347 => x"cfec0c70",
348 => x"2d80cfec",
349 => x"08700852",
350 => x"5270ee38",
351 => x"810b80df",
352 => x"dc34833d",
353 => x"0d040480",
354 => x"3d0d0b0b",
355 => x"80dfcc08",
356 => x"802e8e38",
357 => x"0b0b0b0b",
358 => x"800b802e",
359 => x"09810685",
360 => x"38823d0d",
361 => x"040b0b80",
362 => x"dfcc510b",
363 => x"0b0bf4d0",
364 => x"3f823d0d",
365 => x"0404803d",
366 => x"0d80dfe8",
367 => x"08811180",
368 => x"dfe80c51",
369 => x"800b8e80",
370 => x"800c823d",
371 => x"0d04f73d",
372 => x"0d7b5487",
373 => x"0b893d80",
374 => x"cff00858",
375 => x"58557417",
376 => x"748f0617",
377 => x"53537133",
378 => x"73347384",
379 => x"2aff1656",
380 => x"54748025",
381 => x"e938800b",
382 => x"8b3d3476",
383 => x"51878e3f",
384 => x"8b3d0d04",
385 => x"f33d0d80",
386 => x"cf9c5187",
387 => x"803f800b",
388 => x"8c80800c",
389 => x"8c808008",
390 => x"8c808408",
391 => x"80cfa053",
392 => x"595286e9",
393 => x"3f715487",
394 => x"0b8d3d80",
395 => x"cff00858",
396 => x"58557417",
397 => x"748f0617",
398 => x"53537133",
399 => x"73347384",
400 => x"2aff1656",
401 => x"54748025",
402 => x"e938800b",
403 => x"8f3d3476",
404 => x"5186ba3f",
405 => x"80cfa851",
406 => x"86b33f77",
407 => x"54870b80",
408 => x"cff0088b",
409 => x"3d595755",
410 => x"7417748f",
411 => x"06175458",
412 => x"72337834",
413 => x"73842aff",
414 => x"16565474",
415 => x"8025e938",
416 => x"800b8c3d",
417 => x"34765186",
418 => x"843f810b",
419 => x"8e80840c",
420 => x"80dfe808",
421 => x"5380dfe8",
422 => x"08547274",
423 => x"2e8f3880",
424 => x"cfb05185",
425 => x"e83f80df",
426 => x"e80853e9",
427 => x"3980cfc0",
428 => x"5185da3f",
429 => x"e039bc08",
430 => x"02bc0cf9",
431 => x"3d0d800b",
432 => x"bc08fc05",
433 => x"0cbc0888",
434 => x"05088025",
435 => x"ab38bc08",
436 => x"88050830",
437 => x"bc088805",
438 => x"0c800bbc",
439 => x"08f4050c",
440 => x"bc08fc05",
441 => x"08883881",
442 => x"0bbc08f4",
443 => x"050cbc08",
444 => x"f40508bc",
445 => x"08fc050c",
446 => x"bc088c05",
447 => x"088025ab",
448 => x"38bc088c",
449 => x"050830bc",
450 => x"088c050c",
451 => x"800bbc08",
452 => x"f0050cbc",
453 => x"08fc0508",
454 => x"8838810b",
455 => x"bc08f005",
456 => x"0cbc08f0",
457 => x"0508bc08",
458 => x"fc050c80",
459 => x"53bc088c",
460 => x"050852bc",
461 => x"08880508",
462 => x"5181a73f",
463 => x"b00870bc",
464 => x"08f8050c",
465 => x"54bc08fc",
466 => x"0508802e",
467 => x"8c38bc08",
468 => x"f8050830",
469 => x"bc08f805",
470 => x"0cbc08f8",
471 => x"050870b0",
472 => x"0c54893d",
473 => x"0dbc0c04",
474 => x"bc0802bc",
475 => x"0cfb3d0d",
476 => x"800bbc08",
477 => x"fc050cbc",
478 => x"08880508",
479 => x"80259338",
480 => x"bc088805",
481 => x"0830bc08",
482 => x"88050c81",
483 => x"0bbc08fc",
484 => x"050cbc08",
485 => x"8c050880",
486 => x"258c38bc",
487 => x"088c0508",
488 => x"30bc088c",
489 => x"050c8153",
490 => x"bc088c05",
491 => x"0852bc08",
492 => x"88050851",
493 => x"ad3fb008",
494 => x"70bc08f8",
495 => x"050c54bc",
496 => x"08fc0508",
497 => x"802e8c38",
498 => x"bc08f805",
499 => x"0830bc08",
500 => x"f8050cbc",
501 => x"08f80508",
502 => x"70b00c54",
503 => x"873d0dbc",
504 => x"0c04bc08",
505 => x"02bc0cfd",
506 => x"3d0d810b",
507 => x"bc08fc05",
508 => x"0c800bbc",
509 => x"08f8050c",
510 => x"bc088c05",
511 => x"08bc0888",
512 => x"050827ac",
513 => x"38bc08fc",
514 => x"0508802e",
515 => x"a338800b",
516 => x"bc088c05",
517 => x"08249938",
518 => x"bc088c05",
519 => x"0810bc08",
520 => x"8c050cbc",
521 => x"08fc0508",
522 => x"10bc08fc",
523 => x"050cc939",
524 => x"bc08fc05",
525 => x"08802e80",
526 => x"c938bc08",
527 => x"8c0508bc",
528 => x"08880508",
529 => x"26a138bc",
530 => x"08880508",
531 => x"bc088c05",
532 => x"0831bc08",
533 => x"88050cbc",
534 => x"08f80508",
535 => x"bc08fc05",
536 => x"0807bc08",
537 => x"f8050cbc",
538 => x"08fc0508",
539 => x"812abc08",
540 => x"fc050cbc",
541 => x"088c0508",
542 => x"812abc08",
543 => x"8c050cff",
544 => x"af39bc08",
545 => x"90050880",
546 => x"2e8f38bc",
547 => x"08880508",
548 => x"70bc08f4",
549 => x"050c518d",
550 => x"39bc08f8",
551 => x"050870bc",
552 => x"08f4050c",
553 => x"51bc08f4",
554 => x"0508b00c",
555 => x"853d0dbc",
556 => x"0c04fc3d",
557 => x"0d767079",
558 => x"7b555555",
559 => x"558f7227",
560 => x"8c387275",
561 => x"07830651",
562 => x"70802ea7",
563 => x"38ff1252",
564 => x"71ff2e98",
565 => x"38727081",
566 => x"05543374",
567 => x"70810556",
568 => x"34ff1252",
569 => x"71ff2e09",
570 => x"8106ea38",
571 => x"74b00c86",
572 => x"3d0d0474",
573 => x"51727084",
574 => x"05540871",
575 => x"70840553",
576 => x"0c727084",
577 => x"05540871",
578 => x"70840553",
579 => x"0c727084",
580 => x"05540871",
581 => x"70840553",
582 => x"0c727084",
583 => x"05540871",
584 => x"70840553",
585 => x"0cf01252",
586 => x"718f26c9",
587 => x"38837227",
588 => x"95387270",
589 => x"84055408",
590 => x"71708405",
591 => x"530cfc12",
592 => x"52718326",
593 => x"ed387054",
594 => x"ff8339f7",
595 => x"3d0d7c70",
596 => x"525380ca",
597 => x"3f7254b0",
598 => x"08550b0b",
599 => x"80cfcc56",
600 => x"8157b008",
601 => x"81055a8b",
602 => x"3de41159",
603 => x"538259f4",
604 => x"13527b88",
605 => x"11085253",
606 => x"81833fb0",
607 => x"083070b0",
608 => x"08079f2c",
609 => x"8a07b00c",
610 => x"538b3d0d",
611 => x"04ff3d0d",
612 => x"735280cf",
613 => x"f40851ff",
614 => x"b23f833d",
615 => x"0d04fd3d",
616 => x"0d757071",
617 => x"83065355",
618 => x"5270b838",
619 => x"71700870",
620 => x"09f7fbfd",
621 => x"ff120670",
622 => x"f8848281",
623 => x"80065151",
624 => x"5253709d",
625 => x"38841370",
626 => x"087009f7",
627 => x"fbfdff12",
628 => x"0670f884",
629 => x"82818006",
630 => x"51515253",
631 => x"70802ee5",
632 => x"38725271",
633 => x"33517080",
634 => x"2e8a3881",
635 => x"12703352",
636 => x"5270f838",
637 => x"717431b0",
638 => x"0c853d0d",
639 => x"04f23d0d",
640 => x"60628811",
641 => x"08705757",
642 => x"5f5a7480",
643 => x"2e818f38",
644 => x"8c1a2270",
645 => x"832a8132",
646 => x"70810651",
647 => x"55587386",
648 => x"38901a08",
649 => x"91387951",
650 => x"90a13fff",
651 => x"54b00880",
652 => x"ed388c1a",
653 => x"22587d08",
654 => x"57807883",
655 => x"ffff0670",
656 => x"812a7081",
657 => x"06515657",
658 => x"5573752e",
659 => x"80d73874",
660 => x"90387608",
661 => x"84180888",
662 => x"19595659",
663 => x"74802ef2",
664 => x"38745488",
665 => x"80752784",
666 => x"38888054",
667 => x"73537852",
668 => x"9c1a0851",
669 => x"a41a0854",
670 => x"732d800b",
671 => x"b0082582",
672 => x"e638b008",
673 => x"1975b008",
674 => x"317f8805",
675 => x"08b00831",
676 => x"70618805",
677 => x"0c565659",
678 => x"73ffb438",
679 => x"805473b0",
680 => x"0c903d0d",
681 => x"04758132",
682 => x"70810676",
683 => x"41515473",
684 => x"802e81c1",
685 => x"38749038",
686 => x"76088418",
687 => x"08881959",
688 => x"56597480",
689 => x"2ef23888",
690 => x"1a087883",
691 => x"ffff0670",
692 => x"892a7081",
693 => x"06515659",
694 => x"5673802e",
695 => x"82fa3875",
696 => x"75278d38",
697 => x"77872a70",
698 => x"81065154",
699 => x"7382b538",
700 => x"74762783",
701 => x"38745675",
702 => x"53785279",
703 => x"08518582",
704 => x"3f881a08",
705 => x"7631881b",
706 => x"0c790816",
707 => x"7a0c7456",
708 => x"75197577",
709 => x"317f8805",
710 => x"08783170",
711 => x"6188050c",
712 => x"56565973",
713 => x"802efef4",
714 => x"388c1a22",
715 => x"58ff8639",
716 => x"77785479",
717 => x"537b5256",
718 => x"84c83f88",
719 => x"1a087831",
720 => x"881b0c79",
721 => x"08187a0c",
722 => x"7c76315d",
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2791 => x"00000000",
2792 => x"00000000",
2793 => x"ffffffff",
2794 => x"00000000",
2795 => x"00020000",
2796 => x"00000000",
2797 => x"00000000",
2798 => x"00002bb0",
2799 => x"00002bb0",
2800 => x"00002bb8",
2801 => x"00002bb8",
2802 => x"00002bc0",
2803 => x"00002bc0",
2804 => x"00002bc8",
2805 => x"00002bc8",
2806 => x"00002bd0",
2807 => x"00002bd0",
2808 => x"00002bd8",
2809 => x"00002bd8",
2810 => x"00002be0",
2811 => x"00002be0",
2812 => x"00002be8",
2813 => x"00002be8",
2814 => x"00002bf0",
2815 => x"00002bf0",
2816 => x"00002bf8",
2817 => x"00002bf8",
2818 => x"00002c00",
2819 => x"00002c00",
2820 => x"00002c08",
2821 => x"00002c08",
2822 => x"00002c10",
2823 => x"00002c10",
2824 => x"00002c18",
2825 => x"00002c18",
2826 => x"00002c20",
2827 => x"00002c20",
2828 => x"00002c28",
2829 => x"00002c28",
2830 => x"00002c30",
2831 => x"00002c30",
2832 => x"00002c38",
2833 => x"00002c38",
2834 => x"00002c40",
2835 => x"00002c40",
2836 => x"00002c48",
2837 => x"00002c48",
2838 => x"00002c50",
2839 => x"00002c50",
2840 => x"00002c58",
2841 => x"00002c58",
2842 => x"00002c60",
2843 => x"00002c60",
2844 => x"00002c68",
2845 => x"00002c68",
2846 => x"00002c70",
2847 => x"00002c70",
2848 => x"00002c78",
2849 => x"00002c78",
2850 => x"00002c80",
2851 => x"00002c80",
2852 => x"00002c88",
2853 => x"00002c88",
2854 => x"00002c90",
2855 => x"00002c90",
2856 => x"00002c98",
2857 => x"00002c98",
2858 => x"00002ca0",
2859 => x"00002ca0",
2860 => x"00002ca8",
2861 => x"00002ca8",
2862 => x"00002cb0",
2863 => x"00002cb0",
2864 => x"00002cb8",
2865 => x"00002cb8",
2866 => x"00002cc0",
2867 => x"00002cc0",
2868 => x"00002cc8",
2869 => x"00002cc8",
2870 => x"00002cd0",
2871 => x"00002cd0",
2872 => x"00002cd8",
2873 => x"00002cd8",
2874 => x"00002ce0",
2875 => x"00002ce0",
2876 => x"00002ce8",
2877 => x"00002ce8",
2878 => x"00002cf0",
2879 => x"00002cf0",
2880 => x"00002cf8",
2881 => x"00002cf8",
2882 => x"00002d00",
2883 => x"00002d00",
2884 => x"00002d08",
2885 => x"00002d08",
2886 => x"00002d10",
2887 => x"00002d10",
2888 => x"00002d18",
2889 => x"00002d18",
2890 => x"00002d20",
2891 => x"00002d20",
2892 => x"00002d28",
2893 => x"00002d28",
2894 => x"00002d30",
2895 => x"00002d30",
2896 => x"00002d38",
2897 => x"00002d38",
2898 => x"00002d40",
2899 => x"00002d40",
2900 => x"00002d48",
2901 => x"00002d48",
2902 => x"00002d50",
2903 => x"00002d50",
2904 => x"00002d58",
2905 => x"00002d58",
2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002e48",
2965 => x"00002e48",
2966 => x"00002e50",
2967 => x"00002e50",
2968 => x"00002e58",
2969 => x"00002e58",
2970 => x"00002e60",
2971 => x"00002e60",
2972 => x"00002e68",
2973 => x"00002e68",
2974 => x"00002e70",
2975 => x"00002e70",
2976 => x"00002e78",
2977 => x"00002e78",
2978 => x"00002e80",
2979 => x"00002e80",
2980 => x"00002e88",
2981 => x"00002e88",
2982 => x"00002e90",
2983 => x"00002e90",
2984 => x"00002e98",
2985 => x"00002e98",
2986 => x"00002ea0",
2987 => x"00002ea0",
2988 => x"00002ea8",
2989 => x"00002ea8",
2990 => x"00002eb0",
2991 => x"00002eb0",
2992 => x"00002eb8",
2993 => x"00002eb8",
2994 => x"00002ec0",
2995 => x"00002ec0",
2996 => x"00002ec8",
2997 => x"00002ec8",
2998 => x"00002ed0",
2999 => x"00002ed0",
3000 => x"00002ed8",
3001 => x"00002ed8",
3002 => x"00002ee0",
3003 => x"00002ee0",
3004 => x"00002ee8",
3005 => x"00002ee8",
3006 => x"00002ef0",
3007 => x"00002ef0",
3008 => x"00002ef8",
3009 => x"00002ef8",
3010 => x"00002f00",
3011 => x"00002f00",
3012 => x"00002f08",
3013 => x"00002f08",
3014 => x"00002f10",
3015 => x"00002f10",
3016 => x"00002f18",
3017 => x"00002f18",
3018 => x"00002f20",
3019 => x"00002f20",
3020 => x"00002f28",
3021 => x"00002f28",
3022 => x"00002f30",
3023 => x"00002f30",
3024 => x"00002f38",
3025 => x"00002f38",
3026 => x"00002f40",
3027 => x"00002f40",
3028 => x"00002f48",
3029 => x"00002f48",
3030 => x"00002f50",
3031 => x"00002f50",
3032 => x"00002f58",
3033 => x"00002f58",
3034 => x"00002f60",
3035 => x"00002f60",
3036 => x"00002f68",
3037 => x"00002f68",
3038 => x"00002f70",
3039 => x"00002f70",
3040 => x"00002f78",
3041 => x"00002f78",
3042 => x"00002f80",
3043 => x"00002f80",
3044 => x"00002f88",
3045 => x"00002f88",
3046 => x"00002f90",
3047 => x"00002f90",
3048 => x"00002f98",
3049 => x"00002f98",
3050 => x"00002fa0",
3051 => x"00002fa0",
3052 => x"00002fa8",
3053 => x"00002fa8",
3054 => x"000027d4",
3055 => x"ffffffff",
3056 => x"00000000",
3057 => x"ffffffff",
3058 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | dc25f894c24e3d23e2b9ff8b6c44d284 | 0.592542 | 2.280782 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/fontrom/fontrom.vhd | 1 | 5,445 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fontrom.vhd when simulating
-- the core, fontrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fontrom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END fontrom;
ARCHITECTURE fontrom_a OF fontrom IS
-- synthesis translate_off
COMPONENT wrapped_fontrom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fontrom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "fontrom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fontrom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END fontrom_a;
| gpl-3.0 | 56072c38371e3967c034f6d0ff356864 | 0.516253 | 3.977356 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/memctrl/memctrl.vhd | 1 | 3,806 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memctrl is
Port (
CLK : in std_logic;
RESET : in std_logic;
MEM_A : in std_logic_vector(19 downto 0);
MEM_DI : in std_logic_vector(7 downto 0);
MEM_DO : out std_logic_vector(7 downto 0);
MEM_RW : in std_logic;
MEM_REQ : in std_logic;
MEM_ACK : out std_logic;
SRAM_A : out std_logic_vector(18 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
SRAM_OE : out std_logic;
SRAM_WE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic );
end memctrl;
architecture Behavioral of memctrl is
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
-- STATEMACHINE
type STATE_TYPE is (IDLE, READ1, WRITE1, WRITE2);
signal STATE : STATE_TYPE := IDLE;
begin
SRAM_D <= SRAM_DI;
SRAM_DO <= SRAM_D;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
SRAM_A <= (others=>'0');
SRAM_DI <= (others=>'Z');
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
SRAM_WE <= '1';
SRAM_UB <= '1';
SRAM_LB <= '1';
MEM_DO <= (others=>'0');
MEM_ACK <= '0';
STATE <= IDLE;
else
MEM_ACK <= '0';
case STATE is
when IDLE =>
if MEM_REQ = '1' then
SRAM_A <= '0' & MEM_A(18 downto 1);
if MEM_A(0) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
if MEM_A(19) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if MEM_RW = '0' then
SRAM_OE <= '0';
STATE <= READ1;
else
SRAM_DI <= MEM_DI & MEM_DI;
SRAM_WE <= '0';
STATE <= WRITE1;
end if;
end if;
when READ1 =>
if MEM_A(0) = '0' then
MEM_DO <= SRAM_DO(7 downto 0);
else
MEM_DO <= SRAM_DO(15 downto 8);
end if;
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
MEM_ACK <= '1';
STATE <= IDLE;
when WRITE1 =>
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_WE <= '1';
STATE <= WRITE2;
when WRITE2 =>
SRAM_DI <= (others=>'Z');
MEM_ACK <= '1';
STATE <= IDLE;
when others =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 9b1c62204ea9edb4d652aa51b5560110 | 0.335786 | 4.290868 | false | false | false | false |
APastorG/APG | int_const_mult/int_const_mult_s.vhd | 1 | 3,403 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an int_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_s is
generic(
SPEED_opt : T_speed := t_min; --exception: value not set
MULTIPLICANDS : integer_v --compulsory
);
port(
input : in u_sfixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_s1 of int_const_mult_s is
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(MULTIPLICANDS);
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_s2:
entity work.real_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
--ROUND_STYLE_opt => ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_real,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | d48c3ec5dad483e6019ea518d97a86a4 | 0.412585 | 4.552703 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/vram/vram.vhd | 1 | 5,826 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| gpl-3.0 | 20933bbec01e50a9431614e8ac4ff81f | 0.518366 | 3.931174 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/plasma.vhd | 1 | 7,528 | ---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (16KB)
-- 0x10000000 - 0x000fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- IRQ bits:
-- 7 GPIO31
-- 6 GPIO30
-- 5 ^GPIO31
-- 4 ^GPIO30
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma
architecture logic of plasma is
signal address_reg : std_logic_vector(31 downto 2);
signal data_write_reg : std_logic_vector(31 downto 0);
signal write_byte_enable_reg : std_logic_vector(3 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal mem_write_byte_enable : std_logic_vector(3 downto 0);
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal mem_pause : std_logic;
signal enable_internal_ram : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
begin --architecture
write_byte_enable <= write_byte_enable_reg;
data_write <= data_write_reg;
address <= address_reg;
write_enable <= '1' when write_byte_enable_reg /= "0000" else '0';
mem_pause <= mem_pause_in or (uart_write_busy and enable_uart and write_enable);
irq_status <= gpioA_in(31 downto 30) & (gpioA_in(31 downto 30) xor "11") &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out <= gpio0_reg;
enable_internal_ram <= '1' when mem_address(30 downto 28) = "000" else '0';
enable_misc <= '1' when address_reg(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and address_reg(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
mem_address => mem_address,
mem_data_w => mem_data_write,
mem_data_r => mem_data_read,
mem_byte_we => mem_write_byte_enable,
mem_pause => mem_pause);
misc_proc: process(clk, reset, mem_address, address_reg, enable_misc,
data_read_ram, data_read, data_read_uart, mem_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
gpioA_in, counter_reg, mem_data_write, data_write_reg)
begin
case address_reg(30 downto 28) is
when "000" => --internal RAM
mem_data_read <= data_read_ram;
when "001" => --external RAM
mem_data_read <= data_read;
when "010" => --misc
case address_reg(6 downto 4) is
when "000" => --uart
mem_data_read <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
mem_data_read <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
mem_data_read <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
mem_data_read <= gpio0_reg;
when "101" => --gpioA
mem_data_read <= gpioA_in;
when "110" => --counter
mem_data_read <= counter_reg;
when others =>
mem_data_read <= gpioA_in;
end case;
when others =>
mem_data_read <= ZERO;
end case;
if reset = '1' then
address_reg <= ZERO(31 downto 2);
data_write_reg <= ZERO;
write_byte_enable_reg <= ZERO(3 downto 0);
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if mem_pause = '0' then
address_reg <= mem_address(31 downto 2);
data_write_reg <= mem_data_write;
write_byte_enable_reg <= mem_write_byte_enable;
if enable_misc = '1' and write_enable = '1' then
if address_reg(6 downto 4) = "001" then
irq_mask_reg <= data_write_reg(7 downto 0);
elsif address_reg(6 downto 4) = "011" then
gpio0_reg <= data_write_reg;
end if;
end if;
end if;
counter_reg <= bv_inc(counter_reg);
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type)
port map (
clk => clk,
enable => enable_internal_ram,
write_byte_enable => mem_write_byte_enable,
address => mem_address(31 downto 2),
data_write => mem_data_write,
data_read => data_read_ram);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => data_write_reg(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
end; --architecture logic
| gpl-3.0 | 0320e3d760ae5e5dd01eafa4656b4145 | 0.54822 | 3.530957 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/8255/tb_A8251_top.vhd | 1 | 9,081 | -- Altera Microperipheral Reference Design Version 0802
--**********************************************************************************************
--
-- System: A8251
-- Component: Testbench top level
--
-- File: tb_a8251_top.vhd
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
--**********************************************************************************************
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY a8251top IS
END a8251top;
ARCHITECTURE struct OF a8251top IS
-------------------------------------------------------------------------------
-- SIGNAL declarations
-------------------------------------------------------------------------------
SIGNAL clk : std_logic;
SIGNAL reset : std_logic;
SIGNAL txd_to_rxd : std_logic;
SIGNAL rxd_to_txd : std_logic;
SIGNAL nDTR_to_nDSR : std_logic;
SIGNAL nDSR_to_nDTR : std_logic;
SIGNAL tx_nRTS_to_nCTS : std_logic;
SIGNAL tx_nWR : std_logic;
SIGNAL tx_nRD : std_logic;
SIGNAL tx_nCS : std_logic;
SIGNAL tx_CnD : std_logic;
SIGNAL tx_ExtSyncD : std_logic;
SIGNAL tx_nTxC : std_logic;
SIGNAL tx_nRxC : std_logic;
SIGNAL tx_din : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_txrdy : std_logic;
SIGNAL tx_txempty : std_logic;
SIGNAL tx_rxrdy : std_logic;
SIGNAL tx_syn_brk : std_logic;
SIGNAL tx_nEN : std_logic;
SIGNAL tx_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_nRTS_to_nCTS : std_logic;
SIGNAL rx_nWR : std_logic;
SIGNAL rx_nRD : std_logic;
SIGNAL rx_nCS : std_logic;
SIGNAL rx_CnD : std_logic;
SIGNAL rx_ExtSyncD : std_logic;
SIGNAL rx_nTxC : std_logic;
SIGNAL rx_nRxC : std_logic;
SIGNAL rx_din : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_txrdy : std_logic;
SIGNAL rx_txempty : std_logic;
SIGNAL rx_rxrdy : std_logic;
SIGNAL rx_syn_brk : std_logic;
SIGNAL rx_nEN : std_logic;
SIGNAL rx_dout : std_logic_vector(7 DOWNTO 0);
-------------------------------------------------------------------------------
-- COMPONENT declarations
-------------------------------------------------------------------------------
COMPONENT a8251tb
PORT
(
-- Common ports
clk : OUT std_logic;
reset : OUT std_logic;
txd_to_rxd : IN std_logic;
rxd_to_txd : IN std_logic;
nDTR_to_nDSR : IN std_logic;
nDSR_to_nDTR : IN std_logic;
-- Ports for the Tx USART
tx_txrdy : IN std_logic;
tx_txempty : IN std_logic;
tx_rxrdy : IN std_logic;
tx_syn_brk : IN std_logic;
tx_nEN : IN std_logic;
tx_dout : IN std_logic_vector (7 DOWNTO 0);
tx_nWR : OUT std_logic;
tx_nRD : OUT std_logic;
tx_nCS : OUT std_logic;
tx_CnD : OUT std_logic;
tx_nRTS_to_nCTS : IN std_logic;
tx_ExtSyncD : OUT std_logic;
tx_nTxC : OUT std_logic;
tx_nRxC : OUT std_logic;
tx_din : OUT std_logic_vector (7 DOWNTO 0);
-- Ports for the Rx USART
rx_txrdy : IN std_logic;
rx_txempty : IN std_logic;
rx_rxrdy : IN std_logic;
rx_syn_brk : IN std_logic;
rx_nEN : IN std_logic;
rx_dout : IN std_logic_vector (7 DOWNTO 0);
rx_nWR : OUT std_logic;
rx_nRD : OUT std_logic;
rx_nCS : OUT std_logic;
rx_CnD : OUT std_logic;
rx_nRTS_to_nCTS : IN std_logic;
rx_ExtSyncD : OUT std_logic;
rx_nTxC : OUT std_logic;
rx_nRxC : OUT std_logic;
rx_din : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT a8251
PORT
(
clk : IN std_logic;
reset : IN std_logic;
nWR : IN std_logic;
nRD : IN std_logic;
nCS : IN std_logic;
CnD : IN std_logic;
nDSR : IN std_logic;
nCTS : IN std_logic;
ExtSyncD : IN std_logic;
nTxC : IN std_logic;
nRxC : IN std_logic;
rxd : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0);
txd : OUT std_logic;
txrdy : OUT std_logic;
txempty : OUT std_logic;
rxrdy : OUT std_logic;
nDTR : OUT std_logic;
nRTS : OUT std_logic;
syn_brk : OUT std_logic;
nEN : OUT std_logic;
dout : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------------
-- COMPONENT instantiations
-------------------------------------------------------------------------------
i_a8251tb : a8251tb
PORT MAP
(
clk => clk,
reset => reset,
txd_to_rxd => txd_to_rxd,
rxd_to_txd => rxd_to_txd,
nDTR_to_nDSR => nDTR_to_nDSR,
nDSR_to_nDTR => nDSR_to_nDTR,
tx_txrdy => tx_txrdy,
tx_txempty => tx_txempty,
tx_rxrdy => tx_rxrdy,
tx_syn_brk => tx_syn_brk,
tx_nEN => tx_nEN,
tx_dout => tx_dout,
tx_nWR => tx_nWR,
tx_nRD => tx_nRD,
tx_nCS => tx_nCS,
tx_CnD => tx_CnD,
tx_nRTS_to_nCTS => tx_nRTS_to_nCTS,
tx_ExtSyncD => tx_ExtSyncD,
tx_nTxC => tx_nTxC,
tx_nRxC => tx_nRxC,
tx_din => tx_din,
rx_txrdy => rx_txrdy,
rx_txempty => rx_txempty,
rx_rxrdy => rx_rxrdy,
rx_syn_brk => rx_syn_brk,
rx_nEN => rx_nEN,
rx_dout => rx_dout,
rx_nWR => rx_nWR,
rx_nRD => rx_nRD,
rx_nCS => rx_nCS,
rx_CnD => rx_CnD,
rx_nRTS_to_nCTS => rx_nRTS_to_nCTS,
rx_ExtSyncD => rx_ExtSyncD,
rx_nTxC => rx_nTxC,
rx_nRxC => rx_nRxC,
rx_din => rx_din
);
i_tx_a8251 : a8251
PORT MAP
(
clk => clk,
reset => reset,
nWR => tx_nWR,
nRD => tx_nRD,
nCS => tx_nCS,
CnD => tx_CnD,
nDSR => nDSR_to_nDTR,
nCTS => tx_nRTS_to_nCTS,
ExtSyncD => tx_ExtSyncD,
nTxC => tx_nTxC,
nRxC => tx_nRxC,
rxd => rxd_to_txd,
din => tx_din,
txd => txd_to_rxd,
txrdy => tx_txrdy,
txempty => tx_txempty,
rxrdy => tx_rxrdy,
nDTR => nDTR_to_nDSR,
nRTS => tx_nRTS_to_nCTS,
syn_brk => tx_syn_brk,
nEN => tx_nEN,
dout => tx_dout
);
i_rx_a8251 : a8251
PORT MAP
(
clk => clk,
reset => reset,
nWR => rx_nWR,
nRD => rx_nRD,
nCS => rx_nCS,
CnD => rx_CnD,
nDSR => nDTR_to_nDSR,
nCTS => rx_nRTS_to_nCTS,
ExtSyncD => rx_ExtSyncD,
nTxC => rx_nTxC,
nRxC => rx_nRxC,
rxd => txd_to_rxd,
din => rx_din,
txd => rxd_to_txd,
txrdy => rx_txrdy,
txempty => rx_txempty,
rxrdy => rx_rxrdy,
nDTR => nDSR_to_nDTR,
nRTS => rx_nRTS_to_nCTS,
syn_brk => rx_syn_brk,
nEN => rx_nEN,
dout => rx_dout
);
END struct;
| gpl-3.0 | c9a6f5c18ca0e1496b0cc775de60729c | 0.46812 | 3.12599 | false | false | false | false |
223323/lab2 | HDL/source/coregen/dcm50MHz.vhd | 1 | 6,528 | -- file: dcm50MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.143______0.000______50.0______598.860____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________27____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm50MHz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm50MHz;
architecture xilinx of dcm50MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm50MHz,clk_wiz_v3_6,{component_name=dcm50MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 7,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 37.037,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | 8e96cdf02bb8a122489e6644d2d39f5c | 0.556832 | 4.261097 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/example_design/cham_rom_exdes.vhd | 1 | 4,332 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cham_rom_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END cham_rom_exdes;
ARCHITECTURE xilinx OF cham_rom_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT cham_rom IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : cham_rom
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 792efe19cfa17b60f2d5f736aa0fcfdf | 0.574331 | 4.797342 | false | false | false | false |
sonologic/gmzpu | vhdl/helpers/zpu_med1.vhdl | 1 | 8,396 | ------------------------------------------------------------------------------
---- ----
---- ZPU Medium + PHI I/O + BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
---- medium version, the PHI I/O basic layout and a program BRAM. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPU_Med1(Structural) (Entity and architecture) ----
---- File name: zpu_med1.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
-- RAM declaration
library work;
use work.zpu_memory.all;
entity ZPU_Med1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='X'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=9600; -- RS232 baudrate
ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
interrupt_i: in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end entity ZPU_Med1;
architecture Structural of ZPU_Med1 is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
-- I/O & memory (ZPU)
signal mem_busy : std_logic;
signal mem_read : unsigned(WORD_SIZE-1 downto 0);
signal mem_write : unsigned(WORD_SIZE-1 downto 0);
signal mem_addr : unsigned(ADDR_W-1 downto 0);
signal mem_we : std_logic;
signal mem_re : std_logic;
-- Memory (SinglePort_RAM)
signal ram_busy : std_logic;
signal ram_read : unsigned(WORD_SIZE-1 downto 0);
signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram_we : std_logic;
signal ram_re : std_logic;
signal ram_ready_r : std_logic:='0';
-- I/O (ZPU_IO)
signal io_busy : std_logic;
signal io_re : std_logic;
signal io_we : std_logic;
signal io_read : unsigned(WORD_SIZE-1 downto 0);
signal io_ready : std_logic;
signal io_reading_r : std_logic:='0';
signal io_addr : unsigned(2 downto 0);
begin
memory: SinglePortRAM
generic map(
WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
port map(
clk_i => clk_i,
we_i => ram_we, re_i => ram_re, addr_i => ram_addr,
write_i => mem_write, read_o => ram_read, busy_o => ram_busy);
ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS);
ram_we <= mem_we and not(mem_addr(IO_BIT));
ram_re <= mem_re and not(mem_addr(IO_BIT));
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
BRDIVISOR => BRDIVISOR,
LOG_FILE => "zpu_med1_io.log"
)
port map(
clk_i => clk_i,
reset_i => rst_i,
busy_o => io_busy,
we_i => io_we,
re_i => io_re,
data_i => mem_write,
data_o => io_read,
addr_i => io_addr,
rs232_rx_i => rs232_rx_i,
rs232_tx_o => rs232_tx_o,
br_clk_i => '1',
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir
);
io_addr <= mem_addr(4 downto 2);
-- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
-- Note: We define the address space as 256 kB, so writing to 0x80A00xx
-- will be as wrting to 0x200xx and hence we decode it as I/O space.
io_we <= mem_we and mem_addr(IO_BIT);
io_re <= mem_re and mem_addr(IO_BIT);
io_ready <= (io_reading_r or io_re) and not io_busy;
zpu : ZPUMediumCore
generic map(
WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
D_CARE_VAL => D_CARE_VAL)
port map(
clk_i => clk_i, reset_i => rst_i, interrupt_i => interrupt_i, enable_i => '1',
break_o => break_o, dbg_o => dbg_o,
-- Memory
mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write,
addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re);
mem_busy <= io_busy or ram_busy;
-- Memory reads either come from IO or DRAM. We need to pick the right one.
memory_control:
process (ram_read, ram_ready_r, io_ready, io_read)
begin
mem_read <= (others => '0');
if ram_ready_r='1' then
mem_read <= ram_read;
end if;
if io_ready='1' then
mem_read <= io_read;
end if;
end process memory_control;
memory_control_sync:
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
io_reading_r <= '0';
ram_ready_r <= '0';
else
io_reading_r <= io_busy or io_re;
ram_ready_r <= ram_re;
end if;
end if;
end process memory_control_sync;
end architecture Structural; -- Entity: ZPU_Med1
| bsd-3-clause | 7788c9cc90f7552f03ba4008d3843e1b | 0.405193 | 4.052124 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/bmg_stim_gen.vhd | 1 | 12,579 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (16383 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"cham_rom.mif",
DEFAULT_DATA,
8,
16384);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| gpl-3.0 | f50b2cfe590cc65ca6139b80d9a157c9 | 0.547659 | 3.684534 | false | false | false | false |
APastorG/APG | complex_const_multiplier/complex_const_mult_pkg.vhd | 1 | 5,409 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package complex_const_mult_pkg is
/* function 1 */
/**************************************************************************************************/
--returns the output signals' low index, which is the lowest of the low indexes of the partial output signals
function complex_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
min_output_bit : integer_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer;
--returns the output signals' high index, which is the highest of the high indexes of the partial output signals
function complex_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
max_output_bit : integer_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body complex_const_mult_pkg is
/********************************************************************************************** 1 */
--returns the output signals' low index, which is the lowest of the low indexes of the partial output signals
function complex_const_mult_OL(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
min_output_bit : integer_exc;
constants : real_v;
input_low : integer;
is_signed : boolean)
return integer is
variable result : integer := real_const_mult_OL(round_style_opt => round_style_opt,
round_to_bit_opt => round_to_bit_opt,
max_error_pct_opt => max_error_pct_opt,
constants => constants,
input_low => input_low,
is_signed => is_signed);
begin
if min_output_bit /= integer'low then
return maximum(result, min_output_bit);
else
return result;
end if;
end function;
--returns the output signals' high index, which is the highest of the high indexes of the partial output signals
function complex_const_mult_OH(
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
max_output_bit : integer_exc;
constants : real_v;
input_high : integer;
input_low : integer;
is_signed : boolean)
return integer is
variable result : integer := real_const_mult_OH(round_style_opt => round_style_opt,
round_to_bit_opt => round_to_bit_opt,
max_error_pct_opt => max_error_pct_opt,
constants => constants,
input_high => input_high,
input_low => input_low,
is_signed => is_signed);
begin
--if not (
-- (constants(0) = 0.0 and constants(1)>-1.0 and constants(1)<=1.0)
-- or
-- (constants(1) = 0.0 and constants(0)>-1.0 and constants(0)<=1.0)
-- )
--then
-- result := result + 1;
--end if;
if max_output_bit /= integer'low then
return minimum(result, max_output_bit);
else
return result;
end if;
end function;
end package body; | mit | 35c40782a7488e35aef58697cd15246d | 0.405953 | 4.786287 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/p_source_files_sr.vhd | 4 | 5,060 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_source_files_sr is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of p_source_files_sr is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_return_preg <= p_read;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_read, ap_return_preg)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_return <= p_read;
else
ap_return <= ap_return_preg;
end if;
end process;
end behav;
| mit | 6e89c92857b2aaca0dcf00c765fc80a0 | 0.55415 | 3.264516 | false | false | false | false |
sonologic/gmzpu | vhdl/zwishbone/zwishbone_pkg.vhdl | 1 | 6,416 | ------------------------------------------------------------------------------
---- ----
---- ZWISHBONE gmZPU WISHBONE B4 controller ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- Interface between the gmZPU zpu core and the WISHBONE B4 bus. ----
---- ----
---- Author: ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone (package) ----
---- File name: zwishbone_pkg.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: Yes ----
---- Synthesis tools: ModelSim ----
---- Simulation tools: ModelSim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zwishbone is
component zwishbone_controller is
generic (
DATA_WIDTH : natural:=32; -- width of data bus
ADR_WIDTH : natural:=16;
BUSBIT_WIDTH: natural:=1; -- bus/reg bit, adr MSB
CS_WIDTH : natural:=4
);
port (
-- SYSCON
clk_i : in std_logic;
rst_i : in std_logic;
-- zpu interface (non wishbone signal)
busy_o : out std_logic; -- controller busy
ready_o : out std_logic; -- controller busy
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
re_i : in std_logic; -- enable wb controller
we_i : in std_logic;
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
irq_o : out std_logic;
-- I/O decoder
--cs_o : out std_logic_vector(CS_WIDTH-1 downto 0);
-- wishbone bus
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_ack_i : in std_logic;
wb_adr_o : out unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
wb_cyc_o : out std_logic;
wb_stall_i : in std_logic;
wb_err_i : in std_logic;
wb_lock_o : out std_logic;
wb_rty_i : in std_logic;
wb_sel_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_o : out std_logic_vector((2**CS_WIDTH)-1 downto 0);
wb_tga_o : out unsigned(ADR_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
wb_tgc_o : out unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_o : out std_logic
);
end component zwishbone_controller;
component zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=15;
DATA_WIDTH : natural:=32
);
port (
-- syscon
clk_i : in std_logic;
rst_i : in std_logic;
irq_o : out std_logic;
-- memory control
re_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- bus
to_inc_i : in std_logic;
to_rst_i : in std_logic;
to_o : out std_logic;
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0);
-- status register value (0x0004, from c_control / bus)
err_i : in std_logic;
rty_i : in std_logic
);
end component zwishbone_c_regs;
end package zwishbone;
| bsd-3-clause | 7d873b3ca8369d4ca340742ea56d94c3 | 0.308292 | 5.351126 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/clock/clk20mhz.vhd | 1 | 6,345 | -- file: clk20mhz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____20.000______0.000______50.0_____1200.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk20mhz is
port
(-- Clock in ports
inclk0 : in std_logic;
-- Clock out ports
c0 : out std_logic
);
end clk20mhz;
architecture xilinx of clk20mhz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk20mhz,clk_wiz_v3_6,{component_name=clk20mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => inclk0);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.500,
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => c0,
I => clkfx);
end xilinx;
| gpl-3.0 | 3372ecd2e2dd36802198e0aabe95b483 | 0.55792 | 4.255533 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/gtia_palette.vhdl | 1 | 45,124 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia_palette IS
PORT
(
ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END gtia_palette;
ARCHITECTURE altirra OF gtia_palette IS
begin
process(atari_colour)
begin
case atari_colour is
when X"00" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"00";
when X"01" =>
R_next <= X"11";
G_next <= X"11";
B_next <= X"11";
when X"02" =>
R_next <= X"22";
G_next <= X"22";
B_next <= X"22";
when X"03" =>
R_next <= X"33";
G_next <= X"33";
B_next <= X"33";
when X"04" =>
R_next <= X"44";
G_next <= X"44";
B_next <= X"44";
when X"05" =>
R_next <= X"55";
G_next <= X"55";
B_next <= X"55";
when X"06" =>
R_next <= X"66";
G_next <= X"66";
B_next <= X"66";
when X"07" =>
R_next <= X"77";
G_next <= X"77";
B_next <= X"77";
when X"08" =>
R_next <= X"88";
G_next <= X"88";
B_next <= X"88";
when X"09" =>
R_next <= X"99";
G_next <= X"99";
B_next <= X"99";
when X"0a" =>
R_next <= X"aa";
G_next <= X"aa";
B_next <= X"aa";
when X"0b" =>
R_next <= X"bb";
G_next <= X"bb";
B_next <= X"bb";
when X"0c" =>
R_next <= X"cc";
G_next <= X"cc";
B_next <= X"cc";
when X"0d" =>
R_next <= X"dd";
G_next <= X"dd";
B_next <= X"dd";
when X"0e" =>
R_next <= X"ee";
G_next <= X"ee";
B_next <= X"ee";
when X"0f" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"ff";
when X"10" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"11" =>
R_next <= X"50";
G_next <= X"05";
B_next <= X"00";
when X"12" =>
R_next <= X"61";
G_next <= X"16";
B_next <= X"00";
when X"13" =>
R_next <= X"72";
G_next <= X"27";
B_next <= X"00";
when X"14" =>
R_next <= X"83";
G_next <= X"38";
B_next <= X"00";
when X"15" =>
R_next <= X"94";
G_next <= X"49";
B_next <= X"00";
when X"16" =>
R_next <= X"a5";
G_next <= X"5a";
B_next <= X"01";
when X"17" =>
R_next <= X"b6";
G_next <= X"6b";
B_next <= X"12";
when X"18" =>
R_next <= X"c7";
G_next <= X"7c";
B_next <= X"23";
when X"19" =>
R_next <= X"d8";
G_next <= X"8d";
B_next <= X"34";
when X"1a" =>
R_next <= X"e9";
G_next <= X"9e";
B_next <= X"45";
when X"1b" =>
R_next <= X"fa";
G_next <= X"af";
B_next <= X"56";
when X"1c" =>
R_next <= X"ff";
G_next <= X"c0";
B_next <= X"67";
when X"1d" =>
R_next <= X"ff";
G_next <= X"d1";
B_next <= X"78";
when X"1e" =>
R_next <= X"ff";
G_next <= X"e2";
B_next <= X"89";
when X"1f" =>
R_next <= X"ff";
G_next <= X"f3";
B_next <= X"9a";
when X"20" =>
R_next <= X"50";
G_next <= X"00";
B_next <= X"00";
when X"21" =>
R_next <= X"61";
G_next <= X"00";
B_next <= X"00";
when X"22" =>
R_next <= X"72";
G_next <= X"03";
B_next <= X"00";
when X"23" =>
R_next <= X"83";
G_next <= X"14";
B_next <= X"03";
when X"24" =>
R_next <= X"94";
G_next <= X"25";
B_next <= X"14";
when X"25" =>
R_next <= X"a5";
G_next <= X"36";
B_next <= X"25";
when X"26" =>
R_next <= X"b6";
G_next <= X"47";
B_next <= X"36";
when X"27" =>
R_next <= X"c7";
G_next <= X"58";
B_next <= X"47";
when X"28" =>
R_next <= X"d8";
G_next <= X"69";
B_next <= X"58";
when X"29" =>
R_next <= X"e9";
G_next <= X"7a";
B_next <= X"69";
when X"2a" =>
R_next <= X"fa";
G_next <= X"8b";
B_next <= X"7a";
when X"2b" =>
R_next <= X"ff";
G_next <= X"9c";
B_next <= X"8b";
when X"2c" =>
R_next <= X"ff";
G_next <= X"ad";
B_next <= X"9c";
when X"2d" =>
R_next <= X"ff";
G_next <= X"be";
B_next <= X"ad";
when X"2e" =>
R_next <= X"ff";
G_next <= X"cf";
B_next <= X"be";
when X"2f" =>
R_next <= X"ff";
G_next <= X"e0";
B_next <= X"cf";
when X"30" =>
R_next <= X"54";
G_next <= X"00";
B_next <= X"03";
when X"31" =>
R_next <= X"65";
G_next <= X"00";
B_next <= X"14";
when X"32" =>
R_next <= X"76";
G_next <= X"00";
B_next <= X"25";
when X"33" =>
R_next <= X"87";
G_next <= X"08";
B_next <= X"36";
when X"34" =>
R_next <= X"98";
G_next <= X"19";
B_next <= X"47";
when X"35" =>
R_next <= X"a9";
G_next <= X"2a";
B_next <= X"58";
when X"36" =>
R_next <= X"ba";
G_next <= X"3b";
B_next <= X"69";
when X"37" =>
R_next <= X"cb";
G_next <= X"4c";
B_next <= X"7a";
when X"38" =>
R_next <= X"dc";
G_next <= X"5d";
B_next <= X"8b";
when X"39" =>
R_next <= X"ed";
G_next <= X"6e";
B_next <= X"9c";
when X"3a" =>
R_next <= X"fe";
G_next <= X"7f";
B_next <= X"ad";
when X"3b" =>
R_next <= X"ff";
G_next <= X"90";
B_next <= X"be";
when X"3c" =>
R_next <= X"ff";
G_next <= X"a1";
B_next <= X"cf";
when X"3d" =>
R_next <= X"ff";
G_next <= X"b2";
B_next <= X"e0";
when X"3e" =>
R_next <= X"ff";
G_next <= X"c3";
B_next <= X"f1";
when X"3f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"ff";
when X"40" =>
R_next <= X"4f";
G_next <= X"00";
B_next <= X"35";
when X"41" =>
R_next <= X"60";
G_next <= X"00";
B_next <= X"46";
when X"42" =>
R_next <= X"71";
G_next <= X"00";
B_next <= X"57";
when X"43" =>
R_next <= X"82";
G_next <= X"01";
B_next <= X"68";
when X"44" =>
R_next <= X"93";
G_next <= X"12";
B_next <= X"79";
when X"45" =>
R_next <= X"a4";
G_next <= X"23";
B_next <= X"8a";
when X"46" =>
R_next <= X"b5";
G_next <= X"34";
B_next <= X"9b";
when X"47" =>
R_next <= X"c6";
G_next <= X"45";
B_next <= X"ac";
when X"48" =>
R_next <= X"d7";
G_next <= X"56";
B_next <= X"bd";
when X"49" =>
R_next <= X"e8";
G_next <= X"67";
B_next <= X"ce";
when X"4a" =>
R_next <= X"f9";
G_next <= X"78";
B_next <= X"df";
when X"4b" =>
R_next <= X"ff";
G_next <= X"89";
B_next <= X"f0";
when X"4c" =>
R_next <= X"ff";
G_next <= X"9a";
B_next <= X"ff";
when X"4d" =>
R_next <= X"ff";
G_next <= X"ab";
B_next <= X"ff";
when X"4e" =>
R_next <= X"ff";
G_next <= X"bc";
B_next <= X"ff";
when X"4f" =>
R_next <= X"ff";
G_next <= X"cd";
B_next <= X"ff";
when X"50" =>
R_next <= X"3d";
G_next <= X"00";
B_next <= X"68";
when X"51" =>
R_next <= X"4e";
G_next <= X"00";
B_next <= X"79";
when X"52" =>
R_next <= X"5f";
G_next <= X"00";
B_next <= X"8a";
when X"53" =>
R_next <= X"70";
G_next <= X"00";
B_next <= X"9b";
when X"54" =>
R_next <= X"81";
G_next <= X"11";
B_next <= X"ac";
when X"55" =>
R_next <= X"92";
G_next <= X"22";
B_next <= X"bd";
when X"56" =>
R_next <= X"a3";
G_next <= X"33";
B_next <= X"ce";
when X"57" =>
R_next <= X"b4";
G_next <= X"44";
B_next <= X"df";
when X"58" =>
R_next <= X"c5";
G_next <= X"55";
B_next <= X"f0";
when X"59" =>
R_next <= X"d6";
G_next <= X"66";
B_next <= X"ff";
when X"5a" =>
R_next <= X"e7";
G_next <= X"77";
B_next <= X"ff";
when X"5b" =>
R_next <= X"f8";
G_next <= X"88";
B_next <= X"ff";
when X"5c" =>
R_next <= X"ff";
G_next <= X"99";
B_next <= X"ff";
when X"5d" =>
R_next <= X"ff";
G_next <= X"aa";
B_next <= X"ff";
when X"5e" =>
R_next <= X"ff";
G_next <= X"bb";
B_next <= X"ff";
when X"5f" =>
R_next <= X"ff";
G_next <= X"cc";
B_next <= X"ff";
when X"60" =>
R_next <= X"20";
G_next <= X"00";
B_next <= X"8b";
when X"61" =>
R_next <= X"31";
G_next <= X"00";
B_next <= X"9c";
when X"62" =>
R_next <= X"42";
G_next <= X"00";
B_next <= X"ad";
when X"63" =>
R_next <= X"53";
G_next <= X"08";
B_next <= X"be";
when X"64" =>
R_next <= X"64";
G_next <= X"19";
B_next <= X"cf";
when X"65" =>
R_next <= X"75";
G_next <= X"2a";
B_next <= X"e0";
when X"66" =>
R_next <= X"86";
G_next <= X"3b";
B_next <= X"f1";
when X"67" =>
R_next <= X"97";
G_next <= X"4c";
B_next <= X"ff";
when X"68" =>
R_next <= X"a8";
G_next <= X"5d";
B_next <= X"ff";
when X"69" =>
R_next <= X"b9";
G_next <= X"6e";
B_next <= X"ff";
when X"6a" =>
R_next <= X"ca";
G_next <= X"7f";
B_next <= X"ff";
when X"6b" =>
R_next <= X"db";
G_next <= X"90";
B_next <= X"ff";
when X"6c" =>
R_next <= X"ec";
G_next <= X"a1";
B_next <= X"ff";
when X"6d" =>
R_next <= X"fd";
G_next <= X"b2";
B_next <= X"ff";
when X"6e" =>
R_next <= X"ff";
G_next <= X"c3";
B_next <= X"ff";
when X"6f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"ff";
when X"70" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"89";
when X"71" =>
R_next <= X"00";
G_next <= X"08";
B_next <= X"9a";
when X"72" =>
R_next <= X"00";
G_next <= X"19";
B_next <= X"ab";
when X"73" =>
R_next <= X"10";
G_next <= X"2a";
B_next <= X"bc";
when X"74" =>
R_next <= X"21";
G_next <= X"3b";
B_next <= X"cd";
when X"75" =>
R_next <= X"32";
G_next <= X"4c";
B_next <= X"de";
when X"76" =>
R_next <= X"43";
G_next <= X"5d";
B_next <= X"ef";
when X"77" =>
R_next <= X"54";
G_next <= X"6e";
B_next <= X"ff";
when X"78" =>
R_next <= X"65";
G_next <= X"7f";
B_next <= X"ff";
when X"79" =>
R_next <= X"76";
G_next <= X"90";
B_next <= X"ff";
when X"7a" =>
R_next <= X"87";
G_next <= X"a1";
B_next <= X"ff";
when X"7b" =>
R_next <= X"98";
G_next <= X"b2";
B_next <= X"ff";
when X"7c" =>
R_next <= X"a9";
G_next <= X"c3";
B_next <= X"ff";
when X"7d" =>
R_next <= X"ba";
G_next <= X"d4";
B_next <= X"ff";
when X"7e" =>
R_next <= X"cb";
G_next <= X"e5";
B_next <= X"ff";
when X"7f" =>
R_next <= X"dc";
G_next <= X"f6";
B_next <= X"ff";
when X"80" =>
R_next <= X"00";
G_next <= X"0c";
B_next <= X"65";
when X"81" =>
R_next <= X"00";
G_next <= X"1d";
B_next <= X"76";
when X"82" =>
R_next <= X"00";
G_next <= X"2e";
B_next <= X"87";
when X"83" =>
R_next <= X"00";
G_next <= X"3f";
B_next <= X"98";
when X"84" =>
R_next <= X"05";
G_next <= X"50";
B_next <= X"a9";
when X"85" =>
R_next <= X"16";
G_next <= X"61";
B_next <= X"ba";
when X"86" =>
R_next <= X"27";
G_next <= X"72";
B_next <= X"cb";
when X"87" =>
R_next <= X"38";
G_next <= X"83";
B_next <= X"dc";
when X"88" =>
R_next <= X"49";
G_next <= X"94";
B_next <= X"ed";
when X"89" =>
R_next <= X"5a";
G_next <= X"a5";
B_next <= X"fe";
when X"8a" =>
R_next <= X"6b";
G_next <= X"b6";
B_next <= X"ff";
when X"8b" =>
R_next <= X"7c";
G_next <= X"c7";
B_next <= X"ff";
when X"8c" =>
R_next <= X"8d";
G_next <= X"d8";
B_next <= X"ff";
when X"8d" =>
R_next <= X"9e";
G_next <= X"e9";
B_next <= X"ff";
when X"8e" =>
R_next <= X"af";
G_next <= X"fa";
B_next <= X"ff";
when X"8f" =>
R_next <= X"c0";
G_next <= X"ff";
B_next <= X"ff";
when X"90" =>
R_next <= X"00";
G_next <= X"1f";
B_next <= X"30";
when X"91" =>
R_next <= X"00";
G_next <= X"30";
B_next <= X"41";
when X"92" =>
R_next <= X"00";
G_next <= X"41";
B_next <= X"52";
when X"93" =>
R_next <= X"00";
G_next <= X"52";
B_next <= X"63";
when X"94" =>
R_next <= X"00";
G_next <= X"63";
B_next <= X"74";
when X"95" =>
R_next <= X"05";
G_next <= X"74";
B_next <= X"85";
when X"96" =>
R_next <= X"16";
G_next <= X"85";
B_next <= X"96";
when X"97" =>
R_next <= X"27";
G_next <= X"96";
B_next <= X"a7";
when X"98" =>
R_next <= X"38";
G_next <= X"a7";
B_next <= X"b8";
when X"99" =>
R_next <= X"49";
G_next <= X"b8";
B_next <= X"c9";
when X"9a" =>
R_next <= X"5a";
G_next <= X"c9";
B_next <= X"da";
when X"9b" =>
R_next <= X"6b";
G_next <= X"da";
B_next <= X"eb";
when X"9c" =>
R_next <= X"7c";
G_next <= X"eb";
B_next <= X"fc";
when X"9d" =>
R_next <= X"8d";
G_next <= X"fc";
B_next <= X"ff";
when X"9e" =>
R_next <= X"9e";
G_next <= X"ff";
B_next <= X"ff";
when X"9f" =>
R_next <= X"af";
G_next <= X"ff";
B_next <= X"ff";
when X"a0" =>
R_next <= X"00";
G_next <= X"2b";
B_next <= X"00";
when X"a1" =>
R_next <= X"00";
G_next <= X"3c";
B_next <= X"0e";
when X"a2" =>
R_next <= X"00";
G_next <= X"4d";
B_next <= X"1f";
when X"a3" =>
R_next <= X"00";
G_next <= X"5e";
B_next <= X"30";
when X"a4" =>
R_next <= X"00";
G_next <= X"6f";
B_next <= X"41";
when X"a5" =>
R_next <= X"01";
G_next <= X"80";
B_next <= X"52";
when X"a6" =>
R_next <= X"12";
G_next <= X"91";
B_next <= X"63";
when X"a7" =>
R_next <= X"23";
G_next <= X"a2";
B_next <= X"74";
when X"a8" =>
R_next <= X"34";
G_next <= X"b3";
B_next <= X"85";
when X"a9" =>
R_next <= X"45";
G_next <= X"c4";
B_next <= X"96";
when X"aa" =>
R_next <= X"56";
G_next <= X"d5";
B_next <= X"a7";
when X"ab" =>
R_next <= X"67";
G_next <= X"e6";
B_next <= X"b8";
when X"ac" =>
R_next <= X"78";
G_next <= X"f7";
B_next <= X"c9";
when X"ad" =>
R_next <= X"89";
G_next <= X"ff";
B_next <= X"da";
when X"ae" =>
R_next <= X"9a";
G_next <= X"ff";
B_next <= X"eb";
when X"af" =>
R_next <= X"ab";
G_next <= X"ff";
B_next <= X"fc";
when X"b0" =>
R_next <= X"00";
G_next <= X"33";
B_next <= X"00";
when X"b1" =>
R_next <= X"00";
G_next <= X"44";
B_next <= X"00";
when X"b2" =>
R_next <= X"00";
G_next <= X"55";
B_next <= X"00";
when X"b3" =>
R_next <= X"00";
G_next <= X"66";
B_next <= X"00";
when X"b4" =>
R_next <= X"07";
G_next <= X"77";
B_next <= X"00";
when X"b5" =>
R_next <= X"18";
G_next <= X"88";
B_next <= X"00";
when X"b6" =>
R_next <= X"29";
G_next <= X"99";
B_next <= X"00";
when X"b7" =>
R_next <= X"3a";
G_next <= X"aa";
B_next <= X"0f";
when X"b8" =>
R_next <= X"4b";
G_next <= X"bb";
B_next <= X"20";
when X"b9" =>
R_next <= X"5c";
G_next <= X"cc";
B_next <= X"31";
when X"ba" =>
R_next <= X"6d";
G_next <= X"dd";
B_next <= X"42";
when X"bb" =>
R_next <= X"7e";
G_next <= X"ee";
B_next <= X"53";
when X"bc" =>
R_next <= X"8f";
G_next <= X"ff";
B_next <= X"64";
when X"bd" =>
R_next <= X"a0";
G_next <= X"ff";
B_next <= X"75";
when X"be" =>
R_next <= X"b1";
G_next <= X"ff";
B_next <= X"86";
when X"bf" =>
R_next <= X"c2";
G_next <= X"ff";
B_next <= X"97";
when X"c0" =>
R_next <= X"00";
G_next <= X"2b";
B_next <= X"00";
when X"c1" =>
R_next <= X"00";
G_next <= X"3c";
B_next <= X"00";
when X"c2" =>
R_next <= X"02";
G_next <= X"4d";
B_next <= X"00";
when X"c3" =>
R_next <= X"13";
G_next <= X"5e";
B_next <= X"00";
when X"c4" =>
R_next <= X"24";
G_next <= X"6f";
B_next <= X"00";
when X"c5" =>
R_next <= X"35";
G_next <= X"80";
B_next <= X"00";
when X"c6" =>
R_next <= X"46";
G_next <= X"91";
B_next <= X"00";
when X"c7" =>
R_next <= X"57";
G_next <= X"a2";
B_next <= X"00";
when X"c8" =>
R_next <= X"68";
G_next <= X"b3";
B_next <= X"00";
when X"c9" =>
R_next <= X"79";
G_next <= X"c4";
B_next <= X"0e";
when X"ca" =>
R_next <= X"8a";
G_next <= X"d5";
B_next <= X"1f";
when X"cb" =>
R_next <= X"9b";
G_next <= X"e6";
B_next <= X"30";
when X"cc" =>
R_next <= X"ac";
G_next <= X"f7";
B_next <= X"41";
when X"cd" =>
R_next <= X"bd";
G_next <= X"ff";
B_next <= X"52";
when X"ce" =>
R_next <= X"ce";
G_next <= X"ff";
B_next <= X"63";
when X"cf" =>
R_next <= X"df";
G_next <= X"ff";
B_next <= X"74";
when X"d0" =>
R_next <= X"01";
G_next <= X"1c";
B_next <= X"00";
when X"d1" =>
R_next <= X"12";
G_next <= X"2d";
B_next <= X"00";
when X"d2" =>
R_next <= X"23";
G_next <= X"3e";
B_next <= X"00";
when X"d3" =>
R_next <= X"34";
G_next <= X"4f";
B_next <= X"00";
when X"d4" =>
R_next <= X"45";
G_next <= X"60";
B_next <= X"00";
when X"d5" =>
R_next <= X"56";
G_next <= X"71";
B_next <= X"00";
when X"d6" =>
R_next <= X"67";
G_next <= X"82";
B_next <= X"00";
when X"d7" =>
R_next <= X"78";
G_next <= X"93";
B_next <= X"00";
when X"d8" =>
R_next <= X"89";
G_next <= X"a4";
B_next <= X"00";
when X"d9" =>
R_next <= X"9a";
G_next <= X"b5";
B_next <= X"03";
when X"da" =>
R_next <= X"ab";
G_next <= X"c6";
B_next <= X"14";
when X"db" =>
R_next <= X"bc";
G_next <= X"d7";
B_next <= X"25";
when X"dc" =>
R_next <= X"cd";
G_next <= X"e8";
B_next <= X"36";
when X"dd" =>
R_next <= X"de";
G_next <= X"f9";
B_next <= X"47";
when X"de" =>
R_next <= X"ef";
G_next <= X"ff";
B_next <= X"58";
when X"df" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"69";
when X"e0" =>
R_next <= X"23";
G_next <= X"09";
B_next <= X"00";
when X"e1" =>
R_next <= X"34";
G_next <= X"1a";
B_next <= X"00";
when X"e2" =>
R_next <= X"45";
G_next <= X"2b";
B_next <= X"00";
when X"e3" =>
R_next <= X"56";
G_next <= X"3c";
B_next <= X"00";
when X"e4" =>
R_next <= X"67";
G_next <= X"4d";
B_next <= X"00";
when X"e5" =>
R_next <= X"78";
G_next <= X"5e";
B_next <= X"00";
when X"e6" =>
R_next <= X"89";
G_next <= X"6f";
B_next <= X"00";
when X"e7" =>
R_next <= X"9a";
G_next <= X"80";
B_next <= X"00";
when X"e8" =>
R_next <= X"ab";
G_next <= X"91";
B_next <= X"00";
when X"e9" =>
R_next <= X"bc";
G_next <= X"a2";
B_next <= X"10";
when X"ea" =>
R_next <= X"cd";
G_next <= X"b3";
B_next <= X"21";
when X"eb" =>
R_next <= X"de";
G_next <= X"c4";
B_next <= X"32";
when X"ec" =>
R_next <= X"ef";
G_next <= X"d5";
B_next <= X"43";
when X"ed" =>
R_next <= X"ff";
G_next <= X"e6";
B_next <= X"54";
when X"ee" =>
R_next <= X"ff";
G_next <= X"f7";
B_next <= X"65";
when X"ef" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"76";
when X"f0" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"f1" =>
R_next <= X"50";
G_next <= X"05";
B_next <= X"00";
when X"f2" =>
R_next <= X"61";
G_next <= X"16";
B_next <= X"00";
when X"f3" =>
R_next <= X"72";
G_next <= X"27";
B_next <= X"00";
when X"f4" =>
R_next <= X"83";
G_next <= X"38";
B_next <= X"00";
when X"f5" =>
R_next <= X"94";
G_next <= X"49";
B_next <= X"00";
when X"f6" =>
R_next <= X"a5";
G_next <= X"5a";
B_next <= X"01";
when X"f7" =>
R_next <= X"b6";
G_next <= X"6b";
B_next <= X"12";
when X"f8" =>
R_next <= X"c7";
G_next <= X"7c";
B_next <= X"23";
when X"f9" =>
R_next <= X"d8";
G_next <= X"8d";
B_next <= X"34";
when X"fa" =>
R_next <= X"e9";
G_next <= X"9e";
B_next <= X"45";
when X"fb" =>
R_next <= X"fa";
G_next <= X"af";
B_next <= X"56";
when X"fc" =>
R_next <= X"ff";
G_next <= X"c0";
B_next <= X"67";
when X"fd" =>
R_next <= X"ff";
G_next <= X"d1";
B_next <= X"78";
when X"fe" =>
R_next <= X"ff";
G_next <= X"e2";
B_next <= X"89";
when X"ff" =>
R_next <= X"ff";
G_next <= X"f3";
B_next <= X"9a";
when others =>
-- nop
end case;
end process;
end altirra;
ARCHITECTURE laoo OF gtia_palette IS
begin
process(atari_colour)
begin
case atari_colour is
when X"00" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"00";
when X"01" =>
R_next <= X"0e";
G_next <= X"0d";
B_next <= X"0e";
when X"02" =>
R_next <= X"1d";
G_next <= X"1d";
B_next <= X"1d";
when X"03" =>
R_next <= X"2e";
G_next <= X"2d";
B_next <= X"2e";
when X"04" =>
R_next <= X"3e";
G_next <= X"3d";
B_next <= X"3e";
when X"05" =>
R_next <= X"4f";
G_next <= X"4e";
B_next <= X"4f";
when X"06" =>
R_next <= X"5f";
G_next <= X"5e";
B_next <= X"5f";
when X"07" =>
R_next <= X"70";
G_next <= X"6f";
B_next <= X"6f";
when X"08" =>
R_next <= X"7a";
G_next <= X"7a";
B_next <= X"79";
when X"09" =>
R_next <= X"8b";
G_next <= X"8a";
B_next <= X"8b";
when X"0a" =>
R_next <= X"9c";
G_next <= X"9b";
B_next <= X"9b";
when X"0b" =>
R_next <= X"ad";
G_next <= X"ac";
B_next <= X"ac";
when X"0c" =>
R_next <= X"bc";
G_next <= X"bb";
B_next <= X"bb";
when X"0d" =>
R_next <= X"cd";
G_next <= X"cc";
B_next <= X"cd";
when X"0e" =>
R_next <= X"dc";
G_next <= X"db";
B_next <= X"dc";
when X"0f" =>
R_next <= X"ec";
G_next <= X"ec";
B_next <= X"ec";
when X"10" =>
R_next <= X"35";
G_next <= X"00";
B_next <= X"00";
when X"11" =>
R_next <= X"40";
G_next <= X"05";
B_next <= X"00";
when X"12" =>
R_next <= X"4f";
G_next <= X"14";
B_next <= X"00";
when X"13" =>
R_next <= X"5f";
G_next <= X"25";
B_next <= X"00";
when X"14" =>
R_next <= X"6e";
G_next <= X"34";
B_next <= X"00";
when X"15" =>
R_next <= X"7f";
G_next <= X"45";
B_next <= X"03";
when X"16" =>
R_next <= X"8e";
G_next <= X"55";
B_next <= X"13";
when X"17" =>
R_next <= X"9f";
G_next <= X"66";
B_next <= X"23";
when X"18" =>
R_next <= X"a9";
G_next <= X"71";
B_next <= X"2d";
when X"19" =>
R_next <= X"ba";
G_next <= X"82";
B_next <= X"40";
when X"1a" =>
R_next <= X"ca";
G_next <= X"92";
B_next <= X"50";
when X"1b" =>
R_next <= X"db";
G_next <= X"a3";
B_next <= X"61";
when X"1c" =>
R_next <= X"ea";
G_next <= X"b2";
B_next <= X"70";
when X"1d" =>
R_next <= X"fa";
G_next <= X"c3";
B_next <= X"82";
when X"1e" =>
R_next <= X"fe";
G_next <= X"d2";
B_next <= X"91";
when X"1f" =>
R_next <= X"ff";
G_next <= X"e3";
B_next <= X"a1";
when X"20" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"21" =>
R_next <= X"4b";
G_next <= X"00";
B_next <= X"00";
when X"22" =>
R_next <= X"59";
G_next <= X"09";
B_next <= X"00";
when X"23" =>
R_next <= X"69";
G_next <= X"19";
B_next <= X"03";
when X"24" =>
R_next <= X"78";
G_next <= X"29";
B_next <= X"12";
when X"25" =>
R_next <= X"88";
G_next <= X"3a";
B_next <= X"23";
when X"26" =>
R_next <= X"98";
G_next <= X"4a";
B_next <= X"34";
when X"27" =>
R_next <= X"a9";
G_next <= X"5b";
B_next <= X"45";
when X"28" =>
R_next <= X"b3";
G_next <= X"65";
B_next <= X"4f";
when X"29" =>
R_next <= X"c4";
G_next <= X"76";
B_next <= X"61";
when X"2a" =>
R_next <= X"d4";
G_next <= X"87";
B_next <= X"72";
when X"2b" =>
R_next <= X"e5";
G_next <= X"98";
B_next <= X"83";
when X"2c" =>
R_next <= X"f4";
G_next <= X"a7";
B_next <= X"92";
when X"2d" =>
R_next <= X"fd";
G_next <= X"b8";
B_next <= X"a3";
when X"2e" =>
R_next <= X"ff";
G_next <= X"c7";
B_next <= X"b3";
when X"2f" =>
R_next <= X"ff";
G_next <= X"d7";
B_next <= X"c2";
when X"30" =>
R_next <= X"3d";
G_next <= X"00";
B_next <= X"00";
when X"31" =>
R_next <= X"49";
G_next <= X"00";
B_next <= X"00";
when X"32" =>
R_next <= X"57";
G_next <= X"05";
B_next <= X"0b";
when X"33" =>
R_next <= X"68";
G_next <= X"15";
B_next <= X"1b";
when X"34" =>
R_next <= X"77";
G_next <= X"25";
B_next <= X"2a";
when X"35" =>
R_next <= X"88";
G_next <= X"36";
B_next <= X"3c";
when X"36" =>
R_next <= X"98";
G_next <= X"46";
B_next <= X"4c";
when X"37" =>
R_next <= X"a8";
G_next <= X"57";
B_next <= X"5d";
when X"38" =>
R_next <= X"b2";
G_next <= X"61";
B_next <= X"67";
when X"39" =>
R_next <= X"c3";
G_next <= X"72";
B_next <= X"79";
when X"3a" =>
R_next <= X"d3";
G_next <= X"83";
B_next <= X"89";
when X"3b" =>
R_next <= X"e4";
G_next <= X"94";
B_next <= X"9a";
when X"3c" =>
R_next <= X"f3";
G_next <= X"a3";
B_next <= X"a9";
when X"3d" =>
R_next <= X"fd";
G_next <= X"b4";
B_next <= X"ba";
when X"3e" =>
R_next <= X"ff";
G_next <= X"c4";
B_next <= X"ca";
when X"3f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"d9";
when X"40" =>
R_next <= X"38";
G_next <= X"00";
B_next <= X"27";
when X"41" =>
R_next <= X"42";
G_next <= X"00";
B_next <= X"32";
when X"42" =>
R_next <= X"51";
G_next <= X"01";
B_next <= X"40";
when X"43" =>
R_next <= X"61";
G_next <= X"0e";
B_next <= X"50";
when X"44" =>
R_next <= X"70";
G_next <= X"1e";
B_next <= X"5f";
when X"45" =>
R_next <= X"81";
G_next <= X"2f";
B_next <= X"70";
when X"46" =>
R_next <= X"90";
G_next <= X"3f";
B_next <= X"81";
when X"47" =>
R_next <= X"a0";
G_next <= X"51";
B_next <= X"90";
when X"48" =>
R_next <= X"ab";
G_next <= X"5b";
B_next <= X"9a";
when X"49" =>
R_next <= X"bc";
G_next <= X"6c";
B_next <= X"ac";
when X"4a" =>
R_next <= X"cc";
G_next <= X"7c";
B_next <= X"bc";
when X"4b" =>
R_next <= X"dc";
G_next <= X"8d";
B_next <= X"cd";
when X"4c" =>
R_next <= X"ec";
G_next <= X"9d";
B_next <= X"dc";
when X"4d" =>
R_next <= X"fa";
G_next <= X"ae";
B_next <= X"ed";
when X"4e" =>
R_next <= X"fe";
G_next <= X"bd";
B_next <= X"fa";
when X"4f" =>
R_next <= X"ff";
G_next <= X"cd";
B_next <= X"fe";
when X"50" =>
R_next <= X"2c";
G_next <= X"00";
B_next <= X"46";
when X"51" =>
R_next <= X"37";
G_next <= X"00";
B_next <= X"50";
when X"52" =>
R_next <= X"46";
G_next <= X"01";
B_next <= X"5f";
when X"53" =>
R_next <= X"55";
G_next <= X"0e";
B_next <= X"6e";
when X"54" =>
R_next <= X"65";
G_next <= X"1e";
B_next <= X"7d";
when X"55" =>
R_next <= X"75";
G_next <= X"2f";
B_next <= X"8e";
when X"56" =>
R_next <= X"85";
G_next <= X"3f";
B_next <= X"9f";
when X"57" =>
R_next <= X"95";
G_next <= X"50";
B_next <= X"ae";
when X"58" =>
R_next <= X"a0";
G_next <= X"5b";
B_next <= X"b8";
when X"59" =>
R_next <= X"b1";
G_next <= X"6c";
B_next <= X"ca";
when X"5a" =>
R_next <= X"c1";
G_next <= X"7c";
B_next <= X"da";
when X"5b" =>
R_next <= X"d2";
G_next <= X"8d";
B_next <= X"eb";
when X"5c" =>
R_next <= X"e1";
G_next <= X"9d";
B_next <= X"f8";
when X"5d" =>
R_next <= X"f2";
G_next <= X"ae";
B_next <= X"fe";
when X"5e" =>
R_next <= X"fc";
G_next <= X"bd";
B_next <= X"ff";
when X"5f" =>
R_next <= X"fe";
G_next <= X"cd";
B_next <= X"ff";
when X"60" =>
R_next <= X"19";
G_next <= X"00";
B_next <= X"5e";
when X"61" =>
R_next <= X"24";
G_next <= X"00";
B_next <= X"67";
when X"62" =>
R_next <= X"34";
G_next <= X"03";
B_next <= X"76";
when X"63" =>
R_next <= X"44";
G_next <= X"13";
B_next <= X"85";
when X"64" =>
R_next <= X"53";
G_next <= X"22";
B_next <= X"94";
when X"65" =>
R_next <= X"64";
G_next <= X"33";
B_next <= X"a5";
when X"66" =>
R_next <= X"74";
G_next <= X"43";
B_next <= X"b5";
when X"67" =>
R_next <= X"85";
G_next <= X"55";
B_next <= X"c4";
when X"68" =>
R_next <= X"8f";
G_next <= X"5f";
B_next <= X"ce";
when X"69" =>
R_next <= X"a0";
G_next <= X"70";
B_next <= X"e0";
when X"6a" =>
R_next <= X"b0";
G_next <= X"81";
B_next <= X"f0";
when X"6b" =>
R_next <= X"c1";
G_next <= X"92";
B_next <= X"fc";
when X"6c" =>
R_next <= X"d0";
G_next <= X"a1";
B_next <= X"fe";
when X"6d" =>
R_next <= X"e1";
G_next <= X"b2";
B_next <= X"ff";
when X"6e" =>
R_next <= X"f0";
G_next <= X"c2";
B_next <= X"ff";
when X"6f" =>
R_next <= X"fc";
G_next <= X"d2";
B_next <= X"ff";
when X"70" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"5c";
when X"71" =>
R_next <= X"00";
G_next <= X"09";
B_next <= X"66";
when X"72" =>
R_next <= X"09";
G_next <= X"18";
B_next <= X"75";
when X"73" =>
R_next <= X"1a";
G_next <= X"29";
B_next <= X"84";
when X"74" =>
R_next <= X"29";
G_next <= X"38";
B_next <= X"93";
when X"75" =>
R_next <= X"3a";
G_next <= X"49";
B_next <= X"a4";
when X"76" =>
R_next <= X"4a";
G_next <= X"59";
B_next <= X"b4";
when X"77" =>
R_next <= X"5c";
G_next <= X"6a";
B_next <= X"c3";
when X"78" =>
R_next <= X"66";
G_next <= X"74";
B_next <= X"cd";
when X"79" =>
R_next <= X"77";
G_next <= X"85";
B_next <= X"df";
when X"7a" =>
R_next <= X"87";
G_next <= X"96";
B_next <= X"ef";
when X"7b" =>
R_next <= X"98";
G_next <= X"a7";
B_next <= X"fc";
when X"7c" =>
R_next <= X"a8";
G_next <= X"b6";
B_next <= X"fe";
when X"7d" =>
R_next <= X"b9";
G_next <= X"c7";
B_next <= X"ff";
when X"7e" =>
R_next <= X"c8";
G_next <= X"d6";
B_next <= X"ff";
when X"7f" =>
R_next <= X"d8";
G_next <= X"e7";
B_next <= X"ff";
when X"80" =>
R_next <= X"00";
G_next <= X"0b";
B_next <= X"45";
when X"81" =>
R_next <= X"00";
G_next <= X"16";
B_next <= X"4f";
when X"82" =>
R_next <= X"00";
G_next <= X"25";
B_next <= X"5d";
when X"83" =>
R_next <= X"09";
G_next <= X"36";
B_next <= X"6d";
when X"84" =>
R_next <= X"18";
G_next <= X"45";
B_next <= X"7c";
when X"85" =>
R_next <= X"29";
G_next <= X"56";
B_next <= X"8d";
when X"86" =>
R_next <= X"39";
G_next <= X"66";
B_next <= X"9d";
when X"87" =>
R_next <= X"4b";
G_next <= X"77";
B_next <= X"ac";
when X"88" =>
R_next <= X"56";
G_next <= X"81";
B_next <= X"b6";
when X"89" =>
R_next <= X"67";
G_next <= X"92";
B_next <= X"c8";
when X"8a" =>
R_next <= X"77";
G_next <= X"a2";
B_next <= X"d9";
when X"8b" =>
R_next <= X"88";
G_next <= X"b3";
B_next <= X"e9";
when X"8c" =>
R_next <= X"98";
G_next <= X"c3";
B_next <= X"f7";
when X"8d" =>
R_next <= X"a9";
G_next <= X"d3";
B_next <= X"fe";
when X"8e" =>
R_next <= X"b8";
G_next <= X"e3";
B_next <= X"ff";
when X"8f" =>
R_next <= X"c8";
G_next <= X"f3";
B_next <= X"ff";
when X"90" =>
R_next <= X"00";
G_next <= X"16";
B_next <= X"25";
when X"91" =>
R_next <= X"00";
G_next <= X"22";
B_next <= X"30";
when X"92" =>
R_next <= X"00";
G_next <= X"31";
B_next <= X"3f";
when X"93" =>
R_next <= X"01";
G_next <= X"42";
B_next <= X"4f";
when X"94" =>
R_next <= X"0c";
G_next <= X"51";
B_next <= X"5e";
when X"95" =>
R_next <= X"1e";
G_next <= X"62";
B_next <= X"6f";
when X"96" =>
R_next <= X"2e";
G_next <= X"72";
B_next <= X"80";
when X"97" =>
R_next <= X"40";
G_next <= X"82";
B_next <= X"8f";
when X"98" =>
R_next <= X"4a";
G_next <= X"8d";
B_next <= X"99";
when X"99" =>
R_next <= X"5c";
G_next <= X"9d";
B_next <= X"ab";
when X"9a" =>
R_next <= X"6c";
G_next <= X"ae";
B_next <= X"bc";
when X"9b" =>
R_next <= X"7e";
G_next <= X"be";
B_next <= X"cc";
when X"9c" =>
R_next <= X"8d";
G_next <= X"ce";
B_next <= X"db";
when X"9d" =>
R_next <= X"9e";
G_next <= X"de";
B_next <= X"ed";
when X"9e" =>
R_next <= X"ad";
G_next <= X"ee";
B_next <= X"fa";
when X"9f" =>
R_next <= X"bd";
G_next <= X"fc";
B_next <= X"fe";
when X"a0" =>
R_next <= X"00";
G_next <= X"24";
B_next <= X"00";
when X"a1" =>
R_next <= X"00";
G_next <= X"2f";
B_next <= X"00";
when X"a2" =>
R_next <= X"00";
G_next <= X"3e";
B_next <= X"0a";
when X"a3" =>
R_next <= X"00";
G_next <= X"4f";
B_next <= X"1a";
when X"a4" =>
R_next <= X"08";
G_next <= X"5e";
B_next <= X"29";
when X"a5" =>
R_next <= X"18";
G_next <= X"6f";
B_next <= X"3b";
when X"a6" =>
R_next <= X"28";
G_next <= X"7f";
B_next <= X"4b";
when X"a7" =>
R_next <= X"3a";
G_next <= X"8f";
B_next <= X"5c";
when X"a8" =>
R_next <= X"44";
G_next <= X"9a";
B_next <= X"65";
when X"a9" =>
R_next <= X"55";
G_next <= X"ab";
B_next <= X"78";
when X"aa" =>
R_next <= X"65";
G_next <= X"bb";
B_next <= X"88";
when X"ab" =>
R_next <= X"77";
G_next <= X"cc";
B_next <= X"99";
when X"ac" =>
R_next <= X"86";
G_next <= X"db";
B_next <= X"a8";
when X"ad" =>
R_next <= X"97";
G_next <= X"ec";
B_next <= X"ba";
when X"ae" =>
R_next <= X"a6";
G_next <= X"fa";
B_next <= X"c9";
when X"af" =>
R_next <= X"b7";
G_next <= X"fe";
B_next <= X"d9";
when X"b0" =>
R_next <= X"00";
G_next <= X"2a";
B_next <= X"00";
when X"b1" =>
R_next <= X"00";
G_next <= X"37";
B_next <= X"00";
when X"b2" =>
R_next <= X"00";
G_next <= X"46";
B_next <= X"00";
when X"b3" =>
R_next <= X"01";
G_next <= X"56";
B_next <= X"00";
when X"b4" =>
R_next <= X"0f";
G_next <= X"65";
B_next <= X"00";
when X"b5" =>
R_next <= X"20";
G_next <= X"76";
B_next <= X"03";
when X"b6" =>
R_next <= X"31";
G_next <= X"85";
B_next <= X"13";
when X"b7" =>
R_next <= X"42";
G_next <= X"96";
B_next <= X"24";
when X"b8" =>
R_next <= X"4c";
G_next <= X"a1";
B_next <= X"2d";
when X"b9" =>
R_next <= X"5d";
G_next <= X"b1";
B_next <= X"40";
when X"ba" =>
R_next <= X"6d";
G_next <= X"c1";
B_next <= X"51";
when X"bb" =>
R_next <= X"7f";
G_next <= X"d2";
B_next <= X"62";
when X"bc" =>
R_next <= X"8e";
G_next <= X"e2";
B_next <= X"71";
when X"bd" =>
R_next <= X"9f";
G_next <= X"f2";
B_next <= X"82";
when X"be" =>
R_next <= X"af";
G_next <= X"fd";
B_next <= X"92";
when X"bf" =>
R_next <= X"bf";
G_next <= X"ff";
B_next <= X"a1";
when X"c0" =>
R_next <= X"00";
G_next <= X"24";
B_next <= X"00";
when X"c1" =>
R_next <= X"00";
G_next <= X"31";
B_next <= X"00";
when X"c2" =>
R_next <= X"05";
G_next <= X"40";
B_next <= X"00";
when X"c3" =>
R_next <= X"16";
G_next <= X"50";
B_next <= X"00";
when X"c4" =>
R_next <= X"26";
G_next <= X"5f";
B_next <= X"00";
when X"c5" =>
R_next <= X"36";
G_next <= X"70";
B_next <= X"00";
when X"c6" =>
R_next <= X"47";
G_next <= X"80";
B_next <= X"00";
when X"c7" =>
R_next <= X"58";
G_next <= X"90";
B_next <= X"08";
when X"c8" =>
R_next <= X"62";
G_next <= X"9b";
B_next <= X"12";
when X"c9" =>
R_next <= X"73";
G_next <= X"ac";
B_next <= X"24";
when X"ca" =>
R_next <= X"84";
G_next <= X"bc";
B_next <= X"35";
when X"cb" =>
R_next <= X"95";
G_next <= X"cd";
B_next <= X"46";
when X"cc" =>
R_next <= X"a4";
G_next <= X"dc";
B_next <= X"55";
when X"cd" =>
R_next <= X"b5";
G_next <= X"ed";
B_next <= X"67";
when X"ce" =>
R_next <= X"c5";
G_next <= X"fb";
B_next <= X"77";
when X"cf" =>
R_next <= X"d5";
G_next <= X"ff";
B_next <= X"86";
when X"d0" =>
R_next <= X"02";
G_next <= X"18";
B_next <= X"00";
when X"d1" =>
R_next <= X"0f";
G_next <= X"25";
B_next <= X"00";
when X"d2" =>
R_next <= X"1f";
G_next <= X"34";
B_next <= X"00";
when X"d3" =>
R_next <= X"2f";
G_next <= X"45";
B_next <= X"00";
when X"d4" =>
R_next <= X"3f";
G_next <= X"54";
B_next <= X"00";
when X"d5" =>
R_next <= X"4f";
G_next <= X"65";
B_next <= X"00";
when X"d6" =>
R_next <= X"60";
G_next <= X"75";
B_next <= X"00";
when X"d7" =>
R_next <= X"70";
G_next <= X"86";
B_next <= X"01";
when X"d8" =>
R_next <= X"7b";
G_next <= X"90";
B_next <= X"0a";
when X"d9" =>
R_next <= X"8c";
G_next <= X"a1";
B_next <= X"1c";
when X"da" =>
R_next <= X"9c";
G_next <= X"b1";
B_next <= X"2c";
when X"db" =>
R_next <= X"ad";
G_next <= X"c2";
B_next <= X"3e";
when X"dc" =>
R_next <= X"bd";
G_next <= X"d1";
B_next <= X"4d";
when X"dd" =>
R_next <= X"cd";
G_next <= X"e2";
B_next <= X"5e";
when X"de" =>
R_next <= X"dd";
G_next <= X"f1";
B_next <= X"6e";
when X"df" =>
R_next <= X"ed";
G_next <= X"fd";
B_next <= X"7e";
when X"e0" =>
R_next <= X"1e";
G_next <= X"09";
B_next <= X"00";
when X"e1" =>
R_next <= X"2a";
G_next <= X"16";
B_next <= X"00";
when X"e2" =>
R_next <= X"39";
G_next <= X"25";
B_next <= X"00";
when X"e3" =>
R_next <= X"49";
G_next <= X"36";
B_next <= X"00";
when X"e4" =>
R_next <= X"58";
G_next <= X"45";
B_next <= X"00";
when X"e5" =>
R_next <= X"69";
G_next <= X"56";
B_next <= X"00";
when X"e6" =>
R_next <= X"79";
G_next <= X"66";
B_next <= X"00";
when X"e7" =>
R_next <= X"8a";
G_next <= X"77";
B_next <= X"08";
when X"e8" =>
R_next <= X"94";
G_next <= X"81";
B_next <= X"12";
when X"e9" =>
R_next <= X"a5";
G_next <= X"92";
B_next <= X"24";
when X"ea" =>
R_next <= X"b5";
G_next <= X"a3";
B_next <= X"35";
when X"eb" =>
R_next <= X"c6";
G_next <= X"b3";
B_next <= X"46";
when X"ec" =>
R_next <= X"d6";
G_next <= X"c3";
B_next <= X"55";
when X"ed" =>
R_next <= X"e6";
G_next <= X"d4";
B_next <= X"66";
when X"ee" =>
R_next <= X"f6";
G_next <= X"e3";
B_next <= X"76";
when X"ef" =>
R_next <= X"fe";
G_next <= X"f3";
B_next <= X"86";
when X"f0" =>
R_next <= X"34";
G_next <= X"00";
B_next <= X"00";
when X"f1" =>
R_next <= X"40";
G_next <= X"05";
B_next <= X"00";
when X"f2" =>
R_next <= X"4f";
G_next <= X"15";
B_next <= X"00";
when X"f3" =>
R_next <= X"5f";
G_next <= X"25";
B_next <= X"00";
when X"f4" =>
R_next <= X"6e";
G_next <= X"35";
B_next <= X"00";
when X"f5" =>
R_next <= X"7f";
G_next <= X"46";
B_next <= X"03";
when X"f6" =>
R_next <= X"8f";
G_next <= X"56";
B_next <= X"13";
when X"f7" =>
R_next <= X"9f";
G_next <= X"67";
B_next <= X"23";
when X"f8" =>
R_next <= X"aa";
G_next <= X"71";
B_next <= X"2e";
when X"f9" =>
R_next <= X"ba";
G_next <= X"82";
B_next <= X"40";
when X"fa" =>
R_next <= X"cb";
G_next <= X"92";
B_next <= X"51";
when X"fb" =>
R_next <= X"dc";
G_next <= X"a3";
B_next <= X"62";
when X"fc" =>
R_next <= X"eb";
G_next <= X"b3";
B_next <= X"71";
when X"fd" =>
R_next <= X"fa";
G_next <= X"c3";
B_next <= X"82";
when X"fe" =>
R_next <= X"fe";
G_next <= X"d3";
B_next <= X"92";
when X"ff" =>
R_next <= X"ff";
G_next <= X"e3";
B_next <= X"a1";
when others =>
-- nop
end case;
end process;
end laoo;
| gpl-3.0 | fdcf058456312323741ba89759e225b7 | 0.366213 | 2.201923 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/BINARYZACJA/example_design/BINARYZACJA_exdes.vhd | 4 | 4,094 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity BINARYZACJA_exdes is
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end BINARYZACJA_exdes;
architecture xilinx of BINARYZACJA_exdes is
SIGNAL CLK_i : std_logic;
component BINARYZACJA is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : BINARYZACJA
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
| gpl-2.0 | ef067d693f09beae5738dd11b5966cae | 0.570591 | 4.816471 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/cham_rom_tb.vhd | 1 | 4,355 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: cham_rom_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY cham_rom_tb IS
END ENTITY;
ARCHITECTURE cham_rom_tb_ARCH OF cham_rom_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
cham_rom_synth_inst:ENTITY work.cham_rom_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 434defb29907258a2d38e3a7e3410ab5 | 0.619059 | 4.61824 | false | false | false | false |
223323/lab2 | HDL/source/coregen/dcm108MHz.vhd | 1 | 6,531 | -- file: dcm108MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______385.185____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________27____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm108MHz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm108MHz;
architecture xilinx of dcm108MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm108MHz,clk_wiz_v3_6,{component_name=dcm108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 37.037,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | e59ce54287776ce337a2c534a3c9c0d2 | 0.557189 | 4.263055 | false | false | false | false |
freecores/lq057q3dc02 | design/image_gen_bram_blue.vhd | 1 | 235,872 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: J.40
-- \ \ Application: netgen
-- / / Filename: image_gen_bram_blue.vhd
-- /___/ /\ Timestamp: Thu Nov 06 17:29:19 2008
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_blue.ngc D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_blue.vhd
-- Device : 2vp30ff896-7
-- Input file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_blue.ngc
-- Output file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_blue.vhd
-- # of Entities : 1
-- Design Name : image_gen_bram_blue
-- Xilinx : C:\Xilinx\ISE_9_2
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synopsys translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity image_gen_bram_blue is
port (
clka : in STD_LOGIC := 'X';
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
douta : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end image_gen_bram_blue;
architecture STRUCTURE of image_gen_bram_blue is
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena13 : STD_LOGIC;
signal BU2_N18 : STD_LOGIC;
signal BU2_N16 : STD_LOGIC;
signal BU2_N14 : STD_LOGIC;
signal BU2_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N13 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta25 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta24 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta27 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta26 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta20 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta19 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta22 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta21 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta16 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta15 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta18 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta17 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N1 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta1 : STD_LOGIC;
signal BU2_N1 : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal addra_6 : STD_LOGIC_VECTOR ( 16 downto 0 );
signal douta_7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta13 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta14 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta23 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
addra_6(16) <= addra(16);
addra_6(15) <= addra(15);
addra_6(14) <= addra(14);
addra_6(13) <= addra(13);
addra_6(12) <= addra(12);
addra_6(11) <= addra(11);
addra_6(10) <= addra(10);
addra_6(9) <= addra(9);
addra_6(8) <= addra(8);
addra_6(7) <= addra(7);
addra_6(6) <= addra(6);
addra_6(5) <= addra(5);
addra_6(4) <= addra(4);
addra_6(3) <= addra(3);
addra_6(2) <= addra(2);
addra_6(1) <= addra(1);
addra_6(0) <= addra(0);
douta(5) <= douta_7(5);
douta(4) <= douta_7(4);
douta(3) <= douta_7(3);
douta(2) <= douta_7(2);
douta(1) <= douta_7(1);
douta(0) <= douta_7(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"A4DBB445D2DC4011E7E7B202CD5FFB5B4B625050D094681E0000000000000000",
INIT_02 => X"7B0479FFF5DC655E6D22D8EEA718ADE67FFFFFEBFFF0A71526EBA75D049D1E6A",
INIT_03 => X"C740FC8201D401806FFFCEFCBFF8CAFEBD3CB513675EC1E9D4AA69EAD3E085CF",
INIT_04 => X"69F9E2F1F9FF8E552B4D895DE0637FE73AD5D26A0EAC185F60A62BC4C0B6839D",
INIT_05 => X"9DB50673F3DD91988753CD249065768E628E6484BE56904FF244E8BAD574BA1E",
INIT_06 => X"60E939D1D116A653CFE2481C10CFBECFED1A8DBAE19D64BE45FC506A9D7FED8E",
INIT_07 => X"00E64B1F6F1B6507EA30255A7257C5784BE84600FA4FFC0B64C474D98DE28B68",
INIT_08 => X"EA3D9C5A7FFFD558502ED30CDCE1F6DF5EA472A5F37DFB6CF3B500E018920C47",
INIT_09 => X"7FD87C98960CF02ADBC430E7A37D7FB493EAC0E0BE255737A667289E59BE4067",
INIT_0A => X"112D146C05F92F5AAAFEBF16B76087C43CB540D5D7EADD27EA8B37C70024FFEA",
INIT_0B => X"663C5231CF63A0DF01E85747603C9B27FACAE7F709B2BF2A7FB65015F3E3DD47",
INIT_0C => X"3B6E174766514227B14AC73B909FFFE27FCD9847F1875F5C503C9D17CEBD4FFD",
INIT_0D => X"83518B0C30EF7E806FF40232FCEB9F236AC71F95DE687F4E597AE4CF42DCD7FB",
INIT_0E => X"7CD2148AFEDF9DD3CEB851D46C5C9A0F8066DD9FF151CCAD482A510870A79127",
INIT_0F => X"2FCC55D804276318E5599E1CCD2BB4916A83B1805BADFE0F8C34BB0D6C9F760C",
INIT_10 => X"ADC7133C223A33532E043F808F85290FE9381B24177FCF3E7FF3C012A97F8FCF",
INIT_11 => X"9AE090C08DD2499FD70B4B746415FEFE0BBB749E0F6FE7BD22BBD24826FBFEB1",
INIT_12 => X"CD1B512C4B429BFE0773FC4CBB27EBD1D44FD3752DE2C9D25263B678589DFF2E",
INIT_13 => X"7FFE367FE5E7FBD9A3DB6F2C58878F3D3DE090026761BC8BC9B3E8C0353F090F",
INIT_14 => X"79E7C184C159156A7C035E3AE7A5876C1AC748B7EA24D36FCB226E5701F209FE",
INIT_15 => X"7E581346C267A16EE2BDF6F22CC47D8FD56B6F27C23048FE1A7B9DEF2DFFFA32",
INIT_16 => X"A01CA7035E010137FD8AD00B90C7C7FE5B5E15D89AF11F3C74E7AFC1B6BF5485",
INIT_17 => X"CF4A9172F3FBCEFE5FC28F31A16E4BBEB6C7FF808396F3EA2EAD9EE2ADB08289",
INIT_18 => X"7F953E8D1A13EBC6E78157818FF518F71FC76BD1664090AFF15594462244AFE7",
INIT_19 => X"79400007EEDA4C26860D5AEAE53090719D0715174CDA319B2C40AEFEFBFFBEFE",
INIT_1A => X"09EF9D758F5C0C12A9D389234B04C60AFA10CCF3CFE7BFFE7F63BC63844527E6",
INIT_1B => X"69B7CD8EF5ADFC26BEA05C13CFC0FFFE7F8E738B4B912AE7EE300005DF7AD063",
INIT_1C => X"FCB93EF9AF8F73FE7EA4EFFFA9A19807F918C0CEBE833B72874F662F4680E225",
INIT_1D => X"4B7163F9D9E037DCFD0801FDBFD38FF96B9AFB85E66DD76D88C4490424D75D77",
INIT_1E => X"FEB397730E74397EAD9BF810DE8EE8D65156D1D177E78D8EEA3722BD1FC0FCB2",
INIT_1F => X"C618FC2AA4F3BEE700466D26549A187C2C4A7C9B3FADBBB25FFF7F3732C15E76",
INIT_20 => X"126AB5C537CEF497FE36C9397FC74AB67CFF85D02326503D7E7EFFE13F8F169B",
INIT_21 => X"F493F2BC7FAE28366E1F8D945EB9A3C4F59EE32987E7A623EB8FFFA047E3FF78",
INIT_22 => X"70039C2175016BF73E486DF18FB0C2B63CE55AB177FF3D9D0BA3A1352E5A8903",
INIT_23 => X"CA98813C65FEF1FBE59870698C74EBAC3F2B303B76531FDB5B648CBA7FB12B3E",
INIT_24 => X"A5D1F009473C0DAFED313E45D52F9E75F7E0530D7FE57D3E7C8FEEBC6B938DE6",
INIT_25 => X"5A587877ECBECC3F9B26E3FA9A08553E7F1FFC8A445594352AEC60DEE5FAAF9D",
INIT_26 => X"D67E3AE1FA9380C47FFE1E1D5D086C372335FC86615B6FE0E07119F500C5A86C",
INIT_27 => X"3FFF3C3FFB2F634CA06E3DE46F6B2FC860477AC002829EE0C29C193795D74B00",
INIT_28 => X"6AAC653C051BF0A2E6B24BC40369F4547F6F352D7300D729EB53671C2A57D81C",
INIT_29 => X"AEC034DEF91060EE46DA6E36A942E9616BBD6A8D12EE31A87FFFFE3FE4C6CCEB",
INIT_2A => X"E56F9761F238E4DDEA24AAA8380E6BB43DFFFF77FAA83BB4FDC70BBD7CE3B5E8",
INIT_2B => X"3C27A41BC3DD18F67D3FFFFFFD37C9FEDFC2C7B63AC48C6E0C0331C67DC62F7C",
INIT_2C => X"7F001DFF35635FB5B915FDA52D6AB83C45596D136C7EE87EB9F4F2E47B925BCB",
INIT_2D => X"33D423FD8DF8D0A25DDAE0913A71FFF88486C3746FE3ECD8A7F2F377BA34B03E",
INIT_2E => X"AA3E26EB059EAAFE410C255A119AF3B6A9C43C88BD1E479C7FE794FE57F9FB60",
INIT_2F => X"F212635EC5E8E7FFFEA2DDC44D33EFD41CF50DDE93FFC2BB713FB7E2C9580A7B",
INIT_30 => X"614720D97B5A27CE21B9D6FF7FFBCA5CE9FFDEB7C4BB458D5DD23FEC50FC7BF8",
INIT_31 => X"65FF031D87DDD32DCEFFE6CB993FD30E21C5557E45100AFBD75967335D4D3FAE",
INIT_32 => X"D2FFF92E37FB0BB3B40B66CAFDA709FBAF04921287CC6FE16C573290DCBAFFD4",
INIT_33 => X"C3313F67DC1D96FEDAA0BF45F30D0F916A5F824630EA0F6A796F95EFBFE98D2F",
INIT_34 => X"2AB17A26F83DF7B1201DF57E29C92D8C3987CBC3E8533FDDF7FFFF7B0D2C9933",
INIT_35 => X"93AF860E8ECD98B601D7FBA70DBF1FFEEEFBFD65F423DCC9BD22B77C9FDBD4F9",
INIT_36 => X"32F3FD911127FF7CE67DFC773861E138337C6737FA924B76F2E767933B0CD799",
INIT_37 => X"E3FC3E9AF9A7EB4037DE306FE5A52AFAE77ADE44630857854B358A8AD9F3F0F8",
INIT_38 => X"7380765E2BEF1FA03EE087F5C0DD1787965741122449F5D0270CFECDABE0185F",
INIT_39 => X"0924C977D6B6B7F32704B2D5CE86F8B621347F064C3F7277FEFDDFCF5868E4A5",
INIT_3A => X"8A0B97E55B19FC486329BFD1CECDCCBBF4FDFFC0170FD69F38B0E4433CF86733",
INIT_3B => X"0641BFE4CAF5FA92F8FB1FEB00988933CE244D49A17DD65EC951A2C3FE6067C4",
INIT_3C => X"7E017CDD88A6FDF7E98C1DD8CC493EAB331BC7AFCD3368F564ABA17AF7457126",
INIT_3D => X"F62E18C5C4FF4FFAEDBB8387AB7E18F03902675E5F13FB6E749FFFFA09E54507",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FD44DFE7C3129CF793B70936B58649146E430B7A6A15C7D39686096311A2BEA3",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"3D33A8ECA6B01ED87C570DDFF304318163FCC9F372925EA5F6E1B9B3570482F2"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F9F84AE3A28B7A249FFCFFAE5B62F2BF810648066DEF3748E4BE297D34B5EF5",
INIT_01 => X"A1FF9FE12813A7177C7EBA4A29CAF14DBE0949A3C61CBFF5CDA397AD198A4BB2",
INIT_02 => X"BD391153975B0EDBE7CB307DD948BFF32AEDFDF8A75FF8567FA911EEBFFF5AEB",
INIT_03 => X"3E1021FFC6877FFB57256DF4D3A7472A7EC7B67F1FFFE7B8990FF9FCA093232E",
INIT_04 => X"8207DFFB99E768D25E7FF9FFF37FC7B8CAA7E1F14B3D6A961EA935184142B05E",
INIT_05 => X"3FF71FFFEE1F62471F1FFFF475E361E25F5A714EA9480AAA179CEBFFBC98BFEB",
INIT_06 => X"57A87FFE2CE3A3BECFF163FEE638AD34E907B3FF5D7B3FF121EEA3E7F78E4FA4",
INIT_07 => X"1F8BC94A3A76F93F8ED483F81B5E3FE897CCCBEB271CD2341C3D4CF3D2A343D2",
INIT_08 => X"A22A9BE87993BFC62BF663D7B6B7953E7E190436E2D316863C864FEFF685C738",
INIT_09 => X"96C863B619F45C9679E9F3C2BFFE13035691064FED6F9E3CCF8ED1122CB5BDC1",
INIT_0A => X"417B06264F5E63FF50047C83E2FB22F12FBD7CA7F04E0A44AD988BE4D8D2BE2A",
INIT_0B => X"E556CA7FFB167B91679007DF6DDC180734F733F287CFBC2FB53B03811EF26650",
INIT_0C => X"2809125B77A85604944E9B3BA558BC6850E5F2A599F9ABF863FA950444BA6BFF",
INIT_0D => X"63C727F830FCBDD0570F7E1FE6F88BF4737FF0B4266173FFF3D2E3C5FBC4D96E",
INIT_0E => X"082AFC3C78ED27EC788F8BCAE46A4BF4FC6D384F3F56AE68FCCBEF42277BA03F",
INIT_0F => X"6D04026A87D8BEF17FB839545FEA8AFE5761ECDC9E0E60C05825C9873384FE20",
INIT_10 => X"FF7319FB6FCA9CABD11BEC5764251A54E7DCD27649A9EFE3DC5CFD98ECFB46C8",
INIT_11 => X"EFA4DE6E24D9C5CCD6E64236E5D86F415F81FD6E6E35806A7D917F8D4B0DB11F",
INIT_12 => X"79C8E4B5818ADF5EE66D7C5DBE8A8B12477CFF22FB5DDE0EFFE3DE5CABEFF706",
INIT_13 => X"17467C411EC352F2677C00CEFE3D73C0FFCB1A6C87FA84F7E9AC07FF730CB7A3",
INIT_14 => X"733C6CFF3B85E7CC7F84BFDAA9F56B5140859F030D8124F4478E7BDF1CA7FFB1",
INIT_15 => X"7F0B7086528F1CC4705245EC0057AE83B22862FA1ED7FE3695527F83A6B163A8",
INIT_16 => X"5DEF48DF375237732347565B6BEDFC7321DA78FC6EEE6ED6227C7EF02F84E7EA",
INIT_17 => X"CE30E8F1B31DFBA82B71FB7C2C0D2CE8219C7C530A27B7F47F8DB83150FFF616",
INIT_18 => X"52ADF6101C1E25FC23E1B04917686FBFFF98A13DD1CBFF3295DAB50540CF0070",
INIT_19 => X"08CC4B2D626DF41FFFFEE0F86D6BFBAF428C09C0B8BC382DAB3AB20FEE9DF3D7",
INIT_1A => X"FFFFF9769FD4BC98CEEB9E04620F2919C19C944B79FFF92D0057F1D43E61EFE2",
INIT_1B => X"A8E3D787FA5BD7F32709D98A307FEA230A27EE1A5E8BC7EE33127DB2081CEC9F",
INIT_1C => X"DFADC98145FFD5F213B7F953877F67C0755C98D218D87243FFFFFD34DB2DC2EA",
INIT_1D => X"FF67CFA80FD2E7CA0E6AA4256C3025A6DFFFF5D67E7E050A865FB3FC8F018C7B",
INIT_1E => X"03CC1CD22C362328BC3FF3EF6251F974D4297488058419CC898F51C4B2FCC4AD",
INIT_1F => X"67E02FD3A3A5E5F154C7F0FE4E06264BC9531FEC41FCC360D7B70961824B07D0",
INIT_20 => X"736DF8B1E9112DB10FAAFEE339FF5FA447E3B5E70BD0F5B4402127954860579F",
INIT_21 => X"E3BFBCFFEDFF536F93FB862048EFF0524D7B2E1138DAA07A9D8ED7F46899933F",
INIT_22 => X"63FBEE6B52F5FB2064D52C3BF61D564318BCC912E8E0E50A8E51F8F53DD8F1FB",
INIT_23 => X"3647701BA204AD1D4D21FB4DF01E990B65FEB855C496405175458D75E3FCEE43",
INIT_24 => X"2C835328FEDB6872783DF9B14E0A97C3775D5FE017FFE180AFFCA43EE307E5D4",
INIT_25 => X"972E180C452CB33A69764FC957FFE2F6B7FEF7C79867FF2A340086D76806EAC3",
INIT_26 => X"5D64539057EFE11AAFFBF21D8397865013295428F9A9ECB9772CAD545F8FD169",
INIT_27 => X"6FFFDB33D76FC07E51C3A9B51B4E2273A8016B8957D8B796791D5DBBC75E3FF9",
INIT_28 => X"5D84BA96B55DA56C602357B9F5F2B573A5C46D3F55E01DBB5EA5BFD527CFE7DA",
INIT_29 => X"0E7EEFD3F5FFD20EEF6D789F60E8BAFCC7A3FE8EF7CFE5CB9FECE0FDA71DBD0E",
INIT_2A => X"58065BFE36998807021DFD2E968FD4293FD328B44D3D00BE01895D2529F84FA2",
INIT_2B => X"7441F3CB028FEB27FFAC155077395C7E789405BE0F498E722E489738407FF4D3",
INIT_2C => X"FFA5AF5FE12BD7FC467B916A23EEAC23CB444024303FF25C88C8C8FC4C8CE66B",
INIT_2D => X"357B0DAEA2FDA23E419D68C379EFF9ABF4BA347AE3759F76A7A2F8175B1F93DF",
INIT_2E => X"18B75A5B04875F787574FD7988B471507A9F7FA1211F953FFF5F9BDE1AE2BFF8",
INIT_2F => X"084DA3BF2A156FC195313573E7FF72FFFF25536A70E7FFF4044DFA98746ED32D",
INIT_30 => X"B901015607FF06FFFEBEEA47D1AFFF900945868DFB97700189F714CBBEEA4FD6",
INIT_31 => X"FE1C4754DE6BFA7C08D8C65D5CD1EC41EB0F386E6D523F9F927AB9B2C262DE48",
INIT_32 => X"7BFE8BEE2412752FB07E8BC119D82794BCFF5B0974C33ED40F1BB6AD07FFCAFF",
INIT_33 => X"013664A25B6A84046F020E4F0EA5FE6E16942AFDBFFD87FFFEAE1A680047E146",
INIT_34 => X"A8CBFDA1856FF97FB80AF3FB8FF80FE01C508C703D7FDD400729EA771B8373A2",
INIT_35 => X"5890DA258FFD9FC31FA09373E0FDE92A3A98EA7327EF16A9234BB6E866AD4CFD",
INIT_36 => X"23B138E00FFFA63C4D1CEABD21390451BA183D96CDE2CBFDFB9580F324D9F51A",
INIT_37 => X"0A4C76D6616049E178DEDA9BE361CBF9F7FC9D201E73770BF9938445BFFC7BC1",
INIT_38 => X"D1DFD5117696CC6839C710E38ADA7EBC8B65F86997FC7F86EFB213FC3DF1EF62",
INIT_39 => X"B12AF3D4DD289F8D784BB28817F4FEDE93B0CCFE0F2465EA59ECA33F8083FAF5",
INIT_3A => X"C06D59FB37B23FFEB1A7BFFFFF64CDEA0C10F09F24172495899B2D5CB0B06628",
INIT_3B => X"9F857FFFFE85E9B435FBF139A02DE76759B8C6854EC439C3196FDD21FAD4B51A",
INIT_3C => X"4C7A70C1918CAE129794839BFE21CE6FFBF8437656F33FFEF24AE2AAF7C47FFE",
INIT_3D => X"8D017FF81BC951D313E043F621D730AF825F7BD78EA17FE305F03FFFFD0AB08C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"27FB6C8949377770E21D5AD9FF4D839089471FFFFE9B89F842B47F1CBAEF7FE8",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"2EBA60FE38EB814586FFFFFFE43573FE3425E0FC684FFFFBC456D7635EA36D2C"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B21FFFFEF195C7FE1EE27039B217E6FE2FCB1B7D2884238301F791A40417016C",
INIT_01 => X"20FF787F746E179FBFFC45C32904E81C06786924CCCB9B66FADC6C567F1F4A19",
INIT_02 => X"FFF818FF25E5CA77AA9B9F054E29926DFCAEC4C69C0FB879937FB00171E64FFC",
INIT_03 => X"E32D3F86BD75EDB5FC3F7B1B9EBB762BAA7FF006600070BE61423AF0461430BF",
INIT_04 => X"F0670B8A586FFB61E67FF1A2138EF4D83C3F0098F9BC41FFFFF37FFFEB572CDE",
INIT_05 => X"1CFFC33BE58FF5A240F98079177C81FFFFFEFFFFF36FE02F142DFEBF5EA64463",
INIT_06 => X"3F0C68392B1D07FF7F3FFFFFFDFFE0AB8F587E8C66793C8AFC269A6A552B8C37",
INIT_07 => X"447F781C87FFFBFFAAC60D13A9DDDEF4FFF63C68A27ED0D781FFF311833FEA5E",
INIT_08 => X"312B80E8711E3FDE35EB8234B3FCC16FFFFFF21900FF862C589E4C37435F47FE",
INIT_09 => X"3B3DEF4FEA20F6B7FEF9EAB07FFF1F922C94F77D10DC7FFF1423BE7C9374F624",
INIT_0A => X"FFFDD8877FFEEFE86B34BD277DFEFFF8F595300C54E76779962083317366DDEC",
INIT_0B => X"733574AE1E1F7FFDA856A03A5D7C197DAC0A847AF731866BB373E453DB7DAF2F",
INIT_0C => X"85C950CAA7CA5FF6EBF475B044A10330793937453D2DDBA03FFF6FE27FF1889E",
INIT_0D => X"47B0758A8B1DBC7B7D51CFBF7E0CC8F8BFFEA0E07FE5CF4A584C765FDD65889A",
INIT_0E => X"D81411CE2BBEDAFBFFFF80007FEEB08A6323D4387E5B4B95854E7E83B0294FE6",
INIT_0F => X"E313A3E1FFE0F1BE1B4C6EDF3873DBCE70BB9A8EE7A620EFEB9AAED889FA1DDC",
INIT_10 => X"6ACF4FDCBD0E63288F34273DB8AA3367C7EBEF321C8D9C26DB217890D2FCC9FF",
INIT_11 => X"63EA973886278CF3C91BDC93125889FDCBE55BC1E16127FFAC295FFEFFD4AFF2",
INIT_12 => X"BF4E1C202BBC3A307954B015D3DF27EE62C75FFFFFCCB88E1586FFFF3B2AD6BC",
INIT_13 => X"1D0340E343E3FF83794BBFFFFA02B6226CE27FE84403F4563301FC262BC37E17",
INIT_14 => X"C67FFFFFF43C324647D4F8B426E19199614C972C9BC1D81FEBB63CADADD5D19A",
INIT_15 => X"68F7FBE02D68750A839706C268FFCE3FF0FE395575FA6BC39538FAF6E0B9FE07",
INIT_16 => X"8CD5045E7FD4FEED33A031CBF45495BFEEBA9E43C21FFF1E7FFFFFFFF479C08E",
INIT_17 => X"EDCCB852569EB562BFEA2A404B3FF57FFF6FFFFFE80216E01CFFF8D6EE1531BB",
INIT_18 => X"1435C97F5BFD62FFFE3FFFFFE7A6C7C405BFE796FA6CFF4996098CEFFFC13321",
INIT_19 => X"FCBCFFF3D93524AE7DFF60A2BE0146D1C0000C7F0FC732D40574913362759DE9",
INIT_1A => X"7EAF8CCA98F9126473FF8FFF9865E5BD996C872DE487064BFA0DFB7D29E5F3FE",
INIT_1B => X"FFFFFFFF7472198B79707FD3813F1638906254E3EFF3C10CF8FAFFE0B714D528",
INIT_1C => X"EFA1774EAFB3B4EBFC407C5C5FE99F9E5FFAFF40282BCC7A7AC6B705D88E05BF",
INIT_1D => X"47825F433FE5C4DB61FAFC02434BCEB67FED3450D2922EFFFFFFFFFFE0CD7528",
INIT_1E => X"4FFCC0F6CB8F976E61F94F48D9BC6EE9007CF88F15AA8A4C79BEFCB58CA6710A",
INIT_1F => X"77F2558BFB6634D68721F13F16FA0871FBB2682D57E3D06610C9373FFFEBB083",
INIT_20 => X"FE0FF0A4E256F5B8FD323EEFA451B3DDD387686F7FE25D12D77FB19F6C3366DE",
INIT_21 => X"F8BE829F7A73B015C9D64EB3FFC2D02EDA67B76FE4DE53083FFB2F45B50F65D6",
INIT_22 => X"A1B6357FE5BD4EC37D0DAAA1FF13D2B83F8268680D23BB80FFC7E7D8C56DE6D7",
INIT_23 => X"FDBFCB410F0AE33E7F660C2F1FB7FFFFCEFFF74F3ED34F17C365F93BD89D786F",
INIT_24 => X"7E5A4736C766FFFFC1FFCFE2C9F3906F805588F4178E30690642E8FFE50F737D",
INIT_25 => X"07FE609A391213DF0CDFF61547D82933025DF5FB76B3D5FFF8AF8CBDEB566970",
INIT_26 => X"AEFCB0351C95DF54BCE579F7CB2BFF7D940F53B228F57B4861B447C197B5C77F",
INIT_27 => X"63AE57F7223FFEB043BD30FE5E02C9A242D84AA01FFC7C8B1BFF52CB109B8D86",
INIT_28 => X"C0FBF64358768CBA3F2E0E1FFFF6B741A7FCFDA61F7597CEE43FAA2331FCFEE5",
INIT_29 => X"4F34CEFFFFF2172DFCF040BE66115FDCCE3BA1CCA22BFFDE13481789423FFE09",
INIT_2A => X"E99096A3ED225F907825AC7EE7107B00A033E71A56FFFF53E5120948DCC0C75E",
INIT_2B => X"5E82B969FB6956EE070A1FBAABF23989801A45B1FFC2A3B41DFB91FFFF99FD63",
INIT_2C => X"A64F6A7A3FF82AF630ED1743FFFC6C285B90CE70FDA7971AF38DB0D60FA1FFFD",
INIT_2D => X"AF300B01FFFED7CC7F1AC97371C1F2F88642243812CB5F92BDED5D25F7BB3478",
INIT_2E => X"582CBE312A596915898F0DD8592F806B9D7F6F10BCE6F2D8B195D6E1FFCA5B24",
INIT_2F => X"DC6F4F1D6E17AE27BE6F0ADB8CB908D41E0E1E33FF9F3FBCD1F939F8FFFEF7E2",
INIT_30 => X"7EB5166C8C8FCBCC902CEDFEFF118A05D68327F87FFF57EE0E64B56EEB1ECFB5",
INIT_31 => X"C2AE03FECEFFFAD923EDBFF870C044E663FA30EF84742BF9F1D895B5545FEE15",
INIT_32 => X"5E37BFF807EF0BEC7D4587EF86D87A8C8D2ED04FE8F1EEA88C028AF8EBE2A3F9",
INIT_33 => X"277F87E141DCD894920EBBDC15F6E42E9ED8D125D2947C3C5894434C82F5A752",
INIT_34 => X"362C3B2CF043A16E54E0AF1BE8FA1A8B2EF4C5BE0F48693943389FFEF23183D6",
INIT_35 => X"642CAC139398CCF0DDAF95D45A446D9DB39EFFFFF7CD07FA2BFFF4DED97A5511",
INIT_36 => X"A35C941BE3171DA6BE988FFFF5B8E58C26FFFF99D54AEACBB29CFF8269CA356B",
INIT_37 => X"FC885FFFE6A225AA0F77FF0C027193D7B70BFFD3B864B896109E31EC2E792E66",
INIT_38 => X"5653AF028C65EC567975FFC5C9FD31FDA59F4F968641F4BEBA52F156984042D1",
INIT_39 => X"1B8FFFC939FF3C7F713AA2F52763C3EEBB94747EA6E842DD0EB75FFFDC2DA304",
INIT_3A => X"FBB152A7C697CDF4B130F1D0BD6B4B93FD2AF7FFDC313CB27D1D84476EDBE19E",
INIT_3B => X"AC33A2E05260FF0B5D2B5BFAC36833444F3CE126BAD7841046DFFFEEEFE274FC",
INIT_3C => X"413957FDE998105E731AA5B9C92F3813513FFFF9FFDCAD7DFFEF3365568F334A",
INIT_3D => X"0D0D28751DBF4FDF3E7FFFFDFF2239C7FFD61A1150F1C645D9EB767FF2807FE0",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFDFFFFFE9881FFFFD34AD79A9D4559F0D42EFFC729BFD1FF2283E9F163823E",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"C798F5323AA620A0EE6CCB7FF3B3BFF7FCE5F8F89755FCCC091C77DDCEDC4D2B"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"A8F59DAFB7DFBE183ACCD0434636A8C846888FDAEA7CA4DCFFCFFFFFFCA573F3",
INIT_01 => X"9A661FCFA336D65C3A35325CDCFC99E1DF3FFFFFD927ABFCDBD0BA631AE39C3B",
INIT_02 => X"723039837FAF9512BC0FFFFFC602183CE788237F8DE95D2D908E2F61C7FFBC8A",
INIT_03 => X"FCAF7F7F5BD00DBFFFCB17901A9D16432916F65EA7FF970A85F29E6ED479FC50",
INIT_04 => X"FBA9EF4E6735A0AAEFE73E530528B0A180BE04FC8FC14D7C688196F68EB2F6C1",
INIT_05 => X"13234AD52CF82A026E2E6D0383D3C740465BB6F68219493FFC78FF3FE2FE6EDF",
INIT_06 => X"B861B25DC89477C248A9DB3FC540D5F5FCFE7F1FF6CE3F8FDBAD17FB43CF111C",
INIT_07 => X"6DC33D9FA00DAFDFFFFB780FFDD5779FDB1E1B63F694DCF870A2C9CE3017487D",
INIT_08 => X"FFF2FDD651F1238FDCBD072284D210F42C42D7020B190602F58740576563C7BA",
INIT_09 => X"FE6D1FD3ADEECE31AFC83A37A87307FDBE50916F433E89D869556732E1BFBF01",
INIT_0A => X"4391E158B7E47BFD17870357536207BA6E8F12E3EAD4BF01F4BE7D6724D4803F",
INIT_0B => X"652745B1B4EE78666F3647D5D20DBF01FCEC7E0B722B803FFF4F1FC6DE9599BB",
INIT_0C => X"4FCE20A6CB03FD0F45D4FFFAD060003FF8925F45D200E3E89103F036B007F7FA",
INIT_0D => X"14D9FFB58B22013FFF628FE81FC51EE001B92114FB1BDBFFB4A5FC0CC72985E2",
INIT_0E => X"FF507FA6ECF7D9FA59B98617794FD6FF8FF8BB0AB199D02A5F2E88F70AFCFDFF",
INIT_0F => X"FBE9282874BF91FFBEF13494EE56425E3F6BD1E976F5FFFFF605FFE444AD073F",
INIT_10 => X"8C0D336A7B985F167DC4DFE1BD57FFFC3367FF9224F87FFFFA97E3B4F5F355F7",
INIT_11 => X"6C9B76FD3CE3FCF91D03FFA3CABDFFFFE879EBAFDAA7BFEBED1D3D8082DD17FF",
INIT_12 => X"96C7F6B78DFFFFDFD525F988297AA2E97EC5964994BC527DEEF28C6905601D28",
INIT_13 => X"CDB45975BFF8036F337A81D3FB3DC9B223BA9F27E9EAD6DA46FAD8FE7E4CFEFE",
INIT_14 => X"520BD59F743F0EF2171CC472ACD7E9327BC595DE3F88B2F1C287EE508BFFFFFB",
INIT_15 => X"6FA6747F5D2B585C7EA7921FBFCFD62E921FF21A50FFFFF8922D9450D6182F77",
INIT_16 => X"7B9FB55F1D36FEF47D3F62C6D6FFFEF9D284CF1907026FBC929C70D857AFB941",
INIT_17 => X"EC3F2D2773FFFF7786713F8ED10142A29D2AFA10214FDCECEDAB8917A589B1FC",
INIT_18 => X"8CAC3C8AECDE5FDA7E9BFA133ACFC2BE59274A871E49139E7CBFFCFE504C4F92",
INIT_19 => X"030BE7FD0F4A7BFC13EC3A043F2C6C3A3FFFFFFE11124F2D183D6A98117FFE7E",
INIT_1A => X"FCF4A15FC627A80E1FF37FFCFB1D330603FE90234387237EF22DF7953CAE391D",
INIT_1B => X"7FF87FFBBE9BED9AAFFF37D7FF8783F0F47FFE857AE444CC7600616BC0BAFE7E",
INIT_1C => X"E7F237FA804F74F0BAE7F258497FA88221EF4614BE184FEFBD4066A0566B5B6A",
INIT_1D => X"CCBFF8F82911D24383A61FEF2DD67F3FE9A9223BC5D8A2A47F83FFFFDFBB4485",
INIT_1E => X"D6B6FE3401D2BF27F01C3ACE0A5196425FC7FE7F799DF18331EBE747BFF04AF2",
INIT_1F => X"FFE353716DD551405F9FF81FFFFF37497BF9EF3AFFFE91F8D37FDFF1BEA3FCC7",
INIT_20 => X"3FDFF09FFF2E06BDFFB0E44E7FED2BF8C5FD5B1B1A3BC8C6F1C8BF2A8144D7B7",
INIT_21 => X"FFF461B4FFC049FF143FB0A933A959C6BD3C7BBD1026D7D7FD9A0B323638F1BA",
INIT_22 => X"F17F2D2EAC4B91C7592373FF7F69C1FFC7197CD329E199A67DBF08187F754021",
INIT_23 => X"8DB508BD0913A4FFEFB16CDFFE7FDC2A7D7786FC9E5752AC3DB9BEF9FFF137FE",
INIT_24 => X"FBFB68FAFF9993BA7CABFFFDCAA9D6A61F321513FFE47FFE5FCFDE6A950BF5E7",
INIT_25 => X"5EB3FFFE372AB0E1FBD9C737FF05B7FE6C47DA48E70F95EFE240047EC0C372BF",
INIT_26 => X"BAD5240F6F2E07EF3B4FFD489647CFF3F63FD8BF9494626DFC1A1404FFFCF406",
INIT_27 => X"9DCFB170A00DB5F7FEABBC3759147FAFBC4B55FCB3FCC4AC23BFFFFE1F188C75",
INIT_28 => X"FB4BD357C81C5E71DF10629870FCE04060FFEFFCAE65EFDE022A58DFBF8107FF",
INIT_29 => X"FFAF95C471FCE98A7FFFF09FDAA6B5A41D60E3DFFF42E7FDE28E243C2886C6EF",
INIT_2A => X"3FFFC49FF18A616F6E6DB33E7F21F7A4250D62C36F98D9EF7F0D71EFDD4E1A87",
INIT_2B => X"3EEF0ADE341597C927DED30002E3A6FFBEB0AF67F1C1BE69FFFFE014393FE2D0",
INIT_2C => X"DB78BE9891578D3F3C7BFE5FEFE0C5CEFF7FE6583A3FFE003FFFD67F684AFB0F",
INIT_2D => X"1F2277C7FC90E67DBFFFCEFCBE3FBFF87FD97EFEE49438559AFA6BB8BEC90F8B",
INIT_2E => X"FFAF6735DC7FFFFE798E3FFE81817AD45B6AD0763928DF557FE9788B962F588F",
INIT_2F => X"7832BF34FCDEE6C643FD3498F8EE3F8AADD7D0EC8049EB1F9F35547FFF88DDA1",
INIT_30 => X"BEF94D85FDC1FFF217F38269312B841BFD1C2FF1F7AD73D83FB30956FFFFFFFE",
INIT_31 => X"CE7FC785AFCF979B10C51ED5F7A639EDAFBB937FFFFDFF1E5E13FF3CFE5FE433",
INIT_32 => X"ECD944F9E38D7AE3D7CFA65EC07FFE1E6FFF1F3DFE2FE9EA522BBBA1AE8BBFF1",
INIT_33 => X"6EFFC20C07C3FC0E2FFF8E7CBE67E1F7D33782FF648C7DFD6D9F88A49061F851",
INIT_34 => X"2FFFFEFD4F2CB3F8FF71DFFE8899F1E0777C5CFA4E4EAABCAE8EBF71DBA0BF7E",
INIT_35 => X"BFCE1FFF4BCDF1FF66FDA86F1EC9C98F772D54FFC5C904F56FFFF5213E98F9E0",
INIT_36 => X"34BEC2EFED3C6B8DF5522153D6E855FCBFFFFD1FA6AC63F8463EFFFD5782EFFE",
INIT_37 => X"DFB07BD4EB6DB0FFF3E3FF2FB7B903866167FFFEDFDBCFFC7C206FFFC7F6F35F",
INIT_38 => X"CEF3FFB3FEC383F07E7FFEFF7DEDBF3FD8A1DFF6EE8970AECFFD90EEEE6A5535",
INIT_39 => X"7FCBFEFCFF227F1C9B603757F2FAE06E847B5AFC9570A97B3C6A90B7F910A2BF",
INIT_3A => X"34FBBF62300CDE4A6AFAE2F4BDDA1540B42AFB66FF1C9C87D6387FEBCBD8F8E6",
INIT_3B => X"34F0B4F639BD9501F1ED7D3FFFFFA0F7E9668FF80277D3227FE7F879FF24F9DF",
INIT_3C => X"F3DE4689EFFEA75FF583FFFFF1E905487FFFF8FFFEA9FDDFB9C6FD1F777FDE23",
INIT_3D => X"F34BBFFFFDEF022A23FA7C7FFC3FF9DE45CF3F28587BBE1C3FF5B2F7BA9A670C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0DFE8EFFF50BE09F20841FBCAF7DBF297DEFFBE6857DDCAD9F78BF6EF3CF0410",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"55621FEE9A5FBFE3E5EAC7CE8D6846EE99BA1C97DFDFD46E75A7B3FFFD6C369E"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"CBECFF08D6CC5BEAFCEECFFB3FCFED7EFF17FBFFF922C98219FB9EFFC46FBBF7",
INIT_01 => X"7FF998F90BEFE9BE7E97EF9F6328CFB27BFD1CBBBCF7F7FEE1E41FCAF2D1BFF8",
INIT_02 => X"74ABEF0F07C4AFAC0BFCFD2F50B78FE738DF1FCC35F9FF779BCC0DD8315ADFAA",
INIT_03 => X"5BFCE4E65AFF93E5DA741F335F31BF5FB3B92EF69BECF4E7BFEDBAAC53E7F0BB",
INIT_04 => X"FBE2FFD7FC083A1737543F43C9FC95763E3FD75D1FF2FF83FC6FF41FFF063496",
INIT_05 => X"1F123FD3D1E35FB7BE4F5DDC0BF5FF67F76BD9FFFFFF5DCC63FFAD9D1F8FF7FF",
INIT_06 => X"1F4F2997F9F2FFF7DC23CFFFFFFF73FC53FF1A1A6CAFD7FEC1C45C90245C7EEF",
INIT_07 => X"D3D7CFFFFFFF74307FFF9AAC04BFE9FC5A637FCCFA0DFFFFDE093FC7EE7FB7F8",
INIT_08 => X"7FB5CB307965EDFFE58A791435ACFD1FF986FF3074EF47E5BE0F84C89DF8FF23",
INIT_09 => X"BDDAE3AEAA2FFE93FE777F0076C387E14F0F2EE831F8FE0ECB1F6BFFFFFF020C",
INIT_0A => X"F7DB7E24FE7D8E267F0F7B7AD23F7EADDC56FFFFFFFFB4A47FC674833971E3FF",
INIT_0B => X"FF8F34D6A75F3CAA9F33FFFFFFFF44F27F4F9283DF01F7FE952CA8D7257FFD3F",
INIT_0C => X"1F89FFFFFFFFD8CE7FDDF636D429F7FEC423C13826FFFFAFF9657C007A01BE84",
INIT_0D => X"47D96A17219DFFFDE775C09C625CE3BFF9A4F806BEE05DFB57DF891C43A73E49",
INIT_0E => X"5D299DC10C1EF12FF47B78F61CFC16F4AFFF806AFE9F3BFF1F037F87FFFFE216",
INIT_0F => X"EE32F18E5FA623CD2FFFF2214CF73BE5DC5E5F4BFFFFF6123FE0A2FC35FFF7FF",
INIT_10 => X"AFEFF6AC49273DF6FDEDD4B1FFFFFBD01FC3703E5ABFE7FC50C7C8BE0D9B79AF",
INIT_11 => X"F973964CFFFFFEB83F2D0B1F5CBFD7F797E7B5978E9F542FE5EDF1298E253D5C",
INIT_12 => X"7F1C20D651FFF7E7CF5FBAADB159301FD9E7F9A6061FEC5DAFEFF291852F7FFF",
INIT_13 => X"58DFC49D9D1F435F85CFFC2A0760EC606FFBF5C34253FFFF772206B8BFFFFF96",
INIT_14 => X"3B63FFA257A952908FF8FDCFB9DFFFE86EBC050A4FFFFFE47F28B9ECF2FFB7F3",
INIT_15 => X"76FCF41944E5FEFF04AB858E6FFFFFF67FD04E264CFCAFDED6FFEC498B4E7E57",
INIT_16 => X"B56341DE53FFFFFC7F88799EA1FADFCCB35ECAD0084F639C6587FEF79F90914E",
INIT_17 => X"7030E05819F9DFA5ABFF7491E05E75E604B7FC45FFD1369D89BDF88A9AE5FF5F",
INIT_18 => X"91BD0A88167DB32D908FDEF2FCF986DCF79BEB67B5D3FFFE40FA97E8C8FFFFFE",
INIT_19 => X"1A8FD510FDB34BDB6FD3E783B52BFFF8FB46E0840DFFFFFE763C68D0FFFD7FF2",
INIT_1A => X"F7FBFFFEC911FFFFF928E22191FFFFFE72CD6AE6A7FF5FF5EB7A292D6FFEEA4B",
INIT_1B => X"BE265A6AD3FFFFFE7A03667B03FEEFE376C3C4A7DDBD5A6C0D47FF70FE3B5A9A",
INIT_1C => X"78E8F71FAFFCFFA78DC98C51115CDB06B692FD02FEB92EF3A9E7FFB4D773FFFC",
INIT_1D => X"11495ECC327D2FB9489F48BAFEBE6E4317FFF0A5D666FFFC3FA3CED4E2FFFFFE",
INIT_1E => X"B08654C7FF3D214BD1FFF7E0D786FFFF5D6B1C67A2FFFFFE7196CFB757FBFF9F",
INIT_1F => X"A7DFF8D2ACBFFFFFEF96208FD7FFFFFE61BEBC9847FBFFF39297E607BDFEAD1F",
INIT_20 => X"9EE51F064FFFFFFE27141ABF8BFBFF3C4A6FC76155EE32B502FCFDCFFC7CCED0",
INIT_21 => X"591C39A3DBF3FF01654FF1C747FEAE2C36DB8B0D7CB9AF9C17EF7F417C87FFFF",
INIT_22 => X"5A3FEDB5E4FB9B688FBEA2447BBC5D8CFB33FFC757A5FFFF0F20D6FAADFFFFFE",
INIT_23 => X"CBF991117A3F221DE9FBFFC058CEFFFF8F74AE1913FFFFFE59BCB0DAFFF13E63",
INIT_24 => X"2DF7FFF1D546FFFFFFB2626E60FF0000213350127FF13F288B13DFCBF9183868",
INIT_25 => X"FFA24E51DCFF00003FA5179B7FFF3FE15B91EE57482F222EB62D39ADB53FA47D",
INIT_26 => X"5B3688F6FFFF3F9F1031CB0C93840134DE08D713FB8FF2FF1AFCFFFECFDEFFFF",
INIT_27 => X"EFF8EEFFAE331A4E81B40E577A17EA3FE97DFFFFFAD2FFFFFE2790AFD3FF0000",
INIT_28 => X"135FB32B762FD69F1F7FFFFF4913FFFF39E8EF2133FF00004BCD4E15FFFF3F0D",
INIT_29 => X"FEFFFFFF9B99FFFFBB0DF421AEFF3C000B5B7793FFDF3F73069F4FDF7FC6466C",
INIT_2A => X"00000000000000000BF11F07FFCF3F8CDDFF8FBFEF1708AB6B91EF9BBC47FB9F",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"6C138C8803438F8D4EA5B5FC2DCFFCDF43C06CFAC95389A80000000000000000",
INIT_02 => X"75AC3C003CBFF9FD4BC0945497F547A07FFFFFE9FFFD20D0768687BFCA039FF1",
INIT_03 => X"DC0268442E0BEE5E47FECF6BDFFFF308B4423C12831F7D303333E7CD18E4CEDF",
INIT_04 => X"63FD767C7DFFA06176833C22D3778B5D06E63164F1C94673192A7C033DB973BF",
INIT_05 => X"15CCA89B7DAB392F009C3CFDB6B6ABD1C72DB70312F8603FF002887C21F6FDDE",
INIT_06 => X"80F6F8CE1429899B648A8C0300B27EBFF846887C3E84D89E6478E90455FFCA50",
INIT_07 => X"71B6C3006B915BBFFA4CE03C3332D19E54509FF8071FF1128A83DB5EBBF96E2E",
INIT_08 => X"FC41B83C31D397FA629E9F0E6F59F6F5A53CD6FABF397D26834D001D0A69AC91",
INIT_09 => X"7DC8C5EC64A9BB3BC17CAEF8771BDFD3E319000E377CCCB3566D598049BB9FDF",
INIT_0A => X"73BDBD1B4DDC1FE6BD3BC01E59A39B24558D1202C171D89FF5C6E8381B081E3C",
INIT_0B => X"C38FFC30180E765716A7E300635D9C9FFD86C8080F6AFF1E7F56032D7EAA3F8F",
INIT_0C => X"6060EB0063405C9FE886180407CFFFFC7FB22BE9FFFBBFC332BC430C16CF9FFF",
INIT_0D => X"F097F403C33FFFFE7FE53BB53D03FF811A80C00C97BDFFFF5752F8C0B609A60C",
INIT_0E => X"7FED5901999FFC23DCC74EF27A9AE17F178BEC8039C7606F0713AE0075E36D9F",
INIT_0F => X"E1834EFA07CAEE0D790F1E00F640D03A2C840F801C6C6EBFF2B3040355AFF8F2",
INIT_10 => X"614EF30077DCDEE5A80A4280837D79BFD7BB0422C24FF7FE7F709D60EBFFFE91",
INIT_11 => X"26CC46C08ABF7DBFFDB8447256D7F6FE7F77B65BC89FFFF51338CC7A03DB6728",
INIT_12 => X"E4584E221C23F1FE7FFB31611957F7AACF7CCC72099E7B623B6AB00046D72ED6",
INIT_13 => X"7FFF67CE6257FFD21CF81022ED03D26A7940F700DE3C70AC641374C03F95A0BF",
INIT_14 => X"78E03E01EEE4B66BFB204834F2E745B491CDC2B1E73509DFC2635F8FB99DF7FE",
INIT_15 => X"FEE19B00D7CAECFFDCCCE908E3CA6C5FF2705FC1D19937FE37FCD60FED7FBFFF",
INIT_16 => X"E2E1E527C2EBBB6FC591CF09E3BA3FFE47FF505F3E7F2EFD40E050009B307800",
INIT_17 => X"9409CE7121FDFFFE3F0CC31E1DBD96FFE4C00001F7E904EDFD1F73E19C37B8E7",
INIT_18 => X"7FEF02F281E757FFEA000001BFBB1CBBE389ABF01B2854CACEA5FA701E9CACAF",
INIT_19 => X"9D800001FFD870AAF07916A31D57254060A6A1989C686FB74424E0918FFFCFFE",
INIT_1A => X"B33FBB7778A8C87CB67A07071BECE9A7CDA4C0917FFFDFFE7EE00C8F07CBFFF9",
INIT_1B => X"3AB5BD6EAB4200AF30CA4072CFFF3FFE7EF7F78B8DF3F9FAF74000015FA01F24",
INIT_1C => X"F36300E49FF07EFE7F52D7AFCDD398AAE4A0C0017FB89ED77F5F8419781DB84D",
INIT_1D => X"37FFD26CED9D136FFA5000001FC04ACEEB2FF206FAFC1A5BFBA839A6A5B087AE",
INIT_1E => X"FF3800020EB461037D1CFE47469B23A154067404FF34B9DEF7E41C813FFD75FE",
INIT_1F => X"CB36FF91A5BC3B5A78A16913D5F9285FC80580BCFFD67BFE61FE12054CFE4667",
INIT_20 => X"5C3ECC379EEFB13BFF9301167FF1BFFE63FFC3D6CA38A8AE7E2800009E045EF9",
INIT_21 => X"708FF3F2FFC4DDFE71FF9301F1D10A089EA81CC86FB79D2749CDFEE63EE4D928",
INIT_22 => X"7FFFB44D4BA986A603001E0077ADE388FF9C77652F378C0DF6F5443B06091FB7",
INIT_23 => X"99DF9E00D1DE2C7BC092F3AD441422A678596E626F3CF9A467E82034FF2EAFFE",
INIT_24 => X"E7346BEDA2576F94C52A0D857F5BBE19A058F84CFED4F6FE7F7FCC2428CB1FE4",
INIT_25 => X"89EE46624A2CD54B0DBE78F47CD012FE7FFFC7FEE58F88CEA53BE0C0ACFF9FBD",
INIT_26 => X"968C2CFE038E4F3E7FFFEF8FCC2568C90569FF60C7E597BA6224FB78A611E969",
INIT_27 => X"7FFFFEBFFA3A941EB6253E13489537EB2E0E54BF51FD242C696D89AFBDFA4D34",
INIT_28 => X"B451E637E66D5AB6198DFE22F51C189228B5FD7FA62E6B90AACAD865C518B6C6",
INIT_29 => X"DE6FDB0D76D8576AB0E5F9F462EBC5F9821EF595929463E67FFFFC9FF97E8E3E",
INIT_2A => X"B70A47DFF2C86CE64EBE62A9CE67FD647EFFFFBFFD73838499C903368A0C438F",
INIT_2B => X"EE1EBE760AC76B2E7EBFFFFFFF8693E01FED04CCB1A2B45483BE1E6281EBDCC3",
INIT_2C => X"7FD95DFFAFF96B84FFDAF922E991BE3544FED89C3B0E1AB0F11F759F73A9B8F2",
INIT_2D => X"1FCE348D0DEFA423C4503A04FE9315FD9098E1CE4E4A0B93BC5841A7B9341F86",
INIT_2E => X"EE0A1C1C2C34A3F9B5F5DD8EC6524752D827490B20EA97CA7FF5E5FF97F584CB",
INIT_2F => X"2641AA7066D4E7DFF9328F32678A17983EEA30BF7FFF9611BFFEB49746F162BF",
INIT_30 => X"F6DB55D79ECE3FEC653D7479FFFF35FEF0FF4AD8A65EB919A3EBED1A1299E4FC",
INIT_31 => X"093F04AF7FA0810EF1FFEB6FB63D36951FCA0EF205F09DFC36CEE3ADDB89279C",
INIT_32 => X"E1F9F4C657FD5D220D420A18BD4AECFDCA6678EECF97F7AB9C515C8DAAA8AFDE",
INIT_33 => X"334534D0BFED79F8AB5BA1C195D717C4CC52313A3AE35FAC172FD5C47DBBB9CF",
INIT_34 => X"43518EA50246DFD8E25589F656C79ECE686FCB0ED8785EBFE0F0F95215107FA3",
INIT_35 => X"1A37B8DAB5F6FDDA53B7FC2EFC173FFDF077FF81A95EE3925C4DF7BFBE4EF5FE",
INIT_36 => X"00FAFCF4DD3B0FCFF8FBFF48551AF6E1FC42B60A47C5FEFE378F63F29D6EBFE1",
INIT_37 => X"FCFFFF3078AEF1AF224EC15C23F013D980ABFBA18A0FFFC66D63380381DE7A5C",
INIT_38 => X"BD01E1F265FE22B32BAFBFEFD98B3FDF86F502507C4BFCC82569FFDEC9B8FE57",
INIT_39 => X"6C431853D14A3FD07911EBD2BF9AF6C2561D7FB77F80BB5FF1FE3F0C4B21F4F9",
INIT_3A => X"F692E90C86EBF0826888FFBF944CC89A7BFEDFB8DF25EC6FDD50A23737F2B9AD",
INIT_3B => X"02557FF6D1035823BFF3FFB0FB11F2B7C99FAA8371FE7875DD4C74BFD9FCAFE4",
INIT_3C => X"5FF8FFECB81F7DF7F5486B2010474F82A02D3C37F7F31FE4A603074985F6F8D2",
INIT_3D => X"FAB709FA0F20F7F9AAE77B2F8E0D7FE5441DAC91057E7C785696BFF2B932B57E",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"5C803AAFCF887FE22878E829E4E51F0A49569EF96D05B7627FF89FF02F037FEB",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"D743A0D1E78B584A7E06BF3DE618F6ABA3FF8FE55A1ADFF5FA31C8C36621DA7D"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F9E2FECF88BCF6949FFCFEE41F3AF80FC9E49C2FCCF43F9DBD6CA4FE54AFFE2",
INIT_01 => X"6E7F93F541AF0FB6FE41C98970BE3511A136339FE4BABFE21806D0F0EE3DC85C",
INIT_02 => X"7EDEF07D27EE4EFE831474FFEAF33FE2061D66F3AA67224A7FDDDDDF1FFD2418",
INIT_03 => X"0C04FBFFCEF4BFEA80DBF7F65ECFC89A7FFFF0E747FEA2C7531FBDF4BD192FBF",
INIT_04 => X"42AC0BE9C17FFD883FFFFF7FA77FFD3F36AFF7FAEBE915457F6590293FB3FF00",
INIT_05 => X"7FFF5FFFE9D2A5787233FAF8A615117C3FCA90C6BDBF6E5899873FFFFBB2FFEA",
INIT_06 => X"06D7FFFFC964E7FEBF9E5028F9604C2F1CFD07FE509A7FEEB54097E567DE286C",
INIT_07 => X"BFF5BBB8E4DEF8D4022207FE80E97FE6588327E8DDBEB9126E48BEFFD9D1817F",
INIT_08 => X"3F801FF35CBB7FF0F3B6EFFA18FAC4C67B74C2AF6CC385DD4BA21FFF85C9EB3A",
INIT_09 => X"DC871FD8167C6C1E6F890479BFFE5B65334A8047D13F7D787FCDBF790A37F216",
INIT_0A => X"75FA1805CA3E5BFD4285AD57EC729EE39FCA48623EAD2B97A86E0FECC04E7FDB",
INIT_0B => X"D2610D23F77F32769FE8DF74F45280573AF8C7AC19467FDD0767FFDC78F367B8",
INIT_0C => X"97ECFCC978DEBE542D7D978F6B757F9DAFE77FF0FEFC186C4404610A5F7BEFFF",
INIT_0D => X"1FF9CF687A877E0DA1A9FFC58FFBCD6E3480017381B893FFFBD9F39FFDB47F54",
INIT_0E => X"1EB8FF0A2CF4EB543F0FF3B8C241CFFF7D7C8479FFFF20ACC332E07781FF4F6F",
INIT_0F => X"0EFB85F810BD9BFEFFF254523FF66A9E309FFDCA27A99DAF9E3A2692738B3F90",
INIT_10 => X"FF48A25597E719115A17E3ADFCB6ACD8AAE333178ABEDF75698DFEB513EA39D2",
INIT_11 => X"ABCBFE98E693D151057CBC82A8B75FEFCE97FEEF4FFF676E1D907FF0F87EFFFF",
INIT_12 => X"D30564E892E73FFB117CFE410F70A2A60003003DFB7C1FFFFF93F85417F44CE6",
INIT_13 => X"638EFE1D6F060D16410300F1FF0177FFFFF1D5CCF7F2B13553ECC25B048C11DF",
INIT_14 => X"1D036CC0FBBC73F3FFC16ACC2FF945AD3DEFC8F08B90E89B6BFA07E873AFFF57",
INIT_15 => X"FFF36962A4BFD8559BF856F41C95EA089623660CB18FFFB1CC92FDC91F3844E6",
INIT_16 => X"0E4BAF5AD0C1E066988B4DDDAFDFFE1138A2FD787F50AFA833037EC01FB9E7F1",
INIT_17 => X"49BBDA01F3BFFE7E5C1CFE403F54ADF231637C63E59ADBFBFFF0D030926FFBF0",
INIT_18 => X"56DFFA2E3F2407F473FF0071F0E7377FFFE7C55C7B37FDB4635B2720095752B2",
INIT_19 => X"400CB431601DF19FFFFFFD4B1B6EFC26A98D0CB7A2285BDDF84E96F146FFF9EB",
INIT_1A => X"FFFFFE53BECFBC47C2109C7E0B190BE960D1D6B15D7FF754FECFF2C4BFD963E4",
INIT_1B => X"28CAE009C80EDD24A0C5F1F1A6FFF9829A2FFCBBFFB1E7FC001E7B3C08C24717",
INIT_1C => X"40D3AFF00CFFEC95433FEC64FE968FE87717FF1C1F3930EFFFFFFE38AE09EDEC",
INIT_1D => X"AFAFE971FE7D5FFE7A34C7B9700E89A77FFFF9CF62C0B71A7B855CB42334ADF7",
INIT_1E => X"539FC763CFF1E91DDFFFFC1F1544B6F5B3A7F335663650D28EF99BF045FFED85",
INIT_1F => X"E01F1FFC32DB03700767FC45FCDC49D6F1961FF1F3FFE936B7CFEFA53EFAF8A2",
INIT_20 => X"5AF4F9C1106C4324FF9A5FFF3BFCEAEC87FF5A0D2624F91042B7CCD97017D24B",
INIT_21 => X"289C8EFEFBFCE5D127FC558267A5FA327917B0A23FB099F18C40CFF8F5E925FE",
INIT_22 => X"57FC259DEC67F62E140D595D01BD71E16ACC316DF4B316F8BDA8F9D2EE75D2A6",
INIT_23 => X"258F1C5D21C21F1C40E70C9BFB5B97EC564C7D5F780C7F10249E0CFF47FFF4FA",
INIT_24 => X"DB4C91EBFF479530D5BF3CD18EF5F2218B4CBDFBCFFFF50167FF39C5FA9BF312",
INIT_25 => X"5857381339F23291431B2FF3EFFFF70E8FFF54D2EDBFE87E3227DD6650AEDFF8",
INIT_26 => X"17BE3FEB9FFFF5F99FFCAC032B2FDA1071CEB8B1B6666CE04F12C4BDBFDBDD8D",
INIT_27 => X"1FF955FCB61FE8A2300522D92929C0B23708A021CFED9DBF82393C636E373257",
INIT_28 => X"3F8269245C507BB040F415FDCBFC90B01F1B1F4738FCF04B7A9FEB02EFFFF5C6",
INIT_29 => X"B1E8F141CCFFC7E534F331FF176C95177C23FFC17FFFF6387FF1A5584B7DC466",
INIT_2A => X"7ABF60FE2E8695FE477DFE011FFFE7E7FFE329DA7FDD20BE0078DBB6B5A1BCEA",
INIT_2B => X"F6E0FD3957FFCF1FFFCD115D73DE9BFE014C8D2C8E3F9CFDB1E9C9C20AFFE7A3",
INIT_2C => X"FFC80C01D24F27FE79D7EE4CED8D040E70E6943E197FF64C558A307F80E612EB",
INIT_2D => X"472871C811E538628041C436C75FFCA4EBD4477DAFDFF3F0CB06FD3DCFFFDF3F",
INIT_2E => X"FEAFF9DE34913F0A96ED843DF3FF9191498F33849FFFFCFFFF86A5415EFF4FFE",
INIT_2F => X"69745FB91081EAC600FEFC6E9FFFA9FFFFBA3CD170EBFFF807DBFF2068E3023A",
INIT_30 => X"A80C9F217FFFABFFFF29DA8D3117FFE04FCC003166BF21AF70DFB23A4169DFB9",
INIT_31 => X"FF3F02CAC067FC7C30C73E618074012154FD65BF90C16FCBB94E884EBE0F9630",
INIT_32 => X"030087F05D6D4D0B3FE97A70FFD86FD875DE23DDF271FEA3A72895027FFFBFFF",
INIT_33 => X"E540FA0703E803F81200AA680EFE7CB2AADBB24E7FFE0FFFFF75DDF6003FF5CE",
INIT_34 => X"C84D02B00B27F9519FDC6A2C8FFD5FFFFF4A35FE3CFFF5D44731E6E6B958F260",
INIT_35 => X"6AEA7288AFFB7FFCFD5928FC32FE25CC61D3E66D4141A3659EAA7E79C76D03FE",
INIT_36 => X"DE3B0FFFD2FDE3BE59B7E6EECF56E9B547D29E39EEF827FFF7F61F52F4FBFF80",
INIT_37 => X"2127F12000BD359A01F2F5870379E7FFFD8985E7E9ACBD91727D3686EFFBFFFE",
INIT_38 => X"3452F6117079D7B801E20DD3B601F9ADB35D1126EFFDFFFF07324FFFC3FA9B6E",
INIT_39 => X"D0410D68239B7DC546A163480FFB3FFF166ABFFFFFC9289E10A45CC084EDFABF",
INIT_3A => X"7584EA884FC87FFF32EF7FFFFFB6734E35B400E086C5C2AD9C19284770CCDA47",
INIT_3B => X"E8C0FFFFFF29E49276AB01C0871BBEC73352DAC3CEF284FF96D5011F7D33462E",
INIT_3C => X"7E5300FF606A47696533823BFF78AE0D5FE5838E1986C29998049A7B4F73FFFF",
INIT_3D => X"71A9A05EF10E2BAC43FA83F130A74C397EBA57D9BF23BFFDCD07FFFFFE5C9A70",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"E7DB8F87F09FEDB92BCE9DFB3CEB3FEAB63FFFFFFCB353FC0227001CAD97FF67",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"7710291B3EFF3FA70C1FFFFFF89827FC49C71F011D37FFFC3FEBC89ED4776580"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FEFFFFFF0124AFFE1C020FC737D7FFFF1FFC947D18889C7EFED41F9D38CF5769",
INIT_01 => X"3C0007FE57BFFFFF1FF12FFCCDF1C68FE299779EAF0F37BFBCA1A27EF853BD74",
INIT_02 => X"FFF00700C9681E06695FE0D869FD8D193EEE85303EAFCF3046FFFFFE7E06BFFE",
INIT_03 => X"814BC0DA28FABE9BF991091B5E7FF9EB79FFFFF89FFEFF7E7EBF06F7F77FCF7F",
INIT_04 => X"F8F6B26C0A6DE82221FFFE030F81F83E3FFFFF06529EBFFFFFFCFFFFF3C7DF86",
INIT_05 => X"83FFFC3C1C7FF99C00F9FF9B5A1E7FFFFFFFFFFFFC1FDAA567E401E20A897C0C",
INIT_06 => X"400098E5C77EFFFF80FFFFFFFFFFF8428FC701E2EAAF6EE8FEB439F0C99DD2E2",
INIT_07 => X"7BDF87E07FFFF1FECC2100F0106A1E7CFDA64DDFD1FDE14E7FFFFC6080FFF304",
INIT_08 => X"3A198018A0B5B9BDFCA86FA3D8FE2462FFFFFCDE7FFFFBA078E0BB1C00F8FFFF",
INIT_09 => X"313AC7F3C64226CBFFFFF33EFFFF82582318F27C529FFFFFD80FFE7F8FFBFB67",
INIT_0A => X"FFFFEC06FFFF9A0667D8864B9FBC7FFDF082F00F33F8F83BDBD9830F2018BA23",
INIT_0B => X"0FD9CB81AEFB7FF67C28E03D34FF7FE4B9F987F9A0072283BE7E9DFBF696D6B7",
INIT_0C => X"0AC0E7322D593FD9DFE9F936026A6C4DF86FC3AB7EE8851FFFFFB0E2FFFE3A10",
INIT_0D => X"EC09F9F986F4468D70BB00345AED827F7FFF3F1FFFFAAAAA6F8E749DFF4926F5",
INIT_0E => X"9AFF0DFBF69291FFFFFF00FFFFF7251E34C2E5355FCF96CAF97D807F6A825FCE",
INIT_0F => X"FFD71FFFFFF50B7E2CF08B8FFEF198E7FF3B83006595373EE801B0FB84D98D36",
INIT_10 => X"4DCFE7FFFC7DA1C48FC42702721E277EDA61F00E059EEDFCBFA5BF6EB14EABFF",
INIT_11 => X"FC0FFA5415E12BF1BD81E370092AF2D699830F22A7C993FFA4B7BFFFFFE7DDBE",
INIT_12 => X"D771E3E71950B538FDE59BCCD2D15FF408FBBFFFFF0CDA5E5B813EA75A068488",
INIT_13 => X"1194BB66980EFFD9B80FFFFFFCFE31203216FFFD31C00538C3FE20B2E83CD60F",
INIT_14 => X"1517FFFFF903CA9006D0F4DFA4B89F7E7E83BF6288C137FFFB39C39D1B5EEB3A",
INIT_15 => X"1127EEC4E3441E07FC6EF83FE7FF3FFFAD79C73293CB37E450F4B7C1D2DBFF4D",
INIT_16 => X"0CB47C3EFFF9FF1DD4B6CF4FF3E9097B292D65226B47FFFFFFCFFFFFFF79E694",
INIT_17 => X"B61EC741713CD28DA8DACE256AD7F23FFF0FFFFFF709EADA11FF810E136DC676",
INIT_18 => X"780D39809623A07FFECFFFFFF0DB7DCC2F3ED8E9FC7CF82B48377C1FFFF87E1F",
INIT_19 => X"F95FFFFFEAC9CC367FFF9CE7C00021106F4003FFFFF8383906D6EF61E0F9833C",
INIT_1A => X"7DEF532E6000AEFFAFFFFFFF07FAB30791C0FF6A96B5A18CD293D3F147DBFFFF",
INIT_1B => X"FFFFFFFF73FE6390B72C7FB7F59A72D1B6A1544A5FF1BF1CF6FDFFFF4F3B7856",
INIT_1C => X"FCBD77D97EF91BF1DA41ACE23FC1847CFDFDFFFFD30AABA87DC423DBE071893F",
INIT_1D => X"99633DABFFF9643A47FDFFFC6C8DA3F27FFD2827E27D9CFFFFFFFFFF600F6D71",
INIT_1E => X"97FFFF046E81E7DC7FFA8F20E07FDBC6FFFFFF00E6D1C8FDFC50FF6C72C139BC",
INIT_1F => X"7FF4F34C781F0AE178DFE6A11B5D6DD4FD366BE32E3C2B655719FEAFFFE5CAAF",
INIT_20 => X"FFFFE7A2EE8F32D5FB0840DFAEBAC84E14A9971FFFF9D8CBDEFFC1C1FE76E23A",
INIT_21 => X"E9A8BC80DCC65D2372D7187FFFE832BA34FF3A5B4516C7D07FF19FD7E51764E1",
INIT_22 => X"85EAE4FFE153A366FEAD36D339C7B9087F85602195CBDFFFFFFFF17D8C0F3671",
INIT_23 => X"FE9329F96AD359767E7780202E0FFFFEFFFFF298E1EF5C4FFDA039FD94580976",
INIT_24 => X"7BF2802927857FFF3FFFD0CD3290B2DFF63AF8F96DFC3D45BB5809FC0505D6FF",
INIT_25 => X"03FF2A4DBAD5C8BF1ED4F019F00440263B9E15FAA94096FFF19BD012ED602DE6",
INIT_26 => X"CEFCA62618087F13B65E17F60CF3707F183C6ADCA55C0CCE66E680AF4FD3EF7F",
INIT_27 => X"F6CE7FE6263FC7FD829F33557FAEE0B842378795DFE612AB9BFE9BE7A917DD7E",
INIT_28 => X"7D59F230987825480A33F8A3FFE878ADDFFD6947FA9E4FEC8E7F8FAD4FFFFF09",
INIT_29 => X"7DFCC7BFFFD77F6FFF7867CF95DFBFCC0CFDCB5E3EB5FF4296990FE23C7FFDAC",
INIT_2A => X"D8F65E6FE03B3FE04BB67F6E1387FD16B52D97E04CFFFFE66D415EC7E301A990",
INIT_2B => X"D79CFA4FAB8DD21415153FBCD3FDFED444FDE48FFFFC6E287EEDF1EFFFA9B58F",
INIT_2C => X"B45CCEE39FF03CAC7029E73FFFFFD25233B4366AFDF88B49EBBF4709F6773FFE",
INIT_2D => X"280780FFFFFFA5B44674F018FB5375F65A6BA70FF217BF1D4F1BADC489884D7A",
INIT_2E => X"4C20E736C293A490D32F7EAFAFA7FD1E7D1D77EE8F1013B55AE27797FFF3A390",
INIT_2F => X"157041F6E5DFCABCF8E57206686C6D572B41F3E7FFED42EE5909FFFFFFFF5D70",
INIT_30 => X"F7D25E1A44598231D40B0BFFFFDBF602E3F77FFFFFFFA2FE11EC860B85152531",
INIT_31 => X"6B954FFFFF55574B22A41FFF8F3F9DF87D0FA8F807F860FAD5C04F46DDCFD9B3",
INIT_32 => X"9402FFFFF8E0C9F03D6AB3F29640D1BB26E21CBD17FCCC98EB07EEAA76E6A2EC",
INIT_33 => X"733FFDBC497F68561BFB889347F9EA5A96A0FCB3EAD43A8A9346EEB37C668991",
INIT_34 => X"B3851C93858F95D7565D88AAAD2564D9ECEB5E79F5564A4404B2BFFFFC0F7FF0",
INIT_35 => X"46DFB6ADB4D7C6553E233E4F992BE58CB794FFFFFAFC7FD83FFFE914B0281F59",
INIT_36 => X"1C745BAABDFE447F57245FFFFB3963DC3FFFFC8DB89AF96C0EF57FC28A07287F",
INIT_37 => X"FCCD77FFFDC163263EDBDDA9AD52E0987DA2FFE72BF95EBF2EDDF6A1DCB6B2AB",
INIT_38 => X"6F0BCBAB2C3AFE9904BBFFF6FBF4B80E72FC8647D9340D1704B21C066C12BD4F",
INIT_39 => X"87EFFFF0DBFFC9BCFABF54069769A25704F551B66B2D41BE1F8FD7FFEAB366DE",
INIT_3A => X"FC788A35BC6A8E570E4C36560953B7F31FF86BFFEAA005D4362A8ED441E5CC1E",
INIT_3B => X"1F4C116753327FA9E8ED2FFD06B0C6E87677A468C6EFAE116B4FFFF1F3FFEA1F",
INIT_3C => X"F54FC7FFDCD022D6153E7510FBFF500E771FFFFFFFFC0603FFFB5BF400158063",
INIT_3D => X"58233EA704FF1B393DFFFFFFFF91F8E3FFF3E50572DE31693960879FE954FF9C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFE548BE3FFD7553B7C67B58D4EED3BFFC7F07FC07FEF67C1753C6F2A",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFE01D4EB29B305567BD7BFFEF50FFFE8330EBC1455925667427856BB4DD93F9"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6CC5699FDFD3BE0DF945F0B7BD5B479879FE0A624BFD7B347FFFFFFF3FBD09FF",
INIT_01 => X"79363B38FEDB4C0E64143A00AF7EF8523FCFFFFFBCFD08FFE79F6B909C0C3DD6",
INIT_02 => X"797332FEACF973917FEFFFFF38084EFFC3BEF2136005215049F4E1E0C7FCFFDC",
INIT_03 => X"7F7FFFFF9AF1CE7FDBEACBE2DD9F83FB7C646899BBFFF8747C093583D592AD74",
INIT_04 => X"DB926F35E31592CCA60551F922F213F07EF581C85415912E67441B01D340F5DA",
INIT_05 => X"BC803BA344BDDF43F1174992DBEBF56277D038FB9FEFD871FFF8BFFFCB859F3F",
INIT_06 => X"B029B11C5F98C8CA765C1C01221A78FBFFFD7FFFE14F6FC7FB9A77B06AC3F50A",
INIT_07 => X"71073EF0BC6D2FFFFFFAFFFFAE458FD7E7FB3757E3B6E75D8CBC9FBE5B0DBE99",
INIT_08 => X"FFFFFE2FA68F5FFFFEEE1F2D26AD7838203AC5E27309E134477A9DC5E44585BA",
INIT_09 => X"FD785F2EDA646676A23D6BB24FCDC7FDEED7CDD28B3720BA6AEAFF2327877FFF",
INIT_0A => X"064D0E6A475E13F9C75ED63AAFE8DB70781390574BD8BFFFFE9A3E0EC5E27FFF",
INIT_0B => X"A6579C7ACF1860FC1F14027AF434FFFFFF0A7FFE33667FFFFC442F62B34FFDBB",
INIT_0C => X"1F73E71FF866FFFF8D8BFFF6E04CFFFFFC494FBEE06373F455D7ACF1401DF5FF",
INIT_0D => X"18CAFFFC85B8FFFFF71CFFBC6EFFB8F437767C4B038FD9FFF7D70CF676DEE302",
INIT_0E => X"F8EDFF94C5575DFE94990D4C7E9FF5FFAFC16DF343FEC8323F9CF8965556FFFF",
INIT_0F => X"36CBD79A8C6FADFF8E172DE7A1B9BB6A7E7CCB9209E7FFFFFABFFFEF680AFFFF",
INIT_10 => X"DDF68D4CEC0187E27DC5FEFCB90FFFFEAB9FFFE22847FFFFFB1EFFE5669291F3",
INIT_11 => X"705CB0FD7EF3FFFFC177FF4CEA6FFFFFF895F720663E8FF6FB7FE43C0D7ED5FF",
INIT_12 => X"4693F7E5D9FFFFFFE16FC3697DA807FE8BB6EAAAE27D02FE65E058AEF9606100",
INIT_13 => X"E10CE77AC860BFFD60CB0EBFFB7D8FF016635C90F21AA1F2785DC2BF7FDD43FF",
INIT_14 => X"01E76070FD3F56C26DFCD35F37CF8BCA716BF83F7FDECCFD7EFF827B3EFFFFFC",
INIT_15 => X"93878801911B18A07FE7E6DFFFA572D769FFED557DFFFFFCE7F3ED64DCDBD3F2",
INIT_16 => X"7D3F883FFF9A07D67A3F8390E3FFFFFFE4D8BF22CD379376C223E6F05F7ED3E6",
INIT_17 => X"7FBF264650FFFFFFF4C6FA43DA6A9379C234F238FE479F2BEE8BE1CEC96633CC",
INIT_18 => X"F35FFFA4EECD633E46DEF4BB861FF82C45C16A4CAB26F0707EFFF7FF2E6A4FD3",
INIT_19 => X"BBEAF769E663FCF2E2E196A855E1DE527FFE7FFF6AAB7E34ADFF130178FFFCBF",
INIT_1A => X"EEAF1DAB93E5D8AE3FFBBFFFFAA14CE82BFF1E1EA27FB0BFF0FFFCD4B4ABE43C",
INIT_1B => X"5FF77FFFF9EB76DD9FFC6ECFC07F487FFD67F54245CC823E9FF1FD14AF283FFF",
INIT_1C => X"EFF847F23FFEF4FFE8CFF1B921419B7EF26D3FC91A1CBF1FD7286B3D0C23B8E6",
INIT_1D => X"E77FF8305A4C03FEEDF13F3A9E6F0E77E9B091AD99B4C1921FFFFFFFFC1AF7EA",
INIT_1E => X"51EA3E50900D9FAFF8DE4CB2C1C841D67FFFFFFFFA800D415FFD8721FFFB51FD",
INIT_1F => X"FFBDE0A860B53FD47FFFFFFFFFFC82187FD58F797FF115FFFABFFF6C72FDADFE",
INIT_20 => X"7F3FFF7F7FA68AE5FFED847AFFF927FFE43F99B347A425FF6DA67C0B10273FCF",
INIT_21 => X"FE42802BFFF85BFFEF9F1C2E7F52B5FFF2117B5A0D9E07EFECA2470ABFB0566E",
INIT_22 => X"16DF7C3A2EFD85FFBDEA8A79E74B43FFD75CF47BE7AFC58A7E9FF7FE9E89A20C",
INIT_23 => X"F7F4013D1887E8FFE43C147CF9F37D727E6FFFFD2FE8F415BF45014BFFE9ABFF",
INIT_24 => X"F5FCEC7C7F2E31A27F27FFFD0EFF03AB38BB0B2FFFA99DFF41FFF2A9CFCFA1FF",
INIT_25 => X"010FFFFB435F3AE59D23DF0DFFF617FF073FE244932BE7FFB6A3F37F7C08D5FF",
INIT_26 => X"5D76749FFFC86BFE923FC34CC6DDD1FFF38175FF3CFA785FFB0213D6FFFFD0D8",
INIT_27 => X"EABFDBE4EEDFC5FFF163112F29E2FB2AFF5F243A7FFFEE761C7FFFFE0FD55EF9",
INIT_28 => X"F9E710AFA6B01E83FFF0BE05FFFFF6D41FFFDFFC2E04CCFBDB458A1FFF965BFE",
INIT_29 => X"FFEDF744FEFFF2981FFFB2FFFE43F5EB1D3A3A7FBFA887FEEB7EE9B7FC0580FF",
INIT_2A => X"7FFFD6FFCCB58668F236AEF7BF8F0FFAA4FC7499EBFBF27FFDC57AD3E8E9B8DB",
INIT_2B => X"384A3477FD04A7B603FD63AA69FBF8FF7C59409BCACDBD97FFFFE8307EFFFCCE",
INIT_2C => X"BFFA6CA8FBB1303F3D57D393F6F27F4EFFFFED45BCFFFFFE7FFFF63FF20D7CED",
INIT_2D => X"7F86FC09FC0ACF3A3FFF02EB7CFFFFFE7FE7EDFE1F95BC3583B92EDF7E505FB4",
INIT_2E => X"9FDF231F1FFFFFFE7E007FF8E040397CD8D92FB97C903FA06FFC4A27F9F568BF",
INIT_2F => X"7C0CBFF8FD1EFFF8974A2667FE93BFF9A7FCB4ED11D1E75F7F8B4AB1FE2FA3E4",
INIT_30 => X"4901D3F9FE2AFFFBDFFF98DF74FDEBF7FEC13207FFF4F3B59FCF5732BFFFFFFE",
INIT_31 => X"87EFC21D83FFB887A17C913FFFF4BFD51FC723CF7FFFFFFE7FFFFFF8FEFFF19A",
INIT_32 => X"82988C69FFB13DEE2FFFDCEA5FFFFFFE1FFFE0FE7FF7CAD2420C8BDF993A3FFC",
INIT_33 => X"DDFFF762CF3FFFFE1FFFF0FF7E57F9E9DB1897FFF13D7FF0DD3F1B8053E1BE4D",
INIT_34 => X"1FFFFFFE3F79CFFD3D7DDFFF7FBFFFFDF87F491D3C6D1A95ACEAA54DE7835CFD",
INIT_35 => X"3C62DFFE1BBEFFE9293F4CE6E02BF8D2D0E80E27E3B51E7A79FFF9C91587FE1E",
INIT_36 => X"B9FA408ECD14C9FA5EE99123E1AF6EFC83FFFE4F2963FC063FFFFFFECFD037FD",
INIT_37 => X"3BABB697F42889FF3FFFFF3728A8FC807E1FFFFFCFF22FFEBA53BFFDEFB0FDF9",
INIT_38 => X"FFDFFFDD24897CF07F87FFFF9EDFFFFFD83BDECA87CCFFC21CF9C975AC1BA35C",
INIT_39 => X"7FF7FFFFFDF1FC7C7AA5BF07ABD8FFB465FB93FD656017B6FD1B24BCFED9D97F",
INIT_3A => X"59C9BC045F85BFD43D7F62F6A655BCC13E46481EFF7CC17FC9A0BFF36B9D8DC8",
INIT_3B => X"59FD20F4A997DC807F382233FF7C19BFD7C39FFFCA60F9627FFFFFFFFF42FE3C",
INIT_3C => X"BC2C2953FFFF5CF3ECBA8FFFFA0514A87FFFFFFFFF3BFE3EADDCBF9F870FBFBD",
INIT_3D => X"F8F78FFFFC9365065FFDFFFFFDDFFE3E9A267FB44009FF87B0F037F49D74BC8E",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"73FC7FFFF22FFF7E8850FF3DE00FFF31EAEE8FFEF7FD1B8FB849EFCC77FF27BF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"D436FFFDF9F1FFB0C3EE4FF24BF1818D5E6CD3EE3FEFBB3FF59FAFFFFEBAEA36"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"F1F70ED827FA988D5FEA0F36DFFFD187D0A7C7FFFE650F2260FC7FFFF843C7FE",
INIT_01 => X"7FFE98EB23FFE763AE2FF7FFFC3CB38400FEFE9C13EF8FFF0724FFBE89F7FF25",
INIT_02 => X"1737F7FFF80055CC77FFFD1F9FBFFFFE8EF0FF824CEBBFD1E1F30DC258E71C8D",
INIT_03 => X"67FFFA111FBFFFFF04A6FFBB9F8AFF0BCFF93D36F8F31C7A7FFC40525FFFEFCB",
INIT_04 => X"76517F06EF6F7E53EFCA1FB3D91CDB043FFF47F5BFFDFF43C81BE3FFFFFA06A2",
INIT_05 => X"FDEFBFD3FCCF90BB3FBF82AF67F8FFFFE483FBFFFFFD0B5047FFCE03221FDDFD",
INIT_06 => X"3FBFFBBF5DFDFF7FEFCBEBFFFFFEE9C86FFFDCFC4FDFFDFC720EFF2717BF9EB7",
INIT_07 => X"E30BEBFFFFFFF5F67FFF1C1BD91FEBFEE82AFD8BD3C87D77BAFCFFD3E69038F3",
INIT_08 => X"7FCEF31546DFF3FFCDE9E7FAD97FFC6FF9F4FFE3E5F078F75FFF468783FFFF23",
INIT_09 => X"7281FC1E4CFFFD9FFA43FF83F83CF8F7BFFFCB0B17FFFF613D0BF7FFFFFFAF9E",
INIT_0A => X"F7D57FD3FC01F1B63FFF9A152BFFFF7AFE4B7FFFFFFF5AF27F00879EB22FFFFE",
INIT_0B => X"17FFDC5C8A3FFF3C7E447FFFFFFFE4067F811D8175AFFFFF6205AFC0C6EFFC1F",
INIT_0C => X"7EB07FFFFFFFE9247FE0867A2D3FFFFE030982EFC7BEFABFF1CEFFC3F801C195",
INIT_0D => X"7FE371A5BD5FFFFF637B9F4B835FFA6FFC377F957DD863910FFF7BC0309FFCF1",
INIT_0E => X"B8F797D6EC1CFFFFF66CFF35FF0522BA9FFFFA4CAFAFFDFEFF0D3FFFFFFFF9BE",
INIT_0F => X"F406FEADBE1C386B7FFFFEE3D97FFDFE3E56FF87FFFFFA845FF5CEFAAF7FEFFD",
INIT_10 => X"1FFFFE763BFFFFFFF9C4B333FFFFFD5A7FEA922B963FFFFD492F9097EDDCEBFF",
INIT_11 => X"FA2F727DFFFFFFFA7FF91A38AC3FEFFA451FBE4FEF98FBFFD481FE5E3E1C5D84",
INIT_12 => X"7FB73D8968BFCFF58CFFAB9DDE9EDD7FE487FEC7FF3CA6ECB7FFFC157CC7FFFF",
INIT_13 => X"9FFF907AD13E9D3F8D8BFE13FFE2AC106FFFFE3D0617FFFFFC4302067FFFFFEA",
INIT_14 => X"7B2BFD17BFDB031863FFFF06831BFF1F8931FCE13FFFFFF67F9C364FA97FCFEA",
INIT_15 => X"15FFFEA55903FF1FB5CD03A11FFFFFF87F4B6A4726FFDFF51EFF5A19D23F033D",
INIT_16 => X"388240E1CFFFFFFE7F446BDE96FDFFCA387FB533520F96B73C53FD97FFBD5473",
INIT_17 => X"7F74ED9531FFFFEC30FEA5F6524FE39D4A53FCAFFFE7D54647FFF7EB0203FEBF",
INIT_18 => X"4BFF84C4802E9BC49FE7FFDDFFF5761D1F67F7960997FFFCFAF818B827FFFFFE",
INIT_19 => X"61CFFF49FE7ACE1BBAE7FFDE824FFFFC7F8C75AC1BFFFFFE789B5356C3FFFFEC",
INIT_1A => X"65E7FFD16583FFFC7FBBF1140BFFFFFE7C59CCB6BBFFFFE9EBDD6C39D67CC0B6",
INIT_1B => X"7E82291E09FFFFFE7C54F77247FFFFECF80D2E44D9BF8D134C1FFF9DFFFDCE67",
INIT_1C => X"7DB3180A37FFFFEE4C641F2403FF14983B2FFEF9FF7C42B925FFFFCDE311FFFF",
INIT_1D => X"094C894C647E62BC7367BBEDFF7C5373D9FFFFC759F1FFFFFC9EB43319FFFFFE",
INIT_1E => X"43CFA7D2FFFF6A18BFFFF8C5D1F1FFFFBF1180E099FFFFFE7A24F0726FFCFFF6",
INIT_1F => X"B3FFFFE0B698FFFF1E7660804DFFFFFE75DBC3859FFCFF85322FA8BAFDFFA1CE",
INIT_20 => X"0FE77F0125FFFFFE4A4759843FFCFF88124FD12017FEF1B8C3964206FFFB18FE",
INIT_21 => X"12CF649BBFFCFF89123FD028CCFE3D35F30F131DFF7A97B9D79FFFF33E18FFFF",
INIT_22 => X"586BDDF22CFD1CC70903D830FD7E1CDEF781FFF97A80FFFFFF5BB9F95FFFFFFE",
INIT_23 => X"31C1DF14FC7FD69C33F1FFFE8CD9FFFFFFF091F8F5FFFFFE424CA6337FFFFFEC",
INIT_24 => X"59F9FFFE1769FFFFFF8BE11EE5FFFFFE6248EE0CFFFFFFD80F5BFC47A13D0253",
INIT_25 => X"FF94BECF45FFFFFE3CCB01F2FFFFFF2BA0FFDDD3F90590617F977159787FE4BC",
INIT_26 => X"7CD858E5FFFFFF301B34D781E7195B6C5CB043A5B07FF6FE28FFFFFF9771FFFF",
INIT_27 => X"F83FFC5FAEFC1D9E0A708382B1EFEEFF87FEFFFF6B91FFFFFF960F6049FFFFFE",
INIT_28 => X"F05BD4D3B9DFC33FAC7EFFFFA861FFFFFE5160E069FFFFFE7C167CDBFFFFFF33",
INIT_29 => X"DF7EFFFFDAEBFFFF7C51B3E0E5FFC3FE7C8B89A7FFFFFF41E07FBE7F0F167A9F",
INIT_2A => X"00000000000000007CAEE6AFFFFFFF32021F4F7F5E0E0A09C7FB15473FBFE7BF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"1CE3839B05A5B80B20FA63001A9FFF3EBE80D83CC4CFEC260000000000000000",
INIT_02 => X"71866E00163FFE3D6A8048388D0C6EDE7FFFFFE4FFFFE73B44FED75E3F4BE000",
INIT_03 => X"EE8020381AFA5F7E7FFF3FE07FFFECFAB98188132A667EC00FC3E034D87906CA",
INIT_04 => X"47FE0F16F3FFFC8304FF7B4063DDF3810107F09FBB6E1E5A59F8F00016FFFC7F",
INIT_05 => X"990398F52FB08A30001FFC03755818E5EDED180009BFFFFFF280A00014F0407E",
INIT_06 => X"00FFF8C004507D665C80D000053C017FE280A00015817F5E43FF060AB1FFE89E",
INIT_07 => X"5947E3006922C07FE082C800190E31DE603F1FFD833FF6A2730037A401E09F29",
INIT_08 => X"E48350001B33BE5E7C811FF0723BF9A7863C31040CC37D2B03FD0001229012C2",
INIT_09 => X"7EC77BF3AA89FE6D427C9E169EF05FEB03F8000E1A9412A33A5218804813403F",
INIT_0A => X"F23D8307B85F7FFA89F8001E0F756337F2C21700C242807FE50130003386BF1C",
INIT_0B => X"3380003004654652F520F7006193807FE501F00021AC7FFC7F8984EBF68BFC95",
INIT_0C => X"1160F800614B407FF901E0002B27FFFE7FC1CC287D45FE0AF33CC0FC3F8F2FFD",
INIT_0D => X"FD1000002FDFFFFE7FC4D39FFCA7FEB4FB00C003AC726FFEE0ED00C01580C61F",
INIT_0E => X"7FF70E54FDBFFE483F0040F1242A5FFEEE7D0C800909C001B303FF0073F5017F",
INIT_0F => X"1E0040F97CC381F1BECC1E00CBA550038687FF801A5F427FF1300000CC3FFFFE",
INIT_10 => X"D2E2F30062FD1E304E0E7E808503037FF0380021B3DFF8FE7FFB8E2447FFFFCA",
INIT_11 => X"5E0D86C08288827FEC3840713463F9FE7FFBA73C25FFFFF60C38C0794DF1CFCF",
INIT_12 => X"E19840213BEDFFFE7FFC219E058FFFDEC07CC0713D6B6A7FBDFC300049DCCE6A",
INIT_13 => X"7FFFB880638FFFEB00F800219E06F39BFAB55000C09760E76CDE98C03431277F",
INIT_14 => X"00E000009F013766FC5C8830EF7F814EDD135AB1E020FF3FF040400096F6FFFE",
INIT_15 => X"FF469300CE69307FC0FB5FF8E0F5903FDE50400075D9FFFE7FFF184FEEFFFFFD",
INIT_16 => X"A116833FC1CCF81FD158C008502CFFFE3FFF989FFC7A3FFFF8E00000B7CF8003",
INIT_17 => X"D0D8C070F7F3FFFE7FFF0BDFFC3DDFFEF8C00000DFFFF813FDA54BE0871D5293",
INIT_18 => X"7F3EFCDFFF4C87FFAC000000AFC0E081FFC5C1F0054206EAAD14255F01DFF89F",
INIT_19 => X"A60000009F658091FB0E662302EEA6EA3C9E03380344618FB0ECE0F057FFFFFE",
INIT_1A => X"FBCF3F3703FD6F35C7C0C8C88420709F4824C0F0A7FFFFFE7F42722FF8300BFF",
INIT_1B => X"234C8910201A619F795840703FFFFFFE7F25F723F1F005FDCB8000005F7A1F18",
INIT_1C => X"B9E900E03FFF39FE7FE6FFC3F1F01EFDF8C0C0001F1891CBF4E7F9EF0138DE8F",
INIT_1D => X"7FF8749CF1FC70C1F96000009E1D5E23FEB7FCC1828BFF4753C1BD662482589F",
INIT_1E => X"FD0000029E8DE6BC7A87FF54C610CF44C47EC8C1FFEB14BFD9EC00847FFE7FFE",
INIT_1F => X"9477FE3EA4A8D5FDF01DD02FDBF6353E52DC00857FF8F8FE7FFCEE9188FFBCBF",
INIT_20 => X"101E0A5D69E9C17DBD56010AFFF8F8FE7FFF1FA8883F1AF0FE700000BF0E2CB8",
INIT_21 => X"FB86F3E2FFF5FCFE7FFFBF8E7E1E194FFEF00008978782E6E2B17F31BE8ED7CB",
INIT_22 => X"7FFFC400AECE1E991F3000003BDEA835DE833FBBFF03F4FF70EE3595090F317A",
INIT_23 => X"046F8000B3D8DF68C5154FCF9C0F2792B0710CA99F2AFB756EF23FF3FFCD69FE",
INIT_24 => X"1710D7F05E167787E12FD6C871ACA2EB3C35A7E1FF1F39FE7FFFD8461BECFFE5",
INIT_25 => X"11A7A5058C6018E6F62EB895FF032FFE7FFFED83E3E880FD9F4FE0C091F24FF6",
INIT_26 => X"BB5A2765FCBC05FE7FFFF67EEBC810FB2431FFE0D3F9BFF3678082FF161C388F",
INIT_27 => X"7FFFFEBFEC3287E541F63FF0D8FB87C26D024A7E03FF301F75EEDEA356D134D2",
INIT_28 => X"014B67CCDDF119DD00C0000F5ECC340F43FBF01C04E8582872752C07F114E0BE",
INIT_29 => X"01F00C83ABC06357BC7BDD75232FE256D36AEB67E3359AFE7FFFFEBFED867086",
INIT_2A => X"40311C60CD569350A01719B38FCF199E7FFFFFFFFF01C38C5FC483CCDBA0225C",
INIT_2B => X"55889D198C7F876E7F7FFFFFF894A3E87FDB78FCEA4E639400101575D663E1BE",
INIT_2C => X"7F19FBFFDE1D93935F187E20E3B598B34450C666D2FE0E7EAA25D5A21E109755",
INIT_2D => X"FF38470200FAA3F3C404FD79FCCE04FF48ABAE01E7BE0736F6F0E08032CF36EA",
INIT_2E => X"EE38EBC2AEFB81FC19D04FA2A53AEFB0BCD410B434850F067FF67DFFEFFBC825",
INIT_2F => X"04A99C96BDD0AFBE752168BC76044FF87FE61A5FFFFFA9F67FFDEF0F872D2B78",
INIT_30 => X"9E20E79DE2410FDC66FC3509BFFCAC68FFFF8F08C0DE0B96BFCEEC615A4687FC",
INIT_31 => X"0E3FA7E4AFC01475FFFFF598A5FEAC7E1FD50141E19257FC5C5319A5620D6FFE",
INIT_32 => X"FFFFFC91AC7EB5318D4591A77FC9B7FC789B05A38C1E6FE445EEE64D47A39FF6",
INIT_33 => X"EB42443B7EAAA7FDBA7EB66EE90E8FCF77B3A6CFD2E73FC607FFEE031F38AB3F",
INIT_34 => X"278FD0CC553F8FC875F652CB8BC17F0010EFE40E09778FFFFFF9FD69DD7FE6C4",
INIT_35 => X"EA5B982323C87EF23B5BFA29F95FFFFFFFF9FCBC4FC1E7FB204D47BE7F6FA3FD",
INIT_36 => X"7BD3FDB72343FFDFFFFFFEFEE5B9FBD75C4847113F1B49FB8BE00C19CABE4FD7",
INIT_37 => X"FFFFFF7EFCA5FC59984C81459FC559ED3DE4140BC7FECFEDA6DB28E33DC2FC8E",
INIT_38 => X"D80061C2A3F45B1F0E60510BA53E0FEA41C8A7708D58F97659B7FE9F086BFE1F",
INIT_39 => X"42C00967AEFF0FE5500F9F703F9DFBB870A7FF8780783FF7FFFFFFB3C1F3F97F",
INIT_3A => X"FE0A9DA24E80FA406731FFD818324EB7FFFF3FEB4967F0B7ED10E0062DF98007",
INIT_3B => X"7E693FF64F01AC0F7FFCFFC3AE15FCAFF75FE803F4F7A7777B2C71D7B37D1FF1",
INIT_3C => X"FFFDFFF3B58DFF47FC8F38001E77A2DCD7D41D6F8237BFF343147E2645CDF820",
INIT_3D => X"FB79D80016227ABD327F269FDB08BFF0022F914E8539F7B81767CFF64200FAD5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"6DBF599FF38EBFF291CE529E0553E8380D9B57F9E37A07293FFC7FFA795C7EDB",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"6ED635BEA7F796F87F7E43FC78A58798EFFF1FFBBEAD7FE5FE07D8036F2113FA"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7FF981DEBFCB77E755FF9FF366DC3F79FE525803AB0FCAF5E921163FD349BFF2",
INIT_01 => X"1D7FCFF800590FE7FFF8D805E331CCEA4A22C87FEA3CFFF22E8D227E6E37667C",
INIT_02 => X"FF67D076DBB1CE148B1DD3FFE6747FF2D896CDFD6EAF604C7FFECDE7BFFDC8F8",
INIT_03 => X"0802A7FFE7F97FFAC29453FA9D5F330A7FFFD4FFEFFFF4FFCA1FC3F90D7B17CE",
INIT_04 => X"BB41C7F099DF0F087FFFFFFFDF5F963FEE27F8FCAF7A3BE1FFB8503C487E7F14",
INIT_05 => X"7FE7BFFFC75149807107FCFF7642C4FAFF9E9018FE85F1EC0582A7FFCC7A7FFA",
INIT_06 => X"8623FFFFA575A57A7FCC409A260C0CC80803AFFF8D76FFFE39AA0FF632BF1334",
INIT_07 => X"7FD0F07524EAF8180AFEAFFF3C30FFFE60AA9FFC1D7F83287EEBC6FFE3BD97FF",
INIT_08 => X"368EB7FDC258FFEE43439FE91C7C47F67C1CDA9FEA7F1E867394BFFFD236107F",
INIT_09 => X"67AD7FEE1EF9DFB44876F82AACBF291B5BC60FBFEBA561BD3FE5F5EC2D33F018",
INIT_0A => X"6604E01182FF8FFF3483A5CFF50F0BDD7FE4BFF8251CE418BD0EA7F62BC9FFE5",
INIT_0B => X"B180EE17FA43D2F07FE42720FC4E57982C00AFCA3A81FFE047327FE939F9CCE8",
INIT_0C => X"7FF8E51A3FFEA59B2E80CFDE86E3FFE0BDCFFFCFADF4AC3E38000107BFFEEFFF",
INIT_0D => X"5A005FAE27F3FFE0BD0EFFE5ADF760C0480001F01D88F3FFF463044BFED7C92C",
INIT_0E => X"5305FFD22BF3A12C400FFC78DECAA3FFFF778A93FFACFBEBBFFDFAEF3703D1B0",
INIT_0F => X"700007F80FFEEFFFFF5A78E5FFD6FFF94FFFF55DC16D0D30ADC19F38B067FFD1",
INIT_10 => X"FF8D3C4B7FF5F95777EFF79BDBDE856049018C4C5D673FAD327FFF39CFFA74D6",
INIT_11 => X"3807E9A627F93261638280D55E0FBFA53E0BFF4FFFEF4286626F800007809FFF",
INIT_12 => X"A7FCE4CF9E5FFFB14F8BFF45DFEB0F2E7FFFFFC004833FFFFFD87FAE8FF9C7EE",
INIT_13 => X"01E1FF6D3FEC0D4E7EFFFF0000FCFFFFFFFC187C5FFC023397DBE90271E84BE2",
INIT_14 => X"5EFF9300047E6BFFFFFEC0E83BFE208CAB1412D54F10F462B7F9FFF0549FFFB8",
INIT_15 => X"FFFC8441F27FB7DBB722676930639AB25E279E0F603FFF18510DFEB99FD54D9E",
INIT_16 => X"3F0DCFEA1B072E24A807BC2117BFFF583ADDFE981F937A7E63FF8100007973FF",
INIT_17 => X"183739FE567FFCB485BFFCF15F9787FC61FF8383E07B67FFFFFFE18876DFD6AF",
INIT_18 => X"B3BFFCD05FB6F3F823FFFF81F01DCBFFFFFFF9AF9DAFF42C2DE1C76804002214",
INIT_19 => X"100CFFC1600382BFFFFFFE661F39FC2DB54BF0084357C599587971FEFA7FFD74",
INIT_1A => X"FFFFFF9A726B7E3746679F89F3BAE56F20E985FE54FFFA6B2A3FFD1E5F6297FA",
INIT_1B => X"D4260094FA3B31BA60FE63FEE1FFF2D151DFF0FE3F078FF4501E7FC008C1FAFF",
INIT_1C => X"C0FBF3FEBFFFF6C3E7CFF2EBFF6F5FFE54E7FFE01FF8CB97FFFFFFC15BB35EBA",
INIT_1D => X"B7DFF36DFF023F8C210707C17FFE6DD03FFFFE3F202B0CEA4DBCE073280961A2",
INIT_1E => X"14BF1783F00F42019FFFFFFFAD200AFC0CE0FB751309CD058FF4DFFE6BFFF6AD",
INIT_1F => X"6FFFFFFFC60D55FA9B18F881BEA2DD05FEE2DFFFD7FFF2205FFFF7F53F15FF1E",
INIT_20 => X"165BFFC9BF16DDE7FFD27FFCA7FFF333AFFFE2E3FF07FE30746FE71E800F7F33",
INIT_21 => X"E70CDFFC17FFF99F6FFFE1B8FF97FCD0310F573C3F8875FFF43F3FFFFBA54674",
INIT_22 => X"CFFFCF8CFF2FFB204402EE61FF8A8A80CEA3FE9FF9D2184C9CBFFFF0E20ACCE5",
INIT_23 => X"24001E61DFB7EC5CAB4F0FD7FC4E975001AFF8A8157B804BEC6C5EFD2FFFF882",
INIT_24 => X"07DAEFA7FF95B1AEED6FFBF2F06F219BE8CE3EFDAFFFF9FF1FFFD18FFCF7FA8C",
INIT_25 => X"E637FC5BB16EE1FBA8F93FFAAFFFFBFE7FFF938AF1EFF36C31C21E788E60D718",
INIT_26 => X"CC19B7F4CFFFF9F87FFF1E60CC9FD044700ADF3ECEE064907F01A4ABFFED8959",
INIT_27 => X"FFFE05BB26BF3F9270032B1E3810002A3F0F9D9C3FF12F77811AFF2F3989E1BC",
INIT_28 => X"7F81C9C713070A778007ED83C7FF20CA3E88FFEFE5F923A839D9C7EEDFFFF9C1",
INIT_29 => X"C00F09C7BBFFEEBCD4C1CFFFE3F5A3ACC3BBFF1DCFFFF807FFFE97DD51BF1C5E",
INIT_2A => X"259001FF8DE1A34A3FE7FFA3AFFFF81FFFFD08112DBFAABE7FF819C74CD7626C",
INIT_2B => X"0F38FE5B2FFFF0FFFFF0941E21BA22FE003C19CF7C9887FEC00819F241FFF263",
INIT_2C => X"FFF341C29EB82FFE7FCFFF8F1F492E7480023C3D68FFFB3802BF7EFC0CFE21A2",
INIT_2D => X"78E7FE0F0EC71FBF001BEC06153FFEE33D1646FC6FD020B705BCFEAF27FFE0FF",
INIT_2E => X"FEBFF820B68EFFA73FFE5A7AFE137D5690B2FDCF6FFFE3FFFFE59AAE61FFDFFE",
INIT_2F => X"A09921FBFC4F287D18C279356FFFC7FFFFCEC9AE70E7FFFE7838003F67D9A47D",
INIT_30 => X"9F335A07EFFFC7FFFFCBE9DA0E0FFFFE703C003E634ACD7EFFE2CE0478A83FD5",
INIT_31 => X"FFCBE9E73F9FFF823F3FFE7E02E6BF0AC7F12C3FFD3F1FED290B9AA8FCDA6F40",
INIT_32 => X"03FF7FFF8301050C9BD2D65FFFCF1FE183D8044E71F0BF3AB6F7FAFEEFFFC7FF",
INIT_33 => X"D926D62903B57FFE86B5A617F16D7F394FDFA042EFFFFFFFFF80BBFFFFFFF9C0",
INIT_34 => X"0D29C0A89F4DFF99AC2FEFE29FFE3FFFFF8CF3FFC3FFE632783E1E07C7367FE0",
INIT_35 => X"5DB3FF5D5FFDBFFFFE9F27FFC1FFC9DA3F1C1EF17F2AFBE2FE124E0F07E2BFFF",
INIT_36 => X"FCFC87FFE1FE346A11D81E700F36CAF27E1D5F800FFBFFFFFAA532213417FBDF",
INIT_37 => X"4A480F80007A7707801D618003606FFFF90A225D89227A2B857E0D64DFFDBFFF",
INIT_38 => X"195F2611700073C7FE02FE6C1E40FBBA4FAEE4255FF9BFFFF8A73FFFFFFCD336",
INIT_39 => X"0FEEFE203F789A420808510DBFF77FFFE1367FFFFFF1B05625C80000720DF83C",
INIT_3A => X"87164E8DBFE2FFFFD000FFFFFFC77F2606D800FF931BF9C26E190847F0002780",
INIT_3B => X"59FFFFFFFFCEE38E773301FF93233F90E263DADBCEF1CE000FE7FE00FF18BA71",
INIT_3C => X"006300FF133F0097F9A503E7FFFA340C77D5FC011FB724909DF8280DBF91FFFF",
INIT_3D => X"FE3322B00DF50C7277D0FC0F3FAF74CF6B94932FFF37FFFED17FFFFFFF9089FE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"4FEDF07FFFB7033F07A217C87E8FFFF388FFFFFFFF2337FE03C7001C5CA7FF9F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"379FAFC87CBFFFCDE9FFFFFFFF20EFFE7E070000FDA7FFFFFF8D870FCA4F2B72"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B9FFFFFFFE3B9FFE60020000B6BFFFFFFFF1297902D0800107E1E07C3F87D86F",
INIT_01 => X"4000000117BFFFFFFFFE3A000E3F0000BDD1807D30779BE67B7E5E4FBCD3FFAD",
INIT_02 => X"FFFFFFFFF1F85506E2B0003D308F85F6FB100406BF0FFE7791FFFFFF80067FFE",
INIT_03 => X"7F88003F70FDF11A7A0164ECFFA7FD66A7FFFFFF0001FFFE0000010F077FFFFF",
INIT_04 => X"FD6635F0748FF27B9FFFFFFC007FFFFC400000FEE3FFFFFFFFFFFFFFFC38A306",
INIT_05 => X"7FFFFFC003FFFE787F0600F9F39FFFFFFFFFFFFFFFFFE167F81C001E521C7BDD",
INIT_06 => X"7FFF07E1E31FFFFFFFFFFFFFFFFFFD82703F001EB27E9F77F9A503F73C7FE6EB",
INIT_07 => X"803FFFFFFFFFFDA1F01F000F20CCFF22BCA4E7F322FF0FEAFFFFFF807FFFFC32",
INIT_08 => X"3C078007C099BE5DF8AA05DDBA7F20C9FFFFFF1EFFFFFC3878FF0700381FFFFF",
INIT_09 => X"74BA4B9DDEF49457FFFFFC3EFFFFFC34201F0E81FB1FFFFFE01F01807FFFFC57",
INIT_0A => X"FFFFF006FFFF03C6601F7D78A79FFFFEFA10F00F0FFFFF8D1C078300C0F4D898",
INIT_0B => X"001E3A3668B3FFFE0A78E03F0C00FFE9EE0787F840D7EE19FD7AC39DB4484D6F",
INIT_0C => X"0CD698026338FFE0641FFECE01E6761F7811FC037E11AB7FFFFFC01DFFFF4108",
INIT_0D => X"CBFFFE0781F1B482B082F10B5FFAA9FFFFFFC0FFFFFC3312700F079D111FB0D0",
INIT_0E => X"AA85F53A5B96B7FFFFFFFFFFFFFB3CE2380310D4BDFE20E9017E5FFF19993FF1",
INIT_0F => X"FFEFFFFFFFF9F84C300067BF7CCF67F4003B83009C8D6FC1F5FFBF0783C561F0",
INIT_10 => X"70302FFEBFC3DF08700427FF76F89081E99FFFFE03A261F0F9DC17CDC57A67FF",
INIT_11 => X"000F01CC0C1F980FEFFFFFF00736833DFDFE57B275D88FFFFCCBFFFFFFF80178",
INIT_12 => X"EC7FFFE00724D7F841FAE092838FFFF8B8F3FFFFFFF301D0607F7F7DAD410570",
INIT_13 => X"8198E03058A1FFE238FFFFFFFF013F5E41F17DD66280040003FF1D6E180031FF",
INIT_14 => X"1BEFFFFFFE00E23C79C4FC0798389F007FFFAD1E783E0FFFDC3FFF8207346B2C",
INIT_15 => X"7F07ED37E27C1F00FFEADE011FFFFFFFEE7FFF0F0FBF6BF9E198672E7647FF81",
INIT_16 => X"0CFCFC01FFFFFFFFF8B6FF390FA9FBEFDF819B1CD93FFDBFFFFFFFFFF8795C42",
INIT_17 => X"381EFF368F674212AFA3D60B263FFB7FFF9FFFFFF80DAEC638AFE1E9FC7DFFF0",
INIT_18 => X"1F66A812B1F3CEFFFFDFFFFFF8E97C32177F0F0F007CF8083AAF03FFFFFFFC07",
INIT_19 => X"FD3FFFFFF35423887FFF58E000001FF9253FFFFFFFFFC307F816FF169EE6845B",
INIT_1A => X"7FC79BE7800061C69FFFFFFFFFFF3A058C00FF18FB499B695DF4024BDFFCF5FF",
INIT_1B => X"FFFFFFFF8FFF367745C07F8FF9974AA3D9D4E6913FDDE3FFF9FFFFFFF5622BCA",
INIT_1C => X"BD6177C7F3319C631174E1D5FFEDE4DFEFFFFFFFE94BB8107FEF7BC98000A3DF",
INIT_1D => X"1036C5A7FFF46C5D83FFFFFFA50B5C067FFF30118200A07FFFFFFFFF9FF1693C",
INIT_1E => X"0FFFFFF85C86F8267FF4F0E1800019FFFFFFFFFFF8E2167FFC60FFE3FEEC6B7E",
INIT_1F => X"7FE48FCE87FFDBFFFFFFF8D11C9DDB9BFE616BE0FFD9C066982C1E9FFFFAF9D6",
INIT_20 => X"FFFFF4384E02EEB3FDA380C04338FEE1570EB8FFFFFA24BDCFFFFE15BF05E492",
INIT_21 => X"F201C0803100C5A6435AEDFFFFFF0E1D0FFFC36C2615C5A07FEBFFD912F4F1FF",
INIT_22 => X"C61363FFF3001E5AFFCD3BE0A21F7D787FB760314D8FFFFFFFFFE99DAC0CEECF",
INIT_23 => X"FF2332042CE33DF07F870030125FFFFFFFFFD3F340F3393FEA75B9FF49196B36",
INIT_24 => X"7E070030F3FBFFFFFFFF80FBFCF3F63FD3C678FFC83911963C2227FED4438CFF",
INIT_25 => X"FFFFEB1473CC387FB98F701FD2B6DF943C5ECBFACFD5AFFFFED3E075EE7FEEEE",
INIT_26 => X"A3BC2FC604563FB3B89A8FF00FF7E2FFE0A879B5219C0FD8711500307FEFFFFF",
INIT_27 => X"FB040FF2267FE8FEFCD7353380310F96605A00333FFF57D7E7FFE1EF8F5CC2FF",
INIT_28 => X"7E6F0B0FE780CB26652B0707BFE948A7FFFF9C170698BFF1B8FFD53031707F42",
INIT_29 => X"6AF43F5FFFF170E3FEFFB76FF3E67FE991F75791C0E87EE39B067FD202FFFEF1",
INIT_2A => X"FFBE666F1E0AFFD74FCCCDB19A10FC43B9937F7623FFFF849680AA3FFFFECF4E",
INIT_2B => X"DF2FD87045A4FC2F19C5FFFDFBFFFF197800CC7FFFFF4E9E18E9F16FFFC1727D",
INIT_2C => X"B8E2D8D2C7FFC0C8B01050FFFFFF613C6FF4BBDBFE6F7889417587CDFB93FFA7",
INIT_2D => X"27F9C7FFFFFF3B780FDCBDE7F6630C185C8C27D24DC7FFB31EA1DB045982B2C1",
INIT_2E => X"525B1B32771C9C17E2307FC0AACFFE5C3F5399FE33F5C390E359C9BFFFFC3C27",
INIT_2F => X"198041D0994FF325FDB39BFEABE40E78CC200BB7FFF18331360FC7FFFFFF9CFA",
INIT_30 => X"7AA187F92A39BC9E181893FFFFE2FB0153041FFFFFFFC1F405981EF3B9189C78",
INIT_31 => X"738CBBFFFF999BC763265FFFFFFFE3F441D82EE4D7FF1AF0E6C03E3CAD3FED46",
INIT_32 => X"A7B3BFFFFF1FF7F44AFD1BC4D9C0354BC8E1B1946BFFE54A724A2F669EE09C4E",
INIT_33 => X"67FE83B1F0C0DA471C06258555FFD91764E8C26F171303CCE3CD1FFFFF472F4F",
INIT_34 => X"3398BFC7CFFFF17BA3EEF265A433FA1210E5B007F97076C5C9CCFFFFFF00FFE4",
INIT_35 => X"B39EDE60B2E555660025AFC01D271C1385987FFFFCFCFFEC67FFE64720E6B39E",
INIT_36 => X"0071C864C1753C573A880FFFFDC71FE81FFFFC2E2047307001F0FFF9CFFF9637",
INIT_37 => X"DF4E4FFFF900E0CA1F2BFECE30CBFAE00388FFFAE7FE836FF47EA860F33A8CCC",
INIT_38 => X"6E4FACCC3310E8E0FC47FFF807F9721FFBBE0FC649038DD800F10BDF448D80C8",
INIT_39 => X"804FFFFFE7F505DFFC7DEB06D5D7839800F4CE08B8A03FC7DF8257FFF33F1E16",
INIT_3A => X"FFFCF5C79AB66F98007DD5A8D6F27FB22FC57FFFF33F03E65FB4D6987F3FE9E1",
INIT_3B => X"007D6D8F8328FFA8D9C9EFFFFB3FFE0E1F7DD5B0FE67C7EF239FFFFFFFF60ABF",
INIT_3C => X"3D14CFF7C11FC1D807B03620F8DFBFFE953FFFFFFFEFB4FFFFF0C047B52C2F8C",
INIT_3D => X"1DE3BCC7035F9CF8FE7FFFFFFFD661FFFFE71DA654117E8E06616FFFD7FCFF8C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"BFFFFFFFFF7E8DFFFFFA366CDA8F7AEE3F0327FFCBFDFFE7FF13FFE729BFDED0",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFD5EEEDF7D6DFE61FC3B9FFEFDBBFF17F00F7AF299E5B145CD7F98F82BF5FE7"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"1B7B7C7FE7E67F8807CCE0B0119C768C102FF382361EBF0CFFFFFFFFFEBE23FF",
INIT_01 => X"07FED3E8131C6AF277D9C3807218F837FFFFFFFF7E72FFFFFFCD5E23B45AA3E4",
INIT_02 => X"72F9C3013293F02BBFFFFFFFFDA767FFFFE357A3CC5C337A33BAB81FBFFE7D50",
INIT_03 => X"FFFFFFFFE3CDDFFFE7ADB742D3C06165103AB6E0E4FF360003FAD8A3361CCC70",
INIT_04 => X"E7F767078FB631CD95BBDF7C2C7C1580010C034F3819E1D8758DE3FD5EF0F315",
INIT_05 => X"8B3FECE4F87EEE3C000FA49CC3F3E6E4656BC0FB9E8BCC73FFFC7FFFEDFD5FFF",
INIT_06 => X"401990E1BF60EFB462A7E006FEE223FFFFFC3FFFDBC21FFFE7E5EFCC28990C89",
INIT_07 => X"635CC009820C77FFFFF9BFFF97CB7FEFFF9B7F03192E028F84BF81E59CFEC1F4",
INIT_08 => X"FFFB3FFFD75EFFFFFF79EFDA1CFA7E57220D3D1D0306EB58871BBE399B81044E",
INIT_09 => X"FE368FF291787631A11BDB310FC34BFECE25FE3CF3CF1F707CE40094267D3FFF",
INIT_0A => X"01245F8607C77FFF373F74FCF418C30870346FBAF6CA7FFFF9D17FFEB5F9FFFF",
INIT_0B => X"C73F78FCF7079FFE7F87FE7F6FEEFFFFF34BFFFFC321FFFFFEC59F56A17C13F7",
INIT_0C => X"7FE3E2437ADE7FFFFA07FFFC8043FFFFFE143FE593FA7C711376A3F0000DEBFC",
INIT_0D => X"ACC0FFF00007FFFFF98B7FDE9E5944FE324133C0031BE5FFD7AB75F879FF1FFC",
INIT_0E => X"F1C1FFA46CD051FAF068EBC38037F7FFFFB428FC7FFF3FC27F60A541B835FFFF",
INIT_0F => X"50199086FC2FB4FF8E6F46F8DFFFFC8C7FC05FCB63E3FFFFEA8DFFF161D7FFFF",
INIT_10 => X"BC70A9709FFFF8047F7B79F870FBFFFF5387FFFF23FFFFFFF200FFB8D24D15F4",
INIT_11 => X"719D7E7C7F87FFFDA10BFFDEE47FFFFFF2D2FFE13C5A8FF1DB003783FBDE2CFF",
INIT_12 => X"86AFF3D9C7FFFFFFF872FFA2563247F698E36DE81CFD7DFDFC4D3330FE9FFECC",
INIT_13 => X"F9CDFE69EA4347F411B7F7FF06BEF2F14EB1CB20FC057F007699FEFFFFD183F8",
INIT_14 => X"F35FFD7F031E991F9CAE306038C077F07B9BF0FFFFC605FC7E47FF2381FFFFFF",
INIT_15 => X"FE90FFFE1E04E7CC7B0F963FFF970B83F8EFAE6707FFFFFFFA107E30225687F9",
INIT_16 => X"7DEFDABFFE6282E7F87F3CE605FFFFFFFB837EB43381EBFAF0D7FC7F206FA448",
INIT_17 => X"FBBF2786AFFFFFFFFACBFC7426A99BFCF123FEBF80B7AC80ED9B1E3F0E1FCDF0",
INIT_18 => X"F9EBFEC8E5D2EBFD7105FABC8107F01043A5DB3CCC1F0DFC7F1FF2FFFCCDCFEC",
INIT_19 => X"344BFA2EE381FD7341AA329B661EC0007FFFFFFFFDCDFFC46F7FBC0097FFFF7F",
INIT_1A => X"1277C2581BE647527FFC7FFFF837FF0E5FFE60018DFFDB7FFFFBFB44DB6FCFFF",
INIT_1B => X"3FF8FFFFFC0D071F1FFB8FC27FFFCEFFF4E3F70DE6144AFED038FFC7E7CBFFFF",
INIT_1C => X"5FFA87EE7FFFE4FFFBBFFEE65DF29DFF7209FEA30470FFFFDBF02994E81D07E0",
INIT_1D => X"F13FF972601F1BFFEF99FEE002EA6F8FEE407A649E71FF8E7FFFFFFFF8DB6F0E",
INIT_1E => X"2F90FEB00FD0AFDFFC1E0F8107C69FCE7FFFFFFFFE7D3980DFE5071E7FF9D0FF",
INIT_1F => X"FE3F008F44725FCC7FFFFFFFFFFE0B85BFF10F03FFF62BFFE17FF9E8095F33FF",
INIT_20 => X"7FFFFFFFFF24D31CFFB9040BFFEDDFFFEC7FF9BECA60B2FF4D92FCA30FC49FFF",
INIT_21 => X"FF9B0051FFE8B3FFCE7FFC750F8BA1FF0805FCF903F7C7FFFE3D004DE08B67E6",
INIT_22 => X"F53FF093B9CFC7FFDE117AF9E2F3CBFFF660F37CCA6416667F7FFFFCBF41C3E4",
INIT_23 => X"E20786BF05B983FFEFC0F37FFD0896167F9FFFFBBE3FE7E7FCC6003FFFD1E5FF",
INIT_24 => X"FA001B9FFFC7DA967FDFFFF907FF5475FD3C00C7FFC1C7FF993FF7B87B3381FF",
INIT_25 => X"7FFFFFFF779ECBA5B8FDC01FFFC7CBFFAAFFDDC559EFE1FFF70C883E823FC77F",
INIT_26 => X"F9886A2FFF8FE3FF42FFDDDFA8FFC5FFF7068E6F83FEF35BFBFD1069FFFFE534",
INIT_27 => X"857FD0BC851FE2FFFF62B037C6DB7B4BFDFE065EFFFFF4EC7FFFFFFECF53DDFD",
INIT_28 => X"FB632EB3E155FA2FFF368BB4BFFFFB327FFFFFFEFF01AFFBC580069FFF18D7FF",
INIT_29 => X"FFD76F33FFFFFC867FFFCCBFA745FBCFA1B9C6BFFFF057FFADFF2E34BB0F82FF",
INIT_2A => X"7FFFE7BF880A7C6704BDB3CFFFB0D7FF63FF18F19817907FFE85E603B13DBD3B",
INIT_2B => X"C28909CFFE7BAFFEEBFDABD29803F1BFFF5334E3C8219D31FFFFF607FFFFFF3E",
INIT_2C => X"A7FCD8D3086BF09FFFD11723FC118F8FFFFFF246BFFFFFFE7FFFE6FF5547BB1E",
INIT_2D => X"BF0143DFFDFBA6FD7FFFE7ECFFFFFFFE7FFFF3FC1358FCF67EC711BFFFBF4FFE",
INIT_2E => X"FFFFB6F83FFFFFFE7FFFFFFCF1F47DC73778117FFCFF5FFDA7F5432B0B49B8BF",
INIT_2F => X"7FFF7FFFFFFA754BED87D7FFFFFF3FF477EAA918F4BD3F7FBE705E03FE371FA4",
INIT_30 => X"C201FBFFFFFAFFF9D7D793276C9F9E7FFF68FA03FF817FB5FFFF886A3FFFFFFE",
INIT_31 => X"DE1FB45A1FDFBE417E481003FFA57FCA7FFFD4A45FFFFFFE7FFFFFFFFEDFE597",
INIT_32 => X"CE8C5429FF801FF3DFFFE862CFFFFFFE7FFFFFFFFEEFD6E8F9F0AFFFE3FB7FFD",
INIT_33 => X"BBFFFBC100FFFFFE7FFFFFFFFF73BDF74EE09FFFA7FCFFFB563FCC224F97BE8C",
INIT_34 => X"7FFFFFFFFFBB03F99A81F7FF5FFDFFF1E4BFAF22638AFA7793FE5D1FFFFD8FFD",
INIT_35 => X"7B9CDFFF1BFFFFF3067DCDE2600E3849F25CFCB3FFC73FF903FFFE512C7FFFFE",
INIT_36 => X"617A03466D14C845FD4C7DC7FF0B47FE23FFFF95FB1FFFFE7FFFFFFF3FE04FFE",
INIT_37 => X"B94C752BFF8A93FF83FFFFC55B67FF7E7FFFFFFF3FE3BFFC7A72BFFCBFF0FFE3",
INIT_38 => X"93E0FFE10358FF0E7FFFFFFFFFEE3FFC59C21EDA3FC9FFEE5FFC87EEAC1C40D5",
INIT_39 => X"7FFFFFFFFEDE7FFF98367E953BDA7FD09FF889FCC51800EBFC8C8133FF7861FF",
INIT_3A => X"10197F6E9F83FFAC8FF897F8A03823C13EA5CA9DFF3D10FFC3CC7FFC5C4B8612",
INIT_3B => X"DFF8D5F25678E3817EFFE1C2FFFED27FFB8FBFFFE7900CA07FFFFFFFFF8BFFFF",
INIT_3C => X"FF8FE08CFFFF55BFF338DFFFF9410E227FFFFFFFFF35FFFE64FCFF250705FFE4",
INIT_3D => X"FC971FFFFE63652A7FFFFFFFFEE7FFFFEDDDFE354003FFC47FFAD9FB0FF9C38F",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFBC3FFFFCB09FFFAE005FFA2F7F0FDFB6FF4E78E3F89E0F6D7FF953F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"9228FFEEF80BFF31FFE857C37BF6FF8E7FD8CF7243FFF15FF917DFFFFF6C5FCC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FEAA56FFFFFFFFFFFFFFE5243C000C003FFFFFFFFFFFFFFFFE55407FFFFFFFFF",
INIT_01 => X"FFFFFC4304FFE36D6C25556A54156A543FFFFF1A5BFF2942282FFFFFFD3EC6FF",
INIT_02 => X"3FFFFFFFFFFFBFFFF95501BFFFFFFFFF9003FA4EFFFFF755FFC000BBFFFFF9BF",
INIT_03 => X"4FFFFFD8AAC0C650D43FFFFFFF9301BFFA56ABFFFFFFFFFFFFFFFA4E01A50C30",
INIT_04 => X"A500A95EFFFFDE553FF0018BFFFF99EBFFFFF64F1EFE9834EAF9555554056A54",
INIT_05 => X"FE95ABFFFFFFFFFFFFFFFFE495AF91303FFFFFFFFFFEAAAAA95516FFFFFFFFFF",
INIT_06 => X"FFFFE80F23FFE6FF75B95555540555505FFFFFFC7AC0F690B2EFFFFFFFF9557F",
INIT_07 => X"3FFFFFFFFFFA55AAA9501BFFFFFFFFFEAA40FA9EFFFFC55003FF16C7FFFF4ACF",
INIT_08 => X"5FFFFFFFB2FFF194B99FFFFFFFFFFEBFFFAAAABFFFFFFFFFFFFFFFFA34066A4C",
INIT_09 => X"554FE962FFFE894150FF044CBFFFFAFFFFFF64FF1FFFFFBFDD69A95A54005540",
INIT_0A => X"FFEAAABFFEBFFFFFFFFFFFFE4DFF0A403FFFFFFFFFAA5556A5506FFFFEAFFFFD",
INIT_0B => X"FFFDD0FF6FFFF3BFF65AAA555400100F5FFFFFFFECFC0155AADFFFFFFFFFFFFF",
INIT_0C => X"3FFFFFFFFEAA555695006FFFFEAFFFFE554FEAB7FFFD3541A43FC9DF2FFE297F",
INIT_0D => X"4FFFFFFFF6FC50555ADFFFFFFFFFFFFFFFAAAABFFFBFFFFFFFFFFFFF934EB654",
INIT_0E => X"550FE72BFFF65501540FCFF46FFFD0FFFFF340F0FFFFF3BFFC46A9555000000F",
INIT_0F => X"FFFAAABFFFBFFFFFFFFFFFFFE427AC583FFFFFFFFEAAAAA55405BFFFFFBFFFFE",
INIT_10 => X"FF8900313FFFFFBFFD8555554000003F27FFFFFFFDBD55551B1BFFFFFFFFFABF",
INIT_11 => X"3FFFFFFFAAA5AAE94006AFFFFFFFFFFE553EA87FFF88000154030AFFFFF9FFFF",
INIT_12 => X"1EFFFFFFFF1C55155B5BFFFFFFFFE56FFFFEAABFFFFFFFFFFFFFFFFFFA49FFC4",
INIT_13 => X"903AB1BFF740000155000AFFFFF3ABFFFF6140017FFFFFBFFE2555550000003F",
INIT_14 => X"AFFF9ABFFFFFFFFFFFFFFFFFFE4F4FFC3FFFFFFFAA956AA50F16ABFFFFFFFFFF",
INIT_15 => X"FFA00306BFFFEABFFF8955540000103C59FFFFFFFFBF5405586BFFFFFFFFE56A",
INIT_16 => X"3FFFFFFEA9556AA43F056BFFFFFFFFFF903AC6AFFDFFF05555400FFFFFEACFFF",
INIT_17 => X"58FFFFFFFFC70405186BFFFFFFFFFAAAAFFF95AFFFFFFFFFFFFFFFFFFF80E4E8",
INIT_18 => X"903AC6BFED0FFC15554013FFFFDE2FFFFFB40007BFFFD6BFFFF2555400001430",
INIT_19 => X"AFFF506FFFFFFFFFFFFFFFFFFFA439EC3FFFFFFE55415550FC05ABFFFFFFFFFF",
INIT_1A => X"FF651047BFFFD1AFFFFB00154000140058BFFFFFFFEBC554076ABFFFFFFFFFFE",
INIT_1B => X"3FFFFFF940001543BC05AFFFFFFFFFFE8C3AF1BFECFFF015555057FFFFCBFFFF",
INIT_1C => X"2DFFFFFFFFF1F654C7156BFFFFFFFFFFAFFE901AFFFFFFFFFFFFFFFFFFF90E40",
INIT_1D => X"4FFFC6FFD83FF055550567FFFF9B7FFFFF654108FFFFE9AFFFFD400450015001",
INIT_1E => X"FFFF8306AFFFFFFFFFFFFFFFFFFA54E83FFFFFE900FC000FBC05AFFFFFFFFFFE",
INIT_1F => X"FDD5555EFFFF5A6FFFFE900550155515B2FFFFFFFFF7F2A40B1406FFFFFFFFFF",
INIT_20 => X"3FFFFFA503FC50FAB056BFFFFFFFFFFE7FFF1BFFD800C05555042BFFFF087FFF",
INIT_21 => X"86FFFFFFFFF97D955B13B2FFFFFFFFFFFFFE40056AFFFAFFFFFFFFFFFFFE990C",
INIT_22 => X"3FEF6FFFE800055555003FFFFDAABFFFF645157BFFFF3A6FFFFFD0055419695A",
INIT_23 => X"FFFA900055ABEAAFFFFFFFFFFFFFAA503FFFFA5403BC53AAB15ABFFFFFFFFFFA",
INIT_24 => X"ED05158FFFFFABAFFFFF2005656FAA5A81FFFFFFFFFECC945B0362FFFFFFFFFF",
INIT_25 => X"3FFFF9400FF003AAF16ABFFFFFFFFFE9FFAC6FFFFD10155954003FFFFB1FFFFF",
INIT_26 => X"01BFFFFFFFFE5C545B0F61FFFFFFFFFFFFEA95505556AAABFFFFFFFFFFFFFFA4",
INIT_27 => X"FEAC6FFFF155556A540327FFE1DFFFFFED0415AFFFFFABBFFFFFB55665753FEB",
INIT_28 => X"FFAAA554000556AAFFFFFFFFFFFFFFE83FFFF9000F003FAAC16AFFFFFFFFFFA5",
INIT_29 => X"741051FFFFFE6BFFFFFFDD15A986403C01BFFFFFFFFEB55516CE61BFFFFFFFFF",
INIT_2A => X"3FFFE90F3C103FEA015BFFFFFFFFFE94FEAD6FFFDD16AABE540FCEFFD8EFFFFD",
INIT_2B => X"0046FFFFFFFF9E5945BE62FFFFFFFFFFFA9AAA54000016AAFFFFFFFFFFFFFFFC",
INIT_2C => X"FAB1AFFF495BFF0E940FFAFFD830BFFB9005553FFFFE2B3FFFFFF7A9A9B6814C",
INIT_2D => X"FAAAAAA5300006AAAFFFFFFFFFFFFFFC3FFFE93F3C13FEABC05BFFFFFFFFFE50",
INIT_2E => X"9501553FFFFE283FFFFFFE4DA9A19540052BFFFFFFFFA71555BA62FFFFFFFFFF",
INIT_2F => X"3FFFE43FFC03FEAF006FFFFFFFFFFA43FAB16FFF4A9C004E940F3AFFD9446FFF",
INIT_30 => X"052BFFFFFFFFF882A56921FFFFFFFFFFFFFA556A5400C16AABFFFFFFFFFFFFFC",
INIT_31 => X"FE6C2FFE53B50003A43C1FFF9D1B06FDA40017BFFFFCEB3FFFFFFFD3FFED5404",
INIT_32 => X"FFF9555A9543C15AAABFFFFFFFFFFFFC3FFFA4FAF00FE9ACF1BFFFFFFFFFFA4F",
INIT_33 => X"900018BFFFFFEBFFFFFFFFE0F0FC54150642FFFFFFFFFDD1B95562BFFFFFFFFF",
INIT_34 => X"3FFF94FEF0FFA5ACC1BFFFFFFFFFFA4EFA6B1FF94F890FC3E43C67FF791BADF7",
INIT_35 => X"47DBFFFFFFFFFE74A90476FFFFFFFFFFFFF95015554E005AAABFFFFFFFFFFFFC",
INIT_36 => X"3AABC6A40FD9000538004BFE791A5D9D40F05B7FFFFAAAAFFFFFFFE404FC555B",
INIT_37 => X"FFFA5001550E0016AABFFFFFFFFFFFFC3FFF943FFFEA95BC06FFFFFFFFFFFA4F",
INIT_38 => X"0FFC56EFFFF5AA6FFFFFFFF954FC156F97EFFFFFFFFFFF886900B6FFFFFFFFFF",
INIT_39 => X"3FFE500FFEAAAABC16FFFFFFFFFFFA4F3F95ADA95328555A9D56DFFE795A6125",
INIT_3A => X"D5AFFFFFFFFFFFDDAD0062FFFFFFFFFFFFFE53FC15400055AABFFFFFFFFFFFFC",
INIT_3B => X"FF935DBEA4785A5A9EA2FFFE2656B1D53FFC5B2FFFFFAA1FFFFFFFF904FC5AAB",
INIT_3C => X"FFFE93FF155501556ABFFFFFFFFFFFFC3FFA503FAAAAAAFC5BFFFFFFFFFFF94F",
INIT_3D => X"3FFC1DBFFFD6AE0BFFFFFFE2B101AFABE06FFFFFFFFFFFE759401DFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FE903FAAAAABFF06FFFFFFFFFFFF94EBFE019FFF5B96AA50EBBFFFEE65AF625",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"F5BFFFFFFFFFFFF9514118BFFFFFFFFFFFFF93EB015515555AAFFFFFFFFFFFFC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram : RAMB16_S4_S4
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"8777777889ACFFFFFEFFEC8777877ADFFFFFFFFFFFFFFEB99ACDDDDEEEFFFEEF",
INIT_01 => X"ABCCCCAA99BEFFFFFFEDFFEDEEEFFFEDCCCBCCEFFFFFFFFFCA9999ABBCDEDBA9",
INIT_02 => X"4FFFEEDDDCCBBAAABAA99AAAABBBBBCDEFFFFFFFFFFFFFFFFFFFFFFFFFEDCCBA",
INIT_03 => X"FFFFFFFFEDCCBAAACCCCCCCCDDDDDDDDDDDEEEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_04 => X"FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFEDB989988999ACEFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"87667778999BEFEEEEFEDB77889769DEFFFFFFFFFFFFFFCA9ABDEDDEEFFFFFFF",
INIT_06 => X"ABCCDDCBBBCEFFFFFFEDFFEEEEEFFFEDCCDDDDEFFFFFFFFFDB9988ABCDEFDAA9",
INIT_07 => X"4FFEEEDDDCCBAAAABA9999AAABBBBCCDEFFFFFFFFFFFFFFFFFFFFFFFFFEDCCB9",
INIT_08 => X"FFFFFFFFFEDCBBAABCCCCCCCCCCCCDDDDDDDDEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_09 => X"EFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEDBA9998889ADFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"877767889A9ADECCCDEDB989999878CFFFFFFFFEFFFFFFEDCBCDDCDDDDEFFFFF",
INIT_0B => X"AACCDEEEDCDFEFFFFFFEEEEDDEEEFFEDDEDDDDEFFFFFFFFEDBA988ACCDFFDBA9",
INIT_0C => X"4EEEEEDDDCCCBAAA9A9999ABBBBBCDDEFFFFFFFFFFFFFFFFFFFFFFFFFEDDCBA9",
INIT_0D => X"FFFFFFFFFEDCCBBBBCCCCCCCCCCCCDDDDDDDEEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_0E => X"EFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDCBA999988ACEFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"87777899999ACCA89BDCA889AAA877BEFFFFFFFFFFFFFFFEEDDDDCCDCDEFFFFE",
INIT_10 => X"ABCDDEEEEDFFEFFFFFFEEEEEEEFFFFEDDEDDDDDDFFFFFFFEDBAA99ACDEFDBBBA",
INIT_11 => X"4EDEEEDDDCCCBBAA99999ABCCCCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCBBA9",
INIT_12 => X"FFFFFFFFFFEDCCBBBBBCCCCCCCCCCCCDDDDEEEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_13 => X"EEFFEEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCAA999989CEFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"877778ABAABDEC9679BB989ABAA977ADFFFFFFFFFFFFFFFFFFEEDCDDCDEFFFFE",
INIT_15 => X"ABCDEFFFEEFFEEFFFFFEEEEEEEFEFFEDDDDDDDDDEEEFFEEDCBAAAABDEFFECDDA",
INIT_16 => X"4EDDDDDDCCCCBBA99999ABCCCCCCDEEFFFFFFFFFFFFFFFFFFFFFFFFFFECCBBA9",
INIT_17 => X"FFFFFFFFFFEDDCCCBBBBBBBCBBCCCCCCDDEEEEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_18 => X"EEEFEEEFFFFFFFFFFFFFFFFFFFFFFFFFEEDBA999989BEFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"878779CDAACFFDA779CB989BBBAA979CEFFFFFFFFFFFFFFFFFFEEEEEDEFFFFFF",
INIT_1A => X"BCDDEFFFFFFFFEFFFFFEFFEEEFFFFFFEDDDEFEDDDDDDDDDCCAAAABCDFFFFFFFA",
INIT_1B => X"4DDDDDDDCCCBBBA98899ACDDCCCDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFECBBBBB",
INIT_1C => X"FFFFFFFFFFEDDCCCBBBBBBBBBBBCCCCCDDEEEFFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_1D => X"EEEFFEEEFFFFFFFFFFFFFFFFFFFFFFFFFEDCAA99889BEFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"88888BDECBDFECB99BCB99ACBBBBA77BEFFFFFFFFFFFFFFFFFFFEFFFEFFFFFFF",
INIT_1F => X"BCDEEFFFFFFFFFFFFFEEFFFFEEFFFFFFEEDFFFEEDCBBBBBBBAAAABCCDDEFFFEA",
INIT_20 => X"4DDDDDDDCCCBBA98889ABCDDCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFECBBBBB",
INIT_21 => X"FFFFFFFFFEEDDDDCBAABBBBBBBBCCCCCDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_22 => X"FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEDBBA9878BEFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"8888ADFFDCFFDCBAABB999BCBBBBA769EFFFFFFFFFFFFFFFFFFEEFFFEFFFFFFF",
INIT_24 => X"CDEFFFFFFFFFFFFFFFEEFFFFEEFFFFFFFEEFFFFEDCBAA99AA9ABBBAA9ACFFFC9",
INIT_25 => X"4DDDDDDDCCCBAA8789ABCDDCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDCBBBBB",
INIT_26 => X"FFFFFFFFFEEDDDDCBBAABBBBBBBCCCCCCDDEEEFFFFFFFFFFFFFFFFFFFFFFFFF4",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDCCA9778BDFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"889ACFFFCDFFDCBABBA889BBBBBBA769EFFFFFFFFFFFFFFFFFEEEFFFEFFFFFFF",
INIT_29 => X"DEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFDCBA9889AABCBB9879BFFFA8",
INIT_2A => X"4DDDDDDDCCBBA9889ABCDDDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFECBBBBC",
INIT_2B => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_2C => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_2D => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_2E => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_2F => X"4444444444444444444444444444444444444444444444444444444444444444",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(3) => BU2_doutb(0),
DIA(2) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(3) => BU2_doutb(0),
DIB(2) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED,
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED,
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"03038055BAEC73C2E0E8A20005BFFFFC0B011000C3C0199C0000000000000000",
INIT_02 => X"7190D0000D7FFFFE8301100083039FBC7FFFFFF3FFFFC80878FE4F20057A0000",
INIT_03 => X"E701300006067F3C7FFFFFF03FFFD0F941FF84AC1D3680000003E01182943903",
INIT_04 => X"7FFFFFE72FFFE0FF0700F87F53D3FC010007F0005D9A278C999420000D7FFFFF",
INIT_05 => X"9E0078F19FE273C0001FFC00298A64160C612000057FFFFFEB01B0000C0D803C",
INIT_06 => X"00FFF8C0298A62142E83E000017FFFFFFB01B0000C7C803C7FFFFFF30CFFCCE1",
INIT_07 => X"247803006A7C3FFFFB01F00008FE0E3C7FFFE00101FFFCC2FC000FEEFFD4B4C0",
INIT_08 => X"FF00E00008F38FBC7F7FE0008107FAC7783C0FEEF9EF3EC403FD00010F0A6154",
INIT_09 => X"7F3F8000318BFD4F3C7C81F0F1BBFFF603F8000E1F0E200B090018804A633FFF",
INIT_0A => X"0C3D80FFE9FDDFFE09F8001E1E6C4307F8001000C1C3BFFFFE00C00008807FFE",
INIT_0B => X"838000301D638653FE20F00060B23FFFFE0000001B27FFFE7FFFF810E989FE27",
INIT_0C => X"0D60F80060E17FFFFA0000001AAFFFFE7FFFF010F6C3FF520C3CC003E71E1FFF",
INIT_0D => X"F21000001A6FFFFE7FFBE387799FFF180400C0006BB79FFF000000C001040618",
INIT_0E => X"7FF8EFC7BE7FFFAC000040F0E2D63FFFC1200C80028480067B03FF0070A23EFF",
INIT_0F => X"000040F8DAEC5FFEBE301E00C3A390097687FF801937BDFFFE30000038FFFFFE",
INIT_10 => X"C5CCF300687C1E0D0E0E7E8083007CFFFE380020771FFFFE7FFC6FE7DFFFFFCC",
INIT_11 => X"1E0C06C086877AFFF2384070F32FFFFE7FFC47FFE3FFFFF80038C078F8E2200F",
INIT_12 => X"F2184020F81BFFFE7FFFC1FFFCFFFFCCC07CC070BEF39B817BC9300046DC0E32",
INIT_13 => X"7FFFC0FF9EFFFFEE00F800201FFB0C06FF449000C06340AB0C1E00C0338E5DFF",
INIT_14 => X"80E000001FFE3761FDE4A830E16D3124A11F42B1E09883FFEB804000700DFFFE",
INIT_15 => X"FD3FC300C31AF042C0F87FF8E04780FFF660400033E4FFFE7FFFE07012FFFFFD",
INIT_16 => X"200F3F3FC04F88FFF4F0C00835CDFFFE7FFFE0E002FC1FFF80E000002FFFFFFF",
INIT_17 => X"F500C0701BFFFFFE7FFFF3E0037637FF40C000006FFFFFFFFF6693E080CED25D",
INIT_18 => X"7FC000E000C80BFF700000003FFFFF7FFDD90DF0009CD6C2CCF63C9F005F847F",
INIT_19 => X"E80000001F83FF7FFC9F7B23031B76452C7B80D800C0057FD524E0F027FFFFFE",
INIT_1A => X"FC9FC2B7019A3E9097C3B007009F127F9D14C0F04FFFFFFE7F83F730000003FF",
INIT_1B => X"33FC710820BD247FAD4840715FFFFFFE7FC607CC01F007FFE4000000BFB9E0FF",
INIT_1C => X"2D6900E27FFFFFFE7FFB0BF401F01A7FF500C000FFD8603CF86FFE4F0016AF98",
INIT_1D => X"7FFD8DF701FC70BFFF8000007FE12E1CF327FF57824AAF6963FBC110243ACC7F",
INIT_1E => X"FF4000021F7FD780F2F5FF8FC604BC5C647C804CFF54DC7F6D6C0081FFFFFFFE",
INIT_1F => X"BA8CFFD4A4C2AF5BA0038099DF443CFF6C4C0081FFFFF7FE7FFF41B9F0FFFD7F",
INIT_20 => X"4001F13D0F52FCFED1460104FFFFFBFE7FFFA05F0C3FF97FFFC000004FFED778",
INIT_21 => X"A5D6F3EBFFFBE7FE7FFFE05F841FF8CFBF4000083FCE5B193E02FFC53EB26F40",
INIT_22 => X"7FFFDBDE140FFE80BD4000001FDBFCC7D2017FC2BF1A4C49A0E0FB7D0FB23CFC",
INIT_23 => X"BC8F800083F56FCC2F107FF15C0BE8332076F269FF8CE0F9C5413FE5FFF3DCFE",
INIT_24 => X"0E106FFEDE1259870927E24A7170B9F274B33FCBFFE3FCFE7FFFEFD80C0FFFE4",
INIT_25 => X"159FC307F01F1BF4B02138A3FFE79CFE7FFFF65C080F80FC838FE0C089EE6F98",
INIT_26 => X"333C2033FF5B3EFE7FFFFBDFE00F00F8E641FFE0CCF1DF9C6000A9FEA61C3C50",
INIT_27 => X"7FFFFC9FE03D87FC27B83FF0C4FDDFAC6C8244FF6BFF345F8DAF18A1E73203E4",
INIT_28 => X"589267FCC1FE77C80000015F93CC3BBF89C2F1FD871277CD62C5E053FE859D7E",
INIT_29 => X"00000057C9C0673F3A42C1F463E9EF9AC10CE353FC5D235E7FFFFF7FF9F9FF7E",
INIT_2A => X"7A82380040C08F9AE5D80317F0F063AE7FFFFFFFF5FFFC7C7FE903FCC69FACF8",
INIT_2B => X"77D087B7F0001D767FFFFFFFFD653C187FED80FCE621AD700060019BE563EB7F",
INIT_2C => X"7FE63FFFFFEC5C707FE28020E5CC35A54420D8B5E3BE04FFCC8636411E80EF9A",
INIT_2D => X"BFFD78000646D231C438E3A4005EF1FE900C6202F68E1FDB36A0DB2FC380CFAE",
INIT_2E => X"EE1CEDEE209E97FEA158C39F8F961FDB30A43B2FC6003FA47FD824FFFFFFAFE3",
INIT_2F => X"B87082498F485FD465802B2F8501BFCA7FF4013FFFFFEFF2FFFEC80002E1A44A",
INIT_30 => X"AF40230E01417FFC187EB4267FFFEC65FFFFE407027CB82F3FDCE6F094A6AFFE",
INIT_31 => X"0F7F87E39FFFC393FFFFF207417F7DA25FCE023FFF2A8FFE982102E6CA8DDFD4",
INIT_32 => X"FFFFFB0FC0FFFC1F2D4500DFFE8D2FFE8C010763452E5FCA6680229E06A07FF6",
INIT_33 => X"F3448457FF322FFECD81B920F34E3FEA650C629C18E3FFE6071FD7FF0BC7481F",
INIT_34 => X"49FFE1A39C1E3FED64C83A9C1BC6FFE6001FF5F1FC8FFFFFFFFFFC87E1FFD697",
INIT_35 => X"6EC3815C27C1FF140317FED004CFFFFFFFFFFEC3F23FF32C08488795FF8D2FFE",
INIT_36 => X"03E9FFC800D7FF3FFFFFFFC1FB87F9F8684A870AFFE2E7FCD1E040B7E8FFBFE5",
INIT_37 => X"FFFFFFE1FFE3FC9FD44D01417FF957F1D3E050A7EF3FBFF6CAC3265C3DCDFF18",
INIT_38 => X"EA0061C09FF8E9DF21E050A7D2BF7FF35AC02ECF3D4BFE6801C2FFA0081DFCCF",
INIT_39 => X"99C0472FD07F7FF9F20036CF0F83FCD070C5FF98000579DFFFFFFFF0C257FFCF",
INIT_3A => X"4C05349F4E9FFC901FC0BFCFE0017B67FFFFFFDCC233FEFFF410E00663FD543C",
INIT_3B => X"01815FEE90008FE8FFFFFFF06323FEC7F81FE80353FAAB73990C204FDD7D7FF9",
INIT_3C => X"3FFEFFF89114FE1BFB0F3800483AA9BF111C931FDD377FFA4C0FB51F65F3FD40",
INIT_3D => X"FEBF18004F9CC97E35FF8E7FCA0C7FFA4C1FCB3F6557FAB86807CFFDCC000033",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"767FA87FCD8D7FF8CDDE767F050FF2B871E3C7FDE4800718EFFFFFFE698AFFCB",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"9BCE2C7FE74FE4787F84F3FEF4E60787F7FFFFFDB6C53F0BFC471803209E56FC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7FFD39FF7CD187E0B7FFFFFCC2E29FE1FF9A980398B079F9F2FFD1FFF54B7FF8",
INIT_01 => X"06FFFFFE52105F9FFF741801E88003F3F33E27FFFB387FF8EB8411FFAE0F8B7C",
INIT_02 => X"FF8C1070F77F31E7731CCFFFF476FFF8CB9423FE2F9FB44C7FFF6EFF7FFF70F8",
INIT_03 => X"F0019FFFF5F0FFF0CB94CFFC9C3FAB087FFFE5FF9FFFB8FFC6BFFFFE2413AFD3",
INIT_04 => X"F304BFFD1B3FA70A7FFFFFFFB7BF583FE18FFFFF3BF357F8FFCA103B870100E7",
INIT_05 => X"7FFFFFFFBB4FCE0070E7FFFFBC3B93FDFFE8901A3F83000FF9819FFFECF5FFF0",
INIT_06 => X"0615FFFFC9698CFDFFEA4058C0040C0FF0009FFFEBFDFFF4C1477FFB327FAB3E",
INIT_07 => X"FFE500DDC306F81FF2019FFFD5E3FFF480477FF31AFF2B3A7F08D9FFD883A780",
INIT_08 => X"C6718FFE6BDFFFF4830F7FF01DFF6FF27DE33D80FE3FA207838D7FFFE4B00AFC",
INIT_09 => X"879DFFF611FE978C7200001BFA7F438263C15FFFF27CB97EFFF6FB2DCBCFF01F",
INIT_0A => X"3800000E4FFD03FE5880723FF9AED4BEFFF70DD13C03E01F4CF19FF8B3F7FFF5",
INIT_0B => X"DA001A0FFC6B1F4FFFF7F52803BE301FCDFF9FF3438FFFF58710FFF73BFD77A6",
INIT_0C => X"FFF00B0300016C1FCDFFBFEB1B8FFFF53C22FFF1A3F9CF5E4000010002FEE3FF",
INIT_0D => X"99FF3FC41BEFFFF53CE5FFF58BFA8F60000001F00372FFFFFA8302C7FF1DCFA3",
INIT_0E => X"9EEBFFEE27FACFA2000FFFF8C1CCEFFFFEC78EB7FFCAE3B87FFFF3E778FC343F",
INIT_0F => X"000007F80000EFFFFF227F93FFE463573FFFF83C48EEF83F3BFF7FD47B1FFFE5",
INIT_10 => X"FFAE3FE8FFF959CFCFFFFA905044787F67FF7F9727DFFFC9BE2BFFD9BFF05C8E",
INIT_11 => X"67FFF28988420A7E6FFE7F18E63FFFC9BE57FF97BFF5815E000000000000AFFF",
INIT_12 => X"EFFC1B0FB7BFFFDD80A7FF85DFF11E9E000000000000BFFFFFE27FEA7FFE97E1",
INIT_13 => X"FF5FFFBD1FF5233E0000000000037FFFFFFE6079CFFF2B30B007F2351E5085FC",
INIT_14 => X"600000000002F7FFFFFF74F567FFB58C67F3E33F164F41FCEFF8000044FFFFDD",
INIT_15 => X"FFFFF27F51FFDADF8FE98797292FD67CCE2001F0637FFFDDDCBFFF097FE41C7E",
INIT_16 => X"00240F8DEA2F3018980003FE637FFF9D39BFFF78FFE659FE3C0000000004FFFF",
INIT_17 => X"383007FF2CFFFF38037FFF10FFE223FE3E000003E006FFFFFFFFFA2FDE3FE43F",
INIT_18 => X"0E7FFF11FFC3AFFE3C000001F00307FFFFFFFE27F49FF97C1E28074FFE2F0308",
INIT_19 => X"1FF300016000777FFFFFFF8BA5E7FE8C91D8002FFC2FC10138780FFF3BFFFE78",
INIT_1A => X"FFFFFFE35ED8FF585190602FFC6BE190E0F9BBFF17FFFC7019FFFED1FF8BAFFC",
INIT_1B => X"0BE1FF27FBEBF1C1E0FFDFFFABFFFCE037FFFEB53FD75FFA1FE1800008C00F0F",
INIT_1C => X"C0FC5FFFABFFF8E02FFFFD6B3FAD3FF61BF800001FF80F0FFFFFFFFE93973F33",
INIT_1D => X"6FFFFF693FA5FFFC4F07F8017FFE1A0FFFFFFFFFB4E683F08483FF4B25E9E1C1",
INIT_1E => X"67801803FFFF2301BFFFFFFFC9BD79F9429FFC490DE9C1E38FF87FFFF7FFF8B2",
INIT_1F => X"3FFFFFFFFB53CCFCA1BFFF2180E8C1E3FFFA7FFE5FFFFC3FCFFFF8E1FFABFFE2",
INIT_20 => X"417FFFC98074C1C3FFE21FFE0FFFFC3F9FFFFACC7FB3FFC807E0081FFFFF3B03",
INIT_21 => X"E02C9FFE2FFFFE1F1FFFFFB2FF33FF403EFF183FC078060053FFFFFFFD36D2F8",
INIT_22 => X"3FFFF186FFA3FCE07BFFF07E00780300269FFFFFFEE7F530B3DFFFC0E17CC0C3",
INIT_23 => X"5BFFE07E00701E9C1820F0CFFF932DC017BFFFD0737C0067E3AC1FFF3FFFFF02",
INIT_24 => X"0039FD77FFE6DC9E090FFC1F7764C027E7AC5FFCBFFFFE00FFFFEDEAFF0FFE02",
INIT_25 => X"041FFF98B665C027E79B1FFEBFFFFC01FFFFF30FFE1FF6664FFEE07F01E0CF58",
INIT_26 => X"C399CFFA9FFFFE07FFFFC64DF07FF4360FF6E03F01E063207F006693FFF1113B",
INIT_27 => X"FFFFB415C67F90360FFF2C1FC70000323F0F818FFFFE35F2820FFFA73804C023",
INIT_28 => X"007FD207EF38F3F80007FD8C3FFFC5F97F03FF9F3C04C0370759FFF49FFFFE3F",
INIT_29 => X"000FF9CB87FFF43C4C84FFFF3EFC403C3F7BFFE99FFFFFFFFFFF65B79F7EA37E",
INIT_2A => X"1422FFFFB2804079FF3FFFCBDFFFFFFFFFFE0A7BB37CD9FE0007C207FC470BEF",
INIT_2B => X"FF3BFF935FFFFFFFFFFE51FBBF7EE9FE0003FE0FFD6F97FF000819F6C7FFFB43",
INIT_2C => X"FFFD86E71E720FFE7FC0000FFDE132070001DC3C03FFFC500A5101FE7281C0D9",
INIT_2D => X"7FE0000FFCE9DA7400180C06E8FFFF343979C6FC91AFC0CDFEBCFF375FFFFFFF",
INIT_2E => X"FEBFF800307FFFCBDD483EF90197826DE63E7EF75FFFFFFFFFFB8DC780003FFE",
INIT_2F => X"30BE1F7602E4177CE67EBE475FFFFFFFFFF6D3C78F1FFFFE7FF8003F9DEDC2F5",
INIT_30 => X"86BF7C475FFFFFFFFFF9CFE7FFFFFFFE7FFC003F9E13F30BFFFEFE007A97FFE6",
INIT_31 => X"FFE437FFFFFFFFFE3FFFFE7FFE0788F3C7FC5C3FFC40FFF1CD24867B0219BF80",
INIT_32 => X"03FFFFFFFF01310F83C1719FFF78FFFEFAC802278FF0FFC36FBFACBE5FFFFFFF",
INIT_33 => X"C11971CF0394FFFF04CC4C17FFE3FFC2279F8CFE5FFFFFFFFFD757FFFFFFFE3E",
INIT_34 => X"F1B4EDB06F23FFE39B4FC35E3FFFFFFFFFAFAFFFFFFFF80E003FFE07FF0F7BE0",
INIT_35 => X"44C3D37CBFFE7FFFFF5F9FFFFFFFF1C6401FFE017F1843E0FE027E0F07E57FFF",
INIT_36 => X"FFBD7FFFFFFFC7E61E1FFE000F0D8CF07E1F1F800FF95FFFFCC4DEFF244FFFE2",
INIT_37 => X"738FFF8000058200001F018003607FFFFE0C3F3C2961FFC503801165BFFE7FFF",
INIT_38 => X"E15F0611700027FFFFFEFFDFDE3FBC47701F11253FFE7FFFFD2EFFFFFFFF1CEE",
INIT_39 => X"FFF2FFE03F07BC3F8F18720D7FF8FFFFFA11FFFFFFFE3FCE790FFFFFF1F7FEC3",
INIT_3A => X"060D8C8D7FF1FFFFE45FFFFFFFF87F1E071FFF00711BFD000F190847F00015FF",
INIT_3B => X"90BFFFFFFFF0E07E083CFE0071C7C0F0037CDAC3CEF007FFFFE9FFFFFF08EC00",
INIT_3C => X"007CFF00F1C7FF0FFE39021BFFF9C0F38FF5FFFF1F9F509F9E05CC0D7FE3FFFF",
INIT_3D => X"FFC2A00401FCF2FE8FF0FFFF3F8FCCF00C621B0D7FC3FFFF63FFFFFFFFE087FE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"DFE1FFFFFF9FBFC07471E7CAFF0BFFFCC5FFFFFFFFC30FFE03F8FFE3FD4FFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"7C602FCAFF3BFFF61BFFFFFFFFC01FFE7FF8FFFFFC4FFFFFFFF1830BC37F10FE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"97FFFFFFFFC07FFE7FFDFFFFB6EFFFFFFFFEBA8103E08000AFE9FFFC3FAF9F90",
INIT_01 => X"7FFFFFFF177FFFFFFFFFB9FFF02800006BF1FFFC3F2FDC1978007E4D7F97FFC9",
INIT_02 => X"FFFFFFFFFE0F6E0619DFFFFCBFDFDE0F780004063FC7FFA74FFFFFFFFFF9FFFE",
INIT_03 => X"00F7FFFEBFAFB266F8010C0F9F2FFE4E9FFFFFFFFFFFFFFC7FFFFFFF077FFFFF",
INIT_04 => X"FA665C002F1FFCB97FFFFFFFFFFFFFFC7FFFFFFE03FFFFFFFFFFFFFFFFFF3D06",
INIT_05 => X"FFFFFFFFFFFFFFFC7FFFFFF8E3FFFFFFFFFFFFFFFFFFFDA70003FFFE9DAFEE51",
INIT_06 => X"7FFFFFE30B7FFFFFFFFFFFFFFFFFFE420000FFFE3DCCDE4BFD24D80FFCFFFBE6",
INIT_07 => X"FFFFFFFFFFFFFE800000FFFF3FFD7E507E25BC083EFFF5D9FFFFFFFFFFFFFFFA",
INIT_08 => X"C0007FFFFFAC3E70BE29BC0BE6FFC827FFFFFFE1FFFFFFCE78FFFF02F47FFFFF",
INIT_09 => X"B939780BDE0F25CFFFFFFFC1FFFFFFA2201FFE03387FFFFFFFFFFFFFFFFFFFD8",
INIT_0A => X"FFFFFFF9FFFFFC82601FFC879A5FFFFFFC0F0FF0FFFFFFD1E0007CFFFFD17E34",
INIT_0B => X"001FF9CFE513FFFB0C68E03F03FFFFF130007807FFCE382D3679F60BC888831F",
INIT_0C => X"F0CF40021F07FFFFA8000001FFE19460B27AF6179CB698FFFFFFFFFFFFFF8206",
INIT_0D => X"E40000007FF3C8817AF8F617BCB867FFFFFFFFFFFFFF3CFE000FF2E44C7FFFE5",
INIT_0E => X"70FDF2143CD18FFFFFFFFFFFFFFC3C084003FB72BC817FF2017FC000F878FFFF",
INIT_0F => X"FFFFFFFFFFFE07984000171FFD80FFF8003B8300FC7C1FFFF20040007FC341F2",
INIT_10 => X"00009F3F7A8000F0000427FF8E068FFFF6000001FF9E41F4FDFDF021B9861FFF",
INIT_11 => X"000FFFC3FC0087FFCA00000FFF1123F501FFB06C06387FFFC307FFFFFFFFFE50",
INIT_12 => X"D780001FFF13C7E881FF174F1C40FFFF38F7FFFFFFFFFD6000007FF655800400",
INIT_13 => X"219F17EF679FFFFC3807FFFFFFFFC580000FFEF7DB00040003FFFCE1F8000FFF",
INIT_14 => X"E0FFFFFFFFFF08020033F8C87F389F007FFF9CFE07FFFFFFCFC0007FFF0CE361",
INIT_15 => X"00EFF8D81C7C1F00FFE63E00FFFFFFFFEF8000FFFF877B3FA19F10E08E3FFFFE",
INIT_16 => X"0CAC03FFFFFFFFFE5F4900F9FF99B471AF8E20FF38FFFE7FFFFFFFFFFF86683E",
INIT_17 => X"3FE100F0FF103A610F8C19F0E1FFFCFFFFFFFFFFFFF1313E7F9FD1F0007DFFF0",
INIT_18 => X"5F084FE18FFFF1FFFF3FFFFFFF0D83FE78FFAFF0007CF8080660FFFFFFFFFFFA",
INIT_19 => X"FEFFFFFFFC661F8E7FFFDF1F000000091CFFFFFFFFFFFC05FFE900F0FE107818",
INIT_1A => X"7FFF5C1F00001FD07FFFFFFFFFFFC3F981FF00F8FEFE83099F9865873FECF3FF",
INIT_1B => X"FFFFFFFFFFFFBBF02BFF807FFC9B3D821F986108FFF217FFFFFFFFFFF9BC1832",
INIT_1C => X"9C3E883FFE8560221F182833FFE2133FF3FFFFFFF27467FC7FFEBC39000060BF",
INIT_1D => X"1F5AD49FFFEB9C3FFFFFFFFFC9F73FFA7FFC3FF1020062FFFFFFFFFFFFFE3114",
INIT_1E => X"FFFFFFFF6F7DFFF67FFAFFE100003AFFFFFFFFFFFF035E2BFE5F001FFE5745DF",
INIT_1F => X"7FF0FFCF00003BFFFFFFFF0EE0E178B7FF9F941FFF404AB81F500C7FFFF907B9",
INIT_20 => X"FFFFF9288EFCE38FFE78FF3FEC874A209751A5FFFFEC03803FFFFFE63FF3E762",
INIT_21 => X"FCA9FF7FE2BF70998300FBFFFFD00180FFFFFC701813C67E7FD3FFDE0FF393FF",
INIT_22 => X"0720EFFFFFA0013DFFF2C30063E0FEF87FE7603E3DA7FFFFFFFFF30ACC0C1C3F",
INIT_23 => X"FFC33C0310FCFEF07F47003FF63FFFFFFFFFE6F780FE04FFF37FC600D2A665F9",
INIT_24 => X"7C80003FE7FFFFFFFFFFEAF800F171FFE42D8700DF860E183F409FFF1B8002FF",
INIT_25 => X"FFFFBC1C03C287FFD0BC8FE0CE8F3FD83F9CBFFF0FCCC2FFFF1C000C107FEFE0",
INIT_26 => X"317FDFF903CFFFDBBF1B7FFC0FAFBEFFFF307873DE1C0FC67A0D003F2FFFFFFF",
INIT_27 => X"FC06FFF226BFF07F00E7330FFFC00F8E74350030BFFF90BFFFFF500F8F22BFFF",
INIT_28 => X"7F8F06FFFFFF0F1E489E00107FF68763FFFEACE7FE657FFEC5FD0E3F012FFF8B",
INIT_29 => X"317F002FFFFE701BFFFD470FF00AFFF10BF88D1FB0BFFF679C0CFFEA017FFF7E",
INIT_2A => X"FD84866F0011FFE5E7F5FF3FBC4FFE5FBE18FFC605FFFFF8F80019FFFFFF0F3E",
INIT_2B => X"8FCDE57FDE63E0131E2CFFBC0FFFFFE1800023FFFFFF8E7E25FE0E3FFFD1F007",
INIT_2C => X"BF21C7760FFFFF0F3000CFFFFFFF80FE57DB7C39FF4FF803820607CC03A7FFCC",
INIT_2D => X"2000BFFFFFFFC0FE6F637E02FB7CFC0860F027C1806FFFD2BF3BEDFBC679DFCB",
INIT_2E => X"4C87FCCEEBE07C4A03C07FDF265FFF847E6BEA01800C1C67FC3FC4CBFFFFC038",
INIT_2F => X"1E0041CFEB3FFC117ECBE801971C0F9FF01FFDCFFFFE03C00FF0BFFFFFFFE3FC",
INIT_30 => X"FCCBEC0718F980DFE007F3FFFFFCFC0033F8BFFFFFFFFFF80604F903AEE07CBA",
INIT_31 => X"8383EFFFFFE1E3C0E3D87FFFFFFFFFF87E38D3F71800F974F8C00003E8FFF1AA",
INIT_32 => X"87CCDFFFFFFFFFF878DE25E8E03FF3E3F0E0719D6DFFF691FC79C41E08E0808F",
INIT_33 => X"6FFFDBE1803FC667E001619F47FFED41F8E7141F0810030F03C3D7FFFF87CF3F",
INIT_34 => X"CC7D7FFA2BFFDB97FBDF2A1FAA50031C00E3AFFFFE0F81C231FF5FFFFFFFFFF8",
INIT_35 => X"FBBF361FB86C26780023603FE1A0FC60799FDFFFFF03FFF01FFFFF67C01E721F",
INIT_36 => X"0073C7E0FE7303E6FC8FDFFFFE00FFF07FFFFECFC03E827FFFF2FFFD27FFD3AF",
INIT_37 => X"3ECFAFFFFE001FF27FF7FD0FC0396CFFFF99FFFC1FFF1D5FF83F101FF75650F0",
INIT_38 => X"1F4BDD0FC0F5E0FFFC2FFFFFFFFE57BFFC7F5039C66F2DE000F007CF83047FEE",
INIT_39 => X"80DFFFFFFFF9AEBFFFFEC7F9B6AFC3E000F43FE8C724FFD93E83BFFFFC3F01E6",
INIT_3A => X"FFFE34F8C3EE4FE0007CB6171F76FFED1E0197FFFC3F00060EE30B1F80EBE1FF",
INIT_3B => X"007C5E1FE3A5FFF7C609E7FFFC3FFE0E0E59F63F01CFD7FF1CBFFFFFFFFBBC7F",
INIT_3C => X"FD1C3FF83E1FFFDE0E7BC83F079F9FFE497FFFFFFFF5D9FFFFFDF378C61CEFF0",
INIT_3D => X"1A7440F8FF7F5FF8BFFFFFFFFFE183FFFFFA71389830CFF000605FFFE081FFD3",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFF934BFFFFE1657013A0CFF0000067FFE7437FE800FEFFF71E3F81FE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFE4CA703BB1CFF8000083FFC79CFFE800FDFFCF1E1F80FA1C1801F07E3E9FE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0780F9FFCFFBBF600031FF300E1F8672603003FDFEBD3F03BFFFFFFFFF17B7FF",
INIT_01 => X"0003E3E70C1F8E00781E03FFFEBEF80FBFFFFFFFFF1FE7FFFFEBF7BC3839EFF8",
INIT_02 => X"7C0203FF3E39F0787FFFFFFFFE7F9FFFFFC9FFBC683C9F7C08C1BAFFCFFF3F20",
INIT_03 => X"FFFFFFFFFE7C7FFFFFC5BFFD7BBFBF650B415C002FFFFA0000061F9C081F0C72",
INIT_04 => X"FFD32F385488CFD58CC04D7F20FF19800003FF30001E01FA79B603FC9E44F0A3",
INIT_05 => X"87C0BDE7FFFF0E0000001C60C3FC07E279CC00F9DE73C4FFFFFFFFFFFAFE3FFF",
INIT_06 => X"00067001FFFF0F827C880002BE0217FFFFF8FFFFFBC4FFFFFFDF4F3FEC4203A9",
INIT_07 => X"7D2800043E0CEFFFFFFC7FFFF7CCFFFFFFC5AFB3FD64019183404C186000000E",
INIT_08 => X"FFFC7FFF27D9FFFFFFBE5F38F8A381FF21F9FDFF0300188D070B8001FFFE0406",
INIT_09 => X"FF8CBF2C0D20793FA0F17BCF0FC0C7FD0E1E0000FC0000087008000A59FC7FFF",
INIT_0A => X"00EAFFFE07C2E7FD271F8800F8073CF87FD8000E81397FFFFFE0FFFF45C7FFFF",
INIT_0B => X"D71F8000F8FFFFFE7FD8018F801D7FFFFB76FFFD832FFFFFFF4D7F942D3C1FF1",
INIT_0C => X"7FBC1E74843CFFFFF402FFFA003FFFFFFF7AFFD90C067DF210CFDFF00007EBFF",
INIT_0D => X"C8C5FFFD001FFFFFFE9EFFAF019B7FF3313EFFC0030FF7FFC79784007FFFFFFE",
INIT_0E => X"FE30FFEB6392E9F7F2F6BFC0001FC1FFEF8C10007FFFFFFC7FBF638CFFF1FFFF",
INIT_0F => X"7316578103FFE1FFEE00D800FFFFFFF07F7FFFFE2BEBFFFFB287FFF260FFFFFF",
INIT_10 => X"9C0F6680FFFFFFF87E7F3FFDBA0FFFFFA38BFFD421BFFFFFFC3DFF937182A7FD",
INIT_11 => X"7E1CF9FEFD77FFFEC10FFFB0E3FFFFFFFCF1FFF3BD8033FA7BEC0F80073F41FF",
INIT_12 => X"0697E0A1C0FFFFFFFDC9FF719DC067FBBB7F95E8027F82FEBC21F7C0FFFFFFF2",
INIT_13 => X"FC7BFF30098167F9327FFAFF017D017A7E6DC7C0FFFFFFFE791BEE7FFF23FCFD",
INIT_14 => X"313FFF7F00BCE0ABFC600F803F3FFFFE7C07DFBFFFE9FCF67E2FD04387FFFFFF",
INIT_15 => X"FE7000001FFFFFF27C1FD9BFFF27066BF85F8F8709FFFFFFFE77FEB80191E7FD",
INIT_16 => X"7E1FEE7FFFBD8107F8BFFF061BFFFFFFFFC7FD3800CFEFFC314FFE7F003F3830",
INIT_17 => X"F8FF180607FFFFFFFFF7FD7801D86FFE3097FC3F801FC870EC7B00000FFFFE02",
INIT_18 => X"FE87FBF0E331FFFEB04BFC3F800BFB684066C4030FFFFE027FFFF9FFFE70CFFF",
INIT_19 => X"F021FCAFE105FEFB806C8C8787FF3FFE7FFFFFFFFCF0FFFBE4FE40005FFFFFFF",
INIT_1A => X"A1F8BDC7E3E73FFE7FFFFFFFFE38FFF1D7FD8000DFFFFCFFF8E7FB64F701FBFE",
INIT_1B => X"7FFFFFFFFA0F07E0AFFF0FC1BFFF8EFFFC1FFFAC6F2A79FFD015FE87E2497FFF",
INIT_1C => X"9FF707E0FFFF47FFF0BFFB2D882E24FF121AFF9102C05FFFF0FF1273F001FFE0",
INIT_1D => X"F4FFFDA195C2A6FF6F8AFF9001BA3FFFFFFFFC1C600EFF807FFFFFFFFBE4F7F1",
INIT_1E => X"8F8BFFF8007A8FFFFEE1F07F003F1FC07FFFFFFFFDFED1FF7FFE0703FFFD95FF",
INIT_1F => X"FEC0FF8F7C0F9FC27FFFFFFFFFFFD3FC7FF60F04FFFC33FFFD7FFDB015C282FF",
INIT_20 => X"7FFFFFFFFFD8E3FEFFEE0403FFF9F3FFF3FFFDE3D41D83FFBD8BFE97002F1FFF",
INIT_21 => X"FF5C0003FFE0F3FFEAFFF86117F981FFC008FDB9000B9FFFFEC0FF303F8787E0",
INIT_22 => X"C8FFF804537BA1FFF80CFFBFE185CFFFE7800F3FF3E3E7E07FFFFFFF7F7E03E1",
INIT_23 => X"FC087BFC03C2E5FFF8000F3FFE07E7F07FFFFFFD9F4007EC7E78001FFFF1E7FF",
INIT_24 => X"F40007BFFFFFE3707FFFFFFCDF40D811BCC0003FFFD1C7FFD6FFE617F3B7E7FF",
INIT_25 => X"7FFFFFFEAFA1B3983F01C0CFFFA7C3FFF7FFF26B13A7E7FFF400837E01C1F5FF",
INIT_26 => X"780061BFFF4FEFFF99FFCC92C50FC1FFF806FF7F40016AFDFE00EFDFFFFFF9F2",
INIT_27 => X"7BFFBFC1C30FE3FFFE64CF4FC03CB725FE8107C1FFFFF8E27FFFFFFCDFEE3FF6",
INIT_28 => X"FC6341B780367817FFB673847FFFFC0E7FFFFFFF1F7DDFEC720001FFFF5FC7FF",
INIT_29 => X"FFF8F707BFFFFF7E7FFFFF7FC0BDCDF07638013FFFBFDFFF1FFF703138EFE0FF",
INIT_2A => X"7FFFF87FD4F9FA60073C41BFFE3FDFFF53FEA0F4F80791FFFF0641F7E01E5C0F",
INIT_2B => X"0308F23FFF7F8FFF17FF33F6F80FF0FFFC912317EC1E5E0BFFFFF607BFFFFFFE",
INIT_2C => X"1FFD10F7F803F03FFF908017FA0FDF35FFFFF647FFFFFFFE7FFFF9FF9C407E00",
INIT_2D => X"FE40503BFF061F84FFFFF6EFBFFFFFFE7FFFFFFFE0207D080300FD7FFCFF1FFE",
INIT_2E => X"BFFFC6FFBFFFFFFE7FFFFFFFFE38FA380D87F4FFFCFF7FFE07F96C27F837F8DF",
INIT_2F => X"7FFFFFFFFE3DF0CC13FFFBFFF9FF3FFD0FF1EE04F34FFF1FFFC091FBFFC2FF5C",
INIT_30 => X"2E01FFFFF3FA3FFC1FEFFC1C635F9E1FFF305DFDFF43FFEDBFFFEF9D5FFFFFFE",
INIT_31 => X"6FFF983B002FDE1EFFD04FFDFF847FEFDFFFE7181FFFFFFE7FFFFFFFFF3FEB64",
INIT_32 => X"B1F033EBFFE0BFF42FFFF09D1FFFFFFE7FFFFFFFFF1FF3F32E00AFFFCBFA7FF8",
INIT_33 => X"17FFFC7FDFFFFFFE7FFFFFFFFF8FE7FA180087FF87FDFFFA8E7F5064401FDE21",
INIT_34 => X"7FFFFFFFFFC7B7FC5801DFFFDFFDFFFEC1FEB08260199A1A36F20AC3FFE05FF6",
INIT_35 => X"D800EFFF5BFCFFF0107F737E6019982E7D300B6FFFD8EFFD97FFFF9EE3FFFFFE",
INIT_36 => X"5BFF7E666D03A82A7D100A2FFFCCAFFFD7FFFFE618FFFFFE7FFFFFFFFFFF6FFD",
INIT_37 => X"3FF00C17FF1377FF37FFFFF9871FFFFE7FFFFFFFFFFC9FFED98CBFFE3FF3FFFC",
INIT_38 => X"D7FFFFFE40C7FFFE7FFFFFFFFFF07FFEFBFC7F3F3FCAFFF115FAFDFE2C08A036",
INIT_39 => X"7FFFFFFFFFE0FFFEBA38BEF63BD8FFE39FFEFAFE8508201C3FF07C27FF5DFBFF",
INIT_3A => X"38107E9F1F82FFEBBFFEF3FF0009C03EFF58360BFFFE1DFFE7F3FFFF90387FFE",
INIT_3B => X"7FFAF1F9A009007EBF001F09FFFF1EFFE7F07FFFF40FFBDE7FFFFFFFFFF1FFFE",
INIT_3C => X"3F901F65FFFF9B7FFFC73FFFFD8102267FFFFFFFFFC3FFFF14157EE60701FFDB",
INIT_3D => X"FF0FFFFFFF4364D87FFFFFFFFF03FFFF0C15FF1E4005FFCA7FF4F5F6D0090070",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFC07FFFF0812FFF4E001FFDFFFF8EBF5080D00703FC61F63EFFFDB7F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"1033FFF8F805FFACFFF05FF8CC0F00707FFF3F60E7FFDF3FFE0FFFFFFFB07E02"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFC7FCE7CE3B7EC1F1843FFFC7FFFFFF3FF1FFF3FC0067FFFFFFFFFFFFFFFFF",
INIT_02 => X"8E701FFFFCFFFFFFF3FF1FFF7F00007FFFFFFFFFFFFFF00780FE3FBFFC7BFFFF",
INIT_03 => X"F7FF3FFFFE0180FFFFFFFFFFFFFFE0F801FF833FFBB0FFFFFFFC1FF1BCF3BBEC",
INIT_04 => X"FFFFFFF81FFFC0FF07FFF87FB796FFFEFFF80FFFC1F9BDEFE6703FFFFCFFFFFF",
INIT_05 => X"9FFFF8F1FBC703FFFFE003FFE1F9BDE7F3E13FFFFCFFFFFFF3FFBFFFFC03FFFF",
INIT_06 => X"FF00073FE1F9BEE7F283FFFFFCFFFFFFF3FFBFFFFC03FFFFFFFFFFFC03FFF0FF",
INIT_07 => X"FC7FFCFF96FFFFFFF3FFFFFFF801FFFFFFFFFFFE00FFF8FDFFFFFFE0FBE3780F",
INIT_08 => X"F7FFFFFFF80C7FFFFFFFFFFF00FFFCF8FFC3FFE0FBF0FFF7FC02FFFEE3F9BF27",
INIT_09 => X"FFFFFFFFC077FE70FF837FF0F07C3FFBFC07FFF1F3FDBF8CF87FE77FB6FCFFFF",
INIT_0A => X"FFC27FFFE63E3FFCF607FFE1F39C7CF808FFEFFF3F3C7FFFF7FFFFFFF87FFFFF",
INIT_0B => X"FC7FFFCFF19FF9AC0FDF0FFF9F8C7FFFF7FFFFFFF8DFFFFFFFFFFFFFF077FF38",
INIT_0C => X"FE9F07FF9FDD3FFFF3FFFFFFF9DFFFFFFFFFFFFFF83FFF9DFFC33FFFEFFFFFFE",
INIT_0D => X"FBEFFFFFF99FFFFFFFFFFC78FE7FFFDFFFFF3FFFE7CFFFFF7FFFFF3FF1FCF9E7",
INIT_0E => X"FFFFF0387FFFFFCFFFFFBF0FE1E1FFFF7F3FF37FF8FCFFFFFCFC00FF8F9B7FFF",
INIT_0F => X"FFFFBF07C1F03FFF3EDFE1FF38DFEFFAF978007FE7077FFFFBCFFFFFFB1FFFFF",
INIT_10 => X"38EF0CFF9883E1FEF1F1817F7F00FFFFFBC7FFDFF03FFFFFFFFFF0183FFFFFEF",
INIT_11 => X"E1F3F93F7E80FDFFFBC7BF8FF01FFFFFFFFFF8001FFFFFDFFFC73F87DFFC1FF0",
INIT_12 => X"FBE7BFDFF807FFFFFFFFFE0003FFFFEF3F833F8F9FFC0400FCE9CFFFBF23F1FD",
INIT_13 => X"FFFFFF0001FFFFF3FF07FFDFBFFC0001FCE2EFFF3FFF7F6CF3E1FF3FCF80F8FF",
INIT_14 => X"FF1FFFFFBFFFC89FFE0337CF1F0CDEE77EE0BD4E1F807AFFF3FFBFFFF003FFFF",
INIT_15 => X"FE001CFF3EE9DFC33F0780071FC779FFE67FBFFFF003FFFFFFFFFF8001FFFFFF",
INIT_16 => X"DFFFC0C03FCF71FFE41F3FF7F3F3FFFFFFFFFF0001FFFFFEFF1FFFFF9FFFFFFF",
INIT_17 => X"E4EF3F8FF7FFFFFFFFFFFC0000F80FFF7F3FFFFFDFFFFFFFFE181C1F7DEDFDA1",
INIT_18 => X"FFFFFF00003007FFBFFFFFFF9FFFFFFFFE3E0E0FFDEDF9B2F3F7C3E0FFDF75FF",
INIT_19 => X"CFFFFFFFBFFFFFFFFFFF83DCFEEED93733FC7FE7FFC0F4FFE4CB1F0FEFFFFFFF",
INIT_1A => X"FFFFFCC8FF6ED167983C7FFFFF80E1FFECDB3F0FDFFFFFFFFFFC0FC0000007FF",
INIT_1B => X"3C03FEF8DF80C3FFCC97BF8F3FFFFFFFFFF80FF001F003FFF7FFFFFFBFC7FFFF",
INIT_1C => X"CCB6FF1EFFFFFFFFFFFC07F801F019FFF9FF3FFFBFE7FFFFFF9FFF70FF66516F",
INIT_1D => X"FFFE03F801FC707FFDFFFFFFBFFEF1FFFC2FFF987DB2518F7C07FEF0DB821BFF",
INIT_1E => X"FE7FFFFDBFFE387FFCF3FFE839B8529C7B82FFC100C7EBFF8CB3FF7CFFFFF9FF",
INIT_1F => X"7CFDFFE75B5C52983FFFFF8220C7CBFF8D93FF7CFFFFF9FFFFFF807E00FFFCFF",
INIT_20 => X"9FFFFF06F0C30BFF1C99FEFDFFFFF1FFFFFFC03FF03FF8FFFF7FFFFFDFFF3807",
INIT_21 => X"3C190C19FFFFF5FFFFFFC03FF81FF8307F7FFFF7EFFF3C001CFEFFF9C16C1287",
INIT_22 => X"FFFFE03FF80FFE807E7FFFFFF7E71F07CCFFFFFCC0F411863F1FFF06F083CBFF",
INIT_23 => X"7EF07FFF77E39F8FE1EF3FFE63F835CC3F8FFE12008F17FE7C7FC013FFFFEDFF",
INIT_24 => X"FFEFDFFF61EE64780EDFFE338EFF57FC4CCFC027FFFFDDFFFFFFF03FF00FFFE4",
INIT_25 => X"E67FFF07FFFFF7F8CFDFC76FFFFFDDFFFFFFF83FF00F80FC7DF01F3F7BF19FDF",
INIT_26 => X"CCFFDFEFFFE7BDFFFFFFFC3FF00F00F8187E001F3DFE0FDF9FFF67FF39E3C43F",
INIT_27 => X"FFFFFF7FF03F87FC183FC00F3DFE0FCF93FDBDFF8C00CC3FF66FE75F07F3EFF8",
INIT_28 => X"3FE398033CFF8FEFFFFFFF3FE433C87FF2430E037803AFF19DC61FCFFFE2FCFF",
INIT_29 => X"FFFFFFCFF23F90FFC3C33E0B1C123FE33F0F1CCFFF9DE33FFFFFFFFFF1FFFFFE",
INIT_2A => X"8383FFFFC03B5FE31C1FFC8FFF7FDD9FFFFFFFFFF9FFFFFC3FF1FC033E7FDFEF",
INIT_2B => X"8C1F788FFF7FBE6FFFFFFFFFFE043FF83FF1FF031E1FDEE7FFFFF1F7F99C18FF",
INIT_2C => X"FFFFFFFFFFF39FF03FFCFFDF1C03CE46BBFF3733FCC1FDFF0F87F7FF1E7B5FE3",
INIT_2D => X"7FFE7FFFFD810C323BFF17C3FF61F3FF1F8FE3FE0675BFE3CD3F3C9FFCFFBF27",
INIT_2E => X"11FF1BF1DF218FFF3EDFC27E7765BFE3CB3BFC9FF8FF7FC3FFE01BFFFFFFCFE0",
INIT_2F => X"3FFF83C0772FBFE7923FEC9FF9FF7FE9FFF800FFFFFFCFF1FFFF0FFFFE1E207B",
INIT_30 => X"607FE4BFFDBFFFEDFFFF341FFFFFCC63FFFFF7FFFE3F383FC03F1DFFEF399FFF",
INIT_31 => X"F0FFC7E07FFFE00FFFFFFBFFFCFFBC3E603FFEFFFE3DBFFF1FFF03983262BFE7",
INIT_32 => X"FFFFFDFFFDFFDCDF32BDFFBFFF0E9FFF0FFF071C34D13FF3D8FFE5BFFB5EFFE7",
INIT_33 => X"FCBCFBCFFFC39FFF0FFFBF1F00917FF3D9FFE5BFE31EFFF7F8FFE7FF07FFF7FF",
INIT_34 => X"8FFFFF9FE3A17FF1D93FFDBFEC3DFFF7FFFFF9FFFBFFFFFFFFFFFEFFFCFFE667",
INIT_35 => X"D33C7F3FC83BFFE7FCEFFCFFFC3FFFFFFFFFFFFFFEFFFB700FB4F873FFF19FFF",
INIT_36 => X"FC07FEFFFFCFFFFFFFFFFF7FFF7FFDBF8FB6F8F9FFFCDFFF1FE07F8FF7417FF9",
INIT_37 => X"FFFFFFBFFF9FFEBFE7B3FEBCFFFE4FFE1FE06F9FF0417FF8D33CDE3FD23BFFEF",
INIT_38 => X"F3FF9E3E7FFF67E0CFE06F9FE0C1FFFC433FDE3FD2BFFF8FFE01FF3FF7FBFF3F",
INIT_39 => X"EFC07F1FE081FFFE73FFCE3FD077FF1F8F04FFDFFFFCFDCFFFFFFFDFC3CFFEDF",
INIT_3A => X"7FFFCC7F9177FF1F80007FEFFFFF33EFFFFFFFEFC3EFFFEFF9EF1FF91FFE73C3",
INIT_3B => X"80013FF61FFF8FE7FFFFFFFBE3EFFFEFFDE017FCCFFCD88FEF0C503FE183FFFE",
INIT_3C => X"FFFFFFFD71F3FF77FDF0C7FFC7FCD87FE71CF0FFE1C9FFFC7FFFCCFFBA2FFE7F",
INIT_3D => X"FCC0E7FFC07F78FFC7FFE1FFEBF2FFFC7FFFF8FFBACFFCC78007DFF8EFFFFFF0",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"87FFE7FFEE72FFFCFE3E71FFBABFFCC7FE03CFFEF7FFF8F81FFFFFFC99F9FF7F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FC3E23FF58BFF887FFF8F7FFF8E7F87FEFFFFFFECEFCFFBBFF78E7FCE07F91FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFE3BFFFF3DF81FF3FFFFFF7EFE7FBBFF1DE7FC787F87FE03FFCFFFE6B6FFFC",
INIT_01 => X"FDFFFFFF9E1F3FDDFF87E7FE187FFFFC033E1FFFF3C5FFFCEC7C0FFF517FF383",
INIT_02 => X"FFF7EF8F0F00FFF8031C3FFFF88DFFFCCC6C1FFF517FC7B3FFFF8DFFFFFE7F07",
INIT_03 => X"00007FFFF90BFFFCCC6C3FFFE2FFCCF7FFFFFBFFFFFF3F003E7FFFFFCB1C9FE1",
INIT_04 => X"FCFC7FFEE6FFC8F7FFFFFFFFCFFF9FC01F9FFFFFCCFCCFFFFFF3EFC7FF00FFF8",
INIT_05 => X"FFFFFFFFC7BF8FFF8FEFFFFFC7FC4FFFFFF36FE63F80FFF001807FFFF10BFFFC",
INIT_06 => X"F9F3FFFFF19E63FFFFF3BFE60003F3F000007FFFF20BFFF8FEFEFFFDCFFFCCC3",
INIT_07 => X"FFF9FFE3000107E002007FFFE617FFF8FFFEFFFDE5FFCCC7FFF73FFFE77FC7FF",
INIT_08 => X"06007FFF8C37FFF8FCFEFFFDE7FF880FFE00007FF1FFC107FC7CFFFFF8CFF9FF",
INIT_09 => X"F87CFFFBEBFF187DFC00000471FF87FC7C3F3FFFFC43C4FFFFF8FF3308000FE0",
INIT_0A => X"C000000031FE07FF9F7FEFFFFE31E27FFFF80C1F3C001FE00C007FFF3C2FFFF9",
INIT_0B => X"E3FFF9FFFF8CE13FFFF804CFFFFE0FE00C007FFC7C5FFFF9F8F1FFFACFFE7861",
INIT_0C => X"FFFFF0ECFFFFE3E00C007FF3FC5FFFF9C3E1FFFA57FEF0C18000010001FCE7FF",
INIT_0D => X"1800FFF7FC5FFFF9C3E3FFFE67FCF0DF800001F000FCF7FFFCFCFE3FFFE6309F",
INIT_0E => X"E1E7FFF5FFFCF09F800FFFF8C030E7FFFF78718FFFF31C67FFFFFC08FFFFF3C0",
INIT_0F => X"800007F80000E7FFFFBD804FFFF89C30FFFFFE13CFEFFBC03800FFE7FCBFFFF9",
INIT_10 => X"FFCFC027FFFE663F3FFFFC9FDFC7FB806000FFE708BFFFF1C1E7FFEE5FFC63BF",
INIT_11 => X"1FFFFC8F8FC3F9806001FFE0097FFFF1C1CFFFE85FF9FF3F8000000000009FFF",
INIT_12 => X"E003FFF0597FFFE1FF9FFFEA7FFDFE7F8000000000007FFFFFFC8019FFFF181F",
INIT_13 => X"FF3FFFD2BFF9E0FF800000000000FFFFFFFF7F843FFFCCCF8FFFFC071FC0FC00",
INIT_14 => X"800000000001FFFFFFFF87031FFFC673E00FFC071FC07C00E007FFFF9A7FFFE1",
INIT_15 => X"FFFFFB80CFFFE3207FE7F80739E01E00C1DFFFFFBEFFFFE1DC7FFFD6BFF9C3FF",
INIT_16 => X"FFE3F00FFBE0C00087FFFFFFBEFFFFE1387FFFA7BFFBC7FFC00000000003FFFF",
INIT_17 => X"07CFFFFFBDFFFFC000FFFFAFBFFB9FFFC0000003E001FFFFFFFFFC3031FFF8C0",
INIT_18 => X"01FFFFAFBFFB9FFFC0000001F000FFFFFFFFFFC80C7FFE43FFE7F88FFFE0FC00",
INIT_19 => X"E000000160000FFFFFFFFFF3C31FFF3371C7FFCFFFE03E010787FFFFB9FFFF80",
INIT_1A => X"FFFFFFFC61C7FF9FB00FFFCFFFE41E001F067FFF93FFFF8007FFFF6FBFF39FFF",
INIT_1B => X"F81FFFC7FBE40E001F003FFF27FFFF000FFFFFCF7FE73FFDE000000008C007FF",
INIT_1C => X"3F003FFF27FFFF001FFFFE9B7FCCFFFBE00000001FF807FFFFFFFFFF1C70FFC3",
INIT_1D => X"1FFFFD997FC3FFF7F0F800017FFE07FFFFFFFFFFC71E7FFCFC7FFF8321E61E00",
INIT_1E => X"F87FE003FFFF1CFE7FFFFFFFF1C307FE7E7FFF8101E63E0070003FFF6FFFFF40",
INIT_1F => X"1FFFFFFFFC60C3FF3F7FFFC180E73E0000023FFF4FFFFFC03FFFFD117FC7FFF5",
INIT_20 => X"9F3FFFE980733E0000023FFF1FFFFFC07FFFFF20FFCFFFEFF81FF01FFFFF0303",
INIT_21 => X"1FCCBFFF1FFFFFE0FFFFFA6DFFCFFF9FC000E03FFFF807FFCFFFFFFFFE3831FF",
INIT_22 => X"FFFFFA59FFDFFF5F8000007FFFF803FFE17FFFFFFF040CFF5FBFFFE0E07B3F00",
INIT_23 => X"8000007FFFF000E3F81FFF3FFFE3C33FE79FFFE0707BFF801FCC3FFE1FFFFFFD",
INIT_24 => X"FFF801EFFFF8E381F11FFFE07063FFC01FCC3FFE9FFFFFFFFFFFF651FFFFFCFF",
INIT_25 => X"F80FFFE73063FFC01FD8FFFC9FFFFFFFFFFFE4B1FFFFFB9D8001007FFFE0C067",
INIT_26 => X"3FDBFFFCBFFFFFFFFFFFE933FFFFE7F38001003FFFE0603F80FFE777FFFE1EF8",
INIT_27 => X"FFFFDB63F9FFDF8F8000D01FFF00003DC0F07E7BFFFFC60E7C07FFDFB803FFC0",
INIT_28 => X"80003C07FF0003FFFFF8027BFFFFF9070007FFFFBC03FFC0FF9BFFF8BFFFFFFF",
INIT_29 => X"FFF006387FFFF8C3C303FFFFBE03FFC3FFB9FFF1BFFFFFFFFFFFBB63E0FF3F3F",
INIT_2A => X"F3C1FFFF3E7FFF87FFBDFFF3BFFFFFFFFFFFB6E7C0FEF87F80003C07FC38F3EF",
INIT_2B => X"FFB9FFE33FFFFFFFFFFF6CE7C0FCE7FF8000000FFCF067FFFFF7E60E3FFFFC7C",
INIT_2C => X"FFFEFDFFE1FC1FFFFFC0000FFCF13E07FFFFE3C307FFFF9FF9E0FFFF7E7FFF07",
INIT_2D => X"FFE0000FFDF1E607FFE7F3F9FBFFFFC7C4E039FEFF7FFF03FF3DFFC73FFFFFFF",
INIT_2E => X"014007FFCDFFFFF3E33001FDFF6FFF83FF3EFF073FFFFFFFFFFD7BFFFFFFFFFF",
INIT_2F => X"3F8000FBFE03FF83FF7E7F873FFFFFFFFFFB37FFFFFFFFFFFFF8003FFCF1FE06",
INIT_30 => X"7F3F3F873FFFFFFFFFF227FFFFFFFFFFFFFC003FFEE3FF0C000101FF867FFFF8",
INIT_31 => X"FFF7EFFFFFFFFFFFBFFFFE7FFE078FFC380383C0033FFFFE0EE081F3FE187FFF",
INIT_32 => X"83FFFFFFFF0106F07C3F8FE000C7FFFF033801F7FFF07FFC1F3F9F3E3FFFFFFF",
INIT_33 => X"3EFF8FF0FC73FFFFF8FC0DE7FFE0FFFC1F1F9F7E3FFFFFFFFFE7CFFFFFFFFFFF",
INIT_34 => X"FE3C0C400F1FFFFD878FDC7E7FFFFFFFFFCF9FFFFFFFFFFF803FFE07FF007C1F",
INIT_35 => X"4303CC7C7FFFFFFFFF9F7FFFFFFFFE3F801FFE017F077C1F01FD81F0F81CFFFF",
INIT_36 => X"FF3CFFFFFFFFF81FE01FFE000F030F0F81E0E07FF0073FFFFF041E00C43FFFFC",
INIT_37 => X"FC0FFF800003FBFFFFE0FE7FFC9FDFFFFFF03F03C91FFFFE00000E647FFFFFFF",
INIT_38 => X"FEA0F9EE8FFFEFFFFFFCFFC01E007FFF80000E24FFFFFFFFFE21FFFFFFFFE01F",
INIT_39 => X"FFFCFFE03F007FFFF0078C0CFFFFFFFFFC0FFFFFFFFFC03FFE0FFFFFF003FCFF",
INIT_3A => X"F803F08CFFFFFFFFF83FFFFFFFFF80FFF81FFFFFF0E7FE000FE6F7B80FFFF3FF",
INIT_3B => X"E07FFFFFFFFF1FFF803FFFFFF0FFFF0FFC7F253C310FFDFFFFF1FFFFFF071FFF",
INIT_3C => X"807FFFFFF0FFFFFFFFC1FDFC0007FDFFFFE5FFFF1F8F8F606003F00CFFFFFFFF",
INIT_3D => X"FFFCDE07FE03FE01FFE0FFFF3F9F8300F001E30CFFFFFFFF80FFFFFFFFFF7FFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FF1FFFFFF8FC000F80007C9FFF7FFFF03FFFFFFFFFCFFFF83FFFFFFFCFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"F8002FC9FFC7FFF807FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFEFEF3C380FFFE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"8FFFFFFFFFFFFFFFFFFFFFFFB67FFFFFFFFF39FEFCFF7FFF9FF1FFFC3F9FE000",
INIT_01 => X"FFFFFFFF177FFFFFFFFFC7FFFFCFFFFFE7E1FFFC3F1FE000FC007E4CFFEFFFF1",
INIT_02 => X"FFFFFFFFFFF07FF9F81FFFFC3FBFE000FC0004067FFFFFC73FFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFE3F9FCC01FC010C0FBFDFFF8E7FFFFFFFFFFFFFFFFFFFFFFF073FFFFF",
INIT_04 => X"FC661C001FFFFF38FFFFFFFFFFFFFFFFFFFFFFFE03BFFFFFFFFFFFFFFFFFC1F9",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF803BFFFFFFFFFFFFFFFFFFED8FFFFFFFE1F9F9C23",
INIT_06 => X"FFFFFFE0F33FFFFFFFFFFFFFFFFFFF7DFFFFFFFE3FDF3C31FE24180003FFFCE1",
INIT_07 => X"FFFFFFFFFFFFFF3FFFFFFFFF3FDE3C39FF243C07C1FFF9C7FFFFFFFFFFFFFFFD",
INIT_08 => X"FFFFFFFFFF9E7C387F283C07C1FFF01FFFFFFFFFFFFFFFF1F8FFFF01F83FFFFF",
INIT_09 => X"7E387807E1FFC43FFFFFFFFFFFFFFFC1A01FFE00FC3FFFFFFFFFFFFFFFFFFF9F",
INIT_0A => X"FFFFFFFFFFFFFF01E01FFC007C3FFFFFFFFFFFFFFFFFFFE1FFFFFFFFFFCE3C78",
INIT_0B => X"801FF8001E0CFFFCF0671FC0FFFFFFFE3FFFFFFFFFC01C717878F007FF0700FF",
INIT_0C => X"FF3FC00200FFFFFFCFFFFFFFFFE008007C78F00FFF3087FFFFFFFFFFFFFFFC01",
INIT_0D => X"F7FFFFFFFFF00080FCF8F00FFF381FFFFFFFFFFFFFFFC003800FF1023E7F7FF9",
INIT_0E => X"FCFDF00FFF107FFFFFFFFFFFFFFFC3F38003F78F7EFF0003FE803FFFF807FFFF",
INIT_0F => X"FFFFFFFFFFFFFFEF80000FFFFEFFFFFFFFC47CFF03FCFFFFFBFFFFFFFFC081F1",
INIT_10 => X"80007FFFFCFFFFFFFFFBD80001FE7FFFFBFFFFFFFF8181F301FDF01E7E01FFFF",
INIT_11 => X"FFF0003FFC007FFFF3FFFFFFFF0FC3F201FFF01FF807FFFFFFFFFFFFFFFFFF9F",
INIT_12 => X"E7FFFFFFFF0FE7E701FFF03FE03FFFFFC70FFFFFFFFFFE7F8000FFF839FFFBFF",
INIT_13 => X"C19FF01F807FFFFFC7FFFFFFFFFFF9FF8000FFE7C3FFFBFFFC0003E007FFFFFF",
INIT_14 => X"FFFFFFFFFFFFF3FF800FFFEFFFC760FF80007C01FFFFFFFFEFFFFFFFFF03F31F",
INIT_15 => X"801FF01FFF83E0FF001E01FFFFFFFFFFCFFFFFFFFF80F37FC19FF01F01FFFFFF",
INIT_16 => X"F363FFFFFFFFFFFF9FFFFFF9FF8678FFCF8FE00007FFFFFFFFFFFFFFFFFF8FFF",
INIT_17 => X"3FFFFFF0FF0FFDFFCF8FC0001FFFFFFFFFFFFFFFFFFE3FFF807FE1FFFF82000F",
INIT_18 => X"9F0FD0007FFFFFFFFFFFFFFFFFF1FFFFFFFFCFFFFF8307F7FE1FFFFFFFFFFFFC",
INIT_19 => X"FFFFFFFFFF87FF8FFFFF9FFFFFFFFFF903FFFFFFFFFFFFF9FFFFFFF0FE0FFFE7",
INIT_1A => X"FFFF9FFFFFFFFFCFFFFFFFFFFFFFFC0181FFFFF8FE007CF61F9FD800FFF30FFF",
INIT_1B => X"FFFFFFFFFFFFC3F01DFFFFFFFC63007C1F9FD807FFE00FFFFFFFFFFFFE3FF803",
INIT_1C => X"7E3FFFFFFE79001C1F1F900FFFF00FFFFFFFFFFFFC7FE001FFFF3FF9FFFFE07F",
INIT_1D => X"1F1DA47FFFF003FFFFFFFFFFF1FF0003FFFE3FF1FDFFE1FFFFFFFFFFFFFFBEF3",
INIT_1E => X"FFFFFFFF8FFC0007FFFCFFE1FFFFF9FFFFFFFFFFFFFC61E7FF9FFFFFFE3881C0",
INIT_1F => X"FFF8FFCFFFFFF9FFFFFFFFFFFF01878FFFDFFFFFFF3F84E01F1F6DFFFFF0007F",
INIT_20 => X"FFFFFE270EFF1E7FFFB8FFFFE07F84E0171F43FFFFF0007FFFFFFFF83FF01803",
INIT_21 => X"FF26FFFFEC7F8E80031E07FFFFE0007FFFFFFF8000103801FFE3FFDFFFF00FFF",
INIT_22 => X"073E1FFFFFC000FFFFFFFC001C000007FFC7603FFD9FFFFFFFFFFDF8F3F3FDFF",
INIT_23 => X"FFFCC000FF00000FFF87003FF1FFFFFFFFFFFB0FFF0103FFFC6EFFFFCC7F9E00",
INIT_24 => X"FF00003FEFFFFFFFFFFFF307FF0F0FFFF81EFFFFC07FFFE03F7E7FFFE00001FF",
INIT_25 => X"FFFFCFE3FC3E7FFFE07EFFFFC17FFFE03FE27FFC0FC301FFFFE00003FF80101F",
INIT_26 => X"C0FEFFFF003FFFE3BFE6FFF80F9FC1FFFFC0780FFFE3F03FFC02003F1FFFFFFF",
INIT_27 => X"FFFDFFFA267FFFFFFF0730FFFFFFF07FF80E00307FFFEF7FFFFF9FF070FE7FFF",
INIT_28 => X"800F01FFFFFFF0FFF07C000FFFFF001FFFFF33F801FCFFFF03FE003F011FFFF3",
INIT_29 => X"C0F8001FFFE07007FFFE78F00FF9FFFE07FFFE1F809FFF9B9FFBFFF200FFFFFF",
INIT_2A => X"FE78F990FFF7FFF9DFFBFE3F803FFFBBBFF7FF8603FFFFFF000007FFFFFFF0FF",
INIT_2B => X"BFF3FE7FC01FFFFB1FE3FF3C07FFFFFE00001FFFFFFFF1FFC3F0001FFFE1F003",
INIT_2C => X"BFE03F71FFFFFFF030003FFFFFFFFFFF8FE00007FF8FF807FC07F833FC6FFFF7",
INIT_2D => X"20007FFFFFFFFFFF9F800001FC7FFC0780FFD83FFFDFFFE57FC7F1FFC007E033",
INIT_2E => X"BF000001F3FFFC3C03FF803FDE3FFFEAFF87F3FF8003E007FFFFC307FFFFFFC0",
INIT_2F => X"1FFFBE3F18FFFFDCFF07F3FF8003F01FFFFFFBFFFFFFFC0000007FFFFFFFFFFF",
INIT_30 => X"FF07F7FF07067F1FFFFFF7FFFFFF00000C007FFFFFFFFFFFF80300FC4FFFFC7C",
INIT_31 => X"FC7FE7FFFFFE03C01C003FFFFFFFFFFF800701F81FFFF8F8FF3FFFFF1BFFFE39",
INIT_32 => X"7800BFFFFFFFFFFF873FC3F0FFFFF0F3FF1FF19D9BFFF8F7FF87F7FE071F7F0F",
INIT_33 => X"9FFFE7C1FFFFC187FFFF1E61B3FFF1AFFF1FE7FF07EFFC0FFC3FCFFFFFF80F00",
INIT_34 => X"FFFCFFFCE7FFE24FFC3FCDFFA78FFC1FFF1F9FFFFF80003FFE003FFFFFFFFFFF",
INIT_35 => X"FC7FD9FFB763F87FFFDF1FFFFE2003FFFE603FFFFFFFFFFFFFFFFF87FFFE0C1F",
INIT_36 => X"FF8FC01F0070FFF9FF703FFFFFFFFFFFFFFFFF0FFFFE7C7FFFF1FFFE1FFFE49F",
INIT_37 => X"FF301FFFFFFFFFFDFFFFFE0FFFF8F0FFFF87FFFFFFFFE83FFFFFDFFFF071E0FF",
INIT_38 => X"FFB7FE0FFFF3F0FFFC1FFFFFFFFF997FFFFF9FFFC060CDFFFF0FFFC00003FFF1",
INIT_39 => X"803FFFFFFFFE327FFFFF7FFF88E003FFFF0BFFE70023FFE0FF7C0FFFFFC0FFF9",
INIT_3A => X"FFFF4CFFBCE18FFFFF83880FE071FFC0FFFE0FFFFFC0FFF9FF1FFC1FFFE7F1FF",
INIT_3B => X"FF833FFFFC23FFC03FF61FFFFFC001F1FFBE083FFFDFE7FF007FFFFFFFFCC5FF",
INIT_3C => X"02E3FFFFFFE00021FFFC003FFFBFDFFE3EFFFFFFFFF90BFFFFFE887FB803CFFF",
INIT_3D => X"E7F800FFFF3F9FF87FFFFFFFFFFA17FFFFFC8A3FA00FEFFFFF9F3FFFFF03FFE0",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFFE427FFFFFD927FA39FEFFFFFFF1FFFFF80FFF00001FFF8FFC00001",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFF9277F838FEFFFFFFF87FFFFE07FF00003FFF0FFE00001E3E001FFFE7F1FE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_3B => X"3FFCF3FFC00600007FBFFF07FFFFE1FFFFFFFFFFF80007FFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3A => X"FFE0FF001F81FFFF9FFCF1FFC00600007F7FFE07FFFFE3FFFFFFFFFFE007FFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFF7E1FFF8E003FFDEFFF0E7F8F00200007FEFFF01FFFFE0FF",
SIM_COLLISION_CHECK => "NONE",
INIT_3C => X"7FDFFF03FFFFE0FFFFFFFFFFFE0101DFFFFFFFFFFFFFFFFFFBE4FF180703FFEF",
INIT_3D => X"FFFFFFFFFF836407FFFFFFFFFFFFFFFFF3E4FFF84003FFEEFFF8F3F9E0060000",
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFBFFFFFC7FF00003FFCFFFE00601FFC003FFFE7E3F007FFFFFFFFFD86FFF",
INIT_01 => X"0001FC1FFFE00E01FFE003FFFE7CF8007FFFFFFFFFA05FFFFFF22F3F8007CFFF",
INIT_02 => X"FFFC03FF3E7DF007FFFFFFFFFF40BFFFFFF22F3FD003DF7FF8FFB9FFFFFFFE00",
INIT_03 => X"FFFFFFFFFC833FFFFFF66F7FC3803F66F87F1DFFDFFFFC000001E07FFFE00C71",
INIT_04 => X"FFE4FFBFC780FFC67CFF2C80DFFFE180000000FFFFE001F9FE7803FC1E38F07F",
INIT_05 => X"7FFF8C1800000E00000003FF3C0007E1FE3000F81E03C3FFFFFFFFFFF302FFFF",
INIT_06 => X"00000FFE00000F81FF7000013E020FFFFFFFFFFFEC3DFFFFFFE8DFBFEFC3FF92",
INIT_07 => X"FEF000033E0C1FFFFFFFFFFFD83BFFFFFFE89FB3FEE7FFBA7FFFCC0000000000",
INIT_08 => X"FFFFFFFFB837FFFFFFD13FB8FF63FFBADFF9FDFF030007FE07047FFE00000401",
INIT_09 => X"FFD27FA0FEE07F7A5FF67BFF0FC03FFE0E0FFFFF00000007FFF000077FFCFFFF",
INIT_0A => X"FFE77FFE07C1FFFEC70FFFFF00000007FFE00007FFF8FFFFFFFFFFFF7A2FFFFF",
INIT_0B => X"E70FFFFF00000001FFE00006FFFCFFFFFC81FFFEFCFFFFFFFF90FF88DEFC1F7A",
INIT_0C => X"FFC0018EFFFDFFFFF801FFFCFFDFFFFFFFA5FF81FFFE7CFBEFC0FFF00003F7FF",
INIT_0D => X"F0C3FFF9FFBFFFFFFF25FFCFFFE77DFBCF00FFC00307E3FFE78FFBFF80000001",
INIT_0E => X"FF4BFFCF9FEE7BFB0E008FC0000FE3FFCF83FFFF80000001FFC01FFEFFF3FFFF",
INIT_0F => X"8EE02780001FC3FFCE003FFF00000001FF803FFC13E7FFFFC283FFFB9FBFFFFF",
INIT_10 => X"DC001FFF00000001FF80FFFE7C07FFFFC387FFE7DF7FFFFFFF4BFFDF8FFE33F9",
INIT_11 => X"FFE3FFFFFE0FFFFF0107FFDF1EFFFFFFFF87FFBFC3FE37FC86F3F78000FF83FF",
INIT_12 => X"068FFF3E3DFFFFFFFE97FFBFE3FE6FFCC6FFF9E801FE01FF3C1E0FFF00000001",
INIT_13 => X"FE97FFBFF7FF6FFE4EFFFCFF00FE00FC7E1E3FFF00000001FFE7F1FFFFFFFFFE",
INIT_14 => X"4FFFFE7F007F0073FC1FFFFFC0000001FFFFE07FFFF003F87E1FE07C7DFFFFFF",
INIT_15 => X"FE0FFFFFE0000001FFFFE07FFFC701F3F83FCFF8FBFFFFFFFC9FFF3FFFEFEFFE",
INIT_16 => X"FFFFF1FFFF3F8007F87FBFF9F7FFFFFFFD2FFE3FFFFFE7FF4F3FFF7F001FC000",
INIT_17 => X"F87FBFF9EFFFFFFFFD2FFE7FFFF807FF4F8FFF3F800FF000EC04FFFFF0000001",
INIT_18 => X"FD5FFCFF1FF007FF4FC7FF3F8007FCF040183FFFF0000001FFFFFFFFFF7FCFFF",
INIT_19 => X"4FE7FF2FE003FFFC00107F7FF8000001FFFFFFFFFEFFFFFFE3FF7FFFCFFFFFFF",
INIT_1A => X"C0007E3FFC180001FFFFFFFFFC3FFFFFCFFEFFFFBFFFFFFFFD5FFC7B0FE007FF",
INIT_1B => X"FFFFFFFFFC0F07FF9FFDF03F7FFFF1FFF9BFF8339FE187FF6FF3FF07E188FFFF",
INIT_1C => X"BFFBF81EFFFF85FFFBFFFC33F9E1C3FFADF9FF0101E03FFFE000FC0FFFFE001F",
INIT_1D => X"FF7FFE3FF1C1C1FFB079FF0000721FFFF0000003FFFF007FFFFFFFFFFC0007FF",
INIT_1E => X"D079FF00003C9FFFFF000000FFFFE03FFFFFFFFFFFFFE1FF3FF7F8FEFFFE13FF",
INIT_1F => X"FF00007083FFE03FFFFFFFFFFFFFE3FCFFE7F0FDFFF837FFF7FFFE3FF1C1C1FF",
INIT_20 => X"FFFFFFFFFFFF03FDFFCFFBF9FFF1F7FFF6FFFE3C3003C1FFD279FF7B001E0FFF",
INIT_21 => X"FF9FFFF7FFF0F7FFFFFFFFBEF007C3FFEFFBFE7D00070FFFFF0000FFC07FF81F",
INIT_22 => X"EDFFFFDFF787C3FFEFFBFC7DE00387FFF80000FFFC1FF81FFFFFFFFFFF8003E3",
INIT_23 => X"F7FBFC7E0001C3FFF00000FFFFFFF80FFFFFFFFE7F8007E3FF7FFFF7FFE1E3FF",
INIT_24 => X"F800007FFFFFFC0FFFFFFFFE3F80200E7EFFFFEFFFE1C3FFFDFFF9DFF7CFC3FF",
INIT_25 => X"FFFFFFFC1FC07C7E7DFE3FDFFFC7C7FFDDFFE18F17DFC3FFFFFB7CFF0000E4FF",
INIT_26 => X"3DFF9F9FFF8FE7FFDBFFEC1E03FFE3FFFBFD00FF8000F23FFC00003FFFFFFE0F",
INIT_27 => X"BBFFDFFC00FFC1FFFB9D00FF80007B1FFF00F83FFFFFFF1FFFFFFFFF3F81FFF8",
INIT_28 => X"FD9E804FC0083C0FFFC9FC7BFFFFFFFFFFFFFFFFFF83FFF03BFFFFBFFF9FCFFF",
INIT_29 => X"FFFFF8F87FFFFFFFFFFFFFFFFF03FE0007C7FF7FFF3FCFFFBBFFBFCC381FC1FF",
INIT_2A => X"FFFFFFFFE307FC6007C3FF7FFF3FCFFFF7FF3F0CF80FD0FFFDFA800FC0003E07",
INIT_2B => X"03F7FEFFFE7F9FFF77FE3C0EF807B07FFEEFC00FF0003E07FFFFF9F87FFFFFFF",
INIT_2C => X"F7FE1F0FF807B07FFEEF600FFC003E03FFFFF9B87FFFFFFFFFFFFFFFE3BFFC00",
INIT_2D => X"FF7F2007FE01FF03FFFFF9107FFFFFFFFFFFFFFFFFFFFE0003FFFCFFFEFF3FFF",
INIT_2E => X"7FFFF9007FFFFFFFFFFFFFFFFFFFFC0001FFF3FFFEFF3FFEEFFE8FDFF803B8BF",
INIT_2F => X"FFFFFFFFFFFFF8300DFFF7FFFDFF7FFFEFFFCFFCF033BF3FFF7FA007FF01FF83",
INIT_30 => X"1C01F7FFFBFA7FFDCFFFDFFC603FDE3FFFBFC003FF80FFC27FFFF0003FFFFFFF",
INIT_31 => X"DFFFDFF8001FDE3FFF9FC003FFC4FFF03FFFF8003FFFFFFFFFFFFFFFFFFFF0F8",
INIT_32 => X"7FDFF017FFC07FF81FFFFF003FFFFFFFFFFFFFFFFFFFE1FC1C00A7FFF3FAFFFD",
INIT_33 => X"0FFFFF803FFFFFFFFFFFFFFFFFFFC3FC3C008FFFC7FCFFFFBFFF9FE3400FDE1E",
INIT_34 => X"FFFFFFFFFFFFCFFE3C01CFFF9FFCFFFBBE7F3F876007DA0C79DDF83FFFC03FF8",
INIT_35 => X"3C00DFFF9BFDFFFB60FE7F076007D81C38DFF81FFFE01FFE0FFFFFE01FFFFFFF",
INIT_36 => X"18FC7EFF6D0FC81C391FF81FFFF01FFF0FFFFFF807FFFFFFFFFFFFFFFFFF9FFE",
INIT_37 => X"7DFFFC0FFFFC0FFFCFFFFFFE00FFFFFFFFFFFFFFFFFF7FFF3C009FFF3FF1FFF7",
INIT_38 => X"EFFFFFFF803FFFFFFFFFFFFFFFFFFFFF3C003FFC3FC9FFF713FCFCFF2C07C008",
INIT_39 => X"FFFFFFFFFFFFFFFF7DC07F083BD9FFF78FFCF9FF0507C0007EFFFC2FFFBE07FF",
INIT_3F => X"EFC1FFF0F803FFFDFFF04FFC300000003FEFFF01FFFFE0FFFFFFFFFFFFC07E01"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
WRITE_MODE_B => "WRITE_FIRST",
WRITE_MODE_A => "WRITE_FIRST",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"7FFFFEAAAAAAAAAFFFFFFFFFFFFFFFFAAAAAABFFFFFFFFFFFAAFFFFFAAAAAFEA",
SRVAL_A => X"0",
INIT_3D => X"9556ABFFFFF955BFFFFFFFFEAFFFFFFFFFFFFFFFFFFFFFFEAAAAABFFFFFFFFFF",
INIT_3C => X"FFFFFEAAFFFFFFFFFFFFFFFFFFFFFFFD7FFFFFEAAAAAAAABFFFFFFFFFFFFFFFA",
INIT_3B => X"AAA9ABFFFFFFFFFFFAAFFFFFEAAAAFAA9556AAFFFFF955BFFFFFFFFFFFABFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFAAAAAAFFFFFFFFFFFFFFFFEABFFFFFFFFFFFFFFFFFFFFFFFD",
INIT_39 => X"7FFFFFFAAAAAAAABFFFFFFFFFFFFFFFAEAAAABFFFEFFFFFFFAAABFFFEAAAAFEA",
INIT_38 => X"A556AABFFFFE55BFFFFFFFFFFFABFFFFFFFFFFFFFFFFFFFAAAAAAFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFAFFFFFFFFFFFFFFFFFFFD7FFFFFEAAAAAAAABFFFFFFFFFFFFFFFA",
INIT_36 => X"EAAABFFFFABFFFFFEAAABFFFEAAAABFAAA5AAAFFFFFE55BFFFFFFFFFFFABFFFF",
INIT_35 => X"FFFFFFFFFFFFFFEAAAAAAFFFFFFFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFFFFFFFD",
INIT_34 => X"7FFFFFAAAFAAAAABBFFFFFFFFFFFFFFAAAAAFFFFFABFFABEAA96AFFFEAAAABFE",
INIT_33 => X"AAAAABFFFFFE55BFFFFFFFFFAFABFFFFFFFFFFFFFFFFFFAAAAAAAFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFD7FFFFFAAAFFAAAABAFFFFFFFFFFFFFFA",
INIT_31 => X"AAABFFFFFEAFFFFEAA96ABFFFAAAFFFFAAAAAAFFFFFF55FFFFFFFFFEAAABFFFF",
INIT_30 => X"FFEAFFFFFFFFFFAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFD",
INIT_2F => X"7FFFFFEAABFEAAAAFFFFFFFFFFFFFFFEAAAFFFFFFAABFFFAAAA59BFFFAABFFFE",
INIT_2E => X"AAAAAAFFFFFF96FFFFFFFFFAAAAFFFFFFFEAFFFFFFFFFEAAAAAAAFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFD7FFFFFEAEBFEAAAABFFFFFFFFFFFFFFF",
INIT_2C => X"AAAFFFFFFAAAAAFAAAA55BFFFA9BFFFEAAAAAAFFFFFF95FFFFFFFEAAAAAFFFFB",
INIT_2B => X"FFFFFFFFFFFFFAAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD",
INIT_2A => X"7FFFFFFAEBFFEAAAFFFFFFFFFFFFFFFFAAABFFFFFAAAAAAAAAA56BFFFA56FFFF",
INIT_29 => X"EAAAAABFFFFF95BFFFFFFAAAAABFFFEBFFFFFFFFFFFFEAAAAABAAFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD7FFFFFFFFAFFEAAABFFFFFFFFFFFFFFF",
INIT_27 => X"AAABFFFFFEAAAAAAAAA9AFFFFE56FFFFFAAAAABFFFFF95BFFFFFEAAAAAAFEAAA",
INIT_26 => X"FFFFFFFFFFFFE6AAAAFAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD",
INIT_25 => X"7FFFFFFFFAAFFEAAAFFFFFFFFFFFFFFFAAABFFFFFAAAAAAAAAAAAFFFFE96FFFF",
INIT_24 => X"FAAAAABFFFFF95BFFFFFEAAAAAAAAAAABFFFFFFFFFFFA6AAAAFEAFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD7FFFFFFFFEABFEAAAFFFFFFFFFFFFFFF",
INIT_22 => X"EAAAFFFFFAAAAAAAAAAAAFFFFF96FFFFFEAAAAAFFFFFD5BFFFFFAAAAAAAAAAAA",
INIT_21 => X"BFFFFFFFFFFF96AAAAFEAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9",
INIT_20 => X"7FFFFFFFFEABFFAAAFFFFFFFFFFFFFFFEAAAFFFFFAAA6AAAAAAAAFFFFFE6FFFF",
INIT_1F => X"FFAAAAABFFFFE5BFFFFFAAAAAAAAAAAAAFFFFFFFFFFE5AAAAAFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFA97FFFFFFFFFABFFFAABFFFFFFFFFFFFFF",
INIT_1D => X"FAAABFFFFA955AAAAAAAAFFFFFE5FFFFFFEAAAABFFFFE5BFFFFFAAAAAAAAAAAA",
INIT_1C => X"ABFFFFFFFFFE5AAA6AFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA9",
INIT_1B => X"7FFFFFFFFFFFFFFEABFFFFFFFFFFFFFFFBEAAFFFFA555AAAAAAAAFFFFFF5BFFF",
INIT_1A => X"FFEAAAAAFFFFF9BFFFFEAAAAAAAAAAAAABFFFFFFFFF96AAAAAFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFEA557FFFFFFFFFFFFFFFABFFFFFFFFFFFFFF",
INIT_18 => X"FFEABFFFFAA556AAAAAAAFFFFFF5BFFFFFEAAAAAFFFFF9BFFFFEAAAAAAAAAA9A",
INIT_17 => X"ABFFFFFFFFF9AAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA55",
INIT_16 => X"7FFFFFFFFFFFFFFFEAFFFFFFFFFFFFFFFFEABFFFFA555AAAAAAAABFFFFF97FFF",
INIT_15 => X"FFEAA9AAFFFFF9BFFFFAAAAAAAAAAA96ABFFFFFFFFE5AAAAABFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFAA5557FFFFFFFFFFFFFFFFAFFFFFFFFFFFFFF",
INIT_13 => X"FFEAAFFFFEAAAAAAAAAAABFFFFFD6FFFFFEAAAAAFFFFF9BFFFEAAAAAAAAAAA95",
INIT_12 => X"ABFFFFFFFFE6AAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA5569",
INIT_11 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAABFFFFFAAAAAAAA9ABFFFFFE5BFF",
INIT_10 => X"FFFAAA9AFFFFF9BFFFAAAAAAAAAAAA95AFFFFFFFFF96AAAAAAFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFE956A97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFAAAFFFFFEAAAAAAA56BFFFFFE5BFFFFFEAA5ABFFFFDBFFFAAAAAAAAAAAAA5",
INIT_0D => X"BFFFFFFFFE56AAAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA55AA9",
INIT_0C => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAFFFFFEAAAAA956BFAFFFF96FF",
INIT_0B => X"FFFFAA55BFFFFDBFFEAAAAAAAAAAAAA5BFFFFFFFFA56AAAAAABFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFA55AAA97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFAAAAFFFFFFAAAAA55ABFBFFFF95BFFFFFEA55BFFFF9BFFAAAAAAAAAAAAAAA",
INIT_08 => X"BFFFFFFFE9555AAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAA5",
INIT_07 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAABFFFFFAAAA955AABFFFFFE57F",
INIT_06 => X"FFFFFAA5AFFFF9BFEAAAAAAAAAAAAAAABFFFFFFF956A5AAAAEBFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFAAAAAA997FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFAAABFFFFFAAA955AAABFFFFFE56FFFFFFEA5ABFFFAFFAAAAAAAAAAAAAAAA",
INIT_03 => X"BFFFFFFA556A6AAABFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAA699",
INIT_02 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAABFFFFFEAA556AAAAFFFFFE55B",
INIT_01 => X"FFFFFFA9ABFFFEFAABEAAAAAAAAAAAAAAFFFFFE55555AAAAFFFFFFFFFFEABFFF",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFEA96AAA6A97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SRVAL_B => X"0",
INIT_3F => X"FFFFFFFFFFFFFFFFAAAAABFFFFFFFFFFFFFFFEAAFFFFFFFFFFFFFFFFFFFFFFFD"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_A => X"0",
INIT_3C => X"FFFFFFFE0E0FFF8FFE0000003FFF07FFF8E30FFFFE00FFFF800003FFC01FFF80",
INIT_32 => X"FFFFFE0003FFE3E0C002007FFFF07FFFF000F8FFFBE0FFFC3F00187FFC01FFF8",
INIT_2E => X"000007FFFFC07FFFC0203C01F8F87FFC07C0007FFF00FFFE7FFFFFFFFFFFF01F",
INIT_38 => X"FC000001FFFF9FFFF01F807FFF00FFFFBC0001FFE007FFF07FFFFFC00007FFFF",
INIT_0F => X"000000003FFFFFFFC1E00000070000040000000000F8FFFFFC00000007FFFFFE",
INIT_13 => X"7FFFFFFFFFFFFFFC000000007FFFFFFFFFFF00000000801000000000007FFFFF",
INIT_35 => X"3C0000FFF007FFF87FFFFF0003FFFFFFFFFFFF0001FFFCFFF003000FFFFE7FFF",
INIT_10 => X"FFF00000070000000000000000FFFFFFFC0000000FFFFFFE7FFFFFFFFFFFFFF0",
INIT_1C => X"F3C00001FFFFFFFE7FFFFFFFFE0FE7FFFE0000007FFFFFFFFFFFFF8000F9E0F0",
INIT_37 => X"FFFFFFC0007FFF7FF8000003FFFFBFFFE01F807FFF80FFFF3C0001FFE007FFF0",
INIT_27 => X"7FFFFFFFFFC07803FFC0000003FFFFF0000003FFF00003FFF8100000F80C1FFF",
INIT_28 => X"FFFC000003FFFFF0000000FFF80007FFFC3C0000FFFC1FFE0038003FFFFF03FE",
INIT_1F => X"FF03FFF8003FE1E7C000007C003807FFF3E00003FFFFFFFE7FFFFFFFFF0003FF",
INIT_20 => X"E00000F8003C07FFE3E00003FFFFFFFE7FFFFFFFFFC007FFFF8000003FFFFFFF",
INIT_B => X"0",
INIT_0D => X"FC00000007FFFFFE7FFFFFFFFFFFFFE0000000001FFFFFFF800000000E030000",
INIT_1E => X"FF8000007FFFFFFFFF0FFFF0007FE1E38001003E003807FFF3C00003FFFFFFFE",
INIT_1B => X"C0000007007FFFFFF3E00000FFFFFFFE7FFFFFFFFE0FFFFFF80000007FFFFFFF",
INIT_23 => X"FF0000000FFFFFF01E00FFFF8007C3FFC00001FC00700FFF8380000FFFFFF3FE",
INIT_30 => X"1F80187FFE00FFF27FFFCBFFFFFFF39FFFFFF80001FFC7C0000003FFFFC07FFF",
INIT_2B => X"03E0007FFF807F9E7FFFFFFFFFFBC007FFFE000001FFFFF800000E0FFE0007FF",
INIT_1D => X"7FFFFFFFFE038FFFFE0000007FFFFFFFFFDFFFE0007DE0F08000000F007DE7FF",
INIT_0A => X"000000001FFFFFFF000000000C0380000700000000FFFFFFF800000007FFFFFE",
INIT_29 => X"0000003FFC000FFFFC3C0000FFFC1FFC00F0003FFFE21CFE7FFFFFFFFE000001",
INIT_26 => X"0000001FFFFFC3FE7FFFFFFFFFF0FF07FF80000003FFFFE000001FFFC00003FF",
INIT_04 => X"7FFFFFFFFFFFFF00F80007800FEF0000000000003E07C3F0000FC00003FFFFFF",
INIT_14 => X"000000007FFFFFFFFFFFC00000F3E01800000000007FFDFFFC0000000FFFFFFE",
INIT_3A => X"800003FFE00FFFE07FFFFFF00000FC1FFFFFFFF03C1FFF1FFE000000FFFF8FFF",
INIT_2F => X"C0007C3FF8F07FF80FC0107FFE00FFF67FFFFFFFFFFFF00FFFFFF00001FFDF84",
INIT_0C => X"00000000003EFFFFFC00000007FFFFFE7FFFFFFFFFFFFFE0000000001FFFFFFF",
INIT_06 => X"000000001E07C1F8017C000003FFFFFFFC00400003FFFFFE7FFFFFFFFFFFFF00",
INIT_2A => X"FC7C00003FFC3FFC03E0007FFF803E7E7FFFFFFFFE000003FFFE000001FFFFF0",
INIT_03 => X"F800C00001FFFFFE7FFFFFFFFFFFFF07FE007FC007CF00000000000E7F0FC7F0",
INIT_39 => X"F03F80FFFF00FFFF8C0001FFE00FFFE07FFBFFE00003FE3FFFFFFFE03C3FFF3F",
INIT_31 => X"7FFFF81FFFFFFFFFFFFFFC0003FFC3C1800001FFFFC07FFFE000FC7FFDF07FF8",
INIT_09 => X"7FFFFFFFFFFFFF800000000F0FFFFFFC000000000C03C0700780000001FFFFFF",
WRITE_MODE_A => "WRITE_FIRST",
INIT_33 => X"0003003FFFFC7FFFF00040FFFFE0FFFC3E00187FFC01FFF87FFFF800FFFFFFFF",
INIT_25 => X"F80000F800000FFF0000001FFFFFE3FE7FFFFFFFFFF07F03FE00000007FFFFE0",
INIT_36 => X"7FFFFF00003FFFFFFFFFFF8000FFFE7FF0010007FFFF3FFFE01F807FFF80FFFE",
INIT_07 => X"0380000001FFFFFFFC00000007FFFFFE7FFFFFFFFFFFFF000000001F07FFFFF0",
INIT_12 => X"FC00000007FFFFFE7FFFFFFFFFFFFFF0000000007FFFFFFFFFF6000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_18 => X"7FFFFFFFFFFFFFFFC00000007FFFFFFFFFFFF00003F3E07D000800000020FBFF",
INIT_11 => X"00000000017FFFFFFC0000000FFFFFFE7FFFFFFFFFFFFFE0000000003FFFFFFF",
INIT_0B => X"000000000E00000000000000007FFFFFF800000007FFFFFE7FFFFFFFFFFFFFC0",
SRVAL_A => X"0",
INIT_3B => X"7FFEFFF9E000701FFFFFFFFC1C1FFF1FFE0000003FFF07FFF0F38FFFFE00FFFF",
INIT_1A => X"FFFFFF0000F1E0F860000000007FFFFFF3E000003FFFFFFE7FFFFFFFFFFFFFFF",
INIT_16 => X"000000000030FFFFFBE000000FFFFFFE7FFFFFFFFFFFFFFF000000007FFFFFFF",
INIT_05 => X"6000070E07FFFC00000000001E07C3F8001EC00003FFFFFFFC00400003FFFFFE",
INIT_15 => X"FFFFE00001F7E03C000000000038FFFFF98000000FFFFFFE7FFFFFFFFFFFFFFE",
INIT_19 => X"F00000007FFFFFFFFFFFFC0001F1E0F8C0000000003FFBFFFBF000001FFFFFFE",
INIT_0E => X"7FFFFFFFFFFFFFF0000000001FFFFFFF80C000000703000000000000007CFFFF",
INIT_3E => X"F8001FFFF001FFFF00018FFFC07FFF007FFC3FFFF8000007FFFFFFFF0607FF87",
INIT_24 => X"00003FFF800183FFF00001FC00000FFF8300001FFFFFE3FE7FFFFFFFFFF0001B",
INIT_22 => X"7FFFFFFFFFF0017FFF8000000FFFFFF83F00FFFF000FE3FFC00000F8007C07FF",
INIT_08 => X"F800000007FFFFFE7FFFFFFFFFFFFF000000001F07FFFFF8000000001C07C0F8",
INIT_02 => X"000FE00003FFFFFFFC00E00000FFFFFE7FFFFFFFFFFFFFFFFF01FFC003840000",
INIT_3D => X"FF0000003FFF87FFF8001FFFF401FFFF800007FFC03FFF007FF83FFFF000000F",
INIT_01 => X"0000003FFF1FCFF00007FC0003FFFFFFFC00E000003FFFFE0000000000000000",
INIT_34 => X"F000007FFFC0FFFE3E00007FF003FFF87FFFFE0007FFFFFFFFFFFF0003FFF9F8",
INIT_2D => X"FFFF800003FFFFCC00000FFFFF800FFFE0701C01F9F87FFC03C0007FFF007FDE",
INIT_2C => X"7FFFFFFFFFFFE00FFFFF000003FFFFF800000FCFFF0003FFF0780800E1FC3FFC",
INIT_17 => X"FBF000000FFFFFFE7FFFFFFFFFFFFFFF800000003FFFFFFFFFFFE00003F3E07E",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_21 => X"C3E00007FFFFFBFE7FFFFFFFFFE007FFFF8000001FFFFFFFFF01FFFE001FE1FF",
SRVAL_B => X"0",
INIT_3F => X"0001DFFF807FFF007FFF0FFFFF1800001FFFFFFF0103FFC7FF8000001FFFEFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_03 => X"FFFFFFFFFE07FFFF3003FFFF01FFF0007FFFFFFFFFFFC00001FFFFFFF0E07FFF",
INIT_04 => X"0003FFFF01FFF0007FFFFFFFFFFFE000007FFFFFF0003FFFFFFC000000FFFFFF",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"FFFE0000007FFFFFFFFFF837FFFFFFFFFFFFFFFFFFFFFFFE7C00000003FFFFFF",
INIT_01 => X"03FFFFFFE1E0FFE3FFF8000007FFFFFFFCC1FFFFFC03FFFF1003FFFF80FFFC00",
INIT_3D => X"FFFF01F8000001FFFFFF0000C07FFFFFFFFFFCF3FFFFFFFFFFFFFFFFFFFFFFFE",
INIT_3C => X"7F8000000FFFFFFFFFFE0000000003FFFFFA0000E07FFFFFFFFFFFF3FFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFE7FC000000FFFFFFFFF800000000003FFFFFE000000FFFFFF",
INIT_3A => X"FFFFFF73FFFFFFFFFFFFFFFFFFFFFFFE7FE000000FFFFFFFF000000000000FFF",
INIT_39 => X"FFFF001FC0FFFFFFFFFFFFF3FFFFFFFFFFFFFFFFFFFFFFFE7FF000000FFFFF00",
INIT_38 => X"0000000000001FFFFFFF003FE1FFFFFFFFFFFFDBFFFFFFFFFFDFFFFFFFFFFFFE",
INIT_37 => X"7FF0007FFFFFFC000000000000003FFFFFFFC0FFF6FFFFFFFFFFFF9BFFFFFFFF",
INIT_36 => X"FFC3FFFFFFFFFFFE7FE001FFF0FFF000000000000000FFFFFFFBE1FFFBFFFFFF",
INIT_35 => X"BFFC3F83FFFFFFFFFFE0FFFFFFFFFFFE7FE001FE80FF8000000000000003FFFF",
INIT_34 => X"FFC3F3FFF0FFFFFE7FF03F81FFFFFFFFFFF07FFFFFFFFFFE7FC001F800FF8000",
INIT_33 => X"00000000000FFFFFFF03F3F8001FFFFFFFE07F81FFFFFFFFFFF83FFFFFFFFFFE",
INIT_32 => X"7C00000000FEF80000000000003FFFFFFC07FFF8000FFFFFFFC07FC1FFFFFFFF",
INIT_31 => X"FFF81FFFFFFFFFFE4000018001F870000000000000FFFFFFF01F7FFC01E7FFFF",
INIT_30 => X"FFC0FFF8FFFFFFFFFFFC1FFFFFFFFFFE0003FFC001FC00F00000000001FFFFFF",
INIT_2F => X"C07FFFFC01FFFFFFFF81FFF8FFFFFFFFFFFC0FFFFFFFFFFE0007FFC003FE01F8",
INIT_2E => X"0000000003FFFFFC00FFFFFE00FFFFFFFFC1FFF8FFFFFFFFFFFE07FFFFFFFFFE",
INIT_2D => X"001FFFF003FE01F80000000007FFFFF803FFFFFF00FFFFFFFFC3FFF8FFFFFFFF",
INIT_2C => X"FFFF03FFFFFFFFFE003FFFF003FEC1F800000000FFFFFFE007FFFFFF81FFFFFF",
INIT_2B => X"FFC7FFFCFFFFFFFFFFFF83FFFFFF1FFE7FFFFFF003FFF80000000001FFFFFF80",
INIT_2A => X"0FFFFFFFC1FFFFFFFFC3FFFC7FFFFFFFFFFFC1FFFFFF07FE7FFFFFF803FFFC10",
INIT_29 => X"00000007FFFFFF003FFFFFFFC1FFFFFFFFC7FFFE7FFFFFFFFFFFC0FFFFFFC0FE",
INIT_28 => X"7FFFFFF800FFFC0000000007FFFFFE00FFFFFFFFC3FFFFFFFFE7FFFF7FFFFFFF",
INIT_27 => X"FFFFE0FFFFFFE07E7FFFFFE000FFFFC000000007FFFFF801FFFFFFFFC7FFFFFF",
INIT_26 => X"FFE7FFFF7FFFFFFFFFFFF0FFFFFFF80E7FFFFFC0001F9FC00000180FFFFFE007",
INIT_25 => X"FFFFFFFFCF9FFFFFFFE7FFFF7FFFFFFFFFFFF87FFFFFFC027FFFFF80001F3F80",
INIT_24 => X"0007FE1FFFFF007FFEFFFFFF8F9FFFFFFFF3FFFF7FFFFFFFFFFFF83FFFFFFF00",
INIT_23 => X"7FFFFF80000FFF0007FFFFFFFFFC00FFF87FFFFF8F87FFFFFFF3FFFFFFFFFFFF",
INIT_22 => X"FFFFFC3FFFFFFF807FFFFF800007FC001FFFFFFFFFF803FFE07FFFFF1F87FFFF",
INIT_21 => X"FFF37FFFFFFFFFFFFFFFFC1FFFFFFFE07FFFFFC00007F8003FFFFFFFFFC00FFF",
INIT_20 => X"E0FFFFF67F8FFFFFFFFDFFFFFFFFFFFFFFFFFC1FFFFFFFF07FFFFFE00000FCFC",
INIT_1F => X"FFFFFFFFFF803FFFC0FFFFFE7F1FFFFFFFFDFFFFBFFFFFFFFFFFFE0EFFFFFFF8",
INIT_1E => X"7FFFFFFC0000FFFFFFFFFFFFFE00FFFF81FFFFFEFE1FFFFFFFFFFFFF9FFFFFFF",
INIT_1D => X"FFFFFE06FFFFFFF87FFFFFFE8001FFFFFFFFFFFFF801FFFF03FFFFFCDE1FFFFF",
INIT_1C => X"FFFFFFFFDFFFFFFFFFFFFF04FFF3FFFC7FFFFFFFE007FFFFFFFFFFFFE00FFFFC",
INIT_1B => X"07FFFFF8041FFFFFFFFFFFFFDFFFFFFFFFFFFF00FFF8FFFE7FFFFFFFF73FFFFF",
INIT_1A => X"FFFFFFFF803FFFE00FFFFFF0001FFFFFFFFFFFFFEFFFFFFFFFFFFF807FFC7FFE",
INIT_19 => X"7FFFFFFE9FFFFFFFFFFFFFFC00FFFFC00E3FFFF0001FFFFEFFFFFFFFC7FFFFFF",
INIT_18 => X"FFFFFFC07FFC7FFE7FFFFFFE0FFFFFFFFFFFFFF003FFFF80001FFFF0001FFFFF",
INIT_17 => X"FFFFFFFFC3FFFFFFFFFFFFC07FFC7FFE7FFFFFFC1FFFFFFFFFFFFFC00FFFFF00",
INIT_16 => X"001FFFF0041FFFFF7FFFFFFFC1FFFFFEC7FFFFC07FFC3FFE7FFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFC003FFFFC00001FFFF8C61FE1FF3FFFFFFFC1FFFFFE23FFFFE07FFE3FFE",
INIT_14 => X"7FFFFFFFFFFFFFFFFFFFF800FFFFF8001FFFFFF8E03F83FF1FFFFFFFE1FFFFFE",
INIT_13 => X"00FFFFE07FFE1FFE7FFFFFFFFFFFFFFFFFFF8003FFFFF0007FFFFFF8E03F03FF",
INIT_12 => X"1FFFFFFFE0FFFFFE007FFFF03FFE01FE7FFFFFFFFFFFFFFFFFFF0007FFFFE000",
INIT_11 => X"FFFFFF70703C07FF9FFFFFFFF0FFFFFE003FFFF03FFE00FE7FFFFFFFFFFF7FFF",
INIT_10 => X"FFF0001FFFFF8000FFFFFF60203807FF9FFFFFF8F07FFFFE001FFFF03FFF807E",
INIT_0F => X"7FFFF807FFFF1FFFFFC0003FFFFF000FFFFFFFE0301007FFC7FFFFF8007FFFFE",
INIT_0E => X"001FFFF81FFF007E7FF000073FFF1FFFFF80007FFFFC001FFFFFFFF000000FFF",
INIT_0D => X"E7FFFFF8003FFFFE001FFFF81FFF003E7FFFFE0FFFFF0FFFFF0001FFFFF8007F",
INIT_0C => X"FFFFFFF000001FFFF3FFFFFC003FFFFE001FFFFC0FFF003E7FFFFEFFFFFF1FFF",
INIT_0B => X"FC0007FFFFF000FFFFFFFBF00001FFFFF3FFFFFF803FFFFE000FFFFC07FF801E",
INIT_0A => X"7FFFFFFFFFFFFFFFE0001FFFFFC001FFFFFFF3E0C3FFFFFFF3FFFFFFC01FFFFE",
INIT_09 => X"0003FFFC07FFE0027FFFFFFFFFFFFFFF8000FFFFFF8003FFFFFF00C0F7FFFFFF",
INIT_08 => X"F9FFFFFFF00FFFFF0001FFFE03FFF0007FFFFFFFFFFFFFF80003FFFFFF0007FF",
INIT_07 => X"FFFE0000FFFFFFFFFDFFFFFFF80FFFFF0001FFFE03FFF0007FFFFFFFFFFFF800",
INIT_06 => X"000FFFFFFE001FFFFFFC0001FFFFFFFFFFFFFFFFFC07FFFF0001FFFE01FFF000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SRVAL_B => X"0",
INIT_02 => X"FFF8000000FFFFFFFCE3FFFFFF03FFFF3003FFFF80FFF8007FFFF3FFFFFF8000",
SRVAL_A => X"0",
INIT_05 => X"7FFFFFFFFFFFF000001FFFFFF8003FFFFFFC0001C07FFFFFFE7FFFFFFE07FFFF",
INIT_00 => X"7FFFC7FFFFFE00000FFFFFFF8101FFC7FFE0000007FFFFFFFC003FFFF801FFFF",
INIT_3F => X"FFFFD037FFFFFFFFFFFFFFFFFFFFFFFE0000000003FFFFFFFFFF01FC3C000001"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_21 => X"FFDF00001FFFFF7FFCE1FFFFFFFFFFFFFFFFFFFFFFEFFFFE7FFC0020000FFFFF",
INIT_06 => X"0000001FFCFFFFFFFFFFFFFFFFFFFF8000000001C03FFFFFFFDBE7FFFFFFFF1F",
INIT_0E => X"FF020FFFFFEFFFFFFFFFFFFFFFFFFFFC7FFC0FFFFF00FFFC0000000007FFFFFF",
SRVAL_A => X"0",
INIT_1A => X"7FFFE0000000003FFFFFFFFFFFFFFFFE7E00000701FFFFFFE0603FFFFFFFFFFF",
INIT_1F => X"7FFF0030000007FFFFFFFFFFFFFE007FFFE0000000FFFF1FE0E0F3FFFFFFFFFF",
INIT_12 => X"F800000000FFF81FFE000FFFFFFFFFFFFFFFFFFFFFFFFF807FFFFFFFFE000000",
INIT_2C => X"401FFF8FFFFFFFFFCFFFFFFFFFFFFFFE7FFFFFFFFFF007FFFFF80000001FFFF8",
INIT_38 => X"7FFFFFF0000FFF0003FFFFFFFFFFE0FFFFFFE0003F9FF2000000003FFFFFFFFF",
INIT_04 => X"FF99E3FFFFFFFFC7FFFFFFFFFFFFFFFE00000001FC7FFFFFFFFFFFFFFFFFFE00",
INIT_07 => X"FFFFFFFFFFFFFFC000000000C03FFFFFFFDBC3FFFFFFFE3FFFFFFFFFFFFFFFFE",
INIT_1C => X"FFC0000001FEFFFFE0E07FFFFFFFFFFFFFFFFFFFFF801FFE7FFFC00600001FFF",
INIT_37 => X"FFFFFFFFFFFFFFFE7FFFFFF00007FF00007FFFFFFFFFF0FFFFFFE0000F8FFF00",
INIT_22 => X"F8C1FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FF89FC0027FFFFFFFFFFE07000003FF",
INIT_30 => X"FFFFF800FFFFFFE000000FFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFF00003FF",
INIT_2A => X"FFFF0000000FFFFE3FFFFFC07FFFFFFC400FFFF9FFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2D => X"DFFFFFFFFFFFFFFE7FFFFFFFFF8003FFFF000000003FFFF8FFFFFE003FFFFFFC",
INIT_0C => X"00003FFDFFFFFFFFF0000000001FFFFFFF870FFFFFCF7FFFFFFFFFFFFFFFFFFE",
INIT_09 => X"FFC787FFFFFFFBFFFFFFFFFFFFFFFFFE5FE001FFFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_2B => X"7FFFFF803FFFFFFCE01FFFC3FFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFE0FFF",
INIT_32 => X"FFFF7FFFFFFFFFFE7FFFFFFF00000FFC00000E6207FFFF0FFFFFF801FFFFFFF0",
INIT_24 => X"7FFFFFC01FFFFFFFFFFFFC000000FFFFFFFF00003FFFFFFFC081FFFFFFFFFFFF",
INIT_16 => X"001FFFFFFFFFFFFFE0000006007FFFFFF0701FFFFFFFFFFFFFFFFFFFFFFFF000",
INIT_13 => X"FE600FFFFFFFFFFFFFFFFFFFFFFFFE007FFFFFF83C0000000000001FFFFFFFFF",
INIT_0D => X"F8000000000FFF7FFF070FFFFFC7FFFFFFFFFFFFFFFFFFFC7FF00FFFFF80FFFE",
INIT_2F => X"E000000007FFFFE3FFFFFC007FFFFFE0000007FFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2E => X"7FFFFFFFFC0003FFFC00000001FFFFF1FFFFFC007FFFFFF800003FFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFC0FFE00000003FCFFFFE0603FFFFFFFFFFFFFFFFFFFFFC007FC",
INIT_35 => X"FFFFE0004F9FFF800000FFFFFFDFFFFFFFFFFFFFFFFFFFFE7FFFFFF80001FFE0",
INIT_34 => X"0003FFFF1FFFFC3FFFFFF0005FFFFFE000007FFFFFFFFFFFFFFFFFFFFFFFFFFE",
SRVAL_B => X"0",
INIT_18 => X"E0F03FFFFFFFFFFFFFFFFFFFFFFE00007FFFF0000000000001FFFFFFFFFFFFFF",
INIT_10 => X"7FFFFFFFFF000000000000000001FFFFFC000000007FFE0FFE020FFFFFFFFFFF",
INIT_20 => X"FFFFFFDFF10001FFFFC700001FFFFF1FE8E0FFFFFFFFFFFFFFFFFFFFC00FFFFC",
INIT_39 => X"7FFFFFFFFFFFC1FFFFFF80007F1FFC000000001FFFDFFFFFFFFFFFFFFFFFFFFE",
INIT_02 => X"FFFFFFFFFFFF800007E00003C07FFFFFFFFFFBF9FFFFFFF8FFFFFFFFFFFFFFFE",
INIT_19 => X"FFFFFFFFFFF800707FFFE00000000006FFFFFFFFFFFFFFFE0000000F01FFFFFF",
INIT_11 => X"0000000003FFFFFFFC00000000FFFC0FFE000FFFFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_1D => X"E0E07BFFFFFFFFFFFFFFFFFFFE00FFFC7FFFC00E00001FFFFFFFFFFFFFFFC00F",
INIT_23 => X"FFFFFFFFFFFFFFFE7FF8FFC00FFFFFFFFFFFFC000000FFFFFF9F00003FFFFFFF",
INIT_01 => X"00000000E8FFFFFFFFFFFFFFFFF000001FFE0003C0FFFFFFFFFF81B3FFFFFFFE",
INIT_17 => X"C000000F00FFFFFFF0703FFFFFFFFFFFFFFFFFFFFFFFC0007FFFFE0000000000",
INIT_0F => X"FFFFFFFFFFFFFFF07FFFFFFFFF000000000000000003FFFFFC000000003FFE0F",
INIT_08 => X"00000000007FFFFFFFD7C3FFFFFFFFFFFFFFFFFFFFFFFFFE070000FFFFFFFFFF",
INIT_36 => X"00003FFFFF8FFFFFFFFFFFFFFFFFFFFE7FFFFFF00001FF80000FFFFFFFFFF87F",
INIT_26 => X"FFFF0000FFFFFFFC4001FFFFF07FFFFFFFFF87FFFFFFFFFE7FFFFFC0FFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFC007FFFFFF000000000000003FFFFFFFFFFF000000000FFFCFF",
INIT_33 => X"7FFFFFFE00003FF80000FFFE0FFFFE1FFFFFF800FFFFFFF000003FFFFFFFF0FF",
INIT_05 => X"FFFFFFFFFFFFFFFE00000007FC7FFFFFFFFFFFFFFFFFFF0000000001E07FFFFF",
INIT_28 => X"FFF0FFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFC0000003FFFFFFFFFFC0FEFFFFFC",
INIT_29 => X"7FFFFFFFFFFF8FFFFFFF80000007FFFFFFFFFFE07F7FFFFC6007FFFDFFFFFFFF",
INIT_31 => X"00001FFFFFFFFC3FFFFFFFFFFFFFFFFE7FFFFFFFE00007FF0000000007FFFFC7",
INIT_03 => X"00000001C07FFFFFFFFEF3F07FFFFFF1FFFFFFFFFFFFFFFE00000000F8FFFFFF",
INIT_0B => X"7FE007FFFFFFFFFFFF9FFFFFFFFFFFFFC0000000003FFFFEFF870FFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFE1FE003FFFFFFFFFFFFFFFFFFFFFFFFFE00000000003FFFFF",
INIT_27 => X"0003FFFDD9FFFFFFFFF8CFFFFFFFFFFE7FFFFFCFFFFFFFFFFFFFE0000001FFFF",
INIT_00 => X"7FFFFFFFFFFFFFFE0000000049FFFFFFFFFFC7FFFF0000007FFE0003C07FFFFF",
INIT_1E => X"FFFFFFFFF003FFF87FFF001E000007FFFFFFFFFFFFFF801FFFE0000001FFFE3F",
INIT_25 => X"FFFFF0000001FFFFFFFF00003FFFFFFFC001FFFFF03FFFFFFFFFFFFFFFFFFFFE",
INIT_15 => X"7FFFFFE0000000000001FFFFFFFFFFFFF0000000007FFCFFFE600FFFFFFFFFFF",
INIT_3A => X"FFFF83007F1FF00000007FFFFF8FFFFFFFFFFFFFFFFFFFFE7FFFFFE0001FFE00",
INIT_3B => X"0000FFFFFFDFFFFFFFFFFFFFFFFFFFFE7FFFFFC0003FF800FFFFFFFFFFFF03FF",
INIT_3C => X"FFFFFFFFFFFFFFFE7FFFFFC0007FE001FFFFFFFFFFFE07FFFFFF07807FFFF000",
INIT_3D => X"7FFFFF0000FFE007FFFFFFFFFFFC0FFFFFFF07C07FFFF0000000FFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFF81FFFFFFE0F807C7FF0000000FFFFFFFFFFFFFFFFFFFFFFFFFFFE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFE1F807C7FF00000007FFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFE0001FFE01F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"000007FFFFFFFFFFFFFFFFFFFFFFF9FE7FFFFC0001FFC0FFFFFFFFFFFFE01FFF",
INIT_01 => X"FFFFFFFFFFFFF1FE7FFFFC0001FF07FFFFFFFFFFFFC03FFFFFFC1FC07FFFF000",
INIT_02 => X"7FFFFC00C1FE0FFFFFFFFFFFFF807FFFFFFC1FC03FFFE080070047FFFFFFFFFF",
INIT_03 => X"FFFFFFFFFF00FFFFFFF81F803C7FC0980780E3FFFFFFFFFFFFFFFFFFFFFFF38E",
INIT_04 => X"FFF81FC0387F00380300F3FFFFFFFE7FFFFFFFFFFFFFFE067FFFFC03E1FF0FFF",
INIT_05 => X"000073FFFFFFF1FFFFFFFFFFFFFFF81E7FFFFF07E1FC3FFFFFFFFFFFFC01FFFF",
INIT_06 => X"FFFFFFFFFFFFF07E7FFFFFFFC1FDFFFFFFFFFFFFF003FFFFFFF03FC0103C007C",
INIT_07 => X"7FFFFFFFC1F3FFFFFFFFFFFFE007FFFFFFF07FCC0018007C000033FFFFFFFFFF",
INIT_08 => X"FFFFFFFFC00FFFFFFFE0FFC7001C007C00060200FCFFFFFFF8FFFFFFFFFFFBFE",
INIT_09 => X"FFE1FFDF001F80FC000F8400F03FFFFFF1FFFFFFFFFFFFFE7FFFFFFF8003FFFF",
INIT_0A => X"001F8001F83FFFFFF8FFFFFFFFFFFFFE7FFFFFFF0007FFFFFFFFFFFF801FFFFF",
INIT_0B => X"F8FFFFFFFFFFFFFE7FFFFFFF0003FFFFFFFFFFFF001FFFFFFFE3FFFF0003E0FC",
INIT_0C => X"7FFFFFFF0003FFFFFFFFFFFF003FFFFFFFC3FFFE000183FC003F000FFFFFFFFF",
INIT_0D => X"FF3FFFFE007FFFFFFFC3FFF0000083FC00FF003FFCFFFFFFF87FFFFFFFFFFFFE",
INIT_0E => X"FF87FFF0000187FC01FF703FFFFFFFFFF07FFFFFFFFFFFFE7FFFFFFF000FFFFF",
INIT_0F => X"01FFF87FFFFFFFFFF1FFFFFFFFFFFFFE7FFFFFFFFC1FFFFFFD7FFFFC007FFFFF",
INIT_10 => X"E3FFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFC7FFFF800FFFFFFFF87FFE00001CFFE",
INIT_11 => X"7FFFFFFFFFFFFFFFFEFFFFE001FFFFFFFF0FFFC00001CFFF01FFF87FFFFFFFFF",
INIT_12 => X"F97FFFC003FFFFFFFF0FFFC000019FFF01FFFE17FFFFFFFFC3FFFFFFFFFFFFFE",
INIT_13 => X"FF0FFFC000009FFF81FFFF00FFFFFFFF81FFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_14 => X"80FFFF80FFFFFFFC03FFFFFFFFFFFFFE7FFFFFFFFFFFFFFF81FFFF8003FFFFFF",
INIT_15 => X"01FFFFFFFFFFFFFE7FFFFFFFFFF8FFFC07FFF00007FFFFFFFF0FFFC000001FFF",
INIT_16 => X"7FFFFFFFFFC07FF807FFC0000FFFFFFFFE1FFFC000001FFF80FFFF80FFFFFFFF",
INIT_17 => X"07FFC0001FFFFFFFFE1FFF800007FFFF807FFFC07FFFFFFF13FFFFFFFFFFFFFE",
INIT_18 => X"FE3FFF00000FFFFF803FFFC07FFFFFFFBFFFFFFFFFFFFFFE7FFFFFFFFF803000",
INIT_19 => X"801FFFD01FFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFF0000001FFF80003FFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFE7FFFFFFFFFC000003FFF00007FFFFFFFFE3FFF80001FFFFF",
INIT_1B => X"7FFFFFFFFFF0F8007FFE0000FFFFFFFFFE7FFFC0001FFFFF800FFFF81FF7FFFF",
INIT_1C => X"7FFC0001FFFFFBFFFC7FFFC0061FFFFFC007FFFEFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_1D => X"F8FFFFC00E3FFFFFC007FFFFFFFDFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFF800",
INIT_1E => X"E007FFFFFFFF7FFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFE00FFF80001FFFFEFFF",
INIT_1F => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFC03FFF80003FFFFCFFFF8FFFFC00E3FFFFF",
INIT_20 => X"7FFFFFFFFFFFFC03FFF00007FFFE0FFFF9FFFFC00FFFFFFFE007FFFCFFFFFFFF",
INIT_21 => X"FFE0000FFFFF0FFFF1FFFFC00FFFFFFFF007FFFEFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_22 => X"F3FFFFE00FFFFFFFF007FFFE1FFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFC1F",
INIT_23 => X"F807FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFF81FFF80000FFFFE1FFF",
INIT_24 => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFF00001FFFFE3FFFE3FFFFE00FFFFFFF",
INIT_25 => X"7FFFFFFFFFFFFFFFFE00003FFFF83FFFE3FFFFF0EFFFFFFFF807FFFFFFFFFBFF",
INIT_26 => X"FE00007FFFF01FFFE7FFF3E1FFFFFFFFFC03FFFFFFFFFDFFFFFFFFFFFFFFFFFE",
INIT_27 => X"C7FFE003FFFFFFFFFC03FFFFFFFFFCFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_28 => X"FE01FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFC00007FFFE03FFF",
INIT_29 => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFF80000FFFFC03FFFC7FFC003C7FFFFFF",
INIT_2A => X"7FFFFFFFFFFFFF9FF80000FFFFC03FFF8FFFC00307FFEFFFFE01FFFFFFFFFFFF",
INIT_2B => X"FC0001FFFF807FFF8FFFC00107FFCFFFFF00FFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2C => X"0FFFE00007FFCFFFFF00FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_2D => X"FF80FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFC0003FFFF00FFFF",
INIT_2E => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFE000FFFFF00FFFF1FFFF00007FFC77F",
INIT_2F => X"7FFFFFFFFFFFFFFFFE000FFFFE00FFFE1FFFF0030FFFC0FFFF807FFFFFFFFFFF",
INIT_30 => X"FFFE0FFFFC05FFFE3FFFE0039FFFE1FFFFC03FFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_31 => X"3FFFE007FFFFE1FFFFE03FFFFFFBFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_32 => X"FFE00FFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFF5FFFFC05FFFE",
INIT_33 => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFF7FFFF803FFFC7FFFE01FBFFFE1FF",
INIT_34 => X"7FFFFFFFFFFFFFFFFFFE3FFFE003FFFC7FFFC07F9FFFE5FFFFE007FFFFFFFFFF",
INIT_35 => X"FFFF3FFFE403FFFCFFFF80FF9FFFE7FFFFE007FFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_36 => X"E7FF81FF92FFF7FFFEE007FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_37 => X"FE0003FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFF7FFFC00FFFF8",
INIT_38 => X"FFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFC037FFF8EFFF03FFD3FFFFFF",
INIT_39 => X"7FFFFFFFFFFFFFFFFFFFFFFFC427FFF87FFF07FFFAFFFFFFFF0003DFFFFFFFFF",
INIT_3A => X"FFFFFFFFE07FFFF07FFF0FFFFFFFFFFFFF8001FFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_3B => X"FFFF0FFFFFFFFFFFFFC000FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFF",
INIT_3C => X"FFE000FFFFFFFFFFFFFFFFFFFFFEFFFE7FFFFFFFFFFFFFFFFFFBFFFFF8FFFFF0",
INIT_3D => X"FFFFFFFFFFFC9BFE7FFFFFFFFFFFFFFFFFFBFFFFBFFFFFF1FFFF0FFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFFFFFFFFFFFFFFFF1FFFFFE1FFFF1FFFFFFFFFFFFFF000FFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFFFFFF07FFFFC3FFFFBFFFFFFFFFFFFFF000FFFFFFFFFFFFFFFFFFFFFF81FE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena131 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_6(13),
I1 => addra_6(14),
I2 => addra_6(16),
I3 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N18,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52,
O => douta_7(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N18
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N16,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53,
O => douta_7(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N16
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N14,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54,
O => douta_7(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N14
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N12,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55,
O => douta_7(5)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_1 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_11 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(1)
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq00001 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(12),
I1 => addra_6(13),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq000011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(14),
I1 => addra_6(16),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_221 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
I1 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
O => BU2_U0_blk_mem_generator_valid_cstr_N13
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena1 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena01 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(14),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena11 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena121 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(16),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_3 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(15),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_2 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(14),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_1 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(13),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_0 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(12),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_4 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N12,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N11,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_75 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
O => BU2_U0_blk_mem_generator_valid_cstr_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_65 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
O => BU2_U0_blk_mem_generator_valid_cstr_N11
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_3 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N10,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N9,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_74 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
O => BU2_U0_blk_mem_generator_valid_cstr_N10
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_64 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
O => BU2_U0_blk_mem_generator_valid_cstr_N9
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_2 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N7,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_73 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
O => BU2_U0_blk_mem_generator_valid_cstr_N8
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_63 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
O => BU2_U0_blk_mem_generator_valid_cstr_N7
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_1 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N6,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N5,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_72 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
O => BU2_U0_blk_mem_generator_valid_cstr_N6
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_62 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
O => BU2_U0_blk_mem_generator_valid_cstr_N5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_0 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N4,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N3,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_71 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
O => BU2_U0_blk_mem_generator_valid_cstr_N4
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_61 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
O => BU2_U0_blk_mem_generator_valid_cstr_N3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N2,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N1,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_7 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
O => BU2_U0_blk_mem_generator_valid_cstr_N2
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_6 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
O => BU2_U0_blk_mem_generator_valid_cstr_N1
);
BU2_XST_VCC : VCC
port map (
P => BU2_N1
);
BU2_XST_GND : GND
port map (
G => BU2_doutb(0)
);
end STRUCTURE;
-- synopsys translate_on
| gpl-2.0 | fb118a118c715316bb2ffb0e620aa6a8 | 0.73687 | 2.504241 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/video/video.vhd | 2 | 8,507 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
VGA_CLK : in std_logic;
RESET : in std_logic;
BORDERCOLOR : in std_logic_vector(2 downto 0);
INT : out std_logic;
VA : out std_logic_vector(12 downto 0);
VD : in std_logic_vector(7 downto 0);
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end video;
architecture BEHAVIORAL of video is
constant HSCREENSIZE : integer := 640; -- Hor. visible area (border) size
constant VSCREENSIZE : integer := 480; -- Vert. visible area (border) size
constant HPAPERSIZE : integer := 512; -- Hor. paper area size
constant VPAPERSIZE : integer := 384; -- Vert. paper area size
constant RIGHTBORDERSIZE : integer := 64;
constant BOTTOMBORDERSIZE : integer := 48;
constant HBACKPORCH : integer := 48;
constant HSYNCLENGTH : integer := 96;
constant HFRONTPORCH : integer := 16;
constant VBACKPORCH : integer := 33;
constant VSYNCLENGTH : integer := 2;
constant VFRONTPORCH : integer := 10;
constant HPIXELSIZE : integer := 2;
constant VPIXELSIZE : integer := 2;
signal HCOUNTER : unsigned(9 downto 0); -- Main hor. counter
signal VCOUNTER : unsigned(9 downto 0); -- Main vert. counter
signal HPSCOUNTER : unsigned(1 downto 0); -- Hor. pixel size counter
signal VPSCOUNTER : unsigned(1 downto 0); -- Vert. pixel size counter
signal HPIXELCOUNTER : unsigned(7 downto 0);
signal VPIXELCOUNTER : unsigned(7 downto 0);
signal PIX : std_logic_vector(7 downto 0); -- Pixel data
signal ATTR : std_logic_vector(7 downto 0); -- Attribute data
signal PAPER : std_logic; -- Paper area
signal BORDER : std_logic; -- Visible area (border)
signal LPIX : std_logic_vector(7 downto 0);
signal LATTR : std_logic_vector(7 downto 0);
signal LPAPER : std_logic;
signal LBORDER : std_logic;
signal FLASHCOUNTER : unsigned(6 downto 0);
signal FLASH : std_logic;
signal INTCOUNTER : unsigned(9 downto 0);
begin
main_counter : process (VGA_CLK, RESET)
begin
if RESET = '1' then
HCOUNTER <= (others => '0');
VCOUNTER <= (others => '0');
HPSCOUNTER <= (others => '0');
VPSCOUNTER <= (others => '0');
HPIXELCOUNTER <= (others => '0');
VPIXELCOUNTER <= (others => '0');
FLASHCOUNTER <= (others => '0');
INTCOUNTER <= (others => '0');
INT <= '1';
elsif rising_edge(VGA_CLK) then
INT <= '1';
if INTCOUNTER = 1 and HCOUNTER < 256 then
INT <= '0';
end if;
if HCOUNTER < HSCREENSIZE + HBACKPORCH + HSYNCLENGTH + HFRONTPORCH - 1 then
HCOUNTER <= HCOUNTER + 1;
HPSCOUNTER <= HPSCOUNTER + 1;
if (HPSCOUNTER = HPIXELSIZE - 1) then
HPSCOUNTER <= (others => '0');
HPIXELCOUNTER <= HPIXELCOUNTER + 1;
end if;
else
HCOUNTER <= (others => '0');
HPSCOUNTER <= (others => '0');
HPIXELCOUNTER <= (others => '0');
INTCOUNTER <= INTCOUNTER + 1;
if INTCOUNTER = 628 then
INTCOUNTER <= (others => '0');
end if;
if VCOUNTER < VSCREENSIZE + VBACKPORCH + VSYNCLENGTH + VFRONTPORCH - 1 then
VCOUNTER <= VCOUNTER + 1;
VPSCOUNTER <= VPSCOUNTER + 1;
if (VPSCOUNTER = VPIXELSIZE - 1) then
VPSCOUNTER <= (others => '0');
VPIXELCOUNTER <= VPIXELCOUNTER + 1;
end if;
else
VCOUNTER <= (others => '0');
VPSCOUNTER <= (others => '0');
VPIXELCOUNTER <= (others => '0');
FLASHCOUNTER <= FLASHCOUNTER + 1;
end if;
end if;
end if;
end process;
FLASH <= std_logic(FLASHCOUNTER(6));
make_sync : process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
VGA_HSYNC <= '1';
VGA_VSYNC <= '1';
if HCOUNTER > HPAPERSIZE + RIGHTBORDERSIZE + HBACKPORCH - 1
and HCOUNTER < HPAPERSIZE + RIGHTBORDERSIZE + HBACKPORCH + HSYNCLENGTH then
VGA_HSYNC <= '0';
end if;
if VCOUNTER > VPAPERSIZE + BOTTOMBORDERSIZE + VBACKPORCH - 1
and VCOUNTER < VPAPERSIZE + BOTTOMBORDERSIZE + VBACKPORCH + VSYNCLENGTH then
VGA_VSYNC <= '0';
end if;
end if;
end process;
make_paper : process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
PAPER <= '0';
if HCOUNTER < HPAPERSIZE - 1 and VCOUNTER < VPAPERSIZE then
PAPER <= '1';
end if;
end if;
end process;
make_border : process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
BORDER <= '1';
if (HCOUNTER > HPAPERSIZE + RIGHTBORDERSIZE - 1
and HCOUNTER < HPAPERSIZE + RIGHTBORDERSIZE + HBACKPORCH + HSYNCLENGTH + HFRONTPORCH)
or (VCOUNTER > VPAPERSIZE + BOTTOMBORDERSIZE - 1
and VCOUNTER < VPAPERSIZE + BOTTOMBORDERSIZE + VBACKPORCH + VSYNCLENGTH + VFRONTPORCH) then
BORDER <= '0';
end if;
if HCOUNTER > HPAPERSIZE + RIGHTBORDERSIZE + HBACKPORCH + HSYNCLENGTH + HFRONTPORCH - 1 then
if VCOUNTER = 431 then
BORDER <= '0';
elsif VCOUNTER = 476 then
BORDER <= '1';
end if;
end if;
end if;
end process;
latch_data : process (VGA_CLK)
begin
if rising_edge(VGA_CLK) and HPSCOUNTER = HPIXELSIZE - 1 then
case HPIXELCOUNTER(2 downto 0) is
when "001" => VA <= std_logic_vector(VPIXELCOUNTER(7 downto 6)) & std_logic_vector(VPIXELCOUNTER(2 downto 0)) &
std_logic_vector(VPIXELCOUNTER(5 downto 3)) & std_logic_vector(HPIXELCOUNTER(7 downto 3));
when "011" => PIX <= VD;
when "100" => VA <= "110" & std_logic_vector(VPIXELCOUNTER(7 downto 3)) & std_logic_vector(HPIXELCOUNTER(7 downto 3));
when "110" => ATTR <= VD;
when "111" => LPIX <= PIX;
LATTR <= ATTR;
LPAPER <= PAPER;
LBORDER <= BORDER;
when others => null;
end case;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if LPAPER = '1' then
if (LPIX(7 - to_integer(HPIXELCOUNTER(2 downto 0))) xor (FLASH and LATTR(7))) = '1' then
VGA_G(0) <= LATTR (2);
VGA_G(1) <= LATTR (2);
VGA_G(2) <= LATTR (2) and LATTR(6);
VGA_G(3) <= LATTR (2);
VGA_R(0) <= LATTR (1);
VGA_R(1) <= LATTR (1);
VGA_R(2) <= LATTR (1) and LATTR(6);
VGA_R(3) <= LATTR (1);
VGA_B(0) <= LATTR (0);
VGA_B(1) <= LATTR (0);
VGA_B(2) <= LATTR (0) and LATTR(6);
VGA_B(3) <= LATTR (0);
else
VGA_G(0) <= LATTR (5);
VGA_G(1) <= LATTR (5);
VGA_G(2) <= LATTR (5) and LATTR(6);
VGA_G(3) <= LATTR (5);
VGA_R(0) <= LATTR (4);
VGA_R(1) <= LATTR (4);
VGA_R(2) <= LATTR (4) and LATTR(6);
VGA_R(3) <= LATTR (4);
VGA_B(0) <= LATTR (3);
VGA_B(1) <= LATTR (3);
VGA_B(2) <= LATTR (3) and LATTR(6);
VGA_B(3) <= LATTR (3);
end if;
elsif LBORDER = '1' then
VGA_G(0) <= BORDERCOLOR (2);
VGA_G(1) <= BORDERCOLOR (2);
VGA_G(2) <= '0';
VGA_G(3) <= BORDERCOLOR (2);
VGA_R(0) <= BORDERCOLOR (1);
VGA_R(1) <= BORDERCOLOR (1);
VGA_R(2) <= '0';
VGA_R(3) <= BORDERCOLOR (1);
VGA_B(0) <= BORDERCOLOR (0);
VGA_B(1) <= BORDERCOLOR (0);
VGA_B(2) <= '0';
VGA_B(3) <= BORDERCOLOR (0);
else
VGA_G <= "0000";
VGA_R <= "0000";
VGA_B <= "0000";
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 36dd600a3db0a7d1ee1e73348588bf64 | 0.507464 | 3.557926 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_01600_bad.vhd | 1 | 3,951 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01600_bad.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Entity port sort: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity STD_01600_bad is
-- We sort port by name
port (
i_A1 : in std_logic; -- First Mux, first input
i_A2 : in std_logic; -- Second Mux, first input
i_B1 : in std_logic; -- First Mux, second input
i_B2 : in std_logic; -- Second Mux, second input
i_Sel1 : in std_logic; -- First Mux, selector input
i_Sel2 : in std_logic; -- Second Mux, selector input
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
o_Q1 : out std_logic; -- First module output
o_Q2 : out std_logic -- Second module output
);
end STD_01600_bad;
--CODE
architecture Behavioral of STD_01600_bad is
signal Q1 : std_logic; -- First module output
signal Q2 : std_logic; -- Second module output
signal OutMux1 : std_logic; -- First Mux output
signal OutMux2 : std_logic; -- Second Mux output
begin
-- First Mux, output to be synced
Mux1 : Mux
port map (
i_A => i_A1,
i_B => i_B1,
i_S => i_Sel1,
o_O => OutMux1
);
-- Second Mux, output to be synced
Mux2 : Mux
port map (
i_A => i_A2,
i_B => i_B2,
i_S => i_Sel2,
o_O => OutMux2
);
-- Synchronizes the Mux outputs
P_SyncMux : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Q1 <= '0';
Q2 <= '0';
else
if (rising_edge(i_Clock)) then
Q1 <= OutMux1;
Q2 <= OutMux2;
end if;
end if;
end process;
o_Q1 <= Q1;
o_Q2 <= Q2;
end Behavioral;
--CODE
| gpl-3.0 | c8f32e2c3a4b88775713b9ccdbbd2ea8 | 0.473298 | 4.154574 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/alf/src/clock/clock.vhd | 1 | 6,674 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____56.000______0.000______50.0______557.143____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 28,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
| gpl-3.0 | 552d25c51fad3415f4a04059e518baaa | 0.551993 | 4.240152 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/BINARYZACJA/simulation/BINARYZACJA_tb.vhd | 4 | 4,237 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: BINARYZACJA_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_tb IS
END ENTITY;
ARCHITECTURE BINARYZACJA_tb_ARCH OF BINARYZACJA_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
BINARYZACJA_tb_synth_inst:ENTITY work.BINARYZACJA_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | 493dcb7431f146beec54d3f87eebc92c | 0.626151 | 4.661166 | false | false | false | false |
sonologic/gmzpu | vhdl/helpers/zpu_small1.vhdl | 1 | 7,232 | ------------------------------------------------------------------------------
---- ----
---- ZPU Small + PHI I/O + BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
---- small version, the PHI I/O basic layout and a program BRAM. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPU_Small1(Structural) (Entity and architecture) ----
---- File name: zpu_small1.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
-- RAM declaration
library work;
use work.zpu_memory.all;
entity ZPU_Small1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='0'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=115200; -- RS232 baudrate
ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end entity ZPU_Small1;
architecture Structural of ZPU_Small1 is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
-- Program+data+stack BRAM
-- Port A
signal a_we : std_logic;
signal a_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
signal a_write : unsigned(WORD_SIZE-1 downto 0);
signal a_read : unsigned(WORD_SIZE-1 downto 0);
-- Port B
signal b_we : std_logic;
signal b_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
signal b_write : unsigned(WORD_SIZE-1 downto 0);
signal b_read : unsigned(WORD_SIZE-1 downto 0);
-- I/O space
signal io_busy : std_logic;
signal io_write : unsigned(WORD_SIZE-1 downto 0);
signal io_read : unsigned(WORD_SIZE-1 downto 0);
signal io_addr : unsigned(ADDR_W-1 downto 0);
signal phi_addr : unsigned(2 downto 0);
signal io_we : std_logic;
signal io_re : std_logic;
begin
memory: DualPortRAM
generic map(
WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
port map(
clk_i => clk_i,
-- Port A
a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write,
a_read_o => a_read,
-- Port B
b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write,
b_read_o => b_read);
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
BRDIVISOR => BRDIVISOR,
LOG_FILE => "zpu_small1_io.log"
)
port map(
clk_i => clk_i,
reset_i => rst_i,
busy_o => io_busy,
we_i => io_we,
re_i => io_re,
data_i => io_write,
data_o => io_read,
addr_i => phi_addr,
rs232_rx_i => rs232_rx_i,
rs232_tx_o => rs232_tx_o,
br_clk_i => '1',
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir
);
phi_addr <= io_addr(4 downto 2);
zpu : ZPUSmallCore
generic map(
WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
D_CARE_VAL => D_CARE_VAL)
port map(
clk_i => clk_i, reset_i => rst_i, interrupt_i => '0',
break_o => break_o, dbg_o => dbg_o,
-- BRAM (text, data, bss and stack)
a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read,
b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read,
-- Memory mapped I/O
mem_busy_i => io_busy, data_i => io_read, data_o => io_write,
addr_o => io_addr, write_en_o => io_we, read_en_o => io_re);
end architecture Structural; -- Entity: ZPU_Small1
| bsd-3-clause | 9af3c6a8fd26f6e3731157aac3a2175c | 0.376244 | 4.17311 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/pic/i8259.vhd | 1 | 4,654 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i8259 is
port (
CLK : in std_logic;
RESET : in std_logic;
A0 : in std_logic;
WR : in std_logic;
INTA : in std_logic;
INTR : out std_logic;
IRQ : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0) );
end i8259;
architecture rtl of i8259 is
signal IRR : std_logic_vector(7 downto 0);
signal IRQ_LAST : std_logic_vector(7 downto 0);
signal IMR : std_logic_vector(7 downto 0);
signal ISR : std_logic_vector(7 downto 0);
signal ICW1 : std_logic_vector(7 downto 0);
signal ICW2 : std_logic_vector(7 downto 0);
signal STATE : unsigned(1 downto 0);
signal IRQ_WORK : std_logic_vector(2 downto 0);
signal INIT : std_logic;
signal EXINTA : std_logic;
signal EXWR : std_logic;
alias INTERVAL : std_logic is ICW1(2);
alias ADDRH : std_logic_vector(7 downto 0) is ICW2;
alias ADDRL : std_logic_vector(2 downto 0) is ICW1(7 downto 5);
begin
INTR <= '1' when ISR /= "00000000" or IRR /= "00000000" else '0';
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
IMR <= "11111111";
ISR <= "00000000";
IRR <= "00000000";
IRQ_WORK <= "000";
IRQ_LAST <= "00000000";
DO <= "00000000";
INIT <= '0';
STATE <= "00";
EXINTA <= '0';
EXWR <= '0';
else
EXINTA <= INTA;
EXWR <= WR;
-- write to PIC registers
if WR = '1' and EXWR = '0' then
if INIT = '1' then -- Write to ICW2
ICW2 <= DI;
INIT <= '0';
else
if A0 = '1' then -- Write to OCW1
IMR <= DI;
elsif DI(4) = '1' then -- Write to ICW1 (Reset and Init PIC)
IMR <= "11111111";
ISR <= "00000000";
IRR <= "00000000";
ICW1 <= DI;
INIT <= '1';
end if;
end if;
end if;
-- Write new interrupts to IRR ---------------------
IRQ_LAST <= IRQ;
for POS in 0 to 7 loop
-- if IRQ_LAST(POS) = '0' and IRQ(POS) = '1' and IMR(POS) = '0' then ################# ISR CHECK TOO?????????????
if IRQ_LAST(POS) = '0' and IRQ(POS) = '1' and IMR(POS) = '0' and ISR(POS) = '0' then
IRR(POS) <= '1';
end if;
end loop;
-- Check for interrupts in IRR, clear IRR and set ISR/IRQ_WORK (current interrupt number)
if ISR = "00000000" then
if IRR(0) = '1' then IRQ_WORK <= "000"; IRR(0) <= '0'; ISR(0) <= '1';
elsif IRR(1) = '1' then IRQ_WORK <= "001"; IRR(1) <= '0'; ISR(1) <= '1';
elsif IRR(2) = '1' then IRQ_WORK <= "010"; IRR(2) <= '0'; ISR(2) <= '1';
elsif IRR(3) = '1' then IRQ_WORK <= "011"; IRR(3) <= '0'; ISR(3) <= '1';
elsif IRR(4) = '1' then IRQ_WORK <= "100"; IRR(4) <= '0'; ISR(4) <= '1';
elsif IRR(5) = '1' then IRQ_WORK <= "101"; IRR(5) <= '0'; ISR(5) <= '1';
elsif IRR(6) = '1' then IRQ_WORK <= "110"; IRR(6) <= '0'; ISR(6) <= '1';
elsif IRR(7) = '1' then IRQ_WORK <= "111"; IRR(7) <= '0'; ISR(7) <= '1';
end if;
end if;
-- State machine for interrupt acknowledge
if INTA = '1' and EXINTA = '0' then
case STATE is
when "00" =>
DO <= "11001101";
STATE <= "01";
when "01" =>
if INTERVAL = '0' then -- 8
DO <= ADDRL(2 downto 1) & IRQ_WORK & "000";
else -- 4
DO <= ADDRL(2 downto 0) & IRQ_WORK & "00";
end if;
STATE <= "10";
when "10" =>
DO <= ADDRH;
ISR <= "00000000";
STATE <= "00";
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 812da17190dc93bd19f558cb130706d2 | 0.40202 | 3.664567 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/control.vhd | 1 | 16,546 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+5+2+3+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
-- c_source := C_FROM_REG_SOURCE_EQZ;
when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
-- c_source := FROM_REG_SOURCE_NEZ;
when "001100" => --SYSCALL
-- if(r[4]==0) printf("0x%8.8lx ",r[5]);
when "001101" => --BREAK s->wakeup=1;
when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --FTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "110001" => --TGEU
when "110010" => --TLT
when "110011" => --TLTU
when "110100" => --TEQ
when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_LTZ;
when "00010" => --BLTZL lbranch=r[rs]<0;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_LTZ;
when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_GEZ;
when "00011" => --BGEZL lbranch=r[rs]>=0;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_GEZ;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
when "010001" => --COP1
when "010010" => --COP2
when "010011" => --COP3
when "010100" => --BEQL lbranch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_EQ;
when "010101" => --BNEL lbranch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_NE;
when "010110" => --BLEZL lbranch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_LEZ;
when "010111" => --BGTZL lbranch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_LBRANCH;
branch_function := BRANCH_GTZ;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101110" => --SWR //Not Implemented
when "101111" => --CACHE
when "110000" => --LL r[rt]=*(long*)ptr;
when "110001" => --LWC1
when "110010" => --LWC2
when "110011" => --LWC3
when "110101" => --LDC1
when "110110" => --LDC2
when "110111" => --LDC3
when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
when "111001" => --SWC1
when "111010" => --SWC2
when "111011" => --SWC3
when "111101" => --SDC1
when "111110" => --SDC2
when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH;
mem_source := MEM_FETCH;
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
| gpl-3.0 | d446b456a33eef817eb005599c261a60 | 0.529735 | 3.108398 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/simulation/bmg_stim_gen.vhd | 1 | 12,323 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (4095 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"fontrom.mif",
DEFAULT_DATA,
8,
4096);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
ADDRA <= READ_ADDR_INT AFTER 50 ns;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| gpl-3.0 | 48ddd9ececbd002f0a75003bb0f61c6a | 0.550434 | 3.689521 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_ddiv_29_no_dsp_64/synth/sin_taylor_series_ap_ddiv_29_no_dsp_64.vhd | 4 | 12,846 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64;
ARCHITECTURE sin_taylor_series_ap_ddiv_29_no_dsp_64_arch OF sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_ddiv_29_no_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_ddiv_29_no_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FM" &
"S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64_arch;
| mit | e4846faefc491970189b567b8e5801dd | 0.651331 | 3.003507 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_ddiv_29_no_dsp_64.vhd | 6 | 10,825 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64;
ARCHITECTURE sin_taylor_series_ap_ddiv_29_no_dsp_64_arch OF sin_taylor_series_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_ddiv_29_no_dsp_64_arch;
| mit | 521ab1b51169024beaa8f0a763327d75 | 0.632425 | 3.203611 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/sin_taylor_series.autotb.vhd | 2 | 35,033 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_sin_taylor_series_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_x : STRING := "../tv/cdatafile/c.sin_taylor_series.autotvin_x.dat";
AUTOTB_TVIN_x_out_wrapc : STRING := "../tv/rtldatafile/rtl.sin_taylor_series.autotvin_x.dat";
AUTOTB_TVOUT_ap_return : STRING := "../tv/cdatafile/c.sin_taylor_series.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "../tv/rtldatafile/rtl.sin_taylor_series.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "sin_taylor_series.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "sin_taylor_series.performance.result.transaction.xml";
LENGTH_x : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 19
);
end apatb_sin_taylor_series_top;
architecture behav of apatb_sin_taylor_series_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal x : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal ap_clk : STD_LOGIC;
signal ap_rst : STD_LOGIC;
signal ap_return : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal ap_done : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC);
end component;
-- The signal of port x
shared variable AESL_REG_x : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
begin
AESL_inst_sin_taylor_series : sin_taylor_series port map (
x => x,
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_return => ap_return,
ap_done => ap_done,
ap_start => ap_start,
ap_ready => ap_ready,
ap_idle => ap_idle
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst <= AESL_reset;
AESL_reset <= rst;
AESL_done <= ap_done;
ap_start <= AESL_start;
AESL_start <= start;
AESL_ready <= ap_ready;
AESL_idle <= ap_idle;
AESL_ce <= ce;
AESL_continue <= continue;
gen_check_strlSignal_AESL_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
NULL;
else
if ( AESL_done /= '1' and AESL_done /= '0' ) then
assert false report "Control signal AESL_done is invalid!" severity failure;
end if;
end if;
end if;
end process;
gen_check_strlSignal_AESL_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
NULL;
else
if ( AESL_ready /= '1' and AESL_ready /= '0' ) then
assert false report "Control signal AESL_ready is invalid!" severity failure;
end if;
end if;
end if;
end process;
gen_assign_x_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
x <= AESL_REG_x;
end process;
read_file_process_x : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 152);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable transaction_idx : INTEGER:= 0;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_x, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_x & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_x := esl_str2lv_hex(token, 64 );
esl_read_token(fp, token_line, token);
end if;
wait until AESL_clock'event and AESL_clock = '1';
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
write_file_process_ap_return : process
file fp : TEXT;
file fp_size : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 152);
variable str : STRING(1 to 40);
variable transaction_idx : INTEGER;
variable ap_return_count : INTEGER;
variable hls_stream_size : INTEGER;
variable i : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
transaction_idx := 0;
while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(ap_return));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '1') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '1';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '0';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '0';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '1') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
elsif (reported_stuck = '0' and reported_stuck_cnt < 4) then
if ( AESL_mLatCnterIn_addr > AESL_mLatCnterOut_addr ) then
if ( AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10000 and AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10 * 1156 ) then
report "WARNING: The latency is much larger than expected. Simulation may stuck.";
reported_stuck <= '1';
reported_stuck_cnt := reported_stuck_cnt + 1;
end if;
end if;
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
elsif (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '0');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
| mit | c54763f19bebf4070ae7d222a90aa076 | 0.509891 | 3.705235 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/example_design/bmg_wrapper.vhd | 1 | 9,881 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : fontrom.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT fontrom_top IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : fontrom_top
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 51d4abd7d35d08123cfc7f45bea82352 | 0.494687 | 3.83133 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/atari.vhd | 1 | 15,043 | ---------------------------------------------------------------------------
-- Atari800-Core wrapper
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
-- New Files:
-- DAC.VHD - Delta-Sigma-DAC from Xilinx Appnotes
-- NES-GAMEPAD.VHD - NES-Gamepad controller
-- SRAM-STATEMACHINE.VHD - SRAM (2 x 256KB x 16bit) Controller
-- Changed Files:
-- PS2_TO_ATARI800.VHD - Added PS2_KEYS Output
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ATARI is
port (
CLK_50 : in std_logic;
MCU_READY : in std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
KB_CLK : in std_logic;
KB_DAT : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end ATARI;
architecture rtl of ATARI is
signal CLK : std_logic;
signal LOCKED : std_logic;
signal RESET_N : std_logic;
-- Pokey Keyboard
signal KEYBOARD_SCAN : std_logic_vector(5 downto 0);
signal KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
-- GTIA Consol Keys
signal CONSOL_START : std_logic;
signal CONSOL_SELECT : std_logic;
signal CONSOL_OPTION : std_logic;
signal FKEYS : std_logic_vector(11 downto 0);
signal PS2_KEYS : std_logic_vector(511 downto 0);
-- Gamepads
signal GAMEPAD0 : std_logic_vector(7 downto 0);
signal GAMEPAD1 : std_logic_vector(7 downto 0);
signal JOY1_n : std_logic_vector(4 downto 0);
signal JOY2_n : std_logic_vector(4 downto 0);
-- Video
signal VIDEO_R : std_logic_vector(7 downto 0);
signal VIDEO_G : std_logic_vector(7 downto 0);
signal VIDEO_B : std_logic_vector(7 downto 0);
signal VIDEO_VS : std_logic;
signal VIDEO_HS : std_logic;
signal PAL : std_logic := '0';
signal VGA : std_logic := '1';
signal SCANLINES : std_logic := '0';
-- Scandoubler
signal SCANDOUBLE_CLK : std_logic;
signal HALF_SCANDOUBLE_ENABLE_REG : std_logic;
signal HALF_SCANDOUBLE_ENABLE_NEXT : std_logic;
-- Audio
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
-- SDRAM (SRAM)
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : std_logic_vector(22 DOWNTO 0);
signal SDRAM_DO : std_logic_vector(31 DOWNTO 0);
signal SDRAM_DI : std_logic_vector(31 DOWNTO 0);
signal SDRAM_WIDTH_8BIT_ACCESS : std_logic;
signal SDRAM_WIDTH_16BIT_ACCESS : std_logic;
signal SDRAM_WIDTH_32BIT_ACCESS : std_logic;
-- DMA/Virtual Drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
-- System Control from ZPU
signal ZPU_POKEY_ENABLE : std_logic;
signal ZPU_SIO_TXD : std_logic;
signal ZPU_SIO_RXD : std_logic;
signal ZPU_SIO_COMMAND : std_logic;
alias PAUSE_ATARI : std_logic is ZPU_OUT1(0);
alias RESET_ATARI : std_logic is ZPU_OUT1(1);
alias SPEED_6502 : std_logic_vector(5 downto 0) is ZPU_OUT1(7 downto 2);
alias RAM_SELECT : std_logic_vector(2 downto 0) is ZPU_OUT1(10 downto 8);
alias ROM_SELECT : std_logic_vector(5 downto 0) is ZPU_OUT1(16 downto 11);
begin
u_PLL : entity work.PLL
port map (
CLKIN => CLK_50,
CLKOUT => CLK,
CLKOUT2 => SCANDOUBLE_CLK,
LOCKED => LOCKED );
u_DAC_L : entity work.dac
port map (
CLK_I => CLK,
RES_N_I => RESET_N,
DAC_I => AUDIO_L_PCM,
DAC_O => SOUND_L );
u_DAC_R : entity work.dac
port map (
CLK_I => CLK,
RES_N_I => RESET_N,
DAC_I => AUDIO_R_PCM,
DAC_O => SOUND_R );
u_KEYBOARD : entity work.ps2_to_atari800
port map(
CLK => CLK,
RESET_N => RESET_N,
PS2_CLK => KB_CLK,
PS2_DAT => KB_DAT,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
FKEYS => FKEYS,
PS2_KEYS => PS2_KEYS );
u_JOYSTICKS : entity work.nes_gamepad
port map(
CLK => CLK,
RESET => not RESET_N,
JOY_CLK => JOY_CLK,
JOY_LOAD => JOY_LOAD,
JOY_DATA0 => JOY_DATA0,
JOY_DATA1 => JOY_DATA1,
JOY0_BUTTONS => GAMEPAD0,
JOY1_BUTTONS => GAMEPAD1,
JOY0_CONNECTED => OPEN,
JOY1_CONNECTED => OPEN );
u_ATARI800_CORE : entity work.atari800core_simple_sdram
generic map(
CYCLE_LENGTH => 16,
INTERNAL_ROM => 0,
INTERNAL_RAM => 0,
PALETTE => 0,
VIDEO_BITS => 8 )
port map(
CLK => CLK,
RESET_N => RESET_N and not (RESET_ATARI),
VIDEO_VS => VIDEO_VS,
VIDEO_HS => VIDEO_HS,
VIDEO_B => VIDEO_B,
VIDEO_G => VIDEO_G,
VIDEO_R => VIDEO_R,
VIDEO_BLANK => OPEN,
VIDEO_BURST => OPEN,
VIDEO_START_OF_FIELD => OPEN,
VIDEO_ODD_LINE => OPEN,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
JOY1_n => JOY1_n,
JOY2_n => JOY2_n,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
SIO_COMMAND => ZPU_SIO_COMMAND,
SIO_RXD => ZPU_SIO_TXD,
SIO_TXD => ZPU_SIO_RXD,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => OPEN,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
SDRAM_DI => SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32BIT_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16BIT_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8BIT_ACCESS,
SDRAM_REFRESH => OPEN,
DMA_FETCH => DMA_FETCH,
DMA_READ_ENABLE => DMA_READ_ENABLE,
DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
DMA_ADDR => DMA_ADDR_FETCH,
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_DMA => DMA_MEMORY_READY,
DMA_MEMORY_DATA => DMA_MEMORY_DATA,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
PAL => PAL,
HALT => PAUSE_ATARI,
THROTTLE_COUNT_6502 => SPEED_6502 );
u_SRAM : entity work.sram_statemachine
port map (
CLK => CLK,
RESET_N => RESET_N and not (RESET_ATARI),
ADDRESS_IN => SDRAM_ADDR,
DATA_IN => SDRAM_DI,
DATA_OUT => SDRAM_DO,
WRITE_EN => SDRAM_WRITE_ENABLE,
REQUEST => SDRAM_REQUEST,
BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
COMPLETE => SDRAM_REQUEST_COMPLETE,
SRAM_ADDR => SRAM_A,
SRAM_DQ => SRAM_D,
SRAM_CE0_N => SRAM_CE0,
SRAM_CE1_N => SRAM_CE1,
SRAM_OE_N => SRAM_OE,
SRAM_WE_N => SRAM_WE,
SRAM_UB_N => SRAM_UB,
SRAM_LB_N => SRAM_LB );
u_ZPU : entity work.zpucore
generic map (
PLATFORM => 1,
SPI_CLOCK_DIV => 1 )
port map (
CLK => CLK,
RESET_N => RESET_N,
ZPU_ADDR_FETCH => DMA_ADDR_FETCH,
ZPU_DATA_OUT => DMA_WRITE_DATA,
ZPU_FETCH => DMA_FETCH,
ZPU_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
ZPU_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
ZPU_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
ZPU_READ_ENABLE => DMA_READ_ENABLE,
ZPU_MEMORY_READY => DMA_MEMORY_READY,
ZPU_MEMORY_DATA => DMA_MEMORY_DATA,
ZPU_ADDR_ROM => ZPU_ADDR_ROM,
ZPU_ROM_DATA => ZPU_ROM_DATA,
ZPU_SD_DAT0 => SD_MISO,
ZPU_SD_CLK => SD_SCK,
ZPU_SD_CMD => SD_MOSI,
ZPU_SD_DAT3 => SD_CS,
ZPU_POKEY_ENABLE => ZPU_POKEY_ENABLE,
ZPU_SIO_TXD => ZPU_SIO_TXD,
ZPU_SIO_RXD => ZPU_SIO_RXD,
ZPU_SIO_COMMAND => ZPU_SIO_COMMAND,
ZPU_IN1 => X"00000" & FKEYS,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"00000000",
ZPU_OUT1 => ZPU_OUT1,
ZPU_OUT2 => OPEN,
ZPU_OUT3 => OPEN,
ZPU_OUT4 => OPEN );
u_ZPUROM : entity work.zpu_rom
port map (
CLOCK => CLK,
ADDRESS => ZPU_ADDR_ROM(13 downto 2),
Q => ZPU_ROM_DATA );
u_ZPUPOKEY : entity work.enable_divider
generic map (
COUNT => 16 )
port map (
CLK => CLK,
RESET_N => RESET_N,
ENABLE_IN => '1',
ENABLE_OUT => ZPU_POKEY_ENABLE);
-- Scandoubler
process(SCANDOUBLE_CLK, RESET_N, RESET_ATARI)
begin
if ((RESET_N and not (RESET_ATARI)) = '0') then
HALF_SCANDOUBLE_ENABLE_REG <= '0';
elsif (SCANDOUBLE_CLK'event and SCANDOUBLE_CLK = '1') then
HALF_SCANDOUBLE_ENABLE_REG <= HALF_SCANDOUBLE_ENABLE_NEXT;
end if;
end process;
HALF_SCANDOUBLE_ENABLE_NEXT <= not(HALF_SCANDOUBLE_ENABLE_REG);
u_SCANDOUBLER : entity work.scandoubler
port map (
CLK => SCANDOUBLE_CLK,
RESET_N => RESET_N and not (RESET_ATARI),
VGA => VGA,
COMPOSITE_ON_HSYNC => not VGA,
COLOUR_ENABLE => HALF_SCANDOUBLE_ENABLE_REG,
DOUBLED_ENABLE => VGA,
SCANLINES_ON => SCANLINES,
COLOUR_IN => VIDEO_B,
VSYNC_IN => VIDEO_VS,
HSYNC_IN => VIDEO_HS,
R => VGA_R,
G => VGA_G,
B => VGA_B,
VSYNC => VGA_VSYNC,
HSYNC => VGA_HSYNC );
RESET_N <= LOCKED and MCU_READY;
-- NES Gamepad 1 & Cursor keys on keyboard
JOY1_n <= (not GAMEPAD0(7) and not GAMEPAD0(6) and not PS2_KEYS(16#014#)) &
(not GAMEPAD0(0) and not PS2_KEYS(16#174#)) &
(not GAMEPAD0(1) and not PS2_KEYS(16#16B#)) &
(not GAMEPAD0(2) and not PS2_KEYS(16#172#)) &
(not GAMEPAD0(3) and not PS2_KEYS(16#175#)) ;
-- NES Gamepad 2
JOY2_n <= (not GAMEPAD1(7) and not GAMEPAD1(6)) & not GAMEPAD1(0) & not GAMEPAD1(1) & not GAMEPAD1(2) & not GAMEPAD1(3);
-- Switch video mode
-- VGA/TV (Ins)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#170#)) then
VGA <= not VGA;
end if;
end process;
-- PAL/NTSC (Home)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#16C#)) then
PAL <= not PAL;
end if;
end process;
-- Scanlines on/off (Page Up)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#17D#)) then
SCANLINES <= not SCANLINES;
end if;
end process;
end rtl;
| gpl-3.0 | 9bfa322b9a953d89c5b933d6e6692359 | 0.478362 | 3.596223 | false | false | false | false |
sonologic/gmzpu | vhdl/zwishbone/test/zwishbone_controller_decode_tb.vhdl | 1 | 14,163 | ------------------------------------------------------------------------------
---- ----
---- gmzpu zwc component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone.all;
entity zwishbone_controller_decode_TB is
end entity zwishbone_controller_decode_TB;
architecture Behave of zwishbone_controller_decode_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant ADR_WIDTH : natural:=18;
constant IO_BIT : natural:=ADR_WIDTH-1;
constant ZWC_BIT : natural:=ADR_WIDTH-2;
constant IO_BIT_WIDTH : natural:=1;
constant ZWC_BIT_WIDTH : natural:=1;
constant BUSBIT_WIDTH : natural:=1;
constant CS_WIDTH : natural:=4;
constant DATA_WIDTH : natural:=32;
type sample is record
-- inputs
rst_i : std_logic;
adr_i : unsigned(ADR_WIDTH-1 downto 0);
re_i : std_logic;
we_i : std_logic;
dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_ack_i : std_logic;
wb_stall_i : std_logic;
wb_err_i : std_logic;
wb_rty_i : std_logic;
-- outputs
wb_cyc_o : std_logic;
wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
wb_we_o : std_logic;
wb_lock_o : std_logic;
busy_o : std_logic;
ready_o : std_logic;
dat_o : unsigned(DATA_WIDTH-1 downto 0);
irq_o : std_logic;
wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
wb_adr_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- rst adr_i re we dat_i wb_dat_i ack stl err rty | cyc stb we lck bus rdy dat_o irq wb_dat_o wb_adr_o
('1',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write config
('0',"000000000000000000",'0','1',X"12345678",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- read config
('0',"000000000000000000",'1','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','1',X"00000001",'0',X"00000000","00000000000"),
-- bus write, stb 1 (device 0)
('0',"111000000000000000",'0','1',X"87654321",X"00000000",'0','0','0','0', '1',X"0001",'1','0','1','0',X"00000000",'0',X"87654321","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'1','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, stb 2 (device 1) (0x8803)
('0',"111000100000000011",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',"000000000000000000",'0','0',X"00000000",X"9abcdef0",'1','0','0','0', '1',X"0000",'0','0','0','1',X"9abcdef0",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write timeout compare reg (set to 2)
('0',"000000000000001000",'0','1',X"00000002",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, timeout (0x8803)
('0',"111000100000000011",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'1',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
-- cancel timeout status (write 0 to status reg)
('0',"000000000000000100",'0','1',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- terminate
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000")
);
signal clk : std_logic;
-- inputs
signal rst_i : std_logic;
signal adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal re_i : std_logic;
signal we_i : std_logic;
signal dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_rty_i : std_logic;
signal wb_tgd_i : unsigned(DATA_WIDTH -1 downto 0);
-- outputs
signal wb_cyc_o : std_logic;
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_we_o : std_logic;
signal wb_lock_o : std_logic;
signal busy_o : std_logic;
signal ready_o : std_logic;
signal dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal irq_o : std_logic;
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgc_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_adr_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_tga_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
-- decode
signal zw_we_i : std_logic;
signal zw_re_i : std_logic;
signal zw_adr_i : unsigned(ADR_WIDTH-3 downto 0);
begin
dut : zwishbone_controller
generic map(ADR_WIDTH => ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH, DATA_WIDTH => DATA_WIDTH, BUSBIT_WIDTH => BUSBIT_WIDTH, CS_WIDTH => CS_WIDTH)
port map(clk_i => clk, rst_i => rst_i,
busy_o => busy_o, ready_o => ready_o, adr_i => zw_adr_i, re_i => re_i, we_i => we_i,
dat_i => dat_i, dat_o => dat_o, irq_o => irq_o,
wb_dat_i => wb_dat_i, wb_dat_o => wb_dat_o, wb_tgd_i => wb_tgd_i,
wb_ack_i => wb_ack_i, wb_adr_o => wb_adr_o, wb_cyc_o => wb_cyc_o,
wb_stall_i => wb_stall_i, wb_err_i => wb_err_i, wb_lock_o => wb_lock_o,
wb_rty_i => wb_rty_i, wb_sel_o => wb_sel_o, wb_stb_o => wb_stb_o,
wb_tga_o => wb_tga_o, wb_tgc_o => wb_tgc_o, wb_we_o => wb_we_o);
wb_dat_o <= (others => 'L');
wb_adr_o <= (others => 'L');
dat_o <= (others => 'L');
zw_we_i <= we_i and adr_i(IO_BIT) and adr_i(ZWC_BIT);
zw_re_i <= re_i and adr_i(IO_BIT) and adr_i(ZWC_BIT);
zw_adr_i <= adr_i(ADR_WIDTH-3 downto 0);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
rst_i <= test_data(i).rst_i;
adr_i <= test_data(i).adr_i;
re_i <= test_data(i).re_i;
we_i <= test_data(i).we_i;
dat_i <= test_data(i).dat_i;
wb_dat_i <= test_data(i).wb_dat_i;
wb_tgd_i <= (others => 'Z'); --test_data(i).wb_tgd_i;
wb_ack_i <= test_data(i).wb_ack_i;
wb_stall_i <= test_data(i).wb_stall_i;
wb_err_i <= test_data(i).wb_err_i;
wb_rty_i <= test_data(i).wb_rty_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (dat_o = test_data(i).dat_o) report "dat_o output mismatch" severity error;
assert (busy_o = test_data(i).busy_o) report "busy_o output mismatch" severity error;
assert (ready_o = test_data(i).ready_o) report "ready_o output mismatch" severity error;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (wb_cyc_o = test_data(i).wb_cyc_o) report "wb_cyc_o output mismatch" severity error;
assert (wb_stb_o = test_data(i).wb_stb_o) report "wb_stb_o output mismatch" severity error;
assert (wb_we_o = test_data(i).wb_we_o) report "wb_we_o output mismatch" severity error;
assert (wb_adr_o = test_data(i).wb_adr_o) report "wb_adr_o output mismatch" severity error;
assert (wb_dat_o = test_data(i).wb_dat_o) report "wb_dat_o output mismatch" severity error;
--assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
--assert (wb_ack_o = test_data(i).wb_ack_o) report "ack_o output mismatch" severity error;
-- assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause | 23b41fd002f3c1c056187bef5693e84e | 0.462543 | 3.450183 | false | true | false | false |
APastorG/APG | permutation/permutation_tb.vhd | 1 | 3,959 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
entity permutation_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
architecture permutation_tb_1 of permutation_tb is
/* constants */
/**************************************************************************************************/
constant INPUT_INDEXES : integer_v := (2, 0, 3, 1); --optional
constant OUTPUT_INDEXES : integer_v := (0, 2, 3, 1); --compulsory
/* signals */
/**************************************************************************************************/
constant PARALLEL_DIMENSIONS : positive := 3;
constant INPUT_LENGTH : positive := integer(2**PARALLEL_DIMENSIONS);
constant INPUT_SIZE : positive := OUTPUT_INDEXES'length;
--IN
signal clk : std_ulogic := '1';
signal input : u_sfixed_v(0 to INPUT_LENGTH-1)(INPUT_SIZE-1 downto 0);
signal start : std_ulogic := '0';
--OUT
signal output : u_sfixed_v(0 to INPUT_LENGTH-1)(INPUT_SIZE-1 downto 0);
signal finish : std_ulogic;
----------------------------------------------------------------------------------------------------
signal aux_counter1 : unsigned(0 to 29) := to_unsigned(1, 30);
signal aux_counter2 : unsigned(0 to 29) := to_unsigned(2, 30);
signal aux_counter3 : unsigned(0 to OUTPUT_INDEXES'length-1) := to_unsigned(0, INPUT_SIZE);
/*================================================================================================*/
/*================================================================================================*/
begin
permutation_s:
entity work.permutation_s
generic map(
INPUT_INDEXES => INPUT_INDEXES,
OUTPUT_INDEXES => OUTPUT_INDEXES
)
port map(
clk => clk,
input => input,
start => start,
output => output,
finish => finish
);
--pragma translate off
process (clk)
begin
clk <= not clk after 2 ps;
end process;
process
begin
wait for 36 ps;
start <= '1';
wait for 4 ps;
start <= '0';
wait;
end process;
--generates pseudorandom values for the input
--process (clk)
-- variable real_number : real;
-- variable seed1 : positive := to_integer(aux_counter1);
-- variable seed2 : positive := to_integer(aux_counter2);
--begin
-- if rising_edge (clk) then
-- for i in input'range loop
-- uniform(seed1, seed2, real_number);
-- input(i) <= to_sulv(to_ufixed(real_number, -1, -INPUT_SIZE));
-- end loop;
-- aux_counter1 <= aux_counter1 + to_unsigned(1, 30);
-- aux_counter2 <= aux_counter2 + to_unsigned(1, 30);
-- end if;
--end process;
--generates values for the input that equal their index
process (clk)
begin
if rising_edge (clk) then
for i in input'range loop
input(i) <= to_sfixed(to_integer(aux_counter3) + i, input(i));
end loop;
aux_counter3 <= aux_counter3 + input'length;
end if;
end process;
--pragma translate on
end architecture;
| mit | 0875c46de6a38d86170bed9c4b6dedf3 | 0.429907 | 4.571594 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/video/video_bak.vhd | 2 | 8,546 | -- XGA Signal 1024 x 768 @ 60 Hz timing
-- General timing
-- Screen refresh rate 60 Hz
-- Vertical refresh 48.363095238095 kHz
-- Pixel freq. 65.0 MHz
-- Horizontal timing (line)
-- Polarity of horizontal sync pulse is negative.
-- Scanline part Pixels Time [µs]
-- Visible area 1024 15.753846153846
-- Front porch 24 0.36923076923077
-- Sync pulse 136 2.0923076923077
-- Back porch 160 2.4615384615385
-- Whole line 1344 20.676923076923
-- Vertical timing (frame)
-- Polarity of vertical sync pulse is negative.
-- Frame part Lines Time [ms]
-- Visible area 768 15.879876923077
-- Front porch 3 0.062030769230769
-- Sync pulse 6 0.12406153846154
-- Back porch 29 0.59963076923077
-- Whole frame 806 16.6656
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; -- Active buffer
CACHE_A : out std_logic_vector(5 downto 0); -- Cache address
CACHE_D : in std_logic_vector(31 downto 0); -- Cache data
CURRENT_LINE : out std_logic_vector(7 downto 0); -- Current line to read in cache
LUT_A : out std_logic_vector(3 downto 0); -- LUT address
LUT_D : in std_logic_vector(3 downto 0); -- LUT data
VBLANK : out std_logic;
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
constant H_TICKS : natural := 679;
constant V_TICKS : natural := 805;
constant H_SIZE : natural := 512;
constant V_SIZE : natural := 768;
constant HSYNC_B : natural := 531;
constant HSYNC_E : natural := 600;
constant VSYNC_B : natural := 770;
constant VSYNC_E : natural := 800;
------------------------------------------------------------
signal H_COUNTER : unsigned(9 downto 0); -- Horizontal Counter
signal V_COUNTER : unsigned(9 downto 0); -- Vertical Counter
signal THREE_TICK : unsigned(1 downto 0); -- Three Rows Tick
signal SCANLINE : unsigned(7 downto 0); -- Current Scanline for Video Output
signal FLIP_CACHE : std_logic;
signal PAPER : std_logic; -- Paper Area
signal PAPER_L : std_logic; -- Paper zone
signal PAPER_LL : std_logic; -- Paper zone
signal VBLANK_TICK : unsigned(9 downto 0);
signal PIX_R : std_logic_vector(7 downto 0); -- Red byte latch
signal PIX_G : std_logic_vector(7 downto 0); -- Green byte latch
signal PIX_B : std_logic_vector(7 downto 0); -- Blue byte latch
signal PIX_C : std_logic_vector(7 downto 0); -- Char byte latch
type palette_t is array(0 to 15) of std_logic_vector(23 downto 0);
constant color_palette : palette_t := ( "000000000000000000000000", -- 0
"000000000110000000001010", -- 1
"000001100000000010100000", -- 2
"000001100110000010101010", -- 3
"011000000000101000000000", -- 4
"011000000110101000001010", -- 5
"011001100000101010100000", -- 6
"011001100110101010101010", -- 7
"001100110011010101010101", -- 8
"001100111001010101011111", -- 9
"001110010011010111110101", -- 10
"001110011001010111111111", -- 11
"100100110011111101010101", -- 12
"100100111001111101011111", -- 13
"100110010011111111110101", -- 14
"100110011001111111111111");-- 15
begin
CURRENT_LINE <= std_logic_vector(SCANLINE);
CACHE_SWAP <= FLIP_CACHE;
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
H_COUNTER <= (others => '0');
V_COUNTER <= (others => '0');
THREE_TICK <= "00";
SCANLINE <= "00000001";
FLIP_CACHE <= '0';
PAPER <= '0';
HSYNC <= '1';
VSYNC <= '1';
VBLANK <= '0';
VBLANK_TICK <= (others => '0');
else
PAPER <= '0';
HSYNC <= '1';
VSYNC <= '1';
VBLANK <= '0';
FLIP_CACHE <= '0';
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = H_TICKS then
H_COUNTER <= (others => '0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = V_TICKS then
V_COUNTER <= (others => '0');
end if;
VBLANK_TICK <= VBLANK_TICK + 1;
if VBLANK_TICK = 994 then
VBLANK_TICK <= (others => '0');
end if;
end if;
if H_COUNTER < H_SIZE and V_COUNTER < V_SIZE then
PAPER <= '1';
end if;
if H_COUNTER > HSYNC_B and H_COUNTER < HSYNC_E then
HSYNC <= '0';
end if;
if VBLANK_TICK < 6 then
VBLANK <= '1';
end if;
if V_COUNTER > VSYNC_B and V_COUNTER < VSYNC_E then
VSYNC <= '0';
end if;
if H_COUNTER = H_TICKS - 16 and V_COUNTER < V_SIZE then
THREE_TICK <= THREE_TICK + 1;
if THREE_TICK = 2 then
THREE_TICK <= "00";
SCANLINE <= SCANLINE + 1;
FLIP_CACHE <= '1';
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" => CACHE_A <= std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX_C <= CACHE_D(31 downto 24);
PIX_R <= CACHE_D(23 downto 16);
PIX_G <= CACHE_D(15 downto 8);
PIX_B <= CACHE_D(7 downto 0);
PAPER_L <= PAPER;
when others => null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
LUT_A <= PIX_C(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_R(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_G(7 - to_integer(H_COUNTER(2 downto 0))) &
PIX_B(7 - to_integer(H_COUNTER(2 downto 0)));
PAPER_LL <= PAPER_L;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_LL = '1' then
if THREE_TICK = "01" then
R <= color_palette(to_integer(unsigned(LUT_D)))(11 downto 8);
G <= color_palette(to_integer(unsigned(LUT_D)))(7 downto 4);
B <= color_palette(to_integer(unsigned(LUT_D)))(3 downto 0);
else
R <= color_palette(to_integer(unsigned(LUT_D)))(23 downto 20);
G <= color_palette(to_integer(unsigned(LUT_D)))(19 downto 16);
B <= color_palette(to_integer(unsigned(LUT_D)))(15 downto 12);
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 72cb088013b388cc829726e1b51f03d4 | 0.448683 | 4.291813 | false | false | false | false |
223323/lab2 | HDL/source/tb/vhdl/top_tb.vhd | 1 | 2,130 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: top_tb
--
-- Description:
--
-- TB for top
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity top_tb is
end top_tb;
architecture behavior of top_tb is
-- component Declaration
component top
generic (
RES_TYPE : natural := 0;
TEXT_MEM_DATA_WIDTH : natural := 6;
GRAPH_MEM_DATA_WIDTH : natural := 32
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
--
direct_mode_i : in std_logic;
display_mode_i : in std_logic_vector(1 downto 0);
-- vga
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
blank_o : out std_logic;
pix_clock_o : out std_logic;
psave_o : out std_logic;
sync_o : out std_logic;
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0)
);
end component;
signal clk : std_logic;
signal reset_n : std_logic;
begin
clk_gen : process
begin
clk <= '1';
wait for 41.66 ns;
clk <= '0';
wait for 41.66 ns;
end process clk_gen;
-- component instantiation
uut: top
generic map(
RES_TYPE => 1,
TEXT_MEM_DATA_WIDTH => 6,
GRAPH_MEM_DATA_WIDTH => 32
)
port map(
clk_i => clk,
reset_n_i => reset_n,
--
direct_mode_i => '0',
display_mode_i => "10"
);
-- test bench statements
tb : process
begin
reset_n <= '0';
wait for 100 us; -- wait until global set/reset completes
reset_n <= '1';
-- add user defined stimulus here
wait; -- will wait forever
end process tb;
-- end test bench
end; | mit | f96e343f4981e73e0ddab622c05f444a | 0.495775 | 3.474715 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/interrupt_line_tb.vhdl | 1 | 6,468 | ------------------------------------------------------------------------------
---- ----
---- gmzpu interrupt line component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.pic;
library zpu;
use zpu.txt_util.all;
entity interrupt_line_TB is
end entity interrupt_line_TB;
architecture Behave of interrupt_line_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
component interrupt_line is
port (
clk_i : in std_logic;
int_i : in std_logic;
irq_o : out std_logic;
icr_o : out std_logic;
icr_i : in std_logic;
imr_i : in std_logic;
ier_i : in std_logic;
itr_i : in std_logic;
we_i : in std_logic
);
end component interrupt_line;
type sample is record
-- inputs
int_i : std_logic;
icr_i : std_logic;
imr_i : std_logic;
ier_i : std_logic;
itr_i : std_logic;
we_i : std_logic;
-- outputs
irq_o : std_logic;
icr_o : std_logic;
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- int icr imr ier itr we irq icr
-- reset
('0','0','0','0','0','1', '0','U'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
('1','0','1','0','0','0', '0','0'),
('0','0','1','0','0','0', '1','1'),
('0','0','1','0','0','0', '1','1'),
('0','0','0','0','0','1', '0','1'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0')
);
signal clk : std_logic;
signal int_i : std_logic;
signal icr_i : std_logic;
signal imr_i : std_logic;
signal ier_i : std_logic;
signal itr_i : std_logic;
signal we_i : std_logic;
signal irq_o : std_logic;
signal icr_o : std_logic;
begin
line : interrupt_line
port map(int_i => int_i, icr_i => icr_i, imr_i => imr_i, ier_i => ier_i, itr_i => itr_i, we_i => we_i,
irq_o => irq_o, icr_o => icr_o,
clk_i => clk);
process
variable cycle_count : integer:=0;
begin
print("Start test");
for i in test_data'range loop
int_i <= test_data(i).int_i;
icr_i <= test_data(i).icr_i;
imr_i <= test_data(i).imr_i;
ier_i <= test_data(i).ier_i;
itr_i <= test_data(i).itr_i;
we_i <= test_data(i).we_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity error;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause | 1f3767505dfb9bdf819ef13c3a34826c | 0.300557 | 4.734993 | false | true | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/thermometersLogicTB.vhd | 1 | 1,842 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY thermometersLogicTB IS
END thermometersLogicTB;
ARCHITECTURE behavior OF thermometersLogicTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT thermometersLogic
PORT(
rsTxBusy : IN std_logic;
rst : IN std_logic;
clk50Mhz : IN std_logic;
clk3kHz : IN std_logic;
rsDataOut : OUT std_logic_vector(7 downto 0);
rsTxStart : OUT std_logic
);
END COMPONENT;
--Inputs
signal rsTxBusy : std_logic := '0';
signal rst : std_logic := '0';
signal clk50Mhz : std_logic := '0';
signal clk3kHz : std_logic := '0';
--Outputs
signal rsDataOut : std_logic_vector(7 downto 0);
signal rsTxStart : std_logic;
-- Clock period definitions
constant clk50Mhz_period : time := 20 ns;
constant clk3kHz_period : time := 327680 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: thermometersLogic PORT MAP (
rsTxBusy => rsTxBusy,
rst => rst,
clk50Mhz => clk50Mhz,
clk3kHz => clk3kHz,
rsDataOut => rsDataOut,
rsTxStart => rsTxStart
);
-- Clock process definitions
clk50Mhz_process :process
begin
clk50Mhz <= '0';
wait for clk50Mhz_period/2;
clk50Mhz <= '1';
wait for clk50Mhz_period/2;
end process;
clk3kHz_process :process
begin
clk3kHz <= '0';
wait for clk3kHz_period/2;
clk3kHz <= '1';
wait for clk3kHz_period/2;
end process;
rs232Proc: process(rsTxStart)
begin
if rsTxStart'event and rsTxStart = '1' then
rsTxBusy <= '1' after 20 ns, '0' after 78125 ns;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 5 ns;
rst <= '0';
wait;
end process;
END;
| mit | 2290183881cbda7e8ffe37e15f3b9bee | 0.617807 | 3.29517 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/skew_outpad.vhd | 1 | 2,082 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
| gpl-2.0 | 2f261480a3848418ce25d7969e54ea1e | 0.617675 | 3.973282 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_cdma_0_0/synth/design_1_axi_cdma_0_0.vhd | 1 | 18,573 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_cdma:4.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_cdma_v4_1;
USE axi_cdma_v4_1.axi_cdma;
ENTITY design_1_axi_cdma_0_0 IS
PORT (
m_axi_aclk : IN STD_LOGIC;
s_axi_lite_aclk : IN STD_LOGIC;
s_axi_lite_aresetn : IN STD_LOGIC;
cdma_introut : OUT STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arready : IN STD_LOGIC;
m_axi_arvalid : OUT STD_LOGIC;
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rready : OUT STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wready : IN STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_bvalid : IN STD_LOGIC;
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cdma_tvect_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_cdma_0_0;
ARCHITECTURE design_1_axi_cdma_0_0_arch OF design_1_axi_cdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_cdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_AXI_LITE_IS_ASYNC : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_MAX_BURST_LEN : INTEGER;
C_INCLUDE_DRE : INTEGER;
C_USE_DATAMOVER_LITE : INTEGER;
C_READ_ADDR_PIPE_DEPTH : INTEGER;
C_WRITE_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_SF : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_FAMILY : STRING
);
PORT (
m_axi_aclk : IN STD_LOGIC;
s_axi_lite_aclk : IN STD_LOGIC;
s_axi_lite_aresetn : IN STD_LOGIC;
cdma_introut : OUT STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arready : IN STD_LOGIC;
m_axi_arvalid : OUT STD_LOGIC;
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rready : OUT STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wready : IN STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_bvalid : IN STD_LOGIC;
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
cdma_tvect_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_cdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "axi_cdma,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_cdma_0_0_arch : ARCHITECTURE IS "design_1_axi_cdma_0_0,axi_cdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "design_1_axi_cdma_0_0,axi_cdma,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_cdma,x_ipVersion=4.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=6,C_S_AXI_LITE_DATA_WIDTH=32,C_AXI_LITE_IS_ASYNC=0,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_MAX_BURST_LEN=16,C_INCLUDE_DRE=0,C_USE_DATAMOVER_LITE=0,C_READ_ADDR_PIPE_DEPTH=4,C_WRITE_ADDR_PIPE_DEPTH=4,C_INCLUDE_SF=0,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=256,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF cdma_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 CDMA_INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
BEGIN
U0 : axi_cdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 6,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_AXI_LITE_IS_ASYNC => 0,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_MAX_BURST_LEN => 16,
C_INCLUDE_DRE => 0,
C_USE_DATAMOVER_LITE => 0,
C_READ_ADDR_PIPE_DEPTH => 4,
C_WRITE_ADDR_PIPE_DEPTH => 4,
C_INCLUDE_SF => 0,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 256,
C_FAMILY => "zynq"
)
PORT MAP (
m_axi_aclk => m_axi_aclk,
s_axi_lite_aclk => s_axi_lite_aclk,
s_axi_lite_aresetn => s_axi_lite_aresetn,
cdma_introut => cdma_introut,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arprot => m_axi_arprot,
m_axi_arcache => m_axi_arcache,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awprot => m_axi_awprot,
m_axi_awcache => m_axi_awcache,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
m_axi_bresp => m_axi_bresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bvalid => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_arready => '0',
m_axi_sg_rvalid => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
cdma_tvect_out => cdma_tvect_out
);
END design_1_axi_cdma_0_0_arch;
| gpl-3.0 | 08de5b2485b47c61cbaf4c32cda39bb8 | 0.678835 | 3.036292 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_Block_Mat_exit1220_proc1.vhd | 2 | 36,633 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_Mat_exit1220_proc1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_read2 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read16 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read17 : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
src0_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_0_V_full_n : IN STD_LOGIC;
src0_data_stream_0_V_write : OUT STD_LOGIC;
src0_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_1_V_full_n : IN STD_LOGIC;
src0_data_stream_1_V_write : OUT STD_LOGIC;
src0_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_2_V_full_n : IN STD_LOGIC;
src0_data_stream_2_V_write : OUT STD_LOGIC;
src1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_0_V_full_n : IN STD_LOGIC;
src1_data_stream_0_V_write : OUT STD_LOGIC;
src1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_1_V_full_n : IN STD_LOGIC;
src1_data_stream_1_V_write : OUT STD_LOGIC;
src1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_2_V_full_n : IN STD_LOGIC;
src1_data_stream_2_V_write : OUT STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_Mat_exit1220_proc1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_21 : BOOLEAN;
signal ap_sig_bdd_82 : BOOLEAN;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_idle : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_ready : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_empty_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_read : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_empty_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_read : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_empty_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_read : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_full_n : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_write : STD_LOGIC;
signal grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_137 : BOOLEAN;
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_4_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_5_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_6_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_7_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component image_filter_Duplicate_1080_1920_32_32_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_0_V_empty_n : IN STD_LOGIC;
src_data_stream_0_V_read : OUT STD_LOGIC;
src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_1_V_empty_n : IN STD_LOGIC;
src_data_stream_1_V_read : OUT STD_LOGIC;
src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_2_V_empty_n : IN STD_LOGIC;
src_data_stream_2_V_read : OUT STD_LOGIC;
dst1_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst1_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_0_V_full_n : IN STD_LOGIC;
dst1_data_stream_0_V_write : OUT STD_LOGIC;
dst1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_1_V_full_n : IN STD_LOGIC;
dst1_data_stream_1_V_write : OUT STD_LOGIC;
dst1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_2_V_full_n : IN STD_LOGIC;
dst1_data_stream_2_V_write : OUT STD_LOGIC;
dst2_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst2_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_0_V_full_n : IN STD_LOGIC;
dst2_data_stream_0_V_write : OUT STD_LOGIC;
dst2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_1_V_full_n : IN STD_LOGIC;
dst2_data_stream_1_V_write : OUT STD_LOGIC;
dst2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_2_V_full_n : IN STD_LOGIC;
dst2_data_stream_2_V_write : OUT STD_LOGIC );
end component;
begin
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97 : component image_filter_Duplicate_1080_1920_32_32_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start,
ap_done => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done,
ap_idle => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_idle,
ap_ready => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_ready,
src_rows_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_rows_V_read,
src_cols_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_cols_V_read,
src_data_stream_0_V_dout => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_dout,
src_data_stream_0_V_empty_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_empty_n,
src_data_stream_0_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_read,
src_data_stream_1_V_dout => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_dout,
src_data_stream_1_V_empty_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_empty_n,
src_data_stream_1_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_read,
src_data_stream_2_V_dout => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_dout,
src_data_stream_2_V_empty_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_empty_n,
src_data_stream_2_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_read,
dst1_rows_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_rows_V_read,
dst1_cols_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_cols_V_read,
dst1_data_stream_0_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_din,
dst1_data_stream_0_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_full_n,
dst1_data_stream_0_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_write,
dst1_data_stream_1_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_din,
dst1_data_stream_1_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_full_n,
dst1_data_stream_1_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_write,
dst1_data_stream_2_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_din,
dst1_data_stream_2_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_full_n,
dst1_data_stream_2_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_write,
dst2_rows_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_rows_V_read,
dst2_cols_V_read => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_cols_V_read,
dst2_data_stream_0_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_din,
dst2_data_stream_0_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_full_n,
dst2_data_stream_0_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_write,
dst2_data_stream_1_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_din,
dst2_data_stream_1_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_full_n,
dst2_data_stream_1_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_write,
dst2_data_stream_2_V_din => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_din,
dst2_data_stream_2_V_full_n => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_full_n,
dst2_data_stream_2_V_write => grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_write);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_0_preg <= p_read;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_1_preg <= p_read2;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_2_preg <= p_read;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_3_preg <= p_read2;
end if;
end if;
end if;
end process;
-- ap_return_4_preg assign process. --
ap_return_4_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_4_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_4_preg <= p_read;
end if;
end if;
end if;
end process;
-- ap_return_5_preg assign process. --
ap_return_5_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_5_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_5_preg <= p_read2;
end if;
end if;
end if;
end process;
-- ap_return_6_preg assign process. --
ap_return_6_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_6_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_6_preg <= p_read;
end if;
end if;
end if;
end process;
-- ap_return_7_preg assign process. --
ap_return_7_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_7_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_7_preg <= p_read2;
end if;
end if;
end if;
end process;
-- grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg assign process. --
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_82))) then
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_ready)) then
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_82, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_82)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(p_read, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_0 <= p_read;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(p_read2, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_1 <= p_read2;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(p_read, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_2 <= p_read;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(p_read2, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_3 <= p_read2;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_return_4 assign process. --
ap_return_4_assign_proc : process(p_read, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_4_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_4 <= p_read;
else
ap_return_4 <= ap_return_4_preg;
end if;
end process;
-- ap_return_5 assign process. --
ap_return_5_assign_proc : process(p_read2, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_5_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_5 <= p_read2;
else
ap_return_5 <= ap_return_5_preg;
end if;
end process;
-- ap_return_6 assign process. --
ap_return_6_assign_proc : process(p_read, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_6_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_6 <= p_read;
else
ap_return_6 <= ap_return_6_preg;
end if;
end process;
-- ap_return_7 assign process. --
ap_return_7_assign_proc : process(p_read2, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done, ap_sig_cseq_ST_st2_fsm_1, ap_return_7_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_done)))) then
ap_return_7 <= p_read2;
else
ap_return_7 <= ap_return_7_preg;
end if;
end process;
-- ap_sig_bdd_137 assign process. --
ap_sig_bdd_137_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_137 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_21 assign process. --
ap_sig_bdd_21_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_21 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_82 assign process. --
ap_sig_bdd_82_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_82 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_21)
begin
if (ap_sig_bdd_21) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_137)
begin
if (ap_sig_bdd_137) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_ap_start_ap_start_reg;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_cols_V_read <= p_read2;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_full_n <= src0_data_stream_0_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_full_n <= src0_data_stream_1_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_full_n <= src0_data_stream_2_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_rows_V_read <= p_read;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_cols_V_read <= p_read2;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_full_n <= src1_data_stream_0_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_full_n <= src1_data_stream_1_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_full_n <= src1_data_stream_2_V_full_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_rows_V_read <= p_read;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_cols_V_read <= p_read17;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_dout <= p_src_data_stream_0_V_dout;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_empty_n <= p_src_data_stream_0_V_empty_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_dout <= p_src_data_stream_1_V_dout;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_empty_n <= p_src_data_stream_1_V_empty_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_dout <= p_src_data_stream_2_V_dout;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_empty_n <= p_src_data_stream_2_V_empty_n;
grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_rows_V_read <= p_read16;
-- p_src_data_stream_0_V_read assign process. --
p_src_data_stream_0_V_read_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_read, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
p_src_data_stream_0_V_read <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_0_V_read;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_1_V_read assign process. --
p_src_data_stream_1_V_read_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_read, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
p_src_data_stream_1_V_read <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_1_V_read;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_2_V_read assign process. --
p_src_data_stream_2_V_read_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_read, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
p_src_data_stream_2_V_read <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_src_data_stream_2_V_read;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
src0_data_stream_0_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_din;
-- src0_data_stream_0_V_write assign process. --
src0_data_stream_0_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src0_data_stream_0_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_0_V_write;
else
src0_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
src0_data_stream_1_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_din;
-- src0_data_stream_1_V_write assign process. --
src0_data_stream_1_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src0_data_stream_1_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_1_V_write;
else
src0_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
src0_data_stream_2_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_din;
-- src0_data_stream_2_V_write assign process. --
src0_data_stream_2_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src0_data_stream_2_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst1_data_stream_2_V_write;
else
src0_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
src1_data_stream_0_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_din;
-- src1_data_stream_0_V_write assign process. --
src1_data_stream_0_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src1_data_stream_0_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_0_V_write;
else
src1_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
src1_data_stream_1_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_din;
-- src1_data_stream_1_V_write assign process. --
src1_data_stream_1_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src1_data_stream_1_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_1_V_write;
else
src1_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
src1_data_stream_2_V_din <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_din;
-- src1_data_stream_2_V_write assign process. --
src1_data_stream_2_V_write_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_write, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
src1_data_stream_2_V_write <= grp_image_filter_Duplicate_1080_1920_32_32_s_fu_97_dst2_data_stream_2_V_write;
else
src1_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
end behav;
| gpl-3.0 | eba759bd4314862b7fc6f36dd3f97621 | 0.622253 | 2.638125 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/spw/wrapper/grspw_gen.vhd | 1 | 11,111 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
| gpl-2.0 | 9259a05b3806db44ce085369ba0d9171 | 0.551526 | 4.065496 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/umc18/pads_umc18.vhd | 1 | 8,514 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
| gpl-2.0 | 400cfc3dc4d190762d30cc4d68f30e73 | 0.653512 | 3.253344 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_sm.vhd | 2 | 28,379 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
attribute mark_debug of mm2s_cmnd_wr_i : signal is "true";
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| gpl-3.0 | ede9280832df12f80d1fabe9ca84be71 | 0.400895 | 4.595789 | false | false | false | false |
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