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sonologic/gmzpu | vhdl/ZetaIO/timer/timer.vhdl | 1 | 10,946 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity timer is
generic (
ADR_WIDTH : natural:=3;
DATA_WIDTH : natural:=32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
inc_i : in std_logic;
addr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
we_i : in std_logic;
en_i : in std_logic;
thresh_o: out std_logic
);
end entity timer;
architecture rtl of timer is
-- single timer
-- registers:
-- CNT 0x0
-- THR 0x1
-- output:
-- thresh_o
signal CNT : unsigned(DATA_WIDTH-1 downto 0);
signal THR : unsigned(DATA_WIDTH-1 downto 0);
signal CFG : unsigned(DATA_WIDTH-1 downto 0);
signal halt_r : std_logic;
signal thresh_r : std_logic;
signal dat_en_r : std_logic;
-- CFG reg
signal cfg_hlt_r: std_logic;
signal cfg_rst_r: std_logic;
signal cfg_stk_r: std_logic;
signal cfg_ien_r: std_logic;
signal cfg_ten_r: std_logic;
-- cross clock domain handshake
-- reset CNT
signal clk_to_inc_rst_r : std_logic;
signal inc_to_clk_rst_r : std_logic;
-- acknowledge theshold
signal clk_to_inc_ack_r : std_logic;
signal inc_to_clk_ack_r : std_logic;
begin
-- config register
cfg_hlt_r <= CFG(0);
cfg_rst_r <= CFG(1);
cfg_stk_r <= CFG(2);
cfg_ien_r <= CFG(3);
cfg_ten_r <= CFG(4);
-- enable dat_o when not in reset and read enable
dat_en_r <= (not rst_i) and en_i and (not we_i);
-- assign register or high-z to dat_o
dat_o <= CNT when dat_en_r='1' and addr_i=to_unsigned(0,ADR_WIDTH) else
THR when dat_en_r='1' and addr_i=to_unsigned(1,ADR_WIDTH) else
CFG when dat_en_r='1' and addr_i=to_unsigned(2,ADR_WIDTH) else
(others => 'Z');
process(clk_i)
begin
end process;
write_regs:
process(clk_i,rst_i)
begin
if rst_i='1' then
THR <= (others => '1');
CFG <= (others => '0');
clk_to_inc_rst_r <= '0';
clk_to_inc_ack_r <= '0';
elsif rising_edge(clk_i) then
if en_i='1' then
-- mem i/o
if we_i='1' then
case addr_i(1 downto 0) is
when "00" =>
-- write to CNT, trigger CNT reset
clk_to_inc_rst_r <= '1';
when "01" =>
-- write to THR
THR <= dat_i;
when "10" =>
-- write to CFG
CFG <= dat_i;
if dat_i(3)='1' then
-- if ien is written, reset cnt and ack threshold
clk_to_inc_rst_r <= '1';
clk_to_inc_ack_r <= '1';
end if;
when others =>
-- write to ACK, trigger threshold reset
clk_to_inc_ack_r <= '1';
end case;
end if;
end if;
if inc_to_clk_rst_r='1' then
clk_to_inc_rst_r <= '0';
end if;
if inc_to_clk_ack_r='1' then
clk_to_inc_ack_r <= '0';
end if;
end if;
end process write_regs;
counter:
process(inc_i,rst_i,cfg_ten_r)
variable newCNT : unsigned(DATA_WIDTH-1 downto 0);
begin
if rst_i='1' then
CNT <= (others => '0');
thresh_r <= '0';
inc_to_clk_rst_r <= '0';
inc_to_clk_ack_r <= '0';
elsif rising_edge(inc_i) then
-- reset
if clk_to_inc_rst_r='1' then
CNT <= (others => '0');
inc_to_clk_rst_r <= '1';
else -- clk_to_inc_rst_r='0'
inc_to_clk_rst_r <= '0';
end if;
-- ack threshold
if clk_to_inc_ack_r='1' then
thresh_r <= '0';
inc_to_clk_ack_r <= '1';
else
inc_to_clk_ack_r <= '0';
end if;
-- count and compare
if cfg_ten_r='1' and clk_to_inc_rst_r='0' then
newCNT := CNT;
if halt_r='0' then
-- inc(CNT)
newCNT := CNT + to_unsigned(1, CNT'length);
end if;
CNT <= newCNT;
if newCNT>=THR then
-- set threshold output
thresh_r <= '1';
-- reset counter
if cfg_rst_r='1' then
CNT <= (others => '0');
end if;
else
-- reset threshold output (if not sticky)
if cfg_stk_r='0' and thresh_r='1' then
thresh_r <= '0';
end if;
end if;
end if;
end if;
end process counter;
thresh_o <= cfg_ien_r and thresh_r;
-- halt counter when cfg_hlt_r asserted and threshold detected
halt_r <= cfg_hlt_r and thresh_r;
end architecture rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity timers is
generic (
DATA_WIDTH : natural:=32;
ADR_WIDTH : natural:=4;
N_TIMERS : natural:=4
);
port (
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic;
-- non wishbone
irq_o : out std_logic
);
end entity timers;
architecture rtl of timers is
component timer is
generic (
ADR_WIDTH : natural:=4;
DATA_WIDTH : natural:=32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
inc_i : in std_logic;
addr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
en_i : in std_logic;
we_i : in std_logic;
thresh_o: out std_logic
);
end component timer;
signal irq_r : std_logic_vector(N_TIMERS-1 downto 0);
signal ten_r : std_logic_vector(N_TIMERS-1 downto 0);
signal cs_r : unsigned(ADR_WIDTH-3 downto 0);
signal addr_r : unsigned(ADR_WIDTH-1 downto 0);
signal en_r : std_logic;
signal we_r : std_logic;
signal dat_r : unsigned(DATA_WIDTH-1 downto 0);
-- delayed signals
signal we_d : std_logic;
signal dat_d : unsigned(DATA_WIDTH-1 downto 0);
signal addr_d : unsigned(ADR_WIDTH-1 downto 0);
signal my_cyc_r : std_logic;
begin
timer_gen: for i in N_TIMERS-1 downto 0 generate
timerX : timer
generic map(ADR_WIDTH => 2, DATA_WIDTH => DATA_WIDTH)
port map(clk_i => clk_i, rst_i => rst_i, inc_i => clk_i,
addr_i => addr_d(3 downto 2), thresh_o => irq_r(i),
dat_o => wb_dat_o, dat_i => dat_d,
we_i => we_d, en_i => ten_r(i));
end generate;
wb_tgd_o <= (others => 'Z');
wb_tgd_o <= (others => 'Z');
wb_stall_o <= '0' when my_cyc_r='1' else 'Z';
wb_err_o <= '0' when my_cyc_r='1' else 'Z';
wb_rty_o <= '0' when my_cyc_r='1' else 'Z';
cs_r <= addr_r(ADR_WIDTH-1 downto 2);
--wb_ack_o <= cyc_r and not en_r;
--wb_ack_o <= '0' when ten_r=(ten_r'range => '0') else
-- wb_cyc_i;
process(clk_i,rst_i)
begin
if rst_i='1' then
addr_r <= (others => '0');
en_r <= '0';
we_r <= '0';
dat_r <= (others => '0');
addr_d <= (others => '0');
we_d <= '0';
dat_d <= (others => '0');
ten_r <= (others => '0');
my_cyc_r <= '0';
elsif rising_edge(clk_i) then
if my_cyc_r='1' and wb_cyc_i='0' then
my_cyc_r <= '0';
end if;
if wb_stb_i='1' or en_r='1' then
-- clock in input signals
if wb_stb_i='1' then
addr_r <= wb_adr_i;
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
en_r <= '1';
my_cyc_r <= '1';
else
en_r <= '0';
end if;
we_r <= wb_we_i;
dat_r <= wb_dat_i;
-- delay signals to allow one cycle for chip select
addr_d <= addr_r;
we_d <= we_r;
dat_d <= dat_r;
-- decode cs_i to ten_r
for i in ten_r'range loop
if i=cs_r then
ten_r(i) <= en_r and not rst_i;
else
ten_r(i) <= '0';
end if;
end loop;
else
ten_r <= (others => '0');
end if;
end if;
end process;
wb_ack_o <= 'Z' when rst_i='1' else
'0' when my_cyc_r='1' and wb_stb_i='1' else
'1' when my_cyc_r='1' else
'Z';
--process(clk_i,rst_i)
--begin
-- if rst_i='1' then
-- wb_ack_o <= 'Z';
-- elsif rising_edge(clk_i) then
-- if my_cyc_r='1' then
-- wb_ack_o <= '1';
-- elsif wb_stb_i='1' and wb_cyc_i='1' then
-- wb_ack_o <= '0';
-- else
-- wb_ack_o <= 'Z';
-- end if;
-- end if;
--end process;
irq_o <= '0' when irq_r=(irq_r'range => '0') or rst_i='1' else '1';
--decode_cs: for i in ten_r'range generate
-- ten_r(i) <= en_i and not rst_i when i=cs_r else '0';
--end generate;
end architecture rtl;
| bsd-3-clause | d1430c9018fe85bb53951b3d0b06e24f | 0.436689 | 3.430273 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/vram/vram.vhd | 1 | 6,163 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| gpl-3.0 | 7908264800d61889a3ab8f65cd6618f1 | 0.522797 | 3.898166 | false | false | false | false |
freecores/lq057q3dc02 | design/vsyncx_control.vhd | 1 | 12,541 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: vsyncx_control.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- This file controls VSYNCx. VSYNCx is dependent upon the number of HSYNCx
-- activations (i.e. the numbers of lines) that have passed. The really cool
-- thing about the VSYNCx control state machine is that it is _EXACTLY_ the
-- same as the HSYNCx control state machine expect that instead of have the
-- counter process counting CLK_LCD cycles we have counting HSYNCx cycles!
-- It's really that simple!
--
-- VSYNCx signifies the start of a frame. HSYNCx must pulse exactly 7 times
-- (i.e. 7 lines) after (minimum of 0 ns after - TVh) VSYNCx pulse occurs
-- before sending data to the LCD. You can consider these 7 lines as blank
-- lines that "live" above the physical top of the screen. After 7 HSYNCx
-- pulses have passed we can then start with line 1 and go to line 240 for a
-- total of 7 + 240 lines = 247 lines (or HSYNCx pulses) for every complete
-- image or "frame" drawn to the screen!
--
-- Note: Even though VSYNCx controls the start of a frame you cannot simply
-- disable HSYNCx cycling once the data has been shifted into the LCD. This
-- is b/c there is a MAX cycle time spec in the datasheet of 450 clocks!
-- It is simplest to just leave HSYNCx running at all times no matter what.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY vsyncx_control IS
-----------------------------------------------------------------
-- Generic Descriptions:
--
-- C_LINE_NUM_WIDTH -- Must be at least 9 bits to hold maximum
-- -- timespec of 280 lines.
-----------------------------------------------------------------
generic (
C_VSYNC_TV,
C_VSYNC_TVP,
C_LINE_NUM_WIDTH : POSITIVE
);
port (
RSTx,
CLK_LCD,
HSYNCx : IN STD_LOGIC;
LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
VSYNCx : OUT STD_LOGIC
);
END ENTITY vsyncx_control;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE vsyncx_control_arch OF vsyncx_control IS
--Enables/Disables the line counter process
signal line_cnt_en_sig : std_logic;
--Stores current line number.
--This register is attached to the LINE_NUM output.
signal line_num_reg : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0');
---------------------------------------------------------------
-- States for VSYNCx_Line_Cntr_*_PROC
---------------------------------------------------------------
--FRAME_START => Start of a new frame
--ADD => Add one (1) to the line count
--ADD_WAIT => Wait for HSYNCx pulse to pass
--READY => Get ready to add one (1) for the next line
type TYPE_Line_Cntr_Sts is ( FRAME_START, ADD, ADD_WAIT, READY );
signal Line_Cntr_cs : TYPE_Line_Cntr_Sts;
signal Line_Cntr_ns : TYPE_Line_Cntr_Sts;
begin
--///////////////////////--
-- CONCURRENT STATEMENTS --
--///////////////////////--
LINE_NUM <= line_num_reg;
--///////////--
-- PROCESSES --
--///////////--
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 1 of 3 for the VSYNCx
-- signal controller. This process only controls the reset of
-- the state and the "current state to next state" assignment.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- Line_Cntr_cs
--
-- Notes:
-- N/A
------------------------------------------------------------------
VSYNCx_Line_Cntr_1_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
Line_Cntr_cs <= READY;
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
Line_Cntr_cs <= Line_Cntr_ns;
end if;
end process VSYNCx_Line_Cntr_1_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 2 of 3 for the VSYNCx
-- signal controller. This process controls all of the state
-- changes.
--
-- Inputs:
-- Line_Cntr_cs
-- HSYNCx
-- line_num_reg
--
-- Outputs:
-- Line_Cntr_ns
--
-- Notes:
-- We only want to start counting lines at the first HSYNCx pulse
-- we see _after_ VSYNCx has been activated. This is because
-- VSYNCx must occur before HSYNCx can be counted (NOTE: there is
-- no sense in couting lines unless we know that a new frame has
-- started - this is _most_ important for the ENAB_Cntrl process!)
------------------------------------------------------------------
VSYNCx_Line_Cntr_2_PROC : process( Line_Cntr_cs, HSYNCx, line_num_reg )
begin
case Line_Cntr_cs is
when FRAME_START => --reset the counter because we have started a new frame!
if( HSYNCx = '0' ) then -- a new frame is starting (controlled by VSYNCx_control state machine) and here is our first line!
Line_Cntr_ns <= ADD_WAIT; -- do not add +1 lines until HSYNCx goes high! The rising edge is what counts as a line, not the falling edge!
else
Line_Cntr_ns <= FRAME_START; -- keep waiting for first line to occur after start of new frame
end if;
when ADD_WAIT =>
if( HSYNCx = '1' ) then
Line_Cntr_ns <= ADD; -- line_num_reg + 1 !
else
Line_Cntr_ns <= ADD_WAIT; -- stay here until HSYNCx has been released b/c we only want to count the rising edge of HSYNCx as a line!
end if;
when ADD =>
Line_Cntr_ns <= READY; -- get ready to count another line if necessary
when READY =>
if( line_num_reg = C_VSYNC_TV - 1 ) then -- 0 to 254 = 255 lines (first make sure we haven't reach the end of the VSYNC cycle - which is just a little bit longer than the actual number of lines on the screen - TV)
Line_Cntr_ns <= FRAME_START; -- if we've reached the max VSYNC cycle time (i.e. TV) then start over!
elsif( HSYNCx = '0' ) then
Line_Cntr_ns <= ADD_WAIT; -- a new line has started! line_num_reg + 1!!
else
Line_Cntr_ns <= READY; -- stay here until HSYNCx pulse occurs
end if;
when others => --UH OH! How did we get here???
Line_Cntr_ns <= FRAME_START;
end case;
end process VSYNCx_Line_Cntr_2_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 3 of 3 for the VSYNCx
-- signal controller. This process only controls the change of
-- of output values based on the current state.
--
-- Inputs:
-- Line_Cntr_cs
--
-- Outputs:
-- line_cnt_en_sig
--
-- Notes:
-- N/A
------------------------------------------------------------------
VSYNCx_Line_Cntr_3_PROC : process( Line_Cntr_cs )
begin
case Line_Cntr_cs is
when FRAME_START => --reset line_num_reg at start of new frame
line_cnt_en_sig <= '0';
when READY =>
line_cnt_en_sig <= '0';
when ADD_WAIT =>
line_cnt_en_sig <= '0';
when ADD => --we will only ever be in this state for one CLK_LCD cycle. This is IMPORTANT! b/c we only want to count one CLK_LCD cycle worth of the HSYNCx active pulse no matter how long the HSYNCx pulse is!
line_cnt_en_sig <= '1';
when others => --UH OH! How did we get here???
line_cnt_en_sig <= '0';
end case;
end process VSYNCx_Line_Cntr_3_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process starts, stops, and resets the line counter
-- based on the line count enable signal and the current state
-- of the line counter state machine.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- line_num_reg
--
-- Notes:
-- N/A
------------------------------------------------------------------
Line_cntr_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
line_num_reg <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( line_cnt_en_sig = '1' ) then
line_num_reg <= line_num_reg + 1;
elsif( Line_Cntr_cs = FRAME_START ) then
line_num_reg <= (others => '0');
else
line_num_reg <= line_num_reg;
end if;
end if;
end process Line_cntr_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process activates/deactivates the VSYNCx signal depending
-- on the current line number relative to the VSYNC pulse width
-- paramter.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- VSYNCx
--
-- Notes:
-- N/A
------------------------------------------------------------------
VSYNCx_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
VSYNCx <= '1'; --INACTIVE
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( line_num_reg < C_VSYNC_TVP ) then
VSYNCx <= '0'; --ACTIVE
else
VSYNCx <= '1'; --INACTIVE
end if;
end if;
end process VSYNCx_cntrl_PROC;
END ARCHITECTURE vsyncx_control_arch;
| gpl-2.0 | 5559117e1eb68973c892498a866c075d | 0.497409 | 4.166445 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/pipeline.vhd | 1 | 5,007 | ---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
| gpl-3.0 | a37fb13cf982452fe4fe723306185c97 | 0.569203 | 3.401495 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/zwc_timer_test.vhdl | 1 | 67,260 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cfa40c",
3 => x"3a0b0b80",
4 => x"c7970400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80ce",
162 => x"d0738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"0b0b0b88",
169 => x"f8040000",
170 => x"00000000",
171 => x"00000000",
172 => x"00000000",
173 => x"00000000",
174 => x"00000000",
175 => x"00000000",
176 => x"0b0b0b88",
177 => x"e0040000",
178 => x"00000000",
179 => x"00000000",
180 => x"00000000",
181 => x"00000000",
182 => x"00000000",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80cfa00c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83853f80",
257 => x"c69c3f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"b008b408",
281 => x"b8087575",
282 => x"8ec72d50",
283 => x"50b00856",
284 => x"b80cb40c",
285 => x"b00c5104",
286 => x"b008b408",
287 => x"b8087575",
288 => x"8d952d50",
289 => x"50b00856",
290 => x"b80cb40c",
291 => x"b00c5104",
292 => x"b008b408",
293 => x"b8088bb6",
294 => x"2db80cb4",
295 => x"0cb00c04",
296 => x"fe3d0d0b",
297 => x"0b80df94",
298 => x"08538413",
299 => x"0870882a",
300 => x"70810651",
301 => x"52527080",
302 => x"2ef03871",
303 => x"81ff06b0",
304 => x"0c843d0d",
305 => x"04ff3d0d",
306 => x"0b0b80df",
307 => x"94085271",
308 => x"0870882a",
309 => x"81327081",
310 => x"06515151",
311 => x"70f13873",
312 => x"720c833d",
313 => x"0d0480cf",
314 => x"a008802e",
315 => x"a43880cf",
316 => x"a408822e",
317 => x"bd388380",
318 => x"800b0b0b",
319 => x"80df940c",
320 => x"82a0800b",
321 => x"80df980c",
322 => x"8290800b",
323 => x"80df9c0c",
324 => x"04f88080",
325 => x"80a40b0b",
326 => x"0b80df94",
327 => x"0cf88080",
328 => x"82800b80",
329 => x"df980cf8",
330 => x"80808480",
331 => x"0b80df9c",
332 => x"0c0480c0",
333 => x"a8808c0b",
334 => x"0b0b80df",
335 => x"940c80c0",
336 => x"a880940b",
337 => x"80df980c",
338 => x"80cee00b",
339 => x"80df9c0c",
340 => x"04ff3d0d",
341 => x"80dfa033",
342 => x"5170a738",
343 => x"80cfac08",
344 => x"70085252",
345 => x"70802e94",
346 => x"38841280",
347 => x"cfac0c70",
348 => x"2d80cfac",
349 => x"08700852",
350 => x"5270ee38",
351 => x"810b80df",
352 => x"a034833d",
353 => x"0d040480",
354 => x"3d0d0b0b",
355 => x"80df9008",
356 => x"802e8e38",
357 => x"0b0b0b0b",
358 => x"800b802e",
359 => x"09810685",
360 => x"38823d0d",
361 => x"040b0b80",
362 => x"df90510b",
363 => x"0b0bf4d0",
364 => x"3f823d0d",
365 => x"0404ff3d",
366 => x"0d8e8080",
367 => x"0880cfb0",
368 => x"08811180",
369 => x"cfb00c52",
370 => x"52800b8e",
371 => x"80800c71",
372 => x"822a8106",
373 => x"5271802e",
374 => x"8738800b",
375 => x"8e908c0c",
376 => x"833d0d04",
377 => x"f73d0d7b",
378 => x"54870b89",
379 => x"3d80cfb4",
380 => x"08585855",
381 => x"7417748f",
382 => x"06175353",
383 => x"71337334",
384 => x"73842aff",
385 => x"16565474",
386 => x"8025e938",
387 => x"800b8b3d",
388 => x"34765186",
389 => x"d53f8b3d",
390 => x"0d04f73d",
391 => x"0d80cef8",
392 => x"5186c73f",
393 => x"800b8c80",
394 => x"800c868d",
395 => x"a00b8e90",
396 => x"840c9e0b",
397 => x"8e90880c",
398 => x"840b8e80",
399 => x"840c80ce",
400 => x"fc5186a6",
401 => x"3f80cfb0",
402 => x"08893d58",
403 => x"5380cfb0",
404 => x"08527272",
405 => x"2ef73880",
406 => x"cf845186",
407 => x"8d3f80cf",
408 => x"b0085487",
409 => x"0b80cfb4",
410 => x"08575574",
411 => x"17748f06",
412 => x"17535371",
413 => x"33733473",
414 => x"842aff16",
415 => x"56547480",
416 => x"25e93880",
417 => x"0b8b3d34",
418 => x"765185de",
419 => x"3f80cfb0",
420 => x"0853ffb9",
421 => x"39bc0802",
422 => x"bc0cf93d",
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2456 => x"fc0551ff",
2457 => x"bbdc3fb0",
2458 => x"08548c3f",
2459 => x"74b0080c",
2460 => x"73b00c86",
2461 => x"3d0d0480",
2462 => x"cfb808b0",
2463 => x"0c04f73d",
2464 => x"0d7b80cf",
2465 => x"b80882c8",
2466 => x"11085a54",
2467 => x"5a77802e",
2468 => x"80da3881",
2469 => x"88188419",
2470 => x"08ff0581",
2471 => x"712b5955",
2472 => x"59807424",
2473 => x"80ea3880",
2474 => x"7424b538",
2475 => x"73822b78",
2476 => x"11880556",
2477 => x"56818019",
2478 => x"08770653",
2479 => x"72802eb6",
2480 => x"38781670",
2481 => x"08535379",
2482 => x"51740853",
2483 => x"722dff14",
2484 => x"fc17fc17",
2485 => x"79812c5a",
2486 => x"57575473",
2487 => x"8025d638",
2488 => x"77085877",
2489 => x"ffad3880",
2490 => x"cfb80853",
2491 => x"bc1308a5",
2492 => x"387951f9",
2493 => x"e63f7408",
2494 => x"53722dff",
2495 => x"14fc17fc",
2496 => x"1779812c",
2497 => x"5a575754",
2498 => x"738025ff",
2499 => x"a838d139",
2500 => x"8057ff93",
2501 => x"397251bc",
2502 => x"13085372",
2503 => x"2d7951f9",
2504 => x"ba3fff3d",
2505 => x"0d80df84",
2506 => x"0bfc0570",
2507 => x"08525270",
2508 => x"ff2e9138",
2509 => x"702dfc12",
2510 => x"70085252",
2511 => x"70ff2e09",
2512 => x"8106f138",
2513 => x"833d0d04",
2514 => x"04ffbc85",
2515 => x"3f040000",
2516 => x"00ffffff",
2517 => x"ff00ffff",
2518 => x"ffff00ff",
2519 => x"ffffff00",
2520 => x"00000040",
2521 => x"30313233",
2522 => x"34353637",
2523 => x"38396162",
2524 => x"63646566",
2525 => x"00000000",
2526 => x"2d2d0000",
2527 => x"6c6f6f70",
2528 => x"00000000",
2529 => x"636e743a",
2530 => x"20000000",
2531 => x"0a000000",
2532 => x"43000000",
2533 => x"64756d6d",
2534 => x"792e6578",
2535 => x"65000000",
2536 => x"00000000",
2537 => x"00000000",
2538 => x"00000000",
2539 => x"00002f8c",
2540 => x"00000000",
2541 => x"00002764",
2542 => x"000027bc",
2543 => x"00000000",
2544 => x"00002a24",
2545 => x"00002a80",
2546 => x"00002adc",
2547 => x"00000000",
2548 => x"00000000",
2549 => x"00000000",
2550 => x"00000000",
2551 => x"00000000",
2552 => x"00000000",
2553 => x"00000000",
2554 => x"00000000",
2555 => x"00000000",
2556 => x"00002790",
2557 => x"00000000",
2558 => x"00000000",
2559 => x"00000000",
2560 => x"00000000",
2561 => x"00000000",
2562 => x"00000000",
2563 => x"00000000",
2564 => x"00000000",
2565 => x"00000000",
2566 => x"00000000",
2567 => x"00000000",
2568 => x"00000000",
2569 => x"00000000",
2570 => x"00000000",
2571 => x"00000000",
2572 => x"00000000",
2573 => x"00000000",
2574 => x"00000000",
2575 => x"00000000",
2576 => x"00000000",
2577 => x"00000000",
2578 => x"00000000",
2579 => x"00000000",
2580 => x"00000000",
2581 => x"00000000",
2582 => x"00000000",
2583 => x"00000000",
2584 => x"00000000",
2585 => x"00000001",
2586 => x"330eabcd",
2587 => x"1234e66d",
2588 => x"deec0005",
2589 => x"000b0000",
2590 => x"00000000",
2591 => x"00000000",
2592 => x"00000000",
2593 => x"00000000",
2594 => x"00000000",
2595 => x"00000000",
2596 => x"00000000",
2597 => x"00000000",
2598 => x"00000000",
2599 => x"00000000",
2600 => x"00000000",
2601 => x"00000000",
2602 => x"00000000",
2603 => x"00000000",
2604 => x"00000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"00000000",
2609 => x"00000000",
2610 => x"00000000",
2611 => x"00000000",
2612 => x"00000000",
2613 => x"00000000",
2614 => x"00000000",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"00000000",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000000",
2638 => x"00000000",
2639 => x"00000000",
2640 => x"00000000",
2641 => x"00000000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000000",
2654 => x"00000000",
2655 => x"00000000",
2656 => x"00000000",
2657 => x"00000000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"00000000",
2704 => x"00000000",
2705 => x"00000000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00000000",
2709 => x"00000000",
2710 => x"00000000",
2711 => x"00000000",
2712 => x"00000000",
2713 => x"00000000",
2714 => x"00000000",
2715 => x"00000000",
2716 => x"00000000",
2717 => x"00000000",
2718 => x"00000000",
2719 => x"00000000",
2720 => x"00000000",
2721 => x"00000000",
2722 => x"00000000",
2723 => x"00000000",
2724 => x"00000000",
2725 => x"00000000",
2726 => x"00000000",
2727 => x"00000000",
2728 => x"00000000",
2729 => x"00000000",
2730 => x"00000000",
2731 => x"00000000",
2732 => x"00000000",
2733 => x"00000000",
2734 => x"00000000",
2735 => x"00000000",
2736 => x"00000000",
2737 => x"00000000",
2738 => x"00000000",
2739 => x"00000000",
2740 => x"00000000",
2741 => x"00000000",
2742 => x"00000000",
2743 => x"00000000",
2744 => x"00000000",
2745 => x"00000000",
2746 => x"00000000",
2747 => x"00000000",
2748 => x"00000000",
2749 => x"00000000",
2750 => x"00000000",
2751 => x"00000000",
2752 => x"00000000",
2753 => x"00000000",
2754 => x"00000000",
2755 => x"00000000",
2756 => x"00000000",
2757 => x"00000000",
2758 => x"00000000",
2759 => x"00000000",
2760 => x"00000000",
2761 => x"00000000",
2762 => x"00000000",
2763 => x"00000000",
2764 => x"00000000",
2765 => x"00000000",
2766 => x"00000000",
2767 => x"00000000",
2768 => x"00000000",
2769 => x"00000000",
2770 => x"00000000",
2771 => x"00000000",
2772 => x"00000000",
2773 => x"00000000",
2774 => x"00000000",
2775 => x"00000000",
2776 => x"00000000",
2777 => x"00000000",
2778 => x"ffffffff",
2779 => x"00000000",
2780 => x"00020000",
2781 => x"00000000",
2782 => x"00000000",
2783 => x"00002b74",
2784 => x"00002b74",
2785 => x"00002b7c",
2786 => x"00002b7c",
2787 => x"00002b84",
2788 => x"00002b84",
2789 => x"00002b8c",
2790 => x"00002b8c",
2791 => x"00002b94",
2792 => x"00002b94",
2793 => x"00002b9c",
2794 => x"00002b9c",
2795 => x"00002ba4",
2796 => x"00002ba4",
2797 => x"00002bac",
2798 => x"00002bac",
2799 => x"00002bb4",
2800 => x"00002bb4",
2801 => x"00002bbc",
2802 => x"00002bbc",
2803 => x"00002bc4",
2804 => x"00002bc4",
2805 => x"00002bcc",
2806 => x"00002bcc",
2807 => x"00002bd4",
2808 => x"00002bd4",
2809 => x"00002bdc",
2810 => x"00002bdc",
2811 => x"00002be4",
2812 => x"00002be4",
2813 => x"00002bec",
2814 => x"00002bec",
2815 => x"00002bf4",
2816 => x"00002bf4",
2817 => x"00002bfc",
2818 => x"00002bfc",
2819 => x"00002c04",
2820 => x"00002c04",
2821 => x"00002c0c",
2822 => x"00002c0c",
2823 => x"00002c14",
2824 => x"00002c14",
2825 => x"00002c1c",
2826 => x"00002c1c",
2827 => x"00002c24",
2828 => x"00002c24",
2829 => x"00002c2c",
2830 => x"00002c2c",
2831 => x"00002c34",
2832 => x"00002c34",
2833 => x"00002c3c",
2834 => x"00002c3c",
2835 => x"00002c44",
2836 => x"00002c44",
2837 => x"00002c4c",
2838 => x"00002c4c",
2839 => x"00002c54",
2840 => x"00002c54",
2841 => x"00002c5c",
2842 => x"00002c5c",
2843 => x"00002c64",
2844 => x"00002c64",
2845 => x"00002c6c",
2846 => x"00002c6c",
2847 => x"00002c74",
2848 => x"00002c74",
2849 => x"00002c7c",
2850 => x"00002c7c",
2851 => x"00002c84",
2852 => x"00002c84",
2853 => x"00002c8c",
2854 => x"00002c8c",
2855 => x"00002c94",
2856 => x"00002c94",
2857 => x"00002c9c",
2858 => x"00002c9c",
2859 => x"00002ca4",
2860 => x"00002ca4",
2861 => x"00002cac",
2862 => x"00002cac",
2863 => x"00002cb4",
2864 => x"00002cb4",
2865 => x"00002cbc",
2866 => x"00002cbc",
2867 => x"00002cc4",
2868 => x"00002cc4",
2869 => x"00002ccc",
2870 => x"00002ccc",
2871 => x"00002cd4",
2872 => x"00002cd4",
2873 => x"00002cdc",
2874 => x"00002cdc",
2875 => x"00002ce4",
2876 => x"00002ce4",
2877 => x"00002cec",
2878 => x"00002cec",
2879 => x"00002cf4",
2880 => x"00002cf4",
2881 => x"00002cfc",
2882 => x"00002cfc",
2883 => x"00002d04",
2884 => x"00002d04",
2885 => x"00002d0c",
2886 => x"00002d0c",
2887 => x"00002d14",
2888 => x"00002d14",
2889 => x"00002d1c",
2890 => x"00002d1c",
2891 => x"00002d24",
2892 => x"00002d24",
2893 => x"00002d2c",
2894 => x"00002d2c",
2895 => x"00002d34",
2896 => x"00002d34",
2897 => x"00002d3c",
2898 => x"00002d3c",
2899 => x"00002d44",
2900 => x"00002d44",
2901 => x"00002d4c",
2902 => x"00002d4c",
2903 => x"00002d54",
2904 => x"00002d54",
2905 => x"00002d5c",
2906 => x"00002d5c",
2907 => x"00002d64",
2908 => x"00002d64",
2909 => x"00002d6c",
2910 => x"00002d6c",
2911 => x"00002d74",
2912 => x"00002d74",
2913 => x"00002d7c",
2914 => x"00002d7c",
2915 => x"00002d84",
2916 => x"00002d84",
2917 => x"00002d8c",
2918 => x"00002d8c",
2919 => x"00002d94",
2920 => x"00002d94",
2921 => x"00002d9c",
2922 => x"00002d9c",
2923 => x"00002da4",
2924 => x"00002da4",
2925 => x"00002dac",
2926 => x"00002dac",
2927 => x"00002db4",
2928 => x"00002db4",
2929 => x"00002dbc",
2930 => x"00002dbc",
2931 => x"00002dc4",
2932 => x"00002dc4",
2933 => x"00002dcc",
2934 => x"00002dcc",
2935 => x"00002dd4",
2936 => x"00002dd4",
2937 => x"00002ddc",
2938 => x"00002ddc",
2939 => x"00002de4",
2940 => x"00002de4",
2941 => x"00002dec",
2942 => x"00002dec",
2943 => x"00002df4",
2944 => x"00002df4",
2945 => x"00002dfc",
2946 => x"00002dfc",
2947 => x"00002e04",
2948 => x"00002e04",
2949 => x"00002e0c",
2950 => x"00002e0c",
2951 => x"00002e14",
2952 => x"00002e14",
2953 => x"00002e1c",
2954 => x"00002e1c",
2955 => x"00002e24",
2956 => x"00002e24",
2957 => x"00002e2c",
2958 => x"00002e2c",
2959 => x"00002e34",
2960 => x"00002e34",
2961 => x"00002e3c",
2962 => x"00002e3c",
2963 => x"00002e44",
2964 => x"00002e44",
2965 => x"00002e4c",
2966 => x"00002e4c",
2967 => x"00002e54",
2968 => x"00002e54",
2969 => x"00002e5c",
2970 => x"00002e5c",
2971 => x"00002e64",
2972 => x"00002e64",
2973 => x"00002e6c",
2974 => x"00002e6c",
2975 => x"00002e74",
2976 => x"00002e74",
2977 => x"00002e7c",
2978 => x"00002e7c",
2979 => x"00002e84",
2980 => x"00002e84",
2981 => x"00002e8c",
2982 => x"00002e8c",
2983 => x"00002e94",
2984 => x"00002e94",
2985 => x"00002e9c",
2986 => x"00002e9c",
2987 => x"00002ea4",
2988 => x"00002ea4",
2989 => x"00002eac",
2990 => x"00002eac",
2991 => x"00002eb4",
2992 => x"00002eb4",
2993 => x"00002ebc",
2994 => x"00002ebc",
2995 => x"00002ec4",
2996 => x"00002ec4",
2997 => x"00002ecc",
2998 => x"00002ecc",
2999 => x"00002ed4",
3000 => x"00002ed4",
3001 => x"00002edc",
3002 => x"00002edc",
3003 => x"00002ee4",
3004 => x"00002ee4",
3005 => x"00002eec",
3006 => x"00002eec",
3007 => x"00002ef4",
3008 => x"00002ef4",
3009 => x"00002efc",
3010 => x"00002efc",
3011 => x"00002f04",
3012 => x"00002f04",
3013 => x"00002f0c",
3014 => x"00002f0c",
3015 => x"00002f14",
3016 => x"00002f14",
3017 => x"00002f1c",
3018 => x"00002f1c",
3019 => x"00002f24",
3020 => x"00002f24",
3021 => x"00002f2c",
3022 => x"00002f2c",
3023 => x"00002f34",
3024 => x"00002f34",
3025 => x"00002f3c",
3026 => x"00002f3c",
3027 => x"00002f44",
3028 => x"00002f44",
3029 => x"00002f4c",
3030 => x"00002f4c",
3031 => x"00002f54",
3032 => x"00002f54",
3033 => x"00002f5c",
3034 => x"00002f5c",
3035 => x"00002f64",
3036 => x"00002f64",
3037 => x"00002f6c",
3038 => x"00002f6c",
3039 => x"00002794",
3040 => x"ffffffff",
3041 => x"00000000",
3042 => x"ffffffff",
3043 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | d2825d8632f84b4723f4b82c2e3d9f1c | 0.592417 | 2.280387 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/mem_ctrl.vhd | 1 | 6,140 | ---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "11";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
mem_data_r, opcode_reg, next_opcode_reg, mem_state_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_sel_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_sel_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := mem_data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := mem_data_r(31 downto 16);
else
data_read_var(15 downto 0) := mem_data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := mem_data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := mem_data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := mem_data_r(15 downto 8);
when others => data_read_var(7 downto 0) := mem_data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_sel_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_sel_var := "1100";
else
byte_sel_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_sel_var := "1000";
when "01" =>
byte_sel_var := "0100";
when "10" =>
byte_sel_var := "0010";
when others =>
byte_sel_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := mem_data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_sel_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_sel_var := "0000";
else
address_var := address_in(31 downto 2);
byte_sel_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
elsif rising_edge(clk) then
if pause_in = '0' then
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= mem_data_r;
end if;
end if;
end if;
mem_address <= address_var;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
mem_data_w <= data_write_var;
mem_byte_we <= byte_sel_var;
end process; --data_proc
end; --architecture logic
| gpl-3.0 | da198c8d77ca6eb52738c889199ce19a | 0.561726 | 3.369923 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_07100_good.vhd | 1 | 3,802 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_07100_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Simulation ending: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_07100_good is
end STD_07100_good;
architecture Simulation of STD_07100_good is
-- All signals for tested modules inputs/outputs
signal Clock : std_logic := '0';
signal Reset_n : std_logic;
signal D_Signal : std_logic;
signal Q_Signal : std_logic;
-- Used to stop simulation when no more stimulus are present
signal End_Sim : std_logic;
component DFlipFlop
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end component;
begin
-- The D Flip-Flop to test
T_DFlipFlop : DFlipFlop
port map (
i_Clock => Clock,
i_Reset_n => Reset_n,
i_D => D_Signal,
o_Q => Q_Signal,
o_Q_n => open
);
--CODE
-- Clock process
P_Clock : process
begin
while (End_Sim /= '1') loop -- End_Sim is a std_logic signal
Clock <= not Clock after 5 ns;
end loop;
wait;
end process;
-- Test process
P_Test : process
begin
Reset_n <= '0';
D_Signal <= '0';
wait until rising_edge(Clock);
Reset_n <= '1';
wait until rising_edge(Clock);
D_Signal <= '1';
wait until rising_edge(Clock);
D_Signal <= '0';
End_Sim <= '1';
wait;
-- Or if your simulator supports VHDL-2008:
-- finish(2);
end process;
--CODE
end Simulation;
| gpl-3.0 | 673305def112d194732972bc4db6a821 | 0.494477 | 4.350114 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult_core_s.vhd | 1 | 28,142 | /***************************************************************************************************
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ 3 space tabs are used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This design of a parameterized real constant multiplier implements the multiplierless multiple
/ constants multiplier by Voronenko-Püschel.
/ The input signal is multiplied by the multiplicands and the result is sent to the output on
/ each clk cycle.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_core_s is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
CONSTANTS : real_v; --compulsory
input_high : integer;
input_low : integer
);
port(
input : in u_sfixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed_v(1 to CONSTANTS'length)
(real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => true)
downto
real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => true)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_core_s_1 of real_const_mult_core_s is
/* corrected generics */
/***********************************************************************************************/
constant CHECKS : integer := real_const_mult_CHECKS(input_high,
input_low,
false, --unsigned_2comp_opt
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS);
/* constants for the calculation of port sizes */
/***********************************************************************************************/
--the common output size
constant OUT_HIGH : integer := real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => true);
constant OUT_LOW : integer := real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => true);
/* constants related to the multiplicands */
/***********************************************************************************************/
--vector to preserve the sign of each constant
constant MULT_SIGN_POSITIVE : boolean_v := is_positive_vector_from_constants(CONSTANTS);
--vector with the values of the constants in fixed point (applying parameters of error percentage,
--round style and bit to which to round)
constant NO_NEGATIONS : boolean := all_positive(MULT_SIGN_POSITIVE);
constant MULT_FIXED : u_ufixed_v := fixed_from_real_constants(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
abs(CONSTANTS),
input_high,
input_low,
is_signed => true);
--vector with the left shift needed(possibly negative) to transform the constants to odd natural values
constant PRE_VP_SHIFT : integer_v := calculate_pre_vp_shift(MULT_FIXED);
--maximum left shift needed
constant MAX_PRE_VP_SHIFT : integer := maximum(PRE_VP_SHIFT);
--vector with the constants in positive odd form, ready for the Voronenko-Püschel algorithm
constant MULT_FUNDAMENTAL : positive_v := calculate_mult_fundamental(MULT_FIXED, PRE_VP_SHIFT);
constant INTER_LOW : integer := input_low - MAX_PRE_VP_SHIFT;
/* file constants */
/***********************************************************************************************/
constant FILE_NAME : string := generate_file_name(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULT_FUNDAMENTAL);
constant FILE_PATH : string := DATA_FILE_DIRECTORY & "\" /*"*/ & FILE_NAME; --comment inserted to prevent nonsense syntax highlighting on sublime text 3
file solution_input : text;
/* constants obtained from files */
/***********************************************************************************************/
--carries out the Voronenko_Püschel algorithm and saves the solution to a file
procedure generate_solutions_file
is
--pragma translate off
--synthesis translate_off
package mmcm is new work.mmcm_pkg
generic map(
MAX_TARGET => maximum(MULT_FUNDAMENTAL),
FILE_PATH => FILE_PATH
);
--pragma translate on
--synthesis translate_on
begin
--pragma translate off
--synthesis translate_off
mmcm.VorPus(MULT_FUNDAMENTAL);
--pragma translate on
--synthesis translate_on
end procedure;
--reads the number of vertexes in the solution that is in the file. Additionally, as it is the first
--function that is called in the module, the file with the solutions is also generated, or produces
--an error if the file doesn't exist and we are in synthesis trying to read it
impure function read_number_of_vertexes
return natural is
variable currentline : line;
variable currentchar : character;
variable solution : natural := 0;
begin
--pragma translate off
--synthesis translate_off
file_open(solution_input, FILE_PATH, WRITE_MODE);
file_close(solution_input);
generate_solutions_file;
--pragma translate on
--synthesis translate_on
file_open(solution_input, FILE_PATH, READ_MODE);
if endfile(solution_input) then
assert false
report "The values needed to generate multiplication/divisions have not yet been " &
"generated. It is first required to launch the simulation in order to achieve this"
severity error;
end if;
if not endfile(solution_input) then
readline(solution_input, currentline);
for i in 1 to currentline'length loop
read(currentline, currentchar);
solution := 10*solution + (character'pos(currentchar)-character'pos('0'));
end loop;
end if;
file_close(solution_input);
return solution;
end function;
constant NUMBER_OF_VERTEXES : natural := read_number_of_vertexes;
type T_solutions is record
fundamental : positive;
u : positive;
l1 : natural;
v : positive;
l2 : natural;
s : boolean; --true: v is positive, false: v is negative
is_target : boolean;
flevel : natural;
max_child_flevel : natural;
high : integer;
end record;
type T_solutions_v is array(natural range <>) of T_solutions;
procedure insert(
vector : inout T_solutions_v;
index : in positive;
member : in natural;
value : in natural)
is
begin
case member is
when 0 => vector(index).fundamental := value;
when 1 => vector(index).u := value;
when 2 => vector(index).l1 := value;
when 3 => vector(index).v := value;
when 4 => vector(index).l2 := value;
when others => vector(index).s := ite(value=1, true, false);
end case;
end procedure;
function contains(
vector : positive_v;
number : positive)
return boolean is
begin
for i in vector'range loop
if vector(i) = number then
return true;
end if;
end loop;
return false;
end function;
function index_from_fund(
vertexes : T_solutions_v;
fund : positive)
return natural is
variable result : natural := 0;
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).fundamental = fund then
return i;
end if;
end loop;
return result;
end function;
function calculate_max_flevel(
vertexes : T_solutions_v)
return natural is
variable vertex : T_solutions_v(vertexes'range) := vertexes;
variable max_f : natural := 0;
variable aux : natural;
begin
--calculate max_flevel
if NUMBER_OF_VERTEXES > 0 then
vertex(1).flevel := 0;
end if;
if NUMBER_OF_VERTEXES > 1 then
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertex(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertex(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertex(i).flevel := aux;
max_f := maximum(max_f, aux);
end loop;
end if;
return max_f;
end function;
procedure populate_vertexes(
vertexes : inout T_solutions_v;
max_flevel : in natural)
is
variable aux : natural;
variable lowest_child_flevel : natural_v(1 to NUMBER_OF_VERTEXES) := (others => natural'high);
begin
if NUMBER_OF_VERTEXES>0 then
vertexes(1).flevel := 0;
vertexes(1).high := OUT_LOW + input_high - input_low;
end if;
if NUMBER_OF_VERTEXES>1 then
--generate high values for all fundamentals but the first
for i in 2 to NUMBER_OF_VERTEXES loop
vertexes(i).high := calculate_high(vertexes(i).fundamental,
vertexes(1).high,
is_signed => true);
end loop;
--assign values of flevel for all fundamentals' parents but the first
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertexes(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertexes(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertexes(i).flevel := aux;
end loop;
--increase the flevel value of each fundamental to the highest possible(so as to delay the
--operations the most and reduce the registers used in the pipelining)
for j in 1 to NUMBER_OF_VERTEXES loop
--update the lowest flevel of the children for each vertex
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
end loop;
--then increase the flevel when possible
for i in NUMBER_OF_VERTEXES downto 2 loop
if lowest_child_flevel(i) = natural'high then
vertexes(i).flevel := max_flevel;
else
vertexes(i).flevel := lowest_child_flevel(i) - 1;
end if;
end loop;
end loop;
--assign values to max_child_flevel for all fundamentals
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
end loop;
--if the fundamental is a target increase the max_child_flevel to max_flevel
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).is_target then
vertexes(i).max_child_flevel := max_flevel + 1;
end if;
end loop;
end if;
end procedure;
--reads the solution vertexes and returns a static structure with the data
impure function read_vertexes
return T_solutions_v is
variable result : T_solutions_v(1 to NUMBER_OF_VERTEXES);
variable currentline : line;
variable currentchar : character;
variable aux : natural := 0;
variable member : natural := 0;
variable max_f : natural;
begin
file_open(solution_input, FILE_PATH, READ_MODE);
if not endfile(solution_input) then
readline(solution_input, currentline);--discard first line
if not endfile(solution_input) then
for i in 1 to NUMBER_OF_VERTEXES loop
readline(solution_input, currentline);
member := 0;
for j in 1 to currentline'length loop
read(currentline, currentchar);
if currentchar = ' ' then
insert(result, i, member, aux);
aux := 0;
member := member + 1;
else
aux := 10*aux + (character'pos(currentchar)-character'pos('0'));
end if;
end loop;
--add the last read member
insert(result, i, member, aux);
--add whether the actual fundamental is a target (which is not read from the file)
result(i).is_target := contains(MULT_FUNDAMENTAL, result(i).fundamental);
aux := 0;
end loop;
end if;
end if;
file_close(solution_input);
max_f := calculate_max_flevel(result);
populate_vertexes(result, max_f);
return result;
end function;
constant VERTEXES : T_solutions_v(1 to NUMBER_OF_VERTEXES) := read_vertexes;
--same as before but referred directly to the constant VERTEXES
function index_from_fund(
fund : positive)
return natural is
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if VERTEXES(i).fundamental = fund then
return i;
end if;
end loop;
return 0; --when not found return 0
end function;
constant MAX_FLEVEL : natural := calculate_max_flevel(VERTEXES);
/* constants related to pipelines */
/***********************************************************************************************/
--number of possible positions to place pipelines
constant PIPELINE_POSITIONS : natural := MAX_FLEVEL + ite(NO_NEGATIONS, 1, 2);
--boolean vector which indicates whether a pipeline is placed or not on each possible position
constant IS_PIPELINED : boolean_v(0 to PIPELINE_POSITIONS-1) := generate_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
--number of pipelines
constant PIPELINES : natural := number_of_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
/* signals */
/***********************************************************************************************/
signal fundamental_signals : u_sfixed_vv(1 to NUMBER_OF_VERTEXES)(0 to MAX_FLEVEL)(OUT_HIGH downto INTER_LOW);
signal valid_input_sh : std_ulogic_vector(1 to PIPELINES);
signal pre_output : u_sfixed_v(1 to MULT_FUNDAMENTAL'length)(OUT_HIGH downto OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_valid_output:
if PIPELINES > 0 generate
begin
valid_output <= valid_input_sh(PIPELINES);
process(clk) is
begin
if rising_edge(clk) then
valid_input_sh <= valid_input_sh srl 1;
valid_input_sh(1) <= valid_input;
end if;
end process;
end;
else generate
begin
valid_output <= valid_input;
end;
end generate;
msg_debug("real_const_mult_core_s VERTEXES(1).high: " & image(VERTEXES(1).high));
msg_debug("real_const_mult_core_s input'low: " & image(input'low));
msg_debug("real_const_mult_core_s input'high: " & image(input'high));
msg_debug("real_const_mult_core_s OUT_LOW: " & image(OUT_LOW));
msg_debug("real_const_mult_core_s OUT_HIGH: " & image(OUT_HIGH));
msg_debug("real_const_mult_core_s INTER_LOW: " & image(INTER_LOW));
msg_debug("real_const_mult_core_s FILE_PATH: " & string'(FILE_PATH));
msg_debug("real_const_mult_core_s NUMBER_OF_VERTEXES: " & image(NUMBER_OF_VERTEXES));
msg_debug("real_const_mult_core_s OUT_HIGH: " & image(OUT_HIGH));
msg_debug("real_const_mult_core_s OUT_LOW: " & image(OUT_LOW));
generate_each_constant:
for i in 1 to CONSTANTS'length generate
begin
msg_debug("real_const_mult_core_s CONSTANTS(" & image(i) & "): " & image(CONSTANTS(i)));
msg_debug("real_const_mult_core_s MULT_FUNDAMENTAL(" & image(i) & "): " & image(MULT_FUNDAMENTAL(i)));
msg_debug("real_const_mult_core_s PRE_VP_SHIFT(" & image(i) & "): " & image(PRE_VP_SHIFT(i)));
end generate;
pipeline_or_connection_of_input:
if IS_PIPELINED(0) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end if;
end process;
end;
else generate
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end generate;
if_max_child_of_input_is_higher_than_1:
if VERTEXES(1).max_child_flevel > 1 generate
generate_pipelines_fundamental_for_1_for_each_flevel:
for j in 1 to VERTEXES(1).max_child_flevel - 1 generate
constant high : integer := VERTEXES(1).high;
begin
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end generate;
end;
end generate;
end generate;
generate_pipelines_for_other_fundamentals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant first : natural := VERTEXES(i).flevel;
constant last : natural := VERTEXES(i).max_child_flevel - 1;
constant high : integer := vertexes(i).high;
begin
if_last_greater_than_first:
if last > first generate
for_each_flevel:
for j in first+1 to last generate
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end generate;
end generate;
end generate;
end;
end generate;
generate_fundamental_signals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant current : T_solutions := VERTEXES(i);
constant u : positive := current.u;
constant l1 : natural := current.l1;
constant v : positive := current.v;
constant l2 : natural := current.l2;
constant s : boolean := current.s;
constant flevel : natural := current.flevel;
constant high : integer := current.high;
constant u_high : integer := vertexes(index_from_fund(u)).high;
constant v_high : integer := vertexes(index_from_fund(v)).high;
signal signal1 : u_sfixed(u_high downto OUT_LOW);
signal signal2 : u_sfixed(v_high downto OUT_LOW);
signal signal3 : u_sfixed(u_high+1 downto OUT_LOW);
signal aux1 : u_sfixed(high downto OUT_LOW);
signal aux2 : u_sfixed(high downto OUT_LOW);
signal aux3 : u_sfixed(high+1 downto OUT_LOW);
signal result1 : u_sfixed(high downto OUT_LOW);
signal result2 : u_sfixed(high+1 downto OUT_LOW);
begin
signal1 <= fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW);
signal2 <= fundamental_signals(index_from_fund(v))(flevel-1)(v_high downto OUT_LOW);
signal3 <= resize(fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW), signal3);
aux1 <= resize(signal1, aux1) sll l1;
aux2 <= resize(signal2, aux2) sll l2;
aux3 <= resize(signal3, aux3) sll l1;
result1 <= resize(aux1 + aux2, result1);
result2 <= resize(aux3 - resize(aux2, aux3), result2);
pipeline_or_connection:
if IS_PIPELINED(flevel) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW) when s else
result2(high downto OUT_LOW);
end if;
end process;
end;
else generate
begin
positive_or_negative:
if s generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW);
else generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result2(high downto OUT_LOW);
end generate;
end;
end generate;
end;
end generate;
invert_output:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
signal aux : u_sfixed(high downto OUT_LOW);
signal result1 : u_sfixed(high downto OUT_LOW);
signal result2 : u_sfixed(high downto OUT_LOW);
begin
aux <= fundamental_signals(index)(MAX_FLEVEL)(high downto OUT_LOW);
result1 <= resize(aux, result1);
result2 <= resize(-aux, result2);
pipeline_or_connection:
if NO_NEGATIONS or not IS_PIPELINED(IS_PIPELINED'high) generate
begin
positive_or_negative:
if MULT_SIGN_POSITIVE(i) generate
pre_output(i)(result1'range) <= result1;
else generate
pre_output(i)(result1'range) <= result2;
end generate;
end;
else generate
begin
process(clk) is
begin
if rising_edge(clk) then
pre_output(i)(result1'range)
<= result1 when MULT_SIGN_POSITIVE(i) else
result2;
end if;
end process;
end;
end generate;
end;
end generate;
generate_output_shifts:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
constant adjustment : integer := -PRE_VP_SHIFT(i) - (OUT_LOW - input_low);
begin
depending_on_adjustment_value:
if adjustment > 0 generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sll
adjustment;
else generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sra
abs(adjustment); --to introduce the leftmost bit when shifting to the right
end generate;
end;
end generate;
end architecture; | mit | bfb35a3c242a388d2386f98260df55ae | 0.491621 | 4.496081 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/enable_divider.vhdl | 1 | 2,056 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY enable_divider IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END enable_divider;
ARCHITECTURE vhdl OF enable_divider IS
function log2c(n : integer) return integer is
variable m,p : integer;
begin
m := 0;
p := 1;
while p<n loop
m:=m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant WIDTH : natural := log2c(COUNT);
signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
signal count_next : std_logic_vector(WIDTH-1 downto 0);
signal enabled_out_next : std_logic;
signal enabled_out_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
count_reg <=std_logic_vector(to_unsigned(COUNT-1,WIDTH));
enabled_out_reg <= '0';
elsif (clk'event and clk='1') then
count_reg <= count_next;
enabled_out_reg <= enabled_out_next;
end if;
end process;
-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
process(count_reg,enable_in,enabled_out_reg)
begin
count_next <= count_reg;
enabled_out_next <= enabled_out_reg;
if (enable_in = '1') then
count_next <= std_logic_vector(unsigned(count_reg) + 1);
enabled_out_next <= '0';
if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
count_next <= std_logic_vector(to_unsigned(0,WIDTH));
enabled_out_next <= '1';
end if;
end if;
end process;
-- output
enable_out <= enabled_out_reg and enable_in;
END vhdl;
| gpl-3.0 | 63c8b414f99d58e6782c3efc55fe2b04 | 0.625 | 3.091729 | false | false | false | false |
freecores/lq057q3dc02 | design/image_gen_bram_green.vhd | 1 | 235,881 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: J.40
-- \ \ Application: netgen
-- / / Filename: image_gen_bram_green.vhd
-- /___/ /\ Timestamp: Thu Nov 06 17:02:39 2008
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_green.ngc D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_green.vhd
-- Device : 2vp30ff896-7
-- Input file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_green.ngc
-- Output file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_green.vhd
-- # of Entities : 1
-- Design Name : image_gen_bram_green
-- Xilinx : C:\Xilinx\ISE_9_2
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synopsys translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity image_gen_bram_green is
port (
clka : in STD_LOGIC := 'X';
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
douta : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end image_gen_bram_green;
architecture STRUCTURE of image_gen_bram_green is
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena13 : STD_LOGIC;
signal BU2_N18 : STD_LOGIC;
signal BU2_N16 : STD_LOGIC;
signal BU2_N14 : STD_LOGIC;
signal BU2_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N13 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta25 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta24 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta27 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta26 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta20 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta19 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta22 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta21 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta16 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta15 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta18 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta17 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N1 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta1 : STD_LOGIC;
signal BU2_N1 : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal addra_6 : STD_LOGIC_VECTOR ( 16 downto 0 );
signal douta_7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta13 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta14 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta23 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
addra_6(16) <= addra(16);
addra_6(15) <= addra(15);
addra_6(14) <= addra(14);
addra_6(13) <= addra(13);
addra_6(12) <= addra(12);
addra_6(11) <= addra(11);
addra_6(10) <= addra(10);
addra_6(9) <= addra(9);
addra_6(8) <= addra(8);
addra_6(7) <= addra(7);
addra_6(6) <= addra(6);
addra_6(5) <= addra(5);
addra_6(4) <= addra(4);
addra_6(3) <= addra(3);
addra_6(2) <= addra(2);
addra_6(1) <= addra(1);
addra_6(0) <= addra(0);
douta(5) <= douta_7(5);
douta(4) <= douta_7(4);
douta(3) <= douta_7(3);
douta(2) <= douta_7(2);
douta(1) <= douta_7(1);
douta(0) <= douta_7(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"C65BF1825AEA49D64E8911080801FF0B820843E78E97F6220000000000000000",
INIT_02 => X"C1D167FE7F57FCDC9BF27FDFBEC1026015E4E5FC803FEB525D78380C9307DF90",
INIT_03 => X"B00E83831A923B1874199EFDF9FE23D562086C80C85ABC16CBE30F94D64C95F7",
INIT_04 => X"363D04B25C5C03C2F7DE339F6314B370F3909CDA13A39BF1C1E0BC87F3931CF9",
INIT_05 => X"97C059D19FA05EADBB7FDC204E07F6ED64E3D381CE7F1FBFE36E83811850E2A0",
INIT_06 => X"CB7BBEBD46B3DE8F8C82E481723FEFBE300172013FF140764180DBB087001ACF",
INIT_07 => X"348896E26BBA71FEE2053F000D25AE4A7E75B250B14A115517385E4F81A514C1",
INIT_08 => X"CE0E7018EE1CF88A0727713AC79215F98321311CF7D7F8201BE106747205F849",
INIT_09 => X"3D758B6E04B9CD08DC3F6E7AF837B2C61C02C08E3EF79E4EDD7174F077A08D7C",
INIT_0A => X"7ADEDA0182E467E3135971402A35888DDFF5E199FF4BBB7FF91F77E0DFAADE9A",
INIT_0B => X"277A9C07300AD503CF5C469F2853DF7FF51F77E08B4BAC2A652F86063A23E97B",
INIT_0C => X"D993A41F47633D7FF01DC7C02985403C5249DF05833BFA166BFCBA80CF9FAFFE",
INIT_0D => X"FFCD83C073F93CFE0354F3DFFDF3FFB10BFF64FF0A60954CCD77D8E1C7864551",
INIT_0E => X"54316F0B8BA5F9090F02FE03B22236DE81FB5DC062552A43756E021F406C3BFF",
INIT_0F => X"00FF5E7CDF0D2E8EA955EEC7E58F1100B12D83FFED657BFFDAED030033FDFBFE",
INIT_10 => X"0B1ECD033F884A2668AB860E715DFB3FD66D70205E41F1FE6BE92EFCF2A73D0A",
INIT_11 => X"0D5344C4B88EBC33C52DFC00765EF1FE7B0D4B8425103FFE008080FE1908385B",
INIT_12 => X"5414FC00A99137FE7C05D15005FA3F4600801FEE3A511321948D0B1CE31CE914",
INIT_13 => X"7366360C0BE5DF3A41064EEFCB681D8BF1E9593F6188DE43684D23DD008F3A3B",
INIT_14 => X"CABE80FB5BC2BC45E44DB2F1E210D222EB7FC6455764707E4090C14FD9123F7E",
INIT_15 => X"E872099AAC3690E56A686D615EDBF77F7EF7C7E91BDBBE7E7E9153247D2EBB8E",
INIT_16 => X"F8FE6ED94594F8FD4D5D0F657F21BE7E375D469AA07C56F9389F80813DACCC99",
INIT_17 => X"4F621F1F7CFD1F7E1E27D3D6BF5F03F05C1EFF8E0661E6E2F31506731151A4A7",
INIT_18 => X"7C2951EFD33B6DF41E8CFFCF7186FEDE772B0ACD53C216292342BB5AC7D2A67C",
INIT_19 => X"A8C07FCCEB9C7F6709FC8D5D96EBE8710509237B84A225FC50DABFF6DE715D7E",
INIT_1A => X"F42BAFB924BED9AB374A5A2838C728FFE964BEFD3BFF6CFE7BC09CA44092EDBF",
INIT_1B => X"24CB54D13A4E7AFFEA0E80722FFD90FE7FF8B2148081A00D9C001FFB6536473B",
INIT_1C => X"D0CF81D59DFFA2FE722B0B21009DA06DD98007FE2F9D7B7C7033FE1D5A583CE3",
INIT_1D => X"5ABDD6962EE0259FFD4302FCBD2BF15EB02FF269916F3AB0363C7515F6DF15FF",
INIT_1E => X"4950AF67BD1C97594146F115360DFC4407B14FEF350050F7D5C181807DFFE13E",
INIT_1F => X"8B96E6EB38F85B8B904F56DB2DD6A0FFFD8E5F8B3D1AF83A73D7846122078EAD",
INIT_20 => X"DACFE37B0D9009FF7374415C7C5CF73A7FFAC0FC1EC0B436B0B99FCF77E5F04D",
INIT_21 => X"D4DCB64BCFAA4CBC7FFF95232E2F1ED72574BEDE3D1988F738FAA7F915B6F044",
INIT_22 => X"7FFEDA603E4F81F09B1421C13BBD5F8426296BFF505277D8F303B7FBE569D13F",
INIT_23 => X"776CD33F748A1DFD554AEBFFF5DE2C00603477702E23323F0538BCB147C460BC",
INIT_24 => X"1D4DADFF18D99DADE5795D417B5ABEBC2FDE850647EDAEB67F7F26747426DB53",
INIT_25 => X"817B9BF955779FBDD5565A09FFD78B367F7FF7C864F4673AF56720E05828A38B",
INIT_26 => X"BA8C62D3FF1F25F87FFFF6D0E656E6E54115FF51C10DE67473F30BFE8AB54C00",
INIT_27 => X"7FFFC3BF766476BD059403EAED015C87328F8817830D87DBD91A0F2B90959F3D",
INIT_28 => X"B7DD7740D006CB9A42B272F7C05F744FEBED711411482FFAD891DA45FB91183C",
INIT_29 => X"983986C7389FB43CDD8D6C0DDAA317F9EB7F301DEAD85F8A67F091A70591A18F",
INIT_2A => X"812D8AEF32BA1FFB93E7354FDB4528C67FF777FB178F18E788499EA458594593",
INIT_2B => X"02E6065FA638D7C27DB04A3FE2636EB6E6851DDC5DF6A290CAEF0F95F9BB657C",
INIT_2C => X"4FF57EFCD40784167FAB7E15C81A52EC6636C3E7A0549A1FE31BFDF478710FF8",
INIT_2D => X"0FE2C482BD74870F92BE436E16993EBFE3E1F49F5C50EFFFCDF93E1FADFD0A7A",
INIT_2E => X"93BF40C7FB7F527FCCB7BFF8C1900FFC71FF07BFC180BEFA5C7BA49ED925B137",
INIT_2F => X"C1DBFDE63D51CFF513F0C5EFE04AE0325ACFDAE000957DB23FD50CC50236CAD0",
INIT_30 => X"2FF8F69F6718F5866CB2E4EF688B3438BFAF82F0B713E730D4C1563C83EDC0E6",
INIT_31 => X"41E70BC861D1ED3ABFF5DB52EEF6B0457B2569B7439F87FFDFB0FEF4C9BAEFF1",
INIT_32 => X"7FFDEFC4458E886C7FF2A43A4D9DBDC7E41A73555F7ABFFAEDE6A38F3C09FFE2",
INIT_33 => X"53C81752F1033FCBEE9BC6FCE390BFFA2EBD3CA460707FCC6EB57961E1958AB0",
INIT_34 => X"8B8DF75F19263EFFF6DAFCC99B6CFFBA41865147EFDDC73B7FEBF3CFBEBFE8BE",
INIT_35 => X"DFF0EEA5C44BF7E8386CB004F9D5F8A73F2FF6C7A33FE45FFDCF5F58FFFCEFCF",
INIT_36 => X"5DB47F9700DBF97FBE0713B120F97A7399472AF67F7CBF48000821FE15DFBEF8",
INIT_37 => X"1FC003B677623AAB72C97B9E3FDF4FFEFBC989706854FC7C1BB17CF8CB30E3C6",
INIT_38 => X"CC4C7767D7BF736216F3027EC662FC7D0AD9BBF7C335E3EA3A9A7F1162C28BC7",
INIT_39 => X"AA1F85FFC2B1FE7D673D71FFFE4BCFF045E13F9721A75B988FAEFCC78626BAF0",
INIT_3A => X"6FFF3BF7D1528F1A3098AF5A140D07F1AF87FFD29E1FFC0BFB1F6B72031D86E6",
INIT_3B => X"0A93FD2FC537898BF7D8FFA988D5FE22818DA981956DD947DACDB0FFD9517CF8",
INIT_3C => X"679A3FCD8EEEE35E76A2A060A7B8406FFFDF7DFF27977FFE0D7F1FF3D48D0EDE",
INIT_3D => X"F200E4A4C156307FE8C897FFA6E6FFFE37C737C7B4F70E5871938E7494E89680",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"C80EEFFF70317FFC6EA033E7923FF8845C6D5820878FB58ABEC3EFD93C64DA70",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"47B3F9EF5C6FF8F82A7C5DED86F1CBC88CFAE7E07846FAD8FEF3C745511FABBF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"318F4AE23407009620FFABFF963BEBDAF91B20D7CE2A9DFFCBB11FCF93E47FFF",
INIT_01 => X"E01E7FFF20778BA3FD87710F36A387FBEA02EF8FF26FFFF979215DFFD17DF978",
INIT_02 => X"FB6CBE00642ABFFF184B1E0FF648FFFFFB77C3EF16BDE75C0FEB1B82F84C8D96",
INIT_03 => X"51F7BE0FFC81FFFCA3000FED653FE91A3EC76B0B54A08E8E3A0EE7FFB3606B8C",
INIT_04 => X"86617FFE19BFFA407DF1C9BAB19CEF4CCBF9AADFF2EC67CCFFFFBAB70A283FFF",
INIT_05 => X"7D6EE646C7313F806DAE7D5FBA85CFC0F7F261280665FE7FFD7B3FBFF0F7FFFC",
INIT_06 => X"8EF4725FFC255FC4E7E18BE569E7F8FFF53B7EFEEDE9FFFB1074FFE4EA7EED64",
INIT_07 => X"63F434F5FD73FFF1F5DFBFFFE877FFF0D27BFFF688FFC2FA605395C9111D5787",
INIT_08 => X"FCBA7FFFB5AFFFE33205FFF610FFBCAE69A3227C401F37E349938FF1FE4FAF9A",
INIT_09 => X"8187FFF452FFD31C0BC9275A4E31921B8D6B5BF8FF0D751AE3F7AF8821F51FE4",
INIT_0A => X"32D0215D77AAC66F7DD446FCFF061A8673E371ABFD3C1FF5EAF87FFFD777FFF8",
INIT_0B => X"97F94B7FFF1C284773F9B5EE7BF98FFFF8FF3FFC263FFFFB25D7FFF3BBFD28CE",
INIT_0C => X"F7F18EDBA7FE6FFFDDFF3FF5617FFFF8A953FCF65BFE547050761AB0BB7DB45C",
INIT_0D => X"89C931E06D3FFFFA41C3FCE57FFD8AFE64180199C349D7FEAF42803FFFF5360E",
INIT_0E => X"1146F87ABEFF515E310066F7E80D24F4F0E981BFE1FF67347FB72CFD8088C8FF",
INIT_0F => X"660BE5988A5428FDEFBC3A47EEF8A6673FF87384DE0E03FFF7FBF3E253BFFFFE",
INIT_10 => X"3C555C53F7F91CC07FFCFF8845AEE0FFC7F33FFEF9FFFFF03266F6FF98FDD252",
INIT_11 => X"7FFFFEE70D2E8DFF73FFFFE392BFFFEC95DFFFC9F97D98C2671C99C153D089FF",
INIT_12 => X"5FF7FFF1C73FFFECCB1FF1E8FEEC36E67903F97F919C7EFF1EC95E5CEEFCEDC9",
INIT_13 => X"1BBFF3EB3FE8C5BE67FC871379C1E7FFFFA1214D687FCF8C5886FD2AFB284CFE",
INIT_14 => X"6C417FBC824AABFFFFA01C0D943FE2128E7FFCDEF0B07C7EF7C3F1FFD8FFFFFF",
INIT_15 => X"FFFE93B0DFCFDCB9536BEF2E0B144C399FC7F8FF443EFFF127BFFFCC3FFE717E",
INIT_16 => X"0B07C7D2384EDF6D3FC7FF7F3EFFFFC2DF07FF4EFFE5377E566E7FBE337D31F3",
INIT_17 => X"3FCFFFFFF57E7F97FFFFFFC19FE38F7E5849F7DFEE7EFAFFFFFFF87A17FFFEDB",
INIT_18 => X"FFFFFF291FCBDFFE105501F0A6DB983FFFB7EF9A2FFFF92EC24FDF898187F677",
INIT_19 => X"7FAF03F70F8341100F0FBED0DABCFFF4787F3FE34F87BAE37FB730FFEBFE7F93",
INIT_1A => X"6C0FFFFB262FFF97FE2EFF3A177FEFD0F1DF3DBF27FCFFE4FFFFCFE95FD38FFE",
INIT_1B => X"0537EFAE4E1FAEDB33EB6ABE17FEFF10FFFEC619D3DF8F7E7C6685F50F8A418E",
INIT_1C => X"EDF331BF3BFFFFE5FFFC45E3FBD75DFE0591A1F19FFF7AEFE007FFFF57F67FD7",
INIT_1D => X"FFFCEB1552D4F9C44818078EFFECD4A16FFFFFFF3AB2EFF0086FE43356E7CEF3",
INIT_1E => X"17910381FA1BC26F47FFFFFEB9F337875435F9100A7FFF83F84E24FE67FFFFEF",
INIT_1F => X"C3FFFFD9FC6DFFC96878FECB361F7EB7FF1B35F547C7FF6EFFFF78317AEDFFEE",
INIT_20 => X"749DFAAD72355FEFC10F6075B7C7FFF7FFFFFED4F18EFFA641B0DB317019284A",
INIT_21 => X"E10073A1AFCFFFFF3FFFFB29392E9F5E4B434724001CA359D3BFFFDFFF5E6EF3",
INIT_22 => X"1FFFF8C1F9AF9F3A1C95140F4060986B0E3FFAEFFFA7BAFFDBFBE7DABFA03BC5",
INIT_23 => X"4D6589590766E5A18FAEFFF3FFF5E68FFE7EAC167BBEE5B0CF7CD420FFD7FF9F",
INIT_24 => X"342072736FF03013FFF5DE0A38EEF3CFDFE3756CDFC7FF7FFFFFFA8EF3FFFA12",
INIT_25 => X"FC8FB33D740BFFEB8F90E605CFEFBE3FBFBFE6FF7FFE4C6A03D384C78CFD1331",
INIT_26 => X"8873267B3FEFFFFFFF3FFCBFFFFC2B844212D4E3357E492BE643BC5B5FDFCE15",
INIT_27 => X"FFFFD8DB7F62D0DC180EF7019600D8FCAD4016F7FF1FEE387CC7E64ECE29FF0A",
INIT_28 => X"6414AFFFB46EC208721D22A3FE1FFB948C79FEFCB916FF34DDA7C3E53FFFFFFF",
INIT_29 => X"0C870233F67FFCAC47E7FC424379FFBE71CF83FD3FFFFFFFFFFF837F47DB36A6",
INIT_2A => X"E727FDF62DFB5F7CF5D587C05FFFFFFFFFFE3264DB9163CE691E61FBC846F827",
INIT_2B => X"D56FC7F0BFFFE3FFFFFD85D0E7EE9BC051FF7DE03668A268F38C25ABD9F8FE2A",
INIT_2C => X"FFFC7ED7FF7633FA790EA600EC752C41E16171F151FFBFDEAF40CBF746F5CF2E",
INIT_2D => X"65F3DEFA1D19AE1CCF6828714AFF3FC6175B19F89379174ADFBD4FF4C7FFFBFF",
INIT_2E => X"5A6CFE8E1EFDFFE82DBFA5E00FDCB155A0A6A7F03FFFFBFFFFEFA1EBFFDEF7FE",
INIT_2F => X"224BDFEA8A72937B235C5FBB3DFFB3FFFFF1BDBBFFDD5FFE17877FA3D4150762",
INIT_30 => X"8D1CBDDA9DF87BFFFFE61647FFFDF1FE420FE747E7B886535376E91353BFFEFE",
INIT_31 => X"FFD4DE03FBFDDDFE7EC783E17ADA373555ABD5C97893FFFF825818690EF1FEFF",
INIT_32 => X"58C06760B98617AD93A6AB85A517FFFFF0F4909493953F3DD67FDDDEDDFB67FF",
INIT_33 => X"9B58E4D109F1FFFFF81C55E473F4B27CC97A3040DCFEFFFFFFFA9707FDFCE1FC",
INIT_34 => X"FF5996B70C9A7C3D2BD10FC2BEF3A7FF9F66BF7E3FFFFFFC07C0FF8BDC30A60F",
INIT_35 => X"ED1DE835F8F553FF9D3EFEFEBFBF7F8E0B00FFC502D69E4F41F4D38680789FFF",
INIT_36 => X"F8E777FF7F0FFF0E5040E17CC2E804B876E7CDE48096D3FFDBA89C0C5CB3FA64",
INIT_37 => X"6041FA77BDC3863913138036BE934BFFABE6CFF0068662498570254BFCFEEFFF",
INIT_38 => X"3C6E4E18BD9F0F8763D2C8147E278DED63A2B9BBFFB39FFFF11FBFFFFFFFEC7E",
INIT_39 => X"A861670CC49F21FEA4B51305BEE566FFE7BF3FFFFFFFEEFE2BCF72FFBFB73208",
INIT_3A => X"F8BCBA14FE517FFFE67FFFFFFFFFF3FE35E0FF82BBA525B714424734FA811B47",
INIT_3B => X"A23FFFFFFFFFFFFE05FF00FFA9DAFB2B44CF33DC0BDF63872E32686991503DE3",
INIT_3C => X"75730010B5E96ACD8EFD0925784C4D5F4FD00BFC8684E201BA5D56157F6C7FFF",
INIT_3D => X"F04F5FCD311C6149679EBE0AB9847A4CA2B5D859FF477FFE7707FFFFFFFF3FCE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"DFF3B10759DB900A5C17EA55F238FFFF936FFFFFFFFFFF8E31630F038E0377B7",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0BA4645DD6EDFFF5899FFFFFFFFFFFC6757E0F02DCD71F1FFF9255323C764F49"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"DFFDFFFFFFFFBFE20EF30FEF41A6E9BFFFF4D4F5501A2F50EC2AA6B30AF3AFD1",
INIT_01 => X"3BE787FDAD41FF9FFFFF27FCFDDB6253A15C4F7765371E27BAE33315507BFFDC",
INIT_02 => X"FFFF8BFFFFB3A22E408C9FC46A839FAEB0166AF509EBFF08D7FD3FFFFDFF3FF2",
INIT_03 => X"0FCD80A80A7EC592B9E8362FE7E5FF501FFCFFFFFFFF7FF830678369C78FFF7F",
INIT_04 => X"F5F77A662711F7037FFDFFFF7FFFE7E078E6704653EEFFF1FFFFBFFFFFECFBE8",
INIT_05 => X"FFFFFFFFFFFFEFE64701F91B169FFFFF00C5FF6FFF1CEE4BCCF383649B730437",
INIT_06 => X"001F84CCB7BF8FFFFFFFFE97FFEDBD0807390EE1C8DD0F4AB44C1FE87B3FC242",
INIT_07 => X"FFBFFE77FFF07F5662083CB69744AF4757C9DA15F15FFDFBFFFFFFFFFFFF8806",
INIT_08 => X"E5A3776F2755825ED7F9098F2C07C4DFFFFFFFFFFFFFDC9A50B800B0E84383FE",
INIT_09 => X"64395BF75D2B933FFEFFFFFFFFFCFEEE409882AF0269FFC8FF9FFFFFFF31FED6",
INIT_0A => X"FFFFF33FFFFE7D1840C7F779D38FFFBC460F3FFFFFFFFFE5AF7BE7C05A181388",
INIT_0B => X"00F352F635D326D66A37B1FCFFFFFB427F3FF66C586B688EB977F2A9F8A2E3FF",
INIT_0C => X"0D19CF8778FFFE97CDE4C847744EDD450E205ED0356121FFFFDFFB3FFFFF02A0",
INIT_0D => X"4E209FC349F1904AF6C9B3AFDFAB1FFF7F1FEFFFFFFEA5FA06DBF70B0BD8C2FB",
INIT_0E => X"4428DEDF9DA87FFFFFFFF8FFFFF1984C1AF4F2F2E3A715AF8D94262A3A2BFF39",
INIT_0F => X"BDF1FFFFFEE6D110271DCB965372D099380843CB8BBAFFFF98D43E130ECAA9E5",
INIT_10 => X"629D3763736A602C1B1B6EAA9579DFFF33C5CE81E133209950456D571C4CFFF3",
INIT_11 => X"FCD61E26AA27CFFE82D5C280E65B83892CF8D8B7BF2BFCF3DDD53FFFFFEFAFEA",
INIT_12 => X"CBBD831FB4A9D785E698CC39DDAFF6ADE32FBFFFFE1FF86A037AFA4EAF15E879",
INIT_13 => X"643A4EBFF0FFF1208C753FFF183FE0643D9613248D68453F00836D131FFFFFFC",
INIT_14 => X"5766FFFF403FC94C2608864A963697F81CEB31CF9FFFFFFBB54281C6F670D462",
INIT_15 => X"1A88CE6B8F8BB7CF9F7E82FFFFC1FFF725F2C3F0F34E9BF049B8743F17FFF2FA",
INIT_16 => X"FDB1FFFFFFA2FFFA696B4EA3ACC58C55E82ED9DC8BF53ECEAB83FFFF59C02374",
INIT_17 => X"DF598CD981F37430DEEF9FF907F7E094ED5FFF7F1FF71CB82C90B476E0E63DF9",
INIT_18 => X"813DFDA67FD0755E6A07FFFFFF87DC70283B0F9D00135C39BB9FFFF8FF997CF4",
INIT_19 => X"083FFFFFFE9FAFFC73FF519343DC629655DFFFC0FFFFE0E616B18E78A297BD39",
INIT_1A => X"689E7A77C25CF8431A7BFFFFFFFFE4848D61DE70145A828AE83524D5FFD46BFF",
INIT_1B => X"F2C3037FC13F7A883FACF269BE0EED504908DC76FC9025640BDFFFFFFD45D8BC",
INIT_1C => X"8EA1F20F2F9787452C9E8F8BF37495B73C7FFFFFFC20A1D67FECBC00DA0CB46C",
INIT_1D => X"D9BB9D8FE0C308092DFFFF7CF1BD7EF67FCFC64CFE1C8EA02FF100FFF03F1F57",
INIT_1E => X"A17DFFF1B9D055607F632C00F85C70DEFFFFFFAFFC00FCAA2CB31AE18E3FB71F",
INIT_1F => X"73DE3596D5247EFFF9FFFEB2F1D55757747C9CF973EADDE01CFDB79EC7A43683",
INIT_20 => X"F7FF3D234B114879FDC8503BFF007BFFAECBFDDFFE91BD75E878FFEE817E76F2",
INIT_21 => X"FD7DD14BA3EE5BBBB19F49EB188C81C002FFFF00FFF1FDF87F4596D3ECAE749F",
INIT_22 => X"D64AAFF770C5A2FEF7FFD44A99B12E627EFA765C3B83BF5FC1FF3DE0BE7E507D",
INIT_23 => X"97FE98292A60F87C7CEA1493CF0FBF8FC0FE7521F38EF0FFFF966B436A14FB45",
INIT_24 => X"6DE7EBAF2110C767F87F2D8AB1705DFFFDF47465D90D44CB2E695FFE63D7219A",
INIT_25 => X"F7EEDE8528577FFFEAC14935283B2A7E9164BFEDB7C375AFFFD54654DFFEFBFE",
INIT_26 => X"E7F635CC9C1C55ADFE09FFFB3A53101FFFD2DF841FCF3FFE45592E93DA638A21",
INIT_27 => X"B7E2FFFA9F47F15FF8F930579FEBF0BE64CFE53F54E02960E9F6C6FBFB59BFFF",
INIT_28 => X"D20F70FFCFFFF1BE104C08DD874EAF37F49D1D3181637FFCB3FC231BD30B059C",
INIT_29 => X"11828E894F41ADF54B3C98DDFB91FFC0D0B217552A670CE5B793FAE4E9A7C0FF",
INIT_2A => X"B96D58824BE2FFFB29F9DF4865567A2A0665D54FA31F8DFE9AEA69FFCBFFF0FE",
INIT_2B => X"F0F2958EAD5FDF5AFF4E9239CBFFCFFDACD6C7FFC9FDFEFE5DA67862C9ED25A3",
INIT_2C => X"F8BAB4298EFFFFC36B46DFFFF3FDFFFE0971FE23CE1A54854109A7FB4BFC3F98",
INIT_2D => X"19EBFFFFFFFCFFFE5AE2EF6AA84EB332BDB8946879E0DF8E83C7CC524E17EE1D",
INIT_2E => X"1A9145C7E9AE69DEE1023B1FAEDF1FEF07F7FE91B2AFC3BCBF5B83B82D7FEDCE",
INIT_2F => X"73B0E3504F7F3F8C67EFDE4085FFA752BCEFA2BC4EFFFB3FAC8DFF9FFFFEFFFE",
INIT_30 => X"FFC7CC3FF529B99AF8932BD33BFFFF46A6B0BEFFFFFFFFFE551A805ECB309A24",
INIT_31 => X"1F5E2E3EFFFE9E49DFB4B3FFF1FE3FFE712EC35736F4F492E67BB1C64EFFFE6D",
INIT_32 => X"FD8A9FFFE37FBFFE7E80E469A8718EDDCD3F6516533FFF8BFE85FF3E9E726106",
INIT_33 => X"1F3EF7888CE70E154FC454636E7FFEDBFE57A37536CF57F7029AC4F3FF4203B9",
INIT_34 => X"10435E5BC0FFF547FE6FF374BF27E78A9F3427FFFCCCBD95FCB8F1DFFF3FFE2E",
INIT_35 => X"FFC7D76CA14D7B8D003F8FFF7F36038EF8C67F0F3F3FFE1E7BC09919D3C921E4",
INIT_36 => X"1CFBED381108DFBE2D8C67FF3F87FFFE7E54A383C3E6B674A5034FC226FEFA5F",
INIT_37 => X"64890FFFFFFADFFE37D0C911C437BD83BC9B0FF4AF3F88BFFFE7B3693D0AE830",
INIT_38 => X"45F12880FDA812BF7D80A7FB7F37C9BFCFF721AA0E68D02CDD2BA97FE392BFF5",
INIT_39 => X"84198F77FFAD51FFC7FFB36DEE16920DD9C81654854EDEA9666D0BAEFE3827FE",
INIT_3A => X"C7FEE2C95347787BC38523D7F6A09F2B83DE458FFF070FFE6136F75C7C2585B0",
INIT_3B => X"037F22E7CCFE5E9E5C217FE95FFFCBFE4346AADB1B04CDB8E4E7FF7FFFB13FFF",
INIT_3C => X"FFFC02704FFFAE7E4622AF048AAFF600209EFE7FFFF063E7FF7F3E1A6287A2B3",
INIT_3D => X"50281183DBCE801E278FFF7FCFE1ABA7F0FFE76DE8CF63238ED997DA1F319FD5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"027FFFFFF7EAAFAFF16CBE6BC30FC023D2C1BAFCC42B4EAD99A5A394EFFFE7D6",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFE1002E9119ECD8547247ECF493703A55FDB09BFFF437A34F70BC34DDC5EE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"989BC8BEAA3AC56D387307616FFECF623CDE0110B945D82967FCFFFFCEB5BF8F",
INIT_01 => X"FF4364FB0F7E87D227ED03FF9736DFD98FFFFFFF7ECC5FFFFFF43EB73D2BB4FE",
INIT_02 => X"64E584E10EDF9AD63FE99FFFF8BFFFFDFFF0BEA8DEF0C2C1195A59FA847C1B2B",
INIT_03 => X"FF153FFFBC98FFFCFFFB3EE89D332D222B8774992E706FF9FCBA636AFFFC98B0",
INIT_04 => X"FFFB9ED9FE58A020E8FE95ECDB34F1EAA2892143FFFB2F926F4CFE2AA681E889",
INIT_05 => X"FFF920AC810219790D21C607DDF9993A72D5FB6F0EED0C0C7F18CFFF169593FE",
INIT_06 => X"01F40D4CA9BF2B161FAFDB08D23836C6FF528BFCB0D7E9FF7FE90C1D74F0F379",
INIT_07 => X"61C30682B3EFB63F1EA1ABFCC4EDF0FFFFCA7B0E263C8C7A22E3B3BD96FB2EF6",
INIT_08 => X"97AD4FFE5F53FFFFFDC0FFE530C9F5F525C2223DC6BE52E428D0EDAFC13C2B1E",
INIT_09 => X"FCA73C8D5A82BD0A47777C4210BF21AFFE20AA5FFF0788967280796F5EA86D3F",
INIT_0A => X"84798A8A39ED22C46723DC3FECA58F462FE3000BA4EBAFFF1E981E7DD89BFFFF",
INIT_0B => X"8D29B8F814DA9CFC26B3352401BCEFFF52711FFE23BBFFFFFC1FFCC1AA6F971D",
INIT_0C => X"67188DAB415BDFFC4E593FFBB33FFFFFFEE8FCCB9B72BDF417EE5317FBC3FE85",
INIT_0D => X"8F2E7F3A8DBEFFFF3FE1FDA11E6205BBFBB36B7374FD4AF7F49A61E7D71F7FE2",
INIT_0E => X"3F08FD512F3DD179E537423187973D7A4A067BC081BDDF8A1EE7FD77FEBEEFFA",
INIT_0F => X"5D6AE49511016C7D4E87AA0394BFFFA03DA7B59216566FF666D87F67087EFFFF",
INIT_10 => X"90D41200DFBBF878240CC94A18587CC7531FB91ECDBFFFFF3F0FFDDD0E1BAEFD",
INIT_11 => X"7491607D4E66EABE93DD77577BBDFFFF3E2DFCB5B266D3F83455E08B51FA0177",
INIT_12 => X"784FB287ACFFFFFF3D8DFEAAF2031FBF1CE9DD40D7C70357DB8A087F9EFF7EE8",
INIT_13 => X"BE77F90F25CC291E9459FD1025D1F66223DCA59FF9DFF75A5CED4CDC6576220F",
INIT_14 => X"017FEC91C8E8C915CE38F0C7F02EE7F679DDCDEE8F9299A2DB38201F517FFFFF",
INIT_15 => X"4BA4B0DFF37EE7D62EB8C89EFCA8E1174968AE1B0EE7FFFE74D7660065B4D70F",
INIT_16 => X"3F166BCF3C11CE5BE8CDD20A23E37EFFB95F7B9D89BA67CED15F69DC908F199C",
INIT_17 => X"7D682BC64FE728BFB457EB994FC2B9CE8C13F2C4A9248390F7CE8B7FC45FCEF2",
INIT_18 => X"9CAE9966E22A71FE4E3BBAFD8DB16281721DC5E7C94CAFAE27FDF65F79A430F7",
INIT_19 => X"24D3FBFD8563C7F06A7696F7F5D56CBA723B8F9FE01796FCD32041C497EF3E5F",
INIT_1A => X"8EFEE0377B066F52423F1EE7EC33A970C7586FCD2FFF134CDBEFA2736415F2FF",
INIT_1B => X"3B283F0DA5084DA371E6D2275FFDB14BE4A7E982741C19FE0230BD4BF65DD516",
INIT_1C => X"C1E0341FDDFF7EBFE35325BC671DDFBFD961A26C1011AE73927EFB6E9E7F27FE",
INIT_1D => X"A113C87D4EC9553FB075EC2F163AF6F8DFCC684533FFDBFE2673FFFFCC258FAF",
INIT_1E => X"B979EF88B4BF9FFE69827B43D41FDBFE645AFFFE4A212EB37CDC3BC9B8F4C8FF",
INIT_1F => X"90A761D6E7DFE7FE46F7FFFC05D82C1CBEA819547FE41DFFE5A3D6B0FF0E1F3F",
INIT_20 => X"5C6FF7FBF0305135BFA0E095FF8A8E7FCF67DB705644D1FFA043F3086E5623DF",
INIT_21 => X"7FBCF8F7BF5743FFC8DFF34B5296F07FFB03FC5263363FAFEA5D35A7BE15FFFE",
INIT_22 => X"CB7FE069EA2D36FFDD33FB21CCEB95DF781AEDCDC7C3FC7E539FA7F6E47604CF",
INIT_23 => X"D124FF28702093BB1BC41C9EBB1FFB121A57F7C09D8217C1BD59C53F3F5E7FFF",
INIT_24 => X"48FC52663C6613AA6FFBFFC26E86C9F6FE77A7CAFF46A0E7FCFFDE6C9CD2D77F",
INIT_25 => X"2FB1FFCA49E798DC329E75A5FE3B6AE7F7F6BB0CD6278B7FAD62C4EF306D4783",
INIT_26 => X"4B6A6E6FEE2E87D6F8F5723C9070B4BBFE2A6918F0A89C58DD36A3063FF7FF32",
INIT_27 => X"ECFB055E06735B9FE385C9EAF7E9886470AB0410FE9FFDC6417FFFFBED396F1A",
INIT_28 => X"E263CDDE9730364EFACD5C9B3EFFFECE73FFADDF681ADBFD91236C7FFB2DBEEF",
INIT_29 => X"FCB36ECA478FFFFE7BFFD6F6D2E30BF047F5421FF3F57BFA02F6E0F6F5B34D8F",
INIT_2A => X"7FFFD011D74572A0B11E81B7BA49A5B86CE08BCAEC01723DEC09949E97FC4DE8",
INIT_2B => X"CD2B72FFF461593E25ECB42C88F8E0DF7FF386D18B157EA2B0F43EB507C1FFFE",
INIT_2C => X"07E22E5D98CF549FF428C70E7CC96EC2BF706A255FFFFFFE7FEFB6CE3A04675A",
INIT_2D => X"FFCA31F7390A9F1B1F83B9726FFFFFFE7FD76A4CCCEEB99C977902797F8B7D7C",
INIT_2E => X"6F17A20587FFFFFE1FD53A9C98D3A4570526D579BD684E7ECFD9C6E981A035D7",
INIT_2F => X"38E1E3A2F3C36A061351D2F643294E7A197D80B38916478A7E0B56677EDD0C53",
INIT_30 => X"81A4CFE53D35FF3F676551514E87AFF1909300E4AFFE9D8FBF87ED013BFF9FFE",
INIT_31 => X"94E9C8A4E41D01C6A3014DE5EF5BDCA50FEFF00607FFBFFE4EF9076D7E7843B7",
INIT_32 => X"307C8B2FCFE0F87CB1FFFAD21FFFFFFE4EFE05DD8A42F6772D72F1FBACDD2F79",
INIT_33 => X"9CFFFF494FC7FFFE7FFCF419B7C12BBE5DC903FE2A4A2F7F91FC149C08F982BF",
INIT_34 => X"7FFBFFFE5620AD99692533FD7CD12FF134E0014E6EA7372EF7B9E6F2FFF0497B",
INIT_35 => X"B7C46FCC8B5C3F61DE20430A188B2DCDC2D612AA7FA9DDAB5B7E3FC10FFFFFFC",
INIT_36 => X"B97AA13F31BDD47B958E46EFFF8492C3A170FFEB8BFFEF3E6C36FFFF5F2004A9",
INIT_37 => X"5DF7DBD7FC33B26E94D5FF7F9C7FFF3E61E1FFFFCEBA15EA27A4F2BE5BFF47E8",
INIT_38 => X"96F87FFF8F37FF3E6087FE1FFFF567EBB7412343227C47F3CCF26F6DA24C643E",
INIT_39 => X"7FFFFE8FFFCEDFF2013EDE8EAF0D73FCF7FF75C081617DCFBD6E2947FFFA72C2",
INIT_3A => X"988D7726A780739DA1F97DB1206EC572C243CE5783F70E3608B9FEFFB4A7CF5E",
INIT_3B => X"5DF5BB40CAF03D66512BBE4BBF7BBCDC5FEABFBFCCD019761FFFFE7FFC56F7F3",
INIT_3C => X"E8C08D9DD3FEDA5C8CA0BF8FF4A9C46A2FFFFEFFFE687FF8396FF809CC41F3D8",
INIT_3D => X"F4E39FC3FFED42EA07F8FFFFF8D47FFDEDB0FDE0DEB4FF9FEAAD7743A7DF5F61",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"79FB7FFFD6FA07F77B1BDDEEADD9FF65378A5DC565AD25609182B849E0FE91AE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"B929DFF4D12CFFA25EADEAABAE67F660B9D77D2438EF661D7FC78FF1FF2EAFE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"3FEE7A4EB9EDABDC4FE89C9D42EF0C2AFEA78BFFFFE31A167B9B7F3DB916F3F5",
INIT_01 => X"F7FC15134CF7C80AFE07F3FFFFF444787B4FFCE5E7B787F6DC247FB5CF30FF47",
INIT_02 => X"7E17FFFFF3FA16187B9FBADF657FF3FF3A1BFB2704743E8AFF3D46FEBEE32F56",
INIT_03 => X"73FF828A387FF7EE018DF44E1D7C3F3E1EE6AF7F4EE509FE7FE109BFA6F7CCAD",
INIT_04 => X"9F9AF6A28C8FFBB7E617CFC712A598FC5FE02699A0FFFE832FE3E7EFFFFE8780",
INIT_05 => X"FE1F53E34CF998FC5FE7FEA7C47FCDF4AFC7E7CFFFFD73925BFFFE38C0FFDFE4",
INIT_06 => X"67EFDC230EFFCFDDC7C1FFCFFFFF420C67FFC0A7B1BE6BC4700CDF820C8ABDD5",
INIT_07 => X"FFFDFBFBFFFFDFC87FFFFECE46FEE7CD31D1D873DDB65EDF9857F7B33EB7F8F8",
INIT_08 => X"7F8FFFF92F7EFF8EDDE72871550516FFE96D37A2CC8B3CD039FFD32C90FFE439",
INIT_09 => X"43FF067C56D7665BA159FF42929E08F287FFE6D647FFEC51FFF168F0FFFFFD38",
INIT_0A => X"FE5FFB25CB3500F33FFFFDE231FFF5737FFAF1FAFFFF7FCE7F77FFFE30FEFF97",
INIT_0B => X"B9FFFAEAF7FFF5A33FF978FDFFFFFFE07F2FFFF2CDFEFFE60C7FB277668FE26B",
INIT_0C => X"D72F7BFCFF7FFCB86FFFF66E193DFFCE081FC23CA6B9F9C7BEF4BB81EBFF006F",
INIT_0D => X"47FFE62114FDFF5FC5878ABD392FF5FB9E0E3A8F7640E07481FF79DA2FFFF0DA",
INIT_0E => X"50AEB2ED514FE7EF254C7F47F9C8CF0285FFF8D43F7FF602CCCFFFFFFFFFDFA8",
INIT_0F => X"8A2F7ECFFCB460C1E3FFFCB1C6AFF17E3ADFFFFFFFFFCFF00FFCC4F4FAFFD6BE",
INIT_10 => X"25FFDD08347FB397D2FFBFFFFFFFCFF84FFA77B8C6BFD7FEF61EBCCA500FE8FF",
INIT_11 => X"07FE07FFFFFFFF3C7F0FAEE65F7FD7FEF77DC23E5DEFCAF9827D3E91FA740C7F",
INIT_12 => X"7F9CCB6D7FFFFFFF67726F7E3D47D27812CEBF7EFFE4CF3C51FC5E1FC7FF7BFF",
INIT_13 => X"E6FFF371BD57E5780CAD3E63F09204D9A3FC1E7146EFFFFF31FEAFDFFFFFFF3E",
INIT_14 => X"11BD7F87B79F6B6EDC7D9E56423FFF07B5FCFF6FFFFFFE3E7FE329A07EFFB7F8",
INIT_15 => X"EA7FBFCA57DFFF1BC3FCFE8F9FFFFFBE7BFF3FE4BFFFAFF2227FF96CCCC32F33",
INIT_16 => X"DFF8FD5F1FFFFFBE73FFBC9EBFCFDFFEC8FFBCA7C938B927037F5D119729077A",
INIT_17 => X"63FF2CDF7FE7FFF8BDFCC0FAD011F7B97FDADD33E7BE38E7E43E77DADA3FFEBE",
INIT_18 => X"3554921D947F9BB8CC6BCE6DF3E7C424E27EEBE8389EFFFDFFFCF19FBEFFFFFE",
INIT_19 => X"6561EE71F1F31254D43FE3F1849FFFFC5EF8FD5FCFFFFFFE63F99363FFC7BFC5",
INIT_1A => X"D2FFFFFAC65FFFFF7EF7F32FD7FFFFFE7FF4807AFFFFBFC50916A865F947C5BA",
INIT_1B => X"FEE7F377E7FFFFFE7FF8364FDFFF3FCFEDB80AD30A07C253D9B8FFD5F1FEC70E",
INIT_1C => X"7FFFF9D9BE3F7FD8483E587AA40689641B08FF33F7FC71F3527FF3FD835DFFFF",
INIT_1D => X"577B63FA8C6F3345E1B7FAD7F7F1890CD77EE4FE7A5FFF3FFFE7FA80FBFFFFFE",
INIT_1E => X"0107F893FFEF630E24FFEFFDE9BFFFFFFFE7BF7BFEFFFFFE7F9E6D3C7E7FFFFC",
INIT_1F => X"DFFFF0FD5FB7FFFFCFE70FFD37FFFFFE7CE26134FE7FFFEF5ACD3022997E7D7F",
INIT_20 => X"B7E2BFFFC3FFFFFE782687B7FCFFFFFB79D6D723373EE8E16275F693BFE8ED70",
INIT_21 => X"70E2A42FF8FEFFFD52BC87E6EEFEDBF372ED3804BFF291EEB1EFFBFF1AF7FF7F",
INIT_22 => X"7F8E0862907EF7F13939665AFEF6DD665A91FFFFC8FFFFFFE7E778FF3BFFFFFE",
INIT_23 => X"23D66CC3FEF4E4FEE7AFFFFFC3B7FFFFE7E1FFFFDBFFFFFE6FFAB687FFFFFFFE",
INIT_24 => X"42D3FFFFBC0FFFFFFFE0FBFFF3FFFFFE4FF9F4C7FFFFFFF07FF4C9AB461E6BED",
INIT_25 => X"FFE3733FFFFFFFFE4FFE49C7FFFFFFE0FFAE7C692C96C4EC066ADBEF7FFBE039",
INIT_26 => X"1FFCFBBFFFFFFFE13FF9FDA5D918917FB17A6A5BF1F33D3BB17FFFFFDEEFFFFF",
INIT_27 => X"FFB33A2831D24EAEE7483EA175F7EAF3E19FFFFFDDEFFFFFFFF379BEFFFFFFFE",
INIT_28 => X"9137D53A79FF5D23BB7FFFFFFF97FFFFFFF7F93EFFFFFFFE1F67A60FFFFFFFD7",
INIT_29 => X"CD6FFFFFE1FFFFFF7FFFE2FFFFFFFFFE1FE810BFFFC6FFD87EFFDD456409347A",
INIT_2A => X"00000000000000003FD33F7FFFC67FE2F71E26E1FE4C3C858222D832FCFFD068",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0FB400FDDB4B6FC0816988FE2AE7FE3841F3BC180DF83AC40000000000000000",
INIT_02 => X"F04BA2003F2FFE19AC018000427C7AD452189680BFFF60E7DEFFF0AFD576E061",
INIT_03 => X"640D0000E6282F341403F74077FF5B4C7CF0AAB09F54C0E607ECF029092B39C3",
INIT_04 => X"55FB0A55283FE84107DF8BA2F825046D370C600B6B249ED4805C70003E7FFEDF",
INIT_05 => X"67C0C96185D7476E37832002B13873645A9E9C0022FFFF7DE16D0000E76D2602",
INIT_06 => X"078340F11A41F0A15DEB9800827EDF7C26038100C00CE44A1BB5EEBA1BAF66C0",
INIT_07 => X"99F0B2028BF1EF7C0C07C000010973EA1FC6286C6A8D9971E700B729E7924A44",
INIT_08 => X"F80D8000E0C47D205AE7C3280B1AFF4603010E790955CB6107010089F589C9C2",
INIT_09 => X"3B8EB1666DD3ADA8C000D6951896DD2B0300C06E0074595E462792008FDAFFFF",
INIT_0A => X"7420AEFE32F7AF77ED497000669140468F588DE00E4FBCFFFF1C8000DA21D272",
INIT_0B => X"BC83800000EA6457639C0FE0CC919CFFEF1C8000D105213E3E1A4AD6B5D5F652",
INIT_0C => X"4BB04BE085A01DFFFE1C00004E0E3FFE136EBCE87800FD2764008E00EAF6B7FA",
INIT_0D => X"E60C00005117FFFE428D1DAB872BFD86040004FF244AE63F21AA20E025C9445B",
INIT_0E => X"6663E5BE8C1FFC8300FD00035FC8DEBFFF03ECC0207A34782461FCE08258BE7F",
INIT_0F => X"000080005AA85B755A480EC7DA5B667070E3FC0009DBBC7FE00C0000738BFCFE",
INIT_10 => X"E734C1036F9279E844E5B9000EC9B97FE88C0000517BF8FE72F1657326BBFD32",
INIT_11 => X"2E8830C0865AF97FFCCC00003285F8FE031D2EA35B13FEFE008000002FBEA477",
INIT_12 => X"FEE40000155AF9FE00EFAA8A3515FF9A00801F100045AE40E81245006418CBE9",
INIT_13 => X"7C0AF43E5B00FF9D40000E10EDD00DEEEE1D8600045427129F7BA8C10331767F",
INIT_14 => X"210000037D436A69F133D00D31CDAF677AF1EE38CFD2797DCE60C000FD96FFFE",
INIT_15 => X"F714A5627981F61ED62F303DC1597E7CE87FC00897A1BFFE7F1BCE058F50F7E7",
INIT_16 => X"3E8C8A31340A727EDD980004349C3FFE7E67DB59CC373BF0210000010A9E821B",
INIT_17 => X"FC7D00006DE77EFE7E7A9040CEE730FCA00000005B9FF9F5EBA57671DFDEF8F0",
INIT_18 => X"7F2CCC80809582FE338000006644FF24E7A8007B9E9DEA0BC3413E3CF6786AFF",
INIT_19 => X"53C0000355E5FF3EF0760EB2017A8DEB67D84686B939EAFFFCB90068D1F88EFE",
INIT_1A => X"3BF7D8B61A4F9CF0DF21CEFB81215DFFD7AF0060B7FC9FFE7F2844A781AADF7F",
INIT_1B => X"6F743D687FD8F9FFD7CF0062CFFEB9FE7BDA1CCB00008C3FC80000042F7540F0",
INIT_1C => X"FC0601C3FF7DDFFE7D70E7FA0003BA11EB0000003EDB093E31E7FC0AFDC71BAF",
INIT_1D => X"37B9106F0062E038CD8000006E90B21AED8FFCBC34B2ACA5F123D352BAB3F5FF",
INIT_1E => X"6A730007C4AA1C3E3FEDFFF8DA1DBF8B65F3A709423781FFD20601843E3E45FE",
INIT_1F => X"0384FFF141DC195A58E502F40165A1FFD66E9FB0FE3816FE7FE20E0895000E62",
INIT_20 => X"4DA252FD57D5DDFFC5FA813FBFB1A5FE7FFCC226B70000808482000FD3A0A221",
INIT_21 => X"8606C8A2BFF8AB7E7FFE341AA1CF03071EC3001E3688EE98D3FB7FF0B4BFA562",
INIT_22 => X"7FFF959D196F00A18AFF1E00ED80474BFF3B97FEA02BB3A31DE4BEFF4A5CC3FF",
INIT_23 => X"8350CC00AD8F187AB89F67FEFABF28BD682235F109A88FFF84E963D13FE73D7E",
INIT_24 => X"2F4B1BFFFFBD1DDEFD8CF7F69AB80F7F37593C57FFCB2A7C7FFFBF4517360340",
INIT_25 => X"9043E1B69C97F77E306166E3FFC7CA7C7FFFB8EA01F8983BE013E0DFD9D570C4",
INIT_26 => X"FAFFEB37FFDD5ABC7FFFF5E92E381906C6C2FFCEF568996B8D9E08BFA88DA559",
INIT_27 => X"7FFFE81633D80658758603E75F339E678FBE254FFE60CCEF28DF86C57EFFE7FD",
INIT_28 => X"1630E87BD4C52F1D806216CFE631D91CF4BDE64AD89097FC215A3BBFF7AA5F7E",
INIT_29 => X"BAB187E3F33C59FFF1DED823B18D6FFB1BB2136FF779569E7FFF611FEFF04128",
INIT_2A => X"F4DE9CF132B14FF80EF0C7DF8663887A7FF80F37E34C5801096FF13C41068DD0",
INIT_2B => X"E1F10FBFA1E62BF87E88F1FFF716BE335109BC1F41B8FEB679B1BDDBF84CFD5F",
INIT_2C => X"7EC18D3FEADE0409709F3EE6C06CD4A966A095487C7652FFD5BC57A13D52CFFD",
INIT_2D => X"075C2A7B8A0A44EDBA083822DF366EFF8FB1B283C5E17FFFDDF7F0FFA915662E",
INIT_2E => X"3BB6020FC825B3FFFA9A0A185FFEDFFBF7F506DF8A54BDAE7E1628BFE62D90F9",
INIT_2F => X"978679E5C7987FFE53FB065F8575BC283E99540E7F629CC51F77DE390C642BC0",
INIT_30 => X"DBFBC8AF9977EFC02A9EC72607F681C3FFC1840CB6B0C3A027C50BEEAA2747FF",
INIT_31 => X"354F6B0853A934FA7FE3E38C455090A7031589FF20CFFFFFFE6FFE7555A1BFFC",
INIT_32 => X"FFF5FDEF7D3F2CA1014EF69CF1A08FFFFE9CFA210ABDBFFFFFFBD79F4FA37FE6",
INIT_33 => X"6C41850DFEDA8FF7C8BC99BB4F6E7FFFDF79C29BECB3FFDC2DFFDF7236D3EE85",
INIT_34 => X"8FA2077E36913FFB1F8C32B0FE86FFE013C1DD7D75F4A727FFF8FF5B30FFA4C7",
INIT_35 => X"D7B8A474BBB3FFB82C727A85EBB4F22FFFFBFA9D46FFDAC2C34CCC5EFFF4DFFF",
INIT_36 => X"32947F88C22FED17FFFBEF09C2FEF4EB61CD8897FFFD5FFCAF6BE51F4250FFFD",
INIT_37 => X"FFFFFDC94AD67A02D94B49013FFE2FD402D65D1F655AFFFFBD7C89EDDA99FFBE",
INIT_38 => X"F24201D26FDFE1116D57D8FF23AF7FFC8FF0B5E5FFB7FFBE41917E717EA28B83",
INIT_39 => X"E1DB13FF827F7DFD125447F3F01BFFFA7103FF9721868DD3BFDFFF09C897FD4B",
INIT_3A => X"E77F0DFFCD5BFFA44B939FAD26B3A8FC5FFFFFDDB357FCF2781055D8D80FCBB7",
INIT_3B => X"151DA3C524F30D80AFE0FFC09D4FFDEEFA5817ED8B836D5FE12785FFAB98FFFC",
INIT_3C => X"7FE0BFEB3893FCA6FDA1D7907AE65197FA7FC3FFB07F7FFE25B71BCFD01BFF58",
INIT_3D => X"FE7373D3CD9E60EFECFDFFFF32AC7FFE8E1F07FF502FFDC01B60EFED132D8315",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"EAE6AFFFF5AAFFFF67A153FFD46FFFB230CAB639F693BE0633F8EFE75D67E673",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"F7BA3BF797BFFAA449DA090400E47407E5FDCFFC331AE703FA0810729817FA7F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"4E79EAA625573F0F867E47FFAC88777DFC49D77A2C27FFFFE0052FFFE32DFFFC",
INIT_01 => X"06BF3DFFAF5AB7BDFE93D79CE92FEFFFE12A4FFFED6AFFFC6751C3E7FB3FF4C6",
INIT_02 => X"FF9D6115D671BFFF64951FFFFAC3FFFCDD2F0FFE383FF0587FA2D2AEE04E8F0F",
INIT_03 => X"B202BFFFF8C5FFFFC6215FFF3E7FEFC87FFFC59F70E36D0005C724FFFBAF37D7",
INIT_04 => X"7844BFFFED7FF1183E663087E504AC7FDC1BC53FE2F74FCDFFF5C14D0E357FFF",
INIT_05 => X"7ECC51B88AB8FCFF6012F23FFE23C7E4FFFBE155E45AFFFFFE05BFFFE18FFFFE",
INIT_06 => X"E17E7CBFFE8727FEFFE07D870F7BFFFFFB383FFFFEDFFFFCBC9BFFFCC7FFE8CC",
INIT_07 => X"FFE0C7C0815BFFFFF7D37FFFFEA7FFFF1D07FFFDBDFFF7C07CD4C1A3C5E7B727",
INIT_08 => X"E26EFFFE69EBFFFF6DF5FFFFF1FFEF5C7748D4A1506992B85E0E63FFFED649F8",
INIT_09 => X"6B61FFFC75FF7920776918E60EA2EC65B0094FFFFEC8E7FE7FE48BF37848FFFB",
INIT_0A => X"2ED10147C2E0C60659A379FFFFA3F3FEFFEABA0BBF522FFBEAF0FFFD4237FFFF",
INIT_0B => X"CC06DCFEFFCEA6BFFFF9C94B989FE3FFF1FEFFFA2E7FFFFDC207FFFD4BFEE61C",
INIT_0C => X"7FE5DBFFB7B5B3FFE3FEFFF70D7FFFFD350DFFF36FFC696E5BF06436E4912FBE",
INIT_0D => X"F1FEFFF2E9FFFFFD84B7FFFB5FFE35DE2707FE99A2FF65FFD30C08FFFFFA05BF",
INIT_0E => X"F83FFFF497FFAAFE30006680124257FF7820B22FFFFDE1FDBFFF0B4C111E93FF",
INIT_0F => X"00F06467C0888BFEFC25A0D7F1FE93F23FFFBE5408B8EEFFDFFFFFF3F19FFFFD",
INIT_10 => X"FEB79C97FFFD4B12BFFF7F0E337A38FF5BFFFFE3A03FFFFEB027F9FA5FFE383E",
INIT_11 => X"3FFEFF3415A76DFF57FFFFF4517FFFFF1387F1F63EFF38FE001CF83E9071A3FF",
INIT_12 => X"E7FFFFFFC67FFFFEFDAFFFFB3FFD1ABE0600F80011027FFFFF1AE601FFFF588E",
INIT_13 => X"977FFFDA7FFCFA7E41030010813C6FFFFFC4A4AFFFFFE104FBCFFD426969A27E",
INIT_14 => X"113F803C7C3721FFFFC7BD7B7BFFC8B99A9FFE4DA487F7FDFFFFFFFF91FFFFEF",
INIT_15 => X"FFFFE79ADFFFF8030827FF742966727CAFFFFFFFB7FFFFEC637FFFD2DFE75FFE",
INIT_16 => X"2593FF25ED0FF6365FFFFFFF057CFFFB8FFFFFA0DFF64FFE2811803E0C0639FF",
INIT_17 => X"BFFFFFFFF1FDFFFF1FFFFF615FF13FFE4030001FE004CBFFFFFFBA3D3FFFFE53",
INIT_18 => X"FFFFFF303FFF3FFC47270000E004F5BFFFCF9F1EB3FFFE5BC613FFA9825FF1F3",
INIT_19 => X"577700080001E2EFFFFFFFFB4DFFFF0FFC57FFC9069FF690BFCFFFFFB3FDFFFD",
INIT_1A => X"9FFFFFF266CEFFF16587FFFD0F1FDFA0FFEF1AFF0BFFFFFBFFFFB6B97FF7EFFC",
INIT_1B => X"CAB3FF6C9CBFDFACFFFF23FFABFFFFCFFFFFBE139FCABFFC24F6040E00819C03",
INIT_1C => X"F3F361FEFBFFFFC9FFFFFF5E97D67FFE3F95200E0000E343DFFFFFFFDF7DFFFE",
INIT_1D => X"FFFFFEF0BFBC7FBA154AB800000073A67FFFFFFFD416BFF9AAF3FB226F1BFFF7",
INIT_1E => X"08EDA401001B031AEFFFFFFF7AE4CFF862FEF58F74FEFE51EF8D39FFE7FFFFEB",
INIT_1F => X"57FFFFFFFEFC47F612BFF3D0A4CBFF63D7B294FFD7FFFFF7FFFFF8B4FFAAFF8C",
INIT_20 => X"BCFBF586E85F3FEBEE2750FD9FFFFFEFFFFFFD303F86FFDE5D3814310019DFF7",
INIT_21 => X"FEA3527F5FF7FFFFFFFFFFBCFF8FFF6004D7F0200016432FD27FFFFFFFAE15FF",
INIT_22 => X"FFFFF7C87FDFFE40740C880040092548B84FFC7FFF6059BFD28FF29D8645C7E3",
INIT_23 => X"146C95460009C581D6E6FA57FFD38BFFFF3FFB75266DC3CFFFD8497F7FEFFFFF",
INIT_24 => X"1B220B3B9FFF1C6FF5C7E2D735D9FF81B7E9C5181FFFFFFFFFFFF7697FFFDD86",
INIT_25 => X"FAC3CB09D7BBFF92CB77427FEFFFFFFFFFFFEE81FFFFE4D241EFDEC0E9013A81",
INIT_26 => X"7B4721F34FFFFFFFFFFFE8517FFF9C6401EFB8E038BE964BEFAB7243BFFF8D37",
INIT_27 => X"FFFFD0F5FFF0771C0007F40052F9E5912142F5E3FFFFEDF69DF3F9D77E33FFB6",
INIT_28 => X"18129200107FDE078C03F591FFFFFE808E77FABEEB31FF9FA287CDFD3FFFFFFF",
INIT_29 => X"0083F5947FFFFC07D7E2FFE653A33F8FFFF807F05FFFFFFFFFFFDBE0FFE15DF6",
INIT_2A => X"0BA4FFFFB8273F2BFF4B7FFFFFFFFFFFFFFFEE41E7C15F9E101EC4006626BE18",
INIT_2B => X"F199BFCE7FFFFFFFFFFE44FDFFC81FBE00FF8A0049BF8B38F38160ABBFFFFF57",
INIT_2C => X"FFFE9DDFFFF13FFE00002000E1E4E896E115CE08F3FC7FCE4A569DF93CAF305B",
INIT_2D => X"180CA000F338F075C00CD03B55FCFFC9F6CBD3F77257E78A3A5EBF521FFFE7FF",
INIT_2E => X"BD1056B1AAFEFFF8D3A04AFA55EDB2D9F0CD1F595FFFE7FFFFFAB3FBFFC47FFE",
INIT_2F => X"278ADDE590B146742393CFDE9FFFD7FFFFF2BBFBFFEF3FFE08008020B715E8F0",
INIT_30 => X"9751AECBBFFFAFFFFFF9F7FBFFF8FFFE010000806197EAE4448DF0FC6E3FFFFD",
INIT_31 => X"FFEFC7AFFFF8E3FE3EC00000800C362D02608BAD793FFFFFC59780E4D12C7EC4",
INIT_32 => X"00C00000C07765C8E26DB6A1E54FFFFFF32570D40FACFE7E982CAF9EBFFCB7FF",
INIT_33 => X"66D6828C0054FFFFFAE9394F1CAE7D7F73AF35F2BFFBF7FFFFBD5FFFFFFFFFFE",
INIT_34 => X"FDB8C3CBDBACE73CFF0BF54C7DF92FFFFFD40FFFFFFFFFFE38C00093000B13F0",
INIT_35 => X"B9DD03D53FFFCFFFFE5F9FFF7FFFFFFE1000006903C4AA30583E384A00A53FFF",
INIT_36 => X"FDE56FFFFFFFFFFE0B800091C33D548086EC7A7F8014CFFFE7C160443B772049",
INIT_37 => X"268000A1814E7100E41666C6806967FFCBF627361EF240B817A4FC3FFFF253FF",
INIT_38 => X"048B8407C18027CF9FFF78764F5D5C5EB5B27D20BEFDC7FFF9F77FFFFFFFF3FE",
INIT_39 => X"DF39EFFE8609DCF5B1A3021AFF9C9FFFFE0DFFFFFFFFF1FE0D0F000051C0F24B",
INIT_3A => X"F87270A67F203FFFFB5FFFFFFFFFFFFE7200000077C1B34DF5B9B217030E2D8F",
INIT_3B => X"BB5FFFFFFFFFFFFE060000FF2E205ABE564EFA030FCBDBFFBFCE6727CD4736F0",
INIT_3C => X"310C00102BF678BC708CE9D278BBD32E1FAE040DC69EF55864C80D6FFE037FFF",
INIT_3D => X"FFB342EF13E704A25F804007FFB2AA5A8AEBFCA6FCC0FFFF0AFFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"37A94100C1AA6A7F1DC2E77BFB1EFFFA5DFFFFFFFFFFFFFE311C0000216AFF1F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"2111C1B6FD88FFEF79FFFFFFFFFFFFFE71000000F0B3E0FFFFFD08FA88117C5D"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"AFFFFFFFFFFFFFFC00030000F351F6FFFFFF1DF9D72468DFA2B94681FC5CF74B",
INIT_01 => X"44078002BD3FFFFFFFFEE9FFFE86448D0B160FC2B9332CF54107819852CDFFF8",
INIT_02 => X"FFFF07FFFF57BE0E24C81FD7F2CCAB533883C0E1B46FFE973FFFFFFFFFFFFFE2",
INIT_03 => X"0253001312032B7E31EB51CFD187FDEE9FFFFFFFFFFFFFF64F8780060657FFFF",
INIT_04 => X"FB66A20668FFFA9C3FFFFFFFFFFFFFF40706008103FFFFFFFFFFFFFFFFF7EBA0",
INIT_05 => X"FFFFFFFFFFFFFFFE000001835BEFFFFFFFFEFF9FFFFF3D0330F0009A93F07E13",
INIT_06 => X"000000534F4FFFFFFFFFFF0FFFFE7D200001019F5055B85B3413E4635E17FBDF",
INIT_07 => X"FFFFFF8FFFFFFD99830003C92025704217D7559B90CFF583FFFFFFFFFFFFFF2E",
INIT_08 => X"19A00880C02C06FB6440B586558FF697FFFFFFFFFFFFFE5C10870003908FFFFF",
INIT_09 => X"EFC6306FD90F6E1FFFFFFFFFFFFFFD34008701CE1937FFFFFFFFFFFFFFFFFF9C",
INIT_0A => X"FFFFFCFFFFFF840C00C002D417CF7FC5C48FFFFFFFFFFFF82080180018D90F38",
INIT_0B => X"00F024F1C8835810D6888FFFFFFFFFECF0C0080C18B8F9A2F00E5C572C6D1DFF",
INIT_0C => X"09CFF1B83FFFFFD8C018C08073848B6D11615896DDCE43FFFFFFE0FFFFFF012A",
INIT_0D => X"A5D880004674E39669ACE543CFF357FFFFFFF0FFFFFC92F006F75F92727C6D60",
INIT_0E => X"7EE896627F813FFFFFFFFFFFFFFA36A402F32AEC64746036710F7166F9E7FFC7",
INIT_0F => X"E3CBFFFFFFFB179A181C3C7DBAD551E1F807DC397D92FFFFE838011000587802",
INIT_10 => X"1D1CBB4E5EDD60CFF8E06199792C3FFF99D801000122606D43C49F96FCC5FFFF",
INIT_11 => X"FC2603B56D903FFF38C8010007CCE3A55A06537BB8F3FF0184FAFFFFFFFFDE82",
INIT_12 => X"1B00001F47B6BE71F86057FDF03FF8C8786E7FFFFFFFFE420078ABA11377EEFF",
INIT_13 => X"F0122B3F97BFFA7BAC53FFFFFF7FFC5C3C0445D17E6034FF0080C066F7FFFFFF",
INIT_14 => X"89A3FFFFBF7FE89426CF74EAB90F6700E019675FFFFFFFFC2F81000607297E20",
INIT_15 => X"7D6BD3E38187A10060C887FFFFFFFFFB9E7100000389069DB96A927EBBFFF7B5",
INIT_16 => X"03DCFFFFFFDDFFF95FD9804A48E84F9B2E087ABA27F2C32111A7FFFFBFFFF258",
INIT_17 => X"27E9002F00C3CC16EEE928A75FE522A9C147FFFFFFF13A5E31BA71C600E1DD86",
INIT_18 => X"A139405B3FE3353EBA9FFFFFFFCCE6CE4ACA974000109C689087FFFFFFFFFFF2",
INIT_19 => X"3D8FFFFFFFD4D56E35FE08CC001C7E6A9C7FFFFFFFFFFF798BB0000E209BBDAA",
INIT_1A => X"1F8F4D6C019CFDBF95FFFFFFFFFFC767B60C000985EFC19C00884524FFFAE8A1",
INIT_1B => X"CFFCFFFFFFFFE88F2FBC0C060DDC6C00709167E3FFD1E2CE6E7FFFFFFB4CD6AE",
INIT_1C => X"B43D0C000C47F0DA15C3641FFCC6F71CC2FFFFFFE0E3B3A87FC00C8C19CC19DC",
INIT_1D => X"C003F79FFFCB9A9FB4FFFFFF60C70FE67FE83F803DDC2D1FDFFEFFFFFFFE1659",
INIT_1E => X"04FFFFFA52B7E3E67FC110003B9C5A4FFFFFFFDFFFFC445F1B1004E0888E95D3",
INIT_1F => X"7F83688613C3A4BFFFFFFF57FE15F8DEFEE200FF089A42F08000D0FFFFC037F7",
INIT_20 => X"FFFFFF67CF4F56BFFEFD6003721B0F8A6176AFFFFFFC99E95FFFFFC9B6ACFAC0",
INIT_21 => X"FEE4A1335967AAE88F922BF7E7708235BFFFFE728E74FBD27FE4D4A33B91F57F",
INIT_22 => X"490C9FF84DC4223527FFE341725215BC7F5A542F87F2E3BFFFFFFDA1CF6C3BFF",
INIT_23 => X"8FFF48C9FCFE22FE7DD048A0E3807FFFFFFFBAF99C1387FFFD213B3B00885EAE",
INIT_24 => X"71D863909EB9BE9FFFFE897385655BFFFBF9CC19D8D12E6821F3FFF479EDE5F2",
INIT_25 => X"FBFF2D053BF9BEFFFBE2F90A5B8B69710FD7FFF41780D8DFFFE62BCBBF07DCFE",
INIT_26 => X"D5EC20035B2153EE01F17FE8BD120E3FFF6B5B57FFE7FFFE0A1883100CFC225D",
INIT_27 => X"87A9FFC6FD2FD83FFDA84F33FFF7FFFE0F14016223F3DFC6FBEED71931FBFEFF",
INIT_28 => X"E6A58CFFFFFFFFFE7D3906C89FCC7900E762BD182E9CFFFF95FE8A5833540105",
INIT_29 => X"21078718FEB1A1500C3BF39FB608FFFC43FF2EDC615A2CB587A97DC2D8DFEAFF",
INIT_2A => X"87CA01917979FFE286FC44D5C3A8FB64066C33EEF7BFF3FF135923FFF7FFFFFE",
INIT_2B => X"EFE5E75D1823EA090018CC07677F3FFDB436FFFFF7FFFFFE77F6873CFEE181F9",
INIT_2C => X"072CC64645FFFFE9D8E67FFFFFFFFFFE5EEEF50C36821C2B679727E80593FFFA",
INIT_2D => X"63D1FFFFFFFFFFFE6603350E232E5F06DE80F83A8C2F3FF33FFFD99183BFC7C2",
INIT_2E => X"2711E6076F3E0FAE4101C3F5BA78FFDB7FC9EC106E919ED400569555EAFFFE5B",
INIT_2F => X"0380030C93FFFFF7FFF1EB80BB54144C00A720E3C1FFFE90A307BFFFFFFFFFFE",
INIT_30 => X"FF81DFC09BA542C4000DE016C7FFF07DE7AE9FFFFFFFFFFE030802146D309ECF",
INIT_31 => X"009F59FFFFFFC123DE280FFFFFFFFFFE1DEA123D20F37F5C06C38E11B6FFFF23",
INIT_32 => X"3F7503FFFFFFFFFE5FFEBAE220F2066B0C004E8262FFFC13FF97C800D60CE5A3",
INIT_33 => X"0411B16D65072169C00221C002FFFB2DFFFFF7C9F7E7FECB0099BBFFFF807B54",
INIT_34 => X"0DDB5E8643FFF8BFFF9FCA689A3FF23F80003FFFFF353C6FBF3CAFFFFFFFFFDE",
INIT_35 => X"FFFFCC60518FC5DD00C787FF859B28BD7CAD1FFFFFFFFFFE5B9B5BD1108FD6F7",
INIT_36 => X"1C046056AC2B9F407D5E47FFFF7FFFFE5FAA6163000B2C079910FFFB05FFFFFF",
INIT_37 => X"3C70EFFFFF073FFE68C18C51000553838F137FFA9FFFC5FFFFFFC460000A76EC",
INIT_38 => X"503098C0013CBC800F935FFCFFCFA97FFFFFDE21612E06E01C1147EE8AC23E57",
INIT_39 => X"384BFFFFFFC28E7FFFFF4F236EF9640118311862E008FF6DD856B3DFFFC71FFE",
INIT_3A => X"FFFE81C78F36AF8300051057C8297FB4BF7FABFFFFFFFFFE669B129C014BE58F",
INIT_3B => X"007D457FEB827FA1C07977FF3FFFF7FE590E15180283C1878A07FFFFFFCCFDFF",
INIT_3C => X"65C2F7FEEFFFCDFE36697C0303E27600897FFFFFFFFFBFFFFFFEF095A11FE3C3",
INIT_3D => X"676EED800388DB1E6EFFFFFFFFFB6BDFFFFC5730BDDF9EC380C053FDFEB2FEB5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"51FDFFFFFFE71FDFFFFC450A222FFAC3AC0678FF775BFF07BEE19794EFFFF61A",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFBB99A5A9BD8018280E5FFE1C85F52993B18425FFFE5127F6303C12CEEFEE5"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"9341307F53987F3800C3909C5FFF81EE479B010F6DCC5F272FFFFFFFFF99CFFF",
INIT_01 => X"00C1F7284FFFDEF875A403E06B9E7FB31FFCFFFFFF97FFFFFFF8CE923C629CEC",
INIT_02 => X"784900E3A3D6F9503FFD7FFFFD7D3FFFFFF1CF059D4356400741C9FC82F601DC",
INIT_03 => X"FFEA9FFFC77FFFFFFFF6DEA57A45B4B71905152AB27FB1E60301FED7DFFF2FE2",
INIT_04 => X"FFED4E0FB7741C3517FD84424724B2890104FFDF3FFC35DA65C700082542E25C",
INIT_05 => X"0BBB682659BD10F60C21523F3FFE4BAA415A040A2173C5EC3FEC1FFFE7F97FFF",
INIT_06 => X"000FC1C61F7F3D06445B040E91EE6DB53FA65FFF48B5F7FFFFFAAF3EA39A6C63",
INIT_07 => X"5BC7000DF1230DDF3F013FFF0087FFFFFFF7DD88E4ECFB8EC7095117FC0AD26F",
INIT_08 => X"B8219FFEBC1DFFFFFFE0BDFFB912950EE52A35443830E63C6012BD9FFFD6BE1A",
INIT_09 => X"FFE2FE09048EE2B00695CC3C00820D2C81F2AF3FF4F6DF7E31EF7931A7378BFF",
INIT_0A => X"44A17275C15E823478CBAEFFFC9524CE3BE700527E67CFFF226C9FFCEBABFFFF",
INIT_0B => X"99429CFFEF37FFFE20F00C59D9E15FFF8B70FFFD50E7FFFFFFABFE40E3530FF6",
INIT_0C => X"2F0859118DF43FFFD01E7FF9C0CFFFFFFF03FE05AA636BB11DFD978403D42DB7",
INIT_0D => X"47E77FE080FFFFFFFEAAFF00B626D9FDFBFDC83B075CA57B491F45F8E6FF9FFC",
INIT_0E => X"FE99FFE8D369FF7DA2D54B0078678CFC6B2A3AFFC3FF3FEC7E87C9EBDC96FFFC",
INIT_0F => X"43766263F4BE06FEBB070FFF33FFFCCA7E26EAFCA36CFFFA554DFFA6831FFFFF",
INIT_10 => X"9CB520FF6FFFFF8A7FAC7EFD6887C1F06B93FE1384BFFFFFFE69FF939E73EA79",
INIT_11 => X"4D1FB7746FF83E530DA787E132FFFFFFFE7FFEEF29468A7D03FF4A7041B515F8",
INIT_12 => X"1CBF27C0287FFFFFFEAFFBCAEAEA7C7F21808FC2AC91FAE2C41A8DFF7FFFFFC0",
INIT_13 => X"7D8FFF568D6D83FE1B2BFA02633A622710DCAA67FE3F7FF2324028DD896F7CD5",
INIT_14 => X"AB1FF1C20ABA7D47A15B30BFFF1F7FFA2F22DA027DF0D16843DA5D1015FFFFFC",
INIT_15 => X"4EFBE7FFFF1FFFE8336BBBACDEC0F001C9EE9000CFFFFFFCBC17F84F706EEBFE",
INIT_16 => X"3A5F533FFDF6C70D886241F17BFFFFFFF59FE58FCB66F1FF5A67F64360ECFC07",
INIT_17 => X"1FF67E0593FFC77FFC07FDCA8581BDFF149FF9C371C328470629AC1FFB3FFDC0",
INIT_18 => X"FBEFE2327230D9FF9743FF7C7384B5E18165FF1FF1DF5C6E296FFB7FFE4CF031",
INIT_19 => X"D69DB8BD1C70F572EE9FDEEFF9C9DE7E0759397FFCCCF0FCD39C3C0457FF837F",
INIT_1A => X"B949D6B0FCFB9FFE3BBFFF1FFA47E6FDACE1AB8C1FFFE07FF85FD97575DC83FE",
INIT_1B => X"03B37FF3DA8ECE20A3EA5ABFDFFEC4B7FF5FCE7F3AFDEFFF329FFECF69BC8E2E",
INIT_1C => X"07FF33B1FFFA717FBD2FCBC994AC0FFF61E8F5C3E3AA8DFB640F12DDBFFEEFFE",
INIT_1D => X"FA6FE001AE598EFFB108F1D859FD8DFCC8F25907A7FF07FE2680FFFFF960CE7D",
INIT_1E => X"841BF119758D8FFFE041F326500FE7FE2485FFFFF6391EC1AF643805FFF6A07F",
INIT_1F => X"EB808046DF33FFFE0613FFFF7B05D77D7F1A18117FF36C7FEEFFFA346185C6FF",
INIT_20 => X"073FFFFDADF8C2FDDFD800D77FCFD4FFEAFFF5B9D1F744FFFC1DFA972103CFFF",
INIT_21 => X"6FC000947F8CAEFFE97FFCC07114817FD81AFA71E185A9DFE82133F818BDFFFE",
INIT_22 => X"CCFFE289EA07A57FD6DCFB66A05E9C3FBBA3E461EF58FFFE3B5FFFFFA2DB0008",
INIT_23 => X"EEF2FE872F5CCDDC6E070AEF7406FC0E7C4FFFF78BE55891ADB039B4FFE054FF",
INIT_24 => X"90FF499F7E23FC661F87FFF27FA74B1CECE89B85FF1835FFAEFFEEC367C0C5FF",
INIT_25 => X"23FFFFF0D9E443239C4DD9ADFF1877FFFBFF1725A2B897FFEA07BCE4C37942BB",
INIT_26 => X"E7B8B8BFFEEC81EFE5FAC9A549BFBF3FED0518F40317AED167B65C6FFF0FFDF6",
INIT_27 => X"BDFD856CA80F52BFF2E265D2B08D4138FF5F9F5C3FFFFECE3EFFFFF6D86825CB",
INIT_28 => X"F7043F79A6570027FD4FB456BFFFFF3E7CFFC1329F22C3030DEC62FFFC91B5FF",
INIT_29 => X"FE368F8D9FFFFFFE7CFFA55484C3807532F39BFFFDE1C0FF9DF9E003C31350BF",
INIT_2A => X"7FFFB56E18CE3CD4781DED4FF7F6C2FE33F818057B872A4FF1A104BB64902277",
INIT_2B => X"0108B62FF0622EFC1BF624A33B23294FE97BAA0C1DE9AD527FF3BD053FFFFFFE",
INIT_2C => X"3FF066712C64772FFD370421C39AE575FFFFFC404FFFFFFE7FFFF165D1B6D574",
INIT_2D => X"BD85C3D1F8C3D5D3BFFF7123CFFFFFFE7FE01ED78F07A8008D0125BFF25156BC",
INIT_2E => X"3F8FC750DFFFFFFE7FE68E84BE1B7D38CF1BD9FF79D10FBEABF338E630CBFBDF",
INIT_2F => X"7FFA5C63760CA644A74D95FFB091FFBC318C3EB6C1E83357DEB0C6F8357DEB2B",
INIT_30 => X"D49841FBA2136FBF442DA557125A6F25FD4713E14690E7EC5FFFE44A97FFFFFE",
INIT_31 => X"8DFD8BC01452F13E5CCDC35747F6A39EBFFFF72DDFFFFFFE7FFEF8EEE51B258D",
INIT_32 => X"E82D6CF27F1C5FE9A5FFFCC05FFFFFFE7FFFF9C19271DC508A0153C7F8D15FB8",
INIT_33 => X"64FFFF90FFFFFFFE7FFFF8FE589A30EDBF304BFFBA401FFEF25E1CBB104D7102",
INIT_34 => X"7FFCFFFFE571583B7D195FFE8041DFF6F87E1C3E700F2039F9D8086B7F00A664",
INIT_35 => X"7C2A77E2E4C14FF2F9773CC081A46A83CF3610E3FF25A66B4AFFFFF6DFFFFFFE",
INIT_36 => X"9E38DDA9A1942B92657EDD7BFEA74CF828FFFFF703FFFFFE7FF8FFFFE263C54A",
INIT_37 => X"BDE743EFFE5056FC79E3FFFF37DFFFFE7E1FFFFFFA0CDBF0300A8CFF68467FE8",
INIT_38 => X"7025FFFFD5BFFFFE7FFFFFFFF8760BF476455C478847FFE536FA195360007B2E",
INIT_39 => X"7FFFFFFFFB60BFFA1FDA32CA392A6FDF03F3170D71179A4830977EBFFD8CE63F",
INIT_3A => X"AD4878B347857FFB67E73258C61D220DBD2A348FFC5819F36155FFFFA024F6FE",
INIT_3B => X"B3FD77FA970DDA01475E8157C03939BBFDCF3FFFF626BAAE7FFFFFFFFC3E3FF8",
INIT_3C => X"97BC0281B0FFABDC7F155FFFF8746ABA1FFFFFFFFEA37FFD6CF93D2C300F7FCB",
INIT_3D => X"FFB21FFFFDAF65207FFFFFFFF906FFFDF36FBCEEBCBD7FD3D7DAA9F987031800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFCFFFFF32FFFFC51AD3F079EF77FA2EE039CD9174F0200BFBFC2DBA5FD745F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"02B13F45CE2B7F5EEF1CA5E569890000BFDB82BCEFFE7FD97873DFFFFFC664CE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FF7637B60E054B20FFC9025C9FFFB5C8FD3FC7FFFFDA52D07CFCFFFE00D78FFF",
INIT_01 => X"AFEFD3CAE5EFD3B1FF1BD7FFFFFA0BC07CBFFE19AD6FFFFF5A5EFFE2C02D7F8F",
INIT_02 => X"3F83E7FFFFFC3D6C7FFFFEFFBC7FFFFF4C96FDA400797FF53FE9FF72D607CF20",
INIT_03 => X"7FFFF9C53F3FFBFF2270FB960131BEF5FF3CBF840E03E98047E3FBAAA5EFD6DF",
INIT_04 => X"4E18FD6100699E45F28DAF902C40E0004FFFE1F5A9FFC2281FC7FFFFFFFC3858",
INIT_05 => X"F7EC1FD7EBDBE000CFFF888849FFFF971FE3FFFFFFFE64EA67FFC04E701FE3FF",
INIT_06 => X"0FFFEB1183FFFD5FFFE3E7FFFFFFB0587FFFFF33333FF7FFC199E5A100EDDFCF",
INIT_07 => X"FFE3E7FFFFFFED007FFFFFF0807FFFFF01B7ECC6C1CC1F5FF235FBC79DDC0000",
INIT_08 => X"7FFFFFF8A0FFFFFF8DFFFC87C9473C47F6547BE7B008002027FFCEF157FFFAD5",
INIT_09 => X"CF27CB87CB0738C7E641FBD75E800000FBFFE44BF3FFF5DAFFFEF7FFFFFFFDD6",
INIT_0A => X"99F0BFA7FC0900000BFFF47D23FFFCC2FFFC7EFDFFFFFAAA7F8FFFF9A17FFFEE",
INIT_0B => X"2BFFF3BF6FFFFCD67FFEFFFEFFFF78F67FDFFFF9A83FFF9F0C0F0A8BDBD83A37",
INIT_0C => X"BFFFFFFFFFFFFF987FFFF9F5D4FFFFBF8BAFDB009B96F27FC17A7F37FF03000C",
INIT_0D => X"7FFFF6746DFFFFBE808E2E810267EEEFD00BFF29FD80001DB7FFF97187FFFE36",
INIT_0E => X"867E5AE1214FF97F73503F01F8090CBF8BFFFFB2169FFA77DFFFFFFFFFFFFFDA",
INIT_0F => X"8810BF69F980071B67FFFC9E2E7FFCF7B9FFFFFFFFFFFFFC7FFFEB02697FEFFF",
INIT_10 => X"CBFFFEFCEF0FFB6F9FFFFFFFFFFFFFFA7FFDD5D5AF7FEFFF07FED0C4205FEAFF",
INIT_11 => X"F6FFFFFFFFFFFFFE7FF05CDD5E3FEFFFC4BE0C00210FFEFF59097F0BFE4462FB",
INIT_12 => X"7FE316A79E3FC7FEC77FDD0001EFC3FF1D887E7BFDF46AD24FFFFF6B2C6FFCFF",
INIT_13 => X"417FBD0E814FE2FEDCAAFE27FF11630F71FFFE8D556FFFFFF8FFFFFFFFFFFFFE",
INIT_14 => X"61A8FF2FFE2C05B6A5FE3F6F9D8FFFF8FBFFFF9FFFFFFFFE7FFFA60CBFFFCFFE",
INIT_15 => X"483E3FB4FEBFFFFCFFFFFF1FFFFFFFFE7FFFAE477FFFDFFD46FF90E1C187F8FE",
INIT_16 => X"FFFF7EBFFFFFFFFE7FFFAE2E7FFFFFE283FEF798C56FFEF383F4FEAFFF6107A3",
INIT_17 => X"7FFFA1EDFFDFFFE3B1FFE618CDE7A67C47C9FF3FFFFFCADCA8BFBFF4C9FFFFFD",
INIT_18 => X"D1246B520A37F17DCED3DE27FFE00D36E53FF7D3A45FFFFEFFFFFEBFFFFFFFFE",
INIT_19 => X"2EF3DE7FFFF4131B15FFFFF5285FFFFFFFFFF93FFFFFFFFE7FFDA4BA1FFF7FFC",
INIT_1A => X"7F7FFFF889FFFFFFFFFFF91FEFFFFFFE7FF8687D1FFF7FFC4124E4B04C6FD89E",
INIT_1B => X"FFFFF90FFFFFFFFE7FFFD6C53FFFFFF9DE34E4E91C5F30FF76EFFF47FFF705B0",
INIT_1C => X"7FFF2FBB7FFFFFFCEC8DF7F8FEAFAE24F06BFC93FFFEDD00B6FFFFF8FAFFFFFF",
INIT_1D => X"8A75E8BC6D9F8799E00BFAB3FFF30F18DCFFFBF981FFFFFFFFFFFC7FFFFFFFFE",
INIT_1E => X"0087F6D1FFF1951FE17FF0FEF83FFFFFFFFFFFFCFFFFFFFE7F7F4C83FFFFFFFC",
INIT_1F => X"1B3FFFFF029FFFFFFFFFFFFEFFFFFFFE7F1C437BFFFFFFFF4305315927FE47ED",
INIT_20 => X"CFFFFFFF3FFFFFFE7FC05D7BFFFFFFFEC8F42EAB33FF9193A0D3FD05FFF3A76D",
INIT_21 => X"7FC06173FFFFFFFE3E1C07B4E6FFE1FEB05DFE0BFFF2E472C0DFFFFE9E6FFFFF",
INIT_22 => X"BD246D93CA3FFDFFBA7BA5CDFFFCCD066343FFFF09DFFFFFFFF8FFFFC7FFFFFE",
INIT_23 => X"A4C153F1FFF97DC79F93FFFFF6EFFFFFFFFEFFFFE7FFFFFE5FFB387FFFFFFFF8",
INIT_24 => X"DD3FFFFFC7A7FFFFFFFFFFFFFFFFFFFE7FFDD5FFFFFFFFF87C075224E71FD5C0",
INIT_25 => X"FFFFFFFFFFFFFFFE7FFD77FFFFFFFFFABF555C27F40063C7828CB15CFFFDB451",
INIT_26 => X"7FFD1BCFFFFFFFFE7F404D536A3CE8D03156F4107FFFDD67353FFFFFD827FFFF",
INIT_27 => X"7FF899B5E4103ED97A5E4E297BFF7D7D573FFFFFE627FFFFFFFFFE7FFFFFFFFE",
INIT_28 => X"0262AEC27FFFEEE2825FFFFFF4B7FFFFFFFFFEFFFFFFFFFE7FF97B1FFFFFFFEF",
INIT_29 => X"AF5FFFFFF9BFFFFFFFFFFFFFFFFFFFFE7FF7A69FFFFFFFE7FFFC64011A9B03B0",
INIT_2A => X"00000000000000007FE1AEFFFFFFFFFFF8FD03313FDE7718357FA0CEFFFF937F",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"00F0006B3DB183C500CF2B001C4FFF1CBC0000000C0019CE0000000000000000",
INIT_02 => X"A0988C00155FFF3F280000000183972E6FFF08BDFFFF082F6000A3C015C20000",
INIT_03 => X"B00C000001C5A3EE53FD0FF88FFFC3C380009D700EE9000600E00004F88D6DDA",
INIT_04 => X"2C02070D95FF13C007DF873E671FF861300000049FB9FBE970E0000014BFFF3D",
INIT_05 => X"07C0C66E0C270C103003000153A135E6A3B5C00019BFFFFE3D6C00000086A5F2",
INIT_06 => X"000300F1216150E56C75200007BF3FFFC4000000000698322786F8A92B9FCEC0",
INIT_07 => X"F6AA5202093DDFFFF4040000011B13E22038C78A645BC6710700F0740438AF20",
INIT_08 => X"F40C0000E02C29D81CE78033F1B3E78003010064031C00E900010001F8ED0A1B",
INIT_09 => X"42FF3F76A4B0FBC8C000C60E098F1FF70000C00E3D9B4A26CB8991000E2C5FFF",
INIT_0A => X"70008E0009543FFF494970000E676001812085000C72DFFFF51C0000D891732E",
INIT_0B => X"8F838000149DC444E75C04000D1FBFFFED1C0000C4629E1C40BD8A3FD0B4F8D2",
INIT_0C => X"3C30070004EB3EFFE01C00005733FFFE6C31D7D6CEAFFC2660008E00D58FAFFC",
INIT_0D => X"F40C000049E7FFFE7C54C9AA874DFC46000004FF03CF3FFF4F4200E0087F0458",
INIT_0E => X"784B265595ABFCB3000000033CC5917E1E820CC0174EF0478A60000001AE7CFF",
INIT_0F => X"00000000298E49F9ACF00EC7CC4530506CE000000B8B3CFFFE0C00000C07FFFE",
INIT_10 => X"C7AEC10369417829E8E3C00005C47FFFFE0C00002DC7FFFE7CF526244E97FF12",
INIT_11 => X"5005B8C08ACEFEFFE20C00000879FFFE7C162364D507FF0E008000004245A467",
INIT_12 => X"FC0400000238FFFE7F092CFC11FBFF4C00801F00082C0782BA1081006AEB0873",
INIT_13 => X"7FF3A74044EB3FE840000E00BDC795E4F731A00003486044F085D4C108297DFF",
INIT_14 => X"600000032E3EA69BFD97200133A5B8DDB10B9201C02A77FFF800C00001067FFE",
INIT_15 => X"FA44B9023ADBA18FC40CF801C03C7AFFC217C0086238FFFE7FE294440FBF2FF5",
INIT_16 => X"BEBD1621048271FFE26800040BD07FFE7F8694980F3207FFA0000001177F01E7",
INIT_17 => X"FC2000007A0AFFFE7F431B600C06CBFF0000000067FFFFFBFDB64C7019C9D163",
INIT_18 => X"7E8E3ED0012D1DFF838000007F85FFF5F81CE97818C1D3EBAE04657006F475FF",
INIT_19 => X"DBC000002EBEFFF6FAF9F7B003D751653B94C270C0556FFFF3780060FBFFFFFE",
INIT_1A => X"FB3FFF7002EBC0BA98B67161408DECFFF324006017FFFFFE7D6DBDE80072CEFF",
INIT_1B => X"D821064F3E9C19FFF24C00603FFF7FFE7D4E70440000877FDC0000009EEE3FFB",
INIT_1C => X"F1FC01C33FFEB6FE7E5719A000003FCFEC000000FE4748FBFA37FE10C1F2C13E",
INIT_1D => X"7F56877800616349F30000003F22C13F744BFF38880D53C098DB8A9BBFDF2BFF",
INIT_1E => X"F6B00007AE86AB42B61BFFD2C2D65311141DA48381565BFFFDFC01827FFC70FE",
INIT_1F => X"7A8BFFE080ABF798103485B9F3D7DBFFFEED1F867FFCE2FE7FF9029AF8000CD8",
INIT_20 => X"E1B43AF02ABE87FFF8D901057FF8C3FE7FFE61873C0002C03F00000F0D2BA45E",
INIT_21 => X"CFFE00117FF1CDFE7FFF84742E0F0147E140001EBB69C440DDFB7FF894FD8CE6",
INIT_22 => X"7FFF28710E8F009F583C00000FBE1B74F138BFFD2027F87691C5F9FECE3693FF",
INIT_23 => X"ECFCC00041E90894329A5FFF80942538A00D7BF018B817FF97F0402EFFF5CAFE",
INIT_24 => X"10ABB7FF908FE6FFE147E3EAF4D20FFFC60863F5FFEBC0FE7FFFBCC914C60341",
INIT_25 => X"66BFD919E64A07FF0342C167FFFB16FE7FFFFE5B30000039AF7FE0C016E82748",
INIT_26 => X"5277647FFFDEA47E7FFFD7A91E0000021A80FFC0F0F6BFF005E2727FB483CE5F",
INIT_27 => X"7FFFF47FF3C0061BFC5803E0FCF8A1880D421B3FC8600D1CF59722BFEBD7AFFE",
INIT_28 => X"3175E078DDB9C9C7014208CFFD7C0EDFF45F0782223A2FFDBA7B106FFF9A70BC",
INIT_29 => X"39A1946FFEBC111FFD3D37C1B2A91FFF1179081FFFE2A35C7FFFFC5FC5F00188",
INIT_2A => X"FF7D4E20F2DC4FFF25FAFCFFFF906AA47FFFFFFFE4CD980160F5F03C4290D143",
INIT_2B => X"93FA0D3FDE01FDA67F7FFFFFFCEB7E334F843C1F43BA1E5878118B9FFEC01B7F",
INIT_2C => X"7FE1AAFFFD04E4008FD7BE07C72FCF276608B07DFE6915BFEDBDC0E2AD7B5FFC",
INIT_2D => X"5F784E038070DC3182540320CFF8C67FDBBA8A227D38FFFD63FA023FD050DD8C",
INIT_2E => X"03B017C26FF0B9FFACAA7F02B5B27FFD3FF90A3FF011BE267F944B7FFFC4C002",
INIT_2F => X"DAD7FC5E2DBCBFFAEFFCF5BFF8F0FFAA0387BB7FFFFB2C003F8B46010583ECB7",
INIT_30 => X"F7FCF2FFFDF1FFC66C79C5905FFB53947FFE3400B2028A4747F40E79F0544FFF",
INIT_31 => X"79DED323E7C1AF7FFFFFEA00C48F77A0E31F0838D928BFFFEB8CF9429948FFFB",
INIT_32 => X"FFFBF360767FB8C2714665DFFECE3FFFF3FCF9FB0AD13FFFFFFCFA7FFE23FFDC",
INIT_33 => X"184584CBFFEA3FFFF93D697DBFC0BFFFDFFEF37FFB34FFFE68BFE577F110DE43",
INIT_34 => X"DBDE263F59607FFFDEB03F7FF803FFC244A78E7C62F3C50FFFF1FA98347FD311",
INIT_35 => X"9F7F24FBD00FFFC268FDF904E2A3FCFFFFF1FE5C007FF6325C4E0C1FFFFB7FFF",
INIT_36 => X"7BA4FE40C1B2F1DFFFFFFD40023FF41AA24A4805FFFF9FFF1F6771BF9BB17FFC",
INIT_37 => X"FFFFFEB080BFFE9BBE4A09057FFF5FE7CBCFE9BFA990FFFDFF0355F3D007FFC4",
INIT_38 => X"E54181C29FFF9FA03ECFE9BF8B607FFEBDF46BFBE123FFFC7D29FED17E917387",
INIT_39 => X"D4A7FE7F88327FFEDE87ABFFE01BFF947142FF6721800D707FFFFFB1012F7CFD",
INIT_3A => X"E063E3FF9C2FFFA878D09FA8C7809ECCBFFFFFCDB2FFFE85F11041C1D7FE7732",
INIT_3B => X"63D0AFE794F04E1FDFFFFFF2807FFE01FB1801E1487C734BED730FFF94957FFF",
INIT_3C => X"8FFD7FF71C9FFE49FC20D0F002DD69AFEE1B5FFFAAB0FFFFBCF71BFFC447FF60",
INIT_3D => X"FB3190F0280F98DFF1BADFFFBB22FFFF7EFFFBFFA4AFFE70220017F3ABEA000C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"F85F4FFF9125FFFEC6AFC7FF045FFD205A8CBBF1CA003C0157FD3FF90E51FF4D",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BE6957FFA4FFFE027286041BE7BD7C002FFE4FFE5785FF0FFE3E7070090F0EFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F67C42D5D64BC001DFF0FFFF1C5FFE5FEF470745BDF4BFFF682AFFFC7A4FFFE",
INIT_01 => X"053FD3FFB566FFADFFF7700913D01FFFF5C97FFFFC27FFFE9E12AFFF813FFF02",
INIT_02 => X"FFFA600585BF7FFFF7E33FFFF90FFFFED25DDFFF02FFF4C67FDC3047FFB74C00",
INIT_03 => X"FBFE7FFFFE83FFFE1C5D3FFF41FFF45E7FFF9A679B1C8C0002CFA5FFCF33DFED",
INIT_04 => X"B8187FFC05FFE4527FFFFF7FDED24C7FC077F7FFF9F93FEAFFF7200FB983FFFF",
INIT_05 => X"7F14AFFFD90BDCFF6005FBFFFFE48FF9FFF0C0EDB8C5FFFFFBFC7FFFFD07FFFF",
INIT_06 => X"E062FFFFFAAA97F9FFF28CD1D60FFFFFFB38FFFFF20BFFFFD7CBFFFD0AFFF4D0",
INIT_07 => X"FFF075BE5A6FFFFFFF20FFFFE307FFFF48ABFFFE05FFE2DA7C03F78FD8A125A7",
INIT_08 => X"F6F1FFFFA037FFFFE781FFFB4DFFD6247D172961E564A8A240045FFFFC90C7FC",
INIT_09 => X"E44DFFFC4FFFBEBE2C09002CE2CD081BC008B7FFFF4B5FFCFFF2FC6D237BFFFF",
INIT_0A => X"54D1014E754D879A318013FFFFB9AD7FFFF80E90A4711FFFFFFFFFFE2FFFFFFF",
INIT_0B => X"42005BFFFFF3CE3FFFE5C3DA6700B7FFEDFFFFFCEFBFFFFE1695FFF81BFF632A",
INIT_0C => X"FFF123FC07C7BDFFEDFFFFFD90EFFFFEDE23FFFC0FFF073E23F00030E04B21FF",
INIT_0D => X"DBFFFFF020FFFFFE1CEFFFFE1FFF5ABE27000099E0486FFFEC80027FFFF3F29F",
INIT_0E => X"186FFFE57FFFACFE30006680013463FFFFE083DFFFF96C4E7FF8FFF3D714A7FF",
INIT_0F => X"0000640000000BFFFE44216FFFFD40237FFFFD81297615FFABFFFFF0A67FFFFE",
INIT_10 => X"FFC61C37FFFE0D667FFFFD76F8100FFFF7FFFFF49BFFFFFF0C0FFFF41FFFAABE",
INIT_11 => X"7FFFFD661A7464FFFFFFFFF8EABFFFFE3FAFFFE85FFE9ABE001CF800107007FF",
INIT_12 => X"6FFFFFFFD6FFFFFE969FFFC83FFF907E0000F8001101CFFFFFAE8637FFFFBAED",
INIT_13 => X"B0FFFFE0DFFCF1FE0100001001028BFFFFF97014FFFFE0B647FFFFC8463720FF",
INIT_14 => X"2100003C00036FFFFFFF9A00BFFFF4DAC6F7FF4D854A667EEFFFFFFFCAFFFFFC",
INIT_15 => X"FFFFF2262FFFFF2E470BFFC2185F77BE9FFFFFFF987FFFFC5FFFFFA0BFF8AFFE",
INIT_16 => X"615BFFE4CFA7B3583FFFFFFFFDFFFFFEBFFFFFD0BFFFDFFE1000003E00001FFF",
INIT_17 => X"7FFFFFFF54FFFFFBFFFFFFC0BFFC9FFE3000001FE000BDFFFFFFF87897FFFCC3",
INIT_18 => X"FFFFFFF19FF21FFE37070000E002807FFFFFFFD2F2FFFF0C9327FFB58A57E12B",
INIT_19 => X"3707000000005B5FFFFFFFE9DC7FFF87795FFF9500D7FFEB7FFFFFFF4FFFFFF8",
INIT_1A => X"FFFFFFFC3B1FFFCDABAFFFA40067FF19FFFE31FFF7FFFFF1FFFFFF14DFE8FFFC",
INIT_1B => X"DBCFFFDC095FFFCDFFFD31FF1BFFFFEDFFFFFE987FF5DFFA6406040000807117",
INIT_1C => X"FFF903FFB7FFFFEBFFFFFD07BFD43FF604992000000013683FFFFFFFA37BFFEE",
INIT_1D => X"FFFFFD89BFF9FFF23BCCC00000002C2FDFFFFFFFEEEF7FF82AFFFF3C9B27FFDD",
INIT_1E => X"275EC801001B73FC7FFFFFFFFEF4BFFDAC7FF966E45BFFFBF0FD83FE77FFFFF7",
INIT_1F => X"BFFFFFFFFF056FFF603FFB6211B3FFDBE72FCBFFEFFFFFFFFFFFFF113FFFFFEC",
INIT_20 => X"ACBFF8005813FFD3F0636FFE1FFFFFFFFFFFFF0BBFCFFFC016970831001964C4",
INIT_21 => X"FF449CFD2FFFFFFFFFFFFA4DFFDFFFA24830E820001024F049FFFFFFFFD77BFF",
INIT_22 => X"FFFFFC447FFFFF404403900040061188BDDFFF9FFFF05D7FC3BFFA206D1FFFDB",
INIT_23 => X"0463614000063FC1DAB1FC5FFFEC045FF39FF490BAEFFFDBFFC091FD2FFFFFFF",
INIT_24 => X"080BFCF7FFFF6577F7DFF1F82A57FFDBCFC2E9FE4FFFFFFFFFFFF48FFFFFFE44",
INIT_25 => X"FBCFF7558CEBFFD907A2F1F95FFFFFFFFFFFEECCFFFFF8700005E0C0E0011E61",
INIT_26 => X"0706ABFBBFFFFFFFFFFFD177FFFFEDAE000520E0303E0AA3E019ABAFFFFFCD59",
INIT_27 => X"FFFF8BACFFFF574E00020000120003682141B4EDFFFFFF08BD6BFB0BCC13FFDE",
INIT_28 => X"0011A0005029544800000E8DFFFFF9229EBBFDAB038BFFDF7F647BF3FFFFFFFF",
INIT_29 => X"00800E8AFFFFFE972783FF9FA507FFC0FEDDFFEDDFFFFFFFFFFFA2EBFFFC7C2E",
INIT_2A => X"BBD37FFE89FFFFA7FE9EFFE3DFFFFFFFFFFF10E5FFFC0A7E001E020001501E00",
INIT_2B => X"EF1C7FE21FFFFFFFFFFE9ED3FFF5DD7E00FF1C00029919B8F384BEAAE7FFFF0B",
INIT_2C => X"FFFD5EDFFFEFD7FE00002000E0C07418E108B00593FFFFBB68AB3FFD8E7FFF79",
INIT_2D => X"00008000F1E28EEEC0013001F5FFFFE5AA9D0CFBC12FF8F7DAD87F92FFFFFFFF",
INIT_2E => X"000B66803CFFFFF24DBC81F7451F1F6327CEBF6BFFFFFFFFFFFD9997FFE82FFE",
INIT_2F => X"63EF6CF3438E7F78C4DD7F55BFFFEFFFFFFE4B97FFF0FFFE00000020F0D3EEF1",
INIT_30 => X"B75CDF2DBFFFC7FFFFFBE7AFFFFFFFFE0000000062B5A40DB806400086FFFFFE",
INIT_31 => X"FFEB2FC7FFFFFFFE3EC000000110DE36C41840317A7FFFFFE79D55E1C2E67F32",
INIT_32 => X"00C00000000F95F0583F6EE9E4D7FFFFFC01F76C00423CF0618C3EE0BFFFCFFF",
INIT_33 => X"24135138006FFFFFFE44CB04E093FB32FEF07E70BFFC0FFFFFF8BFFFFFFFFFFE",
INIT_34 => X"FE75218F8034F173332DB1BC3FFD9FFFFFF8FFFFFFFFFFFE40C0006300100000",
INIT_35 => X"1F97B536FFFA7FFFFF613FFFFFFFFFFE200000F103D972004012481A00927FFF",
INIT_36 => X"FED8FFFFFFFFFFFE2C000061C3ED208006E387F78010DFFFFFD87F5FE0FEF934",
INIT_37 => X"3300008181C27600F81000068060EFFFF7F792C65010F87961E60723FFF87FFF",
INIT_38 => X"9608D600018053FFFFE38768D03C2FC6CB83152D7FF2FFFFFE9AFFFFFFFFFFFE",
INIT_39 => X"FFD0605FF8048AB2497B3C0D7FE03FFFF14BFFFFFFFFFFFE050F000010080089",
INIT_3A => X"8D1FEB96FFA57FFFE0AFFFFFFFFFFFFE7B0000003109388399F9E208030005FF",
INIT_3B => X"E57FFFFFFFFFFFFE780000FF23C99BD6D84E9A240FC78AFFDFD5601EC15B4D40",
INIT_3C => X"31000010233C87EBFF0F092078859AF18FF80002C6B3962F0A3C3020FF5FFFFF",
INIT_3D => X"FFFC0326F202F78E77F80000FFA08EAE1877B25FFE6BFFFFEC7FFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"5FE50100C1A85971C2535319FEA3FFFCD6FFFFFFFFFFFFFE3100000023C7000F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BA63279E3D45FFF593FFFFFFFFFFFFFE71000000F32FFFFFFFFFC40C6250CAD3"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B7FFFFFFFFFFFFFE00030000F1A7FFFFFFFEAAFACA681020E7E50680000C27B1",
INIT_01 => X"00078000BC8FFFFFFFFF3DFFFF2D800144B00FC1C1B7D71A7E00EF73FFCBFFEA",
INIT_02 => X"FFFFFFFFFFF3F50E16401FC5424EC609B100DE52BD5BFFC8AFFFFFFFFFFFFFFE",
INIT_03 => X"01600001A2FD8C66F068A2BE180BFE52BFFFFFFFFFFFFFFA0007800006DFFFFF",
INIT_04 => X"77E5EB4EED37FC26FFFFFFFFFFFFFFFC00060000E33FFFFFFFFFFFFFFFF84720",
INIT_05 => X"FFFFFFFFFFFFFFF200000101F3DFFFFFFFFFFFFFFFFFC3C300F00001236C87CC",
INIT_06 => X"00000043E35FFFFFFFFFFFFFFFFFFF4000010000602BE5D67802D95FBE5FFE35",
INIT_07 => X"FFFFFFFFFFFFFE4003000000C0FEEDEF7F012934A2FFFC57FFFFFFFFFFFFFFFE",
INIT_08 => X"01A0000000E9BB90D306892F3EBFEE4FFFFFFFFFFFFFFF8610800003B85FFFFF",
INIT_09 => X"938642CFC46FACFFFFFFFFFFFFFFFE100080000C6A0FFFFFFFFFFFFFFFFFFF28",
INIT_0A => X"FFFFFFFFFFFFF9C200C001936C70FFF9381FFFFFFFFFFF85200000001815FC37",
INIT_0B => X"00F002B9A91C3FE13BF87FFFFFFFFFE5A000000C181F28900C868B2FE04CB4FF",
INIT_0C => X"0E28E07FFFFFFFE09800C0007002EEE8DFE18C4FBBDCD7FFFFFFFFFFFFFFB80E",
INIT_0D => X"F400800040718C66FF6E28DDFDFFCFFFFFFFFFFFFFFFDB2E06F0158893500E49",
INIT_0E => X"316D0FD99E73FFFFFFFFFFFFFFFCDD0602F026F27D68BEC4010050E1F81FFFFF",
INIT_0F => X"C007FFFFFFFC13D0001C6BCD40772E01F8003F070489FFFFEA0000100044D803",
INIT_10 => X"001CA0940A7F600FF80060870BE4FFFFD7C00000010F200146421EBEFE77FFFF",
INIT_11 => X"FC0601931B8FFFFF92C0000007F5B3937C0052B9FD17FFFEA30DFFFFFFFFFF8A",
INIT_12 => X"9800001F0785C63E400051BEE19FFF0E3811FFFFFFFFFE520079E46DEA77EEFF",
INIT_13 => X"E062057FD07FFC42CCC3FFFFFFFFF0023C0DFACE6C6004FF0080222E0FFFFFFF",
INIT_14 => X"EF97FFFFFFFFEC3E262D6B12800007000007CD3FFFFFFFFF980000060713B135",
INIT_15 => X"00C5E9D381804100002D59FFFFFFFFFC7070000003BC2598C972ADFF37FFFB31",
INIT_16 => X"003BFFFFFFFFFFFF8FF8000408A8F5B6DE40557C9FFFF9A1FF2FFFFFFFFF80FA",
INIT_17 => X"47F80006005B4EF9EE4142773FF4CBDEDEAFFFFFFFFA71C618DFB9C600E01D80",
INIT_18 => X"819145EEFFE6DBBF1FAFFFFFFFE2FDCE2DA4D7C000101C088AEFFFFFFFFFFFFC",
INIT_19 => X"F55FFFFFFF4DACC6080020C0001C7E14493FFFFFFFFFFFF203B00007217BB82B",
INIT_1A => X"7FD90060001CFCBAB3FFFFFFFFFFF80FEA0000060603BB0D40103DB3FFD61D9E",
INIT_1B => X"3FFFFFFFFFFFB38DD54000000FACA85780005EA7FFD6FD20F93FFFFFFD299A84",
INIT_1C => X"4AE100000FF79BB70402F1F7FFC0145013FFFFFFF5BCC7F67FDA4300180C0223",
INIT_1D => X"C0C2557FFFEC0E1FC1FFFFFFAAFD5FF07FEC00003C1C103FFFFFFFFFFFFF06F6",
INIT_1E => X"13FFFFFC4377FFFC7FE20000381C473FFFFFFFFFFFFE9E97FFA000E08A6DF4A7",
INIT_1F => X"7FC8608610001F7FFFFFFF7FFF17358FFF1100FF079C18FB00C16FFFFFF132E6",
INIT_20 => X"FFFFFE339082417FFF4A80031007FEA3204129FFFFED9BA0D7FFFFE53091FCAA",
INIT_21 => X"FF90C10333E0A0AF4023BFFFFFD8812897FFFF54A007FDA27FA0C88338749EFF",
INIT_22 => X"00D00FFF93F42028EFFFFA9093E8F97E7F52480F80061FFFFFFFFC48AF8D04FF",
INIT_23 => X"7FFF92F45F001CFE7F604080ED1FFFFFFFFFFAA7DF1C7DFFFE3EBB0325795A78",
INIT_24 => X"79056380167F7FFFFFFFF94D866E27FFFD6F7C01EC0830A2A04D3FFAAF43A1CD",
INIT_25 => X"FFFFA6DF73D57FFFF3037900592DC7F5008EFFF727AA273FFFF8B3C57FFF3FFE",
INIT_26 => X"E4FFAE0047460F6C000CFFFA3F26F33FFF8C98CDFFFFFFFE634B031083FFC4C3",
INIT_27 => X"8792FFFEFCBFB03FFECF850FFFFFFFFE299A01690FFD5963F7FFCA377F457FFF",
INIT_28 => X"FB34F9FFFFFFFFFE001A00FC3FFEB9A8F8FD10306566FFFFD3FC56983DBFBEA5",
INIT_29 => X"2A5C806FFFFF213CF280C08F65D7FFFF77F8109C619271A78796FF4AC57FF33F",
INIT_2A => X"C76980002E63FFFEDFF5909C45F7EE52064FFE068C7FFFFFE78777FFFFFFFFFE",
INIT_2B => X"5FF5D99C7657C31A00023E8366FFFFFEC7F62FFFFFFFFFFE6B340065FF39818B",
INIT_2C => X"00422EAE63FFFFF287D93FFFFFFFFFFE5608B9587B721C29C5BA27D5D1A7FFF7",
INIT_2D => X"683F7FFFFFFFFFFE1F107909064E1F18A080003A6BBFFFFB7FEDF810778BE778",
INIT_2E => X"025598FD6A3E0FF981000302BC3FFFF5FFEBE9107A8BE4500006B7C4E7FFFF93",
INIT_2F => X"0380030AB2FFFFEBFFDBEA00F333CD90009814B33FFFFCDF8808FFFFFFFFFFFE",
INIT_30 => X"FFDBF6008A9EE9A000017DEFFFFFFA834F347FFFFFFFFFFE7A8398E7E1309EA6",
INIT_31 => X"001F4FFFFFFFEA187F75BFFFFFFFFFFE5E3880C1C0F07DF406C380758FFFFFD7",
INIT_32 => X"7E1A8FFFFFFFFFFE0872607420F0030B0C0020D917FFFE2FFFD3CE00FBFFF383",
INIT_33 => X"5B2C4DC164071D51C001AEA567FFFEDFFF8FF9C1C7FFEE83009897FFFFFFACCC",
INIT_34 => X"01C181F95DFFFA4FFFFFEE609BCFEC0380021FFFFF2DC3FA7E6ACFFFFFFFFFFE",
INIT_35 => X"FFFFF0601E0BFEC100020FFFF948E7533EDD5FFFFFFFFFFE6FFDDA41100F4D07",
INIT_36 => X"1C02CBCF3EA3BFC8DF03CFFFFFFFFFFE17F1C543000E0A07810DBFFE13FFFADF",
INIT_37 => X"CF150FFFFFFFFFFE36283A91000165838FA7FFFC7FFFE13FFFFFC66017F19AE0",
INIT_38 => X"58838C00012C88800FF6FFFFFFFF867FFFFFD1203CE828E01C002BC8C4727F9F",
INIT_39 => X"007FFFFFFFFF27FFFFFF26A0974658011800B7B73E3EBFF6046527FFFFFFFFFE",
INIT_3A => X"FFFF32804DBF90030004EDAFED1EBF39445D2BFFFFFFFFFE04A4451C01461180",
INIT_3B => X"007CCE6FE2C6BFF0E9A633F0FFFFFFFE5D73CA1803931980A3FFFFFFFFFE28FF",
INIT_3C => X"221AA7E9DFFFF3FE66DEC00003C7C60002EFFFFFFFF849FFFFFE06503D2FE003",
INIT_3D => X"759281800367631E243FFFFFFFF1B7FFFFFF78F0AE1FD00380C027FFCF013FD5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"8FFFFFFFFFF24FFFFFFD030A96BFD003800093FF8B907FAF801F0FCDBFFFA9FE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFDDF1AD1B7D001800051FF6CDBBFB2810667D12FFF98FE5CAB03C00CB2DEE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"97808DFFE1D61FC800C69F4BAFFFF712683301000C361F20BFFFFFFFFFE26FFF",
INIT_01 => X"00C7F80F5FFFE9FA6E3603E00E6F7F885FFFFFFFFF281FFFFFFA4FD2FA1984E0",
INIT_02 => X"1A3400E0CEBAF86ADFFEFFFFFEA0FFFFFFFD4F403A3F56520B019FFF79FA5F10",
INIT_03 => X"BFFC7FFFF8C33FFFFFF59EA0583924060C4523CC65FDD7000005016F3FFFCF2A",
INIT_04 => X"FFF66EC390C640200BBDDB7473790A880003EA7FFFFFC6F25C72000A84F0E6E9",
INIT_05 => X"0738F0D31D7EE0F00C211B7FFFFFEDA24894000B00FBD7C1FFF4BFFFE605FFFF",
INIT_06 => X"00008B3FFFFFD17E4B5B0008503E3F7BFFF67FFFDC80FFFFFFE65E8CD6B96030",
INIT_07 => X"4FA30006B03E43FFFFF7DFFFD893FFFFFFFC9E946A50F8060006F10298040D92",
INIT_08 => X"7FC2BFFF2C33FFFFFFF53E15B272F47CA41643C6003025A9600BCA7FFFEFC1EE",
INIT_09 => X"FFFC7FC8423FC15D86184C00008150D2000377FFF8F03FF655D87968A63D67FF",
INIT_0A => X"840F020001C71DF850250FFFF772183E4D680043BD619FFFF5A67FFF484FFFFF",
INIT_0B => X"E127EFFFF70FFFFE5EC0038319E2FFFFE0DC3FF9005FFFFFFFF2FF6366D4D277",
INIT_0C => X"5E483BBB00C1FFFF67997FF1003FFFFFFFABFFCFF451B7F45C51277803C3627D",
INIT_0D => X"DBE5FFFE803FFFFFFF11FE7A1E2C2673B945D0030755C0FCE1AA5BFFF9FFFFFE",
INIT_0E => X"FFABFE6F98A950FDA3E28400002382FF43935DFFFFFFFFF07E276429388B7FFF",
INIT_0F => X"8152A4000C56B7FF738DFCFFCFFFFFF27CC6FE48E867FFFC8FC8FFCB82FFFFFF",
INIT_10 => X"808347FF9FFFFFF274726907230DFFFA938DFF9F843FFFFFFF5BFE82B59C8DFA",
INIT_11 => X"67A271B495FDC2E6A193F8D133FFFFFFFF8FFF3F85B229FF83FE27004BBC96FF",
INIT_12 => X"80B7C3E029FFFFFFFE0FFC7FD4999FFEC2EBFA40E08F38B92054AFFFFFFFFFF2",
INIT_13 => X"FFF7FCB1AFE503FF2177F58062ED3DC6B06E8DFFFFFFFFFE52868DC15C70BFAE",
INIT_14 => X"F3BFFF8009AE2CE5E0D51A7FFFFFFFFE43EAE1BCDE89EB914377E25014FFFFFF",
INIT_15 => X"4E1712BFFFFFFFF24FCFC13F3FEF097DC9D7700009FFFFFFFE0FFEE303D63FFF",
INIT_16 => X"481F381FFF10C211887FA000BDFFFFFFFDB7FBE248DAA3FF406FFE0000C6E828",
INIT_17 => X"1B5FBE042FFFFFFFFEFFF226BC6467FF057FFE00012600A806189ABFFFFFFE02",
INIT_18 => X"FE7FFA11D985C7FF06E7F8BC0095B62D002654BFFE3FFE12553E183FFE3CF031",
INIT_19 => X"061FFFFD018DBC5F4E44085FFE3E3FFE7B3D70FFFB7CF0FCC23F7C045FFFFC3F",
INIT_1A => X"B0CFF22FFFFCBFFE7C74BFFFF187E0FCA1FFA80C4FFF643FFBDFE88C4A81E3FF",
INIT_1B => X"7C747FFFF7F1302077F6583DBFFFC57FFA7FE5A58D610BFFC247FC4F67E07E74",
INIT_1C => X"6FF23033BFFD9CFFF27FE18615EAE37FA001FE1D031CAFFC90F147947FFF1FFE",
INIT_1D => X"F53FF1EC07B2E57F801DFE7C9D94CFFFE50132936FFFFFFE5900FFFFF541A60C",
INIT_1E => X"DC05FD78B44E87FFF98003A13BFFFFFE5B03FFFFFE3CC6005FFC38027FF98DFF",
INIT_1F => X"FCC00079F4F7FFFE790FFFFFFC04B77E1FFA1817FFFDBEFFF57FFC3656F7637F",
INIT_20 => X"781FFFFE9E4263FC3F20009EFFF8F1FFE67FF9357B78E07FEC07FC48A00FBFFF",
INIT_21 => X"5EA00085FFC0EFFFC6FFF712C150A7FFE003FB98601A1BFFB641301FD877FFFE",
INIT_22 => X"F1FFF959820964FFF801F8F9E20065FF82C3E3C1F5CDFFFE7C3FFFFA4DDC0009",
INIT_23 => X"EC017D9B62C31CBFBC0706BFFAF5FFFE7FBFFFFF8B07200B7DF0018BFF884BFF",
INIT_24 => X"F6FF474FFF57FF1E7FFFFFFF69C6830E9A608387FFC015FFEAFFCF19BA3DA2FF",
INIT_25 => X"5FFFFFFEB24534880FC1C17FFF6851FF8CFFC434176306FFF00EFE1C8143CADC",
INIT_26 => X"5DE4E1CFFFCC93FFF2FF2236FE5746FFF40400E600F99B14F536E0AEFFFFFE0E",
INIT_27 => X"65FE347055F7867FF2E0646110550D78F8C195527FFFFF3E7FFFFFFC00042880",
INIT_28 => X"FA61BA5946115033FE499278BFFFFFFE7FFFFE06D4C464CCA7E0617FFE5D87FF",
INIT_29 => X"FF8293B93FFFFFFE7FFFC6375E45CE5BB2F0193FFF7DE7FF6DFC0003A00FE1FF",
INIT_2A => X"7FFFD920EBBB7CF3001C0EFFFD3CFFFFC5FE5802B807A13FF920D987EEAA5F57",
INIT_2B => X"0108079FFEE00FFECFFAC420382B41BFFDB1D525E11E6C46FFFB4FF0DFFFFFFE",
INIT_2C => X"1BFEF6713B0D163FFC71B0C5EE063DCC7FFFEE8C9FFFFFFE7FFFD8D9B4F1FA70",
INIT_2D => X"FEC013F9FC84E6933FFFE8B07FFFFFFE7FFFEE3AE3CA510081011D7FFE416FFE",
INIT_2E => X"FFFFF66C8FFFFFFE7FF87179D0163C00D303C5FFF9415FFF1FECD0E034489F4F",
INIT_2F => X"7FFC3F1C7A15E1300D4183FFFA013FFC1FE0B0B104999F2FBE80F7C7FEDBC681",
INIT_30 => X"8A801FFFCC12DFF84BC14270815FDE7E7EE6CB4DFFD8C374CFFFF4F7EFFFFFFE",
INIT_31 => X"D85E88E48419302F414C4F96FF7C9FA7E7FFF8AD6FFFFFFE7FFFFF100428ED9D",
INIT_32 => X"102C33F5FFDD0FC24BFFFF84CFFFFFFE7FFFFE3E615B7D8EE80013FF1CD17FF8",
INIT_33 => X"A9FFFFA0FFFFFFFE7FFFFFFFE20D0220D7003FFF9241FFF8583CBC8580533021",
INIT_34 => X"7FFFFFFFF94B79D67F011FFEA0427FFAE4FF1C9CE00550139EE81BD0FFA13FE9",
INIT_35 => X"861C2FFD0040FFF8D6BA3DF8818598A871460B41FFC877FB3BFFFFD81FFFFFFE",
INIT_36 => X"A0707E7DA194F8B6544EC037FFAC13FFB9FFFFFA27FFFFFE7FFFFFFFFCBF8BF6",
INIT_37 => X"0307CDC7FF012FFE3800FFFEB33FFFFE7FFFFFFFFCD067FA47E30F073841FFF0",
INIT_38 => X"E3C3FFFF226FFFFE7FFFFFFFFDA71FF95AB9FCA338407FE9B1F278B520183808",
INIT_39 => X"7FFFFFFFFEAFBFFCB112BE9F390B7FFD55F3725BC100F85CAF8707F7FEB0F27F",
INIT_3A => X"80E43E520782FFE15FF334FEE008C000476200DFFFC7558FE2607FFFE8730FFE",
INIT_3B => X"4FE334F680081800FE9E82C3FFFF90C7BA8A7FFFEC10CDDE7FFFFFFFFEAA7FFE",
INIT_3C => X"7FAC016FD7FD60C3EEB73FFFFAB1642E7FFFFFFFFC33FFFDA524FD8A0004FFC8",
INIT_3D => X"7A5DFFFFFE8E1ACC7FFFFFFFFD1FFFFE8D267FB880B7FFD87FF82DFEE80A1800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFE43DFFFF1BA2FE8F80F4FFAB7FEC13F4100600009FEC0143E7FE0A20",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"47ADFFC9C023FFA0FFCA03F4A40600007FD801E0F1FF06D6FDE3FFFFFFAB25E4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFE4C6FFFFFFFFFFFFFFE492AFBAAF03FFFFFFFFFFFFFFFF900036FFFFFFFFD",
INIT_01 => X"FFFFE04005BFEE3D1B90000400CF000007FFFEB400019EACBB8BFFFFF77EC87F",
INIT_02 => X"3FFFFFFFFFFFAAA950F001BFFFFFFFFED41554FAFFFF8740F0000C7EFFFFF816",
INIT_03 => X"17FFFFB243007BFB678FFFFFFD34162FFFFFEABFFEFFFFFFFFFFFFE34150EBF0",
INIT_04 => X"2A55140AFFFE693000003C8EFFFF9447FFFFD603CFFFD7D89590000000FF0000",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF9E5AFD1303FFFFFFFFFFA00000FF006FFFFFFFFFE",
INIT_06 => X"FFFFB83CE5FFE6A8B550000000C3C0005BFFFFF623C023FA228FFFFFFE93AADF",
INIT_07 => X"3FFFFFFFFFF900000FFF1BFFFFFFFFFE3CE5555EFFF9043C000301C8BFFF30AF",
INIT_08 => X"5BFFFFFFB8001DFE1E9FFFFFFFFA502FFFFFFFFFFFFFFFFFFFFFFFFF496C0490",
INIT_09 => X"F0E55423FFE7B0000000044CEFFE51AFFFFAB4F327FFFE6FBD00000500000000",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFF939BC5E03FFFFFFFFFFF95013F006FFFFFFFFFFD",
INIT_0B => X"FFE2D0F0CFFFFE6FDB0003C0000000005BFFFFFFEA016DBF03DFFFFFFFFE69AF",
INIT_0C => X"3FFFFFFFFFFFFA900F00BFFFFFFFFFFDF039558BFFE1E0000000CADF4BFCB43F",
INIT_0D => X"43FFFFFFF541FCBFC01BFFFFFFFE596FFFFFFFFFFFFFFFFFFFFFFFFFF93AA0FC",
INIT_0E => X"0039566FFF9B403CF003CF75DFFA7FBFFFD740301FFFFE6FF43003F000000000",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFF925BC43FFFFFFFFFFFFFE50006FFFFFFFFFFFD",
INIT_10 => X"FF593031AFFFFA6FBA8000C00000000025FFFFFFFC12FC6FF05BFFFFFFFA031F",
INIT_11 => X"3FFFFFFFFFFFFFF90C1BFFFFFFFFFFFE00E958BFF9DD003FF0030F90BFF45AFF",
INIT_12 => X"CFBFFFFFFF36F01BF1ABFFFFFFE93EDBFFFFFFFFFFFFFFFFFFFFFFFFFFF895B0",
INIT_13 => X"40E5B2FFE190003FF00F0FAAFFFE47FFFF303001AFFFE96FFC60C00000000000",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFA3A683FFFFFFFFFFFFFF90C6FFFFFFFFFFFFF",
INIT_15 => X"FEF3FF02FFFFE16FFE180003000000000A7FFFFFFF99FFCB02FFFFFFFFE93F16",
INIT_16 => X"3FFFFFFFFFFFFFF9016FFFFFFFFFFFFF90EACBFFD60C000FF00FC0BFFFE1BBFF",
INIT_17 => X"053FFFFFFFCDBFC6F2FFFFFFFFE90056FFFFFFFFFFFFFFFFFFFFFFFFFFFF9394",
INIT_18 => X"90FADBFFB10F0000C00FD5FFFFC91FFFFEF3FF033FFFDC6FFF81000F000000F0",
INIT_19 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A83FFFFFFFFFFFFFE905AFFFFFFFFFFFFF",
INIT_1A => X"FDA0C0033FFFC82FFFEF0000000003F0C42FFFFFFFEAAF15B2FFFFFFFFE555AB",
INIT_1B => X"3FFFFFFFFFEBFFE906AFFFFFFFFFFFFF903FDBFFBDFCC003000F16FFFFA6BFFF",
INIT_1C => X"DE7FFFFFFFF06C55B1FFFFFFFFE6AAFFAFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0C",
INIT_1D => X"903C1BFF580CFC0300031AFFFF467FFFF8633009BFFFD46FFFF640C300F00FFC",
INIT_1E => X"FABFFFFFFFFFFFFFFFFFFFFFFFFFFF943FFFFFFFFFAAFFE506BFFFFFFFFFFFFF",
INIT_1F => X"F6900013BFFF702FFFFB9000000003C063BFFFFFFFFBAC55B2FFABFFFFEAAAFF",
INIT_20 => X"3FFFFFFFFE9AFE941BFFFFFFFFFFFFFF903C6FFF1800F00000002EFFFFF47FFF",
INIT_21 => X"777FFFFFFFFD2855B2FE5BFFFFFAFFFFFEABFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_22 => X"4031BFFF6D000000000333FFFD56BFFFDA00003DFFFFE02FFFF91030001503C0",
INIT_23 => X"FFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFE5BFE405FFFFFFFFFFFFFFF",
INIT_24 => X"C0F0C057FFFF8C2FFFFD6030002A5401B62FFFFFFFFEF850B2FE07FFFFFFFFFF",
INIT_25 => X"3FFFFFFFFEABFA406FFFFFFFFFFFFFFF4031FFFFB1030000000333FFFB1BFFFF",
INIT_26 => X"C12FFFFFFFFF5C54A1FE07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_27 => X"4006FFFF81030000C0032EFFEDDCFFFF6CF0CCBBFFFF4D6FFFFE18000070EA41",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFBFFFA55BFFFFFFFFFFFFFFF",
INIT_29 => X"B403CCCFFFFE0D6FFFFFBDF000753BD7C1CBFFFFFFFFF5556CBE1BFFFFFFFFFF",
INIT_2A => X"3FFFFFFFFBFFEA95FFFFFFFFFFFFFFFE4007FFFF71000154F003D5FFD7A0FFF8",
INIT_2B => X"F16DFFFFFFFFE25A5B6A1BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_2C => X"001BFFFF2D316AA4F0030CBFD7F5FFF5900FFC0FFFFECDBFFFFFC75700614C3B",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFBFFFA56FFFFFFFFFFFFFFFA",
INIT_2E => X"803FF11FFFFDCDFFFFFFE238002D403FC132BFFFFFFFFB5A5B291BFFFFFFFFFF",
INIT_2F => X"3FFFFFFFFBFEAA5AFFFFFFFFFFFFFFF90F1FFFFEDE47FFF4F0030CFFE94AFFF9",
INIT_30 => X"F12DBFFFFFFFFDEBA6C51FFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFC",
INIT_31 => X"031FFFE98E703EF9000C10FFE261FFF54000F2EBFFFC8E3FFFFFFF63AA5C503F",
INIT_32 => X"FFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFC3FFFFFFEBFEAA56BFFFFFFFFFFFFFFE9",
INIT_33 => X"4C00F33FFFFF7DFFFFFFFFB4FEAB54000577BFFFFFFFFE7EFAB01FFFFFFFFFFF",
INIT_34 => X"3FFFFFFFFFAA956FFFFFFFFFFFFFFFE9401AA5433A89FAFE40006AFFD2616FEB",
INIT_35 => X"4699FFFFFFFFFF9EBE6F1FFFFFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFC",
INIT_36 => X"4000FAFE3AD9FFC3E40182FFDEB10BBC3F00F3AFFFF931AFFFFFFFB4039A155B",
INIT_37 => X"FFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFC3FFFFFFFFE965AAFFFFFFFFFFFFFFFF9",
INIT_38 => X"FF00321FFFF4006FFFFFFF89025A1AAC96EEFFFFFFFFFFE2BE6B1FFFFFFFFFFF",
INIT_39 => X"3FFFFFFFFA556ABFFFFFFFFFFFFFFFFE413901BE4E280015340737FF9FB15B34",
INIT_3A => X"D5A2FFFFFFFFFFF7C3AACBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_3B => X"052E98C3E078155549122FFE4FF1AEA3FC00075FFFFA001FFFFFFFD8C35B6FAC",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFEA5ABFFFFFFFFFFFFFFFFFFE",
INIT_3D => X"0000C92FFFD104CFFFFFFF866FECB0EB21B6FFFFFFFFFFF9FFAAB2FFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FFFFFFFEAAAFFFFFFFFFFFFFFFFFFF90A7D091944B85AA40964BFFF7FF6EAA3",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"3986FFFFFFFFFFFE3FE66DFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram : RAMB16_S4_S4
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"443444443358DFFFFFFFEB7555656AEFFFFFFFFFFFFFEC8545688789BBCDCBBB",
INIT_01 => X"CDFFEDA74469DEFFEDA9AA999AABBB988865679CEFFFFFFFDCBBBCEFFFFEB743",
INIT_02 => X"8FFFFFFFFFFFFFFFFEEDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_04 => X"BBBBCDEEEEFFFFFFFFFFFFFFFFFFFFFFDCBBBA9AA9ADFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"443344444347CEFFFFFFDA66667659DFFFFFFFFFFFFFFD975568989ABBCDDCBC",
INIT_06 => X"DEFFFEB9778ADEFFFEBABA999AABCBA98877779CEFFFFFFFECBBBCEFFFFEA644",
INIT_07 => X"8FFFFFFFFFFFFFFFFEDDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_09 => X"BBCCCDDEEEFFFFFFFFFFFFFFFFFFFFFFFEDCBBA999BDFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"443334444446BEDDEFFFC877778757CFFFFFFFFFFFFFFECA87898788AABDEDCC",
INIT_0B => X"DEFFFFECA9ACCDFFFECBAAA99ABBCCA99A97789CEFFFFFFFECBBBBEFFFFDA754",
INIT_0C => X"8FFFFFFFFFFFFFEEEEDCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_0E => X"ABCCCCDEEFFFFFFFFFFFFFFFFFFFFFFFFEDCCBAA99ADFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"443444554457BCBACDFEB878888767BEFFFFFFFFFFFFFFECCA99878889BDEDCB",
INIT_10 => X"EEFFFFFECBCDDDFFFEDBBBAAABBCCCBAAA98878ADEFFFFFFECCCCCEFFFFC8776",
INIT_11 => X"8FFFFFFFFFFFFFFEDDDCDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_13 => X"AACCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCBBBAAADFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"44444567557BDDB99CEDA889A99866AEFFFFFFFFFFFFFFFEEDBA98999ACDEEDB",
INIT_15 => X"EFFFFFFFEDEEDDFFFEDBBBBBBBBCCCBAAA99989ABCDEFFFFECCDDDEFFFFC9996",
INIT_16 => X"8FFFFFFFFFFFFFFEDCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_18 => X"BBBCDCDDFFFFFFFFFFFFFFFFFFFFFFFFFFFDCCCCBAADFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"44334688659DFECAACEDA89BBAA9879DFFFFFFFFFFFFFFFFFEDBAABABCDEEEDC",
INIT_1A => X"FFFFFFFFFEFFEEFFFEDCCCCBBBCCDDCBBAABBBAAAAABCDEEDCCDDEFFFEECCDB6",
INIT_1B => X"8FFFFFFFFFFFFFFDCCCCDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_1D => X"CBCDEDDDEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCCCBAADFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"4333479A87BEEEEDDEFDA9ACBBAB978BFFFFFFFFFFFFFFFFFEDCBCDCCDEEEEED",
INIT_1F => X"FFFFFFFFFFFFFFFFFFDCDEDCBCCDEEEDCBBDEDCA9888ABCDDCCDDDDDCBBCDEB6",
INIT_20 => X"8FFFFFFFFFFFFFECCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_22 => X"DDDEFFEEEEFFFFFFFFFFFFFFFFFFFFFFFFFEEDDCAAACFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"444469BB99CFFFFFEFECAABCBBBBA76AFFFFFFFFFFFFFFFFFEDCBCDDCDEFFFEE",
INIT_24 => X"FFFFFFFFFFFFFFFFFEDDEEEDCCDEFFFEDCDEFFDB876679ABCCDEEDB9778BED96",
INIT_25 => X"8FFFFFFFFFFFFEDCCDDEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_27 => X"EEEFFFFEEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFECAAACEFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"44458BDC9ADFFFFFFFDBABCCBBBBA76AEFFFFFFFFFFFFFFFFFECCDDDDDEFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFEEFFEEDDDEFFFEDDEFFFEB7555679BCCDEEC96457ADB75",
INIT_2A => X"8FFFFFFFFFFFFEDCDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2C => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2D => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2E => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2F => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(3) => BU2_doutb(0),
DIA(2) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(3) => BU2_doutb(0),
DIB(2) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED,
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED,
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"00F00035BD17F3F60026AA0005DFFFFD080000000C000A620000000000000000",
INIT_02 => X"C04A50000C3FFFFDC000000000000CA27FFFFF537FFFA01F80006840108C0000",
INIT_03 => X"280C00000003DCA26FFE00105FFFB3C0000084B001CF000600E000119D1B83F3",
INIT_04 => X"43FC001653FF83C007DF803E6FEC006130000000622B1FEEA05220000D7FFFFE",
INIT_05 => X"07C0C060039AC80030030000122BD0F7D1F5E000057FFFFFD96C0000000227AE",
INIT_06 => X"000300F1326BF376E1FAC000037FFFFFE00000000002002E4078F8B2197FAAC0",
INIT_07 => X"62CC12020A7E3FFFE004000001070C3E4000FFF362C7EC710700F06E05F4AB08",
INIT_08 => X"E00C0000E01C19DC60E7FFC30089F2000301006E050B9C0500010001C2E7E9AC",
INIT_09 => X"7CFFC0863475F308C000C60007CC6FF10000C00E02F5A8B638B190000C703FFF",
INIT_0A => X"70008E0015ED4FF8494970000093C03F894082000DC3BFFFE11C0000D876CC1C",
INIT_0B => X"0F8380001204844FED9C03000CB23FFFF11C0000C3687FFE7F3FF2068871FD92",
INIT_0C => X"0230000004413FFFFC1C000042A7FFFE7FBFE7C6A465FE8660008E00D9128FFD",
INIT_0D => X"F40C0000447FFFFE7F9BEE6D32DBFEA6000004FF1787EFFE0F0200E016848450",
INIT_0E => X"7F8CC838C667FEE30000000302EC4FFFDEA20CC00B05B0487460000000AB3FFF",
INIT_0F => X"000000002E5FE7FEB1C00EC7C003B04508E0000008B3FFFFF00C000004CFFFFE",
INIT_10 => X"CD70C1036280781AF0E0000003C37CFFF00C0000050FFFFE7F06C818DE8FFE82",
INIT_11 => X"E003C0C086C67AFFF00C0000072BFFFE7FE7CC18330FFF8E0080000005E97387",
INIT_12 => X"EC040000000DFFFE7FF1CF000CF7FFB000801F007CF6EFFE765901006708083C",
INIT_13 => X"7FFCC78042E7FFD240000E00FE3AF21DFFBCC00000D440046003F8C10799FDFF",
INIT_14 => X"600000037FFCDE07FB9460013110082A7D07FA01C0A2FBFFE400C000010CFFFE",
INIT_15 => X"FECC11023B75F03D381B4001C0BFF2FFE5E7C00801C57FFE7FFCE7840D801FFA",
INIT_16 => X"C16AA1C1043DF0FFE6E0000405E2FFFE7FF8E7180D842FFC200000016FFFFFFF",
INIT_17 => X"E5D800006DF1FFFE7F83E3800D4C2FFE400000000FFFFFFFFC97687018F9D0C2",
INIT_18 => X"7F3000E000890FFF638000000FFBFFFBFDE0F27819FED23C312EBCA0064FFCFF",
INIT_19 => X"B3C000007F3DFFF9FC6F053003FBD0BFD0B13E5F00B1F4FFE9C00060DFFFFFFE",
INIT_1A => X"FCAFFDB0006851E5706FC04680DEE1FFE9E400605FFFFFFE7E4E75300002C1FF",
INIT_1B => X"1014F879BEFFC3FFE8BC00615FFFFFFE7E6C0368000086FFF80000001F42FFFC",
INIT_1C => X"EA8C01C17FFF79FE7F9A0C3400003ABFFA0000001F6037FCFC5FFFA0C02C5159",
INIT_1D => X"7FE50D7400606047F80000001E3C40FCF96FFF9080B2502A200DFC153EFB13FF",
INIT_1E => X"FDB00007FE82AF3C7A8DFFF4C23C5384A409D87F007C67FFEA8C0183FFFFFFFE",
INIT_1F => X"DE04FFF500FE50824011F878007D07FFEB9C1F83FFFFF1FE7FFD41B300000D47",
INIT_20 => X"5192FDFEF13A03FFEDB00101FFFFFCFE7FFFC058380001407E40000F0E2447C0",
INIT_21 => X"EDA9000AFFFFE8FE7FFF642FD40F00C75E00001E07BF073FEC78FFFDD4BCC3F5",
INIT_22 => X"7FFF902EF40F008085BC000013E453873CB9FFFE8005B7F8C1D37FF031BA0FFF",
INIT_23 => X"A37CC0000FDB97581A1A7FFF608415893014FFFE070D17FFD3408015FFFBC2FE",
INIT_24 => X"090B2FFF808426FF092BFFF70FA307FFB0874023FFF7F2FE7FFFE81EE0060340",
INIT_25 => X"0C57E62007C30FFFB2537FCFFFE782FE7FFFD41B280000389C7FE0C017E3BFD0",
INIT_26 => X"702A602FFFFB00FE7FFFE246C6000001C300FFC0F0F727E0020229FFE8800400",
INIT_27 => X"7FFFFA2FCBC00618246003E0FFFD27900C8205FFE460059FF20FC3C20CCA9FFF",
INIT_28 => X"5759E078DE7E98C80082019FF27C087FFDFE05007CFE2FFEE33E0C5FFFCF027E",
INIT_29 => X"38418837F93C06BFFB3E05000C970FFDC0FDFCBFFFD7247E7FFFFE3FE1F00188",
INIT_2A => X"FABE34C08DBE3FFDE3FCF8BFFF20714E7FFFFFFFF2CC18017FA9F03C414F71F4",
INIT_2B => X"F7FC087FFFC01C067FFFFFFFFAF1BE335FD63C1F4069B37478619503FD80083F",
INIT_2C => X"7F0191FFFE1544001F1A3E07C25A72B5667096CFFFC0ED7FF6FE3AC14C3C5FFE",
INIT_2D => X"7F828E0385CA8E3382381F853F6103FFECFC7EC014701FFE7BFC057FFE10FE52",
INIT_2E => X"039405EE6799B7FFCFF2FFFF6FEEFFFE4BFEF57FFD907F7A7FC7D1FFFFF4A001",
INIT_2F => X"E3A6FC397FF8BFFC97FFFF7FFC71FFE67C6A01DFFFFC6C027FFD960103EF58C2",
INIT_30 => X"2FFFFA7FFD717FF86FBD84503FFC400DFFFFD000B1AC464F87D604F037A13FFF",
INIT_31 => X"017F23182FFE1396FFFFF800C1BF1202430E0A7FE635FFFFF38DFD3BA870BFFD",
INIT_32 => X"FFFFF86070FFCAD1A14464FFFF0BFFFFFBFDFCFDC0D0FFFD5FFFFAFFF920FFF8",
INIT_33 => X"10460467FFF0FFFFF03CF0FEF2B1FFFD7FFFFAFFF630FFF8106FA9701BEF112F",
INIT_34 => X"EE01C6FF9BE17FFD7F7FC6FFE407FFE4386FEA7C6A0FF91FFFFFFE1830FFC988",
INIT_35 => X"7E0025FFF801FFE4100BFF04E66FFF1FFFFFFC9C03FFED2A28498C35FFFDBFFF",
INIT_36 => X"03B1FD80C069FECFFFFFFEC0007FFDF2344A880EFFFEBFFFD29FB17FE7117FFE",
INIT_37 => X"FFFFFF60013FFE1DD4498901FFFF5FF8163FB97FCAD07FFEDE0073FFE00FFFE0",
INIT_38 => X"F24001C0BFFF6FC0D23FB87FD720FFFF1EF357FFC123FFD801C5FFD17E8AFEAF",
INIT_39 => X"EA7FB1FFD7B0FFFF8CF357FFF007FFC871807FE72182B427FFFFFFF100DFFF0F",
INIT_3A => X"AD9757FFEC1FFFE007113FE0078034D47FFFFFF9B26FFE3FF81041C08FFF1031",
INIT_3B => X"00103FE024F03008BFFFFFF0800FFE87FC1801E167FEE947FAFFAFFFDE12FFFF",
INIT_3C => X"5FFEFFF800A7FF13FB2010F054BEE99FF8E72FFFFA33FFFFF11FAFFF840FFFD0",
INIT_3D => X"FEB0D0F059BF483FF787AFFFE522FFFFB32FB7FFA43FFF203C003FF373E80003",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"F3C0BFFFC020FFFF6B7F8FFFE4FFFE801CF09FFA7A003C00DFFE1FFC805BFF4F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"EBE78FFF04BFFC407CFB0FFD73197C000BFF5FFFD009FFE1FC41507046BFB9FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F9A87DE39A23C0009FF9FFF6306FFE5FF87507038BF87FFFB80FFFFEA23FFFF",
INIT_01 => X"017F8FFFEB837FD5FF03500608BFFFFFF9085FFFF6A7FFFFDB171FFFC0FFFA80",
INIT_02 => X"FFF4400D0C80FFFFF800FFFFFD81FFFFFB1A3FFFC07FFD427FFF5CFFDFFA8C00",
INIT_03 => X"FC01FFFFFD0FFFFF371AFFFE03FFF2447FFFEEFF77FE4C00019FDBFFE4C1BFD1",
INIT_04 => X"0F1BFFFE80FFF24A7FFFFFFF34CFCC7FC027F8FFF6005FF1FFFDC0043880FFFF",
INIT_05 => X"7FE31FFF2318DCFF601BFCFFF9181FFFFFF900073FC3FFFFFC03FFFFFD0FFFFF",
INIT_06 => X"E06BFFFFFCDC5FFFFFF90C6DE007FFFFFCC7FFFFF90BFFFF1899FFFE05FFF2C8",
INIT_07 => X"FFFA84A3E787FFFFF8FFFFFFF61BFFFF90B9FFFC05FFF0CC7EE0D770449C0427",
INIT_08 => X"F9FFFFFFCA07FFFFB773FFFF43FFEC167BE01F1EEB2385DC40023FFFFFAF2BFF",
INIT_09 => X"B723FFFB4FFFD46A4A09001FB85E417D0008AFFFFFD789FFFFFBF2D2C787FFFF",
INIT_0A => X"58D101403ADC09FCA18027FFFFEFC6FFFFF30C4EBC70FFFFF1FFFFFFB43FFFFF",
INIT_0B => X"94004DFFFFEBF37FFFF632FD00006FFFF3FFFFFF544FFFFFA64BFFF807FFB4A6",
INIT_0C => X"FFF90EF887F86BFFF3FFFFF9FA7FFFFF5D1FFFFE1FFFA85E43F00030E2C02FFF",
INIT_0D => X"E7FFFFFBEA1FFFFF5E1FFFF027FFB13E27000099E1326FFFF50004FFFFF9F93F",
INIT_0E => X"5A9FFFF40FFFE2BE3000668000F863FFFDA081BFFFFC689FFFFFF0F8A71895FF",
INIT_0F => X"00006400000017FFFFC4209FFFFE844CFFFFFE7B7F0409FFC7FFFFFB8CFFFFFF",
INIT_10 => X"FF581C5FFFFFAE2EFFFFFE166F4601FF8FFFFFF8643FFFFF421FFFE05FFFE97E",
INIT_11 => X"FFFFFE0E8F5D65FF8FFFFFFFE5FFFFFF4F9FFFE85FFF267E001CF80010704FFF",
INIT_12 => X"9FFFFFFFF07FFFFFF07FFFF01FFEF1FE0000F80011009FFFFFCC061BFFFFD31B",
INIT_13 => X"8FFFFFC03FFE2FFE01000010010137FFFFFEB809FFFFF5CD3FFFFE3AEF5AA7FF",
INIT_14 => X"4100003C00018BFFFFFFD4057FFFFAE6410FFFBF5D9CC0FF1FFFFFFFCF7FFFFE",
INIT_15 => X"FFFFFFC15FFFFD313FE7FF8D21EFDD7F7FFFFFFFFCFFFFFE3FFFFFF07FFD5FFE",
INIT_16 => X"1E37FFB0064FDF3FFFFFFFFF9EFFFFFC7FFFFF807FFA7FFE2000003E00029BFF",
INIT_17 => X"FFFFFFFFD1FFFFFCFFFFFFE07FFA3FFE2000001FE0027BFFFFFFFC505FFFFF9C",
INIT_18 => X"FFFFFFD07FF8BFFE27070000E0018BFFFFFFFFF519FFFFAFB3EFFFE9841FFE1C",
INIT_19 => X"270700000000303FFFFFFFF266FFFFD7D64FFFC9009FFF1CFFFFFFFFC5FFFFFF",
INIT_1A => X"FFFFFFFF91BFFFE9F7DFFFE8003FFFFFFFFFFFFF4BFFFFFFFFFFFF103FF45FFE",
INIT_1B => X"CFFFFFA80627FFF3FFFE1FFF4FFFFFF3FFFFFF54FFE8BFFE340604000080020F",
INIT_1C => X"FFFDDFFFA7FFFFF7FFFFFF8CBFFAFFFE5461200000000067FFFFFFFFD4D7FFF4",
INIT_1D => X"FFFFFC0ABFDBFFF050CF0000000014203FFFFFFFF415FFFD21FFFF840A07FFE3",
INIT_1E => X"48C0F001001B2CFFDFFFFFFFFC4E7FFEA2FFFE44115FFFE7FFF65FFFFFFFFFFF",
INIT_1F => X"AFFFFFFFFFABDFFFC17FFC5C711FFFE7F8CB9FFE4FFFFFFFFFFFFF023FC7FFF0",
INIT_20 => X"EC3FFFF03883FFE7FFB4FFFE2FFFFFFFFFFFF82FFFFFFFF818701031001927C7",
INIT_21 => X"FFA86FFF3FFFFFFFFFFFFA047FFFFF90700FF0200010180017FFFFFFFFECD7FF",
INIT_22 => X"FFFFFE3DFFFFFF400400600040000E08943FFFFFFFFAB4FFF3DFFDF01C8FFFE7",
INIT_23 => X"0460014000001101C96FFF4FFFFEBD3FEBAFF838299FFFE7FFB06EFF3FFFFFFF",
INIT_24 => X"07E6FDE7FFFFAB2FFDDFFBEFAF4BFFE7FF907EFD1FFFFFFFFFFFF419FFFFFD84",
INIT_25 => X"FED7FB628B1FFFE7FFA22FFC1FFFFFFFFFFFF2FAFFFFF574000300C0E0010941",
INIT_26 => X"FFE027FE5FFFFFFFFFFFF8AAFFFFD9980003C0E0303E0633E0076113FFFFE6CB",
INIT_27 => X"FFFFC1E1FFFFC77A0001F800120000F0214076EFFFFFF5FA7F6FFC7805F7FFE1",
INIT_28 => X"001064001010D8300000008FFFFFFD3E3FB3FF27C687FFE0FF0387FA5FFFFFFF",
INIT_29 => X"0080008DFFFFFFD8AF45FFFFC27FFFFFFFDBFFF67FFFFFFFFFFF9065FFFEDCDE",
INIT_2A => X"6FA2FFFF4A7FFFDFFFD9FFF47FFFFFFFFFFFE3EFFFFC86BE001E240000C69400",
INIT_2B => X"FED8FFF5BFFFFFFFFFFFA0FBFFFB34FE00FF0000016F9238F383C0A17FFFFFAC",
INIT_2C => X"FFFE67FBFFF5DFFE00002000E2E8FCE0E104200397FFFFD39DD17FFF8C7FFF87",
INIT_2D => X"00008000F22C8508C004200017FFFFF6C470BFFF417FFF01E41BFFE5BFFFFFFF",
INIT_2E => X"00078680C7FFFFFC93085FFE449BFF80C18DFF8CBFFFFFFFFFFC73D7FFF01FFE",
INIT_2F => X"B4AC23F1C15A3F80019C7F98FFFFFFFFFFF92FD7FFFFFFFE00000020F205E5FA",
INIT_30 => X"711C1FB0FFFFFFFFFFF63FC7FFFFFFFE0000000061599DF600028000037FFFFF",
INIT_31 => X"FFFBCFFFFFFFFFFE3EC0000000E0463838057FC179BFFFFFF24E33FDC1C2BFFB",
INIT_32 => X"00C000000000BE003C1DA131E48FFFFFFAEE0DE00001FFFAD64C4F41FFFFFFFF",
INIT_33 => X"18318FD0002BFFFFFC83EAE0008E7CF928403F31FFFFFFFFFFD0AFFFFFFFFFFE",
INIT_34 => X"FFA32D64906DF8F817B1BEBD7FFE7FFFFFA05FFFFFFFFFFE00C0000300080400",
INIT_35 => X"0419BEB57FFC3FFFFFC07FFFFFFFFFFE4000000103CB4200400E7812008AFFFF",
INIT_36 => X"FF82FFFFFFFFFFFE30000001C3E7B88006E0000780127FFFFFEF5228D051F0FB",
INIT_37 => X"4400008181C47C000010000680607FFFFFFC2146404E300483E73EA17FFC3FFF",
INIT_38 => X"98082600018027FFFFFF00DF600357C0706CDF22FFFBBFFFFD09FFFFFFFFFFFE",
INIT_39 => X"FFE3603F0003A3708E17ED02FFF77FFFFA27FFFFFFFFFFFE760F00001001F908",
INIT_3A => X"0E0A1E8BFFCBFFFFF45FFFFFFFFFFFFE7C00000030FFC2FF61060200030017FF",
INIT_3B => X"C83FFFFFFFFFFFFE000000FF21031B0E20B01A180FC003FFFFF66000C1486E3F",
INIT_3C => X"3100001021CB00E7FFF188E47883E4FFFFC00000C698400F0C06FA1DFF92FFFF",
INIT_3D => X"FFFE00EC0C01FA8E8FC00000FF8786F16C02843DFF75FFFFB2FFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"CFD90100C18F278054213B3BFCC5FFFF6DFFFFFFFFFFFFFE3100000021F7FFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0800E7BDF987FFF9F7FFFFFFFFFFFFFE71000000F1B7FFFFFFFE00F41C9031DF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6FFFFFFFFFFFFFFE00030000F00FFFFFFFFFBBFC3CB000004FD90680002B7800",
INIT_01 => X"00078000BCBFFFFFFFFFBBFFFFD800012BC80FC001605801B0001F3F3B83FFF3",
INIT_02 => X"FFFFFFFFFFE4CE0E0D901FC482615C07FE003E3BD98FFFEF9FFFFFFFFFFFFFFC",
INIT_03 => X"00800000C25042037E687E746D17FF9E7FFFFFFFFFFFFFFE00078000063FFFFF",
INIT_04 => X"FE6476CB3E1FFF3DFFFFFFFFFFFFFFFA00060000031FFFFFFFFFFFFFFFFF7D20",
INIT_05 => X"FFFFFFFFFFFFFFF800000100E3DFFFFFFFFFFFFFFFFFFD8300F00000C3309650",
INIT_06 => X"000000410B5FFFFFFFFFFFFFFFFFFEC0000100008032C86AFA81E4C2FECFFCF3",
INIT_07 => X"FFFFFFFFFFFFFF2003000000003578603A83448E3EBFF9CFFFFFFFFFFFFFFFF4",
INIT_08 => X"01A00000003C1A0D7A82C49FE2FFF63FFFFFFFFFFFFFFFE810800001745FFFFF",
INIT_09 => X"F50289DFDCE7CDFFFFFFFFFFFFFFFFA20080000D287FFFFFFFFFFFFFFFFFFF90",
INIT_0A => X"FFFFFFFFFFFFFE8400C00010DA0FFFFEFFFFFFFFFFFFFFD620000000183066CC",
INIT_0B => X"00F00136642FFFFAFC17FFFFFFFFFFF6C000000C18063E54F9020F1F5F6B33FF",
INIT_0C => X"F0185FFFFFFFFFFF3000C00070011C70EA650C3FED74CFFFFFFFFFFFFFFFC218",
INIT_0D => X"D00080004073C0074A6B2C3EDEB73FFFFFFFFFFFFFFF1CE206F013014E4F4F72",
INIT_0E => X"FA6A0A3DBF48FFFFFFFFFFFFFFFF1CF202F0299724607FF80100CFE007FFFFFF",
INIT_0F => X"FFFFFFFFFFFFEFF4001C10A239770001F80000FF0387FFFFF800001000425801",
INIT_10 => X"001C1738377F600FF8006080F8E3FFFFE1C00000011E800544400A7BBF73FFFF",
INIT_11 => X"FC060070F87FFFFFD8C0000007D3E3898000467D7E0FFFFF3FFBFFFFFFFFFF22",
INIT_12 => X"CC00001F079336108000447FFE7FFFF0B80BFFFFFFFFFCE20078DFF9A877EEFF",
INIT_13 => X"400214FFEFFFFF830C37FFFFFFFFFA803C03BCF8286004FF00801EE1FFFFFFFF",
INIT_14 => X"F08FFFFFFFFFFA02261BF432800007000000DCFFFFFFFFFFF000000607084897",
INIT_15 => X"002BE4E381800100001B3FFFFFFFFFFF807000000384E0A0A90294FFCFFFFC31",
INIT_16 => X"0057FFFFFFFFFFFDAFF8000008984FE6AE306CFF7FFFFD9E00DFFFFFFFFFD438",
INIT_17 => X"87F800000034C99F4E3101F8FFFBF3BF3F1FFFFFFFFC5FC07FB7F1C600E01D80",
INIT_18 => X"C1613BF1FFF61F7FFC9FFFFFFFF4FC306F9F47C000101C08865FFFFFFFFFFFFA",
INIT_19 => X"F93FFFFFFF9663C87FFF00C0001C7E0FC4FFFFFFFFFFFFF903B0000020F4BFB4",
INIT_1A => X"7FE6C060001CFC6B8FFFFFFFFFFFFFF51C00000005037C9180607BCFFFF6047F",
INIT_1B => X"FFFFFFFFFFFFC38ED40000000D7790DA0060592FFFE8141FF0FFFFFFFE4E4976",
INIT_1C => X"DEC100000D4363BA0462180FFFF803CFE1FFFFFFF93FAFFA7FE58000180C015F",
INIT_1D => X"C062E4FFFFE8064003FFFFFFCCFC3FFA7FF300003C1C027FFFFFFFFFFFFFA630",
INIT_1E => X"0FFFFFFF63F2FFF67FF60000381C43FFFFFFFFFFFFFFA24FFDE000E08957295A",
INIT_1F => X"7FE46086100000FFFFFFFF8FFFE94CBFFF8000FF00C1AA2200602DFFFFE031A6",
INIT_20 => X"FFFFFEA7E0FC42FFFFD7000303404A63A0E14BFFFFD9989FCFFFFFF6308BFF72",
INIT_21 => X"FF4E01031EA0D59080A047FFFFB0809F8FFFFF989FF3FE7C7FE8C083380C0DFF",
INIT_22 => X"80E37FFFE0A421601FFFFCE04C07FEFE7FC2400F8051FFFFFFFFFF93300CFDFF",
INIT_23 => X"FFFFE3033FFFFFFE7EC04080E4BFFFFFFFFFFE2BE01D03FFFF523B030AB9B4F0",
INIT_24 => X"7C82638005FFFFFFFFFFF3847862FFFFFE637C01DFB9EF3320827FFCCF8023BF",
INIT_25 => X"FFFFC8E303CCFFFFFCFF79004799DFA600037FFDC799427FFFFF3C3CFFFFFFFE",
INIT_26 => X"FBFC200040D03FB80006FFF83F515E7FFFF0E7C3FFFFFFFE7641031057FFFF3F",
INIT_27 => X"878DFFE2FCDFDF7FFF0FFCFFFFFFFFFE45B501675FFE6621FFFF6E20FF3CFFFF",
INIT_28 => X"FC3BFBFFFFFFFFFE28BE00D47FEFC665FFFEA3201CFDFFFFEFFE731801507F31",
INIT_29 => X"71AC8037FFCE2109FC7D806F13EBFFFF8FFFB21C2E6DFEDD8783FF9AC3BFFC7F",
INIT_2A => X"052D0000E797FFFCBFFBEC1C19AFF3A0064BFF3686FFFFFFFBFF6FFFFFFFFFFE",
INIT_2B => X"3FFBE31C2FCFECC80029FF4095FFFFFF07F61FFFFFFFFFFE45D00033FF918182",
INIT_2C => X"0021E0A597FFFFFCFFC0FFFFFFFFFFFE05A0813AFCA21C23867C27C3CE6FFFFB",
INIT_2D => X"9800FFFFFFFFFFFE18A0010A748E1F08C0800019679FFFF5FFF3ED102F87D734",
INIT_2E => X"6C920003FC3E0FA20100032FD5FFFFEAFFF7FA102687D7D8003973771FFFFFE3",
INIT_2F => X"0380032719FFFFD5FFE7F800A80FE9E000800937FFFFFF1F67F07FFFFFFFFFFE",
INIT_30 => X"FFE7EC00AF7FF2C000016FFFFFFFFCFFDFC7BFFFFFFFFFFE7C070107F1309E2C",
INIT_31 => X"001F53FFFFFFF3F83FB9DFFFFFFFFFFE6018031600F07C5006C3803215FFFFAB",
INIT_32 => X"FFA31FFFFFFFFFFE78D347A820F001E30C001FA685FFFF57FFEFE400DFFFFAC3",
INIT_33 => X"481E585164070361C0009F8095FFFC4FFFFFD5C1DBFFF4030098A7FFFFFFCFC3",
INIT_34 => X"01C1BFFD4BFFFE9FFFFFDA60879FF5038001AFFFFFA20007FFB37FFFFFFFFFFE",
INIT_35 => X"FFFFC8600367EAC100015FFFFE781FE0FF16EFFFFFFFFFFE27FFFB61100F3E07",
INIT_36 => X"1C01D83FC0D87FEE3E140FFFFFFFFFFE4FFFFB83000E8C0781027FFC0FFFF77F",
INIT_37 => X"DEE637FFFFFFFFFE6F0BC1110003E9838F91FFFFFFFFFF7FFFFFC8600497CCE0",
INIT_38 => X"36043D00012640800FA1FFFFFFFFDBFFFFFFBE20148790E01C0018270089FFC6",
INIT_39 => X"00D7FFFFFFFF90FFFFFFFF2050AF20011800701FC0BA7F992E8607FFFFFFFFFE",
INIT_3A => X"FFFF08009EEF60030004A1EFF1457FA0D19E0FFFFFFFFFFE11E38A1C0155C980",
INIT_3B => X"007C9F9FF3837F60263FE7FFFFFFFFFE485BFC1803A7B1809CAFFFFFFFFF81FF",
INIT_3C => X"1FE66FF03FFFFFFE6F340000038F26005C5FFFFFFFFD93FFFFFFCB90DE1F9003",
INIT_3D => X"726A8180037FC31EB87FFFFFFFF807FFFFFE0DB0503FD00380C0AFFFEF427F45",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFF00FFFFFFF688A7B9FD00380004FFFD8A1BFE780027FEB9FFFDFFE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFCD79A3D8FD001800037FFBB6C3FCA8103FF9F1FFFFFFE1C3303C00C2C9EE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"900079FFB7E47EE000C360781FFFF8FE702301000CAA9F20DFFFFFFFFFD47FFF",
INIT_01 => X"00C2FFE7BFFFF006083803E00EA67F877FFFFFFFFF90FFFFFFFEFE921C07F4E0",
INIT_02 => X"6C0600E00E38F839BFFFFFFFFF803FFFFFFBFE001C00C64C07809AFFB7FCFCE0",
INIT_03 => X"7FFFFFFFFD817FFFFFFDAFA05C0184140484A2F050FEC400000300DFFFFFF026",
INIT_04 => X"FFF33F03EBC7800A073C32878C010C880000193FFFFFF8F669C40009C444E1B4",
INIT_05 => X"0038B2041EFF00F00C2136FFFFFFF1A66D5800094003CCB3FFF87FFFF301FFFF",
INIT_06 => X"000058FFFFFFE1026DD3000A903E14FFFFFD3FFFF889FFFFFFFD5FC0947D6036",
INIT_07 => X"6D8B0002303ED7FFFFFCBFFFB083FFFFFFE13FCF3C3AF87F00003CFB6000000C",
INIT_08 => X"FFF43FFF0C17FFFFFFFA7FCD6C38F41B24088038003013DC600BA7FFFFFF0006",
INIT_09 => X"FFC0FFE6AC7400FB06020C000080CBF9001BEFFFFF0F000E66107962263C5FFF",
INIT_0A => X"0412C20001C29BFA60061FFFF80FFFFE71B0004E3C603FFFF836BFFE0837FFFF",
INIT_0B => X"D1071FFFF8FFFFFE7FA0000F19E1BFFFF4627FFC800FFFFFFFF7FF728C27E1BD",
INIT_0C => X"7F2807CC01C27FFF8C1AFFF8007FFFFFFFD1FF1EEF9FC27E9C35470003CAD5F9",
INIT_0D => X"6BE1FFF0801FFFFFFFAFFFC70E7240FA38C2D0030747C9FF5191BFFFFFFFFFFE",
INIT_0E => X"FF4BFFCB0874D7F8210058000007F7FFD3893FFFFFFFFFFE7F8723A40084FFFF",
INIT_0F => X"8261800003DF60FFE3835FFFFFFFFFFC7E465E7D5469FFFF57C1FFFF82FFFFFF",
INIT_10 => X"608F2FFFFFFFFFFC79412F05560FFFFCA38FFFCB85FFFFFFFF47FF5ACC5D81FD",
INIT_11 => X"763EF889BB0FFDFBC183FF41307FFFFFFFDFFF063C478BFE4312FC00476E50FF",
INIT_12 => X"009BEF4028FFFFFFFF47FFC41D2E43FFC377F640E23CBB7D40309BFFFFFFFFFE",
INIT_13 => X"FE8FFE4D4C4B5FFF02FFFB00615CBDB330209BFFFFFFFFFE6502237E3E823F75",
INIT_14 => X"017FFC00083C4CB1E03109FFFFFFFFFE741950DF3F2FF86A4327AF9013FFFFFF",
INIT_15 => X"4E0F0E7FFFFFFFFE742750DFFFB004E9C96FE00001FFFFFFFEBFFD9E0059A3FF",
INIT_16 => X"73CFAEBFFE50C1E1889F000023FFFFFFFE3FFF1EC85D23FFA1DFFD80008FB070",
INIT_17 => X"187FFE0407FFFFFFFC0FF91E7C47CFFFE4B7FD800107B4700607867FFFFFFFFE",
INIT_18 => X"FF7FF70FC8C7EFFFE657FDBC0087C3790018CC7FFFFFFFFE791FEEFFFDBCF031",
INIT_19 => X"E64BFDBD0306792B8E38B83FFFFFFFFE7CFEFFFFFF7CF0FCC97E3C041FFFFFFF",
INIT_1A => X"E030B39FFFFF7FFE7FF87FFFF807E0FC8BFC280C9FFF98FFFC3FFB03A807CDFF",
INIT_1B => X"7FF8FFFFFE0000203FF9583C3FFF7BFFFAFFFFC3E96742FFE22DFE0F6242BFF8",
INIT_1C => X"7FF030317FFEA0FFF83FF59200EE45FFA015FE0D01B03FFFC8003BB3FFFFFFFE",
INIT_1D => X"F4FFFA0C12FE41FFC009FE0C1CD08FFFE600FC4F1FFFFFFE7FFFFFFFFD7E760C",
INIT_1E => X"EC09FF70346ABFFFF3000360F7FFFFFE7FFFFFFFFA3E16009FE03803FFFAC6FF",
INIT_1F => X"FC0000C00C0FFFFE7FFFFFFFFFF9277DBFC21810FFF231FFF97FFBC8A2FAC3FF",
INIT_20 => X"7FFFFFFF7F7C83FE7F900097FFE4FFFFF1FFFACF5A7DC0FFFC09FD34202B07FF",
INIT_21 => X"3F800087FFF8E1FFEAFFFCEA599280FFC00DFE46600C5FFFC28130BFE7F3FFFE",
INIT_22 => X"C0FFF4E0114403FFF80FFE58E18707FFD303E09E063BFFFE7FFFFFFCDE60000A",
INIT_23 => X"F00FFA3F6183867FD80701DFFCF3FFFE7FFFFFFAA54700075FB0019FFFC041FF",
INIT_24 => X"ECFF409FFF8FFFFE7FFFFFF9B9464CFF1E6083BFFFB00BFFF9FFE6E6CD4B67FF",
INIT_25 => X"7FFFFFF928C4B87218C1C12FFFE84FFFEBFFCAC42A5787FFFC017BBF008100BF",
INIT_26 => X"5FE0E07FFFCC83FFA5FF913AA5FF81FFF405FD8FC0007A89FC360041FFFFFFFE",
INIT_27 => X"C7FF6482A31F82FFFCE799F71039FD29FD80990EFFFFFFFE7FFFFFFAD6C20064",
INIT_28 => X"FA60C393E6355E19FF0F643EFFFFFFFE7FFFFFFB318390182DE0609FFFDD9BFF",
INIT_29 => X"FFC594703FFFFFFE7FFFF8086042FC607AF0183FFE3DC7FF83FE4001C0E7E27F",
INIT_2A => X"7FFFE11F5706FAF0001C0DBFFFBCC7FF4FFD9801381BC17FFE23E135969C3845",
INIT_2B => X"0108047FFC6037FF0BFE0420382B803FFD316157D5001D4BFFFCE7F8FFFFFFFE",
INIT_2C => X"87F90671380396DFFFB0E197F601CE46FFFFF908FFFFFFFE7FFFE03EDCF04670",
INIT_2D => X"FE80228FFC022E967FFFF0C49FFFFFFE7FFFF1FCF032B800810101FFFF410FFE",
INIT_2E => X"5FFFF9771FFFFFFE7FFFFFFE1FDA7200CD03C8FFFE415FFC1FF5E0E033311F5F",
INIT_2F => X"7FFFFFFF83C77CF8134183FFFA011FFD17F7E0B003491F7FFF400779FE9ADFC7",
INIT_30 => X"AE8003FFFC12FFFC77FEE07300111E03FFC6638EFFDABFE39FFFFB7B7FFFFFFE",
INIT_31 => X"963F68E00427D03F3E2C1FE4FF9D3FE84FFFFF29FFFFFFFE7FFFFFFFF9E7DB69",
INIT_32 => X"40AC17FAFFFC9FE437FFFF071FFFFFFE7FFFFFFFFDB7B114BE000FFFA8D0BFFC",
INIT_33 => X"0BFFFFC0DFFFFFFE7FFFFFFFFCFB9BCA91001FFF62417FFA75BF9C860058D00D",
INIT_34 => X"7FFFFFFFFE7833E6010127FF8040FFFC3E3D5C616013101E09080FC1FFA04FFA",
INIT_35 => X"78002FFE4043FFF03FFEBC9B0193988E53C60FDFFF903FF191FFFFE03FFFFFFE",
INIT_36 => X"25F97DA2218398985AEECBEFFF0827FDD3FFFFFC1FFFFFFE7FFFFFFFFF3F17F9",
INIT_37 => X"1807C42FFF7A15FFB3FFFFFF30FFFFFE7FFFFFFFFF1F2FFEF81C7FFAB843FFFC",
INIT_38 => X"4800FFFFBF1FFFFE7FFFFFFFFE38BFFCE1FE9EE63843FFF145FC7A50A008981C",
INIT_39 => X"7FFFFFFFFC30FFFDA31D3DFC3908FFED2FFD73E2810FD8405C07021FFFE50BFF",
INIT_3A => X"A80A7D8C0783FFE90FFD30EF40060000FE220237FF3A617FB87CFFFFCFEFFFFE",
INIT_3B => X"9FF130E920061800FF1E8137FFFD22BFD8F6FFFFF7F0FBFE7FFFFFFFFF30FFFD",
INIT_3C => X"FFAC007BEFFEB17FF0CCFFFFFCCE62267FFFFFFFFF3EFFFF14CA7FEC0000FFF0",
INIT_3D => X"FC8BFFFFFF307E1A7FFFFFFFFE1DFFFE0CCBFE1480B0FFD1BFE426E630041800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFF83BFFFE984CFF0380F0FFD0FFE805EF180000007FFC0059C3FF515F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"804EFF99C024FFA2FFF007C2680000001FE000FDDBFFA98FFE97FFFFFFCC5BE2"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"FF0FFFEE7E0FB7E7FFE04BFFFC3FFFFE0FFFFFFFF3FFFBDC0000000000000000",
INIT_02 => X"FFC41FFFFCFFFFFE0FFFFFFFFFFFFF9C7FFFFFE0FFFFCFFFFFFFE77FECFFFFFF",
INIT_03 => X"CFF3FFFFFFFFFF9C7FFFFFE03FFFDC3FFFFF7CCFFB79FFF9FF1FFFF1BE07BBE3",
INIT_04 => X"7FFFFFE7CFFFDC3FF8207FC19BBAFF9ECFFFFFFFDC27A5F03FCC3FFFFCFFFFFF",
INIT_05 => X"F83F3F9FFBD8CFFFCFFCFFFFCC27ADF81F89FFFFFCFFFFFFEE93FFFFFFFE279C",
INIT_06 => X"FFFCFF0EEC67AEF80C03FFFFFEFFFFFFF7FFFFFFFFFE001C7FFF0743F8FFCD3F",
INIT_07 => X"010FEDFDF6FFFFFFF7FBFFFFFEFF001C7FFF00039E3FF78EF8FF0F9FFFDC930F",
INIT_08 => X"F7F3FFFF1FFC063E7F180003FF87FBFFFCFEFF9FFCEFBFF6FFFEFFFE2CE3B770",
INIT_09 => X"7F0000063BF3FDF73FFF39FFFFB7DFFAFFFF3FF1ECF3B786073E6FFFF2FFFFFF",
INIT_0A => X"8FFF71FFF1D9DFFDB6B68FFFECF07FFF867F7FFFF33C7FFFF6E3FFFF27F03FFE",
INIT_0B => X"F07C7FFFFCFCFBBFE1E3FFFFF38C7FFFF6E3FFFF3F67FFFE7FC002066FF3FEED",
INIT_0C => X"03CFFFFFFBDD7FFFF7E3FFFFBE2FFFFE7FC007C677E3FF399FFF71FF360C9FFE",
INIT_0D => X"FFF3FFFFBC6FFFFE7FE00FEF7BC7FF39FFFFFB00F0001FFF70FDFF1FF0FCFBA8",
INIT_0E => X"7FF00FFFB81FFF3CFFFFFFFCFE0C3FFF61BDF33FF87CCFB8079FFFFFFF937FFF",
INIT_0F => X"FFFFFFFFEEEFDFFF3F1FF1383B7FCFB10F1FFFFFF7837FFFFBF3FFFFFCDFFFFE",
INIT_10 => X"37DF3EFC98FF87FBFF1FFFFFFFC0FFFFFBF3FFFFFDDFFFFE7FF80FFFC17FFFDD",
INIT_11 => X"FFFFFF3F7EC1FDFFFBF3FFFFFFE7FFFE7FF80FFFF0FFFFD1FF7FFFFFD8F1EFF8",
INIT_12 => X"F7FBFFFFFFFBFFFE7FFE0FFFFC0FFFDFFF7FE0FFDFF8E001FAF9FEFF9FF7F7FF",
INIT_13 => X"7FFF07FFBE1FFFE3BFFFF1FF5FFCF003FB5AFFFFFFDC7FC7FFFFFF3EFF86F8FF",
INIT_14 => X"9FFFFFFCDFFF01FFFD93BFFECF63D7E3FEFFFDFE3F9DFAFFF7FF3FFFFEFDFFFE",
INIT_15 => X"FCC3DEFDC6E3DF81FFF87FFE3F80FBFFF7F83FF7FFFCFFFE7FFF07FBF37FFFFD",
INIT_16 => X"FFE73FFEFB80F9FFF60FFFFBFC01FFFE7FFF07E7F3781FFEDFFFFFFEDFFFFFFF",
INIT_17 => X"F4EFFFFF9BFFFFFE7FFC03FFF337E7FF7FFFFFFFDFFFFFFFFE888F8FE5EBFFBC",
INIT_18 => X"7FC000FFFF8EFBFFBC7FFFFFDFFFFFFFFE1F0387E5EDFD703F1F3C3FF9C0F5FF",
INIT_19 => X"DC3FFFFFDFC3FFFFFF9FF9CFFEEEFF771F8E019FFF8EF5FFF0EFFF9F37FFFFFE",
INIT_1A => X"FFDFFECFFEFEFF771FE03F80FFBFF3FFF0CBFF9FCFFFFFFE7F8FF23FFFFD3BFF",
INIT_1B => X"1FF3FF86C1BFE7FFF1D3FF9F3FFFFFFE7F8FF78FFFFF7DFFEFFFFFFFBF81FFFF",
INIT_1C => X"F1D3FE3FFFFFFFFE7FE3FBC7FFFFC67FF3FFFFFFBF80FFFFFF8FFF3F3F76FFEF",
INIT_1D => X"7FF9FC87FF9F9F3FFDFFFFFFBFC03FFFFE67FFDF7FFAFECE3FFBFFEEC1BCD7FF",
INIT_1E => X"FECFFFF85F7C90FFFCFBFFE73DB8FEDC3BFBFFFDFF3877FFF1D3FE7EFFFFF9FE",
INIT_1F => X"3CFDFFF9FF5CFDD99FF3FFFDFF39F7FFF1D3E07EFFFFF9FE7FFE7F83FFFFF33F",
INIT_20 => X"9E71FFFBFF7CF7FFF3DFFEFCFFFFF5FE7FFF7FC03FFFFF3FFF7FFFF0DFDED83F",
INIT_21 => X"F3CFFFF9FFFFFDFE7FFFBBE007F0FFC73F7FFFE1EFC6D800DE86FFFEEB6E6DB3",
INIT_22 => X"7FFFDFE007F0FF7FBEC3FFFFF7C34C07EEC77FFF3FEE5DB71E30FFFBFF7CF7FF",
INIT_23 => X"9D833FFFFBE80F9FF4E53FFFBF73DFC63FF3FFFBFF71FFFFEF80FFF3FFFFEFFE",
INIT_24 => X"F9F49FFFDF7C3D000EE7FFFBFF83EFFFCF007FEFFFFFDFFE7FFFCFC007F9FCBF",
INIT_25 => X"F7CFFFC007C3EFFFCC4C7FDFFFFFDFFE7FFFE7C4CFFFFFC781801F3FEDF02F9F",
INIT_26 => X"8C1C601FFFE7BDFE7FFFFBDFE9FFFFFFC3FF003F0DF82FBFFFFDE7FFCF7FFC3F",
INIT_27 => X"7FFFFC1FEC3FF9E7E47FFC1F02FE2FDFF3FDFCFFF79FFDBFFBBFFCFEF0C36FFF",
INIT_28 => X"C89E1F8722FF07EFFFFDFFBFFB83F83FF9BFF9FEFF03FFFF1CFC003FFFE87EFE",
INIT_29 => X"C7FE7FEFFDC3F07FFD7FF9FF7F7ADFFE3FFE007FFF9FE73E7FFFFFFFF60FFE77",
INIT_2A => X"FC7FF8FF807BDFFE1FFF007FFFBFDDDE7FFFFFFFFB33E7FEDFCE0FC3BF3F8EE7",
INIT_2B => X"0FFFF0FFFF7FBEEE7FFFFFFFFCFFC1CCFFE7C3E0BFE7CCE787FE71F7FEFFF8FF",
INIT_2C => X"7FFE7FFFFFE47BFFBFE3C1F83E798C4699FF7F7BFF7FFCFFF87FFCFF0CFBFFFF",
INIT_2D => X"3FFCF1FC7C7900327DFFF7C3FFBF01FFF07FFCFEE4FBBFFF87FFF8FFFF6FBF76",
INIT_2E => X"FC77F3F19FDF4FFFF07DFDFEF775BFFF87FFF8FFFEEF7FB87FE7C0FFFFFB3FFF",
INIT_2F => X"FC79FE00F76FFFFF0FFFF8FFFE8F7FCE7FF3FF3FFFFFB3FEFFFE19FEFFE078F3",
INIT_30 => X"1FFFFDFFFF8FFFEE107EFBCFFFFF9FFCFFFFE7FF4F9F7E7FF837FDFFCFC7FFFF",
INIT_31 => X"013FBCF81FFFDFF1FFFFF3FF3C7FAE3E7CFFF6FFFFC77FFFFC73FEFC70EFFFFE",
INIT_32 => X"FFFFFD9F8DFFD61F3EBC9BBFFFF37FFFFC03FFFE31FF7FFE3FFFFDFFFDDEFFEE",
INIT_33 => X"1FBCFBDFFFFC7FFFFFC3FFFF01DF7FFE3FFFFDFFFBCDFFEE001FCE8FF7FFE01F",
INIT_34 => X"F1FFF9FFE7BFFFFE3FFFF9FFF7FDFFF6001FF38399FFFEFFFFFFFCE7CDFFEF6F",
INIT_35 => X"3FFFDBFFEFFBFFF60007FDFB1E1FFFFFFFFFFFE3FEFFF7720FB4F3F3FFFE7FFF",
INIT_36 => X"03B3FEFF3FE7FF3FFFFFFF7FFEFFF9BDC7B6F7FDFFFF7FFFE1FFCEFFFFAFFFFF",
INIT_37 => X"FFFFFFBFFF7FFCBFE7B7F6FCFFFFBFFFE1FFC6FFF76EFFFF3FFF8FFFEFFBFFF6",
INIT_38 => X"FBBFFE3E7FFF9FFFE1FFC7FFE05EFFFFFF0F8FFFEED7FFEE01FCFF6E8179FC9F",
INIT_39 => X"F1FFCFFFE0CEFFFFFF0F8FFFDFF7FFEE71FEFFB8DE7E79EFFFFFFFDEFFBFFEDF",
INIT_3A => X"DE0F8FFFD3F7FFCE7FEF7FCFF87F8733FFFFFFEE4DDFFFEFFDEFBE3FBFFF8FCF",
INIT_3B => X"7FEF9FF73B0FFFF87FFFFFFB7FDFFFEFFDE7FE1EDFFF66BFF1FFDFFFE0EEFFFF",
INIT_3C => X"3FFFFFFDFF6FFF77FDDFEF0FCF7F667FF1FF9FFFC4CEFFFFCE0FC7FFDBDFFF9E",
INIT_3D => X"FCCFEF0FC67F87FFF87F1FFFC1DFFFFFCC1FCFFFFB9FFFBE3FFFEFFBDC17FFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FC3F1FFFE1DDFFFF9C1FFFFFBBBFFF3E60FF77FCEDFFC3FFCFFFFFFEFFB7FFFB",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"1C1FFFFFBBFFFF7E7F03FBFEFBFE83FFE7FFBFFF6FFBFFBBFF7F6F8FC07FC7FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7FFCFDFFFE1BC3FFFBFFFFFFBFFDFFBFFF076F8FF87FFFFFFC7F1FFFF3DDFFFF",
INIT_01 => X"FCFFFFFFCFFEFFDFFFFB6FFFF87FFFFFFEF7BFFFF8DDFFFF3CEFFFFF7F7FFCFE",
INIT_02 => X"FFF87FFDFC7FFFFFFFFFFFFFFEFBFFFF3CE7FFFF7EFFF9BE7FFF9DFF3FFCF3FF",
INIT_03 => X"FFFFFFFFFEFBFFFFF8E7FFFF7EFFFBBC7FFFF1FF8FFF73FFFFBFFFFFF7FF7FE3",
INIT_04 => X"F0E7FFFFFDFFFBB87FFFFFFFB33F73803FEFFFFFFBFF3FFFFFF9FFFC387FFFFF",
INIT_05 => X"7FFFFFFFB80763009FF7FFFFFDFFBFFFFFFDFFFCC03FFFFFFFFFFFFFFFFBFFFF",
INIT_06 => X"1F99FFFFFFFFCFFFFFFDF3FCFFFFFFFFFFFFFFFFFDFFFFFFE067FFFEFDFFFB3A",
INIT_07 => X"FFFCFBBEFFFFFFFFFFFFFFFFFBF7FFFFE047FFFEFFFFFB3A7F00C8FF9C83BBD8",
INIT_08 => X"FFFFFFFFF3EFFFFFC70FFFFDBBFFF7F27DFFFF000F1F3CFFBFFEFFFFFF3FE7FF",
INIT_09 => X"C71FFFFDBBFFE7E673F6FFFF8E3F7B81FFF79FFFFF9FFBFFFFFCFE1EFFFFFFFF",
INIT_0A => X"1F2EFEBFFE3EFBFF3E7FEFFFFFCFFDFFFFFC0DEE438FFFFFFFFFFFFFC7EFFFFF",
INIT_0B => X"E7FFBBFFFFF3FEFFFFF801EF00001FFFFFFFFFFF87DFFFFFC63FFFFDF7FFC79E",
INIT_0C => X"FFFEF1EF87FFE7FFFFFFFFFE03DFFFFF9CFFFFFBF7FFCF3E7C0FFFCF1E3DDBFF",
INIT_0D => X"FFFFFFFC13BFFFFF9DFFFFFBEFFFDF7E58FFFF661F039BFFF9FFFDFFFFFDFF7F",
INIT_0E => X"99FFFFFFDFFFCE7E4FFF997FFFFF97FFFEDF7F7FFFFE6FBFFFFFFFEF871F73FF",
INIT_0F => X"7FFF9BFFFFFFF7FFFF7BDFBFFFFF07DFFFFFFFEF0F07FBFFFFFFFFFC77BFFFFF",
INIT_10 => X"FF9FE3CFFFFFCFE1FFFFFFE60F3BFBFFFFFFFFFFF77FFFFF81FFFFF7FFFFC8FE",
INIT_11 => X"FFFFFFF66F399FFFFFFFFFFFF77FFFFF807FFFFFFFFFC1FE7FE307FFEF8FDFFF",
INIT_12 => X"FFFFFFFFE6FFFFFF0FFFFFEFBFFF0FFE7FFF07FFEEFFBFFFFFF0F9F7FFFFE3F8",
INIT_13 => X"7FFFFFEFBFFF1FFE7EFFFFEFFEFF7FFFFFFF3FFBFFFFF9FCFFFFFFF20F3CDDFF",
INIT_14 => X"7EFFFFC3FFFF77FFFFFFE7FCFFFFFCFE3FFFFFF71DBF7DFFFFFFFFFFEEFFFFFF",
INIT_15 => X"FFFFFBFF3FFFFE3F001FFFF739DF9CFFFFFFFFFFDDFFFFFFFFFFFFDFBFFE3FFE",
INIT_16 => X"000FFFC7FFDFE0FFFFFFFFFFDDFFFFFFFFFFFFDFBFFC3FFE3FFFFFC1FFFE67FF",
INIT_17 => X"FFFFFFFF93FFFFFFFFFFFFBFBFFC7FFE3FFFFFE01FFE07FFFFFFFF9FCFFFFF1F",
INIT_18 => X"FFFFFFAFBFFC7FFE38F8FFFF1FFF87FFFFFFFFE7F7FFFFCF8C1FFFCE7FCFFFFF",
INIT_19 => X"38F8FFFFFFFFF7FFFFFFFFFC7DFFFFE7CFBFFFEEFF4FFFFFFFFFFFFF83FFFFFF",
INIT_1A => X"FFFFFFFFDF7FFFF1EFFFFFCFFFEFFFFFFFFFFFFF87FFFFFFFFFFFFAFBFF83FFE",
INIT_1B => X"C7FFFFCFFFEFFFFFFFFFFFFF87FFFFFFFFFFFF6FBFF07FFC3BF9FBFFFF7FF7FF",
INIT_1C => X"FFFE3FFF2FFFFFFFFFFFFEFFFFE1FFFA1BFEDFFFFFFFF79FFFFFFFFFE7CFFFF8",
INIT_1D => X"FFFFFEFBFFE7FFFA1FCFFFFFFFFFF3DFFFFFFFFFF8F3FFFE27FFFFC7FBEFFFFF",
INIT_1E => X"0FC0FFFEFFE4E0003FFFFFFFFF7DFFFF21FFFF87F1B7FFFFFFF83FFF6FFFFFFF",
INIT_1F => X"9FFFFFFFFFCF3FFF80FFFF9FF1F7FFFFFFF3BFFF5FFFFFFFFFFFFDF37FFFFFF6",
INIT_20 => X"CC7FFFDFF8F7FFFFFFC7DFFF1FFFFFFFFFFFFDE37FFFFFEE1FF01FCEFFE6E7C7",
INIT_21 => X"FFCFDFFE1FFFFFFFFFFFFFD8FFFFFFDE7FFFFFDFFFEFFFFFCFFFFFFFFFF7CFFF",
INIT_22 => X"FFFFFBD8FFFFFFFE7BFFFFFFBFFFFFF773FFFFFFFFFCF3FFE3BFFFDFFCFBFFFF",
INIT_23 => X"7B9FFEBFFFFFF1FE381FFFBFFFFF3CFFF39FFFDFD8FBFFFFFFDFDFFE1FFFFFFF",
INIT_24 => X"FFE1FEEFFFFFCF1FF9CFFC0FD847FFFFFFDFDFFE3FFFFFFFFFFFFFB0FFFFFEFA",
INIT_25 => X"FCCFFC80F807FFFFFFFE1FFE3FFFFFFFFFFFF5B1FFFFF98C7FFFFF3F1FFEF87E",
INIT_26 => X"FFBDDFFC3FFFFFFFFFFFEF71FFFFEE7A7FFFFF1FCFC1FE3C1FFF1DF7FFFFF7C7",
INIT_27 => X"FFFFEF73FFFF98C67FFFFFFFEDFFFFFFDEBFF71BFFFFF9F9FE67FF877C0FFFFF",
INIT_28 => X"7FEFE7FFEFFFDFFFFFFFFF7BFFFFFE3E7F37FFDF7E7FFFFFFFBDFFFC3FFFFFFF",
INIT_29 => X"FF7FFF7BFFFFFF1F9F83FFFF7EFFFFFFFF65FFF83FFFFFFFFFFFDEF3FFFF63BE",
INIT_2A => X"E7C1FFFF76FFFFFFFF65FFF83FFFFFFFFFFFBEF3FFFEFE7E7FE1E7FFFFC667FF",
INIT_2B => X"FF65FFF87FFFFFFFFFFF3DE7FFFDF3FE7F00FFFFFF0F63C70C7FFF58FFFFFFCF",
INIT_2C => X"FFFF7DE7FFF9CFFE7FFFDFFF1E0FFCFF1EFC3FFF6FFFFFE3FBE0FFFEF2FFFFFF",
INIT_2D => X"7FFF7FFF0ECF7C0F3FFC3FFF13FFFFF8FDE07FFDBFFFFFFFFF66FFF87FFFFFFF",
INIT_2E => X"FFFFF97FFDFFFFFF1F703FFBBB67FFFFFEF37FF07FFFFFFFFFFEF7EFFFFFFFFE",
INIT_2F => X"C7901FFA3F19FFFFFEE33FE07FFFFFFFFFFDE7EFFFFFFFFE7FFFFFDF0EE61C03",
INIT_30 => X"0E63BFC07FFFFFFFFFFBEFFFFFFFFFFE7FFFFFFF9F1E7C07FFFEFFFFFEFFFFFF",
INIT_31 => X"FFF3DFFFFFFFFFFE413FFFFFFFFFC63FFFFC7FFE877FFFFFFBC00FF63FFE7FFC",
INIT_32 => X"7F3FFFFFFFFF87FFFFFC203E1BBFFFFFFCE003F7FFFF7FFCCF73DF807FFFFFFF",
INIT_33 => X"FFF0001FFFE7FFFFFF0009F7FF7EFFFDE77FEFB07FFFFFFFFFE09FFFFFFFFFFE",
INIT_34 => X"FFC0CCF79FE3FFFDF03E6F3CFFFFFFFFFFC03FFFFFFFFFFE7F3FFFFCFFF807FF",
INIT_35 => X"FC1E6F34FFFFFFFFFF80FFFFFFFFFFFE7FFFFFFEFC387DFFBFFE781DFF79FFFF",
INIT_36 => X"FF01FFFFFFFFFFFE3FFFFFFE3C1C3F7FF91FFFF87FEE3FFFFFF09EF01FCFFFFD",
INIT_37 => X"07FFFF7E7E3D87FFFFEFFFF97F9FDFFFFFF83F399FC1FFFEFFE7EF20FFFFFFFF",
INIT_38 => X"9FF7F9FFFE7FEFFFFFFDFFC07FFF383F7FE0CE21FFFC7FFFFE07FFFFFFFFFFFE",
INIT_39 => X"FFFD9FFFFFFF9C0F0FF01E01FFF8FFFFFC1FFFFFFFFFFFFE07F0FFFFEFFBFDF7",
INIT_3A => X"0FF9FC81FFF0FFFFF83FFFFFFFFFFFFE7FFFFFFFCFFBFCFF01FFFDFFFCFFF3FF",
INIT_3B => X"F0FFFFFFFFFFFFFE7FFFFF00DF07E401FF00E5FFF03FF9FFFFE79FFF3EB86000",
INIT_3C => X"4EFFFFEFDF07FF1FFFFEF7E7877FFDFFFFEFFFFF3977700F0FFDFC03FFE1FFFF",
INIT_3D => X"FFFF7E17FFFFFE71FFEFFFFF006F3EFF0FFE7803FF83FFFFC1FFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FEEFEFF3E67BFFF27FF0307FF03FFFF83FFFFFFFFFFFFFE4EFFFFFFDF0FFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"73FFE783FE03FFFE0FFFFFFFFFFFFFFE0EFFFFFF0F4FFFFFFFFF7DF800EFFFDF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"1FFFFFFFFFFFFFFE7FFCFFFF0F7FFFFFFFFF39FFFF3FFFFFDFEEF97FFFE7BFFF",
INIT_01 => X"7FF87FFF43FFFFFFFFFFC7FFFFEFFFFEE7EFF03FFEEF9FFF7BFFFF00FC07FFFC",
INIT_02 => X"FFFFFFFFFFF8FFF1FC1FE03BFDDF9FFF7BFFFE03BE07FFF07FFFFFFFFFFFFFFE",
INIT_03 => X"FFFFFFFFFDCF83FEFB97FE07DE0FFFE1FFFFFFFFFFFFFFFC7FF87FFFF9BFFFFF",
INIT_04 => X"FB9BFE33E00FFFC3FFFFFFFFFFFFFFFC7FF9FFFFFCBFFFFFFFFFFFFFFFFF81DF",
INIT_05 => X"FFFFFFFFFFFFFFFC7FFFFEFFFC7FFFFFFFFFFFFFFFFFFEFCFF0FFFFFFCEF0BDD",
INIT_06 => X"7FFFFFBF0CFFFFFFFFFFFFFFFFFFFF7FFFFEFFFFFFECDDCFFCFFFC3CFE3FFF0F",
INIT_07 => X"FFFFFFFFFFFFFFBFFCFFFFFFFFE9DDD6FCFF7C7F3E7FFE3FFFFFFFFFFFFFFFF8",
INIT_08 => X"FE5FFFFFFFE1BFB73CFEFC7FBE7FF9FFFFFFFFFFFFFFFFF06F7FFFFF07FFFFFF",
INIT_09 => X"B9FEF83F9C1FF3FFFFFFFFFFFFFFFFC07F7FFFF313DFFFFFFFFFFFFFFFFFFFDF",
INIT_0A => X"FFFFFFFFFFFFFF027F3FFFEFC3DFFFFFFFFFFFFFFFFFFFE7DFFFFFFFE7F1DBB7",
INIT_0B => X"7F0FFFCFE1E0FFFC000FFFFFFFFFFFF8FFFFFFF3E7FFE3A7B1FEF8FF8067CFFF",
INIT_0C => X"FFF83FFFFFFFFFFFDFFF3FFF8FFFFFFFB39DFBFF1E733FFFFFFFFFFFFFFFFC06",
INIT_0D => X"E7FF7FFFBF8FFFF93397DBFF3F30FFFFFFFFFFFFFFFFE01C790FEFF9C3BF3083",
INIT_0E => X"0397F9FE7F87FFFFFFFFFFFFFFFFE3FA7D0FD8F0199FFFFFFEFFC01FFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFE67FE3F71FFD88FFFE07FFFFFF007FFFFFF3FFFFEFFFBE67FF",
INIT_10 => X"7FE38FFFFB809FF007FF9F7FF81FFFFFFA3FFFFFFEFE3FFD47BFF9FC7F8FFFFF",
INIT_11 => X"03F9FFF007FFFFFFE33FFFFFF8303C79FFFFB1FEFFFFFFFFC007FFFFFFFFFFCC",
INIT_12 => X"EFFFFFE0F870D9F0FFFFB3FFFFFFFFFF3807FFFFFFFFFF7C7F87BFF193881100",
INIT_13 => X"7FFDF3FFFFFFFFFC0C0FFFFFFFFFFCFE43FF7FEFEF9FFB00FF7FFE1FFFFFFFFF",
INIT_14 => X"007FFFFFFFFFF3FE59F8F8DD7FFFF8FFFFFFC3FFFFFFFFFFDFFFFFF9F8F8EF88",
INIT_15 => X"7FE7F7FC7E7FFEFFFFF8FFFFFFFFFFFFDF8FFFFFFC7C77FF36FD73FFFFFFFFCE",
INIT_16 => X"FFCFFFFFFFFFFFFE3007FFFFF778377931FFA3FFFFFFFE7FFFFFFFFFFFFFE7F8",
INIT_17 => X"F807FFFFFFF0306071FEDFFFFFFFFC7FFFFFFFFFFFFF9FC07F8FDE39FF1FE27F",
INIT_18 => X"FEFEDFFFFFF9E0FFFF7FFFFFFFF8FC00107F983FFFEFE3F77E3FFFFFFFFFFFFC",
INIT_19 => X"FEFFFFFFFFE7E0307FFFBF3FFFE381FFC3FFFFFFFFFFFFFDFC4FFFFFDFF04040",
INIT_1A => X"7FFF7F9FFFE303E47FFFFFFFFFFFFFF9FFFFFFFFFB030061FFFFDFFFFFE603FF",
INIT_1B => X"FFFFFFFFFFFFFC70C9FFFFFFF3078023FFFFFFDFFFEFF3FFFFFFFFFFFF8FC7F8",
INIT_1C => X"3CFEFFFFF33B0383FBFDBFFFFFEFF03FFFFFFFFFFE3F9FFC7FFEFFFFE7F3FF3F",
INIT_1D => X"3FFDBBFFFFFFFE3FFFFFFFFFF0FCFFFC7FFDFFFFC3E3FEFFFFFFFFFFFFFFC60F",
INIT_1E => X"FFFFFFFF83F1FFF87FFBFFFFC7E3BEFFFFFFFFFFFFFF3E3FFE3FFF1F7738C1C3",
INIT_1F => X"7FF79F79EFFFFDFFFFFFFFFFFFFE7C7FFFDFFF00FFBFC4E3FFFF73FFFFF7CF99",
INIT_20 => X"FFFFFF2FFF0041FFFF9FFFFCF33F84E3DFFFF7FFFFEE67803FFFFFF83087FFFC",
INIT_21 => X"FF80FEFCF39F0E80FFBEFFFFFFDF7F807FFFFFE0800FFFFE7FCF3F7CC7FC03FF",
INIT_22 => X"FFFEFFFFFF3BDF1FFFFFFF003FFFFFFE7F9DBFF07FCFFFFFFFFFFEF7C00C03FF",
INIT_23 => X"FFFFFC00FFFFFFFE7F7FBF7F1C7FFFFFFFFFFCD8001CFFFFFF8CC4FCE3860F00",
INIT_24 => X"7EFF9C7FF3FFFFFFFFFFFDFC0061FFFFFF9D83FE3F861FC3DFFEFFFF0FFFDF7F",
INIT_25 => X"FFFFF0FF03C3FFFFFFFD86FFBF863FC7FFFEFFF9F8787EFFFFFFC003FFFFFFFE",
INIT_26 => X"FFFEDFFFBFCFFFCFFFFDFFF3C0CF9EFFFFFF003FFFFFFFFE7BB9FCEFCFFFFFFF",
INIT_27 => X"787BFFF503BFE0FFFFF003FFFFFFFFFE7671FE9F3FFF801FFFFF8E3FFF03FFFF",
INIT_28 => X"FFC007FFFFFFFFFE4F83FF33FFF0FFE3FFFF3F3FFC03FFFFFFFF73E7FECFFFC6",
INIT_29 => X"3F777FEFFFEFDEFBFFFEFFF0F007FFFFFFFFCCE3EFDFFF067877FFED3F7FFFFF",
INIT_2A => X"F911FFFFE00FFFFF7FFFFEE3C19FFC1BF9A7FFB97DFFFFFFFC009FFFFFFFFFFE",
INIT_2B => X"FFFFFDE3E03FF033FFE7FF7FF3FFFFFFF809FFFFFFFFFFFE7CE7FFEFFFDE7E79",
INIT_2C => X"FFE01FDC0FFFFFFF003FFFFFFFFFFFFE73CF7EF9FF3DE3D807FFD83FC01FFFFC",
INIT_2D => X"07FFFFFFFFFFFFFE773FFEF6F8F1E0F8FF7FFFF8607FFFF8FFFFF1EFE07FE707",
INIT_2E => X"60EFFFFF0FC1F063FEFFFCE0F3FFFFF1FFFFF3EFE17FE7DFFFFFF073FFFFFFFC",
INIT_2F => X"FC7FFCE0F7FFFFE3FFFFF3FF67FFF1FFFF7FFBCFFFFFFFE01FFFFFFFFFFFFFFE",
INIT_30 => X"FFFFF7FF67FFFCFFFFFE9BFFFFFFFF003FF87FFFFFFFFFFE7FFFFF07FECF6197",
INIT_31 => X"FFE0B7FFFFFFFC07FFC1BFFFFFFFFFFE7FF8FEE7FF0F8327F93C7FF0F3FFFFC7",
INIT_32 => X"FFC3BFFFFFFFFFFE78CC7DCFDF0FFF0CF3FFFF80F3FFFF8FFFFFF7FF37FFFCFC",
INIT_33 => X"47FF9B9E9BF8FF7E3FFF807EF3FFFF5FFFFFE63E37FFF8FCFF676FFFFFFFF03F",
INIT_34 => X"FE3F7FFE47FFFCBFFFFFED9F77FFF9FC7FFF9FFFFFDFFFFFFFC3DFFFFFFFFFFE",
INIT_35 => X"FFFFEF9FF79FF33EFFFF3FFFFF87FFFFFFE7DFFFFFFFFFFE1FFFE47EEFF0FFF8",
INIT_36 => X"E3FFC7FFFF07FFF1FFE7DFFFFFFFFFFE3FFFFDFCFFF18FF87EFEFFFFFFFFFB3F",
INIT_37 => X"3F07EFFFFFFFFFFE1FF7FDEEFFFF0E7C7070FFFFFFFFF7FFFFFFEF9FF30FEF1F",
INIT_38 => X"0F03C1FFFEDDEF7FF06FFFFFFFFFEEFFFFFFDFDFF31FDF1FE3FFF81FFF07FFE6",
INIT_39 => X"FFCFFFFFFFFFDDFFFFFFBFDFCF1FBFFEE7FFF00FFF39FFDF1F07EFFFFFFFFFFE",
INIT_3A => X"FFFFB8FFBF1FBFFCFFFB9E1FFE7CFFFFCE1FE7FFFFFFFFFE0EE003E3FEB3EE7F",
INIT_3B => X"FF83BFFFFCFEFFBFE03FEFFFFFFFFFFE4643FFE7FC6FDE7F7F9FFFFFFFFF3BFF",
INIT_3C => X"FFFE1FFFFFFFFFFE6007FFFFFC5FB9FFC03FFFFFFFFEF7FFFFFF78EFBFFFDFFC",
INIT_3D => X"700D7E7FFCDF7CE19FFFFFFFFFFDEFFFFFFF7ACFBFFFFFFC7F3F9FFFF07EFF9A",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"BFFFFFFFFFFBDFFFFFFE66F5BC7FFFFC7FFFC7FFE73F7FC87FFEFFF07FFFFFFE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFECEE5BE7FFFFE7FFFF3FFC78F7FED7EFEFFE0FFFFFFFE1C3CFC3FF39FE11B"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_3B => X"BFFACDF03FFFE7FFBFA17F0FFFFE3E7FE701FFFFF80F07FE7FFFFFFFFFC1FFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3A => X"900EFEFFF87EFFFEDFFACDF07FFFFFFFBF5DFE0FFFFC7CFFC783FFFFF01FFFFE",
INIT_3E => X"7FFFFFFFFFC7FFFF180DFFF47F0DFFDEFFFFF3F71FFFFFFFBFD3FF27FFFF9F3F",
SIM_COLLISION_CHECK => "NONE",
INIT_3C => X"BFF3FF07FFFF3F3FFF03FFFFFF0061DE7FFFFFFFFFC1FFFE040EFEEFFFFDFFEF",
INIT_3D => X"FF07FFFFFFC07E067FFFFFFFFFE3FFFF0C0EFF077F4DFFFF7FF7DDF63FFFE7FF",
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6FFFFBFFCFF83F0FFF3EFF87FFFFFFFE003CFEFFF39CE0DFBFFFFFFFFFE7DFFF",
INIT_01 => X"FF3E001FFFFFFFFE703FFC1FF19B807F3FFFFFFFFFDFBFFFFFFCDFEDBFFFDB1F",
INIT_02 => X"7007FF1FF18307F87FFFFFFFFF3F7FFFFFFDDF7FBFFF99BFFFFF99FFCFFF3EFF",
INIT_03 => X"FFFFFFFFFEFFFFFFFFF99FDFFFFE3BF7FCFB41FF8FFF39FFFFFF003FFFFFFFDE",
INIT_04 => X"FFFB1F7C5C38FFE3FFC361F800FE0F77FFFFF8FFFFFFFF0E71C7FFF7FBC71F83",
INIT_05 => X"FFC781F81FFFFF0FF3DEF1FFFFFFFE5E71DFFFF77FFC3C7FFFFFFFFFFBFCFFFF",
INIT_06 => X"FFFFC7FFFFFFFEFE71DCFFF6EFC1F3FFFFF8FFFFEF7BFFFFFFF73F7F48019FEB",
INIT_07 => X"718CFFFECFC1CFFFFFF87FFFDF77FFFFFFF77F7FE00307DBFFFFFC03FFFFFFFF",
INIT_08 => X"FFF87FFFB3FFFFFFFFEEFF7DE0030BBDDBF8FFFFFFCFF0019FFB9FFFFFFFFFFE",
INIT_09 => X"FFEDFF60E007FFBDF9F773FFFF7FC7FDFFF41FFFFFFFFFFE781F8698D9C33FFF",
INIT_0A => X"FBF77DFFFE3E67FC7FEFFFFFFFFFFFFE7E3FFFB8C39F7FFFFFC67FFF77EFFFFF",
INIT_0B => X"1EEFFFFFFFFFFFFE7F3FFFF9E61F7FFFF87EFFFEFFDFFFFFFFDDFFECE007FF79",
INIT_0C => X"7FB7FFF9FE3EFFFFF7E6FFFDFFDFFFFFFFDBFF80E01FFEF8E3F278FFFC39E3FE",
INIT_0D => X"8C1CFFFB7FBFFFFFFFFBFF8001BE7DFCC7C0DFFCF8B3EBFF9E77FFFFFFFFFFFE",
INIT_0E => X"FFBFFF8807BC6DFEDF002FFFFFEFDDFF9C78FFFFFFFFFFFE7F38E021FF7DFFFF",
INIT_0F => X"FE8077FFFFCFBDFFBC7F3FFFFFFFFFFE7F79C181C79BFFFF983BFFF47DBFFFFF",
INIT_10 => X"BF7F1FFFFFFFFFFE7E7F10F93BFBFFFF3C7BFFEC7B7FFFFFFFF7FF99039C3BFE",
INIT_11 => X"783E007E7DFBFFFCFE77FF9ECEFFFFFFFF77FFBDC3863FFF7EE1F7FFBF1F6DFF",
INIT_12 => X"FF77F07FD5FFFFFFFF6FFF7DE3CE77FF7EFFFBBF1E7EC6FE7FF087FFFFFFFFFE",
INIT_13 => X"FFEFFF7CF38F77FFBEFFFDFF9F3EC37BCFE087FFFFFFFFFE7801CF3FFF01C0F9",
INIT_14 => X"BFFFFEFFF79F73861FF107FFFFFFFFFE78079FBFFFCFF8F3BCEFCFEFEDFFFFFF",
INIT_15 => X"B1FF01FFFFFFFFFE781F9FBFFF3FFC0E36DFBFFFFBFFFFFFFFEFFEFEFF9FD7FF",
INIT_16 => X"7C3FCE7FFF6F3FFE77BFBFFFD7FFFFFFFEEFFDFE379FD7FFBF3FFEFFFF5F3FFF",
INIT_17 => X"E73F41FBEFFFFFFFFEDFFDFE0387FBFFBB8FFEFFFEEFC7FFF9FF81FFFFFFFFFE",
INIT_18 => X"FDDFFBFFC707FBFFB9CFFEC3FF73FB0EFFFFC3FFFFFFFFFE7EFFF1FFFEC30FCE",
INIT_19 => X"B9C7FEC2FFFDFEF3F1FF87FFFFFFFFFE7FFFFFFFFD830F0338FF43FBCFFFFFFF",
INIT_1A => X"3FFF8C7FFFFFFFFE7FFFFFFFFDF81F0367FED7F3BFFFFFFFFDBFF3FFE707FBFF",
INIT_1B => X"7FFFFFFFFBFFFFDFEFFDA7C37FFF80FFFFBFF7FFE66779FFBDE3FF709E7E7FFF",
INIT_1C => X"DFFBCFCFFFFF3DFFFB7FF99E0EEE7CFFFFF3FF72FF5F9FFFEFFF038FFFFFFFFE",
INIT_1D => X"FF7FFC0C0CFE7CFFDFFBFF73E3A75FFFF7FFFFC0FFFFFFFE7FFFFFFFF97FF9F3",
INIT_1E => X"D3FBFE7FCBD36FFFFDFFFCE00FFFFFFE7FFFFFFFFDC019FFBFF7C7FEFFFCFDFF",
INIT_1F => X"FEFFFFC003FFFFFE7FFFFFFFFFFE38837FEDE7EDFFFBCBFFF7FFFC00ECFE7EFF",
INIT_20 => X"7FFFFFFFFF80FC02FFDFFF6DFFF70BFFF6FFFC01B47C7DFFD3FBFE07DFE5EFFF",
INIT_21 => X"FF3FFF73FFEF1BFFFFFFF804B6113DFFEFFBFC3B9FFB77FFFCFECF80000FFFFE",
INIT_22 => X"EDFFF806F783BDFFEFFBFC3D1FFDB3FFE3FC1FBFF807FFFE7FFFFFFF3F7FFFF6",
INIT_23 => X"F7FBFC7D9FFEDDFFEFF8FFBFFF0FFFFE7FFFFFFC9E78FFFF3ECFFE77FFEFBBFF",
INIT_24 => X"F700BFBFFFFFFFFE7FFFFFFDE679CFFFBC9F7C6FFFDFFBFFD5FFF600FB87BDFF",
INIT_25 => X"7FFFFFFDE77B8003BD3E3EFFFFB7BBFFD5FFEE04398FDDFFF7FBFC7EFFFFEE7F",
INIT_26 => X"FA1F1FDFFF7377FFFFFFDF3E3C0FDDFFFFFFFE7F7FFF6DBFF9C9FFDFFFFFFFFE",
INIT_27 => X"BFFFBBFE3F0FDFFFFB1DFE0FAFFEB6E7FEFF9EC1FFFFFFFE7FFFFFFCCF7E1FF7",
INIT_28 => X"FF9DFC17B9F6FBF7FF8F07FE7FFFFFFE7FFFFFFC0EFE0FEF961F9FBFFF6277FF",
INIT_29 => X"FFF867FF7FFFFFFE7FFFFFFF80BE007FFD0FE77FFF422FFFBBFF7FFFFFEFBEFF",
INIT_2A => X"7FFFFEFF9FFE030FFFE3F37FFEC32FFFFBFEE7FFC7F7BFFFFDDEFE33D97FDDB3",
INIT_2B => X"FEF7FAFFFE9FEFFF7FFCFBDFC7DFBF7FFFCFFE73E6FFDFB9FFFFF7FFBFFFFFFE",
INIT_2C => X"F7FDF98EC7FBA9BFFECF7EF3FBFFDEBDFFFFF00FBFFFFFFE7FFFFFFF1CF03B8F",
INIT_2D => X"FFFF7CFBFEFE1FEEFFFFFF07BFFFFFFE7FFFFFFF00027DFF7EFEFCFFFDBEDFFF",
INIT_2E => X"3FFFFF87BFFFFFFE7FFFFFFFE022FBFF3EFC3BFFFDBEFFFEF7F9FF1FCFFBA0FF",
INIT_2F => X"7FFFFFFFFC38F7FFF2BE77FFFFFEBFFFFFF83F4FFFCBA0DFFF7FB87BFFE63F7F",
INIT_30 => X"637FF7FFF7EDBFFDAFFFBF8FFFCFA1DFFF79DC0DFF667FBFBFFFFF83DFFFFFFE",
INIT_31 => X"4FFFB71CFBEFAFE0FFB3C005FFA37FCFDFFFFFD1DFFFFFFE7FFFFFFFFE1FEF0E",
INIT_32 => X"3FF3F001FFA3BFF7EFFFFFF83FFFFFFE7FFFFFFFFE0FDCE763FFF7FFCF2F7FFD",
INIT_33 => X"E7FFFFFF3FFFFFFE7FFFFFFFFF07D9F34AFFF7FFBDBFFFFFCE7F237CFFB7AFE1",
INIT_34 => X"7FFFFFFFFF87B7FBDAFEEFFF3FBEFFFB807E63FA9FF0AFF3B0D7F83FFFFFDFF3",
INIT_35 => X"DBFFFFFF7FBEFFFB9F7CC39EFE702763FB19F83FFFDFEFFDF7FFFFFFFFFFFFFE",
INIT_36 => X"BCFD8346DE702773FBF1381FFFCFEFFEF7FFFFFFFFFFFFFE7FFFFFFFFFC00FFD",
INIT_37 => X"BDF83C1FFF83F3FF37FFFFFFCFFFFFFE7FFFFFFFFFE01FFCDBFFDFFCC7BEFFF7",
INIT_38 => X"87FFFFFFC0FFFFFE7FFFFFFFFFC07FFEDBFFBF1BC7BEFFF6F3FB86EEDFF827FF",
INIT_39 => X"7FFFFFFFFFC07FFE9B1F7EFFC6F6FFFAEFFA8EFCFEFFE7BFBEF8FE0FFF19F9FF",
INIT_3F => X"000DFFEE3FDDFFFFFFEFEFFBEFFFFFFFBFEFFF83E7FFCFBFFF0FFFFFFFF07FE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
WRITE_MODE_B => "WRITE_FIRST",
WRITE_MODE_A => "WRITE_FIRST",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE556FFFAAAAAAAA55BFFFFEAAFFF94",
SRVAL_A => X"0",
INIT_3D => X"555516FFFFF9557FFFFFFFF95556AFAAEAAFFFFFFFFFFFFFAAAAAFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFE556BEAAAAAAAAA55AFFFFFAAFFF94015555BFFFF955BFFFFFFFFA6955AAAB",
INIT_3A => X"AAAFFFFFFFFFFFFEBEAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_39 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAA5AAAAAA9555AFFFFAAFFFD5",
INIT_38 => X"005545BFFFFE55BFFFFFFFFAA955AAABAAABFFFFFFFFFFFEAAAAFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFAAAA956A556955556FFFFAAFFFE5405505BFFFFE45BFFFFFFFEAA955AAAA",
INIT_35 => X"AAABFFFFFFFFFFFAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_34 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE956A555555555BFFFEAFFFF9",
INIT_33 => X"515505FFFFFE41BFFFFFFFEA5555AAAAAA9AFFFFFFFFFFEAAAAFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FEFFFFFFA55A955555515BFFFEAFFFFE555505BFFFFF51FFFFFFFFE95556AA95",
INIT_30 => X"5A96FFFFFFFFFFAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2F => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFFA5555555055457FFFAABFFFE",
INIT_2E => X"554005BFFFFF51BFFFFFFE955556AA956A9AFFFFFFFFFEAAAAFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFE5455555055457FFF95BFFFE555001BFFFFF51BFFFFFF954555AA695",
INIT_2B => X"5AABFFFFFFFFFEAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2A => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE955555505541BFFF95BFFFF",
INIT_29 => X"9554117FFFFF91BFFFFFE505555A95556ABFFFFFFFFFEAAAABFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFF954555515545BFFFA57FFFFE505116FFFFF91BFFFFFE555555A5555",
INIT_26 => X"6AFFFFFFFFFFE6AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_25 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFE954555555545FFFFE96FFFF",
INIT_24 => X"F905156FFFFF91BFFFFF9545555555555AFFFFFFFFFF96AAAFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFEFFFFFE555555555545FFFFF96FFFFF955555BFFFF95BFFFFF954555555415",
INIT_21 => X"5AFFFFFFFFFF96AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_20 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFE555055555555BFFFF96FFFF",
INIT_1F => X"FE55555AFFFFD5BFFFFE5555555554155AFFFFFFFFFE56AAAFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFEBFFFFE551015455545BFFFFE5FFFFFF944556FFFFE5BFFFFE551455055001",
INIT_1C => X"16FFFFFFFFFE56AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
INIT_1B => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEABFFFE501155455505BFFFFE5BFFF",
INIT_1A => X"FF951555FFFFF5BFFFF955555555540516FFFFFFFFF955AAAFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFAABFFFE950555515501BFFFFF5BFFFFF940055FFFFF5BFFFF9555055555505",
INIT_17 => X"56FFFFFFFFF5556AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA",
INIT_16 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFFF951555005501BFFFFF96FFF",
INIT_15 => X"FF940055BFFFF9BFFFE555545555555556FFFFFFFFE5556AFFFFFFFFFFFFEAFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAABFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFF",
INIT_13 => X"FFAAAFFFFE555540055056FFFFF96FFFFFD54555BFFFF9BFFF95155555555555",
INIT_12 => X"16FFFFFFFFD55AAAAFFFFFFFFFFFEABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAE",
INIT_11 => X"BFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFAAABFFFFA55540055456FFFFFE5BFF",
INIT_10 => X"FFE54545BFFFF9BFFE555515555555555BFFFFFFFF9556AAAFFFFFFFFFFFFEFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAABEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFEAAAFFFFF95541055416EABFFE46FFFFF95545BFFFF9BFFE45540555555555",
INIT_0D => X"6FFFFFFFFE5556AABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAFAA",
INIT_0C => X"BFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFFAFEAAABFFFFE5555555516A5BFFF46FF",
INIT_0B => X"FFFE55057FFFF9BFF9555415555555556FFFFFFFF95556AAFEBFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFEAABFAABFFFFFFFFFFFFFFFEAFFFFFFFFFFFFFF",
INIT_09 => X"AFAAAAAFFFFE9555555556A6BFFF95BFFFFF95046FFFF9BFE555555555555555",
INIT_08 => X"6FFFFFFFE55556AAFABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFAA",
INIT_07 => X"BFFFFFFFFFFFFFFFFAAAFFFFFFFFFFFFEBAAAAABFFFFE5415554556BFFFFD56F",
INIT_06 => X"FFFFE5411BFFF9BF95555555551415556FFFFFFE94155AAAFEBFFFFFFFFEAABF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFAAAAAA9ABFFFFFFFFFFFFFFFFAAFFFFFFFFFFFFF",
INIT_04 => X"EAAAAAABFFFFE5455555416BFFFFE56FFFFFF95416FFF9BA5555555555005555",
INIT_03 => X"6FFFFFE954555AAAFEBFFFFFFFEAAAFFFFFFFFFFFFFFFFFFFFFFFFFEAAAA555A",
INIT_02 => X"BFFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFAAAAAA5BFFFFF9550555515BFFFFE55B",
INIT_01 => X"FFFFFE5556FFFAE555555555551055556FFFFF9555556AABFEBFFFFFFE956BFF",
INIT_00 => X"FFFFFBFFFFFFFFFFFFFFFFFA9555555ABFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFF",
SRVAL_B => X"0",
INIT_3F => X"EABFFFFFFFFFFFFFEAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_A => X"0",
INIT_3C => X"FFFFFFFE001FFF8FFE0000003FFF9FFFFFFFFFFFFF01FFFFFFFFFFFFE03FFFE1",
INIT_32 => X"FFFFFE0003FFE1E0C003007FFFFCFFFFFFFFFFFFFFE0FFFFFFFFFFFFFE01FFF1",
INIT_2E => X"00080FFFFFE0FFFFFFFFFE01F8F87FFFFFFFFFFFFF00FFC7FFF83FFFFFFFC000",
INIT_38 => X"FC000001FFFFFFFFFFFFFFFFFF81FFFFFFFFFFFFF00FFFF1FE03FF800007FF7F",
INIT_0F => X"0000000011F03FFFC0E000000780000EF0000000007CFFFFFC000000033FFFFF",
INIT_13 => X"FFFFF80001FFFFFC000000003FFF0FFFFCE700000023803800000000007FFFFF",
INIT_35 => X"FFFFFFFFF007FFF9FFFFFE0001FFFFFFFFFFFF0001FFF8FDF003000FFFFFFFFF",
INIT_10 => X"F8E000000700000400000000003FFFFFFC000000023FFFFFFFFFF0003FFFFFE0",
INIT_1C => X"FFE00000FFFFFFFFFFFC07F8000001FFFC0000007FFFFFFFFFFFFFC000F9E0F0",
INIT_37 => X"FFFFFFC000FFFF7FF8000003FFFFFFFFFFFFFFFFFF81FFFFFFFFFFFFF007FFF9",
INIT_27 => X"FFFFFFFFF00000001B80000001FFDFE0000003FFF800027FFC7FFF01FF3C1FFF",
INIT_28 => X"3FE0000001FFFFF00000007FFC0007FFFE7FFE01FFFC1FFFFFFFFFFFFFF781FF",
INIT_1F => X"FF03FFFE003FE3E7E00FFFFE00FE0FFFFFE00001FFFFFFFFFFFF807C000000FF",
INIT_20 => X"E00FFFFC00FF0FFFFFE00003FFFFFBFFFFFF803FC00000FFFF8000003FFF3FFF",
INIT_B => X"0",
INIT_0D => X"F8000000039FFFFFFFFFF010FC3FFFC0000000000FFFFFFF800000000F030007",
INIT_1E => X"FF0000003FFF7FFFFF07FFF8007FE1E3C007FFFE00FF8FFFFFE00001FFFFFFFF",
INIT_1B => X"E00FFFFF007FFFFFFFE00000FFFFFFFFFFF00FF0000003FFF00000007FFFFFFF",
INIT_23 => X"7E00000007F7FFE00F00FFFFC00FE3FFC00FFFFC00FE0FFFFFFF000FFFFFF1FF",
INIT_30 => X"FFFFFFFFFE00FFF1FFFF003FFFFFE003FFFFF800007F8180000803FFFFF8FFFF",
INIT_2B => X"FFFFFFFFFF807F1FFFFFFFFFFF0000003FF80000001FFFF800000E0FFF0007FF",
INIT_1D => X"FFFE03F8000000FFFE0000007FFFFFFFFF9FFFE0007DE1F1C007FFFF007FEFFF",
INIT_0A => X"000000000E3E3FFE000000001F0F80007F80000000FFFFFFF8000000000FFFFF",
INIT_29 => X"0000001FFE000FFFFEFFFE00FFFC3FFFFFFFFFFFFFE018FFFFFFFFFFF8000000",
INIT_26 => X"FFFF9FFFFFFFC3FFFFFFFC3FF00000003C00000003FFDFC000001FFFF00003FF",
INIT_04 => X"FFFFFFF83FFFE0000000000007C70000000000003FDFC3FFC03FC00003FFFFFF",
INIT_14 => X"000000003FFFFFFFFE6FC00000FFE01C00000000007FFDFFF80000000003FFFF",
INIT_3A => X"FFFFFFFFE00FFFF18000FFF00000780FFFFFFFF0003FFF1FFE0000007FFFFFFF",
INIT_2F => X"FFFFFFFFF8F07FFFFFFFFFFFFF00FFF1FFFC00FFFFFFC001FFFFE000001F870C",
INIT_0C => X"FC000000003EFFFFF800000001DFFFFFFFFFF839F81FFFC0000000000FFF7FFF",
INIT_06 => X"000000001F9FC1FFF3FC000001FFFFFFF80000000001FFFFFFFFFFFC07FFF000",
INIT_2A => X"FFFFFF007FFC3FFFFFFFFFFFFFC03E3FFFFFFFFFFC0000003FF0000000FFFFF8",
INIT_03 => X"F00000000000007FFFFFFFFFFFFFE00000000300078600000000000E7FFFC7FC",
INIT_39 => X"FFFFFFFFFF01FFFFFFFFFFFFE00FFFF18E01FFC00001FE1FFFFFFFE0007FFF3F",
INIT_31 => X"FEFFC007FFFFE00FFFFFFC0003FFC1C1800001FFFFF8FFFFFFFFFFFFFFF07FFF",
INIT_09 => X"FFFFFFF9C00FFE000000000000783FFC000000001F0FC079FFC0000001FFFFFF",
WRITE_MODE_A => "WRITE_FIRST",
INIT_33 => X"E003003FFFFFFFFFFFFFFFFFFFE0FFFFFFFFFFFFFC03FFF1FFFFF0000FFFFFFF",
INIT_25 => X"F83FFFFFF83C1FFFFFBF803FFFFFE1FFFFFFF83FF00000007E00000003FFDFE0",
INIT_36 => X"FC4FFF00001FFFFFFFFFFF8001FFFE7FF8010003FFFFFFFFFFFFFFFFFFC0FFFF",
INIT_07 => X"FFF0000001FFFFFFF80000000000FFFFFFFFFFFC01FFF8000000000003E37CF0",
INIT_12 => X"F80000000007FFFFFFFFF00003FFFFE0000000003FFF1FFFFDE6000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_18 => X"FFFFFF00007007FFC00000003FFFFFFFFFFFFC0003F3E0FFC0FFC3C0003FFBFF",
INIT_11 => X"00000000013FFFFFFC000000001FFFFFFFFFF0000FFFFFE0000000003FFE1FFF",
INIT_0B => X"000000000F0300001E000000007FFFFFF8000000009FFFFFFFFFFDF9F00FFF00",
SRVAL_A => X"0",
INIT_3B => X"80007FF8C0000007FFFFFFFC003FFF1FFE0000003FFF9FFFFFFFFFFFFF01FFFF",
INIT_1A => X"FFFFFF0001F1E0F8E01FFFFF007FFFFFFFF000003FFFFFFFFFF00FC0000007FF",
INIT_16 => X"001FC000007FFFFFF9F0000003FFFFFFFFFFF80000FFFFFF000000003FFFFFFF",
INIT_05 => X"0000000007E73000000000003FDFC3FFE07E000003FFFFFFF00000000001D87F",
INIT_15 => X"FF3FE00001FFE07E00078000007FFDFFF80000000003FFFFFFFFF80000FFFFFE",
INIT_19 => X"E00000003FFFFFFFFFFFFE0001F1E0F8E07FFFE0007FFBFFFFF000000FFFFFFF",
INIT_0E => X"FFFFF0007FFFFFC00000000001F3FFFF8040000007830007F8000000007CFFFF",
INIT_3E => X"FFFFFFFFFE03FFFFFFFFFFFFC07FFFC1FF000FFFF00000003FFFFFFF000FFF87",
INIT_24 => X"06007FFFE003C3FFF01FFFFC007C1FFFFFFF801FFFFFE1FFFFFFF03FF8000000",
INIT_22 => X"FFFFE01FF80000007F0000000FFFBFF81F00FFFFC01FE3CFE00FFFFC00FF0FFF",
INIT_08 => X"F80000000003FFFFFFFFFFFC007FFC000000000003F07FF8000000001F1FC0FF",
INIT_02 => X"003FE00003FFFFFFF00000000000007FFFFFFFFFFFFFF00000001F8003000000",
INIT_3D => X"FF0000003FFFFFFFFFFFFFFFFE01FFFFFFFFFFFFC07FFFC1C0001FFCE0000000",
INIT_01 => X"0000001FFFFFCFF8001FF40003FFFFFFF00000000000043FFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFC0FFFFFFFFFFFFF803FFF9FFFFFC0007FFFFFFFFFFFF0003FFF0F0",
INIT_2D => X"FFFF00000387FFCC00000FFFFFC0FFFFFFFFFF01FBFC7FFFFFFFFFFFFF807F8F",
INIT_2C => X"FFFFFFFFFFFB80007FFC00000187FFF800000F87FF8003FFFFFFFF00F3FC3FFF",
INIT_17 => X"FBF0000007FFFFFFFFFFFC0000F81FFF800000003FFFFFFFFF7FF00003F7E07F",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_21 => X"FFF00007FFFFF3FFFFFFC01FF8000038FF8000001FFF3FFF3F01FFFF001FF3CF",
SRVAL_B => X"0",
INIT_3F => X"FFFFFFFFC07FFF81FFFC07FFFC0000001FFFFFFF8007FFC7FF8080003FFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_03 => X"FFFFFFFFFF07FFFFFFFFFFFF81FFFC03FFFFFFFFFFFF8000007FFFFFF800FFFF",
INIT_04 => X"FFFFFFFF03FFFC07FFFFFFFFCFFF8000001FFFFFFC00FFFFFFFE0003C7FFFFFF",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"FFF00000001FC000F800FCFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000FFFFFF",
INIT_01 => X"03FFFFFFF001FFE3FFFC800007FFFFFFFFFFFFFFFF03FFFFFFFFFFFF80FFFF01",
INIT_3D => X"FFFF81F8000001FFFFF00000001FC100F001FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"8000000000FFFFFFFFFF0018000003FFFFF00000000F8FF0F003FFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFF8000000000FFFFFFFFFF0000000007FFFFF8000000079FFF",
INIT_3A => X"F007FF7FFFFFFFFFFFFFFFFFFFFFFFFF800000000007FF00FE00000000000FFF",
INIT_39 => X"FFFE000000007FFFF00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000007FE00",
INIT_38 => X"6000000000001FFFFFFE003F8000FFFF801F3FDFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"F80000000003F8000000000000003FFFFFFFC0FFE03FFFFF00181FDFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFC00000000003C000000000000001FFFFFFFFE1FFE03FFFFE",
INIT_35 => X"03E01FCBFFFFFFFFFFFFFFFFFFFFFFFF8000000000078000000187E00007FFFF",
INIT_34 => X"FFFFF3F8601FFFFE0FC01FC3FFFFFFFFFFFFFFFFFFFFFFFF800000000007F800",
INIT_33 => X"000FFFE0001FFFFFFFFFF7F80001FFFE1F801FCFFFFFFFFFFFFF7FFFFFFFFFFF",
INIT_32 => X"80000000000078000003DFC0007FFFFFFF1FFFF80000FFFF3F803FFFFFFFFFFF",
INIT_31 => X"FFFC3FFFFFFFFFFF80000000000039C00003800000FFFFFFFC3FFFF80001FFFF",
INIT_30 => X"FF807FFFFFFFFFFFFFFC1FFFFFFFFFFF8000000000E003F80001000001FFFFFF",
INIT_2F => X"F87FFFFC00E7FFFFFF00FFFFFFFFFFFFFFFE1FFFFFFFFFFF8000000001F803FC",
INIT_2E => X"0000000003FFFFFFE0FFFFFC00FFFFFFFF00FFFFFFFFFFFFFFFF0FFFFFFFFFFF",
INIT_2D => X"8000000001F003F00003C000EFFFFFFF03FFFFFE00FFFFFFFF81FFFFFFFFFFFF",
INIT_2C => X"FFFF83FFFFFE3FFF8000000001F003000003C000FFFFFFFC07FFFFFF01FFFFFF",
INIT_2B => X"FF83FFFFFFFFFFFFFFFFC3FFFFFE0FFF8000000000F0FC0000000007FFFFFFF0",
INIT_2A => X"1FFFFFFF81FFFFFFFF83FFFFFFFFFFFFFFFFC1FFFFFF01FF800018000039F800",
INIT_29 => X"00000007FFFFFFE07FFFFFFF81FFFFFFFF83FFFFFFFFFFFFFFFFE1FFFFFF807F",
INIT_28 => X"800018000000200000000007FFFFFFC1FFCFFFFF81FFFFFFFFC3FFFFFFFFFFFF",
INIT_27 => X"FFFFF0FFFFFFE03F800000000000000000000807FFFFFE07FF9FFFFF83FFFFFF",
INIT_26 => X"FFC3FFFFFFFFFFFFFFFFF0FFFFFFF00780000000000001C00000FE0FFFFFF83F",
INIT_25 => X"FF3FFFFF07FFFFFFFFC1FFFFFFFFFFFFFFFFF87FFFFFFE038000000000000780",
INIT_24 => X"001FFF1FFFFFF0FFFE3FFFF007BFFFFFFFE03FFFFFFFFFFFFFFFF87FFFFFFF01",
INIT_23 => X"8000000000000E0007FFFFFFFFFFC3FFFC7FFFE00707FFFFFFE03FFFFFFFFFFF",
INIT_22 => X"FFFFFC3FFFFFFF8180000000000000000FFFFFFFFFFF0FFFFC7FFFE00307FFFF",
INIT_21 => X"FFF03FFFFFFFFFFFFFFFFC3FFFFFFFE180000000000000003FFFFFFFFFF83FFF",
INIT_20 => X"F3FFFFE0070FFFFFFFF83FFFFFFFFFFFFFFFFE1CFFFFFFF1E00FE00000001838",
INIT_1F => X"7FFFFFFFFFF0FFFFFFFFFFE00E0FFFFFFFFC7FFFBFFFFFFFFFFFFE0CFFFFFFF9",
INIT_1E => X"F03F000000001FFFFFFFFFFFFF83FFFFDFFFFFF80E0FFFFFFFFFFFFF9FFFFFFF",
INIT_1D => X"FFFFFF047FFFFFFDE030000000000FFFFFFFFFFFFF0FFFFFDFFFFFF8041FFFFF",
INIT_1C => X"FFFFFFFFDFFFFFFFFFFFFF007FFFFFFDE000000000000FFFFFFFFFFFF83FFFFF",
INIT_1B => X"3FFFFFF0001FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFFFFFFC000000000000FFF",
INIT_1A => X"FFFFFFFFE0FFFFFE1FFFFFF0001FFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFFFFF",
INIT_19 => X"C000000000000FFFFFFFFFFF83FFFFF83FFFFFF0003FFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFC07FFFFFFFC000000000007FFFFFFFFFF80FFFFFF07FFFFFF0003FFFFF",
INIT_17 => X"FFFFFFFFEFFFFFFFFFFFFFC07FFFFFFFC00000000001FFFFFFFFFFE03FFFFFE0",
INIT_16 => X"FFFFFFF8003FFFFFFFFFFFFFE3FFFFFFFFFFFFE07FFFFFFFC00000000001FFFF",
INIT_15 => X"FFFFFC00FFFFFFC0FFFFFFF8C63FE3FFFFFFFFFFE3FFFFFFFFFFFFE07FFFFFFF",
INIT_14 => X"800000000000FFFFFFFFF803FFFFFF01FFFFFFF8E27F83FFFFFFFFFFF1FFFFFF",
INIT_13 => X"FFFFFFF07FFFFFFF800000000000FFFFFFFFC007FFFFFE03FFFFFFFDF0FF03FF",
INIT_12 => X"FFFFFFFFF9FFFFFFFFFFFFF07FFFFFFF8000000000007FFFFFFF000FFFFFFC07",
INIT_11 => X"FFFFFFF9F0FE03FFFFFFFFFFF8FFFFFFFFFFFFF03FFFFFFF8000000000003FFF",
INIT_10 => X"FFE0003FFFFFF01FFFFFFFF9F0FC07FFFFFFFFFFF8FFFFFFFFFFFFF83FFFF7FF",
INIT_0F => X"8000000000000FFFFF80007FFFFFF83FFFFFFFF0F0F807FFFFFFFFFFF87FFFFF",
INIT_0E => X"E7FFFFF83FFFF1FF8000000000000FFFFF0000FFFFFF907FFFFFFFF078E00FFF",
INIT_0D => X"FFFFFFFFFC7FFFFFE3FFFFFC1FFFE0FF8000000000FC07FFFE0003FFFFFE00FF",
INIT_0C => X"FFFFFFF078001FFFFFFFFFFFFC3FFFFFE3FFFFFC0FFFF0FF8000000001FE07FF",
INIT_0B => X"F80007FFFFFC01FFFFFFFFF0FFFFFFFFFFFFFFFFF83FFFFFF9FFFFFE0FFFF87F",
INIT_0A => X"E000000001FF07FFC0001FFFFFF003FFFFFFF3F1FFFFFFFFFFFFFFFFF81FFFFF",
INIT_09 => X"F8FFFFFE07FFF81FFC00000071FF87FE00007FFFFFE007FFFFFF01E1FFFFFFFF",
INIT_08 => X"FFFFFFFFFC1FFFFFF8FFFFFE07FFF80FFE0000FFF0FFC3000001FFFFFFC01FFF",
INIT_07 => X"FFFF0041FFFFFFFFFFFFFFFFFC0FFFFFFFFFFFFF03FFFC07FFFF3FFFE37FC000",
INIT_06 => X"0007FFFFFF003FFFFFFE0003FFFFFFFFFFFFFFFFFE07FFFFFFFFFFFF03FFFC07",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SRVAL_B => X"0",
INIT_02 => X"FFFF800203FFFFFFFFFFFFFFFF07FFFFFFFFFFFF81FFFE01FFFFE3FFFFFF0000",
SRVAL_A => X"0",
INIT_05 => X"FFFFFFFFC7FF8000000FFFFFFE007FFFFFFE0003FFFFFFFFFFFFFFFFFE07FFFF",
INIT_00 => X"FFFF03FFFFFC000007FFFFFFC003FFC3FFF8800007FFFFFFFFFFFFFFFC03FFFF",
INIT_3F => X"FC00187FFFFFFFFFFFFFFFFFFFFFFFFF8000000000FFFFFFFFFF83FFFF000020"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_21 => X"FFFF00000C7FFF7F0041FFFFFFE0007FFFFFFFFF7FFFFFFFFFF000000003FFFF",
INIT_06 => X"80000000F03FFFFFFFFFFFFFFFFFFF8000000000001F3E31FF0003FF01FFFFFF",
INIT_0E => X"FC0007FFFFFFFFFFFFFFFFFFFFFFFFFD8000070FFE00000000003FFFFFFFFFFF",
SRVAL_A => X"0",
INIT_1A => X"FFFF80000000001FFFFFFFFFFFFFFFFE0000000000FCFFFE00003FFFFFF9FFFF",
INIT_1F => X"FFF80000000003FFFFFFFFFFFFFF83FFFFE00000007FFF1C0000FFFFFFF8007F",
INIT_12 => X"F0000000000FE00F00000FFFFFFFFFFFC7FFFFFFFFFFFF8180007FFE7C000000",
INIT_2C => X"001FFF03FFFFFFFFFFFFFFFFFFFFFFFF8FF00007FFC00007F80000003FFFFFFF",
INIT_38 => X"FFFFFE000003F000001FFFFFFFFFF1FFFFFFE0000FFFE000000007FFFFFFFFF9",
INIT_04 => X"FC0001FC1FFFFFFFFFFFFFFFFFFFFFFF80000000007FFFFFFFFFFFFFFFFFFE00",
INIT_07 => X"FFFFFFFFFFFFFFC000000000001E3E39FF0083FFC1FFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FF00000000FCFC7C00007FFFFFF00FFFFFFFFFFFFFC07FFFFFFF0000000000FF",
INIT_37 => X"FFF81FFFFFFFFFFFFFFFFE000000F000000FFFFFFFFFF8FFFFFFF0000FFFF000",
INIT_22 => X"0001FFFFFFC000FFFFFFFFFFFFFFFFFFFFE00000003FFFFFFFFFFF0FFFF3FFFF",
INIT_30 => X"FFFFF8001FFFFF00000007FFFFFFFFFFFFFFFFFFFFFFFFFF800000F800000078",
INIT_2A => X"FEFE00001FFFFFFFFFFFFF003E7FFFFC001FFFC003FFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFF8FC00001FF000007000000079FFFFFFFFFFFFE001FFFF8F8",
INIT_0C => X"0007FFFFFFFFFFFFE0000000000000007C0207FFFF8FFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"7E0107FFE3FFFFFFFFFFFFFFFFFFFFFF80000000FC3FFFFFFFFFFFFFFFFFFFE0",
INIT_2B => X"FFFFFE001FFFFFFC001FFF800FFFFFFFFFFFFFFFFFFFFFFF83F8001FFFE00007",
INIT_32 => X"FFFC7FFFFFFFFFFF873F83F0000000F00000007F0FFFFFFFFFFFF8000FFFFF00",
INIT_24 => X"FF0000000FFFFFFFFFFFFE03FF9FFFFFFFFE0000007FFFFC0001FFFFF00000FF",
INIT_16 => X"003FFFFFFFFFFFFFC00000000007F8FFC0001FFFFFFFFFFFFFFFFFFFFFFFF807",
INIT_13 => X"80000FFFFFFFFFFFF3FFFFFFFFFFFF018000FFF010000000000001FFFFFFFFFF",
INIT_0D => X"F800000000000000FC0007FFFFCFFFFFFFFFFFFFFFFFFFFF800000063C00FFFC",
INIT_2F => X"0000001F0FFFFFFFFFFFFC001FFFFE00000007FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"9F000000F000001C0000001F0FFFFFFFFFFFFC001FFFF82000000F8FFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFF3E00000000F87FFC00003FFFFFF00FFFFFFFFFFFFFF03FFF",
INIT_35 => X"FFFFF0000FFFFC000000FFFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFF8000000000",
INIT_34 => X"0000FFFFBFFFFF7FFFFFF0000FFFFE0000007FFFFFFFFFFFFFFC3FFFFFFFFFFF",
SRVAL_B => X"0",
INIT_18 => X"00003FFFFFFFFFFFFFFFFFFFFFFF03FFFFFFE0000000000001FFFFFFFFFFFFFF",
INIT_10 => X"80007FFFFC0000000000000007FFFFFFFC0000000001C002B80007FFFFFFFFFF",
INIT_20 => X"FFFFFFDFFFFFBFFFFFE000000CFFFF1C0000FFFFFFF0007FFFFFFFFFCF7FFFFF",
INIT_39 => X"003FFFFFFFFFE3FFFFFFC0003FFFC00000000FFFFFC7FFE0FFF81FFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFF000003E00000003FE000FC0001FC7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFF81FFFFFFFC000000000003FFFFFFFFFFFFFFE00000000000FFFFF",
INIT_11 => X"0000000FFFFFFFFFFC000000000FC00600000FFFFFFFFFFFFFFFFFFFFFFFFFF1",
INIT_1D => X"00007FFFFFF001FFFFFFFFFFFF03FFFFFFFE0000000001FFFFFFFFFFFFFFF9FF",
INIT_23 => X"FFFFFFFFFFFFFFFFFF80000003FFFFFFFFFFFF07FFE3FFFFFFFF00001C7FFFFF",
INIT_01 => X"80000000007FFFFFFFFFFFFFFFF000001FF00000001FE000FC0000FFFFFFFFFF",
INIT_17 => X"00000000000FFFFF80003FFFFFFFFFFFFFFFFFFFFFFFE03F807FE00000000000",
INIT_0F => X"FFFFFFFFFFFFFFF980000FFFFE00000000000000FFFFFFFFFC00000000018000",
INIT_08 => X"00000000001E7C78FF0103FFC1FFFFFFFFFFFFFFFFFFFFFF80000000F83FFFFF",
INIT_36 => X"00003FFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFE00000070000001FFFFFFFFFCFF",
INIT_26 => X"FFFF0000003FFFF00003FFFC003FE1FFFFFFFFFFFFFFFFFFFC0600003FFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFC018007FFE00000000000003FFFFFFFFFFFE00000000007F07F",
INIT_33 => X"BFFFE7E00000008000007FFF0FFFFFBFFFFFF8000FFFFF0000001FFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFF80000000003FFFFFFFFFFFFFFFFFFF0000000000001FFC23",
INIT_28 => X"FFFFFFFFFFFFFFFFF07C000FFFFF001FFFFFC0C003FFFFFFFFFF8C00003FFFF8",
INIT_29 => X"C0F8001FFFF00007FFFF00000FFFFFFFFFFFFF00103FFFF8000FFFF000FFFFFF",
INIT_31 => X"00000FFFFFFFFFFFFFFE7FFFFFFFFFFF800701F8000000F80000000F0FFFFFFF",
INIT_03 => X"00000000003FFC01FC0001F83FFFFFFFFFFFFFFFFFFFFFFF80000000007FFFFF",
INIT_0B => X"800000001E1FFFFFFFFFFFFFFFFFFFFF0000000000001C787E0107FFFF9FFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFF800000003C3FFFFFFFFFFFFFFFFFFFF800000000000E3C78",
INIT_27 => X"0007FFF8007FFFFFFFFFFFFFFFFFFFFFF80E0000FFFFFFFFFFFFF1C000FFFFFF",
INIT_00 => X"FFFFFFFFFFFFFFFF8000000000FFFFFFFFFFC7FFFFC000003FF00000001FC000",
INIT_1E => X"FFFFFFFFFC0FFFFFFFFC0000000001FFFFFFFFFFFFFFC1FFFFC0000000FFFE3C",
INIT_25 => X"FFFFFF00FC3FFFFFFFFE0000007FFFF80001FFFE000781FFFFFFFFFFFFFFFFFF",
INIT_15 => X"801FF800000000000007FFFFFFFFFFFFE00000000003F87FC0000FFFFFFFFFFF",
INIT_3A => X"FFFFC7007FFFC00000007FFFFF83FFC03FE01FFFFFFFFFFFFF1FFC00000FF000",
INIT_3B => X"00007FFFFF01FFC01FC01FFFFFFFFFFFBFBC0000001FE000007FFFFFFFFFC7FF",
INIT_3C => X"0001FFFFFFFFFFFF9FF80000003FC0003FFFFFFFFFFF0FFFFFFF87007FFFE000",
INIT_3D => X"8FF00000003F80007FFFFFFFFFFE1FFFFFFF87007FFFE00000007FFFFF81FFE0",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFFFC3FFFFFFF9F007FFFE00000003FFFFFC0FFF00001FFFFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFF3F007FFFE00000000FFFFFF0FFF00001FFFFFFFFFFFFE3C00000007F0000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"000007FFFFFFFFF00001FFFFFFFFFFFFFFC00000007F00007FFFFFFFFFF83FFF",
INIT_01 => X"0001FFFFFFFFFFFFFFC00000007C0000FFFFFFFFFFE07FFFFFFF3F007FFFE000",
INIT_02 => X"FFF80000007C0007FFFFFFFFFFC0FFFFFFFE3F807FFFE000000067FFFFFFFF00",
INIT_03 => X"FFFFFFFFFF00FFFFFFFE7F003FFFC0080300FFFFFFFFFE000000FFFFFFFFFFFF",
INIT_04 => X"FFFCFF803FFF001C0000FFFFFFFFF000000007FFFFFFFFFFFE3800000038007F",
INIT_05 => X"00007FFFE000000000000FFFFFFFFFFFFE200000800003FFFFFFFFFFFC03FFFF",
INIT_06 => X"00003FFFFFFFFFFFFE20000100000FFFFFFFFFFFF007FFFFFFF8FF803FFE001C",
INIT_07 => X"FE70000100003FFFFFFFFFFFE00FFFFFFFF8FF801FFC003C000003FC00000000",
INIT_08 => X"FFFFFFFFC00FFFFFFFF1FF821FFC007E0007000000000FFE00047FFFFFFFFFFF",
INIT_09 => X"FFF3FF9F1FF8007E000F800000003FFE000FFFFFFFFFFFFFFFE000070000FFFF",
INIT_0A => X"000F80000001FFFF801FFFFFFFFFFFFFFFC000070000FFFFFFF9FFFF801FFFFF",
INIT_0B => X"E01FFFFFFFFFFFFFFFC000060000FFFFFF81FFFF003FFFFFFFE3FF9F1FF800FE",
INIT_0C => X"FFC000060001FFFFF801FFFE003FFFFFFFE7FFFF1FE001FF000F80000007FFFF",
INIT_0D => X"F003FFFC007FFFFFFFC7FFFFFFC183FF003F2000000FF7FFE00FFFFFFFFFFFFF",
INIT_0E => X"FFC7FFF7FFC383FF00FFF000001FE3FFE007FFFFFFFFFFFFFFC01FDE0003FFFF",
INIT_0F => X"01FFF800003FC3FFC000FFFFFFFFFFFFFF803FFE3807FFFFE007FFF8007FFFFF",
INIT_10 => X"C000FFFFFFFFFFFFFF80FFFEFC07FFFFC007FFF000FFFFFFFF8FFFE7FFE3C7FF",
INIT_11 => X"FFC1FFFFFE07FFFF000FFFE001FFFFFFFF8FFFC3FFF9C7FF81FFF80000FF83FF",
INIT_12 => X"000FFF8003FFFFFFFF9FFF83FFF18FFF81FFFC0001FF01FF800F7FFFFFFFFFFF",
INIT_13 => X"FF1FFF83FFF08FFFC1FFFE0000FF00FC001F7FFFFFFFFFFFFFFFF0FFFFFFFFFE",
INIT_14 => X"C0FFFF00007F8078000EFFFFFFFFFFFFFFFFE07FFFF007FC001FF00003FFFFFF",
INIT_15 => X"0000FFFFFFFFFFFFFFFFE07FFFC003F0003FC00007FFFFFFFF1FFF01FFE00FFF",
INIT_16 => X"FFFFF1FFFF800000007FC0000FFFFFFFFF1FFE01FFE00FFFC0FFFF00003FC000",
INIT_17 => X"00FF80001FFFFFFFFF3FFE01FFF807FFC07FFF00001FF80000007FFFFFFFFFFF",
INIT_18 => X"FE3FFC003FF807FFC03FFF00000FFCF000003FFFFFFFFFFFFFFFFFFFFF000000",
INIT_19 => X"C03FFF000003FFFC00007FFFFFFFFFFFFFFFFFFFFE00000007FF80003FFFFFFF",
INIT_1A => X"C0007FFFFFFFFFFFFFFFFFFFFE0000001FFF00007FFFFFFFFE7FFC001FF807FF",
INIT_1B => X"FFFFFFFFFC0000001FFE0000FFFFFFFFFC7FF8001F9887FFC01FFF800181FFFF",
INIT_1C => X"3FFC0000FFFFC3FFFCFFFE61FF1183FFC00FFF8000E07FFFF000FC7FFFFFFFFF",
INIT_1D => X"F8FFFFF3FF0183FFE007FF8000783FFFF800003FFFFFFFFFFFFFFFFFFE800000",
INIT_1E => X"E007FF80003C1FFFFE00001FFFFFFFFFFFFFFFFFFFFFE0007FF80001FFFF03FF",
INIT_1F => X"FF00003FFFFFFFFFFFFFFFFFFFFFC000FFF00003FFFC07FFF8FFFFFF1F0181FF",
INIT_20 => X"FFFFFFFFFFFF0001FFE00003FFF807FFF9FFFFFE0F8383FFE007FFF8001E1FFF",
INIT_21 => X"FFC0000FFFF007FFF1FFFFFF0FEFC3FFF007FFFC00078FFFFF00007FFFFFFFFF",
INIT_22 => X"F3FFFFFF0FFFC3FFF007FFFE0003CFFFFC00007FFFFFFFFFFFFFFFFFFF800001",
INIT_23 => X"F807FFFE0001E3FFF000007FFFFFFFFFFFFFFFFF7F800000FF00000FFFF007FF",
INIT_24 => X"F800007FFFFFFFFFFFFFFFFE1F8030007F00001FFFE007FFE3FFF9FF07FFC3FF",
INIT_25 => X"FFFFFFFE1F807FFC7E00001FFFC007FFE3FFF1FBC7FFE3FFF807FFFF0000F1FF",
INIT_26 => X"3C00003FFF800FFFC3FFE0C1C3FFE3FFF803FFFF8000F07FFE00003FFFFFFFFF",
INIT_27 => X"C3FFC001C0FFE1FFFC03FFFFC000781FFF00603FFFFFFFFFFFFFFFFF3F81FFF8",
INIT_28 => X"FC03FFEFC0083C0FFFF0F801FFFFFFFFFFFFFFFFFF01FFF07800007FFF800FFF",
INIT_29 => X"FFFFF800FFFFFFFFFFFFFFFFFF01FF80000000FFFF801FFFC7FF8000001FC1FF",
INIT_2A => X"FFFFFFFFE001FC00000000FFFF001FFF87FF0000000FC0FFFE01FFCFE0003E0F",
INIT_2B => X"000001FFFF001FFF87FF00000007C0FFFE00FF8FF8003E07FFFFF8007FFFFFFF",
INIT_2C => X"0FFE00000007C07FFF00FF0FFC003F03FFFFFFF07FFFFFFFFFFFFFFFE30FFC00",
INIT_2D => X"FF00FF07FF01FF01FFFFFFF87FFFFFFFFFFFFFFFFFFDFE00000003FFFE003FFF",
INIT_2E => X"FFFFFFF87FFFFFFFFFFFFFFFFFFDFC00000007FFFE003FFF0FFE00000007C03F",
INIT_2F => X"FFFFFFFFFFFFF8000C000FFFFC007FFE0FFFC0000037C03FFF807F87FF01FF80",
INIT_30 => X"1C000FFFF8007FFE1FFFC000003FC03FFF803FF3FF81FFC07FFFFFFC3FFFFFFF",
INIT_31 => X"3FFFC003001FC01FFFC03FFBFFC0FFF03FFFFFFE3FFFFFFFFFFFFFFFFFFFF0F0",
INIT_32 => X"FFC00FFFFFC07FF81FFFFFFFFFFFFFFFFFFFFFFFFFFFE3F81C000FFFF000FFFE",
INIT_33 => X"1FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FC3C000FFFC000FFFC3FFFC003000FC01E",
INIT_34 => X"FFFFFFFFFFFFCFFC3C001FFFC001FFFC7FFF8007000FC00C7FE007FFFFC03FFC",
INIT_35 => X"3C001FFF8001FFFC60FF0067000FC01C3CE007FFFFE01FFE0FFFFFFFFFFFFFFF",
INIT_36 => X"43FE00FF000FC00C3C0007FFFFF01FFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_37 => X"7E0003FFFFFC0FFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C003FFF0001FFF8",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C007FFC0001FFF80FFC01FF0007C000",
INIT_39 => X"FFFFFFFFFFFFFFFF7CE0FF000001FFF01FFC01FF000000007F0001FFFFFE07FF",
INIT_3A => X"7FF1FF000001FFF03FFC03FF800000007F8001FFFFFF83FFFFFFFFFFFFFFFFFF",
INIT_3B => X"7FFC03FFC00000007FC000FFFFFFC1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"7FC000FFFFFFC0FFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFFBF1FF100003FFF0",
INIT_3D => X"FFFFFFFFFFFF81FFFFFFFFFFFFFFFFFFF3F1FFF80003FFE0FFF803F9C0000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFFFFFFE7F3FFF80003FFE1FFF00FF8E00000007FE000FFFFFFE0FF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFF3FFF00003FFC1FFF01FFC100000007FF0007FFFFFF07FFFFFFFFFFFFF801F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena131 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_6(13),
I1 => addra_6(14),
I2 => addra_6(16),
I3 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N18,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52,
O => douta_7(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N18
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N16,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53,
O => douta_7(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N16
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N14,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54,
O => douta_7(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N14
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N12,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55,
O => douta_7(5)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_1 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_11 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(1)
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq00001 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(12),
I1 => addra_6(13),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq000011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(14),
I1 => addra_6(16),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_221 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
I1 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
O => BU2_U0_blk_mem_generator_valid_cstr_N13
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena1 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena01 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(14),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena11 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena121 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(16),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_3 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(15),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_2 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(14),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_1 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(13),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_0 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(12),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_4 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N12,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N11,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_75 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
O => BU2_U0_blk_mem_generator_valid_cstr_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_65 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
O => BU2_U0_blk_mem_generator_valid_cstr_N11
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_3 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N10,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N9,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_74 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
O => BU2_U0_blk_mem_generator_valid_cstr_N10
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_64 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
O => BU2_U0_blk_mem_generator_valid_cstr_N9
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_2 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N7,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_73 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
O => BU2_U0_blk_mem_generator_valid_cstr_N8
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_63 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
O => BU2_U0_blk_mem_generator_valid_cstr_N7
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_1 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N6,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N5,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_72 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
O => BU2_U0_blk_mem_generator_valid_cstr_N6
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_62 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
O => BU2_U0_blk_mem_generator_valid_cstr_N5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_0 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N4,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N3,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_71 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
O => BU2_U0_blk_mem_generator_valid_cstr_N4
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_61 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
O => BU2_U0_blk_mem_generator_valid_cstr_N3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N2,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N1,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_7 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
O => BU2_U0_blk_mem_generator_valid_cstr_N2
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_6 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
O => BU2_U0_blk_mem_generator_valid_cstr_N1
);
BU2_XST_VCC : VCC
port map (
P => BU2_N1
);
BU2_XST_GND : GND
port map (
G => BU2_doutb(0)
);
end STRUCTURE;
-- synopsys translate_on
| gpl-2.0 | c0700e5be224fc401c54d572bcd3eb42 | 0.73688 | 2.59341 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 20 | 292,080 | `protect begin_protected
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`protect end_protected
| mit | 897e3b7a6e560d4e19109ebd8bdee870 | 0.955071 | 1.809284 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/chram/chram.vhd | 1 | 15,415 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity chram is
Port (
CLK : in std_logic;
CHRAM_A : in std_logic_vector(9 downto 0);
CHRAM_WR : in std_logic;
CHRAM_DI : in std_logic_vector(8 downto 0);
CHRAM_DO : out std_logic_vector(8 downto 0);
CHRAM_VA : in std_logic_vector(9 downto 0);
CHRAM_VD : out std_logic_vector(8 downto 0)
);
end chram;
architecture rtl of chram is
subtype word_t is std_logic_vector(8 downto 0);
type memory_t is array(0 to 1023) of word_t;
shared variable ram : memory_t := (
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000011", "001010000", "000101111", "001001101", "000101101", "000111000", "000110000", "000100000",
"000100000", "001110110", "000101110", "000100000", "000110010", "000101110", "000110010", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"011101111", "011100110", "011110000", "000100000", "000100000", "011101110", "011101001", "011101001",
"011110001", "011100110", "000100000", "000100000", "011101101", "011100111", "011110101", "000100000",
"000100000", "001000010", "001001001", "001001111", "001010011", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001010110", "001100101", "001110010", "000101110", "000100000", "000110001", "000101110", "000110010",
"000100000", "000101000", "001100011", "000101001", "000100000", "001001001", "001001001", "001001001",
"000100000", "000110001", "000111001", "000111000", "000111000", "000100000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111110", "001000100", "001001001", "001010010", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001001001", "001001110", "001000001", "001001100",
"001000101", "001001110", "001000100", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001000", "001000001", "001010011", "001000101", "001010010",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001001010", "001000001", "001001101", "001010000", "001000101", "001010010", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001001011", "001001100", "001000001", "001000100", "000110001", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001001101", "001000001", "001000110", "001001001", "001000001",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001010000", "001000001", "001000011", "001001101", "001000001", "001001110",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010000", "001001111", "001010000", "001001011", "001001111", "001010010", "001001110",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010011", "001001111", "001001011", "001001111", "000100000", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001010011", "001010100", "001000001", "001001100", "001001011",
"001000101", "001010010", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001011000", "001011001", "001011010", "001001111", "001001110", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001011010", "001010111", "000100000", "000100000", "000100000", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001000110", "001000001", "001001001", "001010010", "000100000", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001001111", "001001101", "001000010", "001000101",
"001010010", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001111", "001001100", "001001111", "001010010", "001000010",
"001000001", "001001100", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001000110", "001001001", "001010110", "001010100", "001000101", "001000101", "001001110",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010011", "001000001", "001001101", "001001111", "001010110", "001000001", "001010010", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001011000", "001000001", "001010010", "001010100", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000001", "001001110", "001010100", "001001111", "001001110", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010010", "001000001", "001001100", "001001100", "001011001", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010100", "001000101", "001010100", "001010010", "001001001", "001010011", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000010", "001000001", "001010010", "001010011", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000100000",
"000100000", "000100000", "001000100", "001000001", "001010100", "000100000", "000111010", "000100000",
"001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000100000", "000100000",
"000100000", "001010000", "001000011", "000110001", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101",
"001010011", "000110000", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000",
"000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011",
"000110001", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000", "000111010",
"000100000", "001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000110100",
"000100000", "000100000", "001010010", "001000101", "001011010", "000100000", "000111010", "000100000",
"001000011", "001001001", "001010010", "001000011", "001010101", "001010011", "000110101", "000100000",
"000100000", "001010010", "001000101", "001011010", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001000011", "001001001", "001010010", "001000011", "001010101",
"001010011", "000111001", "000100000", "000100000", "001010010", "001000101", "001011010", "000100000",
"000111010", "000100000", "001010000", "001000001", "001000111", "001000001", "001001110", "001001001",
"001001110", "001001001", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001010011", "001010000", "001001111", "001010010", "001010100", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001000111", "001000001", "001001100", "001000001", "001011000", "001001001", "001000001", "001001110",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111010", "000100000", "001010011", "001001111", "001001111", "000100000", "000100000",
"000100000", "000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000",
"000111010", "000100000", "001001110", "001001001", "001001110", "001001010", "001000001", "000100000",
"000100000", "000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010",
"000100000", "001001011", "000110010", "000100000", "000100000", "000100000", "000100000", "000100000",
"000100000", "000100000", "001000011", "001001111", "001001101", "000100000", "000111010", "000100000",
"001010100", "001010010", "001000101", "001000001", "001010011", "000100000", "000100000", "000100000",
"000100000", "001000011", "001001111", "001001101", "000000000", "000000000", "000000000", "000000000",
"001000001", "000111110", "100000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000",
"000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000", "000000000" );
begin
process(CLK)
begin
if rising_edge(CLK) then
if CHRAM_WR = '1' then
ram(to_integer(unsigned(CHRAM_A))) := CHRAM_DI;
else
CHRAM_DO <= ram(to_integer(unsigned(CHRAM_A)));
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
CHRAM_VD <= ram(to_integer(unsigned(CHRAM_VA)));
end if;
end process;
end rtl;
| gpl-3.0 | f4750163f94012519928e1553117bf29 | 0.637561 | 4.352061 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/delay_line.vhdl | 1 | 1,449 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END delay_line;
ARCHITECTURE vhdl OF delay_line IS
signal shift_reg : std_logic_vector(COUNT-1 downto 0);
signal shift_next : std_logic_vector(COUNT-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,sync_reset)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= data_in&shift_reg(COUNT-1 downto 1);
end if;
if (sync_reset = '1') then
shift_next <= (others=>'0');
end if;
end process;
-- output
data_out <= shift_reg(0) and enable;
END vhdl;
| gpl-3.0 | 920fe628399c96d88e3890ede91c69cb | 0.599034 | 3.22 | false | false | false | false |
APastorG/APG | rotator/rotator.vhd | 1 | 6,127 |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.complex_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity rotator is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MIN_OUTPUT_BIT : integer_exc := integer'low; --exception: value not set
MAX_OUTPUT_BIT : integer_exc := integer'low; --exception: value not set
ANGLE_DEGREES : real --compulsory
);
port(
input_real : in std_ulogic_vector;
input_imag : in std_ulogic_vector;
clk : in std_ulogic;
valid_input : in std_ulogic;
output_real : out std_ulogic_vector;
output_imag : out std_ulogic_vector;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture rotator_1 of rotator is
--assumed that both real and imag inputs have the same size
constant NORM_IN_HIGH : integer := input_real'high - SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input_real'low - SULV_NEW_ZERO;
--constant CHECKS : integer := real_const_mult_CHECKS(input'high,
-- input'low,
-- UNSIGNED_2COMP_opt,
-- ROUND_TO_BIT_opt,
-- MAX_ERROR_PCT_opt,
-- MULTIPLICANDS);
constant NORM_OUT_HIGH : integer := complex_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MAX_OUTPUT_BIT,
(1 => cos(ANGLE_DEGREES*MATH_PI/180.0),
2 => sin(ANGLE_DEGREES*MATH_PI/180.0)),
NORM_IN_HIGH,
NORM_IN_LOW,
is_signed => true);
constant NORM_OUT_LOW : integer := complex_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT,
(1 => cos(ANGLE_DEGREES*MATH_PI/180.0),
2 => sin(ANGLE_DEGREES*MATH_PI/180.0)),
NORM_IN_LOW,
is_signed => true);
constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_real_S : u_Sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_input_imag_S : u_Sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_real_S : u_Sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_output_imag_S : u_Sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
aux_input_real_s <= to_sfixed(input_real, aux_input_real_s);
aux_input_imag_s <= to_sfixed(input_imag, aux_input_imag_s);
rotator_s_1:
entity work.rotator_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT => MIN_OUTPUT_BIT,
MAX_OUTPUT_BIT => MAX_OUTPUT_BIT,
ANGLE_DEGREES => ANGLE_DEGREES
)
port map(
input_real => aux_input_real_s,
input_imag => aux_input_imag_s,
clk => clk,
valid_input => valid_input,
output_real => aux_output_real_s,
output_imag => aux_output_imag_s,
valid_output => valid_output
);
output_real <= to_std_ulogic_vector(aux_output_real_s);
output_imag <= to_std_ulogic_vector(aux_output_imag_s);
end architecture; | mit | 4281e4d514d3db24279abeaa604f18d0 | 0.389135 | 4.506657 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/DP_SRAM/dp_sram.vhd | 1 | 8,009 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;
entity dp_sram is
port (
-- CLOCK
CLK : in std_logic; -- 32MHz
nRESET : in std_logic;
-- PORT A
DI_A : in STD_LOGIC_VECTOR(7 downto 0);
DO_A : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR_A : in STD_LOGIC_VECTOR(17 downto 0);
nWE_A : in std_logic;
nCS_A : in std_logic;
nOE_A : in std_logic;
nWAIT_A : out std_logic;
-- PORT B
DI_B : in STD_LOGIC_VECTOR(31 downto 0);
DO_B : inout STD_LOGIC_VECTOR(31 downto 0);
ADDR_B : in STD_LOGIC_VECTOR(31 downto 2);
nWE_B : in std_logic;
nCS_B : in std_logic;
nOE_B : in std_logic;
WAIT_B : out std_logic;
MEM_MASK_B : in STD_LOGIC_VECTOR(3 downto 0);
-- SRAM
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic
);
end dp_sram;
architecture dp_sram_arch of dp_sram is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "11";
-- FSM States
type STATE_TYPE is ( IDLE,
ST_READ1_A,
ST_WRITE1_A,
ST_READ1_B, ST_READ2_B,
ST_WRITE1_B, ST_WRITE2_B, ST_WRITE3_B );
signal STATE : STATE_TYPE := IDLE;
signal A_LOCK : std_logic;
signal B_LOCK : std_logic;
signal nWAIT_B : std_logic;
signal nCS_B_L : std_logic;
signal nWE_B_L : std_logic;
signal MEM_MASK_B_L : STD_LOGIC_VECTOR(3 downto 0);
signal DI_B_L : STD_LOGIC_VECTOR(31 downto 0);
signal ADDR_B_L : STD_LOGIC_VECTOR(31 downto 2);
begin
nWE_B_L <= nWE_B when falling_edge (nCS_B);
MEM_MASK_B_L <= MEM_MASK_B when falling_edge (nCS_B);
DI_B_L <= DI_B when falling_edge (nCS_B);
ADDR_B_L <= ADDR_B when falling_edge (nCS_B);
WAIT_B <= (not nCS_B) or (not nWAIT_B);
CS_B_LATCH: entity work.D_Flip_Flop
PORT MAP(
rst => not nCS_B,
pre => not nRESET,
ce => nWAIT_B,
d => '1',
q => nCS_B_L
);
process (CLK)
begin
if rising_edge(CLK) then
if nRESET = '0' then
STATE <= IDLE;
nWAIT_A <= '1';
nWAIT_B <= '1';
A_LOCK <= '0';
B_LOCK <= '0';
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_D <= (OTHERS=>'Z');
else
if nCS_A = '1' then
A_LOCK <= '0';
end if;
if nCS_B = '1' then
B_LOCK <= '0';
end if;
if A_LOCK = '0' and nCS_A = '0' and STATE /= IDLE then
nWAIT_A <= '0';
end if;
if B_LOCK = '0' and nCS_B_L = '0' and (STATE /= IDLE or (STATE = IDLE and nCS_A = '0') ) then
nWAIT_B <= '0';
end if;
case STATE is
when IDLE =>
if A_LOCK = '0' and nCS_A = '0' then
nWAIT_A <= '0';
A_LOCK <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_A <= ADDR_A;
if nWE_A = '1' then
-- Read
SRAM_OE <= '0';
STATE <= ST_READ1_A;
else
-- Write
SRAM_WE <= '0';
SRAM_D(7 DOWNTO 0) <= DI_A;
STATE <= ST_WRITE1_A;
end if;
else
if nCS_B_L = '0' then
nWAIT_B <= '0';
B_LOCK <= '1';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
SRAM_A <= ADDR_B_L(18 downto 2) & '0';
if nWE_B_L = '1' then
-- Read
SRAM_UB <= '0';
SRAM_LB <= '0';
SRAM_OE <= '0';
STATE <= ST_READ1_B;
else
-- Write
if (ENDIAN_MODE = "11" and (MEM_MASK_B_L(0) = '1' or MEM_MASK_B_L(1) = '1') )
or (ENDIAN_MODE = "00" and (MEM_MASK_B_L(2) = '1' or MEM_MASK_B_L(3) = '1') )then
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(15 downto 0);
SRAM_UB <= not MEM_MASK_B_L(1);
SRAM_LB <= not MEM_MASK_B_L(0);
else
SRAM_D <= DI_B_L(23 downto 16) & DI_B_L(31 downto 24);
SRAM_UB <= not MEM_MASK_B_L(2);
SRAM_LB <= not MEM_MASK_B_L(3);
end if;
SRAM_WE <= '0';
if (ENDIAN_MODE = "11" and (MEM_MASK_B_L(2) = '1' or MEM_MASK_B_L(3) = '1') )
or (ENDIAN_MODE = "00" and (MEM_MASK_B_L(0) = '1' or MEM_MASK_B_L(1) = '1') ) then
STATE <= ST_WRITE1_B;
else
STATE <= ST_WRITE3_B;
end if;
else
SRAM_A <= ADDR_B_L(18 downto 2) & '1';
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(31 downto 16);
SRAM_UB <= not MEM_MASK_B_L(3);
SRAM_LB <= not MEM_MASK_B_L(2);
else
SRAM_D <= DI_B_L(7 downto 0) & DI_B_L(15 downto 8);
SRAM_UB <= not MEM_MASK_B_L(0);
SRAM_LB <= not MEM_MASK_B_L(1);
end if;
SRAM_WE <= '0';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
STATE <= ST_WRITE3_B;
end if;
end if;
end if;
end if;
when ST_READ1_A =>
DO_A <= SRAM_D(7 DOWNTO 0);
nWAIT_A <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when ST_WRITE1_A =>
nWAIT_A <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when ST_READ1_B =>
if ENDIAN_MODE = "11" then
DO_B(15 downto 0) <= SRAM_D;
else
DO_B(31 downto 16) <= SRAM_D(7 downto 0) & SRAM_D(15 downto 8);
end if;
SRAM_A <= ADDR_B(18 downto 2) & '1';
STATE <= ST_READ2_B;
when ST_READ2_B =>
if ENDIAN_MODE = "11" then
DO_B(31 downto 16) <= SRAM_D;
else
DO_B(15 downto 0) <= SRAM_D(7 downto 0) & SRAM_D(15 downto 8);
end if;
nWAIT_B <= '1';
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_D <= (OTHERS=>'Z');
STATE <= IDLE;
when ST_WRITE1_B =>
SRAM_UB <= '1';
SRAM_LB <= '1';
SRAM_WE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
STATE <= ST_WRITE2_B;
when ST_WRITE2_B =>
SRAM_A <= ADDR_B_L(18 downto 2) & '1';
if ENDIAN_MODE = "11" then
SRAM_D <= DI_B_L(31 downto 16);
SRAM_UB <= not MEM_MASK_B_L(3);
SRAM_LB <= not MEM_MASK_B_L(2);
else
SRAM_D <= DI_B_L(7 downto 0) & DI_B_L(15 downto 8);
SRAM_UB <= not MEM_MASK_B_L(0);
SRAM_LB <= not MEM_MASK_B_L(1);
end if;
SRAM_WE <= '0';
SRAM_CE0 <= '0';
SRAM_CE1 <= '1';
STATE <= ST_WRITE3_B;
when ST_WRITE3_B =>
nWAIT_B <= '1';
SRAM_D <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
STATE <= IDLE;
when OTHERS =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
end dp_sram_arch; | gpl-3.0 | 9074e11168ca367287c3f9f84674a7c0 | 0.424273 | 2.647603 | false | false | false | false |
APastorG/APG | counter/counter_tb.vhd | 1 | 10,474 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the counter module.
/
**************************************************************************************************/
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.counter_pkg.all;
use work.tb_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity counter_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture counter_tb1 of counter_tb is
/* types */
/**************************************************************************************************/
type T_overflow_behavior_tb is record
value : T_overflow_behavior;
is_defined : boolean;
end record;
type T_count_mode_tb is record
value : T_count_mode;
is_defined : boolean;
end record;
type T_set_reset_priority_tb is record
value : T_set_reset_priority;
is_defined : boolean;
end record;
/* constants */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true);
constant OVERFLOW_BEHAVIOR_opt : T_overflow_behavior_tb := (t_wrap, false);
--t_saturate, t_wrap
constant COUNT_MODE_opt : T_count_mode_tb := (t_up, true);
--t_up, t_down, t_input_signal
constant COUNTER_WIDTH_dep : positive_exc_tb := (1, false);
constant TARGET_MODE : boolean := true;
constant TARGET_dep : integer_exc_tb := (1, true);
constant TARGET_WITH_COUNT_opt : boolean_exc_tb := (t_false, true);--t_true, t_false
constant TARGET_BLOCKING_opt : boolean_exc_tb := (t_false, true);--t_true, t_false
constant USE_SET : boolean := true;
constant SET_TO_dep : integer_exc_tb := (1, true);
constant USE_RESET : boolean := true;
constant SET_RESET_PRIORITY_opt : T_set_reset_priority_tb := (t_set, true);--t_set, t_reset
constant USE_LOAD : boolean := false;
constant used_UNSIGNED_2COMP_opt : boolean
:= ite(UNSIGNED_2COMP_opt.is_defined,
UNSIGNED_2COMP_opt.value,
false);
constant used_OVERFLOW_BEHAVIOR_opt : T_overflow_behavior
:= ite(OVERFLOW_BEHAVIOR_opt.is_defined,
OVERFLOW_BEHAVIOR_opt.value,
t_wrap);
constant used_COUNT_MODE_opt : T_count_mode
:= ite(COUNT_MODE_opt.is_defined,
COUNT_MODE_opt.value,
t_up);
constant used_COUNTER_WIDTH_dep : positive_exc
:= ite(COUNTER_WIDTH_dep.is_defined,
COUNTER_WIDTH_dep.value,
0);
constant used_TARGET_dep : integer_exc
:= ite(TARGET_dep.is_defined,
TARGET_dep.value,
integer'low);
constant used_TARGET_WITH_COUNT_opt : boolean_exc
:= ite(TARGET_WITH_COUNT_opt.is_defined,
TARGET_WITH_COUNT_opt.value,
t_exc);
constant used_TARGET_BLOCKING_opt : boolean_exc
:= ite(TARGET_BLOCKING_opt.is_defined,
TARGET_BLOCKING_opt.value,
t_exc);
constant used_SET_TO_dep : integer_exc
:= ite(SET_TO_dep.is_defined,
SET_TO_dep.value,
integer'low);
constant used_SET_RESET_PRIORITY_opt : T_set_reset_priority
:= ite(SET_RESET_PRIORITY_opt.is_defined,
SET_RESET_PRIORITY_opt.value,
t_reset);
/* signals */
/**************************************************************************************************/
--IN--
signal clk : std_ulogic := '1';
signal enable : std_ulogic := '0';
signal count_mode_signal : std_ulogic := '0';
signal set : std_ulogic := '0';
signal reset : std_ulogic := '0';
signal load : std_ulogic := '0';
signal value_to_load : std_ulogic_vector(counter_CIW(used_UNSIGNED_2COMP_opt,
used_COUNTER_WIDTH_dep,
TARGET_MODE,
used_TARGET_dep,
USE_SET,
used_SET_TO_dep)
downto 1);
--OUT--
signal count : std_ulogic_vector(counter_CW(used_UNSIGNED_2COMP_opt,
used_COUNTER_WIDTH_dep,
TARGET_MODE,
used_TARGET_dep,
used_TARGET_WITH_COUNT_opt = t_true,
USE_SET,
used_SET_TO_dep)
downto 1);
signal count_is_target : std_ulogic_vector(ite(TARGET_MODE, 1, 0) downto 1);
constant test1 : std_ulogic_vector := "101101";
constant test2 : std_ulogic_vector := "010010";
/*================================================================================================*/
/*================================================================================================*/
begin
counter1:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
OVERFLOW_BEHAVIOR_opt => used_OVERFLOW_BEHAVIOR_opt,
COUNT_MODE_opt => used_COUNT_MODE_opt,
COUNTER_WIDTH_dep => used_COUNTER_WIDTH_dep,
TARGET_MODE => TARGET_MODE,
TARGET_dep => used_TARGET_dep,
TARGET_WITH_COUNT_opt => used_TARGET_WITH_COUNT_opt,
TARGET_BLOCKING_opt => used_TARGET_BLOCKING_opt,
USE_SET => USE_SET,
SET_TO_dep => used_SET_TO_dep,
USE_RESET => USE_RESET,
SET_RESET_PRIORITY_opt => used_SET_RESET_PRIORITY_opt,
USE_LOAD => USE_LOAD
)
port map(
clk => clk,
enable => enable,
count_mode_signal => count_mode_signal,
set => set,
reset => reset,
load => load,
value_to_load => value_to_load,
count => count,
count_is_target => count_is_target
);
-- pragma translate_off
process (clk)
begin
clk <= not clk after 2 ps;
end process;
process (enable)
begin
enable <= not enable after 5 ps;
end process;
process
begin
count_mode_signal <= '1';
reset <= '1';
set <= '0';
load <= '0';
value_to_load <= (others => '1');
value_to_load(value_to_load'left) <= '0';
value_to_load(value_to_load'right) <= '0';
wait for 25 ps;
reset <= '1';
set <= '1';
wait for 25 ps;
reset <= '0';
set <= '0';
wait for 25 ps;
reset <= '0';
set <= '1';
wait for 10 ps;
reset <= '0';
set <= '0';
wait for 35 ps;
count_mode_signal <= '0';
wait for 30 ps;
load <= '1';
wait for 10 ps;
load <= '0';
wait for 200 ps;
wait;
end process;
-- pragma translate_on
end architecture;
| mit | 20e2a04374e074458f7ecad2317d2712 | 0.345785 | 5.267407 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/small1_tb.vhdl | 1 | 6,355 | ------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Small connection to the FPGA ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a testbench to simulate the ZPU_Small1 core as used in the ----
---- *_small1.vhdl ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Small1_TB(Behave) (Entity and architecture) ----
---- File name: small1_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
library work;
use work.zpu_memory.all;
entity Small1_TB is
end entity Small1_TB;
architecture Behave of Small1_TB is
constant WORD_SIZE : natural:=32; -- 32 bits data path
constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant BRATE : positive:=115200;
component ZPU_Small1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='0'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=115200; -- RS232 baudrate
ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component ZPU_Small1;
signal clk : std_logic;
signal reset : std_logic:='1';
signal break : std_logic;
signal dbg : zpu_dbgo_t; -- Debug info
signal rs232_tx : std_logic;
signal rs232_rx : std_logic;
begin
zpu : ZPU_Small1
generic map(
WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
gpio_in => (others => '0'));
trace_mod : Trace
generic map(
ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
LOG_FILE => "small1_trace.log")
port map(
clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
end architecture Behave; -- Entity: Small1_TB
| bsd-3-clause | ab7bd77893d0f920ceab51f475644d64 | 0.348387 | 4.781791 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/gtia_priority.vhdl | 1 | 4,492 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia_priority IS
PORT
(
CLK : in std_logic;
colour_enable : in std_logic;
PRIOR : in std_logic_vector(7 downto 0);
P0 : in std_logic;
P1 : in std_logic;
P2 : in std_logic;
P3 : in std_logic;
PF0 : in std_logic;
PF1 : in std_logic;
PF2 : in std_logic;
PF3 : in std_logic;
BK : in std_logic;
P0_OUT : out std_logic;
P1_OUT : out std_logic;
P2_OUT : out std_logic;
P3_OUT : out std_logic;
PF0_OUT : out std_logic;
PF1_OUT : out std_logic;
PF2_OUT : out std_logic;
PF3_OUT : out std_logic;
BK_OUT : out std_logic
);
END gtia_priority;
ARCHITECTURE vhdl OF gtia_priority IS
signal P01 : std_logic;
signal P23 : std_logic;
signal PF01 : std_logic;
signal PF23 : std_logic;
signal PRI01 : std_logic;
signal PRI12 : std_logic;
signal PRI23 : std_logic;
signal PRI03 : std_logic;
signal PRI0 : std_logic;
signal PRI1 : std_logic;
signal PRI2 : std_logic;
signal PRI3 : std_logic;
signal MULTI : std_logic;
signal SP0 : std_logic;
signal SP1 : std_logic;
signal SP2 : std_logic;
signal SP3 : std_logic;
signal SF0 : std_logic;
signal SF1 : std_logic;
signal SF2 : std_logic;
signal SF3 : std_logic;
signal SB : std_logic;
signal SP0_next : std_logic;
signal SP1_next : std_logic;
signal SP2_next : std_logic;
signal SP3_next : std_logic;
signal SF0_next : std_logic;
signal SF1_next : std_logic;
signal SF2_next : std_logic;
signal SF3_next : std_logic;
signal SB_next : std_logic;
signal SP0_reg : std_logic;
signal SP1_reg : std_logic;
signal SP2_reg : std_logic;
signal SP3_reg : std_logic;
signal SF0_reg : std_logic;
signal SF1_reg : std_logic;
signal SF2_reg : std_logic;
signal SF3_reg : std_logic;
signal SB_reg : std_logic;
begin
-- Use actual GTIA logic...
P01 <= P0 or P1;
P23 <= P2 or P3;
PF01 <= PF0 or PF1;
PF23 <= PF2 or PF3;
PRI0 <= prior(0);
PRI1 <= prior(1);
PRI2 <= prior(2);
PRI3 <= prior(3);
MULTI <= prior(5);
PRI01 <= PRI0 or PRI1;
PRI12 <= PRI1 or PRI2;
PRI23 <= PRI2 or PRI3;
PRI03 <= PRI0 or PRI3;
SP0 <= P0 and not (PF01 and PRI23) and not (PRI2 and PF23);
SP1 <= P1 and not (PF01 and PRI23) and not (PRI2 and PF23) and ( not P0 or MULTI);
SP2 <= P2 and not P01 and not (PF23 and PRI12) and not (PF01 and not PRI0);
SP3 <= P3 and not P01 and not (PF23 and PRI12) and not (PF01 and not PRI0) and ( not P2 or MULTI);
SF0 <= PF0 and not (P23 and PRI0) and not (P01 and PRI01) and not SF3;
SF1 <= PF1 and not (P23 and PRI0) and not (P01 and PRI01) and not SF3;
SF2 <= PF2 and not (P23 and PRI03) and not (P01 and not PRI2) and not SF3;
SF3 <= PF3 and not (P23 and PRI03) and not (P01 and not PRI2);
SB <= not P01 and not P23 and not PF01 and not PF23;
-- register
process(clk)
begin
if (clk'event and clk='1') then
SP0_reg <= SP0_next;
SP1_reg <= SP1_next;
SP2_reg <= SP2_next;
SP3_reg <= SP3_next;
SF0_reg <= SF0_next;
SF1_reg <= SF1_next;
SF2_reg <= SF2_next;
SF3_reg <= SF3_next;
SB_reg <= SB_next;
end if;
end process;
-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
begin
SP0_next <= SP0_reg;
SP1_next <= SP1_reg;
SP2_next <= SP2_reg;
SP3_next <= SP3_reg;
SF0_next <= SF0_reg;
SF1_next <= SF1_reg;
SF2_next <= SF2_reg;
SF3_next <= SF3_reg;
SB_next <= SB_reg;
if (colour_enable = '1') then
SP0_next <= SP0;
SP1_next <= SP1;
SP2_next <= SP2;
SP3_next <= SP3;
SF0_next <= SF0;
SF1_next <= SF1;
SF2_next <= SF2;
SF3_next <= SF3;
SB_next <= SB;
end if;
end process;
-- output
P0_OUT <= SP0_reg;
P1_OUT <= SP1_reg;
P2_OUT <= SP2_reg;
P3_OUT <= SP3_reg;
PF0_OUT <= SF0_reg;
PF1_OUT <= SF1_reg;
PF2_OUT <= SF2_reg;
PF3_OUT <= SF3_reg;
BK_OUT <= SB_reg;
end vhdl; | gpl-3.0 | d4c7b0b9829cdec228574f6459194767 | 0.609305 | 2.429421 | false | false | false | false |
APastorG/APG | general/common_pkg.vhd | 1 | 50,613 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains general types, constants and functions oftenly used in other vhdl files
/
**************************************************************************************************/
library std;
use std.textio.all;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package common_pkg is
/* constants 0 */
/**************************************************************************************************/
--bit used as the first integer bit when representing a fixed point in a std_ulogic_vector. This
-- value should belong to the interval [0, 2**30]. It is also the value of the maximum number
-- of fractional values that will be representable
constant SULV_NEW_ZERO : integer := 2**30;
--maximum number of fractional bits that will be used when calculating a number like 1/3 in binary
constant FRACTIONAL_LIMIT : natural := 15;
--used paths:
--directory where the vhdl sources are
constant SOURCES_DIRECTORY : string := "C:\Users\Antonio\Desktop\Vivado_workspace\PFdC_vivado_project\PFdC_vivado\PFdC_vivado.srcs";
--directory where the solution .txt files are going to be stored
constant DATA_FILE_DIRECTORY : string := "C:\Users\Antonio\Desktop\Vivado_workspace\PFdC_vivado_project\PFdC_vivado\PFdC_vivado.srcs\data_files";
--same as the later but with double backslash \\
constant DATA_FILE_DIRECTORY_M : string := "C:\\Users\\Antonio\\Desktop\\Vivado_workspace\\PFdC_vivado_project\\PFdC_vivado\\PFdC_vivado.srcs\\data_files"; --double backslash for Matlab
--Active-HDL project directory
constant ACTIVE_HDL_PROJECT_PATH : string := "C:\Users\Antonio\Active_HDL\Active_HDL_workspace\PFdC_activeHDL";
--the length of the names used to name the real_const_mult solution files
constant FILE_NAME_LENGTH : positive := 16;
--to control when to show debugging messages
constant DEBUGGING : boolean := false;
constant SEPARATOR_STR : string := "*************************";
/* if then else functions 1 */
/**************************************************************************************************/
function ite(cond : boolean; if_true, if_false : integer) return integer;
function ite(cond : boolean; if_true, if_false : boolean) return boolean;
function ite(cond : boolean; if_true, if_false : real) return real;
function ite(cond : boolean; if_true, if_false : character) return character;
function ite(cond : boolean; if_true, if_false : string) return string;
function ite(cond : boolean; if_true, if_false : std_ulogic) return std_ulogic;
function ite(cond : boolean; if_true, if_false : std_ulogic_vector) return std_ulogic_vector;
function ite(cond : boolean; if_true, if_false : bit) return bit;
function ite(cond : boolean; if_true, if_false : bit_vector) return bit_vector;
function ite(cond : boolean; if_true, if_false : unsigned) return unsigned;
function ite(cond : boolean; if_true, if_false : signed) return signed;
function ite(cond : boolean; if_true, if_false : positive_exc) return positive_exc;
function ite(cond : boolean; if_true, if_false : natural_exc) return natural_exc;
function ite(cond : boolean; if_true, if_false : boolean_exc) return boolean_exc;
function ite(cond : boolean; if_true, if_false : T_round_style) return T_round_style;
function ite(cond : boolean; if_true, if_false : T_overflow_style) return T_overflow_style;
function ite(cond : boolean; if_true, if_false : u_ufixed) return u_ufixed;
function ite(cond : boolean; if_true, if_false : u_sfixed) return u_sfixed;
function ite(cond : boolean; if_true, if_false : boolean_v) return boolean_v;
/* math 2 */
/**************************************************************************************************/
--returns the ceiling of the log2
function log2ceil(
number : positive)
return integer;
--returns the floor of the log2
function log2floor(
number : positive)
return integer;
--returns the maximum of the two integers
function maximum(
a, b: integer)
return integer;
--returns the minimum of the two integers
function minimum(
a, b: integer)
return integer;
--reduces the numbe to an odd one via dividing by two until odd
function reduce_to_odd(
arg : positive)
return positive;
/* debugging 3 */
/**************************************************************************************************/
--shows a message, for debugging purposes
procedure msg_debug(arg: in positive_v; separator: string);
procedure msg_debug(arg: in string);
/* image extraction 4 */
/**************************************************************************************************/
procedure separator;
--returns the 'image attribute of integer type
function image(
sca: integer)
return string;
function real_rightest_dec_bit(
number: real)
return integer;
function real_image_length(
number : real)
return integer;
--returns the 'image attribute of positive_exc type
function image(
number : positive_exc)
return string;
--returns the 'image attribute of natural_exc type
function image(
number : natural_exc)
return string;
--returns the 'image attribute of boolean_exc type
function image(
bool : boolean_exc)
return string;
--returns the 'image attribute of T_round_style type
function image(
bool : T_round_style)
return string;
--returns the 'image attribute of real type
function image(
number: real)
return string;
--returns the 'image attribute of boolean type
function image(
sca: boolean)
return string;
--returns the 'image attribute of std_ulogic type
function image(
sca: std_ulogic)
return string;
--returns the 'image attribute of bit type
function image(
sca: bit)
return string;
--returns the 'image attribute of bit_vector type
function image(
vec : bit_vector)
return string;
--returns the 'image attribute of std_ulogic_vector type
function image(
vec : std_ulogic_vector)
return string;
--returns the 'image attribute of a T_csd type in the 0,1,-1 form
function image(
csd: T_csd)
return string;
--returns the 'image attribute of a u_ufixed type
function image(
u_u: u_ufixed)
return string;
--returns the 'image attribute of a u_sfixed type
function image(
u_s: u_sfixed)
return string;
/* vector manipulation 5 */
/**************************************************************************************************/
--calculates the absolute value of each real of the vector
function "abs"(
arg : real_v)
return real_v;
--returns the maximum positive in the vector
function maximum(
arg : positive_v)
return positive;
--returns the maximum integer in the vector
function maximum(
arg : integer_v)
return integer;
--returns the minimum integer in the vector
function minimum(
arg : integer_v)
return integer;
--returns the maximum real in the vector
function maximum(
arg : real_v)
return real;
--uses bubble sort in a vector of reals to order it from low to high
function order(
arg : real_v)
return real_v;
/* integer/binary conversion 6 */
/**************************************************************************************************/
--returns the minimum number of bits necessary to represent the number in signed/unsigned
function min_bits(
number : integer;
is_signed : boolean)
return natural;
--returns the minimum number of bits necessary to represent the number assuming the use of
-- unsigned for natural numbers and signed for negative
function min_bits(
number : integer)
return natural;
----------------------------------------------------------------------------------------------------
function error_pct(
A : real;
B : real)
return real;
--returns the smallest representation of a real number in u_ufixed form. The fractional bits are
-- limited by the constant FRACTIONAL_LIMIT.
function to_ufixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate)
return u_ufixed;
--returns the smallest representation of a real number in u_sfixed form. The fractional bits are
-- limited by the constant FRACTIONAL_LIMIT.
function to_sfixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate)
return u_sfixed;
----------------------------------------------------------------------------------------------------
--returns the std_ulogic_vector of the desired length that represents the number in signed/
-- unsigned. It asserts the desired length is enough, and that it is signed if number negative
function sulv_from_int(
number : integer;
is_signed : boolean;
length : positive)
return std_ulogic_vector;
--returns the std_ulogic_vector of minimum length that represents the number in signed/unsigned
function sulv_from_int(
number : integer;
is_signed : boolean)
return std_ulogic_vector;
--returns the the std_ulogic_vector of minimum length that represents the number, assuming
-- signed for negative numbers and unsigned for the rest
function sulv_from_int(
number : integer)
return std_ulogic_vector;
--returns the canonical signed digit of the input vector. It returns a type T_csd which is an
-- array of length 2-slv. It encodes three values 0, 1, and -1 as "00","01",and "11"
-- respectively. If the parameter is_signed is ignored it is assumed the vector represents a
-- positive value.
function to_csd(
vector : u_ufixed)
return T_csd;
function to_csd(
vector : u_sfixed)
return T_csd;
----------------------------------------------------------------------------------------------------
--returns the maximum signed that can be represented
function max_vec(
vector : signed)
return signed;
--returns the minimum signed that can be represented
function min_vec(
vector : signed)
return signed;
--returns the maximum unsigned that can be represented
function max_vec(
vector : unsigned)
return unsigned;
--returns the minimum unsigned that can be represented
function min_vec(
vector : unsigned)
return unsigned;
--returns the maximum signed(as slv) that can be represented
function max_vec(
vector : signed)
return std_ulogic_vector;
--returns the minimum signed(as slv) that can be represented
function min_vec(
vector : signed)
return std_ulogic_vector;
--returns the maximum unsigned(as slv) that can be represented
function max_vec(
vector : unsigned)
return std_ulogic_vector;
--returns the minimum unsigned(as slv) that can be represented
function min_vec(
vector : unsigned)
return std_ulogic_vector;
--returns the maximum std_ulogic_vector that can be represented
function max_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector;
--returns the minimum std_ulogic_vector that can be represented
function min_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector;
/* arithmetic operators 7 */
/**************************************************************************************************/
--several functions to complete the functionality of the numeric_std package's
-- operators "+" and "-" so they return std_ulogic_vectors as well
function "+"(
vector : unsigned;
number : integer)
return std_ulogic_vector;
function "+"(
vector : signed;
number : integer)
return std_ulogic_vector;
function "+"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector;
function "+"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector;
function "-"(
vector : unsigned;
number : integer)
return std_ulogic_vector;
function "-"(
vector : signed;
number : integer)
return std_ulogic_vector;
function "-"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector;
function "-"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector;
/* other operators 10 */
/**************************************************************************************************/
--several functions to complete the functionality of operators +, -, *, /, ** so they accept an
-- integer and a real as parameters. It converts the integer to real
function "+"(
i : integer;
r : real)
return real;
function "+"(
r : real;
i : integer)
return real;
function "-"(
i : integer;
r : real)
return real;
function "-"(
r : real;
i : integer)
return real;
function "*"(
i : integer;
r : real)
return real;
function "*"(
r : real;
i : integer)
return real;
function "/"(
i : integer;
r : real)
return real;
function "/"(
r : real;
i : integer)
return real;
function "**"(
i : integer;
r : real)
return real;
function "**"(
r : real;
i : integer)
return real;
/* pipeline functions 11 */
/**************************************************************************************************/
--generates a vector of booleans which indicates in which position to place the pipelines out of
--all the possible ones depending on the parameter SPEED
function generate_pipelines(
positions : natural;
speed : T_speed)
return boolean_v;
function is_pipelined(
positions : natural;
speed : T_speed;
position : natural)
return boolean;
function number_of_pipelines(
positions : natural;
speed : T_speed)
return natural;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package body common_pkg is
/********************************************************************************************** 1 */
function ite(cond: boolean; if_true, if_false: integer) return integer is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean) return boolean is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: real) return real is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: character) return character is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: string) return string is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: std_ulogic) return std_ulogic is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: std_ulogic_vector) return std_ulogic_vector is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: bit) return bit is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: bit_vector) return bit_vector is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: unsigned) return unsigned is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: signed) return signed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: positive_exc) return positive_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: natural_exc) return natural_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean_exc) return boolean_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: T_round_style) return T_round_style is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: T_overflow_style) return T_overflow_style is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: u_ufixed) return u_ufixed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: u_sfixed) return u_sfixed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean_v) return boolean_v is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
/********************************************************************************************** 2 */
function log2ceil(number: positive)
return integer is
begin
return integer(ceil(log2(real(number))));
end function;
function log2floor(number: positive)
return integer is
begin
return integer(floor(log2(real(number))));
end function;
--returns the maximum of the two integers
function maximum(
a, b: integer)
return integer is
begin
return ite(a>b, a, b);
end function;
--returns the minimum of the two integers
function minimum(
a, b: integer)
return integer is
begin
return ite(a<b, a, b);
end function;
--reduction to odd number
function reduce_to_odd(
arg : positive)
return positive is
variable aux : positive := arg;
begin
if arg mod 2 = 1 then
return arg;
else
return reduce_to_odd(arg/2);
end if;
end function;
/********************************************************************************************** 3 */
procedure msg_debug(arg: in positive_v; separator: string) is
constant left : integer := arg'left;
constant right : integer := arg'right;
variable message : line;
begin
write(message, image(arg(left)));
if left /= right then
for i in arg'range loop
if i /= left then
write(message, separator);
write(message, image(arg(i)));
end if;
end loop;
end if;
writeline(output, message);
end procedure;
procedure msg_debug(
arg : in string)
is
variable message : line;
begin
if DEBUGGING then
write(message, arg);
writeline(OUTPUT, message);
end if;
end procedure;
/********************************************************************************************** 4 */
procedure separator is
begin
assert false
report SEPARATOR_STR
severity warning;
end procedure;
function image(
sca: integer)
return string is
begin
return integer'image(sca);
end;
function real_rightest_dec_bit(
number: real)
return integer is
variable copy : real := "mod"(number, 1.0);
variable counter : integer := 0;
begin
--for i in -FRACTIONAL_LIMIT to 0 loop
while copy /= 0.0 and counter > -FRACTIONAL_LIMIT loop
copy := "mod"(10.0*copy, 1.0);
counter := counter - 1;
end loop;
return counter;
end function;
function real_image_length(
number : real)
return integer is
constant rightest_frac_bit : integer := real_rightest_dec_bit(number);
constant fractional_bits : natural := -rightest_frac_bit;
constant integer_bits : integer := 1+integer(floor(log10(realmax(abs(number),1.0))));--at least 1
variable result : positive;
begin
if number = 0.0 then --'0'
result := 3;
elsif abs(number)<1.0 then --'0,f..f'
result := 2+fractional_bits; -- +2 for the leading '0.'
elsif fractional_bits=0 then --'i..i'
result := integer_bits;
else --'i..i,f..f'
result := integer_bits+1+fractional_bits; -- +1 because of the comma
end if;
if number<0.0 then --add the minus sign
return result+1;
else
return result;
end if;
end function;
function image(
number: real)
return string is
constant rightest_frac_bit : integer := real_rightest_dec_bit(number);
variable remain : real := abs(number);
constant fractional_bits : natural := -rightest_frac_bit;
constant integer_bits : natural := 1+integer(floor(log10(realmax(remain,1.0))));--at least 1
constant string_length : integer := real_image_length(number);
variable result : string(1 to string_length);
variable j : integer := 1; --string index
begin
if number = real'low then
return "real'low";
elsif number = real'high then
return "real'high";
end if;
--minus sign
if number < 0.0 then
result(j) := '-';
j := j + 1;
end if;
--integer bits
result(j to j+integer_bits-1) := real'image(floor(remain))(1 to integer_bits);
j := j+integer_bits;
remain := "mod"(remain, 1.0);
--fractional bits with the '.'
if fractional_bits > 0 then
result(j) := '.';
j := j + 1;
for i in 1 to fractional_bits loop
remain := remain * 10;
result (j) := image(integer(floor(remain)))(1);
remain := "mod"(remain, 1.0);
j := j + 1;
end loop;
end if;
return result;
end;
function image(
number : positive_exc)
return string is
begin
return integer'image(integer(number));
end function;
function image(
number : natural_exc)
return string is
begin
return integer'image(integer(number));
end function;
function image(
bool : boolean_exc)
return string is
begin
return boolean_exc'image(bool);
end function;
function image(
bool : T_round_style)
return string is
begin
return T_round_style'image(bool);
end function;
function image(
sca: boolean)
return string is
begin
return boolean'image(sca);
end;
function image(
sca: std_ulogic)
return string is
begin
return std_ulogic'image(sca);
end;
function image(
sca: bit)
return string is
begin
return bit'image(sca);
end;
function image(
vec: bit_vector)
return string is
variable result : string(1 to vec'length);
variable iterator : integer;
begin
iterator := vec'left;
for i in result'range loop
if (vec(iterator) = '1') then
result(i) := '1';
else
result(i) := '0';
end if;
iterator := ite(vec'ascending, iterator+1, iterator-1);
end loop;
return result;
end;
function image(
vec: std_ulogic_vector)
return string is
variable result : string(1 to vec'length);
variable iterator : integer;
begin
iterator := vec'left;
for i in result'range loop
if (vec(iterator) = '1') then
result(i) := '1';
else
result(i) := '0';
end if;
iterator := ite(vec'ascending, iterator+1, iterator-1);
end loop;
return result;
end;
function image(
csd: T_csd)
return string is
variable message : string(1 to 2*csd'length+1);
variable i, j : positive := 1;
begin
for i in csd'range loop
if csd(i) = "00" then
message(j) := '0';
j := j+1;
elsif csd(i) = "01" then
message(j) := '1';
j := j+1;
elsif csd(i) = "11" then
message(j to j+1) := "-1";
j := j+2;
else
assert false
report
"ERRROR on function image(T_csd): received illegal value ""10""."
severity error;
end if;
if i = 0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
return message;
end function;
function image(
u_u: u_ufixed)
return string is
constant string_length : positive := 2+1+maximum(1+u_u'high, 1)-u_u'low; --+2:quotes, +1:comma
variable message : string(1 to string_length);
variable i : integer;
variable j : positive := 1; --string index
begin
message(j) := '"';
j := j + 1;
if u_u'high < 0 then
message(j to j+1) := "0.";
if u_u'high < -1 then
message (j+2 to j -u_u'high) := (others =>'0');
end if;
end if;
for i in u_u'range loop
message(j) := image(u_u(i))(2);
j := j+1;
if i=0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
message(j) := '"';
return message;
end function;
function image(
u_s: u_sfixed)
return string is
constant string_length : positive := 2+1+maximum(1+u_s'high, 1)-u_s'low; --+2:quotes, +1:comma
variable message : string(1 to string_length);
variable i : integer;
variable j : positive := 1; --string index
begin
message(j) := '"';
j := j + 1;
if u_s'high < 0 then
message(j to j+1) := "0.";
if u_s'high < -1 then
message (j+2 to j -u_s'high) := (others =>'0');
end if;
end if;
for i in u_s'range loop
message(j) := image(u_s(i))(2);
j := j+1;
if i=0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
message(j) := '"';
return message;
end function;
/********************************************************************************************** 5 */
function "abs"(
arg : real_v)
return real_v is
variable result : real_v(arg'range);
begin
for i in arg'range loop
result(i) := abs(arg(i));
end loop;
return result;
end function;
function maximum(
arg : positive_v)
return positive is
variable result : positive := positive'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function maximum(
arg : integer_v)
return integer is
variable result : integer := integer'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function minimum(
arg : integer_v)
return integer is
variable result : integer := integer'high;
begin
for i in arg'range loop
if arg(i) < result then
result := arg(i);
end if;
end loop;
return result;
end function;
function maximum(
arg : real_v)
return real is
variable result : real := real'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function order(
arg : real_v)
return real_v is
variable result : real_v(1 to arg'length) := arg;
variable aux : real;
begin
for i in 1 to result'high-1 loop
for j in 1 to result'high-i loop
if result(i) > result(i+1) then
aux := result(i);
result(i) := result(i+1);
result(i+1) := aux;
end if;
end loop;
end loop;
return result;
end function;
/********************************************************************************************** 6 */
function min_bits(
number : integer;
is_signed : boolean)
return natural is
begin
if number=0 then
return 1;
end if;
if number=-1 then
return 1;
end if;
if is_signed then
if number<0 then
if number=integer'low then
return 32;
else
return 1+log2ceil(abs(number));
end if;
elsif number=integer'high then
return 32;
else
return 1+log2ceil(number+1);
end if;
else
if number<0 then
assert false
report
"ERROR in function min_bits: trying to represent negative numbers in unsigned"
severity error;
return 0; --trying to represent negative numbers in unsigned
elsif number=integer'high then -- in unsigned
return 31;
else
return log2ceil(number+1);
end if;
end if; --added the condition number<0 when is_signed is false
-- because when using ite to control which value of
-- is_signed will be sent to min_bits some errors will
-- appear even though the condition is never reached
end function;
function min_bits(
number : integer)
return natural is
begin
if number>=0 then
return min_bits(number, false);
else
return min_bits(number, true);
end if;
end function;
----------------------------------------------------------------------------------------------------
function error_pct(
A : real;
B : real)
return real is
begin
if B = 0.0 then
return real'high;
else
return abs(100*(A-B)/B);
end if;
end function;
function to_ufixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate) --fixed_truncate, fixed_round
return u_ufixed is
constant number_int : natural := integer(floor(abs(number)));
constant number_uf : u_ufixed := to_ufixed(abs(number),
-1,
-FRACTIONAL_LIMIT,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
constant int_bits : integer := min_bits(number_int);
constant frac_bits : integer := -find_rightmost(number_uf, '1');
variable result : u_ufixed(int_bits-1 downto -frac_bits);
variable new_low : integer := result'low;
begin
result := to_ufixed(number,
int_bits-1,
-frac_bits,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
assert number >= 0.0
report
"ERROR in function to_ufixed: real number must be natural"
severity error;
--check if the number is either real'low, real'high as their real'image is not a number representation, but "#INF"
-- Also with 0.0, 1.0, and -1.0 as their representation is 0 downto 0 and this generates errors with functions from
-- the fixed_generic_pkg
if number = real'high then
return to_ufixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = 0.0 then
return to_ufixed(0.0, 0, -1);
elsif number = 1.0 then
return to_ufixed(1.0, 0, -1);
end if;
--in this part the fractional bits that are unnecesary are discarded accordingly with the error_pct
if result'low <0 then
for i in result'low to minimum(result'high, -1) loop
if error_pct(to_real(resize(result,
result'high,
i)),
number)<= max_error_pct
then new_low := i;
end if;
end loop;
--number 0 causes an error because (0 downto 0) is not liked by the function cleanvec from the
-- fixed point package. So the first(-1) fractional bit is only discarded when the number
-- of integer bits is greater than 1
if result'high > 0 then
if error_pct(to_real(resize(result,
result'high,
0)),
number)<= max_error_pct
then new_low := 0;
end if;
end if;
end if;
return resize(result, result'high, new_low);
end function;
function to_sfixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate) --fixed_truncate, fixed_round
return u_sfixed is
constant number_int : integer := integer(floor(number));
constant number_uf : u_ufixed := to_ufixed(abs(number),
-1,
-FRACTIONAL_LIMIT,
round_style => round_style,
overflow_style => fixed_wrap);
constant int_bits : integer := min_bits(number_int, is_signed=>true);
constant frac_bits : integer := -find_rightmost(number_uf, '1');
constant result : u_sfixed := to_sfixed(number,
int_bits-1,
-frac_bits,
round_style => round_style,
overflow_style => fixed_wrap);
variable new_low : integer := result'low;
begin
--check if the number is either real'low, real'high as their real'image is not a number representation, but "-1.#INF00" and "1.#INF00"
-- Also with 0.0, 1.0, and -1.0 as their representation is 0 downto 0 and this generates errors with functions from
-- the fixed_generic_pkg
if number = real'low then
return to_sfixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = real'high then
return to_sfixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = 0.0 then
return to_sfixed(0, 0, -1);
elsif number = 1.0 then
return to_sfixed(1.0, 1, 0);
elsif number = -1.0 then
return tO_sfixed(-1.0, 0, -1);
end if;
--in this part the fractional bits that are unnecesary are discarded accordingly with the error_pct
if result'low <0 then
for i in result'low to minimum(result'high, -1) loop
if error_pct(to_real(resize(result,
result'high,
i)),
number)<= max_error_pct
then new_low := i;
end if;
end loop;
--number 0 causes an error because (0 downto 0) is not liked by the function cleanvec from the
-- fixed point package. So the first(-1) fractional bit is only discarded when the number
-- of integer bits is greater than 1
if result'high > 0 then
if error_pct(to_real(resize(result,
result'high,
0)),
number)<= max_error_pct
then new_low := 0;
end if;
end if;
end if;
return resize(result, result'high, new_low);
end function;
----------------------------------------------------------------------------------------------------
function sulv_from_int(
number : integer;
is_signed : boolean;
length : positive)
return std_ulogic_vector is
begin
if is_signed then
return std_ulogic_vector(to_signed(number, length));
else
return std_ulogic_vector(to_unsigned(abs(number), length));
end if;
end function;
function sulv_from_int(
number : integer;
is_signed : boolean)
return std_ulogic_vector is
begin
return sulv_from_int(number, is_signed, min_bits(number, is_signed));
end function;
function sulv_from_int(
number : integer)
return std_ulogic_vector is
begin
return sulv_from_int(number, number<0);
end function;
----------------------------------------------------------------------------------------------------
function to_csd(
vector : u_ufixed)
return T_csd is
constant aux_vector : u_ufixed := resize(vector, vector'high+1 , vector'low);
variable flag : integer := vector'low-1;
variable result : T_csd(aux_vector'range) := (others => "00");
begin
for i in result'reverse_range loop --from low to high
if aux_vector(i)='0' then
if flag = i-1 then
flag := i;
elsif flag = i-2 then
result(i-1) := "01"; -- 1
flag := i;
else
result(flag+1) := "11"; -- -1
result(i) := "01"; -- 1
flag := i-1;
end if;
end if;
end loop ;
return result(result'high-1 downto result'low); --discard higher bit as it is the "sign"(in csd the values of a number in its
--positive and negative form can be represented in the same amount of bits)
end function;
function to_csd(
vector : u_sfixed)
return T_csd is
constant is_negative : boolean := to_real(vector) < 0.0;
constant aux_vector : u_sfixed := "abs"(vector); --to_csd of the absolute value and then invert the values
variable result : T_csd(aux_vector'high+ 1 downto aux_vector'low);
begin
result := to_csd(to_ufixed(to_real(aux_vector), aux_vector'high, aux_vector'low));
--invert values: -1 to 1, and 1 to -1
if is_negative then
for i in result'range loop
case result(i) is
when "11" => result(i) := "01";
when "01" => result(i) := "11";
when others => null;
end case;
end loop;
end if;
return result;
end function;
----------------------------------------------------------------------------------------------------
function max_int(
bits : positive;
signed_data : boolean)
return integer is
begin
if signed_data then
return 2**(bits-1)-1;
else
return 2**bits-1;
end if;
end function;
function min_int(
bits : positive;
signed_data : boolean)
return integer is
begin
if signed_data then
return -2**(bits-1);
else
return 0;
end if;
end function;
----------------------------------------------------------------------------------------------------
function max_vec(
vector : signed)
return signed is
variable aux : signed(vector'length downto 1);
begin
aux := (others => '1');
aux(vector'length) := '0';
return aux;
end function;
function min_vec(
vector : signed)
return signed is
variable aux : signed(vector'length downto 1);
begin
aux := (others => '0');
aux(vector'length) := '1';
return aux;
end function;
function max_vec(
vector : unsigned)
return unsigned is
variable aux : unsigned(vector'range);
begin
aux := (others => '1');
return aux;
end function;
function min_vec(
vector : unsigned)
return unsigned is
variable aux : unsigned(vector'range);
begin
aux := (others => '0');
return aux;
end function;
function max_vec(
vector : signed)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := max_vec(vector);
return std_ulogic_vector(aux);
end function;
function min_vec(
vector : signed)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := min_vec(vector);
return std_ulogic_vector(aux);
end function;
function max_vec(
vector : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := max_vec(vector);
return std_ulogic_vector(aux);
end function;
function min_vec(
vector : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := min_vec(vector);
return std_ulogic_vector(aux);
end function;
function max_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector is
begin
if signed_data then
return max_vec(signed(vector));
else
return max_vec(unsigned(vector));
end if;
end function;
function min_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector is
begin
if signed_data then
return min_vec(signed(vector));
else
return min_vec(unsigned(vector));
end if;
end function;
/********************************************************************************************** 7 */
function "+"(
vector : unsigned;
number : integer)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := vector + number;
return std_ulogic_vector(aux);
end function;
function "+"(
vector : signed;
number : integer)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := vector + number;
return std_ulogic_vector(aux);
end function;
function "+"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector1'range);
begin
aux := vector1 + vector2;
return std_ulogic_vector(aux);
end function;
function "+"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector is
variable aux : signed(vector1'range);
begin
aux := vector1 + vector2;
return std_ulogic_vector(aux);
end function;
function "-"(
vector : unsigned;
number : integer)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux :=vector - number;
return std_ulogic_vector(aux);
end function;
function "-"(
vector : signed;
number : integer)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := vector - number;
return std_ulogic_vector(aux);
end function;
function "-"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector1'range);
begin
aux := vector1 - vector2;
return std_ulogic_vector(aux);
end function;
function "-"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector is
variable aux : signed(vector1'range);
begin
aux := vector1 - vector2;
return std_ulogic_vector(aux);
end function;
/********************************************************************************************* 10 */
function "+"(
i : integer;
r : real)
return real is
begin
return real(i) + r;
end function;
function "+"(
r : real;
i : integer)
return real is
begin
return real(i) + r;
end function;
function "-"(
i : integer;
r : real)
return real is
begin
return real(i) - r;
end function;
function "-"(
r : real;
i : integer)
return real is
begin
return r - real(i);
end function;
function "*"(
i : integer;
r : real)
return real is
begin
return real(i) * r;
end function;
function "*"(
r : real;
i : integer)
return real is
begin
return real(i) * r;
end function;
function "/"(
i : integer;
r : real)
return real is
begin
return real(i) / r;
end function;
function "/"(
r : real;
i : integer)
return real is
begin
return r / real(i);
end function;
function "**"(
i : integer;
r : real)
return real is
begin
return real(i) ** r;
end function;
function "**"(
r : real;
i : integer)
return real is
begin
return r ** real(i);
end function;
/********************************************************************************************* 11 */
function generate_pipelines(
positions : natural;
speed : T_speed)
return boolean_v is
variable pipelines : natural;
variable aux : natural := positions;
variable result : boolean_v(1 to positions) := (others => false);
begin
case speed is
when t_min => return result;
when t_low => pipelines := integer(ceil(0.25 * real(aux)));
when t_medium => pipelines := integer(ceil(0.5 * real(aux)));
when t_high => pipelines := integer(ceil(0.75 * real(aux)));
when t_max => result := (others => true);
return result;
when t_exc => return result; --no value assigned
end case;
if pipelines>0 then
result(aux) := true;
if pipelines>1 then
for i in pipelines downto 2 loop
aux := aux - aux/pipelines;
result(aux) := true;
end loop;
end if;
end if;
return result;
end function;
function is_pipelined(
positions : natural;
speed : T_speed;
position : natural)
return boolean is
variable indexes : boolean_v(1 to positions) := generate_pipelines(positions,
speed);
begin
return indexes(position);
end function;
function number_of_pipelines(
positions : natural;
speed : T_speed)
return natural is
begin
case speed is
when t_min => return 0;
when t_low => return integer(ceil(0.25 * real(positions)));
when t_medium => return integer(ceil(0.5 * real(positions)));
when t_high => return integer(ceil(0.75 * real(positions)));
when t_max => return positions;
when others => return 0; --no value assigned
end case;
end function;
end package body; | mit | b0bf07b083c99c7598b067f491474237 | 0.522292 | 4.378376 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/syncreset_enable_divider.vhd | 1 | 2,225 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
SYNCRESET : in std_logic;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END syncreset_enable_divider;
ARCHITECTURE vhdl OF syncreset_enable_divider IS
function log2c(n : integer) return integer is
variable m,p : integer;
begin
m := 0;
p := 1;
while p<n loop
m:=m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant WIDTH : natural := log2c(COUNT);
signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
signal count_next : std_logic_vector(WIDTH-1 downto 0);
signal enabled_out_next : std_logic;
signal enabled_out_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
count_reg <= (others=>'0');
enabled_out_reg <= '0';
elsif (clk'event and clk='1') then
count_reg <= count_next;
enabled_out_reg <= enabled_out_next;
end if;
end process;
-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
process(count_reg,enable_in,enabled_out_reg,syncreset)
begin
count_next <= count_reg;
enabled_out_next <= enabled_out_reg;
if (enable_in = '1') then
count_next <= std_logic_vector(unsigned(count_reg) + 1);
enabled_out_next <= '0';
if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
count_next <= std_logic_vector(to_unsigned(0,WIDTH));
enabled_out_next <= '1';
end if;
end if;
if (syncreset='1') then
count_next <= std_logic_vector(to_unsigned(resetcount,width));
end if;
end process;
-- output
enable_out <= enabled_out_reg and enable_in;
END vhdl;
| gpl-3.0 | c0587a0ef9b621ecc1c35b71797148b9 | 0.628764 | 3.094576 | false | false | false | false |
APastorG/APG | adder/adder_tb.vhd | 1 | 6,227 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the adder module.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_generic_pkg.all;
use work.adder_pkg.all;
use work.tb_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_tb1 of adder_tb is
/* constants */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, false); --default
constant DATA_IMM_AFTER_START_opt : boolean_tb := (false, true); --default
constant SPEED_opt : T_speed_tb := (t_medium, true); --exception: value not set
constant MAX_POSSIBLE_BIT_opt : integer_exc_tb := (2, false); --exception: value not set
constant TRUNCATE_TO_BIT_opt : integer_exc_tb := (-2, false); --exception: value not set
constant S : positive := 2; --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_DATA_IMM_AFTER_START_opt : boolean := value_used(DATA_IMM_AFTER_START_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_MAX_POSSIBLE_BIT_opt : integer_exc := value_used(MAX_POSSIBLE_BIT_opt);
constant used_TRUNCATE_TO_BIT_opt : integer_exc := value_used(TRUNCATE_TO_BIT_opt);
/* signals */
/**************************************************************************************************/
constant P : positive := 4;
constant NORMALIZED_HIGH : integer := 1;
constant NORMALIZED_LOW : integer := 0;
constant IN_HIGH : natural := NORMALIZED_HIGH+SULV_NEW_ZERO;
constant IN_LOW : natural := NORMALIZED_LOW+SULV_NEW_ZERO;
constant OUT_HIGH : natural := SULV_NEW_ZERO+adder_OH(used_MAX_POSSIBLE_BIT_opt,
S,
P,
NORMALIZED_HIGH);
constant OUT_LOW : natural := SULV_NEW_ZERO+adder_OL(used_TRUNCATE_TO_BIT_opt,
NORMALIZED_LOW);
--IN--
signal input : sulv_v(1 to P)(IN_HIGH downto IN_LOW);
signal clk : std_ulogic := '1';
signal start : std_ulogic;
signal valid_input : std_ulogic;
--OUT--
signal output : std_ulogic_vector(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
----------------------------------------------------------------------------------------------------
signal aux_counter1 : unsigned(0 to 29) := to_unsigned(1, 30);
signal aux_counter2 : unsigned(0 to 29) := to_unsigned(2, 30);
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("adder_tb_IN_HIGH: " & image(IN_HIGH));
msg_debug("adder_tb_IN_LOW: " & image(IN_LOW));
msg_debug("adder_tb_OUT_HIGH: " & image(OUT_HIGH));
msg_debug("adder_tb_OUT_LOW: " & image(OUT_LOW));
adder1:
entity work.adder
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
DATA_IMM_AFTER_START_opt => used_DATA_IMM_AFTER_START_opt,
SPEED_opt => used_SPEED_opt,
MAX_POSSIBLE_BIT_opt => used_MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => used_TRUNCATE_TO_BIT_opt,
S => S
)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
--pragma translate off
process (clk)
begin
if rising_edge(clk) then
aux_counter1 <= aux_counter1 + to_unsigned(1, 30);
aux_counter2 <= aux_counter2 + to_unsigned(1, 30);
end if;
end process;
process (clk)
begin
clk <= not clk after 2 ps;
end process;
--generates pseudorandom values for the input
process (clk)
variable real_number : real;
variable seed1 : positive := to_integer(aux_counter1);
variable seed2 : positive := to_integer(aux_counter2);
begin
if rising_edge (clk) then
for i in 1 to P loop
uniform(seed1, seed2, real_number);
input(i) <= to_sulv(to_ufixed(real_number, -1, -1 -IN_HIGH + IN_LOW));
end loop;
end if;
end process;
--pragma translate on
end architecture; | mit | 0c7b542b286e77cda68944ccd88c36e7 | 0.419667 | 4.4458 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/dac/dac.vhd | 2 | 1,149 | library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;
| gpl-3.0 | d4926ec262895db646faed9c649a30a7 | 0.558747 | 2.735714 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/heatersLogic.vhd | 1 | 2,957 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity heatersLogic is
generic(
heatNumber : natural := 20
);
port(
rsDataIn : in std_logic_vector(7 downto 0);
rsRdy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
readyOut : out std_logic
);
end heatersLogic;
architecture Behavioral of heatersLogic is
component Heater
port(
rst : IN std_logic;
clk50Mhz : IN std_logic;
pulseWidth : IN std_logic_vector(7 downto 0);
heaterEnable : OUT std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Heater: component is "TRUE";
type registers is array (1 to heatNumber) of std_logic_vector(7 downto 0);
signal reg : registers := (others => X"00");
type state_type is (start, number, value);
signal state, next_state : state_type;
signal save : std_logic := '0';
signal hNumber : integer range 0 to heatNumber := 0;
type enableSignal is array (1 to heatNumber) of std_logic;
signal heaterEnableSignal : enableSignal := (others => '0');
attribute keep : string;
attribute keep of heaterEnableSignal: signal is "true";
attribute S: string;
attribute S of heaterEnableSignal: signal is "yes";
begin
readyOut <= '1';
Heaters_instances:
for I in 1 to heatNumber generate
InstHeater: Heater port map(
rst => rst,
clk50Mhz => clk50Mhz,
pulseWidth => reg(I),
heaterEnable => heaterEnableSignal(I)
);
end generate;
SYNC_PROC: process (clk50Mhz)
begin
if (clk50Mhz'event and clk50Mhz = '1') then
if (rst = '1') then
state <= start;
reg <= (others => X"00");
else
state <= next_state;
for I in 1 to heatNumber loop
if I = hNumber and save = '1' then
reg(I) <= rsDataIn;
else
reg(I) <= reg(I);
end if;
end loop;
end if;
end if;
end process;
OUTPUT_DECODE: process (state, rsDataIn, rsRdy, hNumber)
begin
if (state = number and rsRdy = '1') then
hNumber <= to_integer(unsigned(rsDataIn));
save <= '0';
elsif (state = value and rsRdy = '1') then
hNumber <= hNumber;
save <= '1';
else
hNumber <= hNumber;
save <= '0';
end if;
end process;
NEXT_STATE_DECODE: process (state, rsDataIn, rsRdy)
begin
next_state <= state;
case (state) is
when start =>
if rsRdy = '1' and rsDataIn = X"55" then
next_state <= number;
end if;
when number =>
if rsRdy = '1' then
next_state <= value;
end if;
when value =>
if rsRdy = '1' then
next_state <= start;
end if;
when others =>
next_state <= start;
end case;
end process;
end Behavioral;
| mit | 08ec552c362072d2a62fa253c2368a44 | 0.56882 | 3.584242 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/rom/rom.vhd | 1 | 5,405 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32768,
c_read_depth_b => 32768,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32768,
c_write_depth_b => 32768,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
| gpl-3.0 | ca4fd5b729a29e20a2fe60bec1124a28 | 0.512673 | 3.980118 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/power.vhd | 4 | 8,722 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity power is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
y : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of power is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal tmp_2_fu_80_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_reg_102 : STD_LOGIC_VECTOR (5 downto 0);
signal i_1_fu_91_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_1_reg_110 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal exitcond_fu_86_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_71_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal result_int_reg_48 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_60 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_cast_fu_76_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
component sin_taylor_seriesbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesbkb_U1 : component sin_taylor_seriesbkb
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => result_int_reg_48,
din1 => x,
ce => ap_const_logic_1,
dout => grp_fu_71_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
i_reg_60_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_reg_60 <= i_1_reg_110;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_60 <= ap_const_lv6_1;
end if;
end if;
end process;
result_int_reg_48_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
result_int_reg_48 <= grp_fu_71_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
result_int_reg_48 <= ap_const_lv64_3FF0000000000000;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond_fu_86_p2 = ap_const_lv1_0))) then
i_1_reg_110 <= i_1_fu_91_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp_2_reg_102 <= tmp_2_fu_80_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, exitcond_fu_86_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond_fu_86_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state8)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (ap_const_logic_1 = ap_CS_fsm_state8))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state8)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= result_int_reg_48;
exitcond_fu_86_p2 <= "1" when (i_reg_60 = tmp_2_reg_102) else "0";
i_1_fu_91_p2 <= std_logic_vector(unsigned(i_reg_60) + unsigned(ap_const_lv6_1));
tmp_2_fu_80_p2 <= std_logic_vector(unsigned(tmp_cast_fu_76_p1) + unsigned(ap_const_lv6_1));
tmp_cast_fu_76_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(y),6));
end behav;
| mit | 675ae5226e3ddf25e2c11f5dbf61e88f | 0.5626 | 3.134028 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/txt_util.vhdl | 1 | 18,082 | ------------------------------------------------------------------------------
---- ----
---- Text Utils ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Utils to handle text. Used for the testbenches. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: txt_util (Package) ----
---- File name: txt_util.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- std.textio ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library zpu;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
function hstr(slv: unsigned) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
procedure str_write(file out_file: TEXT;
new_string: in string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end package txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
--synopsys translate off
write(msg_line, text);
writeline(output, msg_line);
--synopsys translate on
end procedure print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end procedure print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end function chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1):=chr(sl);
return s;
end function str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r:=1;
for i in slv'range loop
result(r) := chr(slv(i));
r:=r+1;
end loop;
return result;
end function str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end function str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end function chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer:=1;
variable power : integer:=1;
begin
-- bug fix for negative numbers
abs_int:=abs(int);
num :=abs_int;
while num>=base loop -- Determine how many
len:=len+1; -- characters required
num:=num/base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i):=chr(abs_int/power mod base); -- a string starting
power:=power*base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int<0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end function str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end function str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0):=(others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen:=(slv'left+1)/4;
if (slv'left+1) mod 4/=0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen-1) downto 0 loop
fourbit:=longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen-I):='0';
when "0001" => hex(hexlen-I):='1';
when "0010" => hex(hexlen-I):='2';
when "0011" => hex(hexlen-I):='3';
when "0100" => hex(hexlen-I):='4';
when "0101" => hex(hexlen-I):='5';
when "0110" => hex(hexlen-I):='6';
when "0111" => hex(hexlen-I):='7';
when "1000" => hex(hexlen-I):='8';
when "1001" => hex(hexlen-I):='9';
when "1010" => hex(hexlen-I):='A';
when "1011" => hex(hexlen-I):='B';
when "1100" => hex(hexlen-I):='C';
when "1101" => hex(hexlen-I):='D';
when "1110" => hex(hexlen-I):='E';
when "1111" => hex(hexlen-I):='F';
when "ZZZZ" => hex(hexlen-I):='z';
when "UUUU" => hex(hexlen-I):='u';
when "XXXX" => hex(hexlen-I):='x';
when others => hex(hexlen-I):='?';
end case;
end loop;
return hex(1 to hexlen);
end function hstr;
function hstr(slv: unsigned) return string is
begin
return hstr(std_logic_vector(slv));
end function hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u:='A';
when 'b' => u:='B';
when 'c' => u:='C';
when 'd' => u:='D';
when 'e' => u:='E';
when 'f' => u:='F';
when 'g' => u:='G';
when 'h' => u:='H';
when 'i' => u:='I';
when 'j' => u:='J';
when 'k' => u:='K';
when 'l' => u:='L';
when 'm' => u:='M';
when 'n' => u:='N';
when 'o' => u:='O';
when 'p' => u:='P';
when 'q' => u:='Q';
when 'r' => u:='R';
when 's' => u:='S';
when 't' => u:='T';
when 'u' => u:='U';
when 'v' => u:='V';
when 'w' => u:='W';
when 'x' => u:='X';
when 'y' => u:='Y';
when 'z' => u:='Z';
when others => u:=c;
end case;
return u;
end function to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l:='a';
when 'B' => l:='b';
when 'C' => l:='c';
when 'D' => l:='d';
when 'E' => l:='e';
when 'F' => l:='f';
when 'G' => l:='g';
when 'H' => l:='h';
when 'I' => l:='i';
when 'J' => l:='j';
when 'K' => l:='k';
when 'L' => l:='l';
when 'M' => l:='m';
when 'N' => l:='n';
when 'O' => l:='o';
when 'P' => l:='p';
when 'Q' => l:='q';
when 'R' => l:='r';
when 'S' => l:='s';
when 'T' => l:='t';
when 'U' => l:='u';
when 'V' => l:='v';
when 'W' => l:='w';
when 'X' => l:='x';
when 'Y' => l:='y';
when 'Z' => l:='z';
when others => l:=c;
end case;
return l;
end function to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):=to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):=to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' =>
sl:='U';
when 'X' =>
sl:='X';
when '0' =>
sl:='0';
when '1' =>
sl:='1';
when 'Z' =>
sl:='Z';
when 'W' =>
sl:='W';
when 'L' =>
sl:='L';
when 'H' =>
sl:='H';
when '-' =>
sl:='-';
when others =>
sl:='X';
end case;
return sl;
end function to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k:=s'high-s'low;
for i in s'range loop
slv(k):=to_std_logic(s(i));
k :=k-1;
end loop;
return slv;
end function to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i):=' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l,c,is_string);
res_string(i):=c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end procedure str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l,new_string);
writeline(out_file,l);
end procedure print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l,char);
writeline(out_file,l);
end procedure print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file,new_string(i));
if new_string(i)=LF then -- end of string
exit;
end if;
end loop;
end str_write;
end package body txt_util;
| bsd-3-clause | 85d27af693a937169625d72f7b3245fe | 0.427386 | 4.368688 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03300_good.vhd | 1 | 2,954 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03300_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Buffer port type: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_03300_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_A : in std_logic_vector(3 downto 0); -- Data to add
o_B : out std_logic_vector(3 downto 0) -- Data output
);
end STD_03300_good;
architecture Behavioral of STD_03300_good is
signal B : std_logic_vector(3 downto 0);
begin
-- Adding the input to the output using an internal signal to read from
P_Add : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
B <= (others => '0');
elsif (rising_edge(i_Clock)) then
B <= std_logic_vector(unsigned(i_A) + unsigned(B));
end if;
end process;
o_B <= B;
end Behavioral;
--CODE
| gpl-3.0 | cec84146a78a59a4a2938b2b6f3dc7b9 | 0.484089 | 4.509924 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/boot.vhd | 1 | 13,585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity boot is
port (
CLK50 : in std_logic;
SRAM_A : out std_logic_vector(18 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
KEYB_CLK : in std_logic;
KEYB_DATA : in std_logic;
COMM_CSA : in std_logic;
COMM_CSD : in std_logic;
COMM_SCK : in std_logic;
COMM_MOSI : in std_logic;
COMM_MISO : out std_logic;
COMM_RDY : out std_logic;
SD_MOSI : out std_logic := '1';
SD_MISO : in std_logic;
SD_SCK : out std_logic := '1';
SD_CS : out std_logic;
FL_CS : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic
);
end boot;
architecture rtl of boot is
-- SPI COMMANDS
constant CMD_VIDEO_MODE : std_logic_vector(7 downto 0) := X"00"; -- sequental or swapped read/write attr/char
constant CMD_VIDEO_X_POS : std_logic_vector(7 downto 0) := X"01";
constant CMD_VIDEO_Y_POS : std_logic_vector(7 downto 0) := X"02";
constant CMD_VIDEO_ATTR : std_logic_vector(7 downto 0) := X"03";
constant CMD_VIDEO_CHAR : std_logic_vector(7 downto 0) := X"04";
constant CMD_RAM_MODE : std_logic_vector(7 downto 0) := X"10"; -- 1/2 bytes address increment
constant CMD_RAM_H_ADDR : std_logic_vector(7 downto 0) := X"11";
constant CMD_RAM_M_ADDR : std_logic_vector(7 downto 0) := X"12";
constant CMD_RAM_L_ADDR : std_logic_vector(7 downto 0) := X"13";
constant CMD_RAM_DATA : std_logic_vector(7 downto 0) := X"14";
constant CMD_KEYBOARD : std_logic_vector(7 downto 0) := X"20";
signal CLK : std_logic;
signal VGA_CLK : std_logic;
signal LOCKED : std_logic;
signal TICK : unsigned(3 downto 0) := "0000";
signal RESET : std_logic := '1';
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal POS_X : unsigned(6 downto 0);
signal POS_Y : unsigned(4 downto 0);
signal VA : std_logic_vector(11 downto 0);
signal VDI : std_logic_vector(7 downto 0);
signal VDO : std_logic_vector(15 downto 0);
signal VWR : std_logic;
signal VATTR : std_logic_vector(7 downto 0);
signal VRG : std_logic_vector(7 downto 0);
signal RAM_A : std_logic_vector(19 downto 0);
signal RAM_DI : std_logic_vector(7 downto 0);
signal RAM_DO : std_logic_vector(7 downto 0);
signal RAM_RW : std_logic;
signal RAM_REQ : std_logic;
signal RAM_ACK : std_logic;
signal RAM_RG : std_logic_vector(7 downto 0);
signal COMM_AO : std_logic_vector(7 downto 0);
signal COMM_AI : std_logic_vector(7 downto 0);
signal COMM_A_REQ : std_logic;
signal COMM_A_ACK : std_logic;
signal COMM_DO : std_logic_vector(7 downto 0);
signal COMM_DI : std_logic_vector(7 downto 0);
signal COMM_D_REQ : std_logic;
signal COMM_D_ACK : std_logic;
signal COMM_RG : std_logic_vector(7 downto 0);
signal COMM_MA : std_logic_vector(19 downto 0);
signal KB_DATA : std_logic_vector(7 downto 0);
type STATES is (ST_IDLE, ST_READ_DATA, ST_WRITE_DATA, ST_READ_VRAM_A, ST_READ_VRAM_D, ST_READ, ST_WRITE, ST_INC);
signal STATE : STATES;
begin
SD_CS <= '1';
FL_CS <= '1';
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK,
VGA_CLK => VGA_CLK,
LOCKED => LOCKED );
u_VIDEO : entity work.video
port map(
CLK => CLK,
VGA_CLK => VGA_CLK,
RESET => RESET,
VA => VA,
VDI => VDI,
VDO => VDO,
VWR => VWR,
VATTR => VATTR,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
u_COMM_SPI : entity work.spi_comm
port map(
CLK => CLK,
RESET => RESET,
SPI_CS_A => COMM_CSA,
SPI_CS_D => COMM_CSD,
SPI_SCK => COMM_SCK,
SPI_DI => COMM_MOSI,
SPI_DO => COMM_MISO,
ADDR_O => COMM_AO,
ADDR_I => COMM_AI,
ADDR_REQ => COMM_A_REQ,
ADDR_ACK => COMM_A_ACK,
DATA_O => COMM_DO,
DATA_I => COMM_DI,
DATA_REQ => COMM_D_REQ,
DATA_ACK => COMM_D_ACK );
u_RAM : entity work.memctrl
port map(
CLK => CLK,
RESET => RESET,
MEM_A => RAM_A,
MEM_DI => RAM_DI,
MEM_DO => RAM_DO,
MEM_RW => RAM_RW,
MEM_REQ => RAM_REQ,
MEM_ACK => RAM_ACK,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
SRAM_CE0 => SRAM_CE0,
SRAM_CE1 => SRAM_CE1,
SRAM_OE => SRAM_OE,
SRAM_WE => SRAM_WE,
SRAM_UB => SRAM_UB,
SRAM_LB => SRAM_LB );
u_KEYBOARD : entity work.keyboard
port map(
clk => CLK,
reset => RESET,
PS2_Clk => KEYB_CLK,
PS2_Data => KEYB_DATA,
Key_Data => KB_DATA );
reset_generator : process(CLK)
begin
if rising_edge(CLK) then
if LOCKED = '1' then
if TICK /= "1111" then
TICK <= TICK + 1;
else
RESET <= '0';
end if;
end if;
end if;
end process;
p_state_machine : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= ST_IDLE;
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
COMM_RDY <= '0';
VWR <= '0';
RAM_REQ <= '0';
else
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
VWR <= '0';
RAM_REQ <= '0';
case STATE is
when ST_IDLE =>
if COMM_A_REQ = '1' then
COMM_A_ACK <= '1';
COMM_RG <= COMM_AO;
if COMM_AO(7) = '0' then
STATE <= ST_READ_DATA;
end if;
elsif COMM_D_REQ = '1' then
COMM_D_ACK <= '1';
if COMM_RG(7) = '0' then -- ### READ ###
STATE <= ST_READ_DATA;
else
STATE <= ST_WRITE_DATA;
end if;
end if;
when ST_READ_DATA =>
case ('0' & COMM_RG(6 downto 0)) is
when CMD_VIDEO_MODE =>
COMM_DI <= VRG;
STATE <= ST_IDLE;
when CMD_VIDEO_ATTR =>
VA <= std_logic_vector(POS_Y) & std_logic_vector(POS_X);
STATE <= ST_READ_VRAM_A;
when CMD_VIDEO_X_POS =>
COMM_DI <= '0' & std_logic_vector(POS_X);
STATE <= ST_IDLE;
when CMD_VIDEO_Y_POS =>
COMM_DI <= "000" & std_logic_vector(POS_Y);
STATE <= ST_IDLE;
when CMD_VIDEO_CHAR =>
VA <= std_logic_vector(POS_Y) & std_logic_vector(POS_X);
STATE <= ST_READ_VRAM_D;
when CMD_RAM_MODE =>
COMM_DI <= RAM_RG;
STATE <= ST_IDLE;
when CMD_RAM_DATA =>
RAM_A <= COMM_MA;
RAM_RW <= '0';
RAM_REQ <= '1';
if RAM_RG(0) = '0' then
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
else
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 2);
end if;
STATE <= ST_READ;
when CMD_KEYBOARD =>
COMM_DI <= KB_DATA;
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
when ST_WRITE_DATA =>
case ('0' & COMM_RG(6 downto 0)) is
when CMD_VIDEO_MODE =>
VRG <= COMM_DO;
STATE <= ST_IDLE;
when CMD_VIDEO_ATTR =>
VATTR <= COMM_DO;
if VRG(2) = '1' then
STATE <= ST_INC;
else
STATE <= ST_IDLE;
end if;
when CMD_VIDEO_X_POS =>
POS_X <= unsigned(COMM_DO(6 downto 0));
STATE <= ST_IDLE;
when CMD_VIDEO_Y_POS =>
POS_Y <= unsigned(COMM_DO(4 downto 0));
STATE <= ST_IDLE;
when CMD_VIDEO_CHAR =>
VDI <= COMM_DO;
VWR <= '1';
VA <= std_logic_vector(POS_Y) & std_logic_vector(POS_X);
if VRG(0) = '1' then
STATE <= ST_INC;
else
STATE <= ST_IDLE;
end if;
when CMD_RAM_MODE =>
RAM_RG <= COMM_DO;
STATE <= ST_IDLE;
when CMD_RAM_H_ADDR =>
COMM_MA(19 downto 16) <= COMM_DO(3 downto 0);
STATE <= ST_IDLE;
when CMD_RAM_M_ADDR =>
COMM_MA(15 downto 8) <= COMM_DO;
STATE <= ST_IDLE;
when CMD_RAM_L_ADDR =>
COMM_MA(7 downto 0 ) <= COMM_DO;
STATE <= ST_IDLE;
when CMD_RAM_DATA =>
RAM_A <= COMM_MA;
RAM_DI <= COMM_DO;
RAM_RW <= '1';
RAM_REQ <= '1';
if RAM_RG(0) = '0' then
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
else
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 2);
end if;
STATE <= ST_WRITE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
when ST_READ_VRAM_A =>
COMM_DI <= VDO(15 downto 8);
if VRG(3) = '1' then
STATE <= ST_INC;
else
STATE <= ST_IDLE;
end if;
when ST_READ_VRAM_D =>
COMM_DI <= VDO(7 downto 0);
if VRG(1) = '1' then
STATE <= ST_INC;
else
STATE <= ST_IDLE;
end if;
when ST_WRITE =>
if RAM_ACK = '1' then
STATE <= ST_IDLE;
end if;
when ST_READ =>
if RAM_ACK = '1' then
COMM_DI <= RAM_DO;
STATE <= ST_IDLE;
end if;
when ST_INC =>
POS_X <= POS_X + 1;
if POS_X = 79 then
POS_X <= "0000000";
POS_Y <= POS_Y + 1;
if POS_Y = 29 then
POS_Y <= "00000";
end if;
end if;
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 074aac5c57b9ccfcb49d007464d3a47d | 0.371071 | 4.120412 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/Block_sin_taylor_ser.vhd | 4 | 7,114 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
| mit | 91e243a908e97aef5f1632dc14f22dcd | 0.545825 | 3.28288 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06200_good.vhd | 1 | 2,894 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06200_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Management of numeric values: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_06200_good is
port (
i_D1 : in std_logic;
i_D2 : in std_logic;
i_D3 : in std_logic;
i_D4 : in std_logic;
i_Sel : in std_logic_vector(1 downto 0);
o_Q : out std_logic
);
end STD_06200_good;
architecture Behavioral of STD_06200_good is
constant c_Sel_D1 : std_logic_vector(1 downto 0) := "00";
constant c_Sel_D2 : std_logic_vector(1 downto 0) := "01";
constant c_Sel_D3 : std_logic_vector(1 downto 0) := "10";
constant c_Sel_D4 : std_logic_vector(1 downto 0) := "11";
begin
o_Q <= i_D1 when i_Sel = c_Sel_D1
else i_D2 when i_Sel = c_Sel_D2
else i_D3 when i_Sel = c_Sel_D3
else i_D4;
end Behavioral;
--CODE
| gpl-3.0 | 4b8da4ea95e7e6cd7847d033a3c1ddd1 | 0.489288 | 4.170029 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/zpu_core.vhd | 1 | 50,374 | ------------------------------------------------------------------------------
---- ----
---- ZPU Medium ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the medium size version. ----
---- Supports external memories. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- write_en_o - set to '1' for a single cycle to send off a write request.
-- data_o is valid only while write_en_o='1'.
-- read_en_o - set to '1' for a single cycle to send off a read request.
-- mem_busy_i - It is illegal to send off a read/write request when
-- mem_busy_i='1'.
-- Set to '0' when data_i is valid after a read request.
-- If it goes to '1'(busy), it is on the cycle after read/
-- write_en_o is '1'.
-- addr_o - address for read/write request
-- data_i - read data. Valid only on the cycle after mem_busy_i='0'
-- after read_en_o='1' for a single cycle.
-- data_o - data to write
-- break_o - set to '1' when CPU hits break instruction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable (32-bit)
read_en_o : out std_logic; -- Memory read enable (32-bit)
byte_read_o : out std_logic;
byte_write_o : out std_logic;
short_write_o: out std_logic); -- never happens
end entity ZPUMediumCore;
architecture Behave of ZPUMediumCore is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W;
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):=
SP_START_1(ADDR_W-1 downto BYTE_BITS);
-- Update [SP+1]. We hold it in b_r, this writes the value to memory.
procedure FlushB(signal we : out std_logic;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS);
signal data : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
we <= '1';
addr <= inc_sp;
data <= b;
end procedure FlushB;
-- Do a simple stack push, it is performed in the internal cache registers,
-- not in the real memory.
procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : in unsigned(WORD_SIZE-1 downto 0);
signal b : out unsigned(WORD_SIZE-1 downto 0)) is
begin
b <= a; -- Update cache [SP+1]=[SP]
sp <= sp-1;
end procedure Push;
-- Do a simple stack pop, it is performed in the internal cache registers,
-- not in the real memory.
procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
a <= b; -- Update cache [SP]=[SP+1]
sp <= sp+1;
end procedure Pop;
-- Expand a PC value to WORD_SIZE
function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
variable nv : unsigned(WORD_SIZE-1 downto 0);
begin
nv:=(others => '0');
nv(ADDR_W-1 downto 0):=v;
return nv;
end function ExpandPC;
-- Program counter
signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
-- SP+1, SP+2 and SP-1 are very used, these are shortcuts
signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
-- a_r is a cache for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_r : unsigned(WORD_SIZE-1 downto 0);
-- b_r is a cache for the next value in the stack [SP+1]
signal b_r : unsigned(WORD_SIZE-1 downto 0);
signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal idim_r : std_logic;
signal write_en_r : std_logic;
signal byte_read_r : std_logic;
signal byte_write_r : std_logic;
signal short_write_r : std_logic;
signal read_en_r : std_logic;
signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
signal addrl_r : unsigned(BYTE_BITS-1 downto 0):=(others => '0');
signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0);
type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
st_fetch, st_execute, st_decode, st_decode2, st_resync,
st_store_sp2, st_resync2, st_resync3, st_loadb2,
st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
st_binary_op_res, st_idle);
signal state : state_t:=st_resync;
-- Go to st_fetch state or just do its work
procedure DoFetch(constant FAST : boolean;
signal state : out state_t;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal pc : in unsigned(ADDR_W-1 downto 0);
signal re : out std_logic;
signal busy : in std_logic) is
begin
if FAST then
-- Equivalent to st_fetch
if busy='0' then
addr <= pc(ADDR_W-1 downto BYTE_BITS);
re <= '1';
state <= st_decode;
end if;
else
state <= st_fetch;
end if;
end procedure DoFetch;
-- Perform a "binary operation" (2 operands)
procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0);
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
begin
if DEPTH=2 then
-- 2 clocks: st_binary_op_res+st_binary_op_res2
state <= st_binary_op_res;
dest_p <= result;
elsif DEPTH=1 then
-- 1 clock: st_binary_op_res2
state <= st_binary_op_res2;
dest_p <= result;
else -- 0 clocks
re <= '1';
addr <= sp+2;
sp <= sp+1;
dest <= result;
state <= st_popped;
end if;
end procedure DoBinOp;
-- Perform a boolean "binary operation" (2 operands)
procedure DoBinOpBool(result : in boolean;
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
begin
if result then
res(0):='1';
end if;
DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
end procedure DoBinOpBool;
type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
dec_less_than, dec_less_than_or_equal, dec_lshr,
dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
dec_insn_fetch, dec_pop_down);
signal insn : insn_t;
type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
signal insns : insn_array_t;
type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
signal opcode_r : opcode_array_t;
begin
-- the memory subsystem will tell us one cycle later whether or
-- not it is busy
write_en_o <= write_en_r;
read_en_o <= read_en_r;
byte_read_o <= byte_read_r;
byte_write_o <= byte_write_r;
short_write_o <= short_write_r;
addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
addr_o(BYTE_BITS-1 downto 0) <= addrl_r;
-- SP+1 and +2
inc_sp <= sp_r+1;
inc_inc_sp <= sp_r+2;
opcode_control:
process (clk_i)
variable topcode : unsigned(OPCODE_W-1 downto 0);
variable ex_opcode : unsigned(OPCODE_W-1 downto 0);
variable sp_offset : unsigned(4 downto 0);
variable tsp_offset : unsigned(4 downto 0);
variable next_pc : unsigned(ADDR_W-1 downto 0);
variable tdecoded : insn_t;
variable tinsns : insn_array_t;
variable mult_res : unsigned(WORD_SIZE*2-1 downto 0);
variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r)
variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc)
variable not_lshr : std_logic:='1';
begin
if rising_edge(clk_i) then
break_o <= '0';
if reset_i='1' then
if ENA_IDLE then
state <= st_idle;
else
state <= st_resync;
end if;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
write_en_r <= '0';
byte_read_r <= '0';
byte_write_r <= '0';
short_write_r <= '0';
read_en_r <= '0';
mult_a_r <= (others => '0');
mult_b_r <= (others => '0');
dbg_o.b_inst <= '0';
-- Reseting add_r here makes XST fail to use BRAMs ?!
else -- reset_i='1'
if MULT_PIPE then
-- We must multiply unconditionally to get pipelined multiplication
mult_res:=mult_a_r*mult_b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
mult_res2_r <= mult_res1_r;
mult_res3_r <= mult_res2_r;
mult_a_r <= (others => D_CARE_VAL);
mult_b_r <= (others => D_CARE_VAL);
end if;
if BINOP_PIPE=2 then
bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
end if;
read_en_r <='0';
write_en_r <='0';
byte_read_r <= '0';
byte_write_r <= '0';
short_write_r <= '0';
-- Allow synthesis tools to load bogus values when we don't
-- care about the address and output data.
addr_r <= (others => D_CARE_VAL);
data_o <= (others => D_CARE_VAL);
addrl_r <= "00";
if (write_en_r='1') and (read_en_r='1') then
report "read/write collision" severity failure;
end if;
ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
sp_offset(4):=not opcode_r(ipc_low)(4);
sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
next_pc:=pc_r+1;
-- Prepare trace snapshot
dbg_o.opcode <= opcode_r(ipc_low);
dbg_o.pc <= resize(pc_r,32);
dbg_o.stk_a <= resize(a_r,32);
dbg_o.stk_b <= resize(b_r,32);
dbg_o.b_inst <= '0';
dbg_o.sp <= (others => '0');
dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
case state is
when st_idle =>
if enable_i='1' then
state <= st_resync;
end if;
-- Initial state of ZPU, fetch top of stack (A/B) + first instruction
when st_resync =>
if mem_busy_i='0' then
addr_r <= sp_r;
read_en_r <= '1';
state <= st_resync2;
end if;
when st_resync2 =>
if mem_busy_i='0' then
a_r <= data_i;
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_resync3;
end if;
when st_resync3 =>
if mem_busy_i='0' then
b_r <= data_i;
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
when st_decode =>
if mem_busy_i='0' then
-- Here we latch the fetched word to give one full clock
-- cycle to the instruction decoder. This could be removed
-- if using BRAMs and the decoder delay isn't important.
fetched_w_r <= data_i;
state <= st_decode2;
end if;
when st_decode2 =>
-- decode 4 instructions in parallel
for i in 0 to WORD_BYTES-1 loop
topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
tsp_offset(4):=not topcode(4);
tsp_offset(3 downto 0):=topcode(3 downto 0);
opcode_r(i) <= topcode;
if topcode(7 downto 7)=OPCODE_IM then
tdecoded:=dec_im;
elsif topcode(7 downto 5)=OPCODE_STORESP then
if tsp_offset=0 then
-- Special case, we can avoid a write
tdecoded:=dec_pop;
elsif tsp_offset=1 then
-- Special case, collision
tdecoded:=dec_pop_down;
else
tdecoded:=dec_store_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_LOADSP then
if tsp_offset=0 then
tdecoded:=dec_dup;
elsif tsp_offset=1 then
tdecoded:=dec_dup_stk_b;
else
tdecoded:=dec_load_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_EMULATE then
tdecoded:=dec_emulate;
if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
tdecoded:=dec_neq_branch;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
tdecoded:=dec_eq;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
tdecoded:=dec_loadb;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
tdecoded:=dec_push_sp_add;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
tdecoded:=dec_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
tdecoded:=dec_u_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
tdecoded:=dec_mult;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
tdecoded:=dec_storeb;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
tdecoded:=dec_call_pc_rel;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
tdecoded:=dec_sub;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
tdecoded:=dec_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
tdecoded:=dec_u_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
tdecoded:=dec_call;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
tdecoded:=dec_pop_pc_rel;
elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
tdecoded:=dec_lshr;
end if;
elsif topcode(7 downto 4)=OPCODE_ADDSP then
if tsp_offset=0 then
tdecoded:=dec_shift;
elsif tsp_offset=1 then
tdecoded:=dec_add_top;
else
tdecoded:=dec_add_sp;
end if;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
tdecoded:=dec_break;
when OPCODE_PUSHSP =>
tdecoded:=dec_push_sp;
when OPCODE_POPPC =>
tdecoded:=dec_pop_pc;
when OPCODE_ADD =>
tdecoded:=dec_add;
when OPCODE_OR =>
tdecoded:=dec_or;
when OPCODE_AND =>
tdecoded:=dec_and;
when OPCODE_LOAD =>
tdecoded:=dec_load;
when OPCODE_NOT =>
tdecoded:=dec_not;
when OPCODE_FLIP =>
tdecoded:=dec_flip;
when OPCODE_STORE =>
tdecoded:=dec_store;
when OPCODE_POPSP =>
tdecoded:=dec_pop_sp;
when others => -- OPCODE_NOP and others
tdecoded:=dec_nop;
end case;
end if;
tinsns(i):=tdecoded;
end loop;
insn <= tinsns(ipc_low);
-- once we wrap, we need to fetch
tinsns(0):=dec_insn_fetch;
insns <= tinsns;
state <= st_execute;
-- Each instruction must:
--
-- 1. increase pc_r if applicable
-- 2. set next state if applicable
-- 3. do it's operation
when st_execute =>
-- Some shortcut to make the code readable:
inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
ex_opcode:=opcode_r(ipc_low);
if (mem_busy_i = '0') then -- MWW, do not move on until mem is not busy!
insn <= insns(inpc_low);
-- Defaults used by most instructions
if insn/=dec_insn_fetch and insn/=dec_im then
dbg_o.b_inst <= '1';
idim_r <= '0';
end if;
case insn is
when dec_insn_fetch =>
-- Not a real instruction, fetch new instructions
DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
when dec_im =>
-- Push(immediate value), IDIM=1
-- if IDIM=0 Push(signed(opcode & 0x7F)) else
-- Push((Pop()<<7)|(opcode&0x7F))
if mem_busy_i='0' then
dbg_o.b_inst <= '1';
idim_r <= '1';
pc_r <= pc_r+1;
if idim_r='1' then
-- We already started an IM sequence
-- Shift left 7 bits
a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
-- Put the new value
a_r(6 downto 0) <= ex_opcode(6 downto 0);
else
-- First IM, push the value sign extended
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
Push(sp_r,a_r,b_r);
end if;
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
if mem_busy_i='0' then
write_en_r <= '1';
addr_r <= sp_r+sp_offset;
data_o <= a_r;
Pop(sp_r,a_r,b_r);
-- We need to fetch B
state <= st_store_sp2;
end if;
when dec_load_sp =>
-- Push([SP+Offset])
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
Push(sp_r,a_r,b_r);
-- We are flushing B cache, so we need more time to
-- read the value.
state <= st_load_sp2;
end if;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
Push(sp_r,a_r,b_r);
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= ex_opcode(4 downto 0);
end if;
when dec_call_pc_rel =>
-- t=Pop(), Push(PC+1), PC=PC+t
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= pc_r+a_r(ADDR_W-1 downto 0);
end if;
when dec_call =>
-- t=Pop(), Push(PC+1), PC=t
if mem_busy_i='0' and ENA_LEVEL2 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= a_r(ADDR_W-1 downto 0);
end if;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
if mem_busy_i='0' then
-- Read SP+Offset
state <= st_add_sp2;
read_en_r <= '1';
addr_r <= sp_r+sp_offset;
pc_r <= pc_r+1;
end if;
when dec_push_sp =>
-- Push(SP)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
Push(sp_r,a_r,b_r);
end if;
when dec_pop_pc =>
-- PC=Pop() (return)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0);
sp_r <= inc_sp;
end if;
when dec_pop_pc_rel =>
-- PC=PC+Pop()
if mem_busy_i='0' and ENA_LEVEL2 then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
sp_r <= inc_sp;
end if;
when dec_add =>
-- Push(Pop()+Pop()) [A=A+B, SP++, update B]
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r+b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_sub =>
-- a=Pop(), b=Pop(), Push(b-a)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_pop =>
-- Pop()
if mem_busy_i='0' then
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
Pop(sp_r,a_r,b_r);
end if;
when dec_pop_down =>
-- t=Pop(), Pop(), Push(t)
if mem_busy_i='0' then
-- PopDown leaves top of stack unchanged
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
sp_r <= inc_sp;
end if;
when dec_or =>
-- Push(Pop() or Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r or b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_and =>
-- Push(Pop() and Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r and b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_eq =>
-- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL0 then
DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than =>
-- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than_or_equal =>
-- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_less_than =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_less_than_or_equal =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_load =>
-- Push([Pop()])
if mem_busy_i='0' then
state <= st_load2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_dup =>
-- t=Pop(), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
-- A is dupped, no change
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_dup_stk_b =>
-- Pop(), t=Pop(), Push(t), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
a_r <= b_r;
-- B goes to A
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
if mem_busy_i='0' then
state <= st_resync;
pc_r <= pc_r+1;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= b_r;
write_en_r <= '1';
sp_r <= inc_inc_sp;
end if;
when dec_pop_sp =>
-- SP=Pop()
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= pc_r+1;
sp_r <= a_r(ADDR_W-1 downto BYTE_BITS);
end if;
when dec_nop =>
pc_r <= pc_r+1;
when dec_not =>
-- Push(not(Pop()))
pc_r <= pc_r+1;
a_r <= not a_r;
when dec_flip =>
-- Push(flip(Pop()))
pc_r <= pc_r+1;
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_r(WORD_SIZE-1-i);
end loop;
when dec_add_top =>
-- a=Pop(), b=Pop(), Push(b), Push(a+b)
pc_r <= pc_r+1;
a_r <= a_r+b_r;
when dec_shift =>
-- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
pc_r <= pc_r+1;
a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
a_r(0) <= '0';
when dec_push_sp_add =>
-- Push(Pop()+SP)
if ENA_LEVEL0 then
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <=
a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
end if;
when dec_neq_branch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
if ENA_LEVEL0 then
sp_r <= inc_inc_sp;
-- Need to fetch stack again.
state <= st_resync;
if b_r/=0 then
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
else
pc_r <= pc_r+1;
end if;
end if;
when dec_mult =>
-- Push(Pop()*Pop())
if ENA_LEVEL1 then
if MULT_PIPE then
mult_a_r <= a_r;
mult_b_r <= b_r;
state <= st_mult2;
else
mult_res:=a_r*b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
state <= st_mult5;
end if;
end if;
when dec_break =>
-- Assert the break_o signal
--report "Break instruction encountered" severity failure;
break_o <= '1';
pc_r <= pc_r+1;
when dec_loadb =>
-- Push([Pop()] & 0xFF) (byte address)
if mem_busy_i='0' and ENA_LEVEL0 then
state <= st_loadb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
addrl_r <= a_r(BYTE_BITS-1 downto 0);
--read_en_r <= '1';
byte_read_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_storeb =>
-- [Pop()]=Pop() & 0xFF (byte address)
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_resync;
sp_r <= inc_inc_sp;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
addrl_r <= a_r(BYTE_BITS-1 downto 0);
--write_en_r <= '1';
byte_write_r <= '1';
pc_r <= pc_r+1;
--data_o(WORD_SIZE-1 downto 8) <= (others=>'0');
--data_o(7 downto 0) <= b_r(7 downto 0);
data_o(WORD_SIZE-1 downto 0) <= b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0);
end if;
when dec_lshr =>
-- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
if ENA_LSHR then
-- This instruction takes more than one cycle.
-- We must avoid duplications in the trace log.
dbg_o.b_inst <= not_lshr;
not_lshr:='0';
if a_r(5 downto 0)=0 then -- Only 6 bits used
-- No more shifts
if mem_busy_i='0' then
state <= st_popped;
a_r <= b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
not_lshr:='1';
end if;
else -- More shifts needed
b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
a_r(5 downto 0) <= a_r(5 downto 0)-1;
insn <= insn;
end if;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal decode instruction?!" severity failure;
--break_o <= '1';
end case;
end if;
-- The followup of operations that takes more than one execution clock
when st_store_sp2 =>
if mem_busy_i='0' then
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_popped;
end if;
when st_load_sp2 =>
if mem_busy_i='0' then
state <= st_load_sp3;
-- Now we can read SP+Offset (SP already decremented)
read_en_r <= '1';
addr_r <= sp_r+sp_offset+1;
end if;
when st_load_sp3 =>
if mem_busy_i='0' then
-- Note: We can't increment PC in the decode stage
-- because it will modify sp_offset.
pc_r <= pc_r+1;
-- Finally we have the result in A
state <= st_execute;
a_r <= data_i;
end if;
when st_add_sp2 =>
if mem_busy_i='0' then
state <= st_execute;
a_r <= a_r+data_i;
end if;
when st_load2 =>
if mem_busy_i='0' then
a_r <= data_i;
state <= st_execute;
end if;
when st_loadb2 =>
if mem_busy_i='0' then
a_r(WORD_SIZE-1 downto 8) <= (others => '0');
a_r(7 downto 0) <= data_i(7 downto 0);
state <= st_execute;
end if;
when st_fetch =>
if mem_busy_i='0' then
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
-- The following states can be used to leave cycles free for
-- tools that can automagically decompose the multiplication
-- in various stages. Xilinx tools can do it to increase the
-- multipliers performance.
when st_mult2 =>
state <= st_mult3;
when st_mult3 =>
state <= st_mult4;
when st_mult4 =>
state <= st_mult5;
when st_mult5 =>
if mem_busy_i='0' then
if MULT_PIPE then
a_r <= mult_res3_r;
else
a_r <= mult_res1_r;
end if;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
end if;
when st_binary_op_res =>
-- BINOP_PIPE=2
state <= st_binary_op_res2;
when st_binary_op_res2 =>
-- BINOP_PIPE>=1
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
if BINOP_PIPE=2 then
a_r <= bin_op_res2_r;
else -- 1
a_r <= bin_op_res1_r;
end if;
when st_popped =>
if mem_busy_i='0' then
-- Note: Moving this PC++ to the decoder seems to
-- consume more LUTs.
pc_r <= pc_r+1;
b_r <= data_i;
state <= st_execute;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal state?!" severity failure;
--break_o <= '1';
end case; -- state
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: ZPUMediumCore
| gpl-3.0 | e083c20d574d6c8d29a289b0e564c10c | 0.356594 | 4.546529 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/keyboard/keyboard.vhd | 1 | 12,741 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CONTROL : out std_logic_vector(7 downto 0);
KEYB_A : in std_logic_vector(7 downto 0);
KEYB_A2 : in std_logic_vector(3 downto 0);
KEYB_D : out std_logic_vector(7 downto 0);
KEYB_D2 : out std_logic_vector(3 downto 0);
VGA_SEL : in std_logic; -- 0 = Lvov, 1= MIPS
KEYB_DATA : out std_logic_vector(7 downto 0) -- MIPS
);
end keyboard;
architecture Behavioral of keyboard is
signal CODE : std_logic_vector(7 downto 0);
signal DONE : std_logic;
signal ERROR : std_logic;
signal KEY_REL : std_logic;
signal KEY_EXT : std_logic;
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix : Matrix_Image(0 to 7);
type Matrix2_Image is array (natural range <>) of std_logic_vector(3 downto 0);
signal Matrix2 : Matrix2_Image(0 to 3);
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => not RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
DECODER : process(CLK)
variable KEY : std_logic_vector(10 downto 0);
variable KEY2 : std_logic_vector(5 downto 0);
begin
if rising_edge(CLK) then
if RESET = '0' then
Matrix <= (others => (others => '0'));
KEY_REL <= '0';
KEY_EXT <= '0';
CONTROL <= "00000000";
else
CONTROL <= "00000000";
if VGA_SEL = '0' then
-- Lvov
if DONE = '1' then -- ScanCode Readed
if CODE = X"F0" then -- Key Released
KEY_REL <= '1';
elsif CODE = X"E0" then -- Extended Key
KEY_EXT <= '1';
else
KEY := (others => '0');
KEY2 := (others => '0');
case CODE is -- PS2 Set 2 Scancodes
when x"1C" => KEY := "11000010000"; -- A
when x"32" => KEY := "01100000010"; -- B
when x"21" => KEY := "10110000000"; -- C
when x"23" => KEY := "01010000000"; -- D
when x"24" => KEY := "10100010000"; -- E
when x"2B" => KEY := "11010000000"; -- F
when x"34" => KEY := "00100000001"; -- G
when x"33" => KEY := "00101000000"; -- H
when x"43" => KEY := "11100100000"; -- I
when x"3B" => KEY := "10100000100"; -- J
when x"42" => KEY := "10100100000"; -- K
when x"4B" => KEY := "01000000100"; -- L
when x"3A" => KEY := "11101000000"; -- M
when x"31" => KEY := "10100001000"; -- N
when x"44" => KEY := "01000000010"; -- O
when x"4D" => KEY := "11000001000"; -- P
when x"15" => KEY := "11100000010"; -- Q
when x"2D" => KEY := "01000000001"; -- R
when x"1B" => KEY := "11110000000"; -- S
when x"2C" => KEY := "11100010000"; -- T
when x"3C" => KEY := "10101000000"; -- U
when x"2A" => KEY := "01001000000"; -- V
when x"1D" => KEY := "11000100000"; -- W
when x"22" => KEY := "11100001000"; -- X
when x"35" => KEY := "11001000000"; -- Y
when x"1A" => KEY := "00110000000"; -- Z
when x"16" => KEY := "10010000000"; -- 1
when x"1E" => KEY := "10001000000"; -- 2
when x"26" => KEY := "10000100000"; -- 3
when x"25" => KEY := "10000010000"; -- 4
when x"2E" => KEY := "10000001000"; -- 5
when x"36" => KEY := "00000000001"; -- 6
when x"3D" => KEY := "00000000010"; -- 7
when x"3E" => KEY := "00000000100"; -- 8
when x"46" => KEY := "00010000000"; -- 9
when x"45" => KEY := "00001000000"; -- 0
when x"29" => KEY := "01100000001"; -- SPACE
when x"66" => KEY := "01000001000"; -- PACKSPACE | ZB
when x"5A" => KEY := "00100001000"; -- ENTER | WK
when x"58" => KEY := "11000000100"; -- CAPS LOCK | SU
when x"12" =>
if KEY_EXT = '1' then -- Print Screen
if KEY_REL = '0' then -- Lvov Reset
CONTROL(0) <= '1';
end if;
else
KEY := "11100000001"; -- LEFT SHIFT | NR
end if;
when x"59" => KEY := "01100001000"; -- RIGHT SHIFT | WR
when x"0D" => KEY := "00000010000"; -- TAB
when x"41" => KEY := "01110000000"; -- ,
when x"49" => KEY := "01000010000"; -- .
when x"4E" => KEY := "00000100000"; -- -
when x"5D" => KEY := "01000100000"; -- \
when x"55" => KEY := "11100000100"; -- = | ^
when x"0E" => KEY := "00100100000"; -- ' | :
when x"54" => KEY := "00100000010"; -- [
-- when x"76" => KEY := "10000000001"; -- | STR
-- when x"76" => KEY := "10000000001"; -- | @]
when x"5B" => KEY := "00100000100"; -- ]
when x"1f" =>
if KEY_EXT = '1' then -- Left Win
if KEY_REL = '0' then
CONTROL(2) <= '1'; -- Switch to Host Console
end if;
end if;
when x"27" =>
if KEY_EXT = '1' then -- Right Win
if KEY_REL = '0' then
CONTROL(3) <= '1'; -- Switch to Lvov Screen
end if;
end if;
when x"4C" => KEY := "11000000001"; -- ;
when x"4A" => KEY := "01101000000"; -- /
when x"0B" => KEY := "10000000010"; -- F6 | [G]
when x"83" => KEY := "10000000100"; -- F7 | [B]
when x"11" =>
if KEY_EXT = '1' then
KEY := "00100010000"; -- RIGHT ALT | PS
else
KEY := "00000001000"; -- LEFT ALT | GT
end if;
when x"14" =>
if KEY_EXT = '1' then
KEY := "01100100000"; -- RIGHT CTRL | LAT
else
KEY := "11000000010"; -- LEFT CTRL | RUS
end if;
when x"76" => KEY2 := "010010"; -- ESC | F0
when x"05" => KEY2 := "010100"; -- F1
when x"06" => KEY2 := "011000"; -- F2
when x"04" => KEY2 := "101000"; -- F3
when x"0C" => KEY2 := "100100"; -- F4
when x"03" => KEY2 := "100010"; -- F5
when x"0A" => KEY2 := "001000"; -- F8 | [R]
when x"01" => KEY2 := "000100"; -- F9 | DIN
when x"09" => KEY2 := "000010"; -- F10 | CD
when x"78" => KEY2 := "000001"; -- F11 | P4
when x"07" => KEY2 := "010001"; -- F12 | P/D
when x"74" =>
if KEY_EXT = '1' then
KEY2 := "110001"; -- RIGHT
end if;
when x"75" =>
if KEY_EXT = '1' then
KEY2 := "110010"; -- UP
end if;
when x"6B" =>
if KEY_EXT = '1' then
KEY2 := "110100"; -- LEFT
end if;
when x"72" =>
if KEY_EXT = '1' then
KEY2 := "111000"; -- DOWN
end if;
when x"71" =>
if KEY_EXT = '1' then
KEY2 := "100001"; -- DEL | DIA
end if;
when x"7e" => -- ScrollLock
if KEY_REL = '0' then -- Reset to Standard Lvov ROM
CONTROL(0) <= '1';
end if;
when OTHERS => NULL;
end case;
if KEY_REL = '0' then
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) or
std_logic_vector(unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) or
std_logic_vector(unsigned(KEY2(3 downto 0)));
else
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) and
std_logic_vector(not unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) and
std_logic_vector(not unsigned(KEY2(3 downto 0)));
end if;
KEY_REL <= '0';
KEY_EXT <= '0';
end if;
end if;
else
-- MIPS
if DONE = '1' then
if CODE = X"e0" then
-- Extended key code follows
KEY_EXT <= '1';
elsif CODE = X"f0" then
-- Release code follows
KEY_REL <= '1';
else
if KEY_EXT = '1' then
case CODE is
when X"00" => -- X"12"
if KEY_REL = '0' then
CONTROL(1) <= '1'; -- MIPS Reset
end if;
when X"27" => -- Escape For auto switch from File Manager to Console
if KEY_REL = '1' then
CONTROL(3) <= '1'; -- Switch to Lvov screen in left Win release
end if;
when others => null;
end case;
end if;
-- Cancel extended/release flags for next time
if KEY_REL = '1' then
KEYB_DATA <= x"00";
KEY_REL <= '0';
KEY_EXT <= '0';
else
KEYB_DATA <= CODE;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
-- Lvov
KEYB_D <= "11111111" and
( not Matrix(0) or (7 downto 0 => KEYB_A(0)) ) and
( not Matrix(1) or (7 downto 0 => KEYB_A(1)) ) and
( not Matrix(2) or (7 downto 0 => KEYB_A(2)) ) and
( not Matrix(3) or (7 downto 0 => KEYB_A(3)) ) and
( not Matrix(4) or (7 downto 0 => KEYB_A(4)) ) and
( not Matrix(5) or (7 downto 0 => KEYB_A(5)) ) and
( not Matrix(6) or (7 downto 0 => KEYB_A(6)) ) and
( not Matrix(7) or (7 downto 0 => KEYB_A(7)) );
KEYB_D2<= "1111" and
( not Matrix2(0) or (3 downto 0 => KEYB_A2(0)) ) and
( not Matrix2(1) or (3 downto 0 => KEYB_A2(1)) ) and
( not Matrix2(2) or (3 downto 0 => KEYB_A2(2)) ) and
( not Matrix2(3) or (3 downto 0 => KEYB_A2(3)) );
end Behavioral;
| gpl-3.0 | 16ea027553f441d2d8e5b029fa365f14 | 0.363472 | 4.071908 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/covox.vhd | 1 | 2,829 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY covox IS
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
covox_channel0 : out std_logic_vector(7 downto 0);
covox_channel1 : out std_logic_vector(7 downto 0);
covox_channel2 : out std_logic_vector(7 downto 0);
covox_channel3 : out std_logic_vector(7 downto 0)
);
END covox;
ARCHITECTURE vhdl OF covox IS
component complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
signal channel0_next : std_logic_vector(7 downto 0);
signal channel1_next : std_logic_vector(7 downto 0);
signal channel2_next : std_logic_vector(7 downto 0);
signal channel3_next : std_logic_vector(7 downto 0);
signal channel0_reg : std_logic_vector(7 downto 0);
signal channel1_reg : std_logic_vector(7 downto 0);
signal channel2_reg : std_logic_vector(7 downto 0);
signal channel3_reg : std_logic_vector(7 downto 0);
signal addr_decoded : std_logic_vector(3 downto 0);
BEGIN
complete_address_decoder1 : complete_address_decoder
generic map (width => 2)
port map (addr_in => addr, addr_decoded => addr_decoded);
-- next state logic
process(channel0_reg,channel1_reg,channel2_reg,channel3_reg,addr_decoded,data_in,WR_EN)
begin
channel0_next <= channel0_reg;
channel1_next <= channel1_reg;
channel2_next <= channel2_reg;
channel3_next <= channel3_reg;
if (WR_EN = '1') then
if (addr_decoded(0) = '1') then
channel0_next <= data_in;
end if;
if (addr_decoded(1) = '1') then
channel1_next <= data_in;
end if;
if (addr_decoded(2) = '1') then
channel2_next <= data_in;
end if;
if (addr_decoded(3) = '1') then
channel3_next <= data_in;
end if;
end if;
end process;
-- register
process(clk)
begin
if (clk'event and clk='1') then
channel0_reg <= channel0_next;
channel1_reg <= channel1_next;
channel2_reg <= channel2_next;
channel3_reg <= channel3_next;
end if;
end process;
-- output
covox_channel0 <= channel0_reg;
covox_channel1 <= channel1_reg;
covox_channel2 <= channel2_reg;
covox_channel3 <= channel3_reg;
END vhdl; | gpl-3.0 | 8492fed1727f425b8ee993b450e544fb | 0.625309 | 3.08506 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05600_bad.vhd | 1 | 2,946 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05600_bad.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of combinational feedbacks: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity STD_05600_bad is
port (
i_A : in std_logic; -- First Mux input
i_B : in std_logic; -- Second Mux input
i_Sel : in std_logic; -- Mux select
o_O : out std_logic -- Mux output
);
end STD_05600_bad;
architecture Behavioral of STD_05600_bad is
signal Mux_Sel : std_logic; -- Combinational select
signal O : std_logic; -- Module output
begin
Mux_Sel <= i_Sel and O;
-- Combinational Mux selecting A or B depending on Mux_Sel value
Mux1 : Mux
port map (
i_A => i_A,
i_B => i_B,
i_S => Mux_Sel,
o_O => O
);
o_O <= O;
end Behavioral;
--CODE
| gpl-3.0 | 0c2ba6e3ab526353b81445a82ae9c24d | 0.475221 | 4.560372 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/cpu.vhd | 1 | 3,885 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
ENTITY cpu IS
PORT
(
CLK,RESET,ENABLE : IN STD_logic;
DI : IN std_logic_vector(7 downto 0);
IRQ_n : in std_logic;
NMI_n : in std_logic;
MEMORY_READY : in std_logic;
THROTTLE : in std_logic;
RDY : in std_logic;
DO : OUT std_logic_vector(7 downto 0);
A : OUT std_logic_vector(15 downto 0);
R_W_n : OUT std_logic;
CPU_FETCH : out std_logic
);
END cpu;
architecture vhdl of cpu is
component cpu_65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
halt : in std_logic := '0';
reset : in std_logic;
nmi_n : in std_logic := '1';
irq_n : in std_logic := '1';
so_n : in std_logic := '1';
d : in unsigned(7 downto 0);
q : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0);
debug_flags : out unsigned(7 downto 0)
);
end component;
signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
-- Support for Peter's core (NMI patch applied)
signal debugOpcode : unsigned(7 downto 0);
signal debugPc : unsigned(15 downto 0);
signal debugA : unsigned(7 downto 0);
signal debugX : unsigned(7 downto 0);
signal debugY : unsigned(7 downto 0);
signal debugS : unsigned(7 downto 0);
signal di_unsigned : unsigned(7 downto 0);
signal do_unsigned : unsigned(7 downto 0);
signal addr_unsigned : unsigned(15 downto 0);
signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
signal WE : std_logic;
signal nmi_pending_next : std_logic; -- NMI during RDY
signal nmi_pending_reg : std_logic;
signal nmi_n_adjusted : std_logic;
signal nmi_n_reg : std_logic;
signal nmi_edge : std_logic;
signal CPU_ENABLE_RESET : std_logic;
signal not_rdy : std_logic;
BEGIN
CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
-- CPU designed by Peter W - as used in Chameleon
di_unsigned <= unsigned(di);
cpu_6502_peter:cpu_65xx
generic map
(
pipelineOpcode => false,
pipelineAluMux => false,
pipelineAluOut => false
)
port map (
clk => clk,
enable => CPU_ENABLE_RDY,
halt => '0',
reset=>reset,
nmi_n=>nmi_n_adjusted,
irq_n=>irq_n,
d=>di_unsigned,
q=>do_unsigned,
addr=>addr_unsigned,
WE=>WE,
debugOpcode => debugOpcode,
debugPc => debugPc,
debugA => debugA,
debugX => debugX,
debugY => debugY,
debugS => debugS
);
CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
CPU_ENABLE_RESET <= CPU_ENABLE or reset;
not_rdy <= not(rdy);
nmi_edge <= not(nmi_n) and nmi_n_reg;
nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
-- register
process(clk,reset)
begin
if (RESET = '1') then
nmi_pending_reg <= '0';
nmi_n_reg <= '1';
elsif (clk'event and clk='1') then
nmi_pending_reg <= nmi_pending_next;
nmi_n_reg <= nmi_n;
end if;
end process;
-- outputs
r_w_n <= not(we);
do <= std_logic_vector(do_unsigned);
a <= std_logic_vector(addr_unsigned);
CPU_FETCH <= ENABLE and THROTTLE;
END vhdl;
| gpl-3.0 | 15f4d765f081674d68b7999dd9defa7e | 0.635006 | 3 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_01600_good.vhd | 1 | 3,928 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01600_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Entity port sort: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity STD_01600_good is
-- We sort port by interfaces, with special ports first
port (
-- Special signals:
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
-- First Mux:
i_A1 : in std_logic; -- first input
i_B1 : in std_logic; -- second input
i_Sel1 : in std_logic; -- select input
o_Q1 : out std_logic; -- Mux output
-- Second Mux:
i_A2 : in std_logic; -- first input
i_B2 : in std_logic; -- second input
i_Sel2 : in std_logic; -- select input
o_Q2 : out std_logic -- Mux output
);
end STD_01600_good;
--CODE
architecture Behavioral of STD_01600_good is
signal Q1 : std_logic; -- First module output
signal Q2 : std_logic; -- Second module output
signal OutMux1 : std_logic; -- First Mux output
signal OutMux2 : std_logic; -- Second Mux output
begin
-- First Mux, output to be synced
Mux1 : Mux
port map (
i_A => i_A1,
i_B => i_B1,
i_S => i_Sel1,
o_O => OutMux1
);
-- Second Mux, output to be synced
Mux2 : Mux
port map (
i_A => i_A2,
i_B => i_B2,
i_S => i_Sel2,
o_O => OutMux2
);
-- Synchronizes the Mux outputs
P_SyncMux : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Q1 <= '0';
Q2 <= '0';
elsif (rising_edge(i_Clock)) then
Q1 <= OutMux1;
Q2 <= OutMux2;
end if;
end process;
o_Q1 <= Q1;
o_Q2 <= Q2;
end Behavioral;
| gpl-3.0 | 3ea087b692b829b4936fcd924096bc2b | 0.471232 | 4.169851 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_07300_good.vhd | 1 | 3,782 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_07300_good.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of wait statement in testbenches: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_07300_good is
end STD_07300_good;
architecture Simulation of STD_07300_good is
-- All signals for tested modules inputs/outputs
signal Clock : std_logic := '0';
signal Reset_n : std_logic;
signal D_Signal : std_logic;
signal Q_Signal : std_logic;
-- Used to stop simulation when no more stimulus are present
signal End_Sim : std_logic;
component DFlipFlop
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end component;
begin
-- The D Flip-Flop to test
T_DFlipFlop : DFlipFlop
port map (
i_Clock => Clock,
i_Reset_n => Reset_n,
i_D => D_Signal,
o_Q => Q_Signal,
o_Q_n => open
);
-- Clock process
P_Clock : process
begin
while (End_Sim /= '1') loop
Clock <= not Clock after 5 ns;
end loop;
wait;
end process;
--CODE
-- Test process
P_Test : process
begin
Reset_n <= '0';
D_Signal <= '0';
wait until rising_edge(Clock);
Reset_n <= '1';
wait until rising_edge(Clock);
D_Signal <= '1';
wait until rising_edge(Clock);
D_Signal <= '0';
End_Sim <= '1';
wait;
-- Or if your simulator supports VHDL-2008:
-- finish(2);
end process;
--CODE
end Simulation;
| gpl-3.0 | 08b9f48ee92a9db614c5a786bf32e0f6 | 0.494976 | 4.362168 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03900_bad.vhd | 1 | 4,830 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization trough reset for Raz, enable and Count_Length
-------------------------------------------------------------------------------------------------
-- File name : STD_03900_bad.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: State machine type definition: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03900_bad is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counters signal
i_Stop : in std_logic -- Stop counters signal
);
end STD_03900_bad;
--CODE
architecture Behavioral of STD_03900_bad is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
signal sm_State : std_logic_vector(3 downto 0); -- State signal
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter : Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
sm_State <= "0001";
Raz <= '0';
Enable <= '0';
Count_Length <= (others=>'0');
elsif (rising_edge(i_Clock)) then
case sm_State is
when "0001" =>
-- Set the length value
Length <= c_Length;
sm_State <= "0010";
when "0010" =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= "0100";
when "0100" =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count = '0') then
-- The counter has not finished, wait
Enable <= i_Start xor not i_Stop;
sm_State <= "0100";
else
-- The counter has finished, nothing else to do
Enable <= '0';
sm_State <= "1000";
end if;
when others =>
sm_State <= "0001";
end case;
end if;
end process;
end Behavioral;
--CODE
| gpl-3.0 | c7480aeb681430e3e3d56aa3c968dd8a | 0.480538 | 4.560907 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dsub_3_full_dsp_64/synth/sin_taylor_series_ap_dsub_3_full_dsp_64.vhd | 4 | 12,855 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
| mit | 327ea7630f280e849550c7e59d9da4ee | 0.651575 | 3.005611 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/clock/clock.vhd | 1 | 6,351 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____32.500______0.000______50.0______280.255____257.452
-- CLK_OUT2____25.000______0.000______50.0______306.503____257.452
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "HIGH",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 39,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 30,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 39,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
| gpl-3.0 | 11d6f578cd0d20e493d563fd308a2c71 | 0.593765 | 4.186552 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/tx_unit.vhdl | 1 | 5,641 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library zpu;
use zpu.UART.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
bitpos:=1;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
| bsd-3-clause | 885c54591597ec8987637f6088ced19f | 0.30172 | 5.482021 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/dmips_bram.vhdl | 1 | 105,094 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80f8ec0c",
3 => x"3a0b0b80",
4 => x"e7ea0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80e8b72d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80f8",
162 => x"d8738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b80ce",
171 => x"b62d5050",
172 => x"80085688",
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4259 => x"00000000",
4260 => x"00000000",
4261 => x"00000000",
4262 => x"00000000",
4263 => x"00000000",
4264 => x"00000000",
4265 => x"00000000",
4266 => x"00000000",
4267 => x"00000000",
4268 => x"00000000",
4269 => x"00000000",
4270 => x"00000000",
4271 => x"00000000",
4272 => x"00000000",
4273 => x"00000000",
4274 => x"00000000",
4275 => x"00000000",
4276 => x"00000000",
4277 => x"00000000",
4278 => x"00000000",
4279 => x"00000000",
4280 => x"00000000",
4281 => x"00000000",
4282 => x"00000000",
4283 => x"00000000",
4284 => x"00000000",
4285 => x"00000000",
4286 => x"00000000",
4287 => x"00000000",
4288 => x"00000000",
4289 => x"00000000",
4290 => x"00000000",
4291 => x"00000000",
4292 => x"00000000",
4293 => x"00000000",
4294 => x"00000000",
4295 => x"00000000",
4296 => x"00000000",
4297 => x"00000000",
4298 => x"00000000",
4299 => x"00000000",
4300 => x"00000000",
4301 => x"00000000",
4302 => x"00000000",
4303 => x"00000000",
4304 => x"00000000",
4305 => x"00000000",
4306 => x"00000000",
4307 => x"00000000",
4308 => x"00000000",
4309 => x"00000000",
4310 => x"00000000",
4311 => x"00000000",
4312 => x"00000000",
4313 => x"00000000",
4314 => x"00000000",
4315 => x"00000000",
4316 => x"00000000",
4317 => x"00000000",
4318 => x"00000000",
4319 => x"00000000",
4320 => x"00000000",
4321 => x"00000000",
4322 => x"00000000",
4323 => x"00000000",
4324 => x"00000000",
4325 => x"00000000",
4326 => x"00000000",
4327 => x"00000000",
4328 => x"00000000",
4329 => x"00000000",
4330 => x"00000000",
4331 => x"00000000",
4332 => x"00000000",
4333 => x"00000000",
4334 => x"00000000",
4335 => x"00000000",
4336 => x"00000000",
4337 => x"00000000",
4338 => x"00000000",
4339 => x"00000000",
4340 => x"00000000",
4341 => x"00000000",
4342 => x"00000000",
4343 => x"00000000",
4344 => x"00000000",
4345 => x"00000000",
4346 => x"00000000",
4347 => x"00000000",
4348 => x"00000000",
4349 => x"00000000",
4350 => x"00000000",
4351 => x"00000000",
4352 => x"00000000",
4353 => x"00000000",
4354 => x"00000000",
4355 => x"00000000",
4356 => x"00000000",
4357 => x"00000000",
4358 => x"00000000",
4359 => x"00000000",
4360 => x"00000000",
4361 => x"00000000",
4362 => x"00000000",
4363 => x"00000000",
4364 => x"00000000",
4365 => x"00000000",
4366 => x"00000000",
4367 => x"00000000",
4368 => x"00000000",
4369 => x"00000000",
4370 => x"00003c4c",
4371 => x"ffffffff",
4372 => x"00000000",
4373 => x"ffffffff",
4374 => x"00000000",
4375 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | 5030dddb7567b616ab068f449ffd76d1 | 0.543913 | 2.288782 | false | false | false | false |
223323/lab2 | HDL/source/coregen/dcm75MHz.vhd | 1 | 6,526 | -- file: dcm75MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____75.000______0.000______50.0______466.666____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________27____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm75MHz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm75MHz;
architecture xilinx of dcm75MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm75MHz,clk_wiz_v3_6,{component_name=dcm75MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 9,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 37.037,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | d3aec9e7901e1a64bcea671ab4fcda45 | 0.556696 | 4.259791 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/hello_dbram.vhdl | 1 | 70,238 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end entity DualPortRAM;
architecture DualPort_Arch of DualPortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
shared variable ram : ram_type:=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cd800c",
3 => x"3a0b0b80",
4 => x"c58f0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80c5d62d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80cc",
162 => x"ec738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b0b8b",
171 => x"8a2d5050",
172 => x"80085688",
173 => x"0c840c80",
174 => x"0c510400",
175 => x"00000000",
176 => x"80088408",
177 => x"88087575",
178 => x"0b0b0b8c",
179 => x"bc2d5050",
180 => x"80085688",
181 => x"0c840c80",
182 => x"0c510400",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80ccfc0c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"82c73f80",
257 => x"c4913f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"fe3d0d0b",
281 => x"0b80dce8",
282 => x"08538413",
283 => x"0870882a",
284 => x"70810651",
285 => x"52527080",
286 => x"2ef03871",
287 => x"81ff0680",
288 => x"0c843d0d",
289 => x"04ff3d0d",
290 => x"0b0b80dc",
291 => x"e8085271",
292 => x"0870882a",
293 => x"81327081",
294 => x"06515151",
295 => x"70f13873",
296 => x"720c833d",
297 => x"0d0480cc",
298 => x"fc08802e",
299 => x"a43880cd",
300 => x"8008822e",
301 => x"bd388380",
302 => x"800b0b0b",
303 => x"80dce80c",
304 => x"82a0800b",
305 => x"80dcec0c",
306 => x"8290800b",
307 => x"80dcf00c",
308 => x"04f88080",
309 => x"80a40b0b",
310 => x"0b80dce8",
311 => x"0cf88080",
312 => x"82800b80",
313 => x"dcec0cf8",
314 => x"80808480",
315 => x"0b80dcf0",
316 => x"0c0480c0",
317 => x"a8808c0b",
318 => x"0b0b80dc",
319 => x"e80c80c0",
320 => x"a880940b",
321 => x"80dcec0c",
322 => x"0b0b80cc",
323 => x"c40b80dc",
324 => x"f00c04ff",
325 => x"3d0d80dc",
326 => x"f4335170",
327 => x"a73880cd",
328 => x"88087008",
329 => x"52527080",
330 => x"2e943884",
331 => x"1280cd88",
332 => x"0c702d80",
333 => x"cd880870",
334 => x"08525270",
335 => x"ee38810b",
336 => x"80dcf434",
337 => x"833d0d04",
338 => x"04803d0d",
339 => x"0b0b80dc",
340 => x"e408802e",
341 => x"8e380b0b",
342 => x"0b0b800b",
343 => x"802e0981",
344 => x"06853882",
345 => x"3d0d040b",
346 => x"0b80dce4",
347 => x"510b0b0b",
348 => x"f58e3f82",
349 => x"3d0d0404",
350 => x"803d0d80",
351 => x"ccc85185",
352 => x"de3f800b",
353 => x"800c823d",
354 => x"0d048c08",
355 => x"028c0cf9",
356 => x"3d0d800b",
357 => x"8c08fc05",
358 => x"0c8c0888",
359 => x"05088025",
360 => x"ab388c08",
361 => x"88050830",
362 => x"8c088805",
363 => x"0c800b8c",
364 => x"08f4050c",
365 => x"8c08fc05",
366 => x"08883881",
367 => x"0b8c08f4",
368 => x"050c8c08",
369 => x"f405088c",
370 => x"08fc050c",
371 => x"8c088c05",
372 => x"088025ab",
373 => x"388c088c",
374 => x"0508308c",
375 => x"088c050c",
376 => x"800b8c08",
377 => x"f0050c8c",
378 => x"08fc0508",
379 => x"8838810b",
380 => x"8c08f005",
381 => x"0c8c08f0",
382 => x"05088c08",
383 => x"fc050c80",
384 => x"538c088c",
385 => x"0508528c",
386 => x"08880508",
387 => x"5181a73f",
388 => x"8008708c",
389 => x"08f8050c",
390 => x"548c08fc",
391 => x"0508802e",
392 => x"8c388c08",
393 => x"f8050830",
394 => x"8c08f805",
395 => x"0c8c08f8",
396 => x"05087080",
397 => x"0c54893d",
398 => x"0d8c0c04",
399 => x"8c08028c",
400 => x"0cfb3d0d",
401 => x"800b8c08",
402 => x"fc050c8c",
403 => x"08880508",
404 => x"80259338",
405 => x"8c088805",
406 => x"08308c08",
407 => x"88050c81",
408 => x"0b8c08fc",
409 => x"050c8c08",
410 => x"8c050880",
411 => x"258c388c",
412 => x"088c0508",
413 => x"308c088c",
414 => x"050c8153",
415 => x"8c088c05",
416 => x"08528c08",
417 => x"88050851",
418 => x"ad3f8008",
419 => x"708c08f8",
420 => x"050c548c",
421 => x"08fc0508",
422 => x"802e8c38",
423 => x"8c08f805",
424 => x"08308c08",
425 => x"f8050c8c",
426 => x"08f80508",
427 => x"70800c54",
428 => x"873d0d8c",
429 => x"0c048c08",
430 => x"028c0cfd",
431 => x"3d0d810b",
432 => x"8c08fc05",
433 => x"0c800b8c",
434 => x"08f8050c",
435 => x"8c088c05",
436 => x"088c0888",
437 => x"050827ac",
438 => x"388c08fc",
439 => x"0508802e",
440 => x"a338800b",
441 => x"8c088c05",
442 => x"08249938",
443 => x"8c088c05",
444 => x"08108c08",
445 => x"8c050c8c",
446 => x"08fc0508",
447 => x"108c08fc",
448 => x"050cc939",
449 => x"8c08fc05",
450 => x"08802e80",
451 => x"c9388c08",
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2493 => x"00000000",
2494 => x"00000000",
2495 => x"00000000",
2496 => x"00000000",
2497 => x"00000000",
2498 => x"00000000",
2499 => x"00000000",
2500 => x"00000000",
2501 => x"00000000",
2502 => x"00000000",
2503 => x"00000000",
2504 => x"00000000",
2505 => x"00000000",
2506 => x"00000000",
2507 => x"00000000",
2508 => x"00000000",
2509 => x"00000000",
2510 => x"00000001",
2511 => x"330eabcd",
2512 => x"1234e66d",
2513 => x"deec0005",
2514 => x"000b0000",
2515 => x"00000000",
2516 => x"00000000",
2517 => x"00000000",
2518 => x"00000000",
2519 => x"00000000",
2520 => x"00000000",
2521 => x"00000000",
2522 => x"00000000",
2523 => x"00000000",
2524 => x"00000000",
2525 => x"00000000",
2526 => x"00000000",
2527 => x"00000000",
2528 => x"00000000",
2529 => x"00000000",
2530 => x"00000000",
2531 => x"00000000",
2532 => x"00000000",
2533 => x"00000000",
2534 => x"00000000",
2535 => x"00000000",
2536 => x"00000000",
2537 => x"00000000",
2538 => x"00000000",
2539 => x"00000000",
2540 => x"00000000",
2541 => x"00000000",
2542 => x"00000000",
2543 => x"00000000",
2544 => x"00000000",
2545 => x"00000000",
2546 => x"00000000",
2547 => x"00000000",
2548 => x"00000000",
2549 => x"00000000",
2550 => x"00000000",
2551 => x"00000000",
2552 => x"00000000",
2553 => x"00000000",
2554 => x"00000000",
2555 => x"00000000",
2556 => x"00000000",
2557 => x"00000000",
2558 => x"00000000",
2559 => x"00000000",
2560 => x"00000000",
2561 => x"00000000",
2562 => x"00000000",
2563 => x"00000000",
2564 => x"00000000",
2565 => x"00000000",
2566 => x"00000000",
2567 => x"00000000",
2568 => x"00000000",
2569 => x"00000000",
2570 => x"00000000",
2571 => x"00000000",
2572 => x"00000000",
2573 => x"00000000",
2574 => x"00000000",
2575 => x"00000000",
2576 => x"00000000",
2577 => x"00000000",
2578 => x"00000000",
2579 => x"00000000",
2580 => x"00000000",
2581 => x"00000000",
2582 => x"00000000",
2583 => x"00000000",
2584 => x"00000000",
2585 => x"00000000",
2586 => x"00000000",
2587 => x"00000000",
2588 => x"00000000",
2589 => x"00000000",
2590 => x"00000000",
2591 => x"00000000",
2592 => x"00000000",
2593 => x"00000000",
2594 => x"00000000",
2595 => x"00000000",
2596 => x"00000000",
2597 => x"00000000",
2598 => x"00000000",
2599 => x"00000000",
2600 => x"00000000",
2601 => x"00000000",
2602 => x"00000000",
2603 => x"00000000",
2604 => x"00000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"00000000",
2609 => x"00000000",
2610 => x"00000000",
2611 => x"00000000",
2612 => x"00000000",
2613 => x"00000000",
2614 => x"00000000",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"00000000",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000000",
2638 => x"00000000",
2639 => x"00000000",
2640 => x"00000000",
2641 => x"00000000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000000",
2654 => x"00000000",
2655 => x"00000000",
2656 => x"00000000",
2657 => x"00000000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"ffffffff",
2704 => x"00000000",
2705 => x"00020000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00002a48",
2709 => x"00002a48",
2710 => x"00002a50",
2711 => x"00002a50",
2712 => x"00002a58",
2713 => x"00002a58",
2714 => x"00002a60",
2715 => x"00002a60",
2716 => x"00002a68",
2717 => x"00002a68",
2718 => x"00002a70",
2719 => x"00002a70",
2720 => x"00002a78",
2721 => x"00002a78",
2722 => x"00002a80",
2723 => x"00002a80",
2724 => x"00002a88",
2725 => x"00002a88",
2726 => x"00002a90",
2727 => x"00002a90",
2728 => x"00002a98",
2729 => x"00002a98",
2730 => x"00002aa0",
2731 => x"00002aa0",
2732 => x"00002aa8",
2733 => x"00002aa8",
2734 => x"00002ab0",
2735 => x"00002ab0",
2736 => x"00002ab8",
2737 => x"00002ab8",
2738 => x"00002ac0",
2739 => x"00002ac0",
2740 => x"00002ac8",
2741 => x"00002ac8",
2742 => x"00002ad0",
2743 => x"00002ad0",
2744 => x"00002ad8",
2745 => x"00002ad8",
2746 => x"00002ae0",
2747 => x"00002ae0",
2748 => x"00002ae8",
2749 => x"00002ae8",
2750 => x"00002af0",
2751 => x"00002af0",
2752 => x"00002af8",
2753 => x"00002af8",
2754 => x"00002b00",
2755 => x"00002b00",
2756 => x"00002b08",
2757 => x"00002b08",
2758 => x"00002b10",
2759 => x"00002b10",
2760 => x"00002b18",
2761 => x"00002b18",
2762 => x"00002b20",
2763 => x"00002b20",
2764 => x"00002b28",
2765 => x"00002b28",
2766 => x"00002b30",
2767 => x"00002b30",
2768 => x"00002b38",
2769 => x"00002b38",
2770 => x"00002b40",
2771 => x"00002b40",
2772 => x"00002b48",
2773 => x"00002b48",
2774 => x"00002b50",
2775 => x"00002b50",
2776 => x"00002b58",
2777 => x"00002b58",
2778 => x"00002b60",
2779 => x"00002b60",
2780 => x"00002b68",
2781 => x"00002b68",
2782 => x"00002b70",
2783 => x"00002b70",
2784 => x"00002b78",
2785 => x"00002b78",
2786 => x"00002b80",
2787 => x"00002b80",
2788 => x"00002b88",
2789 => x"00002b88",
2790 => x"00002b90",
2791 => x"00002b90",
2792 => x"00002b98",
2793 => x"00002b98",
2794 => x"00002ba0",
2795 => x"00002ba0",
2796 => x"00002ba8",
2797 => x"00002ba8",
2798 => x"00002bb0",
2799 => x"00002bb0",
2800 => x"00002bb8",
2801 => x"00002bb8",
2802 => x"00002bc0",
2803 => x"00002bc0",
2804 => x"00002bc8",
2805 => x"00002bc8",
2806 => x"00002bd0",
2807 => x"00002bd0",
2808 => x"00002bd8",
2809 => x"00002bd8",
2810 => x"00002be0",
2811 => x"00002be0",
2812 => x"00002be8",
2813 => x"00002be8",
2814 => x"00002bf0",
2815 => x"00002bf0",
2816 => x"00002bf8",
2817 => x"00002bf8",
2818 => x"00002c00",
2819 => x"00002c00",
2820 => x"00002c08",
2821 => x"00002c08",
2822 => x"00002c10",
2823 => x"00002c10",
2824 => x"00002c18",
2825 => x"00002c18",
2826 => x"00002c20",
2827 => x"00002c20",
2828 => x"00002c28",
2829 => x"00002c28",
2830 => x"00002c30",
2831 => x"00002c30",
2832 => x"00002c38",
2833 => x"00002c38",
2834 => x"00002c40",
2835 => x"00002c40",
2836 => x"00002c48",
2837 => x"00002c48",
2838 => x"00002c50",
2839 => x"00002c50",
2840 => x"00002c58",
2841 => x"00002c58",
2842 => x"00002c60",
2843 => x"00002c60",
2844 => x"00002c68",
2845 => x"00002c68",
2846 => x"00002c70",
2847 => x"00002c70",
2848 => x"00002c78",
2849 => x"00002c78",
2850 => x"00002c80",
2851 => x"00002c80",
2852 => x"00002c88",
2853 => x"00002c88",
2854 => x"00002c90",
2855 => x"00002c90",
2856 => x"00002c98",
2857 => x"00002c98",
2858 => x"00002ca0",
2859 => x"00002ca0",
2860 => x"00002ca8",
2861 => x"00002ca8",
2862 => x"00002cb0",
2863 => x"00002cb0",
2864 => x"00002cb8",
2865 => x"00002cb8",
2866 => x"00002cc0",
2867 => x"00002cc0",
2868 => x"00002cc8",
2869 => x"00002cc8",
2870 => x"00002cd0",
2871 => x"00002cd0",
2872 => x"00002cd8",
2873 => x"00002cd8",
2874 => x"00002ce0",
2875 => x"00002ce0",
2876 => x"00002ce8",
2877 => x"00002ce8",
2878 => x"00002cf0",
2879 => x"00002cf0",
2880 => x"00002cf8",
2881 => x"00002cf8",
2882 => x"00002d00",
2883 => x"00002d00",
2884 => x"00002d08",
2885 => x"00002d08",
2886 => x"00002d10",
2887 => x"00002d10",
2888 => x"00002d18",
2889 => x"00002d18",
2890 => x"00002d20",
2891 => x"00002d20",
2892 => x"00002d28",
2893 => x"00002d28",
2894 => x"00002d30",
2895 => x"00002d30",
2896 => x"00002d38",
2897 => x"00002d38",
2898 => x"00002d40",
2899 => x"00002d40",
2900 => x"00002d48",
2901 => x"00002d48",
2902 => x"00002d50",
2903 => x"00002d50",
2904 => x"00002d58",
2905 => x"00002d58",
2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002660",
2965 => x"ffffffff",
2966 => x"00000000",
2967 => x"ffffffff",
2968 => x"00000000",
2969 => x"00000000",
others => x"00000000"
);
begin
do_port_a:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
report "DualPortRAM write collision" severity failure;
end if;
iaddr:=to_integer(a_addr_i);
if a_we_i='1' then
ram(iaddr):=a_write_i;
a_read_o <= a_write_i;
else
a_read_o <= ram(iaddr);
end if;
end if;
end process do_port_a;
do_port_b:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
iaddr:=to_integer(b_addr_i);
if b_we_i='1' then
ram(iaddr):=b_write_i;
b_read_o <= b_write_i;
else
b_read_o <= ram(iaddr);
end if;
end if;
end process do_port_b;
end architecture DualPort_Arch; -- Entity: DualPortRAM
| bsd-3-clause | 03ce558517f45692341c5d653c2adf8b | 0.549304 | 2.316939 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/Main.vhd | 1 | 3,045 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 03/14/2015
-- Design Name:
-- Module Name: Main - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- spec
-- NbN : 50kHz
-- ¬Ë¸x : 0.02ms
-- Åå¬ËÂ\Ô : 5.1ms
-- oÂ\Åáñ] : 1700rpm
entity Main is
port(
clk : in std_logic;
enable : in std_logic;
timing_pulse : in std_logic;
fi_pulse : out std_logic;
sck: in std_logic;
ssel: in std_logic;
mosi : in std_logic;
miso : out std_logic;
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0');
cpu_con : inout std_logic_vector(1 downto 0) := (others => '0'));
end Main;
architecture RTL of Main is
component SerialReceiver
port(
clk : in std_logic;
rx : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component;
component SerialSender
port(
clk : in std_logic;
tx : out std_logic;
data : in std_logic_vector(7 downto 0);
send : in std_logic;
sending : out std_logic := '0'
);
end component;
component PulseTimer
port(
clk : in std_logic;
enable : in std_logic;
start : in std_logic;
match : in std_logic_vector(7 downto 0);
pulse : out std_logic
);
end component;
component Stopwatch
port(
clk : in std_logic;
stamp_and_reset : in std_logic;
time_stamp : out std_logic_vector(7 downto 0)
);
end component;
component SPISlave
port(
sck : in std_logic;
mosi : in std_logic;
miso : out std_logic;
ssel : in std_logic;
in_data : in std_logic_vector(7 downto 0);
out_data : out std_logic_vector(7 downto 0)
);
end component;
component Stepper
port(
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0')
);
end component;
signal counter_match : std_logic_vector(7 downto 0) := (others => '0');
signal time_stamp : std_logic_vector(7 downto 0);
begin
--cpu_con(0) <= timing_pulse;
st: Stepper port map (
iac_pulse => iac_pulse,
iac_clockwise => iac_clockwise,
iac_out => iac_out
);
sw: Stopwatch port map (
clk => clk,
stamp_and_reset => timing_pulse,
time_stamp => time_stamp
);
spi: SPISlave port map (
sck => sck,
mosi => mosi,
miso => miso,
ssel => ssel,
out_data => counter_match,
in_data => time_stamp
--in_data => std_logic_vector(to_unsigned(123, 8))
);
fi_pulse_gen: PulseTimer port map (
clk => clk,
enable => enable,
start => timing_pulse,
match => counter_match,
pulse => fi_pulse
);
end RTL;
| bsd-3-clause | ccce251f3101d42af0bb51d78026c2a6 | 0.579967 | 2.793578 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/Latches And Flip Flops/D Flip Flop.vhd | 1 | 541 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Flip_Flop is
port
(
rst : in std_logic;
pre : in std_logic;
ce : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity D_Flip_Flop;
architecture Behavioral of D_Flip_Flop is
begin
process (ce, rst, pre) is
begin
if rising_edge(ce) then
q <= d;
end if;
if (rst='1') then
q <= '0';
elsif (pre='1') then
q <= '1';
end if;
end process;
end architecture Behavioral; | gpl-3.0 | 4a45d466834750e9a2b50d80e1147dc1 | 0.530499 | 3.319018 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/zwishbone_tb.vhdl | 1 | 7,086 | ------------------------------------------------------------------------------
---- ----
---- zwishbone testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone;
entity zwishbone_TB is
end entity zwishbone_TB;
architecture Behave of zwishbone_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
component zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=16;
DATA_WIDTH : natural:=32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- c_decode
en_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0)
);
end component zwishbone_c_regs;
signal clk : std_logic;
signal reset : std_logic:='1';
signal break : std_logic;
signal enable : std_logic;
signal we : std_logic;
signal adr : unsigned(15 downto 0);
signal dat_o : unsigned(31 downto 0);
signal dat_i : unsigned(31 downto 0);
signal cfg : unsigned(31 downto 0);
begin
c_regs : zwishbone_c_regs
generic map(
ADR_WIDTH => 16,
DATA_WIDTH => 32
)
port map(
clk_i => clk,
rst_i => reset,
en_i => enable,
we_i => we,
adr_i => adr,
dat_i => dat_o,
dat_o => dat_i,
cfg_o => cfg
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
do_test:
process(clk)
variable state : integer:=0;
begin
if rising_edge(clk) then
if reset='1' then
adr <= (others => '0');
dat_o <= (others => '0');
enable <= '0';
we <= '0';
else
case state is
when 0 =>
adr <= (others => '0');
dat_o <= to_unsigned(2, dat_o'length);
we <= '1';
enable <= '1';
state := state + 1;
when 1 =>
adr <= (others => '0');
dat_o <= to_unsigned(2, dat_o'length);
we <= '1';
enable <= '1';
state := state + 1;
when 2 =>
we <= '0';
enable <= '0';
state := state + 1;
when 3 =>
we <= '0';
enable <= '0';
state := state + 1;
when 4 =>
adr <= (others => '0');
enable <= '1';
state := state + 1;
when 5 =>
adr <= (others => '0');
enable <= '1';
state := state +1;
when others =>
state := state + 1;
end case;
end if;
end if;
end process do_test;
end architecture Behave; -- Entity: zwishbone_TB
| bsd-3-clause | b4b8dc34a0a3344e91131f24cca4f58d | 0.282388 | 5.686998 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/ClockGenerator.vhd | 1 | 722 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ClockGenerator is
Port ( clk100Mhz : in STD_LOGIC;
reset : in STD_LOGIC;
clk50Mhz : out STD_LOGIC);
end ClockGenerator;
architecture Behavioral of ClockGenerator is
begin
DCM_SP_inst : DCM_BASE
generic map (
CLKDV_DIVIDE => 4.0, -- CLKDV divide value
CLK_FEEDBACK => "NONE" -- Specify clock feedback of NONE or 1X
)
port map (
CLKIN => clk100Mhz, -- 1-bit output: 0 degree clock output
CLKDV => clk50Mhz, -- 1-bit output: Divided clock output
RST => reset -- 1-bit input: Active high reset input
);
end Behavioral; | mit | 325a8a557b3bce22df24494a4562d9de | 0.623269 | 3.820106 | false | false | false | false |
sonologic/gmzpu | vhdl/zpu_pkg.vhdl | 1 | 15,392 | ------------------------------------------------------------------------------
---- ----
---- ZPU Package ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the package. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpupkg, UART (Package) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zpupkg is
constant OPCODE_W : integer:=8;
-- Debug structure, currently only for the trace module
type zpu_dbgo_t is record
b_inst : std_logic;
opcode : unsigned(OPCODE_W-1 downto 0);
pc : unsigned(31 downto 0);
sp : unsigned(31 downto 0);
stk_a : unsigned(31 downto 0);
stk_b : unsigned(31 downto 0);
end record;
component Trace is
generic(
LOG_FILE : string:="trace.txt"; -- Name of the trace file
ADDR_W : integer:=16; -- Address width
WORD_SIZE : integer:=32); -- 16/32
port(
clk_i : in std_logic;
dbg_i : in zpu_dbgo_t;
stop_i : in std_logic;
busy_i : in std_logic
);
end component Trace;
component ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end component ZPUSmallCore;
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
interrupt_i : in std_logic; -- Interrupt
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end component ZPUMediumCore;
component Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end component Timer;
component gpio is
port(
clk_i : in std_logic;
reset_i : in std_logic;
--
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned( 0 downto 0);
data_o : out unsigned(31 downto 0);
--
port_in : in std_logic_vector(31 downto 0);
port_out : out std_logic_vector(31 downto 0);
port_dir : out std_logic_vector(31 downto 0)
);
end component gpio;
component ZPUPhiIO is
generic(
BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
ENA_LOG : boolean:=true; -- Enable log
LOG_FILE : string:="log.txt"); -- Name for the log file
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
busy_o : out std_logic; -- I/O is busy
we_i : in std_logic; -- Write Enable
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_i : in unsigned(2 downto 0); -- Address bits 4-2
--
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
br_clk_i : in std_logic; -- UART base clock (enable)
--
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0)
);
end component ZPUPhiIO;
-- Opcode decode constants
-- Note: these are the basic opcodes, always implemented using hardware.
constant OPCODE_IM : unsigned(7 downto 7):="1";
constant OPCODE_STORESP : unsigned(7 downto 5):="010";
constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
constant OPCODE_ADD : unsigned(3 downto 0):="0101";
constant OPCODE_AND : unsigned(3 downto 0):="0110";
constant OPCODE_OR : unsigned(3 downto 0):="0111";
constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
constant OPCODE_NOT : unsigned(3 downto 0):="1001";
constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
constant OPCODE_NOP : unsigned(3 downto 0):="1011";
constant OPCODE_STORE : unsigned(3 downto 0):="1100";
constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
-- The following instructions are emulated in the small version and
-- implemented as hardware in the full version.
-- The constants correpond to the "emulated" instruction number.
-- Enabled by the ENA_LEVEL0 generic:
constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
-- Enabled by the ENA_LEVEL1 generic:
constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
-- Enabled by the ENA_LEVEL2 generic:
constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
-- Enabled by the ENA_LSHR generic:
constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
-- The following opcodes are always emulated.
constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
end package zpupkg;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package UART is
----------------------
-- Very simple UART --
----------------------
component RxUnit is
port(
clk_i : in std_logic; -- System clock signal
reset_i : in std_logic; -- Reset input (sync)
enable_i : in std_logic; -- Enable input (rate*4)
read_i : in std_logic; -- Received Byte Read
rxd_i : in std_logic; -- RS-232 data input
rxav_o : out std_logic; -- Byte available
datao_o : out std_logic_vector(7 downto 0)); -- Byte received
end component RxUnit;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component BRGen is
generic(
COUNT : integer range 0 to 65535);-- Count revolution
port (
clk_i : in std_logic; -- Clock
reset_i : in std_logic; -- Reset input
ce_i : in std_logic; -- Chip Enable
o_o : out std_logic); -- Output
end component BRGen;
end package UART;
| bsd-3-clause | d037ea040995615e5886d89ec13b252e | 0.479535 | 4.095796 | false | false | false | false |
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`protect end_protected
| mit | 7c709df3e011ff29c3f47cb11985f364 | 0.943778 | 1.851576 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/vram/vram.vhd | 1 | 6,222 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| gpl-3.0 | 1eadfa0645e0f220244a2494e76be104 | 0.522019 | 3.883895 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/rom_pkg.vhdl | 1 | 4,618 | ------------------------------------------------------------------------------
---- ----
---- ZPU memories package ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a package with the memories used for the ZPU core. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_memory (Package) ----
---- File name: rom_pkg.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zpu_memory is
component DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end component DualPortRAM;
component SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end component SinglePortRAM;
end package zpu_memory;
| bsd-3-clause | 33b4da8bb86696cf1e6b5f59d6104c7e | 0.295799 | 5.631707 | false | false | false | false |
dqydj/PaperBack_EPaper_Display | firmware_VGA/FPGA/grab_screen.vhd | 1 | 7,130 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity FrameGrabber is
port(
-- Memory
ADDR: out std_logic_vector(18 downto 0);
IO: inout std_logic_vector(7 downto 0);
MEM_OE: out std_logic := '1'; -- Active low
MEM_WE: out std_logic := '1'; -- Active low
MEM_CE: out std_logic := '1'; -- Active low
-- VGA
HSYNC: in std_logic;
VSYNC: in std_logic;
DCLK: in std_logic;
--RED: in std_logic_vector(7 downto 4);
GREEN: in std_logic_vector(7 downto 4);
--BLUE: in std_logic_vector(7 downto 4);
-- Control State
FRAME_GRAB_DONE: out std_logic;
FRAME_WRITE_DONE: in std_logic
);
end FrameGrabber;
architecture Behavioral of FrameGrabber is
-- Screen Constants
constant SCREEN_WIDTH : integer := 800;
constant SCREEN_HEIGHT : integer := 600;
constant SCREEN_OVERSCAN : integer := (800*600)+10000;
constant SCREEN_OVERSCAN_FLAG : integer := SCREEN_OVERSCAN-100;
-- Left columns to ignore
constant FRONT_PORCH : integer := 206;
-- Rows to Ignore
constant ROW_PORCH : integer := 26;
-- State Frame Grab
signal READY_GRAB: std_logic := '0';
signal CHECK_WRITE_DONE: std_logic := '0';
signal pixel_reset_clk: unsigned(0 to 1) := (others => '0');
signal pixel_count: unsigned(27 downto 0) := (others => '0');
signal VGA_COL : unsigned(10 downto 0) := (others => '0');
signal VGA_ROW : unsigned(10 downto 0) := (others => '0');
-- PIXEL caches
signal SEEN_VSYNC: std_logic := '0';
signal PIXEL_00: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_01: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_02: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_03: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_04: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_05: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_06: std_logic_vector(3 downto 0) := (others => '0');
signal PIXEL_07: std_logic_vector(3 downto 0) := (others => '0');
-- Return decoded EPD Pixels
function epdPix (
PIXEL : in std_logic_vector(3 downto 0);
ADDRESS : in unsigned(1 downto 0)
) return STD_LOGIC_VECTOR IS
variable decodedPixel : STD_LOGIC_VECTOR(1 downto 0);
begin
if (ADDRESS = "00") then
if (PIXEL(3) = '1') then
decodedPixel := "10";
else
decodedPixel := "01";
end if;
elsif (ADDRESS = "01") then
if (PIXEL(2) = '1') then
decodedPixel := "10";
else
decodedPixel := "01";
end if;
elsif (ADDRESS = "10") then
if (PIXEL(1) = '1') then
decodedPixel := "10";
else
decodedPixel := "01";
end if;
elsif (ADDRESS = "11") then
if (PIXEL(0) = '1') then
decodedPixel := "00";
else
decodedPixel := "01";
end if;
end if;
return decodedPixel;
end epdPix;
begin
-- Control clocking video into the SRAM
MEM_WE <= DCLK when
(
READY_GRAB = '1' and
pixel_count < SCREEN_OVERSCAN and
HSYNC = '0' and
VGA_COL >= to_unsigned(FRONT_PORCH, VGA_COL'length) and
VGA_COL < to_unsigned(SCREEN_WIDTH + FRONT_PORCH, VGA_COL'length) and
VGA_ROW >= ROW_PORCH
) else '1';
-- Pixel Clock
process(DCLK, HSYNC)
begin
if(rising_edge(HSYNC)) then
if (VSYNC = '0') then
VGA_ROW <= to_unsigned(0, VGA_ROW'length);
else
VGA_ROW <= VGA_ROW + 1;
end if;
end if;
if(rising_edge(DCLK)) then -- Rising pixel clock
if (pixel_reset_clk /= "11") then
pixel_reset_clk <= pixel_reset_clk + 1;
end if;
if (pixel_reset_clk = "01") then
FRAME_GRAB_DONE <= '0';
READY_GRAB <= '1';
CHECK_WRITE_DONE <= '1';
pixel_count <= (others => '0');
SEEN_VSYNC <= '0';
MEM_CE <= '1';
MEM_OE <= '1';
ADDR <= (others => 'Z');
IO <= (others => 'Z');
end if;
if (READY_GRAB = '0') then -- Check for state with synchronizing flip flop
READY_GRAB <= CHECK_WRITE_DONE;
CHECK_WRITE_DONE <= FRAME_WRITE_DONE;
else -- if READY_GRAB is '1' or it's time to grab a frame
if (VSYNC = '0') then
SEEN_VSYNC <= '1';
VGA_COL <= (others => '0');
VGA_ROW <= (others => '0');
else
SEEN_VSYNC <= SEEN_VSYNC;
end if;
if (VSYNC = '1' and SEEN_VSYNC = '1') then
if (pixel_count = to_unsigned(0, pixel_count'length)) then
FRAME_GRAB_DONE <= '0';
READY_GRAB <= '1';
MEM_CE <= '0';
MEM_OE <= '1';
end if;
if (pixel_count = to_unsigned(SCREEN_OVERSCAN_FLAG, pixel_count'length)) then
FRAME_GRAB_DONE <= '1';
MEM_CE <= '1';
MEM_OE <= '1';
end if;
-- PIXEL LOGIC
if (pixel_count /= to_unsigned(SCREEN_OVERSCAN, pixel_count'length)) then
if (
HSYNC = '0' and
VGA_COL >= to_unsigned(FRONT_PORCH, VGA_COL'length) and
VGA_COL < to_unsigned(SCREEN_WIDTH + FRONT_PORCH, VGA_COL'length) and
VGA_ROW >= ROW_PORCH
) then
case pixel_count(2 downto 0) is
when "000" => PIXEL_00 <= GREEN(7 downto 4);
when "001" => PIXEL_01 <= GREEN(7 downto 4);
when "010" => PIXEL_02 <= GREEN(7 downto 4);
when "011" => PIXEL_03 <= GREEN(7 downto 4);
when "100" => PIXEL_04 <= GREEN(7 downto 4);
when "101" => PIXEL_05 <= GREEN(7 downto 4);
when "110" => PIXEL_06 <= GREEN(7 downto 4);
when others => PIXEL_07 <= GREEN(7 downto 4);
end case;
if (pixel_count > to_unsigned(3, pixel_count'length)) then
ADDR <= std_logic_vector(pixel_count(18 downto 0) - 4);
case pixel_count(2) is
when '0' => IO <= epdPix(PIXEL_04, pixel_count(1 downto 0)) &
epdPix(PIXEL_05, pixel_count(1 downto 0)) &
epdPix(PIXEL_06, pixel_count(1 downto 0)) &
epdPix(PIXEL_07, pixel_count(1 downto 0));
when others => IO <= epdPix(PIXEL_00, pixel_count(1 downto 0)) &
epdPix(PIXEL_01, pixel_count(1 downto 0)) &
epdPix(PIXEL_02, pixel_count(1 downto 0)) &
epdPix(PIXEL_03, pixel_count(1 downto 0));
end case;
else
IO <= "00000000";
ADDR <= (others => '1');
end if;
pixel_count <= pixel_count + 1;
MEM_CE <= '0';
end if;
end if;
-- HSYNC Row Rollover / Reset columns, new row
if (HSYNC = '0') then
VGA_COL <= VGA_COL + 1;
else
VGA_COL <= (others => '0');
end if;
-- Rollover Logic
if (pixel_count = to_unsigned(SCREEN_OVERSCAN, pixel_count'length)) then
pixel_count <= to_unsigned(0, pixel_count'length);
READY_GRAB <= '0';
CHECK_WRITE_DONE <= '0';
FRAME_GRAB_DONE <= '0';
ADDR <= (others => 'Z');
IO <= (others => 'Z');
MEM_CE <= '1';
SEEN_VSYNC <= '0';
VGA_COL <= (others => '0');
VGA_ROW <= (others => '0');
-- Just grabbed a frame from VGA - go write it to the EPD
end if;
end if;
end if; -- Ready to Grab was 1
end if; -- end rising clock
end process; -- End Pixel Clock from AD9883/MST9883
end Behavioral; | mit | abdd03884bcfe896cc72dd361f8baa1d | 0.565217 | 2.923329 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb.vhd | 6 | 4,189 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: LUT_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUT_tb IS
END ENTITY;
ARCHITECTURE LUT_tb_ARCH OF LUT_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
LUT_tb_synth_inst:ENTITY work.LUT_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | c2199d6ee739c05d9d487d6ee6b90002 | 0.621867 | 4.613436 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/simulation/mips_vram_tb.vhd | 1 | 4,523 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: mips_vram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY mips_vram_tb IS
END ENTITY;
ARCHITECTURE mips_vram_tb_ARCH OF mips_vram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
mips_vram_synth_inst:ENTITY work.mips_vram_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | b652857ba4499225af2271f423744203 | 0.615742 | 4.587221 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_poly_5.vhdl | 1 | 1,271 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_5;
ARCHITECTURE vhdl OF pokey_poly_5 IS
signal shift_reg: std_logic_vector(4 downto 0);
signal shift_next: std_logic_vector(4 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
| gpl-3.0 | e2b4a89a3f414196e67c2e572d4080a5 | 0.598741 | 3.185464 | false | false | false | false |
APastorG/APG | general/common_data_types_pkg.vhd | 1 | 5,832 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains common data types
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package common_data_types_pkg is
subtype T_sulv_index is integer range -2**30 to 2**30-1;
type T_speed is (t_exc, t_min, t_low, t_medium, t_high, t_max);
--std_ulogic_vector vector
type sulv_v is array (natural range <>) of std_ulogic_vector;
--std_ulogic_vector vector of vectors
type sulv_vv is array (natural range <>) of sulv_v;
type natural_v is array (natural range <>) of natural;
type positive_v is array (natural range <>) of positive;
type integer_v is array (natural range <>) of integer;
type integer_vv is array (natural range <>) of integer_v;
type real_v is array (natural range <>) of real;
type boolean_v is array (natural range <>) of boolean;
--u_sfixed vector
type u_sfixed_v is array (integer range <>) of u_sfixed;
--vector u_sfixed vectors
type u_sfixed_vv is array (integer range <>) of u_sfixed_v;
--vector of vector of u_sfixed vectors
type u_sfixed_vvv is array (integer range <>) of u_sfixed_vv;
--u_ufixed vector
type u_ufixed_v is array (integer range <>) of u_ufixed;
--vector of u_ufixed vectors
type u_ufixed_vv is array (integer range <>) of u_ufixed_v;
--sfixed vector
type sfixed_v is array (integer range <>) of sfixed;
--ufixed vector
type ufixed_v is array (integer range <>) of ufixed;
--vector in canonical signed digit representation. Each bit has the possible values of 0, 1, or
-- -1, which are represented by 2 bits: 00, 01, or 11 respectively
type T_csd is array (integer range<>) of bit_vector(2 downto 1);
--types for describing the behavior of fixed and floating point data
alias T_round_style is fixed_round_style_type;
alias T_overflow_style is fixed_overflow_style_type;
--type used for exceptions of generics of type positive (possible values: positive + '0').
-- Exception will portrayed by value 0
type positive_exc is range 0 to integer'high;
--type used for exceptions of generics of type natural (possible values: natural + '-1').
-- Exception will portrayed by value -1
type natural_exc is range -1 to integer'high;
--subtype used for exceptions of generics of type integer.
-- Exception will portrayed by value integer'low
subtype integer_exc is integer;
--subtype used for exceptions of generics of type real
subtype real_exc is real;
--type used for exceptions of generics of type boolean (possible values: t_false, t_true, and
-- t_exc)
type boolean_exc is (t_exc, t_true, t_false);
--types to use in testbenches to ease the testing of defined/undefined generics. They allow
-- setting a value for a generic and whether the assignment has been done inside the instantiation
type T_round_style_tb is record
value : T_round_style;
is_defined : boolean;
end record;
type T_overflow_style_tb is record
value : T_overflow_style;
is_defined : boolean;
end record;
type T_speed_tb is record
value : T_speed;
is_defined : boolean;
end record;
type boolean_tb is record
value : boolean;
is_defined : boolean;
end record;
type boolean_exc_tb is record
value : boolean_exc;
is_defined : boolean;
end record;
type natural_tb is record
value : natural;
is_defined : boolean;
end record;
type natural_exc_tb is record
value : natural_exc;
is_defined : boolean;
end record;
type positive_tb is record
value : positive;
is_defined : boolean;
end record;
type positive_exc_tb is record
value : positive_exc;
is_defined : boolean;
end record;
type integer_tb is record
value : integer;
is_defined : boolean;
end record;
type integer_exc_tb is record
value : integer_exc;
is_defined : boolean;
end record;
type real_tb is record
value : real;
is_defined : boolean;
end record;
type real_exc_tb is record
value : real_exc;
is_defined : boolean;
end record;
/* functions 1 */
/**************************************************************************************************/
--function to convert boolean_exc to boolean to prevent errors in the elaboration phase
function to_boolean(
arg : boolean_exc)
return boolean;
end package;
package body common_data_types_pkg is
function to_boolean(
arg : boolean_exc)
return boolean is
begin
if arg = t_true then
return true;
else
return false;
end if;
end function;
end package body; | mit | 40b8de461f23f20fe5c589abcca7e5c0 | 0.571749 | 4.156272 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/hello_bram.vhdl | 1 | 72,756 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cd800c",
3 => x"3a0b0b80",
4 => x"c58f0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80c5d62d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80cc",
162 => x"ec738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b0b8b",
171 => x"8a2d5050",
172 => x"80085688",
173 => x"0c840c80",
174 => x"0c510400",
175 => x"00000000",
176 => x"80088408",
177 => x"88087575",
178 => x"0b0b0b8c",
179 => x"bc2d5050",
180 => x"80085688",
181 => x"0c840c80",
182 => x"0c510400",
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2251 => x"79557a54",
2252 => x"7d538552",
2253 => x"8d3dfc05",
2254 => x"51c2873f",
2255 => x"80085684",
2256 => x"ab3f7b80",
2257 => x"080c7580",
2258 => x"0c8d3d0d",
2259 => x"04f63d0d",
2260 => x"7d7f80dc",
2261 => x"fc08705b",
2262 => x"585a5a75",
2263 => x"80c13877",
2264 => x"7925b338",
2265 => x"c1fa3f80",
2266 => x"0881ff06",
2267 => x"708d3270",
2268 => x"30709f2a",
2269 => x"51515757",
2270 => x"768a2e80",
2271 => x"c3387580",
2272 => x"2ebe3877",
2273 => x"1a567676",
2274 => x"347651c1",
2275 => x"f83f8118",
2276 => x"58787824",
2277 => x"cf387756",
2278 => x"75800c8c",
2279 => x"3d0d0478",
2280 => x"5579547c",
2281 => x"5384528c",
2282 => x"3dfc0551",
2283 => x"c1943f80",
2284 => x"085683b8",
2285 => x"3f7a8008",
2286 => x"0c75800c",
2287 => x"8c3d0d04",
2288 => x"771a568a",
2289 => x"76348118",
2290 => x"588d51c1",
2291 => x"b83f8a51",
2292 => x"c1b33f77",
2293 => x"56c239fb",
2294 => x"3d0d80dc",
2295 => x"fc087056",
2296 => x"54738838",
2297 => x"74800c87",
2298 => x"3d0d0477",
2299 => x"53835287",
2300 => x"3dfc0551",
2301 => x"c0cc3f80",
2302 => x"085482f0",
2303 => x"3f758008",
2304 => x"0c73800c",
2305 => x"873d0d04",
2306 => x"fa3d0d80",
2307 => x"dcfc0880",
2308 => x"2ea2387a",
2309 => x"55795478",
2310 => x"53865288",
2311 => x"3dfc0551",
2312 => x"c0a03f80",
2313 => x"085682c4",
2314 => x"3f768008",
2315 => x"0c75800c",
2316 => x"883d0d04",
2317 => x"82b63f9d",
2318 => x"0b80080c",
2319 => x"ff0b800c",
2320 => x"883d0d04",
2321 => x"fb3d0d77",
2322 => x"79565680",
2323 => x"70545473",
2324 => x"75259f38",
2325 => x"74101010",
2326 => x"f8055272",
2327 => x"16703370",
2328 => x"742b7607",
2329 => x"8116f816",
2330 => x"56565651",
2331 => x"51747324",
2332 => x"ea387380",
2333 => x"0c873d0d",
2334 => x"04fc3d0d",
2335 => x"76785555",
2336 => x"bc538052",
2337 => x"7351f5ca",
2338 => x"3f845274",
2339 => x"51ffb53f",
2340 => x"80087423",
2341 => x"84528415",
2342 => x"51ffa93f",
2343 => x"80088215",
2344 => x"23845288",
2345 => x"1551ff9c",
2346 => x"3f800884",
2347 => x"150c8452",
2348 => x"8c1551ff",
2349 => x"8f3f8008",
2350 => x"88152384",
2351 => x"52901551",
2352 => x"ff823f80",
2353 => x"088a1523",
2354 => x"84529415",
2355 => x"51fef53f",
2356 => x"80088c15",
2357 => x"23845298",
2358 => x"1551fee8",
2359 => x"3f80088e",
2360 => x"15238852",
2361 => x"9c1551fe",
2362 => x"db3f8008",
2363 => x"90150c86",
2364 => x"3d0d04e9",
2365 => x"3d0d6a80",
2366 => x"dcfc0857",
2367 => x"57759338",
2368 => x"80c0800b",
2369 => x"84180c75",
2370 => x"ac180c75",
2371 => x"800c993d",
2372 => x"0d04893d",
2373 => x"70556a54",
2374 => x"558a5299",
2375 => x"3dffbc05",
2376 => x"51ffbe9e",
2377 => x"3f800877",
2378 => x"53755256",
2379 => x"fecb3fbc",
2380 => x"3f778008",
2381 => x"0c75800c",
2382 => x"993d0d04",
2383 => x"fc3d0d81",
2384 => x"5480dcfc",
2385 => x"08883873",
2386 => x"800c863d",
2387 => x"0d047653",
2388 => x"97b95286",
2389 => x"3dfc0551",
2390 => x"ffbde73f",
2391 => x"8008548c",
2392 => x"3f748008",
2393 => x"0c73800c",
2394 => x"863d0d04",
2395 => x"80cd8c08",
2396 => x"800c04f7",
2397 => x"3d0d7b80",
2398 => x"cd8c0882",
2399 => x"c811085a",
2400 => x"545a7780",
2401 => x"2e80da38",
2402 => x"81881884",
2403 => x"1908ff05",
2404 => x"81712b59",
2405 => x"55598074",
2406 => x"2480ea38",
2407 => x"807424b5",
2408 => x"3873822b",
2409 => x"78118805",
2410 => x"56568180",
2411 => x"19087706",
2412 => x"5372802e",
2413 => x"b6387816",
2414 => x"70085353",
2415 => x"79517408",
2416 => x"53722dff",
2417 => x"14fc17fc",
2418 => x"1779812c",
2419 => x"5a575754",
2420 => x"738025d6",
2421 => x"38770858",
2422 => x"77ffad38",
2423 => x"80cd8c08",
2424 => x"53bc1308",
2425 => x"a5387951",
2426 => x"f9e93f74",
2427 => x"0853722d",
2428 => x"ff14fc17",
2429 => x"fc177981",
2430 => x"2c5a5757",
2431 => x"54738025",
2432 => x"ffa838d1",
2433 => x"398057ff",
2434 => x"93397251",
2435 => x"bc130853",
2436 => x"722d7951",
2437 => x"f9bd3fff",
2438 => x"3d0d80dc",
2439 => x"d80bfc05",
2440 => x"70085252",
2441 => x"70ff2e91",
2442 => x"38702dfc",
2443 => x"12700852",
2444 => x"5270ff2e",
2445 => x"098106f1",
2446 => x"38833d0d",
2447 => x"0404ffbd",
2448 => x"d23f0400",
2449 => x"00000040",
2450 => x"48656c6c",
2451 => x"6f20776f",
2452 => x"726c6421",
2453 => x"00000000",
2454 => x"0a000000",
2455 => x"43000000",
2456 => x"64756d6d",
2457 => x"792e6578",
2458 => x"65000000",
2459 => x"00ffffff",
2460 => x"ff00ffff",
2461 => x"ffff00ff",
2462 => x"ffffff00",
2463 => x"00000000",
2464 => x"00000000",
2465 => x"00000000",
2466 => x"00002e60",
2467 => x"00002690",
2468 => x"00000000",
2469 => x"000028f8",
2470 => x"00002954",
2471 => x"000029b0",
2472 => x"00000000",
2473 => x"00000000",
2474 => x"00000000",
2475 => x"00000000",
2476 => x"00000000",
2477 => x"00000000",
2478 => x"00000000",
2479 => x"00000000",
2480 => x"00000000",
2481 => x"0000265c",
2482 => x"00000000",
2483 => x"00000000",
2484 => x"00000000",
2485 => x"00000000",
2486 => x"00000000",
2487 => x"00000000",
2488 => x"00000000",
2489 => x"00000000",
2490 => x"00000000",
2491 => x"00000000",
2492 => x"00000000",
2493 => x"00000000",
2494 => x"00000000",
2495 => x"00000000",
2496 => x"00000000",
2497 => x"00000000",
2498 => x"00000000",
2499 => x"00000000",
2500 => x"00000000",
2501 => x"00000000",
2502 => x"00000000",
2503 => x"00000000",
2504 => x"00000000",
2505 => x"00000000",
2506 => x"00000000",
2507 => x"00000000",
2508 => x"00000000",
2509 => x"00000000",
2510 => x"00000001",
2511 => x"330eabcd",
2512 => x"1234e66d",
2513 => x"deec0005",
2514 => x"000b0000",
2515 => x"00000000",
2516 => x"00000000",
2517 => x"00000000",
2518 => x"00000000",
2519 => x"00000000",
2520 => x"00000000",
2521 => x"00000000",
2522 => x"00000000",
2523 => x"00000000",
2524 => x"00000000",
2525 => x"00000000",
2526 => x"00000000",
2527 => x"00000000",
2528 => x"00000000",
2529 => x"00000000",
2530 => x"00000000",
2531 => x"00000000",
2532 => x"00000000",
2533 => x"00000000",
2534 => x"00000000",
2535 => x"00000000",
2536 => x"00000000",
2537 => x"00000000",
2538 => x"00000000",
2539 => x"00000000",
2540 => x"00000000",
2541 => x"00000000",
2542 => x"00000000",
2543 => x"00000000",
2544 => x"00000000",
2545 => x"00000000",
2546 => x"00000000",
2547 => x"00000000",
2548 => x"00000000",
2549 => x"00000000",
2550 => x"00000000",
2551 => x"00000000",
2552 => x"00000000",
2553 => x"00000000",
2554 => x"00000000",
2555 => x"00000000",
2556 => x"00000000",
2557 => x"00000000",
2558 => x"00000000",
2559 => x"00000000",
2560 => x"00000000",
2561 => x"00000000",
2562 => x"00000000",
2563 => x"00000000",
2564 => x"00000000",
2565 => x"00000000",
2566 => x"00000000",
2567 => x"00000000",
2568 => x"00000000",
2569 => x"00000000",
2570 => x"00000000",
2571 => x"00000000",
2572 => x"00000000",
2573 => x"00000000",
2574 => x"00000000",
2575 => x"00000000",
2576 => x"00000000",
2577 => x"00000000",
2578 => x"00000000",
2579 => x"00000000",
2580 => x"00000000",
2581 => x"00000000",
2582 => x"00000000",
2583 => x"00000000",
2584 => x"00000000",
2585 => x"00000000",
2586 => x"00000000",
2587 => x"00000000",
2588 => x"00000000",
2589 => x"00000000",
2590 => x"00000000",
2591 => x"00000000",
2592 => x"00000000",
2593 => x"00000000",
2594 => x"00000000",
2595 => x"00000000",
2596 => x"00000000",
2597 => x"00000000",
2598 => x"00000000",
2599 => x"00000000",
2600 => x"00000000",
2601 => x"00000000",
2602 => x"00000000",
2603 => x"00000000",
2604 => x"00000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"00000000",
2609 => x"00000000",
2610 => x"00000000",
2611 => x"00000000",
2612 => x"00000000",
2613 => x"00000000",
2614 => x"00000000",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"00000000",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000000",
2638 => x"00000000",
2639 => x"00000000",
2640 => x"00000000",
2641 => x"00000000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000000",
2654 => x"00000000",
2655 => x"00000000",
2656 => x"00000000",
2657 => x"00000000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"ffffffff",
2704 => x"00000000",
2705 => x"00020000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00002a48",
2709 => x"00002a48",
2710 => x"00002a50",
2711 => x"00002a50",
2712 => x"00002a58",
2713 => x"00002a58",
2714 => x"00002a60",
2715 => x"00002a60",
2716 => x"00002a68",
2717 => x"00002a68",
2718 => x"00002a70",
2719 => x"00002a70",
2720 => x"00002a78",
2721 => x"00002a78",
2722 => x"00002a80",
2723 => x"00002a80",
2724 => x"00002a88",
2725 => x"00002a88",
2726 => x"00002a90",
2727 => x"00002a90",
2728 => x"00002a98",
2729 => x"00002a98",
2730 => x"00002aa0",
2731 => x"00002aa0",
2732 => x"00002aa8",
2733 => x"00002aa8",
2734 => x"00002ab0",
2735 => x"00002ab0",
2736 => x"00002ab8",
2737 => x"00002ab8",
2738 => x"00002ac0",
2739 => x"00002ac0",
2740 => x"00002ac8",
2741 => x"00002ac8",
2742 => x"00002ad0",
2743 => x"00002ad0",
2744 => x"00002ad8",
2745 => x"00002ad8",
2746 => x"00002ae0",
2747 => x"00002ae0",
2748 => x"00002ae8",
2749 => x"00002ae8",
2750 => x"00002af0",
2751 => x"00002af0",
2752 => x"00002af8",
2753 => x"00002af8",
2754 => x"00002b00",
2755 => x"00002b00",
2756 => x"00002b08",
2757 => x"00002b08",
2758 => x"00002b10",
2759 => x"00002b10",
2760 => x"00002b18",
2761 => x"00002b18",
2762 => x"00002b20",
2763 => x"00002b20",
2764 => x"00002b28",
2765 => x"00002b28",
2766 => x"00002b30",
2767 => x"00002b30",
2768 => x"00002b38",
2769 => x"00002b38",
2770 => x"00002b40",
2771 => x"00002b40",
2772 => x"00002b48",
2773 => x"00002b48",
2774 => x"00002b50",
2775 => x"00002b50",
2776 => x"00002b58",
2777 => x"00002b58",
2778 => x"00002b60",
2779 => x"00002b60",
2780 => x"00002b68",
2781 => x"00002b68",
2782 => x"00002b70",
2783 => x"00002b70",
2784 => x"00002b78",
2785 => x"00002b78",
2786 => x"00002b80",
2787 => x"00002b80",
2788 => x"00002b88",
2789 => x"00002b88",
2790 => x"00002b90",
2791 => x"00002b90",
2792 => x"00002b98",
2793 => x"00002b98",
2794 => x"00002ba0",
2795 => x"00002ba0",
2796 => x"00002ba8",
2797 => x"00002ba8",
2798 => x"00002bb0",
2799 => x"00002bb0",
2800 => x"00002bb8",
2801 => x"00002bb8",
2802 => x"00002bc0",
2803 => x"00002bc0",
2804 => x"00002bc8",
2805 => x"00002bc8",
2806 => x"00002bd0",
2807 => x"00002bd0",
2808 => x"00002bd8",
2809 => x"00002bd8",
2810 => x"00002be0",
2811 => x"00002be0",
2812 => x"00002be8",
2813 => x"00002be8",
2814 => x"00002bf0",
2815 => x"00002bf0",
2816 => x"00002bf8",
2817 => x"00002bf8",
2818 => x"00002c00",
2819 => x"00002c00",
2820 => x"00002c08",
2821 => x"00002c08",
2822 => x"00002c10",
2823 => x"00002c10",
2824 => x"00002c18",
2825 => x"00002c18",
2826 => x"00002c20",
2827 => x"00002c20",
2828 => x"00002c28",
2829 => x"00002c28",
2830 => x"00002c30",
2831 => x"00002c30",
2832 => x"00002c38",
2833 => x"00002c38",
2834 => x"00002c40",
2835 => x"00002c40",
2836 => x"00002c48",
2837 => x"00002c48",
2838 => x"00002c50",
2839 => x"00002c50",
2840 => x"00002c58",
2841 => x"00002c58",
2842 => x"00002c60",
2843 => x"00002c60",
2844 => x"00002c68",
2845 => x"00002c68",
2846 => x"00002c70",
2847 => x"00002c70",
2848 => x"00002c78",
2849 => x"00002c78",
2850 => x"00002c80",
2851 => x"00002c80",
2852 => x"00002c88",
2853 => x"00002c88",
2854 => x"00002c90",
2855 => x"00002c90",
2856 => x"00002c98",
2857 => x"00002c98",
2858 => x"00002ca0",
2859 => x"00002ca0",
2860 => x"00002ca8",
2861 => x"00002ca8",
2862 => x"00002cb0",
2863 => x"00002cb0",
2864 => x"00002cb8",
2865 => x"00002cb8",
2866 => x"00002cc0",
2867 => x"00002cc0",
2868 => x"00002cc8",
2869 => x"00002cc8",
2870 => x"00002cd0",
2871 => x"00002cd0",
2872 => x"00002cd8",
2873 => x"00002cd8",
2874 => x"00002ce0",
2875 => x"00002ce0",
2876 => x"00002ce8",
2877 => x"00002ce8",
2878 => x"00002cf0",
2879 => x"00002cf0",
2880 => x"00002cf8",
2881 => x"00002cf8",
2882 => x"00002d00",
2883 => x"00002d00",
2884 => x"00002d08",
2885 => x"00002d08",
2886 => x"00002d10",
2887 => x"00002d10",
2888 => x"00002d18",
2889 => x"00002d18",
2890 => x"00002d20",
2891 => x"00002d20",
2892 => x"00002d28",
2893 => x"00002d28",
2894 => x"00002d30",
2895 => x"00002d30",
2896 => x"00002d38",
2897 => x"00002d38",
2898 => x"00002d40",
2899 => x"00002d40",
2900 => x"00002d48",
2901 => x"00002d48",
2902 => x"00002d50",
2903 => x"00002d50",
2904 => x"00002d58",
2905 => x"00002d58",
2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002660",
2965 => x"ffffffff",
2966 => x"00000000",
2967 => x"ffffffff",
2968 => x"00000000",
2969 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | b81ef5889e8c2f6df2dd91ce758aa6ad | 0.534444 | 2.386773 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/clock/clock.vhd | 1 | 6,329 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____32.500______0.000______50.0______815.385____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
end xilinx;
| gpl-3.0 | 2da4b5d11c72f7f25156afd2e873a4c8 | 0.556644 | 4.285037 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/ram_xilinx.vhd | 1 | 23,423 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM for Spartan 3 Xilinx FPGA
--
-- Compile the MIPS C and assembly code into "text.exe".
-- Run convert.exe to change "text.exe" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "run_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- corectly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
begin
RAMB16_S9_inst0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(31 downto 24),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(3));
RAMB16_S9_inst1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(23 downto 16),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(2));
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(15 downto 8),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(1));
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(7 downto 0),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(0));
end; --architecture logic
| gpl-3.0 | ff250f79545f313ab8be4d47af6a78bd | 0.845793 | 7.207077 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/synth/sin_taylor_series_ap_sitodp_4_no_dsp_32.vhd | 4 | 12,554 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch : ARCHITECTURE IS "sin_taylor_series_ap_sitodp_4_no_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "sin_taylor_series_ap_sitodp_4_no_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=1,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=0,C_B_WIDTH=32,C_B_FRACTION_WIDTH=0,C_C_WIDTH=32,C_C_FRACTION_WIDTH=0,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_" &
"THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
| mit | f655f8331e1d02f956eea5acfddeff1b | 0.649753 | 3.002631 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05400_bad.vhd | 1 | 2,826 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05400_bad.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of internal tristate: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05400_bad is
port (
i_A : in std_logic_vector(3 downto 0); -- Input data of tristate block
i_OE : in std_logic_vector(3 downto 0); -- Enable vector of tristate buffers
o_B : out std_logic -- Single module output
);
end STD_05400_bad;
architecture Behavioral of STD_05400_bad is
begin
-- Assign output with Z or an input value depending on enable signals
o_B <= i_A(3) when (i_OE(3)='1') else 'Z';
o_B <= i_A(2) when (i_OE(2)='1') else 'Z';
o_B <= i_A(1) when (i_OE(1)='1') else 'Z';
o_B <= i_A(0) when (i_OE(0)='1') else 'Z';
end Behavioral;
--CODE | gpl-3.0 | fd797c0188106fa2cfb3026efec6f473 | 0.485492 | 4.361111 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/timer.vhdl | 1 | 4,770 | ------------------------------------------------------------------------------
---- ----
---- 64 bits clock counter ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a peripheral used by the PHI I/O layout. It just counts the ----
---- elapsed number of clocks. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Timer(Behave) (Entity and architecture) ----
---- File name: timer.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end entity Timer;
architecture Behave of Timer is
signal sample : std_logic;
signal reset : std_logic;
signal cnt : unsigned(63 downto 0);
signal cnt_smp : unsigned(63 downto 0);
begin
reset <= '1' when (we_i='1' and data_i(0)='1') else '0';
sample <= '1' when (we_i='1' and data_i(1)='1') else '0';
-- Carry generation
do_timer:
process (clk_i)
begin
if rising_edge(clk_i) then
if reset_i='1' or reset='1' then
cnt <= (others => '0');
cnt_smp <= (others => '0');
else
cnt <= cnt+1;
if sample='1' then
-- report "sampling" severity failure;
cnt_smp <= cnt;
end if;
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process do_timer;
data_o <= cnt_smp(31 downto 0) when to_01(addr_i)="0" else
cnt_smp(63 downto 32);
end architecture Behave; -- Entity: Timer
| bsd-3-clause | 26f392f7078915e0729cecd1604952c6 | 0.287212 | 5.592028 | false | false | false | false |
freecores/lq057q3dc02 | design/image_gen_bram_red.vhd | 1 | 235,863 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: J.40
-- \ \ Application: netgen
-- / / Filename: image_gen_bram_red.vhd
-- /___/ /\ Timestamp: Thu Nov 06 16:30:20 2008
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_red.ngc D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_red.vhd
-- Device : 2vp30ff896-7
-- Input file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_red.ngc
-- Output file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_red.vhd
-- # of Entities : 1
-- Design Name : image_gen_bram_red
-- Xilinx : C:\Xilinx\ISE_9_2
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synopsys translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity image_gen_bram_red is
port (
clka : in STD_LOGIC := 'X';
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
douta : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end image_gen_bram_red;
architecture STRUCTURE of image_gen_bram_red is
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena13 : STD_LOGIC;
signal BU2_N18 : STD_LOGIC;
signal BU2_N16 : STD_LOGIC;
signal BU2_N14 : STD_LOGIC;
signal BU2_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N13 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta25 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta24 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta27 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta26 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta20 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta19 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta22 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta21 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta16 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta15 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta18 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta17 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N1 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta1 : STD_LOGIC;
signal BU2_N1 : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal addra_6 : STD_LOGIC_VECTOR ( 16 downto 0 );
signal douta_7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta13 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta14 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta23 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
addra_6(16) <= addra(16);
addra_6(15) <= addra(15);
addra_6(14) <= addra(14);
addra_6(13) <= addra(13);
addra_6(12) <= addra(12);
addra_6(11) <= addra(11);
addra_6(10) <= addra(10);
addra_6(9) <= addra(9);
addra_6(8) <= addra(8);
addra_6(7) <= addra(7);
addra_6(6) <= addra(6);
addra_6(5) <= addra(5);
addra_6(4) <= addra(4);
addra_6(3) <= addra(3);
addra_6(2) <= addra(2);
addra_6(1) <= addra(1);
addra_6(0) <= addra(0);
douta(5) <= douta_7(5);
douta(4) <= douta_7(4);
douta(3) <= douta_7(3);
douta(2) <= douta_7(2);
douta(1) <= douta_7(1);
douta(0) <= douta_7(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"7FFF3EDEFFFFEF6BFF9E7F70D97FF5F81F5EFC7FFFDF866FFFFFFFFFFFFFFFFF",
INIT_02 => X"DEDE737BFEFFF0F9C35EFB7E4FCF87FFC31E27ECFFFFC3A42313C7B8DB12BFFF",
INIT_03 => X"FBDFF53E979BF2FDD96949963FF7DBCA3D2C77EAE3D63017FBF33FAF7E178761",
INIT_04 => X"A4C18795F79FF02EEC38716103C7BD8F3AF327977EE7CBFB968FC47C3FF5F8F7",
INIT_05 => X"5821B26F3BE712A326C237FCF7CDF9E753FFCBFF53EDF9EFFF5EEDCEAB9BEDFF",
INIT_06 => X"FC2EDFFF1CE3FCFAA7FDE2FF87EBF9FBFFFCF30E5033E15DD64D230D7F3FCF18",
INIT_07 => X"73F8F2FF9FE4FA5BF9FCF93FDF51B3DDD2F340DBF9D7FF0BDF008F6DFFE3FBE5",
INIT_08 => X"F7FEF03FFF98F7BFF7826262F73D799698FE168ED3E1FFF2F137FFFAFFFFCAFB",
INIT_09 => X"C04DEB08EFAD7896087E674FFCBA7BFF781DFE21FCFFC5FCFFA8E73EB9F7F54B",
INIT_0A => X"837122A5CD3DE6DF258FFAB34E3951CFF71FEFC23EE6790B73FDFFFFFFFFFFDF",
INIT_0B => X"9F47F1826C10D15BCE3C6F08FDEF7F8BB1FDFFFFFFD67F9DEEEEDA3AF974241F",
INIT_0C => X"FEBD573FFE7E7FB7B97DF7FFEBFEFFFFCDE9B65A41C6669BDFCF5BA7BFBFDAEF",
INIT_0D => X"BC3EC7FF1F9E7FFFAB8F389EFD4346D9587EFCAF2FD7DFDF633D70D79F7F59FF",
INIT_0E => X"BE38FD28475741C9EF3E184FA5E7FBF5A0AD52A9CB9FD5E7FDFCFA07FD7FBFDF",
INIT_0F => X"567EE81F74F53BFD48E707ADA7B5D31F7BF9E8E0E9FF6FEE7FBE0FFF2F5C7B73",
INIT_10 => X"D8F4D8BD7709E56F8DFD55FC6790EFFE7F7E7FFFEFBFFB3F8D1EF9EE1CD675DB",
INIT_11 => X"F3F9ADFC57FFEDFE7F5FFFFFEFDFFA7F817E262A5AB3EBD6360016077FFC9EC4",
INIT_12 => X"7EBFFFFFBDB7F7FF8FAA5F4690E2FFC3EC80DF3CFFFF13F47DEFDD3B8EF765F3",
INIT_13 => X"98D64309F0BDF7FE3C7F7F98F43DDA89FEF74F3E77FB35386DF1FFFFCFFFC8FF",
INIT_14 => X"3D5B7FFD33CF01E85D27DB7F3DF7FD1B7FE07FDFE6BEDFEBFF5FF8FE5E19FBE3",
INIT_15 => X"9F90F00ABBEBF5FEDFB7CB5BE7F9FFD7F377F0F93BBCF7FBC0A14054BA63FE3C",
INIT_16 => X"A7AFF0D7D1FEDDEBFBFFF079EBF1F3DBADA31CFB6C307FBE75BAFFFF19FFFEFF",
INIT_17 => X"E7FDF0FDC7FFCFDB8F726B823A2F5E6F12FEFF81BFFF7FFFFFB84CEB03E3FEFF",
INIT_18 => X"98D0EE484E63F3A7C1FFFEB9FDF87F7FFFDEE9BE6FFFE3FBC9FFFBF3EBEEF5B7",
INIT_19 => X"C7CFFC7E7FBD77FDFE98196C4BF1EDFDE7FC71F5567BF0BFFEF8F1FFDF3FBFDB",
INIT_1A => X"FFDFDDABD9FC75F1717FF88F3EDFE97FE9FD77FCFEA7DFEBA0B7AD7C6532C7E3",
INIT_1B => X"FFA9FD6F3FFFFF7FFDBE7FF7FFAF5FEB9FFF944BD27AAFFDF287FE7FFAD5B3F8",
INIT_1C => X"FBFD7FFFFBDBFFFFB52668D61F5A47EE3E67FF9EF8EAEFF83FFE5F3AECF17BE4",
INIT_1D => X"B613251C7D4C69217E47FF8275FDFDF8E65F5F8CF47DE3CBFF8B5F4FFF7BF73C",
INIT_1E => X"FF75FFE63AFFFFFDF4379FFC5C39EBE79C07DFFE3FFFE7BFFFED7FFFC3FEFFFB",
INIT_1F => X"3EB7CF7507BCE3FFE93F1FFC773DDFFFF3EEFFEBA7FFF9FBAD4F58306A28377F",
INIT_20 => X"E2FD7FDFFC7F97FE6BFEDFD5E3F7FB97AECFE41639293FFFB71A9FCEDD1E7E3F",
INIT_21 => X"E1FFEFB7FFF5F9C7EF8F839B6170FA0B43A41F1C1FCFDD7FDEB1F39E14AF7FDF",
INIT_22 => X"FFF3E45B6410A84F863A2E389FE7FEFC7F3CF1CF5556E3AFF3BF3FDFEB7FCFCD",
INIT_23 => X"BCD915A8EFEFBFFC8E9E7DFFB1EFEBFE67E9BB7B2DFFDFD7F7FB976BFFFFE5EF",
INIT_24 => X"BE1E3FFF9A77E3F9258FF77D66E29EE78F23D7DFFC7BEFEFBFFFDBD8374203EC",
INIT_25 => X"F4BFFF4FE976AEFB7E4FD7FEBD6FD1EF97FFF8539A5DEF20FEFC49F6F3F7EFF8",
INIT_26 => X"FDFD7FFE7D7FDBEFB3FC3A23AA328EC551B12B00FDF8BFD0BE97DFFFDB145BCB",
INIT_27 => X"AC3EFD41DBA0086896D198F9F1FE1FD637FD93FFE0BBEFFFFF7F1715FD1F8AE7",
INIT_28 => X"7FF8FED77FFFC3F2FE8FFDFEF85E2FBFFF3E3D99FF3F7FCF7DFC9FFF3FFF55EF",
INIT_29 => X"BD7FE05ED4258FFFFFBC9B86FE7D1FDEFDFCFEEBBEF5DB3FAC1FFF41EE26D582",
INIT_2A => X"FEFCFA73F27C9FEE9FFFFCEBBF0C7E3DAB5FFF67777F402F3DFE4182BABFEE79",
INIT_2B => X"F7FD9CFDBF1DFFEFBC1FFFC77F52D82A7FE96BA917EFBE7D9AF3EC1EEE65187F",
INIT_2C => X"A1209FC79FF6A1C53DBD6FF461FFDF7F80F3EF9FF7376AFFE5FE3FF713FEFDEF",
INIT_2D => X"3D5D4787AFE7DF9FFFF9CFC79F63FDE720F3BE3FB5FD395FE7BE30F3F156778F",
INIT_2E => X"339E6FF3B7BDCFE8976CBE31BAFF797FEAFF59F7FDB077DFD06B58E7EFF983BE",
INIT_2F => X"FBD47FBAFE63F9C64EBD7FFBFE797FDBC7341D3FFFFFBC9276BE753BA9EF32AE",
INIT_30 => X"BF1DFFFDFE79FDF3FFDBCD6F7E7E02B3FABFFDAF2C3D7C9FF3BE4BFBFFB8BFD9",
INIT_31 => X"F847111CFFAFA229EF7FFD6E5DFFB1FBE3FC7DFFE68C3FCFFB97BA7FBF7A2DD0",
INIT_32 => X"EE7CFC5FFFF7F7FBFBA7F2FFFF3A0F1FFC4F7EFF3DE8A7DFFFDFFAFCCE7CFBFB",
INIT_33 => X"B1BFD35F3FF9DCFFFCEAEFFECDFF73ED7FFFF9FEFCF1FAF3CD979CE91751377F",
INIT_34 => X"E420F77FDFD46BE47EFFF97FFD0BFCFDBEC369CAACFF1FFCE0F0DE07F3C3FEE1",
INIT_35 => X"BEA6FD7BF6DFDFF9F5BDE63279CFFFF871741F1073E3FFF6FCF7BF93B7FEE4FF",
INIT_36 => X"EFA5DE434717FF58F97DFF81F9F3EF7BB6BBBF9BD5FE187F2EF7CAFFEFAC4BEE",
INIT_37 => X"FCFDFFD8BF3FFF59F4F03EA7FEFEEAF55CC2DE3FF7CB97E7DF7F5FFB62CFFFFD",
INIT_38 => X"FD7D1FF9FEFED55881F99A17EBB61FF79E3F8FF970463EF9B597288319FBFFDE",
INIT_39 => X"AB3D535B85621FEFCC5FFE1DF6867DFDC06F7C8C44BFFF3FF1FFFFF67F3FEF58",
INIT_3A => X"EE3FDF3D660EF9F7FC5CE1D1DE127C0F30FF79797FFCFFFFFCF9E5C37F7CC17D",
INIT_3B => X"DDC23EE6B7E4344EF9FC7ABDAFFE1F1F9F7DF302FFF0EFEAE3040F5DBEC20FF7",
INIT_3C => X"FFFD647F7FAF7FA7DE7DE0FDAFF468F36C50907DFF1CBFCFFFEFAF3FF7FFFFA7",
INIT_3D => X"DE4BFCF67DBA822121FDE17DD720BFFFEFF7BFFCFB1FFF8B8E334DB1C7A715DF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FC7D59FFD365BF7FED9BCF7FE87FFFEBD91BEEDDF02352BB5EFECC7ECFDFBFF7",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BF0BFEFD83EBFFC5DF4023BE7F6D5892BF473D3F6FFEBFCF8FECF15A3639ABF8"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"E61059FE7FBFB67C63A7DEEFF7FBFD828F9BF7C3A7B34DEE6A300FFEF975BF1F",
INIT_01 => X"4BF0DF39FFFA3EC11FFEF1CF2E20E3ECB71A0FFE7CEDBF1F594FBFFFC7EC3E1F",
INIT_02 => X"3FFEEAD8D1DD9FF47E355FFCBF25FF7FFDF79F7F03ECEDB5E40F6EE4FFFF1C7F",
INIT_03 => X"A84EF7FDAF76FFFFFB5F7EBF35FEFDFFED287FFD9FFFF8D6903FEDC4F7F8BFFB",
INIT_04 => X"96FE7E8F5BD737FFC529FF6DF7DFFE3B539FE2FAFEF73CFF3DBCE466F66DD3FA",
INIT_05 => X"9C4BBFFFE7FADC73A1FFB1F9DDB77EFFBC1EB3B539C5FAF509CB33FCE586FFFF",
INIT_06 => X"F2CFFCFF6FBF5EFBFC0FD0BFB2F749EFC60B98F5425EFF7FB7EDFFCE9DC238F7",
INIT_07 => X"FFCF4F88D432FDFB229F640FDA96FF5FB7E3FF0E7FCFFDE3D61BD9F7EEE7AF00",
INIT_08 => X"9B99B417B9AEFF8FFEF0EF1F43FFFD33FCC0B9137ABFC124E4EEFF1FBFAF25F2",
INIT_09 => X"FC7EC79ED3FFFD4BF86CC5EA445FBBFC9B66FF979FF929F03E1F703230FDA7C1",
INIT_0A => X"CFF761AE5C6C33FED8883E3F5DFCE7FC7FBFFDF54FB1EEACA9A8580FCCBEFF8F",
INIT_0B => X"F95CBBEEA7F7EF7DFFF6A7F01F9B190A0B00EEDF059DFFDFF93DC7BB5FBFFD3F",
INIT_0C => X"7FF6F666D855658199149F399341FFDCDDFFC7F8C73E527FB7B78C82FDED77BF",
INIT_0D => X"9A96FFF49DDDFF9DB3F3F7FE3FDD8BFF9394AC7FC4911603FE2CDFF5FFFF74FF",
INIT_0E => X"FCDFCF7E5E3FE0FFF8303F6E2523CE379F0FA1F8FFDFA46F7FFFFCA04A2E741A",
INIT_0F => X"CD2F82A9697D373F97A00EFEFF4F89CCFC1FFD90198115FFA45B7FF07B5CFF8F",
INIT_10 => X"FFE57D7F7E6FF85FB8B766261FBBA56D8B6EFFD23534FCFFD47FDF597FFBF9BF",
INIT_11 => X"3BD71CDDAF94C2F719ABFDEFF8EEF8FFD26F9F4E97EFC7FD8382E7FCF78ECC7F",
INIT_12 => X"24ACF07FFE6FFFFE6E3F9FEB3FE71DFF9432F02621139E3AFFFE49BFFE1FEEC9",
INIT_13 => X"BFFE1FE073271FFFA7E57DAAC2D334BCEFFF286FFFFFF87F1BC6CD665928E258",
INIT_14 => X"FE5C8552853AD2BFD17FFF51FFF7FF874DA21D2E710A6B0DCA78EF7FF0F7FFFE",
INIT_15 => X"D1FDFEDFFDF89FF2A0F30A915296E454051ACE7FFAFBFFFD3FF80D2DFCBCBFFB",
INIT_16 => X"F6C784B34685C7D3429C617FC6FBFFFD7FEC1B3571FDFFF185A8859195EF5D73",
INIT_17 => X"2EB907FDAEF7FFFFFFE67A78657DFFD7D07319CDFE92CCDFEE7BFFE1DFFEDF45",
INIT_18 => X"D930FBD471FD7587CA3A81E1A168377FFFF0FFFB0FB80FA42C4D18FA1728C922",
INIT_19 => X"89397EE33D476CFFFFFCFCFEC3F79BFF8C1DFFB68A21FAA6D3BFD7F7DBF7FFFD",
INIT_1A => X"FFFCFFFFFFFFFFE9AFADE9AFBCEF7D09A8DFB8F585E7FFF767FFF7243C3E9347",
INIT_1B => X"CFFFDF6280D9757F848525F150EBFFD967FFFF9D7F72FF5FC5FD1A1A0BEEA1FF",
INIT_1C => X"791C6DB705F3FFC78FFFFEC4FF79FF7FD39E0E917FFF3D6BFFFFFE7DFA1FF3F6",
INIT_1D => X"FFFFFD1DFF13FEB9AF3724AAFF029A873FFBF3E3FB6FFD3FFDFFE95982BCF517",
INIT_1E => X"B3F12C18FF8672073FF3E417FFC5FEDC0CFFFF91896E7B0C010A7DBF24FFFFF3",
INIT_1F => X"5FFAF42FFFF2FFCFCD7FF9964354BBF8DE4F5E3F07FCFF7EFFFF7ED4BF8FFDFB",
INIT_20 => X"D93FF9E74C7852911F3B1FBF1FFDFFFFFFFFFB397FDEFDF7C1FE170780964A6D",
INIT_21 => X"D4411E3FCFFE7FE7FFFFAF7DEFBF7AABFC58351BFF6F745C6FFFF97F9FF72FFF",
INIT_22 => X"FF8F7DDFEFBEBFEFC4813B66416856607BBF3FFEDF7EA97FE5BFB9E7B1B70F6A",
INIT_23 => X"FA4EB2D62F85688FCDFFFFFF71FFD77F7A6C3DFCDBC901F1B48FBCFCFFFFFF9C",
INIT_24 => X"2CFFFE1CE9FFD0FB1C5DFCE6A1B743A361A5FDFF7BFEFFFFFFD9FC25BF549F21",
INIT_25 => X"EE4EFDC5D4969851E984FFFB4EFFFFFFFF99E667BFA1FFCF8E6298CE5B582AD1",
INIT_26 => X"1B8A5BFE8EFFFFFFFF19E327FFFFFCC3DEA828814AA4475EE2A1FDEEF9FCE8F6",
INIT_27 => X"FF79AFAFFFFFC67380CCCB7CB8FA82B94976624FE1FCFFA45E46FDDBAA003CFD",
INIT_28 => X"84377CE62C349886C9FAEBFF97FC5EE2FF47FF9F5360AF83AB93E39A36FE3FFF",
INIT_29 => X"06FAD7FFBFFEEF15BFCA5FFFCD1410F4ACD9FD1272FD01FFFFFFBCAFFFFFF9FF",
INIT_2A => X"4FD859FFC81C3D0D0241FFED70FF86FFFF3FCAA7F7FE1AFD92E04B3244F1DA03",
INIT_2B => X"BAA7F587D8F6557FF87FE627F7FCFBF9BE21003370CBA49AFFE5C7CFFFCF792E",
INIT_2C => X"F0FFA777F87C1F7F9043041057A7F83CFFC7E7CFFF07E1D197F64A7F9983042D",
INIT_2D => X"E59208CD1B0DCB1073E7F381DFA7F7FDB3F589BF0FA26C8DC2E7FE254BED443F",
INIT_2E => X"6BEE2F9BC7B7F8BF2FF734BD747F3332E20C760945C4E23FF07F51AFF3A5FDFD",
INIT_2F => X"C3F3C238499A9591EA0CFE7A7FC4B2BFF0FD4BF600EFF439944D83B79C6562B9",
INIT_30 => X"FCF378B29F950EBFF0FCE4E886DFBFC3B1E21F61914F7E9DA0C7004794FFFB7F",
INIT_31 => X"FFF298F13C1FDFF7CD0F0E302F3172554DC3AFBC0BFFFDFFED1992E5569C7AEE",
INIT_32 => X"8D6E8C979FCE9FFCFD7BFFE9DBFFBF87E0199E566C035FADB96B66E6AFB2C9BF",
INIT_33 => X"5EBFBFF315CFFFFE5FD60AA89A4E85632F7C86C877AAD9BFFFFE43F61F1FFFBF",
INIT_34 => X"1FF36D446E846FCA3637B3C897DC89BFFFBB77E35FFFFF0FE6A1786334606793",
INIT_35 => X"C399B6457FE4DCBFFCC8A67BFFE7017FEC9F7C22FEE3FAC34F9911FA59CDFFBF",
INIT_36 => X"FE579FABFFFF9EFBCDE47F52824F40E26AB1CBEA0D763FEF3FD3EFE8A4612DEE",
INIT_37 => X"806B1C07C5398CC3AD6AF6FDBD417F0FFFB506CE782FE77052B674AB874E1D7F",
INIT_38 => X"DA3D31C404A80FB7FFFF6CD304513D0A5A2022DAC7AFB81E7EA1F9FFFFFECF8F",
INIT_39 => X"FFF3A086273B6F0B8B1F6AC373E29AC0BEDEABFFFFFE5FC7B6EF8107D0F69D6B",
INIT_3A => X"7B33414693A733C211D9B3FFFFFFE7FFA8D1FE002D12CA7829E3EFBD933DBDCB",
INIT_3B => X"AB3FCFFFFFFFDBFDCD87F8FFB005731FFF2BFFB44FD52244F0F37350128BA40D",
INIT_3C => X"FFCB80EB5773671FFFFFBFBB401EE2A54FF6DA3138BD6C575EA45245883F3FA0",
INIT_3D => X"FFFFFFBC918FE233897DFBCF5396B904BB55F39DB4B7573E79FD8FFFFFF1F2FF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"A5FDFA3978D9751F9491C82DFBCB970F15FE3FFFFFDEE5FDAB53D30826C4FFDF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"6AB4228FF9EC028B07FFFFFFFF9FE6FFD3CA4F3F9DD1FFF5FFFFC1FE9F5C592C"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"43FFFFFFFF83EB3FEE9500E1A48FFFFA0F3FEFFFFFA787729FEA7CD3A0749A3B",
INIT_01 => X"D8CA7FC0DD2F47DC78EFE7BFFFE9A2706FE6ED4BEBCC168FB4760BCAEB386BA7",
INIT_02 => X"9FE3FFF0F7FADBB80850DF460A1245B92238DC5CB5A84252467FFFFFF87FFB4F",
INIT_03 => X"9E6EFF75C730D3F07AA267B2FBB8A2E7A01FFFFFFFFF3DFF83B2B11D26F7087F",
INIT_04 => X"E0E6A2209C439687F21FFFFE0FFF3F5DA4F1F3BCEAFE63FFFC0FFCF481FFEF1A",
INIT_05 => X"B43FF03F1FFF3FFDC0CF3D5C3897FFFFFFFFEDF8FF1FF644CB1AFD6C4B2D640F",
INIT_06 => X"B9610C8259BEFFFFFFFFEFFFFFFFC42CE97E3FE309D0E7EC69D086B37AF2FB2D",
INIT_07 => X"3FF3FFFEFFFFCD830F9B0FE486096FC70B8B8A302D7135F0707FC003FFFF9FFD",
INIT_08 => X"85EBE75FE4ADE08E386AD7DAC7FD8E2F67FF82F7FFFFFFF9843EF75C263DFFFE",
INIT_09 => X"73AFD20E40D8787B80FF3337FFFFFFC1A3FE85BCFA7FFFFFFFFCFFFFFF7F88DF",
INIT_0A => X"4FFE48EFFFFFFF97D1E1B4715D7F40FFFFFF7F67FC1F7F3CE86D30B38E7F32E7",
INIT_0B => X"913E6C17EE3DFFFEDF1FFFAFF9F1FF60996690BB922B2E403ED99691A37CD015",
INIT_0C => X"76EF3FFFFA13FDE17FF8AF754BFA195A655C73905870BADB8FC2AE6FFC1FFC21",
INIT_0D => X"761C69FDF58DF52AB0D9BCFC5F11D7BFC081369FF07D7AF3BA3C9C1377E27FFB",
INIT_0E => X"2785BEE96F42041A59281AFF43FE3FFDD0BDF487FE87219317D8DEFFF66FF1EF",
INIT_0F => X"ED69CD3EE7F15FF1D3EA57DFFEAFC307FF7E25006B9BFFFFFCD912F6DDF3C4FB",
INIT_10 => X"DE87FF9FFC5F601FFE6458073C91FCFFBFABF43FF53A52DD2D4BA2E5C697286D",
INIT_11 => X"F9FF8214B04CFC3FB9DD0538D92C692F345073622768854E6937467ECFF1DDA3",
INIT_12 => X"8A1A04673DE5817700A412C3E18BAE0CA5CB347F7FED5DB39E60FFBA7F505FAF",
INIT_13 => X"5EF1FD716D7F83D21F6E28FFF9339E0983637FEA97FB9DABCCFFFCFFFFFDFC1F",
INIT_14 => X"539327FFF71BEE5D9156FBFA40EA188D086E9FFFCD7FFDCFFA7978263C59B120",
INIT_15 => X"B407EA52A5E16C88BF77FFE8597FFDEFE74870321A7DE0F608F20108ED1D96ED",
INIT_16 => X"C6FFFFFF03FFA4ED4379FB4CAFFFAAF8A1A1D916DA8F494B0F489FFDF7A04209",
INIT_17 => X"725D7FA001FAA83DA48723C3DBBFB85F0A437FFFF806B6D5B7524D041B92BE26",
INIT_18 => X"2B96AD79C1B31E544984FFFFBA7E44F1BEE7E147229B0A1225FFFDFF9FFFFFE1",
INIT_19 => X"703FFFFE548B95CDFD5BC0E113E11B6383FFE3FFFF80BFFDA94004738242DDAA",
INIT_1A => X"FA32F6ED7D1761EEFFFFFFFFFF8EFF797ACC6441788ECFC61B2E549F01790A67",
INIT_1B => X"FFBFFF4BFFFFFDFD808FB0EFB28A51A82CA2E99239453D57877B3FFF629C44BF",
INIT_1C => X"BE979B004BB00AAF194682EE8ECC0797F1B01FFFF288525DB538CBAD5596627F",
INIT_1D => X"B533846385E0226AA60F1FFCD221CF2BF1AD03F44463EFFFC73FFFEEFFFFB833",
INIT_1E => X"718F807CADBB2AC7BCEA917F0CA8D9FE2FF0FFDF8FFE10C3FDAB847F7A049ECF",
INIT_1F => X"F47B5BF337D875F35FE7E7FFFFFEF31F7035412002FE7C1F657A1512C2DE2B9B",
INIT_20 => X"BFDE9B3FE389B7F79F869EB5B156AB1912B887F66279D130923FD31D80D2BD2F",
INIT_21 => X"6F2C3C5ABADD9D4FC9BCA6F1FFE3D87D1B1957883C4ABC9BF170B495E9553FF4",
INIT_22 => X"AE07EFBFF3706AB9C736C58E9404FFC3DD8A4CF44F5FFFFD7FBDEE4FFB8257F7",
INIT_23 => X"B26D458F599C4B1BE38BFB84F3FFF6FD7FEFFF9FDAC13FC7FEF7247C67C64FF3",
INIT_24 => X"83423480E7FF6FFCFFFFFEE7FF0DFFE3FB7DD52B574F4A5E446EC05FDACCF586",
INIT_25 => X"8B37FF87FBBF7FE3F445FD3B0EC482C86A366258829061D76CE08AE748F70335",
INIT_26 => X"EEFDBDD5EDB513B577D9299CAAD58DE7DCF74415C279A7CBD11A4F722F0FFFFF",
INIT_27 => X"C3B7CC7968BE406E71D3EE56587789A1FAD3F4BD3C7FC07F2BF7F3EFE4F1DFFF",
INIT_28 => X"2FB6380E44041D71C851387CFFEFD2438FFFEEF75BFAAFFFC7E03645E0A1E280",
INIT_29 => X"E12FC50FD9F3224FFEFFF543CFF7CC7F6F93A6AA6366797FDC1FFDE3C7F13E76",
INIT_2A => X"FC7E53E68F87C7FE7FB295CF19EE7B2B93EFF781DAF6FF1038A183F9C7FF2153",
INIT_2B => X"FFFB717B8D7002F17C9FFFEE23E1FCC80CA32B0FFFFFCBBF99A33BB7AFEB2D6D",
INIT_2C => X"62BD31467FFFE5289B1575FC1FFFA47FCA13E7FAFFBDD2ABC3AA68FAEA7FEE3D",
INIT_2D => X"F05F17FFDF07643F83814F4EFC8A404D219B8978E17FF9FFFF2D780B6ABC9C2F",
INIT_2E => X"A38656057E93165167F2FA7163FDF6F9FFE1E157A8DF518471200915FE1FD42A",
INIT_2F => X"88A3E6926FFFFFEFFE9A79D7DF67BAFBBF9EC3C7FE165A1D01434BFFDF733E7F",
INIT_30 => X"FE4DFE1EF3B781A3BFAF73FEFF50D07C8A347EFFDF77FF7FB700E67813B5727A",
INIT_31 => X"873B97BE712184E230A8FD17BF77FFF9892378FAE047D47AAB87524DF3FFFFDF",
INIT_32 => X"E7A91D33FF73FFFFFB4089FA7F1C697ED557EE3BB7FC0F67FDAFC529A1A43E7D",
INIT_33 => X"EF1CF7EA6FFAA0085AEF7E7F77EC8F2D612FE6CAFEFE6613C0280EF35D5AB7F8",
INIT_34 => X"BD09FFFF9F850C38FD4ED4411CF6736474765C477160960565FEDAFBFD79BFFF",
INIT_35 => X"ECA314736398CD46D883BE7E929AE8267F6E2C7E7562CFFDCDDF7F20D718CC17",
INIT_36 => X"15C8178FC7F85C795BE4F432EB4859FBC6374E8E24083C95DFE7FC3C5FBEFE3E",
INIT_37 => X"BE583A518CECDAE59EF4DEFBDEAFF1A6C80BFFFEFFFC72F3E8A1AD8B82D26935",
INIT_38 => X"B2133D6F246DF8A05FDFFFFFFEFFF1EBE7F944E0351110E5D526BE6E414FD6E7",
INIT_39 => X"97DFFFFFC1FFF78FF7F1D5C9D1C1EFF495D8A67D9574AFEABF9954A3D022A533",
INIT_3A => X"FFF599D31585FCEC0AE39A9B6138F9919AA2E0B6CF508219C7BF4EEC5471EE09",
INIT_3B => X"BAFEBD679517FDB7F0A84DF078662235A8A64454C21DC41D387F7FFFEE7FF7BF",
INIT_3C => X"05745565F438B2A3912FB85F2A7DDE79F37B1FFDE57E27FFFFFFD8EF51C98BFE",
INIT_3D => X"81CBB09C95BFB26C7E6FCFFB5DFD2FFF7FFD719017F9D6F6E486BEFFD750FFFC",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFF31FF87DF959FF7F7FD8E25B8D435D88CAB7BFCA9171E55D6747E47589E711",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFC65AEED8F8DD09AA1B793F99BB3FEBC36021D118D907B98A59291879D57CF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"4264CBDFC65E326D06E095149942DA63C8FE9CF3DFFD982FBB07BFF87FE9BFFE",
INIT_01 => X"410DDC78711C591FA40A3D04C03D16063DEFFFF96BC479FFFFFE7D140B7652A3",
INIT_02 => X"8F9EC28267FAD5BAB1FFFFFFFFF4F6C7FFBD545704FE7832EDDA10EF9F29F8FB",
INIT_03 => X"D3FFFF3FFFFCFB37FEBEC5F3DBF3EC9435BEE2E38FB93CC7208F198C4FF2DEA3",
INIT_04 => X"FDBECBA86F0491F4263CEB2EE9A00760F5D7135953DC9B21F83873CBB93ACF7B",
INIT_05 => X"58833F76A2A4ADCD1370381B2FEB35D79860BE44D4AB90F7CBF87C1FF8E5BF0F",
INIT_06 => X"5A1D03A6A427306FFE8830516B2C6FFBF1F93A9F77F7FF3EFDB92BE78BF2897F",
INIT_07 => X"9D83795EF0C3BFDDEFFB3C0FE48FFE3CFEB3BFB1DEAD2ED95F0827F6A0431A31",
INIT_08 => X"F3FFBBDFC5BF7F1DD7333B40EECCD3BD62C4AF6ADFC26687B405A2E33663D09F",
INIT_09 => X"F7EFF31D8D4D5EBD4C5F7BF9EAADE1C9FC2C88DCF0F3C72BF220762404B37FFF",
INIT_0A => X"E15791EB9C0013F893E4AFA10F627CF1B2C3F026B24EFAFDF3C973DFD1BEFFC7",
INIT_0B => X"9B6203A0F19759F5AFA711561760F97EBFD7F7CF015FFFFFF7CBE79DE95C7C7A",
INIT_0C => X"ADF315FE9887F7BFBAB7E77D10DFFFFFF7DFDF8C89C9FBFD72E1B46F6A17B3F1",
INIT_0D => X"5B3F9AB81473FFFFD7CFDFFECBEE1DFD8CED2210E0BA39E7E5B3561ECB67F499",
INIT_0E => X"CFF3D7DDAFC853F932DC995AEC31E9F6A02253CD47400EC3AF1D788F4677F5FF",
INIT_0F => X"58E5E71AD85553FF5F6F9D6FD5EA5975B4A793BCFBD7AEFFED838BFB13A7FFFF",
INIT_10 => X"3EEB06230F96938DEE78AA7D7CD7FFBFCB7CEBF1B17FFFFFCF97878DDFC6CFF7",
INIT_11 => X"F6A53BFEFE77FFFFC697FFD6FDC5833FCFE707E7F3B5F7CBF3F3F6A1B63453DF",
INIT_12 => X"CDAFFBEB43DB6621DF0F6FBFFBDC37E790FFBD9F3E26F0FCFBFC08084F79C341",
INIT_13 => X"EFFD9FFE3F143FFFA7FF59B40D3C83F5355BFFFC9C0D7F13EB87A77FFF7BFFF9",
INIT_14 => X"9FFED5D40D7D19E9AAD4711E87EDF35B9826B9BFC3F9F4FDFD3FFDD4878E3C46",
INIT_15 => X"963A5E7087E38FDF8FA53F5FEBEC143853FFD44057BC7001FEDDBF0B3F82FEFD",
INIT_16 => X"C7B89CBFFFFE647E7A7FFFC8AF3C7FE6FFD9BE5471B0B7FF92E4254F618232F3",
INIT_17 => X"30F38CDC3E3CFF7FB73C7F95AAF68B7DF2010A62FDE60FA2C700AEA77F27DA63",
INIT_18 => X"BFBC3FA88FBDFAFFD509C86E27772B7D5CA3EE7A485294138CBA99C84F7742CB",
INIT_19 => X"C9C9F8511B8D47F4D2A1EF489BBE04E9859F1FE7CEBA79A9267F387EBF7DFEBF",
INIT_1A => X"D5E5CBF3F50F346FFA661BFE3D61A741DF7CB84A7BF9FDFFBBBD76D7E7D4E4C7",
INIT_1B => X"BC5D2AFFFEFB7BE6DFBC7E27FAE7E0FF7B7C7850CF5D9F078AD9FEB5742DB3FF",
INIT_1C => X"7F64ED29FFDFE9FFBA7C7EC0C6FC9DE767A7FF31059B3BEFD95B7805655259AB",
INIT_1D => X"FD7CFFB78E73DCE3B70AFE517F96FA7F1B277385369AAEB9F2ED1BFEF94914B8",
INIT_1E => X"DA0A3EDC990F3FF1843CB68EFC1003B191DF87837DFF021DFFECF0CCBFAFC7CF",
INIT_1F => X"460F6A9D69B41153961E9FDFFFFEC44271F80FEBFFF9E7CF77FF1B07C369C9E3",
INIT_20 => X"B7DCBFFFFC88EB16F1FD8C53F5F1B7BEFCFE7CAD1E1FF2CF76707ED045BD50F1",
INIT_21 => X"F7E45C17F9FF67BD79DF2ED7563BA1D776C73D7A3C87FCFDF90227E321CD0B2D",
INIT_22 => X"75FFB46D511589DFB917283C456B98F5BA9F6500530CBFD7B8EC7FFCFE5A2EF3",
INIT_23 => X"3F63346DD7CAC37FEC29882BCC793A0DFD9BFFFBDC9C076BF47CA4C7F7F83FBE",
INIT_24 => X"F57BB03E7844C2DDEA2B59DAF48B5A67FD727BBFFBE9773E7BAC36A5463D8DDF",
INIT_25 => X"948880D9178713BD380A452DF7D7873FE3EEF449F0F7DBD638EAC38D86DCA9A7",
INIT_26 => X"BB89ECDEA3093F3FFBAFE37CCB0BCFEF1E432A76A75C82A37D11C97BBB73A8E1",
INIT_27 => X"F3FFFCEB60EDC3FBFFE71AF3DE74513B7FE3812135B551FDE37D5B984EACFFF8",
INIT_28 => X"3FF5EA1113E4640DAFDEB3D3837CE3EBB57496D6D8ED87FC7B8E133EB74F473F",
INIT_29 => X"F7DAA0D125FFF3E586DA72D3D65FE98F2E7EE2B39FDE9FFFE79FA6278C5D87FE",
INIT_2A => X"8BDB7029C5F0DF815D8820047EA00FFFCF5EBD720D7FDCFFCE8152DC89A7875A",
INIT_2B => X"3711BBD2FF67DFCF8F3F3814641FC2FEEFA1B0D38E23BA6DEFDFFE4FFCFFFD3F",
INIT_2C => X"87FEF42C6C0B97BAEF21555E74C66BD4165FB7DA7E7FFF07A1A946149AB5DD02",
INIT_2D => X"FFC8F25BD9C39E34F1F9E12259DFFFFF98CA5752EF445F19F1D58E03FDBB27DF",
INIT_2E => X"E0FDBA7F1EDFFFFFE72D2291EEADB0BB6B66798FFAFE3FC64DF9E3A74C53C4FA",
INIT_2F => X"FDD6CA4DEB088A3698ED07BFFB183BDE8E4FF6617AA7A05FFF83F873E3012DB6",
INIT_30 => X"0BC74D7DFBFB3DDE43F3C1D9CE9BAC1BF9D0E5C7E964E3453EFED355BE3DFFFD",
INIT_31 => X"4DF3E437D5279565B7C879DDF4C1591E5ABFE9E1DC7CFFF1DA67D895659708F5",
INIT_32 => X"3ED57379FF170149CD300F18B47FF809E0C8105AF69434FC30EB16BFFB5C3ACC",
INIT_33 => X"DC2FC824B77F807FE6D60FA294D635F933E7BC5C77257ACAE4AF55C49A6B9D10",
INIT_34 => X"CAB69FADE394EDFDB6F8D53EDFD5FEFF69FF5F6BB7F26F960AEA57C9FE0E72FB",
INIT_35 => X"BD581F7F5065FCD9606502F7CA5B2A3A976AB421F96DD5CD8B47F84B6EFFFFFF",
INIT_36 => X"9FFB96EEA67C4818B79370ACF65E0FFC66F3FF06A1B8FFFFA16952D696C12BF9",
INIT_37 => X"BA3442E97F50A9B752539F891B5C7F0786372DDA3CBAAC7D16BEBFFC35BAFC07",
INIT_38 => X"A59E67F49E68FF31AA9F91EE0A33CD9C424A1FF8E64CFE43E7B9BFEF5DB50524",
INIT_39 => X"8ABF02DE9F9470D8D7718FB39489BF535FF853EE504F3E38BFBAC2E97F138F86",
INIT_3A => X"70FF2F13DF44FF3EFF1DE7B8BE73743C3FB679007FF6AC1E6A2673F2138D827D",
INIT_3B => X"3FD8857945696CDEBF41C1C37FAACA5DBAFEDFFE5597CB0FB448E07C28CE7881",
INIT_3C => X"BFF5E2BB3FEAA310A1A9C1FFA252E237C1CEFB18D132C4B59461671117ADBF7C",
INIT_3D => X"6D42B8FF8C520E6FCA65632F58924B78CED8FF9F59A9DFF4FFEC99FB8CE35C62",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"B5A4A68A76ECED73BAD5EC38D1ABCF2FFFEF47BF352812573F74B5F7E7EF01EE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"A89BFBE9E8CDD7ABE7E7FFCDD3C29C537F7060916F38D97703E04BFF9E4EB72D"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"8DF76FF0052F02993FF9CE322F3DE0E6166B137F5F39CA6DDD733570B8EF5BFA",
INIT_01 => X"FFFFA31BC6FEAA4647FDEBBFFFCF5D8391B3885201FE2870D916F198D6FBF3E3",
INIT_02 => X"2B7263BFFD31E7B7DFFBEC76FF3CB3ABEF75DF8373EFEBFBE6E995F6665B40AE",
INIT_03 => X"DBB5F600E62FADBA87507FD448CDD78FEDFFC2EF041657AE34FF0CCD17BC4B95",
INIT_04 => X"00E85FEF24B2FF2F6FE44C77A7BDB205707F4D677FBFC9A55C983D7B7E40ACAB",
INIT_05 => X"7F363FE7C1470E2EFC7DEF0783CFBB5D9E2DD87F1FC53A69B726CC6D69A0EC2A",
INIT_06 => X"397D687997CFBABC320E827E1FC2ACC7ED1EFD6AED0F3173FF7E1EAEC2EE3F8F",
INIT_07 => X"A566E9FFFFE85F3DB47B8D789743C87D42EA7EEA1DACB2EFFFD89F5EE74F050A",
INIT_08 => X"CECE23EBD23BE0F9193A7F1ECA0FFD5FF978EEEE7F57D93BBFFC4C7D6BCF53BA",
INIT_09 => X"C30AD2C6C1BFED7EF9F95FD6EAE643341EFCBF9B838F2FE955511ABFFFFE1A9B",
INIT_0A => X"F930FFDFF67C32A4AEFFAAF2296F67E6CB571B7FFFFFF55BEFFAD38BC1A7DBF8",
INIT_0B => X"0E7FE27C6E6FB1D91B9342DFFFFF6B39EE7D0FA5EE87C8F93CFFC78CC1DFCFBD",
INIT_0C => X"854A53AFFFFFD55BEAE5A13809DF24FE8E2DC819B99FDC3DF861FFD7FCF75E95",
INIT_0D => X"D1E8C661C3AB69F841B5C6D1D41B0EFFF132DFC72FC4311A063FE7BDAE97A4A2",
INIT_0E => X"180BE67802FEF95E7AEFFFCF9F98FCAC241FD49BFB1FD36195F911FBFFFFFFB3",
INIT_0F => X"FAF1FFCFDFEB95CC9DDFF6F77ECFDDB9FA1C41891FFFFE07BA5C234270A611FD",
INIT_10 => X"D8DFF10BCD97F23F9309E39E0FFFFD6DBA592E0947E731F610CFB63C711F50FE",
INIT_11 => X"BD19F9EBEFFFFF7F964FE23B934141DCBA7F810F8E7B68FDCBC1FD0E3F2E3160",
INIT_12 => X"8579A057FC0B51AD762F92E5B1B9CE5FC243FD6687756797660FFFAC12C7ED98",
INIT_13 => X"B3EFDDD0705F42BFC357FFAEF7514EC931C0A805D2C9EB5C4E11297B37FFDFF5",
INIT_14 => X"E207F88FB784B7F585E74A3E01B0F711D8048C0363FFFFF986149F208FE4F67D",
INIT_15 => X"21E46593AC423FF7337602A5ABFFFFBDCAC0B2945CDC1E850708A03FEC3E2EFE",
INIT_16 => X"F1BDE07DDFFFF8BFE42363FE547AE23EAF363ED3326FE07DC95FFB45FDCE3437",
INIT_17 => X"D9E4D26191FF84F16CFFF7735C6F6AEF1147FD8C7CE749F481222D5D9C403DDE",
INIT_18 => X"84D2ABDF64BC2C2F6A4FF20CDF6D3640B5A95EA94B27FF0C6C172AF3DBFFFFFF",
INIT_19 => X"B8AF34999F0F3F5EDD9E422FE4EFFFED96205442E3FFFFFFC201FB220BEDEB0F",
INIT_1A => X"A4AF7C058DEBFFD7F3559F20DFFFFFFFCAA7A0F825ED7EB796810047D7FFA757",
INIT_1B => X"00A8276EF5FFFFFFF2EB3F8709EDBECB3C0BC6C9A83ED98FE7AE7F58DF6A42BE",
INIT_1C => X"A9ACF7387DF9DE57B4D939A5AE7FCE94B78BB1153F0679CEE59FAE13B7F3FFC9",
INIT_1D => X"9DA8ED3DED7A8FD2AAC2F561FFDC3424A953A89D957FFFE64D9E0EEA63FFFFFF",
INIT_1E => X"323E26C5FE3773FA6A9F98DA5ECFFFFA35FAF7C8C2FFFFFFA31F844D85F167A8",
INIT_1F => X"4321E97DF3B77FFE777D030C2EFFFFFFDF444745A9E957D30A5A8BEE726DE85B",
INIT_20 => X"4684073073FFFFFFA4C07B7778E8B71A0AA96CB21C643EBB46BCE412F4F23A21",
INIT_21 => X"C681319CA0E95787E5830BC320DB2A3B44CC45D5F518C9F3DD05779F1CCC7FFF",
INIT_22 => X"433E55C910434FBDADB2F1AFC9FD0B09942EFE7ED9DF7FFFD8B03C8AE6FFFFFF",
INIT_23 => X"C0D36EDDF2BDE828E2617F1EE9967FFF48F11465E0FFFFFFF914AFC58FE9C7AA",
INIT_24 => X"03067FC7BE2B7FFF51C96614D3FFFFFFF9F3BD3B7FC8DB39882FDD28D509029D",
INIT_25 => X"88CA98695F7FFFFF8D99B414FE1ECB3CD346F3EE2821EDA8E93E7D14436FC0DC",
INIT_26 => X"9C5C63CBFE1DC776283A0340561A6A27415CBB93DB66239458987FE11A717FFF",
INIT_27 => X"EA3DD79E7232801C53FE762A9CE7AA1B59D39FF889C67FFF104BBED79F7FFFFF",
INIT_28 => X"43396EE4811CCC79AD9F9FFF6712FFFFE25434DB7F7FFFFFBB528D5DFCFDC77C",
INIT_29 => X"A49A8FFFB783FFD7E0392F13C17FE7FFA0D76E15F935C77B6A667B0B71F6E61E",
INIT_2A => X"FFFFFFFFFFFFFFFFA4DDBCF5FBB1D7A350DC2251806C3878BF36650319BDB5F2",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFF3FF7EFF2FFFEFFFFFF7FCEBBFFBFDDFBDFFFFFFFFCFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"8F1FFFFCFFFFF9FE0BBDFFFFBFC3FAFFDDFF002BBFFFFADEFD1C4FCA67BE7FFF",
INIT_03 => X"E73CFBFF0FDFD5FFF99DD19BDFFFE211C13023D38F96B0EFFDF00F4DFFB387EE",
INIT_04 => X"A33A0970F97FD1C1EFC0CA1F17FF43D7F2EFEFDADBFDEFF7DE1EDAFFFFFBF1FF",
INIT_05 => X"5FFF6233EFEF4805F511EFF3BBEDFFF73B7FF9FFBFF3F3F7FFBDF3FF27DFEFFF",
INIT_06 => X"F7CD3FFEFFF1F9F773FEEDFF37F7F3E7F7FFFFFF8FBBC3BFFE3745F43EFFEBE1",
INIT_07 => X"FBC0EDFF37F3F1E7F7FFFFFFFF8387DDFCA21E71E7CFF9FA5F00D0BEF7EF7AEB",
INIT_08 => X"F1FDFFFFFFFDEF9FA55182DC50D13F8FF801D62EEFE1FFF3FA32FFFCDCFBFBFF",
INIT_09 => X"85D56120F873648CE7FE0E2FC73B7FFDF2F7FFCE9FFF93F1FFCB7FFF3BECFB87",
INIT_0A => X"EB00689FCEFC657EBB23FCC1AF3C16A0F70FFFFF3CFFFFC7B9FEFFFFF6E5BF1D",
INIT_0B => X"D2E7FA015F74FA5FE59FFFF73CDE3FC731FEFFFFF7DEFFFFC671AAC38D2A9C3E",
INIT_0C => X"FE7EEFC03DDFFFCF3DFEFFFF9BEFFFFF845B161641A11F2948302E9FEFFFC9CF",
INIT_0D => X"3DFFFFFF93ECFFFFA7B20497F0640F76B7FF039F9FEFD7F7845778CFF63FC9E7",
INIT_0E => X"C1085A7DEA9DFDF8E700F83F89EDFFFBC0499E9997FFE7E7FCFC04F83FFEFFEF",
INIT_0F => X"4E00E7FFFBE03FF809E4FE6107BBE3EFFDFBE7FFF6FAFFFFBC7FFFFFD77CFCFF",
INIT_10 => X"9EF33781DF344BFDE3F4F3FFFFDBFFFFFD3FFFFFEFBFFBFF8FB3DE8C451AFFF8",
INIT_11 => X"49F3DBFFEF37FBFFFF3FFFFFF77FFAFF81CA073C6BF2F7DA0E000FFFDFFF6FE1",
INIT_12 => X"FE9FFFFFF2ABF9FFF08DA75E038BEDFB9C803FC33FFF81F5BDE6F2C3DE56CB71",
INIT_13 => X"90DAF890FBADF9FA7C00FFE7FC2E4E5AFFF7B7C0FF7EB23AE7EFFFFFE63EDCFF",
INIT_14 => X"BA3CFFFE77E766C7BD7FC7B7DF77FF7F7FC9FFDBF57DDBF7FF7FFFFF7E7DF7FF",
INIT_15 => X"7EE28B075BEFE77FBFA399AFF6F9DFE3FF8FFFFEB1A0E3E7CECBFE8A5667FFFF",
INIT_16 => X"939FC5EFE27EFDF7E1FFFFFFFBE7E7E7ECC4D4E708B2BE1F5A7DFFFE3FFFFF3F",
INIT_17 => X"FFFFFFFFCFFFE7E7E94C42773CE00F9F79FFFFFE3BFFFFFFFF7D3DAF5BF3E7FF",
INIT_18 => X"F9AA35E31C69B3DFE3FFFFC6BEFC3FFFFD7DA0DAE7F3F873CFFFEBFD6766FBFF",
INIT_19 => X"C1FFFF803B7B8FFBFCBEEDBB3BF1E7FBFEFCFFFC9FCFFBFFFCFCFFFCAFFFF7E7",
INIT_1A => X"FFFCD272E7F0F6F47EBF7C7FCFEFF1BFFA2DFFF8BF2F8FC79E13A9A6D614D7FF",
INIT_1B => X"FD667EEF5FFFEFBFF7DDFFF8FFC77FC7FE204821B3936FFFF7FFFF817E1FD7F8",
INIT_1C => X"FBDEFFF7F3E7BFC7FD7B70237F486BFD7C1FFFE17CE8FBFAFFDDFF69E67EF5FD",
INIT_1D => X"FDC77EC78353900FBE5FFFFD74FCF3FDF1DF3FD1C9F9ECE5FC27DD6F7FF9DFFF",
INIT_1E => X"FF0BFFF8FD7F70FFF1773FEBEB7DE3E7E3718FFEFFBF37FCFBEFFFFFE3FE7F87",
INIT_1F => X"3CB7BEF8743EFFEFF6FBEFFC7A79C7FC7BFFFFF3C3F97987B3DFBD9BEF91857F",
INIT_20 => X"E7FEBFF9F1BF4FFDF1FDFFFFFFFEFFEFB1DFD9DC5A9062FF7FE37FF03FBF3FFF",
INIT_21 => X"F7F91F9BFFFDFDFFF07FC2FC1F3FD6B2B77880E21F6FBA9F9FBFFDBFB82F6D8F",
INIT_22 => X"FFFFC6197A80F8D3B3029E065FAFFDD93F3FF9DF3AFF6B8FCFDC7F9CFA7F2FFF",
INIT_23 => X"FCEF4C66AFF3DFFB7F7EFE0FF25BF3FE9B8FFF3C27F46FEFE7D7D02FFFF5F7FF",
INIT_24 => X"366FFFFFF965F3D1F7EFFFFE5EE14FCF9FFFCCBFFFF7E7FFFFFFF769FF3F53E1",
INIT_25 => X"F9E7FF0FB90FE5D7FE67EF3F3EF7F3FFCFFFF2B8BD3D4029FF2C24509DF7AFCC",
INIT_26 => X"5D7EFFFF5EFFFFFFA9FE3DF3DC0F21337941E6A9F5F18FD40757FFFFCE67330B",
INIT_27 => X"BB1F3EBF1F9F2008DFA019AAF9FEDFD33BA7B3FFF185363FF8BF1D1BFB1EB9CF",
INIT_28 => X"7BD2A9B3FFFFCFF7BF6FE4FFFE055E3FFAFE71D1FFFEFFFFBAFDFF7FFEFF3BF7",
INIT_29 => X"7DBFF4DFFBB17EBFFF7E3947FFFDDFFC7FFFFFF7FFFEDF7FC06FFD3E7AE731CC",
INIT_2A => X"FCFEBE7CFBFC1FDDBFFFF8F7FFEDBE3F81AFFF53F4B291D2BFEC287F0A7FFEFD",
INIT_2B => X"8FFD7EF3FF62FF8FB2CFFFBFFEB9B7AEFFF24CCF051FFE7BFCF7EF17FF8AEDFF",
INIT_2C => X"866D9FFFFFEF8F127F9FE3587DC99FFFFF73DF67FFDF45FFF67C7EE33EFB7FDF",
INIT_2D => X"FFFD2F59C7E1BD0EFFF9CFC3FF6355FFEC74FE43FBF93FFFEB7F9DFDF97E7FA7",
INIT_2E => X"CFFEF7EB97B0FFF7916DFC3779FBFFFF873D3EF9F7FC7FD7DCA68FF3FFFBFE3F",
INIT_2F => X"B7183DFCF86277FF7E3EFEFDFD7DFFE3DC9CAA5FFFFFA9A2F97FFB858378EFCF",
INIT_30 => X"9E3EF9FFFEFBFFE78096863FFF9A8F17F27FFF2169FD61CFF7DCE7EBA6181FE6",
INIT_31 => X"D3E51BAE5F810B5BF0FF7C1FF7FFEFDBF7CEE9E7E79A3FFFFF32FCFF7AFCF3ED",
INIT_32 => X"F1FDDFDFDFFFE7F9FFEFFAFFFF55BCFFF861FFFE35F773EF7FFFFCFFFE79FC73",
INIT_33 => X"38FFFE7FFFFDAFFFFD227FFDEFAC27CF7FFFF9FDFB77FC73B62D827997D4D95F",
INIT_34 => X"85CCD9FFEFB4A7CEBF7FFEFCEE23BFFDCB3C980209B78FFFFFF1DF3FFBE76AF5",
INIT_35 => X"FFF6DDFCE0D77FFF8FBB812C18FFBFFCFEF3FFF1FFC7FBFC3E379FCF0FFFBFFF",
INIT_36 => X"FCAE67B9A877FF3CFEFBFFE67CE7FE7DFB737FD3A37F5DFD2971E6BFFFDD27C7",
INIT_37 => X"FFFFFFCA79F7FE7BF679BFC5F1F95DEDA105D6BFE7A86FCFBF767D7CFCA7FFFF",
INIT_38 => X"FC785E39F9F8DAB02878EABFE7DAEFCFDF7FBF3E633F3FF9C5D3235CE70FFF7F",
INIT_39 => X"B314E527F842EFC7BFFF8F3EE5F7FD73F36AD9BB53547C6FFFFFFFEF1F7FF71F",
INIT_3A => X"DC1F9E3E7507FC73803D7FFB496AFE2FFFFF80E5DD5FF75FFE7FF237F8F875B9",
INIT_3B => X"ACAADD6AE8F7E76FFFFE82791F9D8F8FDE7FF0C338FF74D2CEED3FE3FEE2FFCF",
INIT_3C => X"FFFD38FCD7FE3FFFFCFEFDF87DB757F2B1EB89FFFF74FFFFDFC7BFFCDF6FFFC7",
INIT_3D => X"FEDCFAFEFEF58E5B9BEE18FFEF95FFFFCFFBC7FDF66FFFFFBF230FFDD9BBA6BF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"6330FFFFED5AFFFFBEFBDFFDB97FFFDF9D038CBE6F951887DFFD3FFE1FD7BF8F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"DFCB9F7FDD7FFF63E54DEBFD7AFC95614F8FBE7F1FA5BFEBFF86F8FA777DB6F4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"BBBC4DEC3F3EDC0DBFC3FF1FEB123FCBFF39E7E983BC73FD669E0FFFF3C1FFFF",
INIT_01 => X"F9F9FFC7FFE2FCF3FFF8E6FFEECC97E27BCB1FFFF009FFFFFEC75F7FD5E1FD37",
INIT_02 => X"FFFFF4F0F0505FE236211FFF3FD1FFFF7A5FFFFF3BE1107DED102DE8FFFFFBF1",
INIT_03 => X"EBCB9FFE1E03FFFFF9EE3F7F45E10EFBFFDCF6EDDFFFBBA667BCF5F8F8E07D7F",
INIT_04 => X"F3F7FF7FFDE3F0FBF383FFF3E77FD57F8A5FF5FDFCDF3EFCFE3C710F7DF68FE7",
INIT_05 => X"E087FFFFFF2DB8BFBCAFFAFF9F6FBF7FFEDE6257D8C479ED91C4E7FF1707FFFF",
INIT_06 => X"BFFFFFFF9F1F9FFFFEEC0C79AA6704FAB9F917FEE4BBFFFFFFEDFF3EFFFFFDFF",
INIT_07 => X"7EDF5219F8D204EA469D73FFFA47FFFFFFEFFFFFBFFFFFD7DEF3FFFFD86BE0AD",
INIT_08 => X"C26D23EFC40FFFFFCFEBFFFCF7FFFF93BD2BF14D7BBFB708E5F3FFFF1F8F63FB",
INIT_09 => X"FD3DFFFD53FFFE7FFC8E02377C7F3F9A89E8BE0F3FEFA7FA7F3FB142DD3B20EA",
INIT_0A => X"A06501D496FF4FFF24683F0FBFE4F1F17F7F73F4CE101FC6248E97FFAA2FFFFF",
INIT_0B => X"FD1C8FFFFFFB787E7FF1DDFFA411D6DC3E007F3F55BFFFFFFD7FFFDD4FFF3FBF",
INIT_0C => X"7FFEF2FB580C3829DBF0FFFA831BFFFF3BFDFFDEB7FFCD7FC825BBC44EED8FFF",
INIT_0D => X"798EBFF4190FFFFF39FFCFC7EE3F69FFB42764E088C747B7FFE0C3FEFFFFBC7E",
INIT_0E => X"F3FFFFC81EFFFCFFC0C1FFF0DFFB1FFF7F7F02FC7F5FE55FBFFFFD232DA17C4C",
INIT_0F => X"91110549A2FEC6FFD7F1947C7E6FD45F7FFFFC81B8FE4F57C539FFF434EBFFFF",
INIT_10 => X"FFDFFF1FFF5FCE16BE8FFA24F3081709C224FFE47CEFFF7FC36FFFE3DFF7E97F",
INIT_11 => X"3C1FE92CCDE03C7ACC62FFF0F4BFFFFFFCBFFF7A0FF7FA7FEF81F8000FD0AFFF",
INIT_12 => X"9569FFFFE6FFFFFFBFFFFF9BA7FF9FFD9FFE001E20F1BCFDFFFC5EEFFFFFF8AC",
INIT_13 => X"7FFFFFBD27FE7FFDBDFCFC66FC3CF87FF1FF5DE7BFFFF9EE07CFE948FCF5D45F",
INIT_14 => X"DD9A7CC90608A87FE0FFFA09FFF8FEAF98D7FB15BD432A49E1EDF0FFC1EFFFFF",
INIT_15 => X"E07FFCE4FFFB7F6CE426D38CDE83283F9B0DF1FFC1E7FFFD7FFFFE20EB7F7FFD",
INIT_16 => X"8072D703E2E495E24609FFFFE3E7FFFD3FF3FC74623C7FFFA03A7C8806F45F3F",
INIT_17 => X"F6337FFF95E3FFFD9FF9FD88F83CF3EFE9B5F8C3FCE7ECBFF1FCFCE7FFFBBFA3",
INIT_18 => X"BFFFFDF87C3C7BCFCF4D001F5D8A5A9FFFFFFFFE7FC797DDE2F0D3F06CF4001C",
INIT_19 => X"D24F7EE24187FACFFFFFFFFFEFCF07F2CF3E0B2D9CB1BFABD7CABFF9EDE3FFFF",
INIT_1A => X"FFFFFFFFE2FF81E4AFFEF23299C003B2231115FB9BF3FFFB9FFFFFE37F7CAFBF",
INIT_1B => X"C7FFE0CA0155FC77230E37FF87F7FFF79FFFFF65FFFEDF0DA94B81FA8B1007CF",
INIT_1C => X"383B17FF12FFFFF7FFFFFEBCFFF5FF99C4226270FFFF7D87FFFCFFFFFB9FFCF8",
INIT_1D => X"FFFFFF7DFFFFFFB983B82D67FF00F3E63FFCFC1FF837FEFDE8FFF056198EFB3C",
INIT_1E => X"8AEF3148FF8077559FFCF80FFF95FF3F58FFF46097A80C71F02E3BFFE7FFFFE7",
INIT_1F => X"7FFDF87FFFC4FFFFCAFFFB1E1420748711D31FFE6FFFFFE7FFFFFD03FFFFFFF9",
INIT_20 => X"CF7BFFF1DC79D5571EC0FE7FBFFEFFE7FFFF7DC5EFBEFFF1F3E98B500090A489",
INIT_21 => X"CDB99D7E0FFCFFFFFFFF593FCF3DFDF7F67869480006F47D4FFFFEFFFFFE9FFF",
INIT_22 => X"FFFFAAFFCFFA7F95B43E992EFE018BD538BFFFFF3FFDCBFFEE3BFFFBBBDFD9A5",
INIT_23 => X"D1807731508B67936B9FFFFCFFFF8FFF7B4FFEF972E3752C6D12BC7F8FFCFFFF",
INIT_24 => X"A4CFFF3EF0FFC0BC3FFDFBE1E8473BE34C7E7EFCCDFFFFFFFFFFB539DFB81FF5",
INIT_25 => X"7FAFFEFC925A6744BCBC9FF8F9FFFFFFFFFFF05DFFDE78F1B1B8103E0DC98E37",
INIT_26 => X"4F0BCFF619FFFFFFFFFFDF27FFFFF68B993FB57FF22C0A695663FC07F0FFFB83",
INIT_27 => X"FFFFD673FFFFC4F7F8F955FF4B81F4327BC6034BFFFFFCBABFEFFFCF02D687CC",
INIT_28 => X"87C3D8074D2280A5FB7D23FFEFFFBE3A3F3FFFAFE812E7D3FE34F77E19FFFFFF",
INIT_29 => X"01F2E7EFFFFF1F2A7FFF8FFF0761D0B01E79FEC7DDFEFFFFFFFFEE7BFFFFD0FF",
INIT_2A => X"D7F231FF47E12F5495B9FD57CFFC01FFFFFFCCFFFFFC48FF82FF32C37A984809",
INIT_2B => X"5CD4F8A6D7F86CFFFFFF8E77FFFD97FFBEFEB3C3FC26775CFFF3EFE7FFFF8787",
INIT_2C => X"FFFC26FFFFF17EBFFFBCF3E0140B2157FFE7E7EDE78FFFE123F662DE454F2856",
INIT_2D => X"E7FDB7F0D99AE3387FDBE7F4FFAFF8F8C1F5A45E8E23A7042139FAB47FF182FF",
INIT_2E => X"1E071F18ADFFFF7CDBF72EDFE0B89936E4AC7B89BFF7FAFFFFFFC3FEFCC3F93F",
INIT_2F => X"E5F5D5D99A339712E343FE3B87E8327FFFF85FE6FF1FF8FF88737FC9DE5731F9",
INIT_30 => X"CFAEBD0B07D64E7FFFFD2FDE7F3FFFFFCF02FF7FD362C116E11F6F73D6FFFCFF",
INIT_31 => X"FFE70DE6FFFF3FCFFC0FFE3FA42BF09268CFCF8B8BFFFEFFE784FE2B0CDBD3C5",
INIT_32 => X"9C10FC9E780648AB9AFFBFEB45FFFFFFDFC0C66F1724B3B938191A97E7EB8B7F",
INIT_33 => X"9BBF8FFF76B7FFFF8FF7F451ECFC8797664BFBA0AFE7C37FFFEE25FFFFFFFFCF",
INIT_34 => X"FFDAA3B869D28B32936C2BE7CFBD137FFFC46DFF3FFFFFFFEC9E78F24C96E371",
INIT_35 => X"DC93F4478F99567FFF35B1C73FFFFFFFD8407C6D42E927C22138C7FF18EDFFFF",
INIT_36 => X"FF150FC7FFFFE1FDC15C7FBCD136EE9D6443EA50AC2AFF1FFFFCBC275BE1B665",
INIT_37 => X"F927E321E89B88BF1EF4FDFDD3AD9FFFFF7CA1563E7E80B49C4528AD3FC1A6FF",
INIT_38 => X"540BFFE6B86ECFCFFFFC9C9B9DA82322364F0D63BF0EB3FFFD03D7FFFFFF3FFF",
INIT_39 => X"FFEF22B2782C395AEAB452956695AFFF7B6E67FFFFFF3FFFA6A0FF006BEE1FE5",
INIT_3A => X"D78D27FF8A0B17FFE69D8FFFFFFF1FFFA6B101FF9BFAA96B76D9FFC6E5B19984",
INIT_3B => X"6F7C3FFFFFFFE7FFA47807006CD10067FF14BF89E56C2583AFECF26418BB6F5F",
INIT_3C => X"F7F37F14AB57976FFFFF7D9AEA171E3FC8E0FB5ED5B507B376953F9284B627DF",
INIT_3D => X"FFFF99FBF716B2279CFA7B8E95793D135990E04646D68FC0D5FE7FFFFFFFE1FD",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"AEE07A3F024C0E9E3996CBC53E0BCFCB41FFFFFFFFE1F4FFDA9B7FF7FBD37FFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"108527EF4F9B5F2671FFFFFFFFE1F67F8DECFFC0534BFFF8FFFFA1FF3CD5CC34"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"AFFFFFFFFFFFF37FE019FF003577FFFDF0FFF9FFFF16A58A4FF17C201249A0FE",
INIT_01 => X"F80C80001C6FBFFF80D7E7CFFFE83499CFEBFC37A5F1E769E517B154B8F25CE6",
INIT_02 => X"E09FFF0F0FFD1B207F13FF543C13E8058681E51BD9CDCD1931FFFFFFFFFFFC3F",
INIT_03 => X"EE4AFF65C53E9046BE9B075B2D1F19CC3FFFFFFFFFFFFEDD8FBC001961BF87FF",
INIT_04 => X"C41E449D6F73996EBDFFFFFFFFFFFFBFA301033C7E7F9FFFFFFFF3F87FFFA4AC",
INIT_05 => X"7BFFFFFFFFFFFFFD80F0C181B2B8FFFFFFFFF3FCFFFFE2743006FD6D31CFA29D",
INIT_06 => X"C180FFE130F9FFFFFFFFF3FCFFFFE0AFE7FFFF62B35F786A5E7C3B858E74C607",
INIT_07 => X"FFF8FFFFFFFFEFE90F7BFF60024ED7E1A5B5DF3F7EF40E96FFFFFFFFFFFFFFFD",
INIT_08 => X"79E71F40E108243129CC13799A7ABAA2FFFFFD0FFFFFFFF7B8C1F0B1FDBBFFFF",
INIT_09 => X"49D15E9D2A3900DC7FFFC30FFFFFFFDBBCFE7CCC5CFFFFFFFFF9FFFFFFFFF09D",
INIT_0A => X"BFFF70DFFFFFFFCFEE1F81347D5FBFFEFFFFFF9FFFFFFFB3339C0F8F7D185AC8",
INIT_0B => X"EFFE376157FFFFFC7EFFFFDFFE0EFFF1F21E8F879DF88AA3BD774A97DFCD05DB",
INIT_0C => X"2EFEFFFFFC0FFFFFA42360736FF98CC67A7FB886A2A05197FFFC42DFFFFFAC65",
INIT_0D => X"7E07E7FCDB0ED126397DBF60CC60302B3CFEB2BFFFFE8BFDBE3F831CDFBBFEFB",
INIT_0E => X"49324957905007B4EA27093FBFFB85FDFE40B7FFFE2633FDCFE35FFFF867FFF0",
INIT_0F => X"D9BC24FF1FFACFE781595F5FFFDF42EFFFBF19FC4F0FFFFFFB9C0EFE1C880624",
INIT_10 => X"83D3FFFFFDFFE0FFFF847FFFBCF4FFFFD9F50C3FF36CD12805B4AA27FBA433D8",
INIT_11 => X"FE00093330BCFFFFB65FFC3F347F951600A65913B5D829DA596ED1FF3FE7FEA9",
INIT_12 => X"D051FC7814598F58E74382BA2EE31B00755693FFFF33F853FB2A7E39FA0FBE9F",
INIT_13 => X"5793BF0204603E928BA267FFFD3E82A79516FFF368FCBC67F0FF2AFFFFFFFFFF",
INIT_14 => X"52BB9FFFFD0645FFA4FA07F60D0CB802F84F9FFFFEFFFE3FC874F8381448F0B9",
INIT_15 => X"C3DFEDC9C1F139C7707BFFF086FFFE1FC6C8F03C37347377409022D5AFBCC6A8",
INIT_16 => X"383FFFFFFFFFFF1C6278FB19797CF472DE497A3494B7D8A4A2A67FFFF4EB94C5",
INIT_17 => X"12E4FFB6FE7235FE8EAE0FA495BF945C4945FFFFE4A8CA65AC95388E1F8378C0",
INIT_18 => X"95FC35F46C7FF378921FFFFFDA38CC85FFB4A5111DBC04CE60BF03FFFFFF3E1E",
INIT_19 => X"74FFFFFF90CEC9BDFFD868C8CCA20225C7FF1FFFFFFF7F095BDDFFF6FA1CFBAC",
INIT_1A => X"FA2C6F08DEB455DFFFFFFFFFFFF1FF542BA39FF9743344E875D4E4A3A0DD297B",
INIT_1B => X"FE7FFFF1FFFFFF5F28D80F00F59C0FBCE0B83EC4813322F5E1BCFFFF08AEDC2B",
INIT_1C => X"FC0F84003C4326A340A0DF5173BDDB2A33FFFFFFEEC6ED3FC0A70E9A0A4B523F",
INIT_1D => X"640C2D85F9FF810A2FDFFFFFD6C5C23F87BF2EAE1A20DCFFFCFFFFF1FFFFA2DE",
INIT_1E => X"719FFFFF3E9D6687FA0B03169AA3C5FEDFFFFFFFFFFFA4DFFA5460FFC05D71CE",
INIT_1F => X"FA6A5A96AAC375FC3FF8FFFFFFFD37F7FCAFD1DFF211C689E7040EADFCD70279",
INIT_20 => X"7FE1DFDFE7FE268FFFD4A80D0C4D7F9A8D3AB0F8FCFC5CD6CC5FE3159E5BEE45",
INIT_21 => X"9F0496874D228163BFB29FFFFFB7820725C69B9005E39F93F1905FD2186B11F8",
INIT_22 => X"1ED4787FFF31C3AB297FFA6DE2305C039268EF61314FFFF9FFC3C7DFFA68478F",
INIT_23 => X"F4F17989F54B637B80262AAE3C7FF9F9FFFFFEB7D919FFFFFF3E914062E6A73D",
INIT_24 => X"9CD521AD47FFF7FF7FFFFFDBFF8FFFFFFEF0F1334323E3D793A6AC5F21927E02",
INIT_25 => X"37CFFFC7FC7F3FFFF09AC133607337AD095A9A9C2CF4A3D3860B39A68C1A23CF",
INIT_26 => X"E2E3F6D92964D6F023531DBF2C931A6D7913894883A9181BC019269E5FFFFFFF",
INIT_27 => X"970FFFF290BC5FF50812C0CD78597011D0BCB688BE3FEE3F8BEFD7F335FBFFFF",
INIT_28 => X"BFAF20FE83F8EC919DBAB36C78EF5B87FFFFF1E733FB1FFFDBF555C983EE9543",
INIT_29 => X"B2DB4ADFE6E2D387FFFFA61F27D7B3FFEFE2170C631E50D69497FFC33AFD7E25",
INIT_2A => X"FEFC0BE32FA7F67F5FD70E4E1744A95858FFFF39FEF9FFA24B20F9F8FFFF40CD",
INIT_2B => X"7FB58A42BBD0CD30DBCFFF18F7FFFE8CA89BD700FFFF889FEEAA15CFDFDF6121",
INIT_2C => X"C9AEBAA877FFC9CC9F407AFFFFFFC33F84325F997FB22887CF309F43010FF6FF",
INIT_2D => X"B7C9FBFF3FFF7CFFD33EA836FAD444757687E7A891BFF0F8FF833AB213F67278",
INIT_2E => X"E788ED28E2DD31DB6FF6695F05FFF9F1FF0E7126D6C62848D74527DBFFFF47CD",
INIT_2F => X"D89813D85FFFFFEBFF19F2E707FCCAD28F75B1E7FFE9E3E3E9CBBFFF3F8FC1FF",
INIT_30 => X"FFFB3821EC7E2EF0802367FFFF9A5AC5DB021FFF3F8FFFFFB149ED225A262EB8",
INIT_31 => X"873857FF8E6AAF5EC321BE0FFF8FFFFFB61320FFD298B170E75F349BEFFFFFFB",
INIT_32 => X"346A7E0FFF77FFFFD56D41E4CAE225DECC335D37E3FFFF1FFE734DD7EA420116",
INIT_33 => X"8B5CD7CA530932F4B6183EFEE7F37F3DFD4EEEC6C6D477AC3F7AEF474132F5A0",
INIT_34 => X"7B5BFFFD6FC3FCDEF6DEB0947FBB61842F8F7E3F84782342E84D3DFCFE787FFF",
INIT_35 => X"F79DF56A5638435AF7F87FFCD92CE5EC9474A9FAFA81BFFFF0F9476A65613CAC",
INIT_36 => X"33F8F0895F68C27472B0107A717647FDB873AE1AB9D2BFA3A62FFFFD3FC1FAF9",
INIT_37 => X"FC8383C3758D4607912FFDD16062F599FC15FFFFFFFFFFFFF07EF6E5DE750B68",
INIT_38 => X"F43CEEBA4396FE90F3AFFFFFF1FFF1F7F8F789E10030B52F33E5CB7111A7A6C3",
INIT_39 => X"81FFFFFFECFFD3FFFFFFE20BA6902320F3C062134D8F71CFFD49BE931ABE9CC1",
INIT_3A => X"FFFF9CE09023AC3779E0DB7DF553F7CBFEB1C990159E81E7B7F21D599249FA90",
INIT_3B => X"C61CBE1FF317F361AB551ABF8286C1FDB1338DB70657F95C9BFCFFFFCEFF5BFF",
INIT_3C => X"B58DBDBCD6C0219FC4DCB848D95FD08B0AFCFFFFF93F77FCFFFDCE31DCB273FA",
INIT_3D => X"861303368DBFD7E8FFF33FFCFE3D9FFCFFFFCCDF7EAED6F083A7BF6FCD65F003",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FCFFFFFFE7FBCFCFFFCB5FC215F8E19E8BB87C7FCCB70D7BB3C31EDF6C676E1",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFD0C3F82C4AD1BD69EDBEFDE4070EC2D9EF08CC2C156EFEB3D0CD6C07E7834"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"5A9847E1D64D3C3C039497FBFB8377E9827B01BA0FBE1F0A7FCFFFFFFFFFF6FF",
INIT_01 => X"CA0C5F7F7C1E6DCFB57A3E79F05EF1B5F3CFFFFFF7C5FCFFFFFE7B102017EEFC",
INIT_02 => X"F006FCFFF8BB33A383EFFFFFFFBF75FFFF7C1F904A188DF1227843F6CF50BC34",
INIT_03 => X"E3FFFFFFFFA4FFCFFF7C874E3128F5E712B8328A8CBE13409523ED5F25FB0419",
INIT_04 => X"FE7B63C1B2CD3FE3E7BAF30A3F6DD0B1ACA0F02F3828B71DBAA983C998F4FB7B",
INIT_05 => X"0A82FF2D37AD71B1B331B418EBF3726593573FC792EF83FBEBFC3FFFFC07FFFF",
INIT_06 => X"435F0C30E7066485F3C34FCF439277FFE3FFBD7FFCFFBFFFFE75B3849CA027E8",
INIT_07 => X"953B873008739FFFF3F9BBFFC7C73FFFFF7377DA03F7B23C308DA2F35B96C8D8",
INIT_08 => X"F3FF7FE79DDFFFFFEFE777ED0A876E7F65F26A62EBFCA3F2B78132E3C9BBF29B",
INIT_09 => X"CFFCFFCD516BA9F8E51F56B8C38C7FD9A38AEAC004085865E4C30D575B527FFD",
INIT_0A => X"582F1E48E36817FC6FAAB69E03E927BFF3A88ADF521BFDFFF9D7FFD7E0BFFFFF",
INIT_0B => X"D8A25F9CF48FC08FEE0317C6ECF4FCFF78E9FF8F1FFFFFFFCFCBFF0DE9514A7C",
INIT_0C => X"A305F6E7F631FA7FF8B7FF9C117FFFFFCFCBE7CD2DC661EEF9902C896650EBFA",
INIT_0D => X"7CF4E7382EBFFFFFEFCFE78A1DA0B3D78A7FFD1A136E33FF17B4E8C07167ED79",
INIT_0E => X"FF97EFE1FFFC53FFE27F74EFE39749CF3E6D06A2024721C3D338F38CA613E81F",
INIT_0F => X"6DF2BFEEFB9FCD8F4D04D0D873EDBFF9F2411EDD3BF7FF1FCCA1F7FE28FBFFFF",
INIT_10 => X"A51052EF6FF90E49939402FD7F77FFDFDC97F7F06D7BFFFFFFD7FFC7CFCA9BF7",
INIT_11 => X"D121DBFFFF67FFFF4EF9FFE422F3FFFFFFA7FFFBFFD117C791FEBA88B50FB7FF",
INIT_12 => X"90F7F7BB43E799DFEF6F9F0DF7FB3FFFBCF79F0F2E7F3CFFAA997C873F7EB80F",
INIT_13 => X"FF7F7F94FFFD37FF99FFBAFB0E33A27C745584E47FFE3A7DE43AF97FFF7FFCFD",
INIT_14 => X"82FFADBB8B1A0669A9A2BF1E871E750DF428427FFFF38BF69B6FC07719FFC3BA",
INIT_15 => X"6F27D6BC80E3842F967824DFF7FAEA5CE1FFD5A7F3FFFFFBF77EFE0C7F6FC3FF",
INIT_16 => X"E6608083E739F2508BFFC94F87FFFEF9F6BEFD469E59B0FD8F6E852F66C88236",
INIT_17 => X"7D7F21BF3FFFFFFFFE5EFB42096098FFE507F100BAAD42FACC9D31D4001C0AD1",
INIT_18 => X"FCBEF9B44334677FC8C2F7801D434F68474CA7B2F0CC827DBD78C9E9EFF5EB84",
INIT_19 => X"A129F06E861745F9235B648F9C835193FE6C5FF87FF35270B3FF92A4ACFFFFFF",
INIT_1A => X"DA0AC61CF90AD311E4A187FFFDB268488FFDDDE8FAFFFD7FFF7EFEF6DF2AE83F",
INIT_1B => X"E17C09FF59ACD3E45EBCFD5CF1FFCEFFFB7FFBB3BFF932FFA3CEFCC9E9780FFF",
INIT_1C => X"3F9E5573FFDFF4FFB8FFF07BD73232FFE756FE3D536ABBDFA58E1D9709D83867",
INIT_1D => X"BCFF7A84C72CC1FF147EFF662ADBD98FF9C95074F09F4E6BB133C7FF1E1A74FF",
INIT_1E => X"5796FEFAA65E76FE6A7ECD699012506B8F225FFFFDFEF0319FFCC441FFDFB9FF",
INIT_1F => X"8D9EC58FC8B2BFC98EDFBFFFFFFFFD91BFFF0C61FFFF8FFFF9FC3E089F9768FF",
INIT_20 => X"97797FFFFF61F06DF3EC0FD7FBF7C7FF7FFCBBC56388DEF767193E992C5328F8",
INIT_21 => X"F3EB1CC7F0F4AFFE71FD3D25856E97EF63E49F3C95FBB3F4AE14FC4D9A4753E5",
INIT_22 => X"699DCDE26A99EBE77A7FE938975C45FBE6F6022D06412A33E366FFFFFE6C0943",
INIT_23 => X"3F8A126339A7E67FE3D95951CA0CD71B9986FFFE7F502127F885BC67F6F677FC",
INIT_24 => X"FD0576BED8B7E8CB9DA6A63B3D1C60ACB8A5C73FF2FC4BFCF39E5D185F37AFE7",
INIT_25 => X"8D807FD845475BFCFA8B829DF9C64FFCEF9FC02501E3EDEF7E06D4A0B14540DF",
INIT_26 => X"F905DDD97F55F7FCC39FF8636015D1F33AB5422B2305CF5BFEBA5B5E76034815",
INIT_27 => X"975FE0FB622FF9F71CCFA86EB86837DFBFBB1CEA4378E70BC97A88A95A1CEFFA",
INIT_28 => X"DEC069913EA8D8125FDE05E24FFFF919C8D68F8647D5EFF62D7A10B57F3C3FFF",
INIT_29 => X"8FFB1A0312FFFD1DEF1633376E3D9C0A32FA90B03FA1DFFFB73FD9F4AADFF1FF",
INIT_2A => X"A9B9231C2BE4F9B8438AEDDABEBA0FFFCFBF43868A4FBDFDFCFE8921A39BFE14",
INIT_2B => X"4EE199C7F76927F7DEFECA7A8C578C7DFFB47D179D07CEAADE3F2184BFFFFE01",
INIT_2C => X"CE7E726784FB8F7DF6355B86F5AAD2FB0F87D97FFCFFFFFFEF45699F34218F93",
INIT_2D => X"FB0053D9F9B2D818CBFFCFA0BD3FFFFF9FFB253748C07AC1B6E44AEFFE16DFE7",
INIT_2E => X"75FCFA635C3FFFFFDAE9A1FA56B04DB419BD366FFF6613E7AD76769844DDDC5D",
INIT_2F => X"8B649C4F8613535AADC506AFFB80B3ECFCEDEE9771A7D79FFF98D90BE1824F35",
INIT_30 => X"135ACE3FFFEA73EF0BC7CD91187DD897F1E29D8DF940D332AFFC26C0BDFFFFFF",
INIT_31 => X"1AC79B1209E7DCD15EBEEB8BFE82D64F58FC2850DFFFFFFFA3F7138752F8B339",
INIT_32 => X"C9FD4B6DF92961830BAFE46C48FFFFFFBFB3343D72AD36F09152FC7FE65FBDFC",
INIT_33 => X"954BF30217FFFFFFC17BA49C6FF78DFFCE7F14FFB67A7DFC671788D78C07D58E",
INIT_34 => X"A924D76EF8D1E9FC1A375C9FC826FDDAF3E60DD6666D16BBA2F77FCFFB867B2F",
INIT_35 => X"1641ACFFBE07FF7FE57ED7766C3B8E38FD4A3F93FD7129DA41FFFFF3627FFFFF",
INIT_36 => X"C6FA2667581442D4F905F725FC5A6DB49DC9FFD1377FFFFF90629DB8EEEEC1F8",
INIT_37 => X"78253F17FE8E464947577F70C33EFFF9F957CF44BF52F5FD09199FFC5185FF7B",
INIT_38 => X"AC03DFE045397F3FCABE60A0493C6260C07A3FFE9FB47FBD4BDDCDECC24E4798",
INIT_39 => X"AA8E8140D32301A49BDBF796FE57FFB6AF1C5AFDA06015F4BD6AE95FFFAAFB95",
INIT_3A => X"11648734B743BFA91F9C8BFFB81617723F81B753FF090C8AB46BF7FD9C5575A9",
INIT_3B => X"7F3BCBB8E21AFFB17FE41DA1FFCFBD1875772BFFF800F673C1CD82BFB49A5576",
INIT_3C => X"FFC78E2ACFF48B48CB5FBBFF1DA41659FA4B79BF1D5A517AD5938FBF571FFFF2",
INIT_3D => X"0EF9C5FFDEB56A89FD53E66FE3D7EA7F7588E7D26F19FFE97FF1E137DB1C2FD2",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"C85012B34643367DB619F3F21F1DFFC8FFE5A7FE87D163C55FE43C1A2FF7335C",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"E127F1E1CABFEFF9CFFC7FC947F761C6BF661AAF8BFFC3586D122AFF0F7294E7"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"F5E89FD68938E34E1F3A1A76B7FC52BB189DBAFFBE698EB180FC93C50555A471",
INIT_01 => X"BF3F2E8B3F3DF068C606C27FFE8E40458FBCE7C6AE0177717EA4FFFADC95CFC1",
INIT_02 => X"5504237FFE4885C3F1321F057F579C7E6CF03FDE5D8FC7DFF0FDCAF64E18E168",
INIT_03 => X"F5F1F4FE643A606DDBEC5FB655B5E313F3E98BF7981EE1683B6E0930EF7EB9CB",
INIT_04 => X"35233FE0615EFBB7FF5B2FF7C7FEBC12F8FF0187FBFF077E79C519FCFF827FFF",
INIT_05 => X"9FDAAE5FD4598C18F8FEAA3C63FF3971A74CC0FCFFF841E7E21A7F9C5D937C7F",
INIT_06 => X"7CFE7F895FFF38ECE7B9A0FFFFFC0FE3B3017E6030C3B0764A81FFDDA5AD7F17",
INIT_07 => X"1383817FFFFFF1EFC785FE9D5ABF87F5F6B9FF45A7CEF61F9CDFEEFFFF918606",
INIT_08 => X"F4801C1E5B7F90F23635FEA87ADFF7BFF4EA7FFFE79E4239FCFF653EEDFF9E5D",
INIT_09 => X"2DB3EBD874EFFE7FF1DE6FF7F4C1C23C3FFFC71F9DFFC947B3D8CD7FFFFF884B",
INIT_0A => X"FCE3EFD7FFA3F33CAFFFF4DB0B9FF554392C911FFFFF3F9DF544CC0145E7B4F0",
INIT_0B => X"CFFFEF4AF91F8B09056FB6CFFFFFD3A3F441C03A4227ABF0AD17DEE26BCFFEBE",
INIT_0C => X"812698E7FFFFEFF9F3B9602DF12781F6B131C4F92C5FFD7EF0BFEFFFFC63BF1E",
INIT_0D => X"E14D3EEAB7F7C5F7FFCFDF3E073FFDECF785EFDFDF608E1BDFFFCB76878FF3E1",
INIT_0E => X"7E3FA81371781CEC7D41FF8FCFED7C598FFFE5D99D2FCD86F21446B5FFFFFB45",
INIT_0F => X"E569FF978FB5EE0FE63FF633FA8FF0D94415C6BAFFFFFFF3C496FF49FD5353F0",
INIT_10 => X"C73FF3AA0C3FE56F23F3F8A37FFFFF07C492F2BAC550B3ECFEF78F947FD8320F",
INIT_11 => X"8A00D3B19FFFFF63E896F28441F173FF70CF985B0E78288FF6D7FF078F33D776",
INIT_12 => X"F9AEFC37C2C283CF54BF8557003E1F3FF8DBFF17FFBADF8865FFFE06DE1FFF70",
INIT_13 => X"7F7C475D803E1CBFF907FD07FF4EC5C18FFFF9C62617F708F6F762B28FFFFFE3",
INIT_14 => X"F8DFFDAEFF99739F45F888691B5FFBF5C11579096FFFFFFBFBB8F17EF4FA65AE",
INIT_15 => X"A6F8BAF929EDFC126C660493E7FFFFF1F357DEAD64FA65168B7E180A90BF75BE",
INIT_16 => X"5220E5D4B3FFFFFFF76B90446ABEB953C34CF5385C3F47BCC7BFFE2EFF90FFA4",
INIT_17 => X"EEAF0E440C7A43DE8C81CCC37F7FBF9F214FFB6FFFF7BC3DE2FCB68A39EFFF2D",
INIT_18 => X"F2C737D95B1FA94FCB3FF9473FFBC07489F6A2C38DDFFFAAE1C4195337FFFFFF",
INIT_19 => X"B75FF4273F92DF9B4CE79E25B9D7FFCA7414C82917FFFFFFECAAB39A3AF636FB",
INIT_1A => X"82079C030A27FFE4768B45150BFFFFFFEC0B775A5FF6D7384E5639E348BC8A37",
INIT_1B => X"86C5A51A0BFFFFFFC44CD70283F6970FADBDE46FBF7C01D293CFF2F33F8604D1",
INIT_1C => X"CDCF28057BF237E0AAE9DC342DBC4B7B424A7CEEFFF4291FB437CE058CCFFFF3",
INIT_1D => X"390AC76A137FEC56558B0B86FF3D57F9ED67CF0335AFFFFB8B22A01919FFFFFF",
INIT_1E => X"DAFF804CFFFB57B924FBEF0336BFFFFCA4A15F38D9FFFFFFCA9C283DF3FAEFB7",
INIT_1F => X"8793F1838AFFFFFF255057FC65FFFFFF9578A8C2C7F20F9C4B44CD8A1872CD3A",
INIT_20 => X"282850CCD5FFFFFFB16070CCA7F34F6CDEEAA9B7B06413DFE5DE7AE4F838A46E",
INIT_21 => X"EBA0B0B81FF3EF15CF06ABF6AA3CACBEE8DCA9DFE6BA8962EF91F8624E77FFFF",
INIT_22 => X"70193A7C0A1D66F97EC0655AEA5E4606A19DFF80E2CCFFFF30D45C06E9FFFFFF",
INIT_23 => X"C702F14DD4DF3245539CFFE011FDFFFF302A4C63E9FFFFFFBD8282567FF0FF07",
INIT_24 => X"147AFFF8B154FFFF30E52EF3CAFFFFFFBD8488EDFFF1E79A0051B2BD7574EAAD",
INIT_25 => X"4118B718CAFFFFFFB9E2A9F9FFE1E798350BB0BB3DA30FE843BD361F9ADE1366",
INIT_26 => X"B8E313D1FFE3E396DA4770841D1A7E4C577C5388065FA9D6E7FFFFFE61C4FFFF",
INIT_27 => X"E696E03AB37F71ACA1BEBE80055E2EA748327FFF1082FFFFB6E690CF4AFFFFFF",
INIT_28 => X"B737430E19BE8E3811B27FFF857AFFFFD90D10C72AFFFFFFBCE3ADDBFF03E39D",
INIT_29 => X"7EB57FFFF7FAFFFFE6D9D80FAAFFFFFFA7E0B7A3FE33E39E19144824B2ACAF4F",
INIT_2A => X"FFFFFFFFFFFFFFFFA76D2853FC37E3E6F5CF3D435BD04CD82F3FE31A9FBF517B",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFBF7FDFAFF7FFFEEFFFF7FFFFFE3FFFFFFFFFFFCFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFEF8FFFFFFFFFFF7FFFFFFFFFFF7FFE1FF10717FFFE9013EE0C7BBCD34FFFF",
INIT_03 => X"F3FFFFFFFFE7D3FFD9FE36257FFFF91FFEC03A8C7BDF4FFFFFFFFF9CBFCF9FEB",
INIT_04 => X"FFFC79B38FFFF80F10001600F7D7000FFDF01FE3FFC397E7EF7FF9FFFFFFFFFF",
INIT_05 => X"A000C2133FEF31C3F8E01FFF1FF3FFFFE7FFE7FFFFFFFFFFF3FFFFFFDFE7F3FF",
INIT_06 => X"F80CFFFF9FFFFDFF73FFFFFFFBFFFFFFFBFFFFFFFFC7FFFFA1F8FE531CFFC201",
INIT_07 => X"F7FFFFFFFBFFFFFFFBFFFFFFFFFFCFBFA09DE027E23FFBFBA0FFE00EEBE3FDFD",
INIT_08 => X"FBFFFFFFFFFEEFFDB9CFFD2ACD1CFA7F07FF19FFEBF3FFF9FC31FFFF9FFFFFFF",
INIT_09 => X"86CD9F1A052D5F831FFE091FE7FEFFFEFCF3FFF1DFFFFCFBFF97FFFFFFF3FFFF",
INIT_0A => X"1B000E7FFDBE1BFFF5E7FF00FCFF8BB1DFFFFFFFFFFFFFFFF3FFFFFFFFFF7FFF",
INIT_0B => X"232FFC00AE38C2A4CE7FFFFFFEDF7FFFFBFFFFFFFFEFFFFFFE90E22120238E31",
INIT_0C => X"FCFFFFFFFEFF3FFFFBFFFFFFF7EFFFFFFC7809C6B68D0F07B8000E7FDFDFC7FF",
INIT_0D => X"FFFFFFFFE7BFFFFFDF3E03402522FFAEF000007FCFCFEFEFBFFF80C03FFF30E7",
INIT_0E => X"FF0FD829BC4CFED8E0FF07FFCCECFFFFF6D71E861FFFF8FFFFFFFFFFFEFE7FFF",
INIT_0F => X"41FF1FFF99FD7FFFC6F0FE1E07DFFCFFFFFC1FFFFFFB7FFFFFFFFFFFE7DFFFFF",
INIT_10 => X"BBF5F07E4F9830FF7FFB8FFFFFE7FFFFFEFFFFFFF7BFFCFF8F8458A813C9FFF8",
INIT_11 => X"E7FFFFFFFFCFFDFFFCFFFFFFFF3FFDFF81CD801FA619FFE601FFFFFFBFFE1FF7",
INIT_12 => X"FD7FFFFFFF47FFFF808F804E0111F3FB837FFFFFFCFFCDFB7CE70FFC3EF830FF",
INIT_13 => X"9F220708012FFFFF03FFFFFF7BDF7C39FFF7CFFF3AB7CC7DF3F3FFFFFF7FFBFF",
INIT_14 => X"41FFFFFFFBFF9BDFFF67D7CF3B73E53CFFEB9FE7F97FF9FFFF8FFFFFBC83FFFF",
INIT_15 => X"FE3CD8FF3DFBFDFF7FF7C7C7F87EFBFFFFFFFFFF7FCDFFFFB0F301FE396AFFFE",
INIT_16 => X"CFCFE3FFFFFFFDFFF3FFFFFFF7F5FFFFED07E51F2F8E5FFE01FFFFFFF3FFFFFF",
INIT_17 => X"F5FFFFFFFFFFFFFF967F8A0F1FA8D7FFB7FFFFFFFFFFFFFFFF5A2C903FF7F3FF",
INIT_18 => X"F93BC6073FD0C7FFF7FFFFFF7FFFFFFFFF5B4F421BF3EBFFEBFFF7FE9FFFF3FF",
INIT_19 => X"E3FFFFFF7CFFFFFFFFDD3163C1FBEFF6EDFE7FFE0FE6FBFFF5FFFFFFDFFFCFFF",
INIT_1A => X"FFFFEC12C7FDFEFFF07D7FFF1FFFF3FFF1FEFFFF7FDFFFFF80D240C237F2D3FF",
INIT_1B => X"FE1FFC1FFFFFE7FFFBEEFFFFFFFFBFFF803DEA4F73F60FFFF9FFFFFE79E3EFFF",
INIT_1C => X"FFEEFFFBFFFFBFFF82FEB34DFF468B7FFFFFFFFE73F7F7FCFFFEFF59C77FFEF8",
INIT_1D => X"83B942757F4101FFFE3FFFFE7AFEF3FEFF8EFFDDE1F9EFF9FFC7BE9FFFFFE7FF",
INIT_1E => X"FF9FFFFF7F7FFBFEFE8FFFFEF07AEFCFFF839FFF7E78AFFFFFFEFFF3FFFF7DFF",
INIT_1F => X"FF79FFFFFB7EF3FFFFFF9FFEFCFEDFFFFFFFFFF3FFFEFFFFBF3C61B4118084FF",
INIT_20 => X"FFFFFFFCF97F17FFF3FFFFEFFFF9FBFFC03F9EF87D80E1FFFF9CFFFFBE7E787F",
INIT_21 => X"E3FFFFDBFFFBF1FFFFFFE3DE64003183BF607FFFDF9FBCBF3F79FE7F7F3FFFFF",
INIT_22 => X"FFFFD8BC457F18C03D1D81FF4FC79F3F9FFFFE3FFC47FBDFE7FEFFF9F3FFC7FF",
INIT_23 => X"7D2F3C1F87EBDFFC9F3FFFFFCC57EFCC67C67FFCDEF81FFFCF8FEFA7FFFBF3FF",
INIT_24 => X"CF3F7FFFD85BC3E07BC7FFFF8FF01FFFCF57E31FFFFFE7FFFFFFE5ACD9FFB3E3",
INIT_25 => X"F87FFFFFC6FF3BEF9F9FFFFFFFFFDFFFBFFFF92292FDA024FE13E3CF63F5FFFF",
INIT_26 => X"BFFFFFFFBFFFD7FFE7FFFF327DFFE00BBC7E1E67FDFFEFEFFFAF3FFFEE5E1FF7",
INIT_27 => X"98FFFCCE607FE003FE41E799F9FFBFECFFAFDDFFF7C3071FFBFFEF0BFFFFBFFF",
INIT_28 => X"FAE33071F5FF9FFA7C9FC5FFF2CB0F7FFE7F0CB3FFFE3FFFFCFE7FFFFFFFE3FF",
INIT_29 => X"FE7FC83FF966EF7FFCFF7DB8FFFF9FFFFBFFFFFFFFBEFAFFDFDFFFDFE5E7F144",
INIT_2A => X"FE7F7DFEBCFB7FFE7FFFFFFFFFD1FDBFDD5FFFBFFD7EF1F73FF04FFE72FFDFF8",
INIT_2B => X"FFFEF9FFFFDCFFFFEC9FFFFFFD6D4FD8FFFC8F0FFBDFDEFFFF7FDDFFFD1C16FF",
INIT_2C => X"EF1A7FFFFFFB7FF0FF7D1C607BBBFF7FFFFFFFB7FFB082FFF8FFFFFFE1F97FFF",
INIT_2D => X"3F3F1F9EFBFDFF7FFFFFFFE7FFF16FFFCCF87E03FFFCFFFFF7FC78FFFFBC7F9F",
INIT_2E => X"FFFDCFF7BFD28FFFD1FB7E6BFCFCFFFFC7FEFAFFF87EFFCFB410B9FFFFFF9E3D",
INIT_2F => X"CD72FD3F7CF0FFFFEFFFFAFFFEFEFFF3B34941BFFFFFD43CFFFFFFC13A9C1C1F",
INIT_30 => X"BFFFFCFFFFFCFFEBFFDBED3FFFFDF5B2FDFFF8DE4BBE9FFFCFFFFFF7F7EEFFFF",
INIT_31 => X"9F43171B3FC0F217FFFFF8FF1FFFDFE7CFFFF3FFFEB57FFFFDA3FD7D7DF97FFE",
INIT_32 => X"FFFB3F3FE3FFEFE7E7F7FC7FFF8B3FFFFDE2FAFC7FD87FFE7FFFFDFFFFF9FFF7",
INIT_33 => X"7FF7FF3FFFFDBFFFF8A0F6FFFFF87FFE7FFFFCFFFCFBFFFFBAD2F10607931BBF",
INIT_34 => X"F29DE0FFEB9F7FFFFFFFFAFFFAF7FFFB8ECAD2B23FCFFFFFFFF83F7FFFFFFDF9",
INIT_35 => X"BF7938FFE127BFF9F76D78691BDFFFFFFFF9FF0FF9FFFF78B9FFFF3FFFFCBFFF",
INIT_36 => X"F787021C8FDFFFFFFFFFFFA9F8FFDDFFFAFF9FE1FFFD7FFE3D9FCC7FF7CFFFFF",
INIT_37 => X"FFFFFFD9FD7FCEBDFEFF1FF7FFFCBFF66C2FDC7FF3DDFFFF3FF99FFFE7073FF9",
INIT_38 => X"F8FFBFF3FFFD11209FD7F57FE57BFFFFBFFFDFFFF6B7FFFFF9EC38CFFFFFFEDF",
INIT_39 => X"62B3DFFFEB4BFFFFDE3FDFFF7E3FFEFF8C6FDBA7B01EFC3FFFFFFFF4FDBFCF1D",
INIT_3A => X"CEFFCFFFEF3FFFFF80079FCFB8F23BFFFFFFFFF23EFFCFAFFFFFFFF8FFFC523B",
INIT_3B => X"F39FDFF6BAF8589FFFFFFDFC7F3FFFEFFEFFFFFC7FF9D5C9364CFFFFFFCBFFFF",
INIT_3C => X"FFFFFFFF0FDFFFAFFE7FFFF07FFE27ACFC168FFFFEFCFFFFDFFFF7FFDEDFFFFF",
INIT_3D => X"FF3FFDF67D3A763D09718FFFE77CFFFFCFFFCFFFFEDFFFC7C09CADBEE78D587F",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"64804FFFF735FFFFEFFFFFFFD7FFFF879EFC6EBDF906FC7FBFFE1FFF37EF7FC7",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"1CF7FFFFD0FFFF9F865A4FFFFAB9F9009FFFDFFFB7C37FCFFF19FCED7ABE4AF9"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"C3145FFE7FFEF80CC7FFFFFFC7E1FFE9FFFCFB0D02FFCBF6649E3FFFED37FFFF",
INIT_01 => X"EBFFFFFFF3F1FFE1FFFDFBFDE7B30FF4FC16DFFFF8F9FFFF3CE7BFFF967FFFF9",
INIT_02 => X"FFFDFB0979233FF4F93C3FFFFFE7FFFFFCF73FFFDDFFF8FBF6717DF7BFFF3C00",
INIT_03 => X"EC36BFFFFFE3FFFFFEE7FFFF7BFFF6FFF5FAEBF38FFFFC79F87FFBFFF9F3FEFD",
INIT_04 => X"FFEFFFFFE3FFF9FFFA78FFFF9F5FF8FFFC3FF8FFF8E3FF7FFFFFFA043102BFF4",
INIT_05 => X"FF67FFFF8F81C07FC3DFFCFFFE1F7FFFFF3C7817DDC107F605C25FFFEE63FFFF",
INIT_06 => X"C1FFFFFFFF1F3FFFFF1E3655EB0B03F30BF84FFFFA57FFFFCFFFFFFF21FFFFF3",
INIT_07 => X"FF3FB4BABB1603F38D9C2FFFEF07FFFFCFFDFFFFABFFFFE3AF673CFFC3D1D613",
INIT_08 => X"150C6FFFD70FFFFFFFFDFFFFEFFFFFD7FF88E5C1E1FFC3901BFFFFFFFFDF9FFC",
INIT_09 => X"FEF9FFFCF7FFFF87FD8FFBED6F3F3FFC87F07FFFFFC7CDFCFFFFF8C0B838DFF3",
INIT_0A => X"FFF901F1561F3FFFC3F71FFFFFF5EAFEFFFFBBFB95F0FFF73A714FFF8E1FFFFF",
INIT_0B => X"FEE3C7FFFFFBF9FFFFF837EA03F0CFEF2300DFFFC9BFFFFFFEF9FFFFDFFFFE7F",
INIT_0C => X"FFF9F9E60783EBCEF50FBFFCE99FFFFFFFFBFFF87FFF3EFFC03987FF8F1DBFFF",
INIT_0D => X"A27E7FFFBBF3FFFFFFFFFFFA0FFFF6FFB7C7E3000D4537FFFF1FEDFFFFFD70BF",
INIT_0E => X"F9FFFFF39FFFF3FF80FFFFFF38A337FFFF9FF6FFFFBFDE1E7FFFFF9A6FDF8990",
INIT_0F => X"9EFF07F61C2FDFFFEFAFF87FFF9FC9EE3FFFFE3D0FFF666748F8FFFF7DF7FFFF",
INIT_10 => X"FFDFFE3FFFBFD8307F7FFE74108D678E961DFFF8F13FFFFFF99FFFB81FFFF7FF",
INIT_11 => X"FFEFF344E288F97C9419FFFFF0FFFFFFCF1FFFA15FFFFCFFF07FFFFFFFCF9FFF",
INIT_12 => X"1C1BFFFFEFFFFFFFDFFFFF781FFF3FFFE001FFFE200E1FFFFFFF3F57FFFFF0DA",
INIT_13 => X"7FFFFF4AFFFF3FFFC1FC03E100032BFFFFFF83BBFFFFFD443FFFF3E1B58B805D",
INIT_14 => X"E1E603C7F80A01FFFFFFFA17FFFFFDB33B0FE22943CE04CCC81BFFFFC4FFFFFE",
INIT_15 => X"FFFFFBFCFFFCFEF3E311E3110E7E9CBAA8FBFFFFFDFFFFFF7FFFFFE6F7FE7FFF",
INIT_16 => X"00D1E7BAF51B779811FBFFFF9DFFFFFFFFFFFF9E7FFE7FFFBEC60387F8FE36FF",
INIT_17 => X"51C8FFFF9FFFFFFEFFFFFF8BFFFE7FFF86CC07C000FDF67FFFFFFFF7DFFC7F3E",
INIT_18 => X"FFFFFF82FFFEFFFFB87BFFFF01F66DBFFFFFFFF66FFF7FDDE32FE3A1FE18B324",
INIT_19 => X"C87B811D01F8F49FFFFFFFFFBBFFFFDE5E1FF3139065A20770067FFFC9FFFFFF",
INIT_1A => X"FFFFFFFFEEFFFFF7CFDFFC1E9059D2E56016BBFF23FFFFFFFFFFFFDFFFF89FCF",
INIT_1B => X"F7FFFF4202CB2E7960005BFF4BFFFFE3FFFFFF9D7FF63FFFE58400058BFF3AD7",
INIT_1C => X"F8039BFF27FFFFE3FFFFFF9E7FEFFFFFC3C19E0FFFFFB917FFFFFFFFF3BFFFFB",
INIT_1D => X"FFFFFF07FFE7FFFDF0C0231FFF00FFEFFFFFFFFFFCEFFFFDC3FFFF0408622D22",
INIT_1E => X"8C1FC338FF802BC9BFFFFFFFFFDFFFFFC2FFF8A2B004DDE4FF159FFFDFFFFFFF",
INIT_1F => X"1FFFFF9FFFEAFFFFB17FFC088597D564E0C4BFFFEFFFFFFFFFFFFC05FFFFFFF3",
INIT_20 => X"F6BFFFE548FBF5F4E1FF5FFE0FFFFFFFFFFFFF2EFFFFFFF985E7913000905351",
INIT_21 => X"3C255EFE3FFFFFFFFFFFF9DFFFFEFFD1B878F338000000C3FFFFFFFFFFFC5FFF",
INIT_22 => X"FFFFD819FFFDFF29BBC0671E000603CC177FFFFFFFFD18FFF15FFFD75C613DC4",
INIT_23 => X"FFFF0F0F00868D8898BFFFFFFFFF9DFFFCBFF9CFAD7679C41CC77EFFBFFFFFFF",
INIT_24 => X"DCDFFF7FFFFFF27FFFAFFAF8628753C75F025FFF7FFFFFFFFFFFC357FFFFFE1B",
INIT_25 => X"9FDFF9EC949E576360805FFC7FFFFFFFFFFFDBF7FFFFFD07BFC5E801FFC619BB",
INIT_26 => X"CE3487FE1FFFFFFFFFFFCC77FFFFF8939FC53C000DDC797B8E1FFE7FFFFFF381",
INIT_27 => X"FFFFFD6BFFFFE37F80FBB8000400F2818739FCEFFFFFFD45FF1FFF873A99D7EC",
INIT_28 => X"F8001BF801E6BFDBF8FFC7E7FFFFFFC67F87FFDF465A37E38F39CFE81FFFFFFF",
INIT_29 => X"FFFD0FFFFFFFFF38BF8BFFFF42A3E0CF6C72FF13DFFFFFFFFFFFBD6FFFFFD67F",
INIT_2A => X"CFEE0FFF82DFCF8C6272FE6FDFFFFFFFFFFFFD67FFFE07FFFD0037FC0343F358",
INIT_2B => X"1ABAFECECFFF83FFFFFF7CEFFFFC8FFFC10013FC070DC735FFFFFFFFFFFFFFC0",
INIT_2C => X"FFFFFFEFFFFA1FFF80000FFFE12B0432FFFFFFF2FFFFFFFE37EE223F03E3CF72",
INIT_2D => X"98007FFFE9C3FDBEFFE7FFFBFFDFFFFF27EED83F71B0C8FE385FFC3C67FE01FF",
INIT_2E => X"01FFFFE7CFCFFFFFCAF5C67DB8518E4C2B4CFDF1EFF8F9FFFFFF93CFFFFFFEFF",
INIT_2F => X"EBFC177DD10FA6F12800FB43EFF0C9FFFFFBF3CFFFFFFFFFFF80FFFFE96DB55D",
INIT_30 => X"EB403A43EFE785FFFFF6CBE7FFFFFFFFFFFDFF7FE4873D48E0E39F8FE5FFFFFF",
INIT_31 => X"FFFAEBFFFFFFFFFFFC0FFE3FD73999B050339FC7F3FFFFFFF77B2E5755381ED8",
INIT_32 => X"FC00FC9F80005467BC3FDFF7B97FFFFFFF03C335A7C7A59D4326D8B70FCC00FF",
INIT_33 => X"BC7FDFFF888FFFFFFFD8EF130F0216561AA7E75F0FCBC8FFFFD933FFFFFFFFFF",
INIT_34 => X"FFF1DD2C3FB3D0528A6328982FD648FFFF9E03FFFFFFFFFFE280780383F0C4F0",
INIT_35 => X"C6F73CA0EFD58DFFFF0DAFFFFFFFFFFF85C07CF181E751C2E0FF8FFF98F7FFFF",
INIT_36 => X"FFC9C7FFFFFFFFFF833C7F60E0FC9E809DFCF43F3331BFFFFFE82CCC2F5DD433",
INIT_37 => X"FF1FFF81F06B5480FDFFFE02E0E93FFFFFFDC122A773A596195362772F95DDFF",
INIT_38 => X"20F6FFF8C010D7FFFFFE7EBC238F006EC2B3DD5BAFB8D7FFFF57CFFFFFFFFFFF",
INIT_39 => X"FFF0A3853F30964EA81F8F3E2F5427FFFEDE1FFFFFFFFFFFE69F00FFFC08BFE3",
INIT_3A => X"71145AB0C4A24FFFF3FE7FFFFFFFFFFF9E8E00007CE36598FFC63FF8F931CFFF",
INIT_3B => X"B97FFFFFFFFFFFFF9C0000001914F76FFFFF7F1FF67C7BFFDFE1F3799CC43144",
INIT_3C => X"F00300001A988F9FFFFFFF1DF31DAEC387FCFB9E66DE9A708F707B50C1D09FFF",
INIT_3D => X"FFFFFFFC0A1D08C2DBFB7BF1666541F0E6A324DC45DFBFFF21FFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"9FFD7A3F035688F09FD8EC398932BFF3C9FFFFFFFFFFFBFFFBE300001A10FFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BAC604DE3E023FCB9BFFFFFFFFFFF9FF81F0000034E7FFFFFFFFA3FFFE6D083E"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B7FFFFFFFFFFFCFFE01E000069E7FFFFFFFFBBFFFF2799F99FFE7C00F3A9F4EC",
INIT_01 => X"F80F00004EBFFFFFFF3FFFFFFFF73009D7F0FC00DED173C2DB4A12717F4D3F33",
INIT_02 => X"FF7FFFFFFFF752607ABFFF45BFC9D59C265C263FF2333E4FAFFFFFFFFFFFFFFF",
INIT_03 => X"F176FF648695D1B17E5E483C45397D519FFFFFFFFFFFFF3FFFBF0019317FFFFF",
INIT_04 => X"03DB537E1F9D62477FFFFFFFFFFFFFFDDFFE033C28FFFFFFFFFFFFFFFFFFFE60",
INIT_05 => X"FFFFFFFFFFFFFFFFFF000103887FFFFFFFFFFFFFFFFFFC97FFFEFD6C423435AF",
INIT_06 => X"FE00001D00FFFFFFFFFFFFFFFFFFFF601FFFFF62C2794BE483582771D3F60616",
INIT_07 => X"FFFFFFFFFFFFF0F8F0FBFF60039CA3379E18A7C86F780EA5FFFFFFFFFFFFFFFF",
INIT_08 => X"FE1FFF40E1DE10FA5651AF8F3B7CA589FFFFFFFFFFFFFFF9BF000FFED03FFFFF",
INIT_09 => X"BEC068F4B975ADCBFFFFFCFFFFFFFFEBBF01FC0EFB7FFFFFFFFFFFFFFFFFFF7C",
INIT_0A => X"FFFF803FFFFFFF7BFFFF834CDF7FFFFFFFFFFFFFFFFFFFE03C03FF8001ABFAE4",
INIT_0B => X"FFFE02B6FE7EFFFD3F9FFFFFFFFFFFFEDC017F80619F3ABD75C0F2FF9366B337",
INIT_0C => X"E11F7FFFFFFFFFFFE81C1F708FF8E8D2FB4A731CDF99C84FFFFF7E3FFFFFDE61",
INIT_0D => X"EDF81FFC1F0D7867F54B797EF0F6F067FF00CE7FFFFF04F9BE3FE4634E237FFE",
INIT_0E => X"3501C95B10D7078DF3DFF8FFFFFC83FBFE0045677FD87D0E3FFDFFFFFF9FFFFF",
INIT_0F => X"EE3BE3FFFFFC3FF7FF38E71FFFFFBC1FFFC001038F07FFFFFFE3FEFE1C0EB4E2",
INIT_10 => X"FE4F7FFFFFFF9FFFFFFB80FFC3F3FFFFF9C3FC3FF09662021901930C1CCC3C3A",
INIT_11 => X"FFFFF00FCF03FFFFF463FC3FF3982E091000422A063831C7A645CFFFFFF8FF35",
INIT_12 => X"C19FFC7FF381B053100003AF305CD3FECD958FFFFFC0FD77F918FF7DBAFF017F",
INIT_13 => X"90903E2C43202B1287391FFFFE3E78E18CF0FEEC5600831FFF0011FFFFFFFFFF",
INIT_14 => X"2EA47FFFF9FE32CDEC77FBFE0C0F7800078FBFFFFFFFFFFFC987F83FF396081A",
INIT_15 => X"D077061801FEF9FFF077FFFFFFFFFFFFC033F03FF02263A3A6913D31248313D8",
INIT_16 => X"FF5FFFFFFFFFFFFEC203FB19F9F1157620CA2B08B27F975F615EFFFFFF181833",
INIT_17 => X"F207FFB0FFE49FB3C08C438A4C7FCDFF2750FFFFF7600683B81134721F83F8FF",
INIT_18 => X"319CC81123F34B3FACAFFFFFEDFCC303FF383CE3FF8000EE1C7FFFFFFFFFFFF9",
INIT_19 => X"D75FFFFFE70C41B3FE99DE0B3F9C03AEBFFFFFFFFFFFFFF7071FFFF0FD07FC95",
INIT_1A => X"FF72D90B3F88462FFFFFFFFFFFFFFF9ADBBFFFF97ACC3828719C093A9FFEB783",
INIT_1B => X"FFFFFFFFFFFFFD9F8F67FFFFFA94BF51E0D852F67EDDA876A27FFFFFF3C03C53",
INIT_1C => X"9FA07FFFF2B0416DC0202D39FC518AE3F77FFFFFF40020DDFAFEF187C3C3457F",
INIT_1D => X"E4C03A4FFE0A3DD2D8BFFFFFFB021CE3FAB4B19FC3E3CAFFFFFFFFFFFFFFFCF6",
INIT_1E => X"9B3FFFFF10986149FCF05F344363C9FFFFFFFFFFFFFF7337FEC01F003F706610",
INIT_1F => X"FC7BA6B4633C85FFFFFFFFFFFFFE5F0FFFCFCE000CB9F12EE7C0C173FF3433CF",
INIT_20 => X"FFFFE7FFFFFD1BFFFFFC670222D3EBBD3FF907FFFFC621E92ABFFCE620D0E049",
INIT_21 => X"FF918F007F6F2F6A3FFCD5FFFFC8BCF8EBBFE36006078023FA4E5DAFF987B3FF",
INIT_22 => X"3E3897FFFFC023B31BFFFCF3A420C0BDE4464D03FE1FFFFEFFFFFF3FD9F045FF",
INIT_23 => X"F2017E74C613DC05BCA1F64DCBFFFFFEFFFFFF4FE7ECFFFFFFC17180659707C8",
INIT_24 => X"DF43FC4C9FFFFFFFFFFFFFE7FFF3FFFFFC9071C3542DC95BF07B5FBFD0A1922A",
INIT_25 => X"FFFFFFE3FFFFFFFFF8E37EC3625D9371E723BD3D30F255FB020C38620F1D6301",
INIT_26 => X"F1FDB02155B9B387EF86FE73D0F0A5F6841BFB3B03C88005E0E1C2DEDFFFFFFF",
INIT_27 => X"4FDFFFFD00BF9F79781A05C3879F000F9E74B23BFFFFC77FF7FFE3E7FBFF3FFF",
INIT_28 => X"3FB63A01FFFF0C0FFC71B78BFF776B43FFFFC3FF77F7FFFFE7FBBE31F1EBCC24",
INIT_29 => X"AE95C70FFFF70C07FFFFD8E76FF7FFFFA7F57D70C1D276BB4CDFFFE201FEFF79",
INIT_2A => X"FE7FFC601F2FF9FEFFEF2B30C637DB97C88FFFF79FFFFFC38CDFE807FFFF803F",
INIT_2B => X"3FD5253C19E04633C8DFFFCEC3FFFF0F307CD0FFFFFF087FBAC10E8FFFCFE1C3",
INIT_2C => X"D896C7A5BFFFF1F0DF38D7FFFFFF00FFA7A185BAFF1F0731FD9C004E1DDFF9FD",
INIT_2D => X"3030B7FFFFFF83FF96FFD200FCE0BC654F7FE01E31BFFFFEFFD2D37C87DDE829",
INIT_2E => X"F6A7DAE4FB1E0FAF600E98BB53FFFFF9FFD5F2F8ED1DF9CDCFCF3693FFFF980F",
INIT_2F => X"3887F03C97FFFFFFFFC3FFF8130344E98007DDFFFFFE83FF19CCC7FFFFFFFFFF",
INIT_30 => X"FFA3F43FBAFF9F378023CFFFFFE35CC34404FFFFFFFFFFFFEAA3331C0C381EBE",
INIT_31 => X"873887FFFFB3B7C1BC227FFFFFFFFFFFCFD7EBFB1CE073FC1FC0F0A8D7FFFFF7",
INIT_32 => X"785B3FFFFF8FFFFFD40117F773011CF93C0FC167F7FFFFDFFFB749FF7E00000F",
INIT_33 => X"C2FECBD404076EA30E04FFFF37FFFFFFFE9F2B3E5BE3799FFFF93FBFBE5DDB60",
INIT_34 => X"B8C5FFFEEFFFFFFFF83F430C515F7F741FFDFFFFF957C1392E7E7FFFFF78FFFF",
INIT_35 => X"F87EA26668A42FEECFFAFFFF1D5BE38CC6785FFDFCFF7FFF86BCEFB3796BAFC3",
INIT_36 => X"0FFA0F726063C1E5BE783FFDFD813FFF85BB9F2CC1CA3CC03D21FFFEFFFFF87F",
INIT_37 => X"FCBC043CF90CC1F98B43EF1D801B78DFF9F3FFFFFFFFFAFFFFFF6AE3E6ECC7CC",
INIT_38 => X"DB37BD3380F7FFDFF59FFFFFFFFFF2FFFFFFECE3FF90FCCC0FE4F86DABE479E7",
INIT_39 => X"8BFFFFFFF3FFFDFFFFFFBD085BD05CC30FC0E39A5804FFDFFD3AD88CE33E7C01",
INIT_3A => X"FFFF9A0005FFDFC387E07E665C74FFE9FEB2118FE61E7FFFD900626E1153FCDF",
INIT_3B => X"01FC3E6FC071FF8BCD1E0F8003060003DF9E11D8011FF19C77FFFFFFF1FFAFFF",
INIT_3C => X"2A920A8B37003F81F5D2B790075FFF075C7FFFFFFEFF5FFFFFFFD3C1D6E0E406",
INIT_3D => X"A4948C267D7F941B7FFFFFFFFFFC2FFFFFFF51E1E7EF000C00673F9FF31DFFA4",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFB1FFFFFFE05309B3EE8E5087B3FFFC33A7FF42FF474FBD70029E3",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFF13F08503CAE71E7FA3FFCFC03FEACC9575D3D30189EDA98200E640FF5FEC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"99FF39FFDF01FE640196EC48EA0386EDEEF801C2B0DDDF187FFFFFFFFFF079FF",
INIT_01 => X"C61E5F976E1F8CF3FB043F80BF7FF072BFFFFFFFFFE273FFFFFDDE9F2AADC6C3",
INIT_02 => X"BF44FF01FFBDF0077FFFFFFFFFF1FBFFFFFFDB9F6BA5044FC57FEBF9CE767D7F",
INIT_03 => X"FFFFFFFFFF24FFFFFFFEFBF15AB9EC572A3F45CD2E47363F8C310EC019FC02C5",
INIT_04 => X"FFFC7F3064836F8B3D3F3CB2D20ED67F9CC00F0F03F08FC7842DFC35D83CF877",
INIT_05 => X"D68335584BB6038173B113E7EC030FFF9587C03F518B88FFF7FFFFFFFF09FFFF",
INIT_06 => X"C39E20301806038FF50F8038395AEFFFFFFB7FFFF527FFFFFFFC5FF9BED36024",
INIT_07 => X"90CC00F7BA1A7FFFFFFC7FFFE32FFFFFFFFD7B8A32EABE7BDF8EA56B9C1B060A",
INIT_08 => X"FFFF7FFFC2EFFFFFFFF6FF5AE3A789FE98F5E89DF3FFD5A1B7CC6CE3003BF16F",
INIT_09 => X"FFEEFF709CD0DF3F267EF0C7F38C0FFFBFD6E4C00707C015A74B034E81E1FFFF",
INIT_0A => X"C2673077000A73FAD0392B800BE71877AC738637EE877FFFFFE3FFEF9EFFFFFF",
INIT_0B => X"28388480F87F3F81B8C312C7816FFFFFFC47FFFF019FFFFFFFF3FF9F4B236174",
INIT_0C => X"F6B1F01F8DFFFDFF3F31FFFE113FFFFFFFC3FFFE21ED8DF902B65C0E6196B7FC",
INIT_0D => X"BB01FFFC3FFFFFFFFFE3FFC9FFEDBFE773CE4C1CF0AD1BFF7C4089C07F67E3F9",
INIT_0E => X"FFDFFFD7DFD2A9C31A91E4F0E0164BFF25CF32607E47E03DD5492B1F99E3FFFF",
INIT_0F => X"95D030F107DD99FFE4D785388FEFFF01D26E6CFCFAEFFFFFF77BFFFA3C37FFFF",
INIT_10 => X"8C23CC1F9FFFFE31C2F380FC7BEFFFFFF06BFFF838E7FFFFFFA7FFABFFF7EBCB",
INIT_11 => X"A123617EFD7FFFFFAE6EFFFC38EFFFFFFFAFFF83FFFEEFFFC5E27D704C191DFF",
INIT_12 => X"226FEBFB4BFFFFFFFFBFFF05FFE817FFFBFFFF0FD3744DFE7B02FB7FFF7F78F3",
INIT_13 => X"FF7FFF4FFFA517FFF9FFFFFFF27FCDFDB64A8303FFFFF9FDEA3B7BFFFFFFFEFC",
INIT_14 => X"FAFF7EFF777D50B552ECC0E187FFF30DFA24F7BFFFFBF8F3DA1FF47791FFFFFD",
INIT_15 => X"F457667F80E38333F9EAD37FFFF305F80B7FADE7EBFFFFFCFFBF7F9D3FFE1FFF",
INIT_16 => X"99F63D7FFFC201607F7FD64FDFFFFFFFFE3F7D55BFE8C3FFFBDF7E6F1F7E1299",
INIT_17 => X"F57FCEFFBFFFFFFFFF1FFCD177F17BFF95B6FC6087C7E591370A404700000403",
INIT_18 => X"FEBFFE6D0775E3FFB24FFA600383EB6847211F8200C08C03C316F3F7FFFD0C00",
INIT_19 => X"ECE3FDE003E5B9F6BC3D21B06083CE7FC2E27FFFFE789C0067FFECE77FFFFF7F",
INIT_1A => X"3FF07DBFFEF34FFDC2623FFFFC7BB0308FFF41D37DFFF9FFFF7FF5F337A703FF",
INIT_1B => X"C33EF7FFBE909C183F7C4EC7FFFFC9FFFC7FFDD4F666B6FFEEA3FE9E667967FF",
INIT_1C => X"1FF1C6E4FFEFE9FFFF7FFFABDCE76AFFB7F5FE324F0157FFC510C18CF1DC07E1",
INIT_1D => X"FBFFFBC5CFEB26FFCBFDFE096317E7FFFE0E4FF00F63F1E7CFEABFFFF9E5E400",
INIT_1E => X"E39DFEEBE454B1FFFD00030BF4139FE7FFEBBFFFFFFFDF4EFFE6C7CAFFFFE5FF",
INIT_1F => X"FD7F7C9383B0DFC7FECBFFFFFFFFDD707FE20FF1FFFBCFFFFAFFFB5C304B88FF",
INIT_20 => X"F7D57FFFFF1DC961FFEC0FF7FFFF07FFF1FF1CACAE4C9FFFF01AFDFE6822B9FF",
INIT_21 => X"FFA31CDFFFF41FFFF5FE1784319BDDFFEF037F3A240B96FBC4F0BCCC273C63E3",
INIT_22 => X"FFFEBB8D4FBFD3FFF0669F3C250A5EFFD0F040931BC433F1E3CC7FFFFF9FC6AB",
INIT_23 => X"F812785FE3A539FFF80666C0B3041BF981AB7FFF3E8FC187FFE7BCAFF9F0BBFF",
INIT_24 => X"FEFE4F7E47300C3980747FFDE2403F0DFD67FFBFFDF18FFFFBFFFE6693EFF1FF",
INIT_25 => X"83AA003C5FC77C7F3E0BFF9FFFE40FFFFBFFE4F6D233D7FFB91644079875D0BF",
INIT_26 => X"F982831FFFFA87FFC7FFC189C717FBFFFF129491157F9093FD8399BEF1FCF2F3",
INIT_27 => X"F7BFD7F1C31FD9FFFCC5A81302632BD8FF231EEEC0FFFA07D8D7079FAF3CFFF8",
INIT_28 => X"FDCCA7FED3FF9270FF86060970FFFDF9D4C80054A9BF9FFC5FF9503BFFCB9FFF",
INIT_29 => X"7FFC11E8FFFFFE03CAE4B3A03A39860C8806DF7FFFB45FFF97FFDDFACCFFF3FF",
INIT_2A => X"B3D24354EED5F06ABF89C4A7FFCDFFFFFFFF02060CFF92FFFF8F278E23ECC463",
INIT_2B => X"7FFF66CFFF6FFFFF2FFEB3830887CE7FFFC0457A7A6B3AF3BFFFDA0B7FFFFFFF",
INIT_2C => X"37FDBB9A0807CF3FFF47D6D5D1E253D4BF7FFA7FFFFFFFFFCBA98F4F26E8385E",
INIT_2D => X"F7F08C03EE81439567FFE520FEFFFFFFC8AC04F4CB01BD6CCFFB38DFFCFEAFFF",
INIT_2E => X"73FFD060BFFFFFFFBCB19F03C0A1B22AB13C0FDFFD9D3FFF6EF8FB7D48F78CBF",
INIT_2F => X"F278BF4F5DEDBC789F02069FF8FBBFF65DFFF4457CB98FBFF3F0DF33FC72D23C",
INIT_30 => X"A93CFFFFF7FABFFE67D7EAF870AFE1B3FF9B6FB3F29D2E683EFFD6A81FFFFFFF",
INIT_31 => X"060FD7F971CF86EEE1C3D3B7FB3DE9EF167FC0AB5FFFFFFFBC071C87CD51E37B",
INIT_32 => X"95F27B2FFD222824C89FF760FFFFFFFFC07CD800F362ACFA2D3CCFFFB25E7FFD",
INIT_33 => X"E327FC4128FFFFFF80C3C87FFF0C3FF8F500363FD67FFFFF7FFFAB33F06987E0",
INIT_34 => X"C898E710F8ED67F9F3305E7F187AFFF96B7F57EF987AE55F05F0A993FC4562C4",
INIT_35 => X"F776DFFF9079FFF1627EA6FE901E6D403AF916AFFEC4A17C682BFFA341FFFFFF",
INIT_36 => X"77FF84E78014CDA439EF2EF3FF36A16034D3FFE5ECFFFFFFA0DC1F80010E0FFD",
INIT_37 => X"3C6CD098FF70002857BAFFFD7801FFFFD0C8F0C03FE2C3F9FF367FFE51FEFFFD",
INIT_38 => X"DA0A3FFF2218FFC1DD8100608D20E1F83E849FFEDFFEFFF36DFA41FD80184890",
INIT_39 => X"E2717F3F1920C0785EE2FF34DFDC7FF33FFD0BFF401738ECFE39E0E0FF7268B2",
INIT_3A => X"DAF1FF4ED8C0FFFEFF7C15FD580518F47FFFD700FF080507C46A4FFFC8330E2D",
INIT_3B => X"7FF9D5F0E00DF075BFBF16CCFFF6089A047DA7FFEA0FF5BFA8CF7E7FC5EDDCF8",
INIT_3C => X"7FBDF463FFFACC95687B57FFFAB00C4BD133077FE49ADCFFC6927FE59885FFFC",
INIT_3D => X"B093D3FF3F909023ADC5E11009E8F6FC7E58FFF87083FFCC7FFE3BF1B009F037",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"ADBAF1836C8EC2FCCAABFFF7E085FFFFFFFD2FF21009FC323FE1C625C7FA9F92",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"AD8AFFF20985FFAEFFE5AFF80C0FFE309FF403B36FFD4F9F5E9D99FFFFDDCA23"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B06A3C75506BFFFFFFFFE50EABFCFBF3CE5B6FE4FF005A940E43EA205006FFF8",
INIT_01 => X"FFEFFDA959FFF4F76CE450155550056A9FFFFFEFF00FC3E87EBFFFFE924FA550",
INIT_02 => X"CE5B7FE4FC00054FA500FC859006FFF88F2FBFE3FFFFF8A503F16ACFFFFFDF07",
INIT_03 => X"AFFFFFF40C0FB0FA2EBFFFFEA4E3EA5061AA41B6556BFFFFFFFFAA4F9B00EBEF",
INIT_04 => X"8C1FAAF7FFFFE4E543F06BCBFFFFCF2FFFEBF7A962FBFD7E2BE554155554016A",
INIT_05 => X"61A941B6A56AFFFFFFFFEAA4AB053BEBCEACBFE00000003E4000061AA406FFA4",
INIT_06 => X"FFFFEEA577FBFC3F8AF954015554016AFFFFFFFF4FC3AC3ED97FFFFFA4F7FE50",
INIT_07 => X"D3F1BFE40040FFFF4140186BE506FFA7401BFFF7EFFFE02543F06B0BFFFFCF3F",
INIT_08 => X"9FFFFFFFDEC3FC3F033FFFFFE4E40E55AC690061A41AFFFFFFFFFFFA3AB0FFAB",
INIT_09 => X"0F0B0FB7FFFFE0E54FF05892FFAF8A7FFFFFCE545BFFF53FE3E40001655555AA",
INIT_0A => X"BC55401C541BFFFFFFFFFFFE43AAACEBE556FFFA4000FFF080032CBFE4F6FFA2",
INIT_0B => X"FFFF8E55ABFFFA3FFCE944006A55556A9FFFFFFFA3BC4FF0007FFFFFE3A403FE",
INIT_0C => X"FAAAFFFE40003C00900061BFF406FFE23FC70FCBFFFF93950FF01AE5BFAF7CBF",
INIT_0D => X"DFFFFFFFF8AC4FC3F06FFFFFE3A5C0F0FC55501B101BFFFFFFFFFFFFA495613B",
INIT_0E => X"3F07FB2FFFFD3F950FF01FFABFFEE3FFFFFE3E5A3FFFFA3FFD9554006A955556",
INIT_0F => X"00555556C01AFFFFFFFFFFFFE4396CFFFFEAAAA9000000039401B1BFF906FFE6",
INIT_10 => X"FFD53A6CBFFFFA3FFED554015AA550158BFFFFFFFE2C4FFFAD6FFFFFE790FEB0",
INIT_11 => X"FFEA55550000000F9416F1BFF95BFFF74F06FB6FFFF4FA553FC15EFFFFFFBBFF",
INIT_12 => X"C7FFFFFFFFBB03FAB1AFFFFFE493EAB000555955B01AFFFFFFFFFFFFF90FAFBB",
INIT_13 => X"4C05BC6BFE50E9553F055AFFFFFA8FFFFF803961FFFFFA7FFF7A55555AA55006",
INIT_14 => X"0015AA40706AFFFFFFFFFFFFF93FFE57FFE94000F000000E955AB2FFF95BFFF8",
INIT_15 => X"FF8035B6FFFFFA7FFFDEA55555A55006C3FFFFFFFBCAF3FAF2BFFFFFE4D3EAF0",
INIT_16 => X"FFEA4003F0000FFA9556B2FFFA6BFFF84C05B05BF800E5553C1553FFFFF16FFF",
INIT_17 => X"F2FFFFFFFBD9F0FAADBFFFFFF9E3FFC30005AA4F71ABAFFFFFFFFFFFFE4FFA57",
INIT_18 => X"4C55BC6FF954E4140C1AA7FFFFFDFFFFFFD0F5B6FFFFF67FFFF8E55555555406",
INIT_19 => X"C005AA4C75BFABFFFFFFFFFFFF93E91BFFFA5003FC000FA95555B2FFFAAFFFE4",
INIT_1A => X"FFCFBAF6FFFFF67FFFFDE55A55555416ACBFFFFFFFEDB0396DAABFFFF923FC00",
INIT_1B => X"FFFE9503FFFCFFA51541B2FFEAAFFFE77C556C6FF800E400005AF7FFFFEA3FFF",
INIT_1C => X"6DFFFFFFFFE6750D6C69ABFFFE240000FF01A940B6FFA5AFFFFFFFFFFFF4EAAF",
INIT_1D => X"7C56B1BFF000E40F006FF7FFFFCABFFFFF8E9BF6FFFFE37FFFFFE5194005401A",
INIT_1E => X"3FF1A940B6FFA56BFFFFFFFFFFF93FFFFFFFA940FFFF3FA40005B6FFE9BFFFE7",
INIT_1F => X"FF795BCBFFFFD37FFFFF35590000001A6DFFFFFFFFE4B14EAC651BFFFE7903C3",
INIT_20 => X"FFFFA950FFFC0E500545B6FFA5BFFF933C56B6FFF3FFA43F006FCFFFFFF7BFFF",
INIT_21 => X"1CBFFFFFFFF9FD0FF154C6FFFF8E90FF0FFC5550B1BFA556FFFFFFFFFFFE953F",
INIT_22 => X"3C56CBFFF2BE94FA156C1FFFFF14BFFFF8E51F1FFFFFC07FFFFF75550303FF1A",
INIT_23 => X"C0FC5555B06AA555BFFFFFFFFFFFEA4FFFFFA940FFFC0E400555B6FE95BFFE4E",
INIT_24 => X"F7A51F3FFFFFB07FFFFF755503C3BFC5076FFFFFFFAA783FF050B6FFFF93E400",
INIT_25 => X"FFFEA500FFF039400556CBFA55BFFE393046DBFFF2A943EA15B02FFFFDB0FFFF",
INIT_26 => X"162FFFFFFFBEBB3FFC50B6FFFFE43900F03C0055FC16A551BFFFFFFFFFFFFF93",
INIT_27 => X"0001CBFFDD543EAF15B01FFFE770BFFFF7A46F7FFFFF717FFFFFCE5503C49BF0",
INIT_28 => X"F000005AFFC5AA50ABFFFFFFFFFFFFA7FFFAA400FF03E555555B1BFA41AFF9E5",
INIT_29 => X"E3A56F7FFFFF317FFFFFE2540EC096EC061FFFFFFFBFCBC3FF13B6FFFFF93943",
INIT_2A => X"FFFA943FFF0FA559955C6FFA41AFF8D01501CBFA34153ABC15B0C7FFDE73BFFF",
INIT_2B => X"C2F2FFFFFABF93C3FBC3B7FFFFFE4E903C003C5BFFF16A906BFFFFFFFFFFFFFF",
INIT_2C => X"1501CBE44F053AC055B033FFD383BFFD5395BF7FFFFB31BFFFFFF8E40EAF92EC",
INIT_2D => X"30500C6FABF05A956AFFFFFFFFFFFFFFFFEA90FAFF0E955A956DBFFA01BFE79F",
INIT_2E => X"A395F07FFFFA31BFFFFFFE770E5A91AFC697FFFFFAAFA8BFFAC3B7FFFFFE90E9",
INIT_2F => X"FFAA50EAFFFA955AAAB6FFFA46FF924F15068BE23FF13F0F55B073FFE3946FFD",
INIT_30 => X"C646BFFFFAABA9EBFFC3B6FFFFFFFA53415405AFFFC005A5AAFFFFFFFFFFFFFF",
INIT_31 => X"C5567BD90E6FFEBF55B15BFFE36041BF9351C1FFFFFD00BFFFFFFF74039695AF",
INIT_32 => X"959555AFF000016AAAFFFFFFFFFFFFFFFFAA50FABFFAA416AB2BFFEA56FF890F",
INIT_33 => X"5E41C6FFFFEDCF7FFFFFFE750395A96BF648BFFFFEABFA2ACFC3B6FFFFFFFFA4",
INIT_34 => X"FFAA50FAFFEA9416AC6FFFEA5AFF84000556B573F92EAAAB55B16FFF9E6CE8FE",
INIT_35 => X"B299BFFFFEAFFF89C3BFC7FFFFFFFFE9EAE5556AF03E005AAABFFFFFFFFFFFFF",
INIT_36 => X"515ABF9D556EAA6C606C6FFF8EB35DF90E41C6BFFFF8BE3FFFFFFF8A54EAA95B",
INIT_37 => X"003A555ABC3E0016AABFFFFFFFFFFFFFFFEA40FFFE955556B1BFFFEA6AFF8900",
INIT_38 => X"3E42053FFFFBBEEFFFFFFFD3A4A9A907A8486AFFFFABFFDD83AFCBFFFFFFFFF9",
INIT_39 => X"FFA900FFFA55555AF1BFFFFAAAFF89555156AA5D547DBAA1A01C7FFE7FBFA295",
INIT_3A => X"92B606FFFFAAFFE2C3EEC7FFFFFFFFFA550EA556BC000015AABFFFFFFFFFFFFF",
INIT_3B => X"5005FA5E55B8AA6C531DFFF9EBAFFBD63E461A7FFFF1BEEFFFFFFFE7A8D55506",
INIT_3C => X"A543A555AF0000155ABFFFFFFFFFFFFFFFA503FFFA55555AC6FFFFFAABFF9955",
INIT_3D => X"3E571BFFFFEDAE9FFFFFFFED59255501DC62B1BFFFAAFFF4FFEBB2FFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FE943FFFFA555AAB1BFFFFFAFFFF9D555516EA9355B86A6BFEDEFFF99BAF0BFA",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"906C6CBFFFFEFFF9ABFBADFFFFFFFFFFE543E955AF00000556AFFFFFFFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram : RAMB16_S4_S4
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"CBBBA9ABCDEFFFFFFEEEEDAAAABAACEFFFFFFFFFFFFFFEB9899A976665565445",
INIT_01 => X"9AA99ABCBBABAA875545676556556666566678ACDDEFFEEDBAAAAAABBCFFFFED",
INIT_02 => X"FFEEEDDCCBBBBBBBCBA9999999AAAABCDEEFFFFFFFFFFFEEFFFFFFFFFDBA9999",
INIT_03 => X"FEDDCCCCBBAA9999AABBCCCCCCCCCCDDCCDDEEFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"5555567789ABDEFFFFFFFFFFFFFFFFEECAABBAABBABDFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"CBBBAABCDDDEFFFFEEEEDCAAAACA9BDEFFFFFEEEEFFFFFCA889A987665566545",
INIT_06 => X"9AAAABCCDDCCB97655456755555566665667788ACDEEEEDCBA9A99ABBDFFFEDD",
INIT_07 => X"FEEEDDCCCCBBBBBBCCA999999AAAABCDEFFFFFFFFFFFFFEEFFFFFFFFFECAA998",
INIT_08 => X"FEDCCCCCBBBAA999AABBBBCCCCCCCCCDCCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"46666677789ABCEFFFFFFFFFFFFFFFFFDCBBBBAAAACEFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"CBBBAABCDEDDFFDDDDDDCABBBBCB9ACFFFFFEEDDEEFFFFECA89A976665566544",
INIT_0B => X"AAAABCDEEDDC9875555566555555567667766779BCEEEDCBB99A989BBDFFFEDC",
INIT_0C => X"FEDDDDDCCCCCCBABBCBA999AAABBCCDEFFFFFFFFFFFFFFFFFFFFFFFFFECBA988",
INIT_0D => X"FEDCCCCCCCBBAA99AABBBBCCCBBCCCCCCCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"45666667789ABCEFFFFFFFFFFFFFFFFFEDCBBBBAAABDFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"BBCCBBCDEEDDEDA9ABCCBABCCBCB99CEFFFEEDDDDEFFFFFDCA99876654566543",
INIT_10 => X"ABBBBCDEEDEDA875455566555655567666656567ABDEEDCBA99A999BBEFECCDC",
INIT_11 => X"FEDDDDDCCCCCCBBBBCBA9ABBBBBCCDEEFFFFFFFFFFFFFFFFFFFFFFFFFECA9988",
INIT_12 => X"FEDCCCCCCCCCBAA9AAABBBBCBBBBCCCCCCDDDEEFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"45666567889ABCDFFFFFFFFFFFFFFFFFEECBBBBBBABDFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"BBCCBCDEEEEFFDA78ABBA9BDDCCBA9BEFFFEDDCDDEFFFFFFECB9876544566544",
INIT_15 => X"ABBBCCDDEEFEA8654555665556555666665555679BCEEDBAA99A99ABCEFECEEC",
INIT_16 => X"FEDDDDDCCCCCCCBBABAAABCCCCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFECA9999",
INIT_17 => X"FEEDCCCCDDDCBBAA9AAABBBBBBBBBCCCCCDDDEEFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"44566556789ABCDEFFFFFFFFFFFFFFFFFEDCBBBBBABDFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"BBCBBCEFEDFFFDB88ACBAABDCCCCBABEFFFEDCCDEEFFFFFFEDBA887545656555",
INIT_1A => X"ABCCCDDEEEFEB865555566555666667765556678ABCCCCAAA8899ABDEEFFFFFB",
INIT_1B => X"FEDDDDDDCCCCCCBAAAAABCCCCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFECAA99A",
INIT_1C => X"FFEDDCCDDDDDCBAA9AAABBBBAABBBBBBCCDDDEEFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"54566666789ACDDEFFFFFFFFFFFFFFFFFFECBBBBAABDFFEFFFFFFFFFFFFFFFFF",
INIT_1E => X"ABBBBDFFEEFFECBAACCBAACECCCDCAADFFFEDCDDEEFFFFFFEDBA887645555555",
INIT_1F => X"ABCDDDDEEFFEC976555566555666677865457889BBBBBA999889ABCCDDDFFFFB",
INIT_20 => X"FEDDDDDDCCCCCCA99AABBCDCCCDDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFECA99AA",
INIT_21 => X"FFFEDDDDEEEDCBBAAAAABBBBAABBBBBBCCCDDEEFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"55567776689ACDDEFFFFFFFFFFFFFFFFFFEDCBBAA9ACEFEFFFFFFFFFFFFFFFFF",
INIT_23 => X"ABBBCEFFFFFFECCBCCCBABCDCCCDC99CFFFEDDDDEFFFFFFFDCB9777644444555",
INIT_24 => X"BCDDDEEEFFFEDA876555565556677788654579ABBCBBA999888AAAAAAACFFFCA",
INIT_25 => X"FEDEEDDDCCCCCBA99AABCCCCCDDEFFFFFFFFFFFFFFEEFFFFFFFFFFFFFECA999A",
INIT_26 => X"FFFFEDDEEEEDCCBAAAAAABBBBBBBBBBBBCCDDEEFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"55567777689ACDEEFFFFFFFFFFFFFFFFFFEDDCBA99ACEFEFFFFFFFFFFFFFFFFF",
INIT_28 => X"ABBCDFFFEFFFDBBBCCBAABCCCCCCCA9CFFFEDDDDEFFFFFFEDBA8888654444434",
INIT_29 => X"BCDDEEFFFFFECA876655555566777777655569BCCCCBA999989AAAA989BEFFBA",
INIT_2A => X"FEDEEDDDDCCCBAA9ABBCCDDDDDEEFFFFFFFFFFFFFFEEFFFFFFFFFFFFFECBA99A",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(3) => BU2_doutb(0),
DIA(2) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(3) => BU2_doutb(0),
DIB(2) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED,
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED,
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFE7FFFFFFFFFFFFFFFFFFFFFFCFFFFE00F004FFFFF7FFC0003FC433CFFFFF",
INIT_03 => X"FFFFFFFFFFFFEFFFE6000F833FFFE7E00000390037EFFFFFFFFFFFFE7FFFFFF7",
INIT_04 => X"C00006705FFFD7F000001E003FEFFFFFFFFFFFFC3FFFFFFFFFFFE7FFFFFFFFFF",
INIT_05 => X"0000020CF7F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFF3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000030FDFFFDFE",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC08000101EFFFC040000001FF7F7FFF3",
INIT_08 => X"FFFFFFFFFFFF1FFFC1C000193CE3FC000000E01FF7FFFFFFFFCFFFFFFFFFFCFF",
INIT_09 => X"F8C200F9FCCCBE800001F0FFF87DFFFFFF0FFFFFFFFFFE7FFFFFFFFFFFFFFFFF",
INIT_0A => X"04FFF1FFFE7FFFFFFE1FFFFFDFFFFC7FEFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFF",
INIT_0B => X"FC1FFFFFDFFF3DFFFFFFFFFFFF3FFFFFFFFFFFFFFFFFFFFF810F1DE08CCE7F30",
INIT_0C => X"FFFFFFFFFF3E7FFFFFFFFFFFFFDFFFFF8387FFC6478CFFC007FFF1FFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFDFFFFF80C1FFC7A6E1FFC10FFFFFFFFFFFFFFFC00FFF3FCFFFFFFF",
INIT_0E => X"80F027EE5FC3FFE71FFFFFFFF3F3FFFFB1EFE17FE7FFFFFFFFFFFFFFFFFC7FFF",
INIT_0F => X"BFFFFFFFFFFEFFFF81EF01FFFFFFFFFEFFFFFFFFFFFCFFFFFFFFFFFFFFBFFFFF",
INIT_10 => X"7DEE0FFFBFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFF078276FCFC7FFE7",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE307FFFE1F7FFE1FFFFFFFFFFFFFFF8",
INIT_12 => X"FFFFFFFFFFFFFFFFFF707FBE00F7FFE47FFFFFFFFFFFFE00FFFFFFFFFF3FFFFF",
INIT_13 => X"9FFDFFF800DBFFFCFFFFFFFFFFFF8007FCEFFFFFFC7FFFFFFFFFFFFFFFFFFDFF",
INIT_14 => X"FFFFFFFFFFFFFC3FFEFFEFFFFCFFFEFFFFF7FFFFFEFFFDFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FF7FE7FFFFF7FE7FFFCFFFFFFFFFFDFFFFFFFFFFFFF3FFFF80FCFFFE0099FFFE",
INIT_16 => X"FFFFFFFFFFFFFBFFFFFFFFFFFFFBFFFF9207FBFF107E3FFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FBFFFFFFFFFFFFFFFF800DFF006FCFFFCFFFFFFFFFFFFFFFFE3CCC7FFFFFFC7F",
INIT_18 => X"F9C407FF003FF7FFCFFFFFFFFFFFFFFFFEBC0F3DFFFFF4FFF7FFFFFFFFFFF9FF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFC11CFFFFF0F9F3FFFFFFFFFFF1FFFBFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFF0DF8FBE1F8FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF80EC06FE080ED7FF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF803E008F0C0E0BFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFF7FFF8003C87700BE08FFFFFFFFFFFFFFFFFFFFFFFF87F8F9E1FF",
INIT_1D => X"807D7E7F00BF017FFFFFFFFFFFFFFFFFFFFFFFE3FE7FF1FFFFFFFFFFFFFFEFFF",
INIT_1E => X"FFFFFFFFFEFEFFFFFFFFFFF1FFFFF1FFFFFFFFFFFFFFCFFFFFFFFFFFFFFFF9FF",
INIT_1F => X"FFFFFFFFFFFFE1FFFFFFFFFFFFFF2FFFFFFFFFFFFFFFF9FFC0FFBE78007F84FF",
INIT_20 => X"FFFFFFFFFEFFEFFFFFFFFFF3FFFFF9FFFFFFDF3F807FE0FFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFE7FFFFFBFFFFFFC33F98FFF07C7F9FFFFFBFFF7F7FFFFFFFFFFFDEEDFF",
INIT_22 => X"FFFFE0FE58FFF8C07E007FFFBFFFFFFFFFFFFFFFFF8FE9FFFFFFFFFFFCFFFFFF",
INIT_23 => X"FFEF03FF7FF7FFFFFFFFFFFFFF97EBFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFF9FF",
INIT_24 => X"FFFFFFFFE79BE7FFFFFFFFFFFFFFFFFFFF8FFFFFFFFFF9FFFFFFF9EEC0FFF3E0",
INIT_25 => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFFEFFFFFFFFDE361FDE023FDFFE03FFFFBDFFF",
INIT_26 => X"FEFFFFFFFFFF8FFF9FFFFDEC13FFE007FE7FFE1FFBFFDFFFFFFFFFFFF19DE7FF",
INIT_27 => X"87FFFEDFEFFFE0073981FF87FFFFCFFFFFDFE3FFF800FFFFFC7FFE07FFFF5FFF",
INIT_28 => X"3DFC3FF0FBFFFFFDFFFFFBFFFA30FFFFFC7FFE8FFFFF9FFFFFFFFFFFFFFF9FFF",
INIT_29 => X"FFFFFFFFFD181FFFFE7FFE7FFFFE3FFFFFFFFFFFFFFF3CFFC03FFE3FF7E7F1C3",
INIT_2A => X"FFFFFFFF7FFC3FFFFFFFFFFFFFBE7E7FC13FFFFFF9FEF1F07FFF8FFEFDFFFFFF",
INIT_2B => X"FFFFFFFFFFBF7F1FE0BFFFFFFE0C7FF8BFFFF00F003FFFFFFFFFFE0FFE000FFF",
INIT_2C => X"E0073FFFFFF1BFF0BFFEFF807BC7FEFFFFFFFFCFFF3001FFFFFFFFFFFFFC3FFF",
INIT_2D => X"7FFEFFE0FBC3FEFFFFFFFFFFFFB083FFF3FFFFFFFFFF7FFFFFFFFFFFFFFFFFCF",
INIT_2E => X"FFFFFFFFCFD1FFFFEEF0FE1FFFFF7FFFFFFFFDFFFFFFFFE7F3DF5FFFFFFFDE3C",
INIT_2F => X"FEE1FF7FFFFF7FFF9FFFFDFFFFFFFFE7F0EE20FFFFFFDC3DFFFFFFFE39FFFFFF",
INIT_30 => X"7FFFFFFFFFFFFFF7FFA31C1FFFFFDC31FFFFFFFF887FFFFFFFFFFFFFCFC1FFFF",
INIT_31 => X"E0C0AF07FFFFD98FFFFFFFFFE3FFFFFFFFFFFFFFFF48FFFFFE41FEFEFFEA7FFF",
INIT_32 => X"FFFFFEFFFFFFFFFFFFFFFFFFFFFD7FFFFE61FDFFFBF8FFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFF21F9FFF3D8FFFFFFFFFFFFFFFFFFFFC1F1DF000FEFE7FF",
INIT_34 => X"F903FFFFF7D0FFFF7FFFFDFFF1FFFFFFF1F9E3823BFFFFFFFFFFFFFFFFFFFFFE",
INIT_35 => X"7FFFFFFFF3FFFFFFF8C4FDEF183FFFFFFFFFFFFFFFFFFCFF7FFFFFFFFFFEFFFF",
INIT_36 => X"F842FCFF8FCFFFFFFFFFFFDFFFFFFE7FFDFFFFFFFFFE3FFFCC0FFFFFFF80FFFF",
INIT_37 => X"FFFFFFE7FEFFFF7FF9FFFFFBFFFF1FF80C1FEFFFFF80FFFFFFFFFFFFF3FFFFFF",
INIT_38 => X"FFFFFFFFFFFF8FC06FCFCFFFF382FFFFFFFFFFFFFFCFFFFFFE02C77FFFFBFF3F",
INIT_39 => X"F58F8FFFF7B2FFFFFFFFFFFFFFCFFFFFFF9127FFF01DFE1FFFFFFFE3FE7FFFFF",
INIT_3A => X"FFFFFFFFFFCFFFFFFFF8BFEFF8027C1FFFFFFFFFFF3FFFDFFFFFFFFFFFFFF038",
INIT_3B => X"807C7FF639003FFFFFFFFFFFFFFFFFDFFFFFFFFFFFFD8DC7F033AFFFFF32FFFF",
INIT_3C => X"FFFEFFFEFFFFFFDFFFFFFFFFFE7BAF9F0AE11FFFFF05FFFFEFFFCFFFEF5FFFFF",
INIT_3D => X"FFFFFFF9FE7C4EFE0F001FFFFE05FFFFFFFFFFFFCF3FFFFF807FFE78E0713FFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"67805FFFE105FFFFDFFFFFFFCE7FFFFF9FFFE77EF0F83FFFFFFFFFFFCFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFFFFFF8E7FFFFFF843FFFEFD1E3EFFFFFFFFFFCFFFFFF7FFFFFFF0FC7FB9FE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FC0867FFFFFF3FF3FFFFFFFFFFFFFFF7FFFFFCF17C7F87F8679E1FFFF105FFFF",
INIT_01 => X"F7FFFFFFFFFFFFFFFFFFFC01E07FFFF8FF1E3FFFFF0BFFFFFFFFFFFF88FFFFFF",
INIT_02 => X"FFFFFC068900FFF8FF3CFFFFFF03FFFFFFEFFFFF80FFFFFFF870B1FF7FFFFFFF",
INIT_03 => X"EFFE7FFFFF07FFFFFFFFFFFF81FFF9FFF9F9F1FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFF01FFFFFFFC07FFFFCFBFFFFFFFFFFFFFFFFFFFFFFFFFFC034EFE7FF8",
INIT_05 => X"FFFFFFFFC71FFFFFFFFFFFFFFFFFFFFFFFFFFC139E3CFFF8063E3FFFFE07FFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFF813CBF8FFFC0C073FFFFC17FFFFFFFFFFFE43FFFFFF",
INIT_07 => X"FFFFF859D811FFFC08631FFFF30FFFFFFFFFFFFE4BFFFFFFFFFFFFFFE73FF9FF",
INIT_08 => X"18F31FFFE71FFFFFFFFFFFFE0BFFFFEFFE77193EF07FFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFE17FFFFFFFE7003E13AFFC7FF7FFFFFFFFFFFF3FFFFFFFFE1DBC7FFFC",
INIT_0A => X"C00101F1DBFE07FFFFFFFFFFFFFBF1FFFFFFFFE01C0FFFF831FF3FFFCE1FFFFF",
INIT_0B => X"FFFFFFFFFFFCF0FFFFFFFBF3FFF03FF031003FFF819FFFFFFFFFFFFD17FFFFFF",
INIT_0C => X"FFFFFFF43FFFE7F0E3007FFF1DBFFFFFFFFFFFFC3FFFFFFF803E7FFFF2FF87FF",
INIT_0D => X"C601FFF87DBFFFFFFFFFFFFA1FFFFFFFB7F81FFFF3390FFFFFFFF3FFFFFEF87F",
INIT_0E => X"FFFFFFFA3FFFFFFFFF00000000630FFFFFFFF9FFFFFFF83FFFFFFE6C2FFFFBE0",
INIT_0F => X"E000F800001FCFFFFFDFFFFFFFFFFEDFFFFFFE924FFF7D878407FFF8F9BFFFFF",
INIT_10 => X"FFE0FFFFFFFFE70FFFFFFCFB5F8EFC0F0E03FFFFF97FFFFFFFFFFFF03FFFFEFF",
INIT_11 => X"FFFFFDCB4F8F047F0C07FFFFF87FFFFFFFFFFFF03FFFFFFF80000000003F5FFF",
INIT_12 => X"0C07FFFFF6FFFFFFFFFFFFE87FFFFFFF80000001DFFFBFFFFFFFFF8FFFFFFF07",
INIT_13 => X"FFFFFFE87FFFFFFF81FC001FFFFF77FFFFFFFFC7FFFFFE83FFFFFDD79D8F025E",
INIT_14 => X"81FE003FFFF66BFFFFFFFDE3FFFFFE4007FFFC1719CE4DCED807FFFFE5FFFFFF",
INIT_15 => X"FFFFFC03FFFFFF00E00FFC0718FE2C7C9807FFFFDDFFFFFEFFFFFFC07FFFFFFF",
INIT_16 => X"00CFF83DF1FF19BC3007FFFFDDFFFFFEFFFFFFD0FFFFFFFFC0FE007FFF021DFF",
INIT_17 => X"3007FFFFDDFFFFFFFFFFFFC47FFFFFFF80FC003FFF03FDFFFFFFFFF83FFFFFC0",
INIT_18 => X"FFFFFFCD7FFFFFFFF8780000FE01847FFFFFFFF99FFFFFE21C1FFC3FFFFF8218",
INIT_19 => X"B8780000FE00F4BFFFFFFFFFC7FFFFE13FFFFCDF9FE6631B3001FFFF8BFFFFFF",
INIT_1A => X"FFFFFFFFF1FFFFF81FFFFFDE9FC23318E0107FFFC7FFFFFFFFFFFF8C7FFF7FFF",
INIT_1B => X"0FFFFF8203C21F80E0003FFF87FFFFFFFFFFFF0EFFF9FFFF9DFC0000740030CF",
INIT_1C => X"F803BFFFAFFFFFFFFFFFFF8FFFF3FFFDBFFFFE000000320FFFFFFFFFFC7FFFFC",
INIT_1D => X"FFFFFE0E7FFFFFF9FFFFDF0000FF081FFFFFFFFFFF1FFFFE07FFFF8805E31EC1",
INIT_1E => X"8FFFFF07007FE33E7FFFFFFFFFE3FFFF81FFFF2C8DE13E03FF07BFFF6FFFFFFF",
INIT_1F => X"3FFFFFFFFFF1FFFFC0FFFFD8B9F13603FFC7BFFF7FFFFFFFFFFFFE0E7FFFFFFB",
INIT_20 => X"E07FFFDDF0813613FFFFFFFF1FFFFFFFFFFFFD1FFFFFFFF1861F9F0FFF6FC4C1",
INIT_21 => X"FC3DFFFF1FFFFFFFFFFFFD3FFFFFFFE1BF87FF07FFFFF83FDFFFFFFFFFF83FFF",
INIT_22 => X"FFFFFC3FFFFFFFA1BFFFFF01FFFFFC3C0FFFFFFFFFFE07FFFE3FFFFFC085FE03",
INIT_23 => X"FFFFFF00FF7FE178077FFFFFFFFFDCFFFF1FFFEFE0847E03FC1FDFFE9FFFFFFF",
INIT_24 => X"033FFFFFFFFFE1FFFFDFFDF064FC9C00BF3FFFFDDFFFFFFFFFFFF83BFFFFFF01",
INIT_25 => X"FFFFFFF310E598801FBC3FFDDFFFFFFFFFFFE03BFFFFFE03BFFCF800003FF8C8",
INIT_26 => X"313DFFFBBFFFFFFFFFFFECFBFFFFFF679FFC3C000003877801FFFFFFFFFFFC7F",
INIT_27 => X"FFFFDCF7FFFFFFFF80F800000000F18000FFFFF7FFFFFE03FFFFFFFFBAE4180C",
INIT_28 => X"80003C0001E6804007FFFFFFFFFFFF01FFFFFFFFFE663803713DFFF3BFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFC77FF7FFFFFE3FFF00F27FFFE47FFFFFFFFFFFFCF7FFFFEFFF",
INIT_2A => X"3FF1FFFF7E1FF003FE7FFF887FFFFFFFFFFFBCFFFFFFFFFF8000140003C03CC7",
INIT_2B => X"E6FFFF097FFFFFFFFFFFBDFFFFFE7FFF80000C00070C38F3FFFFFFFFFFFFFFFF",
INIT_2C => X"FFFF3DFFFFFCFFFF80000000073703F1FFFFFFFFFFFFFFFFCFF61DFF7F03F071",
INIT_2D => X"800000000F18FB81FFFFFFFFE7FFFFFFC3F740FE7F4CF0FDC7BEFF3BDFFFFFFF",
INIT_2E => X"FFFFFFFFF3FFFFFFE9FE263E3F16F07DC82CFEFE5FFF07FFFFFD97FFFFFFFFFF",
INIT_2F => X"F0F9373E1F2778F0C8207C7C5FFF07FFFFFEF7FFFFFFFFFF800000000F82333E",
INIT_30 => X"08207C7C5FF803FFFFFCE7FFFFFFFFFF800000800700033F1FFFFFFFFBFFFFFF",
INIT_31 => X"FFF5E7FFFFFFFFFF83F001C00739BF8FBFFFFFFFFCFFFFFFF8FD1E389BD85CC0",
INIT_32 => X"83FF0360000007E07FFFFFFFFEFFFFFFFFFD3E043807058107E03CC85FF007FF",
INIT_33 => X"7FFFFFFFFF7FFFFFFFE0F21FF00163CB06E01B805FF3C7FFFFEFEFFFFFFFFFFF",
INIT_34 => X"FFE01333F071EBCF8660D3005FE7C7FFFFDFDFFFFFFFFFFFE17F87FC000F27F0",
INIT_35 => X"C2F0C7185FE643FFFFBD9FFFFFFFFFFFFC3F83FE001F8FC21FFFFFFFE703FFFF",
INIT_36 => X"FF7C3FFFFFFFFFFFFF0380FF0002FE8003FFFFFFC0C07FFFFFF033F3F0C3EFED",
INIT_37 => X"FF00007E0009388003FFFFFF0011BFFFFFF9FEFEC0FE7E7F1BB0A3189FE643FF",
INIT_38 => X"FFFFFFFF0000CFFFFFFDFF7FC070BCE68113FE3D9FCF4FFFFE703FFFFFFFFFFF",
INIT_39 => X"FFFDA378C0C04CC6D70FFC791F9B9FFFFCC1FFFFFFFFFFFFE6800000000A7DE0",
INIT_3A => X"8E0C7C79BF313FFFFBBFFFFFFFFFFFFFFE80000000061E07FF3FFFFF0131FBFF",
INIT_3B => X"CFFFFFFFFFFFFFFFFC00000000EC0F9FFFFFFFFFF87C45FFFFF1F3809F001AC3",
INIT_3C => X"F003000002E87FFFFFFFFFFFFC1C33FFFFECFBE1070F03F0000C7CD9BEE27FFF",
INIT_3D => X"FFFFFFFFFC1C0E01E7E87BFF079181F0007FE7D539227FFFBCFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FF27A3F03B0F0F0605F2FF372067FFC7BFFFFFFFFFFFFFF8403000002E7FFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"7D47E732F406FFF3F7FFFFFFFFFFFFFFFE00000008F7FFFFFFFFDFFFFF7DCFC2"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6FFFFFFFFFFFFFFF9FE000001E8FFFFFFFFFC7FFFFC77E07BFF07C00F3E6F8E0",
INIT_01 => X"87F000003FFFFFFFFFFFFFFFFFF7CFF9CFF0FC00FFCE7BDC44C3F3BCF484FFC4",
INIT_02 => X"FFFFFFFFFFF86BE079DFFF443FBC618E9DC1E7FFBBC8FF909FFFFFFFFFFFFFFF",
INIT_03 => X"FF7EFF6407886D8F05C3CFFFD9C8FE637FFFFFFFFFFFFFFF8040001911BFFFFF",
INIT_04 => X"FBC3DFFFFFF0FC82FFFFFFFFFFFFFFFF8000033C18BFFFFFFFFFFFFFFFFFC0E0",
INIT_05 => X"FFFFFFFFFFFFFFFF8000010078BFFFFFFFFFFFFFFFFFFFF7FFFEFD6C83E855F2",
INIT_06 => X"8000000300BFFFFFFFFFFFFFFFFFFF5FFFFFFF6203ADA1ABFC403FF1E109FB0D",
INIT_07 => X"FFFFFFFFFFFFFF47FFFBFF6003DD59A17F003FF84DFFF493FFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFF40E1DDBAA53F403FF899FF4867FFFFFFFFFFFFFFFFC0000002387FFFFF",
INIT_09 => X"B0C078F3870E33C7FFFFFFFFFFFFFFF7C00003F23C3FFFFFFFFFFFFFFFFFFFA3",
INIT_0A => X"FFFFFFFFFFFFFF8780007F7C3EBFFFFFFFFFFFFFFFFFFFC03FFFFF8001E5C0A7",
INIT_0B => X"8001FE300F9FFFFEFFFFFFFFFFFFFFFF1FFFFF8001F9E0FEB5C0F4F0F390CF0F",
INIT_0C => X"1FFFFFFFFFFFFFFFCFFFFF700FF8E2ADB348F5F02CC9383FFFFF81FFFFFFFF9F",
INIT_0D => X"F7FFFFFC1F0C72197949F9932F4FF01FFFFF01FFFFFFFFFDC1C07D863FDCFFFC",
INIT_0E => X"F901C9B14F6F0783FC0007FFFFFF7FFD81FFF39FFFFFFEFFFFFE3FFFFFFFFFFF",
INIT_0F => X"F0381FFFFFFFFFF980F80FBFFFFFFFFFFFFFFEFFF0FFFFFFFBFFFEFE1C0E371E",
INIT_10 => X"81C0FF3FFFFFFFFFFFFFFF00000FFFFFFDFFFC3FF00673F8010183E540FC3FF9",
INIT_11 => X"FFFFFFFFFFFFFFFFC87FFC3FF0003FF9F00043E087F83E3EC07C3FFFFFFFFFC3",
INIT_12 => X"E01FFC7FF0015FB3F00003633FC01C01FDEC7FFFFFFFFE718707FFFE7DFFFFFF",
INIT_13 => X"10903FE07F1FCC127F38FFFFFFC1FCE1FC0FFFF039FF7FFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FE40FFFFFE01FBCDE38FFCE1F3F007FFFFF07FFFFFFFFFFFE807F83FF01F6F82",
INIT_15 => X"CF8FF6E7FE0006000F8FFFFFFFFFFFFFE003F03FF03FB4FAC0903EF1DC7FE4F8",
INIT_16 => X"003FFFFFFFFFFFFF8203FB19F9F1BFE7C0C86CFF71FFE5C0E081FFFFF807E001",
INIT_17 => X"F207FFB0FFEF785E008C5471C3FFE9C0E04FFFFFF81F01019FEEDC01E07C0700",
INIT_18 => X"319CD7E31FFF9300609FFFFFF000C001FFC03C00007FFF0E03FFFFFFFFFFFFFD",
INIT_19 => X"373FFFFFF80FC181FF187E08007FFC207FFFFFFFFFFFFFFAFF1FFFF0FF0FFF5C",
INIT_1A => X"FC497F08007FB81FFFFFFFFFFFFFFFE3FBBFFFF97E00FFC8719CD7C67FECC003",
INIT_1B => X"FFFFFFFFFFFFFE1F9DFFFFFFFE6780E1E098C50DFFF227779EFFFFFFFCFFFC3D",
INIT_1C => X"7DBFFFFFFE7B0011C04088FBFFF204E3F2FFFFFFF8FFE03FFCC8FF803C3CB8FF",
INIT_1D => X"E4605133FFE1C1C2FA7FFFFFE3FFC01DFCB1BF803C1C31FFFFFFFFFFFFFFC0F1",
INIT_1E => X"F77FFFFFDF646031FF031F083C1C33FFFFFFFFFFFFFFB00FFC1FFFFFFF38B0C0",
INIT_1F => X"FF8D3E881C0007FFFFFFFFFFFFFF70FFFFD03FFFFF8046EFE76072FFFFEDC3CF",
INIT_20 => X"FFFFFFFFFFFE01FFFFA31FFFD3DFAD7F3F58DDFFFFE801FFE67FFFF83F28E031",
INIT_21 => X"FFB17FFF92F029D23F5D13FFFFD080FFE77FFC0007FF807DFC1E63800600CFFF",
INIT_22 => X"3EDD0FFFFFA01C43070000FF983FC07FF87E7300003FFFFFFFFFFFFFE7FFBBFF",
INIT_23 => X"0E017FFC381CC0FFC0DF3E0C07FFFFFFFFFFFFFFFFF3FFFFFF6DF1FF8A67EFB0",
INIT_24 => X"9FBF3C0C0FFFFFFFFFFFFFFFFFFFFFFFFF0DF1FCB7CE2723F0BE3FFFE0C00ECD",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFEFFFC9E9E7101E0BE7FFE3F0E8CE3FE0FC7E1F01F1CFF",
INIT_26 => X"FFFC4FFE823E7187E01DFFFBFF4F3CF8FC1C0707FC087FFFFFF9FE1E3FFFFFFF",
INIT_27 => X"C01BFFF7FFFFE0FE781DFC3FFFE0FFFFE1F14E387FFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"3FB939FFFFFFF3FF83F24FE7FFFF843FFFFFFFFF8FFFFFFFFFFDCFFE01EC43E7",
INIT_29 => X"A1983FDFFFE00003FFFFFFFF9FEFFFFFDFF8B1FF31C5CF13C317FFF5FF7FFFFE",
INIT_2A => X"FFFFFF9FFFDFFFFF3FF6C5FF3807BA2BC71FFFB865FFFFFC0FFFE7FFFFFFFFFF",
INIT_2B => X"FFE4C1FF06003FEBC73FFF71F7FFFFF03FFFCFFFFFFFF7FFB9F0FF5FFFEFE1FB",
INIT_2C => X"C779FFDCCFFFFE00E0FFCFFFFFFFFFFFAFC04679FFDFFFCBFE7FFFB1FE3FFFFE",
INIT_2D => X"CFFF8FFFFFFFFFFF830043FDFFFF039280001FF1CE7FFFF9FFE1E3FF001C07EF",
INIT_2E => X"949FC3E3F3E0005D600107FC8FFFFFF3FFE3FBFF0C1C0633C0373D17FFFFE00F",
INIT_2F => X"F8800FFF0FFFFFEBFFE7FBFFE0003F078007E7FFFFFF03FFF9CFBFFFFFFFFFFF",
INIT_30 => X"FFC7F83FC7007FCF80237BFFFFFC5F3FC007BFFFFFFFFFFF9C181BFFEFC001FC",
INIT_31 => X"87380FFFFFC3B83F8023BFFFFFFFFFFF803011FC1F000FF8FFC00F770FFFFFD7",
INIT_32 => X"007BBFFFFFFFFFFF93DEE3F87C00FCEFFC003EFFCFFFFF8FFFCFB1FF47FFFFFF",
INIT_33 => X"863FE7E07800E13FFE03FFFFCFFFFF7FFFFF13FE67FF807FFFF81FFFFF9FE0E0",
INIT_34 => X"C7C3FFFF1FFFFEBFFFFF3BFC697F80FBFFFC3FFFFE0FFF06107FDFFFFF87FFFF",
INIT_35 => X"FFFF7B9E78DCF0F13FF9FFFFE187E073387FDFFFFF00FFFF827FFFC381679EFF",
INIT_36 => X"FFF9FFFC7F983FFBFCFFEFFFFE00FFFF837C7FCF01C67EFFC323FFFFFFFFFCFF",
INIT_37 => X"FE7FEFFFFE0C3FFF87301E1E0006FEE0040FFFFFFFFFFAFFFFFFF31FFE9C10F3",
INIT_38 => X"F7FC2E3C000DF0E00C7FFFFFFFFFF9FFFFFFF11FFFF023F3FFE4F861C7E3FFF9",
INIT_39 => X"78FFFFFFFFFFE3FFFFFFC1F7C3307FFFFFC0E3F46403FFE1FFFBF77FFC3E03FF",
INIT_3A => X"FFFFD8FFB91FFFFFFFE03C6F9C73FFC7FCB3F67FF81E0001F6206C7010B7F0E0",
INIT_3B => X"FFFC7F9FE073FFC7F11FF87FFC060001F65BF1E000CFE1E3F0FFFFFFFFFFC7FF",
INIT_3C => X"CF9FF87008003F81F27B4FE000FFDFFF3FFFFFFFFFFF8FFFFFFF98FE671FFFFE",
INIT_3D => X"BC277FC602BFD7F8FFFFFFFFFFFEDFFFFFFF9AFE48105FFCFFE77FFFE07FFFC3",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFCFFFFFFFFC3FF2D00B7FDF7FB7FFFE746FFE430FB8C0FC8005FE1",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFEFEFF3600B7FFE1FF87FFE77F7FFEF39B8C1FCC01FFEDB77FFF063FBF9FE3"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"E7FFFBFFEF81BF0BFF9AFC78E403F9ED8E07FE027FBE1F07FFFFFFFFFFFFFFFF",
INIT_01 => X"3E125FF0601FF3FF80FFC0007F3DF00F7FFFFFFFFFFFFFFFFFFE3F1F933C3EFF",
INIT_02 => X"80C70000FFFDF07FFFFFFFFFFFCEFFFFFFFE3F1FD33CFC7FFC7FF9FFFF8F3F00",
INIT_03 => X"FFFFFFFFFFDBFFFFFFFF1F7FC3381C77393F1DF0DFFFFA007C3F0FC001FFFEFD",
INIT_04 => X"FFFF9FBFE7001FE33C3F6DC20CF0D8007CFFFF0F03FF7FFD806E00031878F8FF",
INIT_05 => X"1E83748003B8007EF3CE0FFFEFFCFFFD91B80002907387FFFFFFFFFFFFF3FFFF",
INIT_06 => X"C3E01FCFFFF9FF8DF1B00005B8E21FFFFFFCFFFFFBC3FFFFFFFBFFBFBF0C1FF8",
INIT_07 => X"91B0000D39E2FFFFFFFFFFFFFFC7FFFFFFF8FFBA331C41DC1F8F94639FE301FB",
INIT_08 => X"FFFFFFFFFF1FFFFFFFFAFFF8E367F03E00F1E8FFFC000C2DB7FE1F1CFFC40FF9",
INIT_09 => X"FFF1FFEEF1C010FE187770FFFC73FBFDBFF31F3FF8003FF3E73300BB0000FFFF",
INIT_0A => X"3C6FB07FFFF617FC1FD5DC7FF3E0FFF1E00381F70100FFFFFFFFFFFFFF1FFFFF",
INIT_0B => X"D7D4F87F0000FF81E70311CF7E63FFFFFF83FFFFFE3FFFFFFFE7FF9E65008FFB",
INIT_0C => X"EF31F20E7E03FFFFFC33FFFFEE3FFFFFFFE7FF9FDE0C0CF3FC8F7C0F9FED5BFF",
INIT_0D => X"FC03FFFFC0BFFFFFFFC7FFF7FFCC3DFBFC30CC1F0FDBC3FFA3F0F03F80981FF9",
INIT_0E => X"FFD7FFE3FFE1BBFFFDE1B4FF1FFF93FF83F0FA1F81B81FFFCE79E6FE7FFFFFFF",
INIT_0F => X"FBE077FFFFCE1BFFC3E7B907001000FFCC9FDDFE7DFFFFFFF807FFFDC07FFFFF",
INIT_10 => X"83C3C000000001FFC30FA1FEFCFFFFFFE007FFFFC0FFFFFFFFCFFFCBFFF9BFFF",
INIT_11 => X"FEDF20FFFEFFFFFFCE07FFE3C1FFFFFFFFDFFFBBFFF9B7FFFBF1F7FFFCFDF3FF",
INIT_12 => X"3E1FF7C4B1FFFFFFFFDFFFBFFFF1BFFFC1FFFAF0FEFA23FF4403F800008007FF",
INIT_13 => X"FF9FFF7DFFC4BFFFC0FFFD00FEF9A0F9C8438000000007FD91C6F8FFFFFFFFFE",
INIT_14 => X"C2FFFE00FF3A3076FCE0000078000F0D81DDF07FFFFC07FBE6FFE38863FFFFFF",
INIT_15 => X"F87086007F1C7F3F8019F03FFFFC03EFF8FFC21807FFFFFFFF1FFEFCFFBE77FF",
INIT_16 => X"801183FFFFFC007FF8FF8FB00FFFFFFFFF1FFFB47FB8F7FFC33FFE90FFDCF29F",
INIT_17 => X"F2FF9F002FFFFFFFFE3FFD30FFB01FFFC98FFE9F7FEE679FF8078038FFFFFFFF",
INIT_18 => X"FEFFFB1CFFB407FFCCC7FC9FFFF793FFB81E007DFF3F7FFF80F1BFFFFFF90FFF",
INIT_19 => X"DEE7FE9FFEFFFEF8C0011E7FFF7C3FFF81E13FFFFFFC1FFFEFFF1F181FFFFFFF",
INIT_1A => X"A0003E7FFFFC3FFD81E17FFFFEFC3FFF5FFE3E3CFFFFFEFFFD7FFF0ECF2607FF",
INIT_1B => X"80FD7FFFFC7F1FFFDFFE3038FFFFF0FFFD7FF7EDCF6631FFDCE1FFFF9DC4FFFF",
INIT_1C => X"BFF83818FFFFCDFFFB7FFB89EEE6B9FFCBF5FF61BF270FFFEAE03E7C01DFFFE1",
INIT_1D => X"FB7FFFBBFDEEBDFFE3FDFF519C59EFFFEFF0400C0003FFE180197FFFFCFE04FF",
INIT_1E => X"E39DFFD31807DFFFF1FF00F7F3EC1FE180197FFFFFFFE07FBFF53831FFFFC3FF",
INIT_1F => X"FFFF839FF84F1FC181397FFFFFFFE270FFF1F003FFFC07FFFAFFFF3FCDCEB5FF",
INIT_20 => X"8833FFFFFFFE0663FFF3F013FFF80FFFF9FFFB9E23CDA3FFE019FEBB9015D7FF",
INIT_21 => X"FFDCE317FFFB07FFFBFFFC8E31F9A1FFF000FD7FC400C1FFFEF0C3CC3F0383E1",
INIT_22 => X"F3FF748678CBA5FFFF807D7DC48BD5FFE0F07F80E3C3C3F19C22FFFFFF0000E7",
INIT_23 => X"FFE40C3DC0259AFFF0007FC07C03E3F9FE66FFFCFF0001EFFF18432FFFFF07FF",
INIT_24 => X"F8007FFE3FCFF0F9FFEDFFFD1F80001E7E18002FFFFE37FFE7FFE900E8ABE7FF",
INIT_25 => X"FF99FFFD43873FFD7C74001FFFF837FFE7FFEA07E8A7C7FFFFE0C87EA0740D7F",
INIT_26 => X"BD7F003FFF838FFFFFFFEF0F7FFFC5FFFDE0F057B97CF64DFE7C19FE0FFFFCF1",
INIT_27 => X"CFFFE7FF7CEFC5FFFF34D829BC608BC9FFDCE0EE3FFFFC01B830007DE7BD1FFC",
INIT_28 => X"FE355FD5ACE04479FFF9F80F3FFFFE07B3C0FFC8E6FDCFF83707907FFF8C8FFF",
INIT_29 => X"FFFFE00FBFFFFFFFA607339046FBCFF08E011F7FFF38CFFFCFFFE1FEF02FEEFF",
INIT_2A => X"E81C7CCCB5330DE4FF880B7FFFF0EFFF87FFFC06F02FEEFFFE76BFC5FCE02676",
INIT_2B => X"7FFF093FFF90EFFF87FF7C03F04FBEFFFE789D89DC631AF97FFFEE0FBFFFFFFF",
INIT_2C => X"0FFE7C03F047BF7FFFF93F33EBE24ADD7FFFEE7FBFFFFFFFD831F0C03D187DCC",
INIT_2D => X"FFFEAFC7F280471CDFFFF420BFFFFFFFB8CFFBF7C83F7DDEFFFF0E3FFF019FFF",
INIT_2E => X"2FFFE160BFFFFFFFFF3E7FFCC09F7B9CC93C003FFC037FFE1FFFFC01B083BCBF",
INIT_2F => X"FC7F7FB0C1DF693CC9000F7FFE07FFFE0FF3F83980D3BFBFFFFE6F07F10141BC",
INIT_30 => X"D500F7FFFC05FFFC9FEFF3BE80BFBFBFFFFCD783FC820EB861FFE6E0BFFFFFFF",
INIT_31 => X"FFFFE4BE81CFD9D3FFFCC383FC41CF0F31FFF0E3FFFFFFFFC0071F78C1CF51FD",
INIT_32 => X"63EC7B13FE83EF77D87FF860DFFFFFFF80001FFFF3E16FFCD100F7FFC5A17FFE",
INIT_33 => X"EF1FFF801FFFFFFF803C0FFFFFFD19FD17003FFFA981FFFCFE7FCCBE0077D8E0",
INIT_34 => X"887F0700F8FCABFC15304FFFA780FFFCF57F98B60069B8F375EC39BFFFA79DB7",
INIT_35 => X"1170DFFF2F82FFF8EFFF39660009B0EC76E4D09FFFA7DEC067E7FFC35FFFFFFF",
INIT_36 => X"C2FC3AFF000390687A80C0EFFFA5DEEF3337FFF9E3FFFFFFC03FE07F000E17FC",
INIT_37 => X"7DE3E0F7FF7BFFE79009FFFE78FFFFFFE03FFFC0C002AFFC1930DFFF6E03FFF4",
INIT_38 => X"D806FFFFBF07FFFF907F001F0EC05FFD1800BFFCE003FFF4BBFC7CFF00089070",
INIT_39 => X"CDFF00FFE2C0BFFD3803BFC8E022FFF42FFE79FD800F201CFEE7F097FF67F771",
INIT_3A => X"3E077F80E03DFFFCDFFEF3FE580EE00C7FEFE777FFF20BFEDC693FFFEFF0FFD3",
INIT_3B => X"3FFD33FF4006000DFFAFE7FBFFFB0FE6DC7C9FFFF3FFF3C1CFCF01FFF90D23FD",
INIT_3C => X"BFCE0739FFFC0FE30878CFFFFCCFFD879F0300FFF91823FD3A65FF19E07FFFEC",
INIT_3D => X"80F7CFFFFF2FFE27B339E0FFF2FA01FE822EFF3B807BFFECFFF717F82006000F",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"B37CF07C88FA01FE068EFFFC007FFFDEFFFA0FFA1806000FBFFE075DFFFCDFE1",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"258FFFF4087FFFFFFFFA0FFDC800000F3FF803DEF7FE6FE0C0F407FFFF9FFE21"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF003FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFF80FFFFFFFFFFFFC7FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFF03FFFEFFFFFFFE1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF003FFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFF001FFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFE3FFFF803FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FF3FFFF803F3FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE073F1FFCF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC63873FFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFC7981FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFEFC03FFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFC03FFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00FFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"9FFFFFF80007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80FFFFFE0007FFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8007FFFF0001FFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFF80000FFF00103FFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFFFFF",
INIT_18 => X"860007FF00000FFFFFFFFFFFFFFFFFFFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000FE00012FFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0070F0001F7FFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFC07870001F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFE81870000FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000007BFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000001FFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFC0000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FF",
INIT_22 => X"FFFFFF004000073FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFF",
INIT_23 => X"FE10FFFFFFFFFFFFFFFFFFFFFFEFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE10C0000C1F",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1C00021FDFFE001FFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFE1FE0001FFFFF8001FFFFFFFFFFFFFFFFFFFFE3FFFF",
INIT_27 => X"FFFFFF3FF0001FFFFFFE007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFC00FFFFFFFFFFFFFFFFFFDFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFF8180E3F",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBEFFFFFFFE010E0FFFFFF001FFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFF9F7FFFFFFFF380077FFFFFF0FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"9FFFFFFFFFFFC00F7FFFFFFF87FFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFF07FFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FE03FFFFFFFE1C3",
INIT_2F => X"FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFF8FF01FFFFFFFE3C3FFFFFFFFC7FFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFF807C03FFFFFFE3CFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"803FC0FFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFF9FFFFFFFE7FFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFE7FFFFFDFFFFFFFE7FFFFFFFFFFFFFFFFFFFF800FE0FFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFF8007FC7DC7FFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFF8003FE10E7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFF",
INIT_36 => X"8001FF00703FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFF03FFFFFFFFDFFFFFFFFFFFFFFFFFFFF8001FF800007FFFF",
INIT_39 => X"F87FFFFFFFFDFFFFFFFFFFFFFFFFFFFF8000FFC00FE3FFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFF80007FF007FDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FC7",
INIT_3B => X"80003FF9C7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE023FF9FFDFFFFFFDFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFC207FF1FFFFFFFFFBFFFFFFFFFFFFFFBFFFFF",
INIT_3D => X"FFFFFFFFFFFF81FFF0FFFFFFFFFBFFFFFFFFFFFFFFFFFFFF80001FFFFFFEFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"987FBFFFFEFBFFFFFFFFFFFFFFFFFFFFE0001FFFFFFFFFFFFFFFFFFFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFFFFFFFFFFFFFFFFBC07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFF83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF9861FFFFFEFBFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFE1FFFFFFF00E1FFFFFFF7FFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFF06FFFFFF00C3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FC3FFFFFFFFFF",
INIT_03 => X"1001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE07FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8001FFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFE003FFFFF801FFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFEFF407FFFFF000FFFFFFEFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFE7E7EFFFFFF000FFFFFCFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"E000FFFFF8FFFFFFFFFFFFFFF7FFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFEFFFFFFFFFFFFC1EF1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFF",
INIT_0A => X"FFFEFE0E21FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE3FFFFFFC000FFFFF1FFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFC000FFFFFC0FFFFFFFE7FFFFFFFFFFFFEEFFFFFFF",
INIT_0C => X"FFFFFFF800001FFF00FFFFFFFE7FFFFFFFFFFFFFCFFFFFFFFFC0000001FE7FFF",
INIT_0D => X"01FFFFFFFE7FFFFFFFFFFFFDFFFFFFFFC800000000FEFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFDFFFFFFFF80000000001CFFFFFFFFFFFFFFFFFFFFFFFFFFF0100007FF",
INIT_0F => X"8000000000003FFFFFFFFFFFFFFFFF3FFFFFFF60300083F803FFFFFFFE7FFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFF00207003F001FFFFFFFEFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFE303070038003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000003FFF",
INIT_12 => X"03FFFFFFF9FFFFFFFFFFFFF7FFFFFFFF8000000000007FFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFF7FFFFFFFF81FC00000000FFFFFFFFFFFFFFFFFFFFFFFFFE38627001A0",
INIT_14 => X"81FE00000001F7FFFFFFFFFFFFFFFFFFFFFFFFF8E6318C30C7FFFFFFFBFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFF1FFFFFF8E701CC0087FFFFFFE3FFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FF3FFFC00E00E1800FFFFFFFE3FFFFFFFFFFFFEFFFFFFFFF80FE00000001E3FF",
INIT_17 => X"0FFFFFFFE3FFFFFFFFFFFFFFFFFFFFFF80FC0000000003FFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFF8780000000003FFFFFFFFFFFFFFFFFFFFFFFFC000007C00",
INIT_19 => X"F87800000000F37FFFFFFFFFFFFFFFFFFFFFFFE060181C030FFFFFFFF7FFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFE1603C0C001FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFDFC3C00001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFC00000000373F",
INIT_1C => X"07FC7FFFDFFFFFFFFFFFFF7FFFFFFFFFFFFFFE00000037FFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFF00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFE1C0000",
INIT_1E => X"8FFFFF0000001CFFFFFFFFFFFFFFFFFFFFFFFFDF7E1E000000F87FFF9FFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFE77E0E080000387FFF9FFFFFFFFFFFFFFFFFFFFFFD",
INIT_20 => X"FFFFFFE23F06081000003FFFFFFFFFFFFFFFFEFFFFFFFFFF87FF9F000000383E",
INIT_21 => X"03C23FFFFFFFFFFFFFFFFEFFFFFFFFFFBFFFFF00000000003FFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFDFBFFFFF0000000003FFFFFFFFFFFFFFFFFFFFFFE03F020000",
INIT_23 => X"FFFFFF0000001E07FFFFFFFFFFFFE3FFFFFFFFF01F03800003E03FFF7FFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFF9F03E00000C03FFE3FFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFEF03E0000043FFFE3FFFFFFFFFFFFFFFFFFFFFFFBFFCF80000000707",
INIT_26 => X"00C3FFFC7FFFFFFFFFFFF3FFFFFFFFFF9FFC3C0000000087FFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFE3FFFFFFFFFF80F800000000F07FFFFFFFFFFFFFFFFFFFFFFFFFC503E00C",
INIT_28 => X"8000000001E6803FFFFFFFFFFFFFFFFFFFFFFFFF8181C00300C3FFFC7FFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFF81C000000181FFF83FFFFFFFFFFFC3FFFFFFFFFF",
INIT_2A => X"FFFFFFFF81E000000181FFF03FFFFFFFFFFFC3FFFFFFFFFF8000080003C0003F",
INIT_2B => X"0101FFF03FFFFFFFFFFFC3FFFFFFFFFF80000000070C000FFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFC3FFFFFFFFFF80000000073F000FFFFFFFFFFFFFFFFFFFF9FFFF80FC0070",
INIT_2D => X"800000000F18F87FFFFFFFFFFFFFFFFFFFF83FFF80FF00FC0001FFC03FFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFF7F819FFC0EF007C0813FF003FFFFFFFFFFE6FFFFFFFFFFF",
INIT_2F => X"FFFE08FFE0C000F0081FFF803FFFFFFFFFFC0FFFFFFFFFFF800000000F0030FF",
INIT_30 => X"081FFF803FFFFFFFFFF81FFFFFFFFFFF80000000070000FFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFF81FFFFFFFFFFF800000000739807FFFFFFFFFFFFFFFFFFFFE01FFE01820C0",
INIT_32 => X"800000000000381FFFFFFFFFFFFFFFFFFFFE01FBC0077981001FFF003FFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFF01E00000FBC3011FFC003FFC3FFFFFF01FFFFFFFFFFF",
INIT_34 => X"FFFFE0C0000FF3C3819FFC003FF83FFFFFE03FFFFFFFFFFFE00000000000180F",
INIT_35 => X"C10FF8003FF83FFFFFC27FFFFFFFFFFFFC0000000000003DFFFFFFFFFFFFFFFF",
INIT_36 => X"FF83FFFFFFFFFFFFFF0000000001017FFFFFFFFFFFFFFFFFFFFFC000003FF7E1",
INIT_37 => X"FF0000000008FF7FFFFFFFFFFFFE7FFFFFFE00010001F7F0180FDC007FF83FFF",
INIT_38 => X"FFFFFFFFFFFF3FFFFFFE0000000077E1000C00007FF03FFFFF8FFFFFFFFFFFFF",
INIT_39 => X"FFFE5C00000037C100000000FFE07FFFFF3FFFFFFFFFFFFFE68000000009FE1F",
INIT_3A => X"000380007FC0FFFFFC7FFFFFFFFFFFFFFE8000000001FFFFFFFFFFFFFECE07FF",
INIT_3B => X"F0FFFFFFFFFFFFFFFC0000000003FFFFFFFFFFFFFF8383FFFFFE0C00600003C0",
INIT_3C => X"F00300000207FFFFFFFFFFFFFFE3C1FFFFF30400F80003F0000380207F01FFFF",
INIT_3D => X"FFFFFFFFFFE3F1FFFFF78400F80E01F000001824FE01FFFFC3FFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFF85C0FC0F00F000201000FC01FFFF87FFFFFFFFFFFFFF80030000020FFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"00381801F801FFFC0FFFFFFFFFFFFFFF80000000000FFFFFFFFFFFFFFF823001"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"1FFFFFFFFFFFFFFF80000000007FFFFFFFFFFFFFFFF800007FFF83FF0C1F00E0",
INIT_01 => X"80000000007FFFFFFFFFFFFFFFF800063FFF03FF003F83C0383C0C03F803FFF8",
INIT_02 => X"FFFFFFFFFFFF841F87E000BBC07F8180783E18007C07FFE07FFFFFFFFFFFFFFF",
INIT_03 => X"0081009BF87F8180F83C30003E07FF80FFFFFFFFFFFFFFFF800000190E7FFFFF",
INIT_04 => X"FC3C2000000FFF01FFFFFFFFFFFFFFFF8000033C077FFFFFFFFFFFFFFFFFFF1F",
INIT_05 => X"FFFFFFFFFFFFFFFF80000100077FFFFFFFFFFFFFFFFFFF0800010293FC1F8981",
INIT_06 => X"80000000FF7FFFFFFFFFFFFFFFFFFF800000009DFC1E1D91FFBFC00E00FFFC03",
INIT_07 => X"FFFFFFFFFFFFFF800004009FFC3E3D98FFFFC0078CFFF88FFFFFFFFFFFFFFFFF",
INIT_08 => X"000000BF1E3E7C98FFBFC007D8FFF01FFFFFFFFFFFFFFFFF80000001FFFFFFFF",
INIT_09 => X"7F3F870FC0FFC03FFFFFFFFFFFFFFFFF80000001FFFFFFFFFFFFFFFFFFFFFFC0",
INIT_0A => X"FFFFFFFFFFFFFFFF80000083FFFFFFFFFFFFFFFFFFFFFFFFC000007FFE1E3C98",
INIT_0B => X"800001CFFFFFFFFFFFFFFFFFFFFFFFFFE000007FFE061C807A3F0F0F0C0F00FF",
INIT_0C => X"FFFFFFFFFFFFFFFFF000008FF0071C807CB70E0F1F0607FFFFFFFFFFFFFFFFFF",
INIT_0D => X"F8000003E0F38C00FEB6060C1F800FFFFFFFFFFFFFFFFFFF800003FFFFFFFFFF",
INIT_0E => X"FEFE360D3F80F87FFFFFFFFFFFFFFFFF80000FFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFC7FFFFFFFFFFFF8007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000101E3F1C801",
INIT_10 => X"803FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0003C00FF98C07FEFE7C193F03C007",
INIT_11 => X"FFFFFFFFFFFFFFFFFF8003C00FFFC0060FFFBC1C7807C001FF83FFFFFFFFFFFF",
INIT_12 => X"FFE003800FFEE00C0FFFFC1CC03FE0000203FFFFFFFFFF8F80FFFFFFFFFFFFFF",
INIT_13 => X"EF6FC01F80FFF01200C7FFFFFFFFFF1F83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"01FFFFFFFFFFFC339FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F807C00FE0F07D",
INIT_15 => X"BFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0FC00FC0787DFF6FC00E03FFF8F8",
INIT_16 => X"FFFFFFFFFFFFFFFFFDFC04E6060E78F9FF3790000FFFF9C01FFFFFFFFFFFFFFF",
INIT_17 => X"0DF8004F001FFFE1FF73B8003FFFF1C01FBFFFFFFFFFFFFFFFFFE3FFFFFFFFFF",
INIT_18 => X"CE633800FFFFE3001F7FFFFFFFFF3FFFFFFFC3FFFFFFFFF1FFFFFFFFFFFFFFFE",
INIT_19 => X"08FFFFFFFFF03E7FFFE781F7FFFFFFDFFFFFFFFFFFFFFFFC00E0000F00FFFFE3",
INIT_1A => X"FF8780F7FFFFFFFFFFFFFFFFFFFFFFFC0440000681FFFFF78E633801FFF30003",
INIT_1B => X"FFFFFFFFFFFFFFE07E00000001F87FFE1F673803FFE0207781FFFFFFFF0003FF",
INIT_1C => X"FE40000001FCFFFE3FFF7007FFE000E3F1FFFFFFFF001FFFFF07007FFFFFFFFF",
INIT_1D => X"1BFFE0FFFFF001C2F9FFFFFFFC003FFFFF4E407FFFFFFFFFFFFFFFFFFFFFFF0F",
INIT_1E => X"F0FFFFFFE0039FFFFFFCE0FFFFFFFFFFFFFFFFFFFFFFCFFFFFE0000000FFCF3F",
INIT_1F => X"FFF0C17FFFFFFBFFFFFFFFFFFFFF8FFFFFE00000007F8F1018FFE1FFFFF403CF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFC000000C202600C0E7E3FFFFF001FFE1FFFFFFC0071FFF",
INIT_21 => X"FFCE00000C00263DC0E3EFFFFFE080FFE0FFFFFFF8007FFFFFE1807FFFFFFFFF",
INIT_22 => X"C1E3FFFFFFC0000300FFFF007FC03FFFFF8180FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"01FE8003FFE03FFFFF00C1F3FFFFFFFFFFFFFFFFFFFFFFFFFF9E0E001C07E07F",
INIT_24 => X"E000C3F3FFFFFFFFFFFFFFFFFFFFFFFFFFFE0E00080FE0FC0FC1FFFFFF0001F0",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFC0000011FF0FE1FC1FFFFC00103FC01F0001FFFE0FFFF",
INIT_26 => X"FFFE0000003FF0781FE3FFFC003FC3FF03E000FFFFF7FFFF800601E1FFFFFFFF",
INIT_27 => X"3FE7FFF8007FFFFF87E003FFFFFFFFFF800E01C7FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"C040C7FFFFFFFFFF800C001FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000001EFC018",
INIT_29 => X"A060003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFCE0001C7C00C3FEFFFF800FFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFF9FE000007841C3FFFFFC003FFFFFFF0001FFFFFFFFFFF",
INIT_2B => X"FFFBFE000000001C3FFFFF800FFFFFFFC0003FFFFFFFFFFFB800003FFFF01E07",
INIT_2C => X"3FFFFF03FFFFFFFF00003FFFFFFFFFFFA0003807FFE00007FFFFFFFFFFFFFFFF",
INIT_2D => X"00007FFFFFFFFFFF8C003C03FF00000FFFFFFFFFFFFFFFFFFFFFFC00001C0010",
INIT_2E => X"88803C1FFC00003E9FFFFFFFFFFFFFFFFFFFFC000C1C00003FF8C3EFFFFFFFF0",
INIT_2F => X"077FFFFFFFFFFFF7FFFFFC00000000007FF803FFFFFFFC0006307FFFFFFFFFFF",
INIT_30 => X"FFFFFFC0000000007FDC87FFFFFFA0003FF87FFFFFFFFFFF8007FCFFF000007F",
INIT_31 => X"78C7FFFFFFFC40007FDC7FFFFFFFFFFF800FFFFFE00000FF003FFFFFFFFFFFEF",
INIT_32 => X"FF847FFFFFFFFFFF903FFFFF800003F003FFFFFFFFFFFFFFFFFFFE0080000000",
INIT_33 => X"81FFFFFF80001FC001FFFFFFFFFFFF9FFFFFFC01800000000007FFFFFFE0001F",
INIT_34 => X"003FFFFFFFFFFF7FFFFFFC03868000000003FFFFFF8000FFFF803FFFFFFFFFFF",
INIT_35 => X"FFFFFC01870300000007FFFFFE001FFFFF803FFFFFFFFFFF81FFFFFC01607F00",
INIT_36 => X"0007FFFF8007FFFFFF001FFFFFFFFFFF80FFFFF001C1FF0000DFFFFFFFFFFFFF",
INIT_37 => X"FF001FFFFFF3FFFF80FFFFE00001FF0003FFFFFFFFFFFDFFFFFFFC000103E000",
INIT_38 => X"F003DFC00003FF0003FFFFFFFFFFFFFFFFFFFE00000FC000001B079E001FFFFF",
INIT_39 => X"07FFFFFFFFFFFFFFFFFFFE003C0F8000003F1C0F83FFFFFFFE040FFFFFC1FFFF",
INIT_3A => X"FFFFE7007E000000001FFF9FE38FFFFFFF4C0FFFFFE1FFFFF01F9F80100FFF00",
INIT_3B => X"0003FFFFFF8FFFFFFEE007FFFFF9FFFFF03C0E00003FFE000FFFFFFFFFFFFFFF",
INIT_3C => X"F06007FFFFFFC07FF03C0000003FE000FFFFFFFFFFFFFFFFFFFFE70038000001",
INIT_3D => X"BC780006007FE807FFFFFFFFFFFFFFFFFFFFE700300020030018FFFFFF83FFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFE00710080020004FFFFFF81FFFBC00003F03FFF801F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFFFF007800800000007FFFFF80FFF1006003E03FFE0013BF000006007FE01F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_3B => X"FFFE0FFF800000027FDFF807FFFC0FFE1C7C7FFFFC000FFFF030FFFFFE0CFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3A => X"01F8FFFF0003FFF33FFF0FFF98000003FF1FF88FFFFC0FFE1C68FFFFF00FFFFF",
INIT_3E => X"C0FF0FFFF0F9FFFF0171FFF80003FFE1FFF01FFDE00000007FFFF8E3FFFF1FFF",
SIM_COLLISION_CHECK => "NONE",
INIT_3C => X"7FFFF8C7FFFF0FFF08783FFFFF0003FFE0FCFFFFFE19FFFE01F8FFFE0003FFF3",
INIT_3D => X"80F03FFFFFC001DFC0FE1FFFFCF9FFFF01F1FFFC0007FFF3FFF80FFFC0000000",
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"000007FFFFFE7FF0006103871FFC00138E000002007FE0FFFFFFFFFFFFFFFFFF",
INIT_01 => X"01E1A00F9FE000018000000000FE0FFFFFFFFFFFFFFFFFFFFFFFFFE07C3C0100",
INIT_02 => X"80380000007E0FFFFFFFFFFFFFFFFFFFFFFFFFE03C3C0380038007FFFFFFFE00",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFF803C380388C7C0E3FFFFFFFC0003C0F03FFE000103",
INIT_04 => X"FFFFFFC01800001CC3C0F3FDFFFF2000030000F0FC00000380100000E7FF07FF",
INIT_05 => X"E17CFBFFFC4000000C0000001000000391800001EFFC7FFFFFFFFFFFFFFFFFFF",
INIT_06 => X"3C00000000000073F1800003C7FDFFFFFFFFFFFFFFFFFFFFFFFFFFC04000001F",
INIT_07 => X"91800003C7FDFFFFFFFFFFFFFFFFFFFFFFFFFFC5CC00003FE0707B9C60030004",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFDFF871C18007FFF0E1700000003DE4800000000000007",
INIT_09 => X"FFFFFF9F0E3FE07FFF8F8F00000007FE400C00000000000FE7030007FFFFFFFF",
INIT_0A => X"FF9FCF800001EFFFE00E000003E0000FE003800FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"E00F00000000007FE003103FFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFF9EFFF0FF",
INIT_0C => X"E031F1FFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFF3F3FFFF7F83F00003E7FF",
INIT_0D => X"FFFFFFFFFF7FFFFFFFFFFFFFFFF3C3FFFFFF33E00007E7FFC00F000000000007",
INIT_0E => X"FFEFFFFFFFFFC7FFFFFE7B00000FE7FFC000020000000001C079E1FFFFFFFFFF",
INIT_0F => X"FFFFF800003FE7FF8007810000000001C0FFC3FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"C003C00000000001C3FF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFC7FF",
INIT_11 => X"FFFF1FFFFFFFFFFFF1FFFFFFFFFFFFFFFFFFFFC7FFFFCFFFFFFFF80003FE0FFF",
INIT_12 => X"C1FFFFFFFFFFFFFFFFFFFFC3FFFFCFFFFFFFFC0001FC1FFF8003F80000000001",
INIT_13 => X"FFFFFF83FFFBCFFFFFFFFE0001FD9FFE0043800000000003FFFE07FFFFFFFFFF",
INIT_14 => X"FDFFFF0000FC0FF800E00000000000F3FFFC0FFFFFFFFFFC01FFFFFFFFFFFFFF",
INIT_15 => X"00700600000000C1FFF80FFFFFFFFFF007FFFFFFFFFFFFFFFFFFFF03FFC18FFF",
INIT_16 => X"FFF07FFFFFFFFF8007FFFFFFFFFFFFFFFFFFFE0BFFC70FFFFCFFFF00003F0D60",
INIT_17 => X"0FFFFFFFDFFFFFFFFFFFFE0FFFCFE7FFFE7FFF00001F98600000000000000001",
INIT_18 => X"FF7FFC03FFCBFFFFFF3FFF00000FFCF00000000000000001FFF07FFFFFFEF000",
INIT_19 => X"FF1FFF000103FFFF0001000000000001FFE0FFFFFFFFE0001FFFFFFFFFFFFFFF",
INIT_1A => X"C000000000000003FFE0FFFFFFFFC0003FFFFFFFFFFFFFFFFEFFF801FFD9FFFF",
INIT_1B => X"FFFCFFFFFFFFE0003FFFFFFFFFFFFFFFFEFFF803FF99CFFFFF1FFF000383FFFF",
INIT_1C => X"7FFFFFFFFFFFF3FFFCFFFC77FF19C7FFFC0BFF9E00C0FFFFF0000003FE20001F",
INIT_1D => X"FCFFFC7FFE11C3FFFC03FFBE00201FFFF0004003FFFC001FFFF8FFFFFFFFFB00",
INIT_1E => X"FC63FF3C00380FFFFE0000000FFFE01FFFF8FFFFFFFFFF807FFBFFFFFFFFFFFF",
INIT_1F => X"FE00006007FFE03FFFF8FFFFFFFFFF8FFFFFFFFFFFFFFFFFFDFFFCFFFE31C3FF",
INIT_20 => X"FFF0FFFFFFFFFF9FFFFFFFEFFFFFFFFFFFFFFC7FDC33C1FFFFE7FF7C000E0FFF",
INIT_21 => X"FFFFFFEFFFFFFFFFFFFFF87FCE07C3FFFFFFFEFC04070FFFFF0F0033C0FFFC1F",
INIT_22 => X"FFFFF87F8707C3FFFFFFFEFE040993FFFF0F807FFC3FFC0FFFE1FFFFFFFFFF1F",
INIT_23 => X"FFFFFFFE0024D9FFFFFF803FFFFFFC07FFE1FFFFFFFFFE1FFFFFFFDFFFFFFFFF",
INIT_24 => X"FFFF8001FFFFFF07FFE3FFFEFFFFFFFFFFFFFFDFFFFFFFFFFFFFF0FF0727C3FF",
INIT_25 => X"FF87FFFEBFF8FFFEFFFFFFFFFFFFFFFFFFFFF1F8072FE3FFFFFF3FFF4074ECFF",
INIT_26 => X"7EFFFFFFFFFC7FFFFFFFF0F0800FE3FFFFFF0FEFC17C663FFFFFE601FFFFFF0F",
INIT_27 => X"FFFFF800801FE3FFFFFB07C7C06073C7FFFFFF11FFFFFFFFF80FFFFE1FC3FFFF",
INIT_28 => X"FFFB8013C0E03877FFFFFFF0FFFFFFFFF03F003F1F03FFFFF8FFEFFFFFF07FFF",
INIT_29 => X"FFFFFFF07FFFFFFFE1F8338F8107FFFF71FFE0FFFFC03FFFFFFFFE01001FC1FF",
INIT_2A => X"E7E07FC33C0FFE1F0077F0FFFF001FFFFFFFFFF9001FC1FFFFF9C003C0E01871",
INIT_2B => X"8000F0FFFE001FFFFFFFFFFC003FC1FFFFFFE207E06304F8FFFFF1F07FFFFFFF",
INIT_2C => X"FFFFFFFC003FC0FFFFFEE00FFDE244DCFFFFF1807FFFFFFFC7C1FFC03C07FE3F",
INIT_2D => X"FFFF703FFC80401C3FFFFBDF7FFFFFFF870FFFF7C800FE3F0000F1FFFE007FFF",
INIT_2E => X"1FFFFF9F7FFFFFFF803FFFFFC080FC7F06C3FFFFFE00FFFFFFFFFFFE00BFC37F",
INIT_2F => X"807FFFFFC1C0F0FF06FFFFFFFC007FFFFFFFFFFE00BFC07FFFFF30FFFE00403C",
INIT_30 => X"0EFF0FFFF8007FFFFFFFFC7F009FC07FFFFF387FFF000E381FFFF91F7FFFFFFF",
INIT_31 => X"FFFFF87F01DFE03FFFFF3C7FFF81CF0F0FFFFF1C3FFFFFFF80071FFFC1C0E0FE",
INIT_32 => X"FFFF84FFFFC3EF07C7FFFF9F3FFFFFFF80001FFFF3E0CDFF0EFF0FFFF800FFFF",
INIT_33 => X"E0FFFFFFFFFFFFFF80000FFFFFFCDBFE08FFCFFFC000FFFFFFFFF07F006FE01F",
INIT_34 => X"88000700F8FC27FE08CFBFFFC001FFFFFEFFE07F0067C00CFBFFC67FFFC7FF87",
INIT_35 => X"088F3FFFC001FFFFF0FFC0FF0007C01FF9FFEF7FFFC7FFC0601FFFFCBFFFFFFF",
INIT_36 => X"E1FFC1FE000FE01FFC7FFF1FFFC7FFE0300FFFFE1FFFFFFF80000000000E0FFE",
INIT_37 => X"FE1FFF0FFF83FFE01007FFFF87FFFFFF8000003F00029FFE00CF3FFF8001FFFB",
INIT_38 => X"1801FFFFC0FFFFFFE000FFFFF0003FFE01FF7FFF0001FFFBC7FF83FE0007E00F",
INIT_39 => X"F000FFFFFC007FFE01FC7FFF0001FFFBDFFF87FE0000C0037F1FFF0FFF9BFFF0",
INIT_3F => X"2271FFF80803FFC1FFF01FFE300000007FFFFC61FFFF8FFFC0F3FFFFFFE001DF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
WRITE_MODE_B => "WRITE_FIRST",
WRITE_MODE_A => "WRITE_FIRST",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"FFFFEAAAAAAAAAAAFFFFFFFFFFFFFAAAAAAAAAA955555555556BFFFFAAAAFFFF",
SRVAL_A => X"0",
INIT_3D => X"EAAAFFFFFFFAAABFFFFFFFFAAA955555515AAFFFFFFFFFFFAAAAAFFFFFFFFFFF",
INIT_3C => X"FFFEAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAABFFFFFFFFFFFFAAA",
INIT_3B => X"AAAAAAA555555556A9ABFFFFAAAAAFFFEAAAFFFFFFFEAABFFFFFFFFEAA555555",
INIT_3A => X"555AFFFFFFFFFFFEBEAABFFFFFFFFFFFFFFAAAAAABFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFAAAAAAAAAAAFFFFFFFFFFFFAAAAAAAAAA55555555AAAABFFFFEAAAAFFF",
INIT_38 => X"EAAAFFFFFFFEAABFFFFFFFFEAA55555556ABFFFFFFFFFFFABEAABFFFFFFFFFFF",
INIT_37 => X"FFEAAAAAABEAFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAFFFFFFFFFFFFAAA",
INIT_36 => X"AAAAAAA555555556AAABFFFFFAAEABFFFAAABFFFFFFFAAFFFFFFFFFAAA555555",
INIT_35 => X"5AABFFFFFFFFFFFABEAABFFFFFFFFFFFAAAAAAAAAFEAFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFAAAAAAAAAAABFFFFFFFFFFFAAAAAAAAFE955555555AAAFFFFFFAABABFF",
INIT_33 => X"FAAABFFFFFFFBAFFFFFFFFEAA95555555AABFFFFFFFFFFEABABEAFFFFFFFFFFF",
INIT_32 => X"AAAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAFFFFFFFFFFFAA5",
INIT_31 => X"6AAAAFFAA5555555AAAFFFFFFEAFFFFFFEAABFFFFFFFFFFFFFFFFFEAA9555555",
INIT_30 => X"6AAAFFFFFFFFFFAAAABEAFFFFFFFFFFEAAAAAAAAAABFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFAAAAAAAAAAAAAFFFFFFFFFFEA5AAAABFFE955A95A5AAAFEFFFFEABFFFF",
INIT_2E => X"FEAAAFFFFFFFEFFFFFFFFFE9A55555556AAAFFFFFFFFFFAAAABEAFFFFFFFFFAA",
INIT_2D => X"9AAAA6AAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAFAAAAAAAABFFFFFFFFFEA5",
INIT_2C => X"AAAABFFFA5AA956AAAAFEFFFFEAAFFFFFEAAAAFFFFFFEFFFFFFFFFAAA5555556",
INIT_2B => X"6AAFFFFFFFFFFEBEAABEAFFFFFFFFAAA96AA96AAAAAFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFEAAAFAAAAAAAABFFFFFFFFFFAAAAAABFFFEAAA9556AAAFBFFFFA9AFFFF",
INIT_29 => X"FEAAAAFFFFFFEFFFFFFFFEAAA56A5556AAFFFFFFFFFFFABEAAFEAFFFFFFFEAA9",
INIT_28 => X"5AAAAAAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAFEAAAAAAAAFFFFFFFFFFAA",
INIT_27 => X"AAAABFFFFAAA9555AAAFFFFFFE9BFFFFFEAAAAFFFFFFEFFFFFFFFAAAA96A555A",
INIT_26 => X"AAFFFFFFFFFFEAEAABFFAFFFFFFFEAAA5A96AAAAABFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFAAAFEAAAAAAABFFFFFFFFFEA9AAABFFFFEAAA955AAAFFFFFFF9BFFFF",
INIT_24 => X"FEAAAAFFFFFFEFFFFFFFEAAAA969556AAAFFFFFFFFFFEBEAAFFFAFFFFFFEAAAA",
INIT_23 => X"6A56AAAAAFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFAAABFAAAAAAAAFFFFFFFFFFA",
INIT_22 => X"96AABFFFFEAAAA55AAABFFFFFFEBFFFFFFAAAAFFFFFFFFFFFFFFEAAAA9A955AA",
INIT_21 => X"ABFFFFFFFFFFABFAAFFFBFFFFFFAAA55A556AAAAAFFFFFFFFFFFFFFFFFFFFFEB",
INIT_20 => X"FFFFFFFFAAABFAAAAAAAAFFFFFFFFFFE96AAAFFFFEAAAA95AAAABFFFFFEAFFFF",
INIT_1F => X"FFEAAABFFFFFFEFFFFFFEAAAAAAAAAAAABFFFFFFFFFFAFFAABFFFFFFFFEAA969",
INIT_1E => X"955AAAAAAFFFFFFFFFFFFFFFFFFFEAABFFFFFFFFAAAAEAAAAAAAAFFFFFFFFFFE",
INIT_1D => X"96AAAFFFFFFFAAA5AAAAAFFFFFFAFFFFFFFAAAAFFFFFFEFFFFFFAAAAAAAAAAAA",
INIT_1C => X"ABFFFFFFFFFEAFFAABFFFFFFFFEAAAAA55AAAAAAAFFFFFFFFFFFFFFFFFFFAAAB",
INIT_1B => X"FFFFFFFEAAABAAAAAAAAAFFFFFFFFFFE96AAABFFFFFFAAAAAAAAAFFFFFFAFFFF",
INIT_1A => X"FFFAAAAFFFFFFEFFFFFFAAAAAAAAAAAAABFFFFFFFFFAAFEAABFFFFFFFFE956AA",
INIT_19 => X"6AAAAAA6AFFFFFFFFFFFFFFFFFFEAAABFFFFFFFEABFFFAAAAAAAAFFFFFFFFFFF",
INIT_18 => X"A6AAABFFFFFFAAAAA6AAAFFFFFFABFFFFFFFAAAFFFFFFEFFFFFFAAAAAAAAAAAA",
INIT_17 => X"AFFFFFFFFFFAAFAAABFFFFFFFFA95569AAAAAAA5AFFFFFFFFFFFFFFFFFFAAAAB",
INIT_16 => X"FFFFFFFEAFFFFAAAAAAAAFFFFFFFFFFFA6AAAFFFFFFFAAAA96AAAFFFFFFEBFFF",
INIT_15 => X"FFFFEAAFFFFFFEFFFFFAAAAAAAAAAAAABFFFFFFFFFFAAEAAAFFFFFFFFFA9555A",
INIT_14 => X"AAAAAAAAAFFFFFFFFFFFFFFFFFEAAAABFFFFFFFFAFFFFFFAAAAAAFFFFFFFFFFF",
INIT_13 => X"A6AAABFFFFFFAAAA95AAABFFFFFEBFFFFFFFEAAFFFFFFEFFFFEAAAAAAAAAAAAA",
INIT_12 => X"BFFFFFFFFFEAFEAAAFFFFFFFFFA9555AAAAAAAAAAFFFFFFFFFFFFFFFFFFAAAAB",
INIT_11 => X"FFFFFFFFFFFFFFFAAAAAAFFFFFFFFFFEA5AAAAFFFFFFAAAA956AABFFFFFEAFFF",
INIT_10 => X"FFFFEAABFFFFFEFFFFAAAAAAAAAAAAAABFFFFFFFFFEBFAAAABFFFFFFFEAA555A",
INIT_0F => X"AAAAAAAABFFFFFFFFFFFFFFFFFEAABABFFFFFFFFFFFFFFFEAAAAAFFFFFFFFFFE",
INIT_0E => X"95AAAAFFFFFFEAAAA55AABFFFFFFAFFFFFFFEAAAFFFFFEFFFFAAAAAAAAAAAAAA",
INIT_0D => X"BFFFFFFFFFABFABEAFFFFFFFFEAA6A5A56AAAAAAFFFFFFFFFFFFFFFFFFAAAFEB",
INIT_0C => X"FFFFFFFFFFFFEBFFAAAAAFFFFFFFFFFE956AFABFFFFFFEAAA55AABFFFFFFEBFF",
INIT_0B => X"FFFFFAAABFFFFEFFFFAAAAAAAAAAAAAABFFFFFFFFEABFAAFFFFFFFFFFEAAA955",
INIT_0A => X"56AAAAABFFFFFFFFFFFFFFFFFEAAABABFFFFFFFFFFFFAAAFAAA9ABFFFFAFFFFE",
INIT_09 => X"A5AAFAAFFFFFFFAAA55AABFFFFFFFAFFFFFFFAAABFFFFEFFFEAAAAAAAAAAAAAA",
INIT_08 => X"BFFFFFFFFABEABEAFEFFFFFFFFAAA55556AAAAAFFFFFFFFFFFFFFFFFEAAFAAAB",
INIT_07 => X"FEAFFFFFFFFFAAAAAAAAABFFFFFFFFFEAAAAAAAFFFFFFFEAA95AAAFFFFFFFAFF",
INIT_06 => X"FFFFFAAAAFFFFAFFFAAAAAAAAAAAAAAABFFFFFFFFABEABEABFFFFFFFFFA95555",
INIT_05 => X"5AAAAAAFFFFFFFFFFFFFFFFFAAFFEAABFAABFFFFFFFFFFEAAAAAAAFFFFFFFFFF",
INIT_04 => X"A6AAAAAFFFFFFFAAA95AAABFFFFFFAFFFFFFFEAAAFFFFAFFEAAAAAAAAAAAAAAA",
INIT_03 => X"BFFFFFFFFBFAAFAAFFFFFFFFFFA955555AAAAAAFFFFFFFFFFFFFFFFAAAFFAAAB",
INIT_02 => X"FAAAFFFFABFFFFFAAAAA56BFFFFFFFFFA5AAAAAFFFFFFFAAA95AAABFFFFFFAFF",
INIT_01 => X"FFFFFFAAABFFFFFEABAAAAAAAAAAAAAABFFFFFFAAFFABEABFFFFFFFFFEA55555",
INIT_00 => X"5AAA96AFFFFFFFFFFFFFFFFAAAABAAAFFAAAFFFFAAFFFFFFFAA955AFFFFFFFFF",
SRVAL_B => X"0",
INIT_3F => X"5556ABFFFFFFFFFFAAAAABFFFFFFFFFFFFFEAAAAAAFFFFFFFFFFFFFFFFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_A => X"0",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"E0000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000103FFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_B => X"0",
INIT_0D => X"FFFFFFFFFFFFFFFF800000387FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"8000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000039FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000FFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFF8000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"80000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_A => "WRITE_FIRST",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFF80000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_18 => X"FFFFF800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000001FFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000001FFFFFFFFF",
SRVAL_A => X"0",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000001FFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"800000103FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFF",
INIT_22 => X"FFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFF80000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000FFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFF000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SRVAL_B => X"0",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"FFFFFFFFFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFDFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0FFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"8FFCFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0FFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3F",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF817FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFF83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF997FFFFFFFF7FFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFF81FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"80FFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80FE7FFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFF80FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81E",
INIT_35 => X"3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFC3C7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3CFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FE7EFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFF8C67FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FF3F",
INIT_30 => X"F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFF0FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0FFCFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF83F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFF0E707FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF03FFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFF8C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F3FFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFE197FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFF07FFFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE003C3FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00307FFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"800000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFC00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80060FFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"F00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFF800000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800001FFFFFFCFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8203FFFFFFFFCFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"8787FFFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFF8787FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF03FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FE01FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FF3FFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFE03FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SRVAL_B => X"0",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SRVAL_A => X"0",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_21 => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFF7F001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SRVAL_A => X"0",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFC30",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC3FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFF3FFFF7FFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF87FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE3FFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7FFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE3FFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFEDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E3FFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF887FFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9FFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SRVAL_B => X"0",
INIT_18 => X"FFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFFFFE001FFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFE3D07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81FFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFF7FFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE3FFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFC00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7F",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE103FFF",
INIT_29 => X"DFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE383FFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE6FFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F",
INIT_1E => X"0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFE00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFFFFFFEFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"C3FFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFEFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0FFFFF9FFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1FFFFFDFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFC7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFF8E7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"EE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF98FCFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFC1FFFFF9FFC7FFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFF9FFCEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"9FCE0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFBF861FFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFF87EFFFFFFFFFFBF003FFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFC3FFFFFFFFFFFBC007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFBC7FFFFFFFFFFF8001FFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFF1FFFFFFFFFFFFF8003FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FF8FF9FFFFFFFFFF8007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800FFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFF801FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFF801FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"8003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFF8007FFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8007FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFF8007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFBF7EFFFFFFFFFFFFFFFFFFF801FFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFDBE7FFFFFFFFFFFFFFFFFF801FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFF801FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFF",
INIT_25 => X"807FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFFF8BF3FF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE83F9FFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF9FFC3FFFFFFFFFFFFFFFFF87FFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFEFFF1FFF8FFFFFFFFFFFFFFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFF9FFFCC7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"9FFF803FC3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1FFF8F",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9CFF07FFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFE1DBF23FFFFFFFFFFFFFFFFBFFE003FC3FFFFFF",
INIT_2D => X"FFFFFFFFFF7FBFE3FFFFFFFFFFFFFFFFFFF0000837FFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFC000003F7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFF",
INIT_2F => X"FF8000003E3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFBFC3",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFF1C7FFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFE3FFFFFFFFFFFFFFFFE30F0FFFFFFFFFFFFFFFFFFF8E0003E3FFFFF",
INIT_32 => X"FFFFFFFFFFFC10F83FFFFFFFFFFFFFFFFFFFE0000C1FF3FFFFFFFFFFFFFFFFFF",
INIT_33 => X"1FFFFFFFFFFFFFFFFFFFF0000003E7FFFFFFFFFFFFFFFFFFFFFFFFFFFF9FFFFF",
INIT_34 => X"F7FFF8FF0703DFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFFF80078",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8003F9FFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF8001FCFFFFFFFFFFFFFFFFFFFFFFFFFF1FFFF",
INIT_37 => X"FFFFFFFFFFFC001FEFFFFFFFFFFFFFFFFFFFFFFFFFFD7FFFFFFFFFFFFFFFFFFF",
INIT_38 => X"E7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000F",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFF001E397FFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFF001E383FFFFFFFFFFFFFFFFFFFFFFF3FFFF",
INIT_3C => X"FFFFFFFFFFFFF000F787FFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"7F0FFFFFFFFFFFFFFFFFFFFFFF07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFF07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"DFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0003F0FFFFFFFFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena131 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_6(13),
I1 => addra_6(14),
I2 => addra_6(16),
I3 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N18,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52,
O => douta_7(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N18
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N16,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53,
O => douta_7(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N16
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N14,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54,
O => douta_7(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N14
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N12,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55,
O => douta_7(5)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_1 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_11 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(1)
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq00001 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(12),
I1 => addra_6(13),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq000011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(14),
I1 => addra_6(16),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_221 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
I1 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
O => BU2_U0_blk_mem_generator_valid_cstr_N13
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena1 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena01 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(14),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena11 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena121 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(16),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_3 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(15),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_2 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(14),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_1 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(13),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_0 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(12),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_4 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N12,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N11,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_75 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
O => BU2_U0_blk_mem_generator_valid_cstr_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_65 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
O => BU2_U0_blk_mem_generator_valid_cstr_N11
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_3 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N10,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N9,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_74 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
O => BU2_U0_blk_mem_generator_valid_cstr_N10
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_64 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
O => BU2_U0_blk_mem_generator_valid_cstr_N9
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_2 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N7,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_73 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
O => BU2_U0_blk_mem_generator_valid_cstr_N8
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_63 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
O => BU2_U0_blk_mem_generator_valid_cstr_N7
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_1 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N6,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N5,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_72 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
O => BU2_U0_blk_mem_generator_valid_cstr_N6
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_62 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
O => BU2_U0_blk_mem_generator_valid_cstr_N5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_0 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N4,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N3,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_71 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
O => BU2_U0_blk_mem_generator_valid_cstr_N4
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_61 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
O => BU2_U0_blk_mem_generator_valid_cstr_N3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N2,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N1,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_7 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
O => BU2_U0_blk_mem_generator_valid_cstr_N2
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_6 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
O => BU2_U0_blk_mem_generator_valid_cstr_N1
);
BU2_XST_VCC : VCC
port map (
P => BU2_N1
);
BU2_XST_GND : GND
port map (
G => BU2_doutb(0)
);
end STRUCTURE;
-- synopsys translate_on
| gpl-2.0 | 1ea3b61db6846202e19fb03c314366cd | 0.73686 | 2.71422 | false | false | false | false |
freecores/lq057q3dc02 | design/lq057q3dc02_tb.vhd | 1 | 5,372 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: lq057q3dc02_tb.vhd,v 1.2 2008-11-07 05:41:08 jwdonal Exp $
--
-- Description:
-- Test bench to verify lq057q3dc02 pcore.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - pix_enab_clk_cntr.vhd
-- - image_gen.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lq057q3dc02_tb IS
END ENTITY lq057q3dc02_tb;
ARCHITECTURE lq057q3dc02_tb_arch OF lq057q3dc02_tb IS
COMPONENT lq057q3dc02_top
PORT(
RSTx,
CLK_100M_PAD : IN std_logic;
CLK_LCD,
HSYNCx,
VSYNCx,
ENAB,
RL,
UD,
VQ : OUT std_logic;
R,
G,
B : OUT std_logic_vector(6-1 downto 0)
);
END COMPONENT;
--////////////////--
-- INITIAL VALUES --
--////////////////--
signal
RSTx,
CLK_100M_PAD : std_logic := '0';
signal
CLK_LCD,
HSYNCx,
VSYNCx,
ENAB,
RL,
UD,
VQ : std_logic := 'U';
signal
R,
G,
B : std_logic_vector(6-1 downto 0) := (others => 'U');
signal verifyDone : std_logic := '0';
BEGIN
--/////////////////--
-- UNIT UNDER TEST --
--/////////////////--
uut: lq057q3dc02_top
port map (
RSTx => RSTx,
CLK_100M_PAD => CLK_100M_PAD,
CLK_LCD => CLK_LCD,
HSYNCx => HSYNCx,
VSYNCx => VSYNCx,
ENAB => ENAB,
RL => RL,
UD => UD,
VQ => VQ,
R => R,
G => G,
B => B
);
-- System clock generation - 100MHz (50% duty-cycle)
CLK_100M_PAD_gen_PROC : process( CLK_100M_PAD )
begin
if( verifyDone = '0' ) then
if( CLK_100M_PAD = '0' ) then
CLK_100M_PAD <= '1' after 5 ns;
elsif( CLK_100M_PAD = '1' ) then
CLK_100M_PAD <= '0' after 5 ns;
end if;
end if;
end process CLK_100M_PAD_gen_PROC;
--////////////////////--
-- BEGIN VERIFICATION --
--////////////////////--
lq057q3dc02_verify_PROC : process
begin
RSTx <= '0';
wait for 1000 ns; --wait 100 clock cycles
RSTx <= '1'; --release reset
wait for 20 ms; --allow to run long enough to draw one full screen (320x240x160ns ~= 13ms + ~4ms overhead + a little extra)
verifyDone <= '1'; --stops clock from running and prevents simulation from running indefinitely
assert false report "====================================";
assert false report " lq057q3dc02 TEST COMPLETE!!! ";
assert false report " ***This is NOT a failure.*** ";
assert false report "====================================" severity failure;
wait;
end process lq057q3dc02_verify_PROC;
END ARCHITECTURE lq057q3dc02_tb_arch;
| gpl-2.0 | 891fab53100fb34f2e7dea69efcbe910 | 0.461281 | 3.909753 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_mixer.vhdl | 1 | 53,784 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_MISC.all;
ENTITY pokey_mixer IS
PORT
(
CLK : IN STD_LOGIC;
CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
GTIA_SOUND : IN STD_LOGIC;
COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
);
END pokey_mixer;
ARCHITECTURE vhdl OF pokey_mixer IS
signal volume_next : std_logic_vector(15 downto 0);
signal volume_reg : std_logic_vector(15 downto 0);
signal volume_sum : std_logic_vector(9 downto 0);
signal channel_0_en : std_logic_vector(3 downto 0);
signal channel_1_en : std_logic_vector(3 downto 0);
signal channel_2_en : std_logic_vector(3 downto 0);
signal channel_3_en : std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk)
begin
if (clk'event and clk='1') then
volume_reg <= volume_next;
end if;
end process;
-- next state
process(channel_enable,channel_0,channel_1,channel_2,channel_3)
begin
channel_0_en <= channel_0;
channel_1_en <= channel_1;
channel_2_en <= channel_2;
channel_3_en <= channel_3;
-- if (channel_enable(3)='0') then
-- channel_0_en <= X"0";
-- end if;
--
-- if (channel_enable(2)='0') then
-- channel_1_en <= X"0";
-- end if;
--
-- if (channel_enable(1)='0') then
-- channel_2_en <= X"0";
-- end if;
--
-- if (channel_enable(0)='0') then
-- channel_3_en <= X"0";
-- end if;
end process;
process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_sound)
variable channel0_en_long : unsigned(10 downto 0);
variable channel1_en_long : unsigned(10 downto 0);
variable channel2_en_long : unsigned(10 downto 0);
variable channel3_en_long : unsigned(10 downto 0);
variable gtia_sound_long : unsigned(10 downto 0);
variable covox_0_long : unsigned(10 downto 0);
variable covox_1_long : unsigned(10 downto 0);
variable volume_int_sum : unsigned(10 downto 0);
begin
channel0_en_long := (others=>'0');
channel1_en_long := (others=>'0');
channel2_en_long := (others=>'0');
channel3_en_long := (others=>'0');
gtia_sound_long := (others=>'0');
covox_0_long := (others=>'0');
covox_1_long := (others=>'0');
channel0_en_long(7 downto 4) := unsigned(channel_0_en);
channel1_en_long(7 downto 4) := unsigned(channel_1_en);
channel2_en_long(7 downto 4) := unsigned(channel_2_en);
channel3_en_long(7 downto 4) := unsigned(channel_3_en);
gtia_sound_long(7 downto 4) := gtia_sound>ia_sound>ia_sound>ia_sound;
covox_0_long(7 downto 0) := unsigned(covox_channel_0);
covox_1_long(7 downto 0) := unsigned(covox_channel_1);
volume_int_sum := ((channel0_en_long + channel1_en_long) + (channel2_en_long + channel3_en_long)) + (gtia_sound_long + (covox_0_long + covox_1_long));
volume_sum(8 downto 0) <= std_logic_vector(volume_int_sum(8 downto 0));
volume_sum(9) <= volume_int_sum(10) or volume_int_sum(9);
end process;
process (volume_sum, volume_next)
begin
case volume_sum(9 downto 0) is
when "0000000000" =>
volume_next <= X"0000";
when "0000000001" =>
volume_next <= X"00cc";
when "0000000010" =>
volume_next <= X"0198";
when "0000000011" =>
volume_next <= X"0264";
when "0000000100" =>
volume_next <= X"032f";
when "0000000101" =>
volume_next <= X"03fa";
when "0000000110" =>
volume_next <= X"04c4";
when "0000000111" =>
volume_next <= X"058e";
when "0000001000" =>
volume_next <= X"0657";
when "0000001001" =>
volume_next <= X"0720";
when "0000001010" =>
volume_next <= X"07e8";
when "0000001011" =>
volume_next <= X"08b0";
when "0000001100" =>
volume_next <= X"0977";
when "0000001101" =>
volume_next <= X"0a3e";
when "0000001110" =>
volume_next <= X"0b05";
when "0000001111" =>
volume_next <= X"0bcb";
when "0000010000" =>
volume_next <= X"0c91";
when "0000010001" =>
volume_next <= X"0d56";
when "0000010010" =>
volume_next <= X"0e1a";
when "0000010011" =>
volume_next <= X"0edf";
when "0000010100" =>
volume_next <= X"0fa2";
when "0000010101" =>
volume_next <= X"1066";
when "0000010110" =>
volume_next <= X"1128";
when "0000010111" =>
volume_next <= X"11eb";
when "0000011000" =>
volume_next <= X"12ad";
when "0000011001" =>
volume_next <= X"136e";
when "0000011010" =>
volume_next <= X"142f";
when "0000011011" =>
volume_next <= X"14f0";
when "0000011100" =>
volume_next <= X"15b0";
when "0000011101" =>
volume_next <= X"1670";
when "0000011110" =>
volume_next <= X"172f";
when "0000011111" =>
volume_next <= X"17ee";
when "0000100000" =>
volume_next <= X"18ac";
when "0000100001" =>
volume_next <= X"196a";
when "0000100010" =>
volume_next <= X"1a27";
when "0000100011" =>
volume_next <= X"1ae4";
when "0000100100" =>
volume_next <= X"1ba1";
when "0000100101" =>
volume_next <= X"1c5d";
when "0000100110" =>
volume_next <= X"1d18";
when "0000100111" =>
volume_next <= X"1dd3";
when "0000101000" =>
volume_next <= X"1e8e";
when "0000101001" =>
volume_next <= X"1f48";
when "0000101010" =>
volume_next <= X"2002";
when "0000101011" =>
volume_next <= X"20bc";
when "0000101100" =>
volume_next <= X"2174";
when "0000101101" =>
volume_next <= X"222d";
when "0000101110" =>
volume_next <= X"22e5";
when "0000101111" =>
volume_next <= X"239d";
when "0000110000" =>
volume_next <= X"2454";
when "0000110001" =>
volume_next <= X"250a";
when "0000110010" =>
volume_next <= X"25c1";
when "0000110011" =>
volume_next <= X"2677";
when "0000110100" =>
volume_next <= X"272c";
when "0000110101" =>
volume_next <= X"27e1";
when "0000110110" =>
volume_next <= X"2895";
when "0000110111" =>
volume_next <= X"2949";
when "0000111000" =>
volume_next <= X"29fd";
when "0000111001" =>
volume_next <= X"2ab0";
when "0000111010" =>
volume_next <= X"2b63";
when "0000111011" =>
volume_next <= X"2c15";
when "0000111100" =>
volume_next <= X"2cc7";
when "0000111101" =>
volume_next <= X"2d79";
when "0000111110" =>
volume_next <= X"2e2a";
when "0000111111" =>
volume_next <= X"2eda";
when "0001000000" =>
volume_next <= X"2f8b";
when "0001000001" =>
volume_next <= X"303a";
when "0001000010" =>
volume_next <= X"30ea";
when "0001000011" =>
volume_next <= X"3198";
when "0001000100" =>
volume_next <= X"3247";
when "0001000101" =>
volume_next <= X"32f5";
when "0001000110" =>
volume_next <= X"33a2";
when "0001000111" =>
volume_next <= X"3450";
when "0001001000" =>
volume_next <= X"34fc";
when "0001001001" =>
volume_next <= X"35a9";
when "0001001010" =>
volume_next <= X"3654";
when "0001001011" =>
volume_next <= X"3700";
when "0001001100" =>
volume_next <= X"37ab";
when "0001001101" =>
volume_next <= X"3856";
when "0001001110" =>
volume_next <= X"3900";
when "0001001111" =>
volume_next <= X"39a9";
when "0001010000" =>
volume_next <= X"3a53";
when "0001010001" =>
volume_next <= X"3afc";
when "0001010010" =>
volume_next <= X"3ba4";
when "0001010011" =>
volume_next <= X"3c4c";
when "0001010100" =>
volume_next <= X"3cf4";
when "0001010101" =>
volume_next <= X"3d9b";
when "0001010110" =>
volume_next <= X"3e42";
when "0001010111" =>
volume_next <= X"3ee8";
when "0001011000" =>
volume_next <= X"3f8e";
when "0001011001" =>
volume_next <= X"4034";
when "0001011010" =>
volume_next <= X"40d9";
when "0001011011" =>
volume_next <= X"417d";
when "0001011100" =>
volume_next <= X"4222";
when "0001011101" =>
volume_next <= X"42c5";
when "0001011110" =>
volume_next <= X"4369";
when "0001011111" =>
volume_next <= X"440c";
when "0001100000" =>
volume_next <= X"44af";
when "0001100001" =>
volume_next <= X"4551";
when "0001100010" =>
volume_next <= X"45f3";
when "0001100011" =>
volume_next <= X"4694";
when "0001100100" =>
volume_next <= X"4735";
when "0001100101" =>
volume_next <= X"47d5";
when "0001100110" =>
volume_next <= X"4876";
when "0001100111" =>
volume_next <= X"4915";
when "0001101000" =>
volume_next <= X"49b5";
when "0001101001" =>
volume_next <= X"4a53";
when "0001101010" =>
volume_next <= X"4af2";
when "0001101011" =>
volume_next <= X"4b90";
when "0001101100" =>
volume_next <= X"4c2e";
when "0001101101" =>
volume_next <= X"4ccb";
when "0001101110" =>
volume_next <= X"4d68";
when "0001101111" =>
volume_next <= X"4e04";
when "0001110000" =>
volume_next <= X"4ea0";
when "0001110001" =>
volume_next <= X"4f3c";
when "0001110010" =>
volume_next <= X"4fd7";
when "0001110011" =>
volume_next <= X"5072";
when "0001110100" =>
volume_next <= X"510d";
when "0001110101" =>
volume_next <= X"51a7";
when "0001110110" =>
volume_next <= X"5240";
when "0001110111" =>
volume_next <= X"52da";
when "0001111000" =>
volume_next <= X"5372";
when "0001111001" =>
volume_next <= X"540b";
when "0001111010" =>
volume_next <= X"54a3";
when "0001111011" =>
volume_next <= X"553a";
when "0001111100" =>
volume_next <= X"55d2";
when "0001111101" =>
volume_next <= X"5669";
when "0001111110" =>
volume_next <= X"56ff";
when "0001111111" =>
volume_next <= X"5795";
when "0010000000" =>
volume_next <= X"582b";
when "0010000001" =>
volume_next <= X"58c0";
when "0010000010" =>
volume_next <= X"5955";
when "0010000011" =>
volume_next <= X"59e9";
when "0010000100" =>
volume_next <= X"5a7d";
when "0010000101" =>
volume_next <= X"5b11";
when "0010000110" =>
volume_next <= X"5ba4";
when "0010000111" =>
volume_next <= X"5c37";
when "0010001000" =>
volume_next <= X"5cca";
when "0010001001" =>
volume_next <= X"5d5c";
when "0010001010" =>
volume_next <= X"5dee";
when "0010001011" =>
volume_next <= X"5e7f";
when "0010001100" =>
volume_next <= X"5f10";
when "0010001101" =>
volume_next <= X"5fa0";
when "0010001110" =>
volume_next <= X"6031";
when "0010001111" =>
volume_next <= X"60c0";
when "0010010000" =>
volume_next <= X"6150";
when "0010010001" =>
volume_next <= X"61df";
when "0010010010" =>
volume_next <= X"626d";
when "0010010011" =>
volume_next <= X"62fc";
when "0010010100" =>
volume_next <= X"638a";
when "0010010101" =>
volume_next <= X"6417";
when "0010010110" =>
volume_next <= X"64a4";
when "0010010111" =>
volume_next <= X"6531";
when "0010011000" =>
volume_next <= X"65bd";
when "0010011001" =>
volume_next <= X"6649";
when "0010011010" =>
volume_next <= X"66d5";
when "0010011011" =>
volume_next <= X"6760";
when "0010011100" =>
volume_next <= X"67eb";
when "0010011101" =>
volume_next <= X"6875";
when "0010011110" =>
volume_next <= X"68ff";
when "0010011111" =>
volume_next <= X"6989";
when "0010100000" =>
volume_next <= X"6a12";
when "0010100001" =>
volume_next <= X"6a9b";
when "0010100010" =>
volume_next <= X"6b23";
when "0010100011" =>
volume_next <= X"6bac";
when "0010100100" =>
volume_next <= X"6c33";
when "0010100101" =>
volume_next <= X"6cbb";
when "0010100110" =>
volume_next <= X"6d42";
when "0010100111" =>
volume_next <= X"6dc9";
when "0010101000" =>
volume_next <= X"6e4f";
when "0010101001" =>
volume_next <= X"6ed5";
when "0010101010" =>
volume_next <= X"6f5a";
when "0010101011" =>
volume_next <= X"6fdf";
when "0010101100" =>
volume_next <= X"7064";
when "0010101101" =>
volume_next <= X"70e9";
when "0010101110" =>
volume_next <= X"716d";
when "0010101111" =>
volume_next <= X"71f0";
when "0010110000" =>
volume_next <= X"7274";
when "0010110001" =>
volume_next <= X"72f7";
when "0010110010" =>
volume_next <= X"7379";
when "0010110011" =>
volume_next <= X"73fc";
when "0010110100" =>
volume_next <= X"747d";
when "0010110101" =>
volume_next <= X"74ff";
when "0010110110" =>
volume_next <= X"7580";
when "0010110111" =>
volume_next <= X"7601";
when "0010111000" =>
volume_next <= X"7681";
when "0010111001" =>
volume_next <= X"7701";
when "0010111010" =>
volume_next <= X"7781";
when "0010111011" =>
volume_next <= X"7800";
when "0010111100" =>
volume_next <= X"787f";
when "0010111101" =>
volume_next <= X"78fe";
when "0010111110" =>
volume_next <= X"797c";
when "0010111111" =>
volume_next <= X"79fa";
when "0011000000" =>
volume_next <= X"7a77";
when "0011000001" =>
volume_next <= X"7af5";
when "0011000010" =>
volume_next <= X"7b71";
when "0011000011" =>
volume_next <= X"7bee";
when "0011000100" =>
volume_next <= X"7c6a";
when "0011000101" =>
volume_next <= X"7ce6";
when "0011000110" =>
volume_next <= X"7d61";
when "0011000111" =>
volume_next <= X"7ddc";
when "0011001000" =>
volume_next <= X"7e57";
when "0011001001" =>
volume_next <= X"7ed1";
when "0011001010" =>
volume_next <= X"7f4b";
when "0011001011" =>
volume_next <= X"7fc5";
when "0011001100" =>
volume_next <= X"803e";
when "0011001101" =>
volume_next <= X"80b7";
when "0011001110" =>
volume_next <= X"812f";
when "0011001111" =>
volume_next <= X"81a7";
when "0011010000" =>
volume_next <= X"821f";
when "0011010001" =>
volume_next <= X"8297";
when "0011010010" =>
volume_next <= X"830e";
when "0011010011" =>
volume_next <= X"8385";
when "0011010100" =>
volume_next <= X"83fb";
when "0011010101" =>
volume_next <= X"8471";
when "0011010110" =>
volume_next <= X"84e7";
when "0011010111" =>
volume_next <= X"855d";
when "0011011000" =>
volume_next <= X"85d2";
when "0011011001" =>
volume_next <= X"8646";
when "0011011010" =>
volume_next <= X"86bb";
when "0011011011" =>
volume_next <= X"872f";
when "0011011100" =>
volume_next <= X"87a2";
when "0011011101" =>
volume_next <= X"8816";
when "0011011110" =>
volume_next <= X"8889";
when "0011011111" =>
volume_next <= X"88fc";
when "0011100000" =>
volume_next <= X"896e";
when "0011100001" =>
volume_next <= X"89e0";
when "0011100010" =>
volume_next <= X"8a51";
when "0011100011" =>
volume_next <= X"8ac3";
when "0011100100" =>
volume_next <= X"8b34";
when "0011100101" =>
volume_next <= X"8ba4";
when "0011100110" =>
volume_next <= X"8c15";
when "0011100111" =>
volume_next <= X"8c85";
when "0011101000" =>
volume_next <= X"8cf4";
when "0011101001" =>
volume_next <= X"8d64";
when "0011101010" =>
volume_next <= X"8dd3";
when "0011101011" =>
volume_next <= X"8e41";
when "0011101100" =>
volume_next <= X"8eaf";
when "0011101101" =>
volume_next <= X"8f1d";
when "0011101110" =>
volume_next <= X"8f8b";
when "0011101111" =>
volume_next <= X"8ff8";
when "0011110000" =>
volume_next <= X"9065";
when "0011110001" =>
volume_next <= X"90d2";
when "0011110010" =>
volume_next <= X"913e";
when "0011110011" =>
volume_next <= X"91aa";
when "0011110100" =>
volume_next <= X"9216";
when "0011110101" =>
volume_next <= X"9281";
when "0011110110" =>
volume_next <= X"92ec";
when "0011110111" =>
volume_next <= X"9357";
when "0011111000" =>
volume_next <= X"93c1";
when "0011111001" =>
volume_next <= X"942b";
when "0011111010" =>
volume_next <= X"9495";
when "0011111011" =>
volume_next <= X"94fe";
when "0011111100" =>
volume_next <= X"9567";
when "0011111101" =>
volume_next <= X"95d0";
when "0011111110" =>
volume_next <= X"9638";
when "0011111111" =>
volume_next <= X"96a0";
when "0100000000" =>
volume_next <= X"9708";
when "0100000001" =>
volume_next <= X"9770";
when "0100000010" =>
volume_next <= X"97d7";
when "0100000011" =>
volume_next <= X"983d";
when "0100000100" =>
volume_next <= X"98a4";
when "0100000101" =>
volume_next <= X"990a";
when "0100000110" =>
volume_next <= X"9970";
when "0100000111" =>
volume_next <= X"99d5";
when "0100001000" =>
volume_next <= X"9a3b";
when "0100001001" =>
volume_next <= X"9a9f";
when "0100001010" =>
volume_next <= X"9b04";
when "0100001011" =>
volume_next <= X"9b68";
when "0100001100" =>
volume_next <= X"9bcc";
when "0100001101" =>
volume_next <= X"9c30";
when "0100001110" =>
volume_next <= X"9c93";
when "0100001111" =>
volume_next <= X"9cf6";
when "0100010000" =>
volume_next <= X"9d59";
when "0100010001" =>
volume_next <= X"9dbb";
when "0100010010" =>
volume_next <= X"9e1d";
when "0100010011" =>
volume_next <= X"9e7f";
when "0100010100" =>
volume_next <= X"9ee0";
when "0100010101" =>
volume_next <= X"9f41";
when "0100010110" =>
volume_next <= X"9fa2";
when "0100010111" =>
volume_next <= X"a003";
when "0100011000" =>
volume_next <= X"a063";
when "0100011001" =>
volume_next <= X"a0c3";
when "0100011010" =>
volume_next <= X"a122";
when "0100011011" =>
volume_next <= X"a182";
when "0100011100" =>
volume_next <= X"a1e1";
when "0100011101" =>
volume_next <= X"a23f";
when "0100011110" =>
volume_next <= X"a29e";
when "0100011111" =>
volume_next <= X"a2fc";
when "0100100000" =>
volume_next <= X"a359";
when "0100100001" =>
volume_next <= X"a3b7";
when "0100100010" =>
volume_next <= X"a414";
when "0100100011" =>
volume_next <= X"a471";
when "0100100100" =>
volume_next <= X"a4cd";
when "0100100101" =>
volume_next <= X"a52a";
when "0100100110" =>
volume_next <= X"a586";
when "0100100111" =>
volume_next <= X"a5e1";
when "0100101000" =>
volume_next <= X"a63c";
when "0100101001" =>
volume_next <= X"a698";
when "0100101010" =>
volume_next <= X"a6f2";
when "0100101011" =>
volume_next <= X"a74d";
when "0100101100" =>
volume_next <= X"a7a7";
when "0100101101" =>
volume_next <= X"a801";
when "0100101110" =>
volume_next <= X"a85a";
when "0100101111" =>
volume_next <= X"a8b4";
when "0100110000" =>
volume_next <= X"a90c";
when "0100110001" =>
volume_next <= X"a965";
when "0100110010" =>
volume_next <= X"a9be";
when "0100110011" =>
volume_next <= X"aa16";
when "0100110100" =>
volume_next <= X"aa6d";
when "0100110101" =>
volume_next <= X"aac5";
when "0100110110" =>
volume_next <= X"ab1c";
when "0100110111" =>
volume_next <= X"ab73";
when "0100111000" =>
volume_next <= X"abca";
when "0100111001" =>
volume_next <= X"ac20";
when "0100111010" =>
volume_next <= X"ac76";
when "0100111011" =>
volume_next <= X"accc";
when "0100111100" =>
volume_next <= X"ad21";
when "0100111101" =>
volume_next <= X"ad77";
when "0100111110" =>
volume_next <= X"adcb";
when "0100111111" =>
volume_next <= X"ae20";
when "0101000000" =>
volume_next <= X"ae74";
when "0101000001" =>
volume_next <= X"aec8";
when "0101000010" =>
volume_next <= X"af1c";
when "0101000011" =>
volume_next <= X"af70";
when "0101000100" =>
volume_next <= X"afc3";
when "0101000101" =>
volume_next <= X"b016";
when "0101000110" =>
volume_next <= X"b068";
when "0101000111" =>
volume_next <= X"b0bb";
when "0101001000" =>
volume_next <= X"b10d";
when "0101001001" =>
volume_next <= X"b15f";
when "0101001010" =>
volume_next <= X"b1b0";
when "0101001011" =>
volume_next <= X"b201";
when "0101001100" =>
volume_next <= X"b252";
when "0101001101" =>
volume_next <= X"b2a3";
when "0101001110" =>
volume_next <= X"b2f4";
when "0101001111" =>
volume_next <= X"b344";
when "0101010000" =>
volume_next <= X"b393";
when "0101010001" =>
volume_next <= X"b3e3";
when "0101010010" =>
volume_next <= X"b432";
when "0101010011" =>
volume_next <= X"b481";
when "0101010100" =>
volume_next <= X"b4d0";
when "0101010101" =>
volume_next <= X"b51f";
when "0101010110" =>
volume_next <= X"b56d";
when "0101010111" =>
volume_next <= X"b5bb";
when "0101011000" =>
volume_next <= X"b608";
when "0101011001" =>
volume_next <= X"b656";
when "0101011010" =>
volume_next <= X"b6a3";
when "0101011011" =>
volume_next <= X"b6f0";
when "0101011100" =>
volume_next <= X"b73c";
when "0101011101" =>
volume_next <= X"b789";
when "0101011110" =>
volume_next <= X"b7d5";
when "0101011111" =>
volume_next <= X"b821";
when "0101100000" =>
volume_next <= X"b86c";
when "0101100001" =>
volume_next <= X"b8b7";
when "0101100010" =>
volume_next <= X"b902";
when "0101100011" =>
volume_next <= X"b94d";
when "0101100100" =>
volume_next <= X"b998";
when "0101100101" =>
volume_next <= X"b9e2";
when "0101100110" =>
volume_next <= X"ba2c";
when "0101100111" =>
volume_next <= X"ba75";
when "0101101000" =>
volume_next <= X"babf";
when "0101101001" =>
volume_next <= X"bb08";
when "0101101010" =>
volume_next <= X"bb51";
when "0101101011" =>
volume_next <= X"bb99";
when "0101101100" =>
volume_next <= X"bbe2";
when "0101101101" =>
volume_next <= X"bc2a";
when "0101101110" =>
volume_next <= X"bc72";
when "0101101111" =>
volume_next <= X"bcb9";
when "0101110000" =>
volume_next <= X"bd01";
when "0101110001" =>
volume_next <= X"bd48";
when "0101110010" =>
volume_next <= X"bd8f";
when "0101110011" =>
volume_next <= X"bdd5";
when "0101110100" =>
volume_next <= X"be1b";
when "0101110101" =>
volume_next <= X"be62";
when "0101110110" =>
volume_next <= X"bea7";
when "0101110111" =>
volume_next <= X"beed";
when "0101111000" =>
volume_next <= X"bf32";
when "0101111001" =>
volume_next <= X"bf77";
when "0101111010" =>
volume_next <= X"bfbc";
when "0101111011" =>
volume_next <= X"c001";
when "0101111100" =>
volume_next <= X"c045";
when "0101111101" =>
volume_next <= X"c089";
when "0101111110" =>
volume_next <= X"c0cd";
when "0101111111" =>
volume_next <= X"c110";
when "0110000000" =>
volume_next <= X"c154";
when "0110000001" =>
volume_next <= X"c197";
when "0110000010" =>
volume_next <= X"c1d9";
when "0110000011" =>
volume_next <= X"c21c";
when "0110000100" =>
volume_next <= X"c25e";
when "0110000101" =>
volume_next <= X"c2a0";
when "0110000110" =>
volume_next <= X"c2e2";
when "0110000111" =>
volume_next <= X"c324";
when "0110001000" =>
volume_next <= X"c365";
when "0110001001" =>
volume_next <= X"c3a6";
when "0110001010" =>
volume_next <= X"c3e7";
when "0110001011" =>
volume_next <= X"c428";
when "0110001100" =>
volume_next <= X"c468";
when "0110001101" =>
volume_next <= X"c4a8";
when "0110001110" =>
volume_next <= X"c4e8";
when "0110001111" =>
volume_next <= X"c528";
when "0110010000" =>
volume_next <= X"c567";
when "0110010001" =>
volume_next <= X"c5a6";
when "0110010010" =>
volume_next <= X"c5e5";
when "0110010011" =>
volume_next <= X"c624";
when "0110010100" =>
volume_next <= X"c662";
when "0110010101" =>
volume_next <= X"c6a0";
when "0110010110" =>
volume_next <= X"c6de";
when "0110010111" =>
volume_next <= X"c71c";
when "0110011000" =>
volume_next <= X"c75a";
when "0110011001" =>
volume_next <= X"c797";
when "0110011010" =>
volume_next <= X"c7d4";
when "0110011011" =>
volume_next <= X"c811";
when "0110011100" =>
volume_next <= X"c84d";
when "0110011101" =>
volume_next <= X"c88a";
when "0110011110" =>
volume_next <= X"c8c6";
when "0110011111" =>
volume_next <= X"c902";
when "0110100000" =>
volume_next <= X"c93e";
when "0110100001" =>
volume_next <= X"c979";
when "0110100010" =>
volume_next <= X"c9b4";
when "0110100011" =>
volume_next <= X"c9ef";
when "0110100100" =>
volume_next <= X"ca2a";
when "0110100101" =>
volume_next <= X"ca64";
when "0110100110" =>
volume_next <= X"ca9f";
when "0110100111" =>
volume_next <= X"cad9";
when "0110101000" =>
volume_next <= X"cb13";
when "0110101001" =>
volume_next <= X"cb4c";
when "0110101010" =>
volume_next <= X"cb86";
when "0110101011" =>
volume_next <= X"cbbf";
when "0110101100" =>
volume_next <= X"cbf8";
when "0110101101" =>
volume_next <= X"cc31";
when "0110101110" =>
volume_next <= X"cc69";
when "0110101111" =>
volume_next <= X"cca1";
when "0110110000" =>
volume_next <= X"ccd9";
when "0110110001" =>
volume_next <= X"cd11";
when "0110110010" =>
volume_next <= X"cd49";
when "0110110011" =>
volume_next <= X"cd80";
when "0110110100" =>
volume_next <= X"cdb8";
when "0110110101" =>
volume_next <= X"cdee";
when "0110110110" =>
volume_next <= X"ce25";
when "0110110111" =>
volume_next <= X"ce5c";
when "0110111000" =>
volume_next <= X"ce92";
when "0110111001" =>
volume_next <= X"cec8";
when "0110111010" =>
volume_next <= X"cefe";
when "0110111011" =>
volume_next <= X"cf34";
when "0110111100" =>
volume_next <= X"cf69";
when "0110111101" =>
volume_next <= X"cf9f";
when "0110111110" =>
volume_next <= X"cfd4";
when "0110111111" =>
volume_next <= X"d008";
when "0111000000" =>
volume_next <= X"d03d";
when "0111000001" =>
volume_next <= X"d071";
when "0111000010" =>
volume_next <= X"d0a6";
when "0111000011" =>
volume_next <= X"d0da";
when "0111000100" =>
volume_next <= X"d10d";
when "0111000101" =>
volume_next <= X"d141";
when "0111000110" =>
volume_next <= X"d174";
when "0111000111" =>
volume_next <= X"d1a8";
when "0111001000" =>
volume_next <= X"d1db";
when "0111001001" =>
volume_next <= X"d20d";
when "0111001010" =>
volume_next <= X"d240";
when "0111001011" =>
volume_next <= X"d272";
when "0111001100" =>
volume_next <= X"d2a4";
when "0111001101" =>
volume_next <= X"d2d6";
when "0111001110" =>
volume_next <= X"d308";
when "0111001111" =>
volume_next <= X"d33a";
when "0111010000" =>
volume_next <= X"d36b";
when "0111010001" =>
volume_next <= X"d39c";
when "0111010010" =>
volume_next <= X"d3cd";
when "0111010011" =>
volume_next <= X"d3fe";
when "0111010100" =>
volume_next <= X"d42e";
when "0111010101" =>
volume_next <= X"d45e";
when "0111010110" =>
volume_next <= X"d48f";
when "0111010111" =>
volume_next <= X"d4bf";
when "0111011000" =>
volume_next <= X"d4ee";
when "0111011001" =>
volume_next <= X"d51e";
when "0111011010" =>
volume_next <= X"d54d";
when "0111011011" =>
volume_next <= X"d57c";
when "0111011100" =>
volume_next <= X"d5ab";
when "0111011101" =>
volume_next <= X"d5da";
when "0111011110" =>
volume_next <= X"d609";
when "0111011111" =>
volume_next <= X"d637";
when "0111100000" =>
volume_next <= X"d665";
when "0111100001" =>
volume_next <= X"d693";
when "0111100010" =>
volume_next <= X"d6c1";
when "0111100011" =>
volume_next <= X"d6ee";
when "0111100100" =>
volume_next <= X"d71c";
when "0111100101" =>
volume_next <= X"d749";
when "0111100110" =>
volume_next <= X"d776";
when "0111100111" =>
volume_next <= X"d7a3";
when "0111101000" =>
volume_next <= X"d7d0";
when "0111101001" =>
volume_next <= X"d7fc";
when "0111101010" =>
volume_next <= X"d828";
when "0111101011" =>
volume_next <= X"d854";
when "0111101100" =>
volume_next <= X"d880";
when "0111101101" =>
volume_next <= X"d8ac";
when "0111101110" =>
volume_next <= X"d8d8";
when "0111101111" =>
volume_next <= X"d903";
when "0111110000" =>
volume_next <= X"d92e";
when "0111110001" =>
volume_next <= X"d959";
when "0111110010" =>
volume_next <= X"d984";
when "0111110011" =>
volume_next <= X"d9af";
when "0111110100" =>
volume_next <= X"d9d9";
when "0111110101" =>
volume_next <= X"da03";
when "0111110110" =>
volume_next <= X"da2d";
when "0111110111" =>
volume_next <= X"da57";
when "0111111000" =>
volume_next <= X"da81";
when "0111111001" =>
volume_next <= X"daab";
when "0111111010" =>
volume_next <= X"dad4";
when "0111111011" =>
volume_next <= X"dafd";
when "0111111100" =>
volume_next <= X"db26";
when "0111111101" =>
volume_next <= X"db4f";
when "0111111110" =>
volume_next <= X"db78";
when "0111111111" =>
volume_next <= X"dba0";
when "1000000000" =>
volume_next <= X"dbc8";
when "1000000001" =>
volume_next <= X"dbf1";
when "1000000010" =>
volume_next <= X"dc19";
when "1000000011" =>
volume_next <= X"dc40";
when "1000000100" =>
volume_next <= X"dc68";
when "1000000101" =>
volume_next <= X"dc8f";
when "1000000110" =>
volume_next <= X"dcb7";
when "1000000111" =>
volume_next <= X"dcde";
when "1000001000" =>
volume_next <= X"dd05";
when "1000001001" =>
volume_next <= X"dd2c";
when "1000001010" =>
volume_next <= X"dd52";
when "1000001011" =>
volume_next <= X"dd79";
when "1000001100" =>
volume_next <= X"dd9f";
when "1000001101" =>
volume_next <= X"ddc5";
when "1000001110" =>
volume_next <= X"ddeb";
when "1000001111" =>
volume_next <= X"de11";
when "1000010000" =>
volume_next <= X"de36";
when "1000010001" =>
volume_next <= X"de5c";
when "1000010010" =>
volume_next <= X"de81";
when "1000010011" =>
volume_next <= X"dea6";
when "1000010100" =>
volume_next <= X"decb";
when "1000010101" =>
volume_next <= X"def0";
when "1000010110" =>
volume_next <= X"df15";
when "1000010111" =>
volume_next <= X"df39";
when "1000011000" =>
volume_next <= X"df5d";
when "1000011001" =>
volume_next <= X"df82";
when "1000011010" =>
volume_next <= X"dfa6";
when "1000011011" =>
volume_next <= X"dfc9";
when "1000011100" =>
volume_next <= X"dfed";
when "1000011101" =>
volume_next <= X"e011";
when "1000011110" =>
volume_next <= X"e034";
when "1000011111" =>
volume_next <= X"e057";
when "1000100000" =>
volume_next <= X"e07a";
when "1000100001" =>
volume_next <= X"e09d";
when "1000100010" =>
volume_next <= X"e0c0";
when "1000100011" =>
volume_next <= X"e0e2";
when "1000100100" =>
volume_next <= X"e105";
when "1000100101" =>
volume_next <= X"e127";
when "1000100110" =>
volume_next <= X"e149";
when "1000100111" =>
volume_next <= X"e16b";
when "1000101000" =>
volume_next <= X"e18d";
when "1000101001" =>
volume_next <= X"e1af";
when "1000101010" =>
volume_next <= X"e1d0";
when "1000101011" =>
volume_next <= X"e1f2";
when "1000101100" =>
volume_next <= X"e213";
when "1000101101" =>
volume_next <= X"e234";
when "1000101110" =>
volume_next <= X"e255";
when "1000101111" =>
volume_next <= X"e276";
when "1000110000" =>
volume_next <= X"e296";
when "1000110001" =>
volume_next <= X"e2b7";
when "1000110010" =>
volume_next <= X"e2d7";
when "1000110011" =>
volume_next <= X"e2f7";
when "1000110100" =>
volume_next <= X"e317";
when "1000110101" =>
volume_next <= X"e337";
when "1000110110" =>
volume_next <= X"e357";
when "1000110111" =>
volume_next <= X"e377";
when "1000111000" =>
volume_next <= X"e396";
when "1000111001" =>
volume_next <= X"e3b6";
when "1000111010" =>
volume_next <= X"e3d5";
when "1000111011" =>
volume_next <= X"e3f4";
when "1000111100" =>
volume_next <= X"e413";
when "1000111101" =>
volume_next <= X"e432";
when "1000111110" =>
volume_next <= X"e450";
when "1000111111" =>
volume_next <= X"e46f";
when "1001000000" =>
volume_next <= X"e48d";
when "1001000001" =>
volume_next <= X"e4ab";
when "1001000010" =>
volume_next <= X"e4c9";
when "1001000011" =>
volume_next <= X"e4e7";
when "1001000100" =>
volume_next <= X"e505";
when "1001000101" =>
volume_next <= X"e523";
when "1001000110" =>
volume_next <= X"e541";
when "1001000111" =>
volume_next <= X"e55e";
when "1001001000" =>
volume_next <= X"e57b";
when "1001001001" =>
volume_next <= X"e598";
when "1001001010" =>
volume_next <= X"e5b6";
when "1001001011" =>
volume_next <= X"e5d2";
when "1001001100" =>
volume_next <= X"e5ef";
when "1001001101" =>
volume_next <= X"e60c";
when "1001001110" =>
volume_next <= X"e628";
when "1001001111" =>
volume_next <= X"e645";
when "1001010000" =>
volume_next <= X"e661";
when "1001010001" =>
volume_next <= X"e67d";
when "1001010010" =>
volume_next <= X"e699";
when "1001010011" =>
volume_next <= X"e6b5";
when "1001010100" =>
volume_next <= X"e6d1";
when "1001010101" =>
volume_next <= X"e6ec";
when "1001010110" =>
volume_next <= X"e708";
when "1001010111" =>
volume_next <= X"e723";
when "1001011000" =>
volume_next <= X"e73f";
when "1001011001" =>
volume_next <= X"e75a";
when "1001011010" =>
volume_next <= X"e775";
when "1001011011" =>
volume_next <= X"e790";
when "1001011100" =>
volume_next <= X"e7aa";
when "1001011101" =>
volume_next <= X"e7c5";
when "1001011110" =>
volume_next <= X"e7e0";
when "1001011111" =>
volume_next <= X"e7fa";
when "1001100000" =>
volume_next <= X"e814";
when "1001100001" =>
volume_next <= X"e82f";
when "1001100010" =>
volume_next <= X"e849";
when "1001100011" =>
volume_next <= X"e862";
when "1001100100" =>
volume_next <= X"e87c";
when "1001100101" =>
volume_next <= X"e896";
when "1001100110" =>
volume_next <= X"e8b0";
when "1001100111" =>
volume_next <= X"e8c9";
when "1001101000" =>
volume_next <= X"e8e2";
when "1001101001" =>
volume_next <= X"e8fc";
when "1001101010" =>
volume_next <= X"e915";
when "1001101011" =>
volume_next <= X"e92e";
when "1001101100" =>
volume_next <= X"e947";
when "1001101101" =>
volume_next <= X"e960";
when "1001101110" =>
volume_next <= X"e978";
when "1001101111" =>
volume_next <= X"e991";
when "1001110000" =>
volume_next <= X"e9a9";
when "1001110001" =>
volume_next <= X"e9c2";
when "1001110010" =>
volume_next <= X"e9da";
when "1001110011" =>
volume_next <= X"e9f2";
when "1001110100" =>
volume_next <= X"ea0a";
when "1001110101" =>
volume_next <= X"ea22";
when "1001110110" =>
volume_next <= X"ea3a";
when "1001110111" =>
volume_next <= X"ea52";
when "1001111000" =>
volume_next <= X"ea69";
when "1001111001" =>
volume_next <= X"ea81";
when "1001111010" =>
volume_next <= X"ea98";
when "1001111011" =>
volume_next <= X"eab0";
when "1001111100" =>
volume_next <= X"eac7";
when "1001111101" =>
volume_next <= X"eade";
when "1001111110" =>
volume_next <= X"eaf5";
when "1001111111" =>
volume_next <= X"eb0c";
when "1010000000" =>
volume_next <= X"eb23";
when "1010000001" =>
volume_next <= X"eb39";
when "1010000010" =>
volume_next <= X"eb50";
when "1010000011" =>
volume_next <= X"eb66";
when "1010000100" =>
volume_next <= X"eb7d";
when "1010000101" =>
volume_next <= X"eb93";
when "1010000110" =>
volume_next <= X"eba9";
when "1010000111" =>
volume_next <= X"ebbf";
when "1010001000" =>
volume_next <= X"ebd6";
when "1010001001" =>
volume_next <= X"ebeb";
when "1010001010" =>
volume_next <= X"ec01";
when "1010001011" =>
volume_next <= X"ec17";
when "1010001100" =>
volume_next <= X"ec2d";
when "1010001101" =>
volume_next <= X"ec42";
when "1010001110" =>
volume_next <= X"ec58";
when "1010001111" =>
volume_next <= X"ec6d";
when "1010010000" =>
volume_next <= X"ec82";
when "1010010001" =>
volume_next <= X"ec98";
when "1010010010" =>
volume_next <= X"ecad";
when "1010010011" =>
volume_next <= X"ecc2";
when "1010010100" =>
volume_next <= X"ecd7";
when "1010010101" =>
volume_next <= X"eceb";
when "1010010110" =>
volume_next <= X"ed00";
when "1010010111" =>
volume_next <= X"ed15";
when "1010011000" =>
volume_next <= X"ed29";
when "1010011001" =>
volume_next <= X"ed3e";
when "1010011010" =>
volume_next <= X"ed52";
when "1010011011" =>
volume_next <= X"ed67";
when "1010011100" =>
volume_next <= X"ed7b";
when "1010011101" =>
volume_next <= X"ed8f";
when "1010011110" =>
volume_next <= X"eda3";
when "1010011111" =>
volume_next <= X"edb7";
when "1010100000" =>
volume_next <= X"edcb";
when "1010100001" =>
volume_next <= X"eddf";
when "1010100010" =>
volume_next <= X"edf3";
when "1010100011" =>
volume_next <= X"ee06";
when "1010100100" =>
volume_next <= X"ee1a";
when "1010100101" =>
volume_next <= X"ee2d";
when "1010100110" =>
volume_next <= X"ee41";
when "1010100111" =>
volume_next <= X"ee54";
when "1010101000" =>
volume_next <= X"ee67";
when "1010101001" =>
volume_next <= X"ee7b";
when "1010101010" =>
volume_next <= X"ee8e";
when "1010101011" =>
volume_next <= X"eea1";
when "1010101100" =>
volume_next <= X"eeb4";
when "1010101101" =>
volume_next <= X"eec7";
when "1010101110" =>
volume_next <= X"eed9";
when "1010101111" =>
volume_next <= X"eeec";
when "1010110000" =>
volume_next <= X"eeff";
when "1010110001" =>
volume_next <= X"ef11";
when "1010110010" =>
volume_next <= X"ef24";
when "1010110011" =>
volume_next <= X"ef36";
when "1010110100" =>
volume_next <= X"ef49";
when "1010110101" =>
volume_next <= X"ef5b";
when "1010110110" =>
volume_next <= X"ef6d";
when "1010110111" =>
volume_next <= X"ef80";
when "1010111000" =>
volume_next <= X"ef92";
when "1010111001" =>
volume_next <= X"efa4";
when "1010111010" =>
volume_next <= X"efb6";
when "1010111011" =>
volume_next <= X"efc8";
when "1010111100" =>
volume_next <= X"efda";
when "1010111101" =>
volume_next <= X"efeb";
when "1010111110" =>
volume_next <= X"effd";
when "1010111111" =>
volume_next <= X"f00f";
when "1011000000" =>
volume_next <= X"f020";
when "1011000001" =>
volume_next <= X"f032";
when "1011000010" =>
volume_next <= X"f043";
when "1011000011" =>
volume_next <= X"f055";
when "1011000100" =>
volume_next <= X"f066";
when "1011000101" =>
volume_next <= X"f077";
when "1011000110" =>
volume_next <= X"f089";
when "1011000111" =>
volume_next <= X"f09a";
when "1011001000" =>
volume_next <= X"f0ab";
when "1011001001" =>
volume_next <= X"f0bc";
when "1011001010" =>
volume_next <= X"f0cd";
when "1011001011" =>
volume_next <= X"f0de";
when "1011001100" =>
volume_next <= X"f0ef";
when "1011001101" =>
volume_next <= X"f100";
when "1011001110" =>
volume_next <= X"f110";
when "1011001111" =>
volume_next <= X"f121";
when "1011010000" =>
volume_next <= X"f132";
when "1011010001" =>
volume_next <= X"f142";
when "1011010010" =>
volume_next <= X"f153";
when "1011010011" =>
volume_next <= X"f163";
when "1011010100" =>
volume_next <= X"f174";
when "1011010101" =>
volume_next <= X"f184";
when "1011010110" =>
volume_next <= X"f195";
when "1011010111" =>
volume_next <= X"f1a5";
when "1011011000" =>
volume_next <= X"f1b5";
when "1011011001" =>
volume_next <= X"f1c5";
when "1011011010" =>
volume_next <= X"f1d6";
when "1011011011" =>
volume_next <= X"f1e6";
when "1011011100" =>
volume_next <= X"f1f6";
when "1011011101" =>
volume_next <= X"f206";
when "1011011110" =>
volume_next <= X"f216";
when "1011011111" =>
volume_next <= X"f226";
when "1011100000" =>
volume_next <= X"f236";
when "1011100001" =>
volume_next <= X"f245";
when "1011100010" =>
volume_next <= X"f255";
when "1011100011" =>
volume_next <= X"f265";
when "1011100100" =>
volume_next <= X"f275";
when "1011100101" =>
volume_next <= X"f284";
when "1011100110" =>
volume_next <= X"f294";
when "1011100111" =>
volume_next <= X"f2a4";
when "1011101000" =>
volume_next <= X"f2b3";
when "1011101001" =>
volume_next <= X"f2c3";
when "1011101010" =>
volume_next <= X"f2d2";
when "1011101011" =>
volume_next <= X"f2e1";
when "1011101100" =>
volume_next <= X"f2f1";
when "1011101101" =>
volume_next <= X"f300";
when "1011101110" =>
volume_next <= X"f310";
when "1011101111" =>
volume_next <= X"f31f";
when "1011110000" =>
volume_next <= X"f32e";
when "1011110001" =>
volume_next <= X"f33d";
when "1011110010" =>
volume_next <= X"f34c";
when "1011110011" =>
volume_next <= X"f35c";
when "1011110100" =>
volume_next <= X"f36b";
when "1011110101" =>
volume_next <= X"f37a";
when "1011110110" =>
volume_next <= X"f389";
when "1011110111" =>
volume_next <= X"f398";
when "1011111000" =>
volume_next <= X"f3a7";
when "1011111001" =>
volume_next <= X"f3b6";
when "1011111010" =>
volume_next <= X"f3c5";
when "1011111011" =>
volume_next <= X"f3d4";
when "1011111100" =>
volume_next <= X"f3e2";
when "1011111101" =>
volume_next <= X"f3f1";
when "1011111110" =>
volume_next <= X"f400";
when "1011111111" =>
volume_next <= X"f40f";
when "1100000000" =>
volume_next <= X"f41e";
when "1100000001" =>
volume_next <= X"f42c";
when "1100000010" =>
volume_next <= X"f43b";
when "1100000011" =>
volume_next <= X"f44a";
when "1100000100" =>
volume_next <= X"f458";
when "1100000101" =>
volume_next <= X"f467";
when "1100000110" =>
volume_next <= X"f476";
when "1100000111" =>
volume_next <= X"f484";
when "1100001000" =>
volume_next <= X"f493";
when "1100001001" =>
volume_next <= X"f4a1";
when "1100001010" =>
volume_next <= X"f4b0";
when "1100001011" =>
volume_next <= X"f4be";
when "1100001100" =>
volume_next <= X"f4cd";
when "1100001101" =>
volume_next <= X"f4db";
when "1100001110" =>
volume_next <= X"f4ea";
when "1100001111" =>
volume_next <= X"f4f8";
when "1100010000" =>
volume_next <= X"f507";
when "1100010001" =>
volume_next <= X"f515";
when "1100010010" =>
volume_next <= X"f524";
when "1100010011" =>
volume_next <= X"f532";
when "1100010100" =>
volume_next <= X"f540";
when "1100010101" =>
volume_next <= X"f54f";
when "1100010110" =>
volume_next <= X"f55d";
when "1100010111" =>
volume_next <= X"f56b";
when "1100011000" =>
volume_next <= X"f57a";
when "1100011001" =>
volume_next <= X"f588";
when "1100011010" =>
volume_next <= X"f596";
when "1100011011" =>
volume_next <= X"f5a4";
when "1100011100" =>
volume_next <= X"f5b3";
when "1100011101" =>
volume_next <= X"f5c1";
when "1100011110" =>
volume_next <= X"f5cf";
when "1100011111" =>
volume_next <= X"f5dd";
when "1100100000" =>
volume_next <= X"f5ec";
when "1100100001" =>
volume_next <= X"f5fa";
when "1100100010" =>
volume_next <= X"f608";
when "1100100011" =>
volume_next <= X"f616";
when "1100100100" =>
volume_next <= X"f624";
when "1100100101" =>
volume_next <= X"f633";
when "1100100110" =>
volume_next <= X"f641";
when "1100100111" =>
volume_next <= X"f64f";
when "1100101000" =>
volume_next <= X"f65d";
when "1100101001" =>
volume_next <= X"f66b";
when "1100101010" =>
volume_next <= X"f67a";
when "1100101011" =>
volume_next <= X"f688";
when "1100101100" =>
volume_next <= X"f696";
when "1100101101" =>
volume_next <= X"f6a4";
when "1100101110" =>
volume_next <= X"f6b2";
when "1100101111" =>
volume_next <= X"f6c0";
when "1100110000" =>
volume_next <= X"f6cf";
when "1100110001" =>
volume_next <= X"f6dd";
when "1100110010" =>
volume_next <= X"f6eb";
when "1100110011" =>
volume_next <= X"f6f9";
when "1100110100" =>
volume_next <= X"f707";
when "1100110101" =>
volume_next <= X"f716";
when "1100110110" =>
volume_next <= X"f724";
when "1100110111" =>
volume_next <= X"f732";
when "1100111000" =>
volume_next <= X"f740";
when "1100111001" =>
volume_next <= X"f74e";
when "1100111010" =>
volume_next <= X"f75d";
when "1100111011" =>
volume_next <= X"f76b";
when "1100111100" =>
volume_next <= X"f779";
when "1100111101" =>
volume_next <= X"f787";
when "1100111110" =>
volume_next <= X"f796";
when "1100111111" =>
volume_next <= X"f7a4";
when "1101000000" =>
volume_next <= X"f7b2";
when "1101000001" =>
volume_next <= X"f7c0";
when "1101000010" =>
volume_next <= X"f7cf";
when "1101000011" =>
volume_next <= X"f7dd";
when "1101000100" =>
volume_next <= X"f7eb";
when "1101000101" =>
volume_next <= X"f7fa";
when "1101000110" =>
volume_next <= X"f808";
when "1101000111" =>
volume_next <= X"f817";
when "1101001000" =>
volume_next <= X"f825";
when "1101001001" =>
volume_next <= X"f833";
when "1101001010" =>
volume_next <= X"f842";
when "1101001011" =>
volume_next <= X"f850";
when "1101001100" =>
volume_next <= X"f85f";
when "1101001101" =>
volume_next <= X"f86d";
when "1101001110" =>
volume_next <= X"f87c";
when "1101001111" =>
volume_next <= X"f88a";
when "1101010000" =>
volume_next <= X"f899";
when "1101010001" =>
volume_next <= X"f8a7";
when "1101010010" =>
volume_next <= X"f8b6";
when "1101010011" =>
volume_next <= X"f8c4";
when "1101010100" =>
volume_next <= X"f8d3";
when "1101010101" =>
volume_next <= X"f8e2";
when "1101010110" =>
volume_next <= X"f8f0";
when "1101010111" =>
volume_next <= X"f8ff";
when "1101011000" =>
volume_next <= X"f90e";
when "1101011001" =>
volume_next <= X"f91d";
when "1101011010" =>
volume_next <= X"f92b";
when "1101011011" =>
volume_next <= X"f93a";
when "1101011100" =>
volume_next <= X"f949";
when "1101011101" =>
volume_next <= X"f958";
when "1101011110" =>
volume_next <= X"f967";
when "1101011111" =>
volume_next <= X"f976";
when "1101100000" =>
volume_next <= X"f984";
when "1101100001" =>
volume_next <= X"f993";
when "1101100010" =>
volume_next <= X"f9a2";
when "1101100011" =>
volume_next <= X"f9b1";
when "1101100100" =>
volume_next <= X"f9c1";
when "1101100101" =>
volume_next <= X"f9d0";
when "1101100110" =>
volume_next <= X"f9df";
when "1101100111" =>
volume_next <= X"f9ee";
when "1101101000" =>
volume_next <= X"f9fd";
when "1101101001" =>
volume_next <= X"fa0c";
when "1101101010" =>
volume_next <= X"fa1c";
when "1101101011" =>
volume_next <= X"fa2b";
when "1101101100" =>
volume_next <= X"fa3a";
when "1101101101" =>
volume_next <= X"fa4a";
when "1101101110" =>
volume_next <= X"fa59";
when "1101101111" =>
volume_next <= X"fa68";
when "1101110000" =>
volume_next <= X"fa78";
when "1101110001" =>
volume_next <= X"fa87";
when "1101110010" =>
volume_next <= X"fa97";
when "1101110011" =>
volume_next <= X"faa7";
when "1101110100" =>
volume_next <= X"fab6";
when "1101110101" =>
volume_next <= X"fac6";
when "1101110110" =>
volume_next <= X"fad6";
when "1101110111" =>
volume_next <= X"fae5";
when "1101111000" =>
volume_next <= X"faf5";
when "1101111001" =>
volume_next <= X"fb05";
when "1101111010" =>
volume_next <= X"fb15";
when "1101111011" =>
volume_next <= X"fb25";
when "1101111100" =>
volume_next <= X"fb35";
when "1101111101" =>
volume_next <= X"fb45";
when "1101111110" =>
volume_next <= X"fb55";
when "1101111111" =>
volume_next <= X"fb65";
when "1110000000" =>
volume_next <= X"fb75";
when "1110000001" =>
volume_next <= X"fb86";
when "1110000010" =>
volume_next <= X"fb96";
when "1110000011" =>
volume_next <= X"fba6";
when "1110000100" =>
volume_next <= X"fbb7";
when "1110000101" =>
volume_next <= X"fbc7";
when "1110000110" =>
volume_next <= X"fbd7";
when "1110000111" =>
volume_next <= X"fbe8";
when "1110001000" =>
volume_next <= X"fbf9";
when "1110001001" =>
volume_next <= X"fc09";
when "1110001010" =>
volume_next <= X"fc1a";
when "1110001011" =>
volume_next <= X"fc2b";
when "1110001100" =>
volume_next <= X"fc3b";
when "1110001101" =>
volume_next <= X"fc4c";
when "1110001110" =>
volume_next <= X"fc5d";
when "1110001111" =>
volume_next <= X"fc6e";
when "1110010000" =>
volume_next <= X"fc7f";
when "1110010001" =>
volume_next <= X"fc90";
when "1110010010" =>
volume_next <= X"fca1";
when "1110010011" =>
volume_next <= X"fcb3";
when "1110010100" =>
volume_next <= X"fcc4";
when "1110010101" =>
volume_next <= X"fcd5";
when "1110010110" =>
volume_next <= X"fce6";
when "1110010111" =>
volume_next <= X"fcf8";
when "1110011000" =>
volume_next <= X"fd09";
when "1110011001" =>
volume_next <= X"fd1b";
when "1110011010" =>
volume_next <= X"fd2d";
when "1110011011" =>
volume_next <= X"fd3e";
when "1110011100" =>
volume_next <= X"fd50";
when "1110011101" =>
volume_next <= X"fd62";
when "1110011110" =>
volume_next <= X"fd74";
when "1110011111" =>
volume_next <= X"fd86";
when "1110100000" =>
volume_next <= X"fd98";
when "1110100001" =>
volume_next <= X"fdaa";
when "1110100010" =>
volume_next <= X"fdbc";
when "1110100011" =>
volume_next <= X"fdce";
when "1110100100" =>
volume_next <= X"fde0";
when "1110100101" =>
volume_next <= X"fdf3";
when "1110100110" =>
volume_next <= X"fe05";
when "1110100111" =>
volume_next <= X"fe18";
when "1110101000" =>
volume_next <= X"fe2a";
when "1110101001" =>
volume_next <= X"fe3d";
when "1110101010" =>
volume_next <= X"fe50";
when "1110101011" =>
volume_next <= X"fe62";
when "1110101100" =>
volume_next <= X"fe75";
when "1110101101" =>
volume_next <= X"fe88";
when "1110101110" =>
volume_next <= X"fe9b";
when "1110101111" =>
volume_next <= X"feae";
when "1110110000" =>
volume_next <= X"fec1";
when "1110110001" =>
volume_next <= X"fed5";
when "1110110010" =>
volume_next <= X"fee8";
when "1110110011" =>
volume_next <= X"fefb";
when "1110110100" =>
volume_next <= X"ff0f";
when "1110110101" =>
volume_next <= X"ff22";
when "1110110110" =>
volume_next <= X"ff36";
when "1110110111" =>
volume_next <= X"ff4a";
when "1110111000" =>
volume_next <= X"ff5d";
when "1110111001" =>
volume_next <= X"ff71";
when "1110111010" =>
volume_next <= X"ff85";
when "1110111011" =>
volume_next <= X"ff99";
when "1110111100" =>
volume_next <= X"ffad";
when "1110111101" =>
volume_next <= X"ffc1";
when "1110111110" =>
volume_next <= X"ffd6";
when "1110111111" =>
volume_next <= X"ffea";
when "1111000000" =>
volume_next <= X"ffff";
when others =>
volume_next <= X"ffff";
end case;
end process;
-- output
volume_out <= volume_reg;
END vhdl;
| gpl-3.0 | da6d32345dffc67aa9e95e4cbabb85f1 | 0.563718 | 2.789771 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/trace.vhdl | 1 | 12,808 | ------------------------------------------------------------------------------
---- ----
---- ZPU Trace Module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a module to log an ----
---- execution trace. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Trace(Behave) (Entity and architecture) ----
---- File name: trace.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- std.textio ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
entity Trace is
generic(
LOG_FILE : string:="trace.txt"; -- Name of the trace file
ADDR_W : integer:=16; -- Address width
WORD_SIZE : integer:=32); -- 16/32
port(
clk_i : in std_logic;
dbg_i : in zpu_dbgo_t;
stop_i : in std_logic;
busy_i : in std_logic
);
end entity Trace;
architecture Behave of Trace is
file l_file : text open write_mode is LOG_FILE;
signal counter : unsigned(63 downto 0);
begin
-- write data and control information to a file
receive_data:
process
variable l : line;
variable stk_min : unsigned(31 downto 0):=(others => '1');
variable stk_ini : unsigned(31 downto 0);
variable first : boolean:=true;
variable sp_off : unsigned(4 downto 0);
variable idim : boolean:=false;
variable im_val : unsigned(31 downto 0):=(others => '0');
begin
counter <= to_unsigned(1,64);
-- print header for the logfile
print(l_file,"#PC Opcode SP A=[SP] B=[SP+1] Clk Counter Assembler");
print(l_file,"#---------------------------------------------------------------------------");
print(l_file," ");
wait until clk_i='1';
wait until clk_i='0';
while true loop
counter <= counter+1;
if dbg_i.b_inst='1' then
write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))&
" 0x"&hstr(dbg_i.opcode)&
" 0x"&hstr(dbg_i.sp)&
" 0x"&hstr(dbg_i.stk_a)&
" 0x"&hstr(dbg_i.stk_b)&
" 0x"&hstr(counter)&" ");
--------------------------
-- Instruction Decoder --
--------------------------
sp_off(4):=not dbg_i.opcode(4);
sp_off(3 downto 0):=dbg_i.opcode(3 downto 0);
if dbg_i.opcode(7 downto 7)=OPCODE_IM then
if idim then
im_val(31 downto 7):=im_val(24 downto 0);
im_val(6 downto 0):=dbg_i.opcode(6 downto 0);
else
im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32));
end if;
idim:=true;
write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val));
elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then
if sp_off=0 then
write(l,string'("storesp 0 ; pop"));
elsif sp_off=1 then
write(l,string'("storesp 4 ; 1*4 = popdown"));
else
write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then
if sp_off=0 then
write(l,string'("loadsp 0 ; dup"));
elsif sp_off=1 then
write(l,string'("loadsp 4 ; 1*4 = dupstkb"));
else
write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then
if dbg_i.opcode(5 downto 0)=OPCODE_EQ then
write(l,string'("eq"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then
write(l,string'("loadb"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then
write(l,string'("neqbranch"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then
write(l,string'("pushspadd"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then
write(l,string'("lessthan"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then
write(l,string'("ulessthan"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then
write(l,string'("mult"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then
write(l,string'("storeb"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then
write(l,string'("callpcrel"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then
write(l,string'("sub"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
write(l,string'("lessthanorequal"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
write(l,string'("ulessthanorequal"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then
write(l,string'("call"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then
write(l,string'("poppcrel"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
write(l,string'("lshiftright"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then
write(l,string'("loadh"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then
write(l,string'("storeh"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then
write(l,string'("ashiftleft"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then
write(l,string'("ashiftright"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then
write(l,string'("neq"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then
write(l,string'("neg"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then
write(l,string'("xor"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then
write(l,string'("div"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then
write(l,string'("mod"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then
write(l,string'("eqbranch"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then
write(l,string'("config"));
elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then
write(l,string'("pushpc"));
else
write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))&
" ; invalid emulated instruction");
end if;
elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then
if sp_off=0 then
write(l,string'("addsp 0 ; shift"));
elsif sp_off=1 then
write(l,string'("addsp 4 ; 1*4 = addtop"));
else
write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "&
integer'image(to_integer(sp_off))&"*4");
end if;
else -- OPCODE_SHORT
case dbg_i.opcode(3 downto 0) is
when OPCODE_BREAK =>
write(l,string'("break"));
when OPCODE_PUSHSP =>
write(l,string'("pushsp"));
when OPCODE_POPPC =>
write(l,string'("poppc"));
when OPCODE_ADD =>
write(l,string'("add"));
when OPCODE_OR =>
write(l,string'("or"));
when OPCODE_AND =>
write(l,string'("and"));
when OPCODE_LOAD =>
write(l,string'("load"));
when OPCODE_NOT =>
write(l,string'("not"));
when OPCODE_FLIP =>
write(l,string'("flip"));
when OPCODE_STORE =>
write(l,string'("store"));
when OPCODE_POPSP =>
write(l,string'("popsp"));
when OPCODE_NOP =>
write(l,string'("nop"));
when others =>
write(l,integer'image(to_integer(dbg_i.opcode))&
" ; invalid instruction");
end case;
end if;
if dbg_i.opcode(7 downto 7)/=OPCODE_IM then
idim:=false;
end if;
-----------------------------
-- End Instruction Decoder --
-----------------------------
writeline(l_file,l);
if dbg_i.sp<stk_min then
stk_min:=dbg_i.sp;
end if;
if first then
stk_ini:=dbg_i.sp+8;
first:=false;
end if;
end if;
wait until clk_i='0' or stop_i='1';
if stop_i='1' then
print(output,"Minimum SP: 0x"&hstr(stk_min)&" Size: 0x"&hstr(stk_ini-stk_min));
wait;
end if;
end loop;
end process receive_data;
end Behave;
| bsd-3-clause | e1c86b5156587f23baf960bb70bcead1 | 0.38148 | 4.757801 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/fifo_w64_d2_A.vhd | 4 | 4,437 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w64_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w64_d2_A_shiftReg;
architecture rtl of fifo_w64_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w64_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w64_d2_A is
component fifo_w64_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w64_d2_A_shiftReg : fifo_w64_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| mit | 365111763e9dcd7961084896760b99a2 | 0.52558 | 3.4637 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/simulation/bmg_tb_top.vhd | 2 | 4,227 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_top.vhd
--
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BMG_TB_TOP IS
END ENTITY;
ARCHITECTURE BMG_TB_TOP_ARCH OF BMG_TB_TOP IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Simulation Complete"
SEVERITY FAILURE;
END IF;
END PROCESS;
BMG_TB_INST:ENTITY work.BMG_TB
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 63ca5db0a278202154528dfe5dac0342 | 0.615567 | 4.599565 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/SerialSender.vhd | 1 | 1,749 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:02:23 03/15/2015
-- Design Name:
-- Module Name: SerialSender - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SerialSender is
port(
clk : in std_logic;
tx : out std_logic := '1';
data : in std_logic_vector(7 downto 0);
send : in std_logic;
sending : out std_logic := '0'
);
end SerialSender;
architecture RTL of SerialSender is
signal temp_data : std_logic_vector(7 downto 0);
signal bit_pos : integer range 0 to 9 := 0;
signal sending : std_logic := '0';
begin
process(clk) begin
if (clk'event and clk = '1') then
-- serial send
if (send = '1') then
sending <= send;
end if;
if (sending = '1') then
case bit_pos is
when 0 =>
tx <= '0';
bit_pos <= bit_pos + 1;
temp_data <= data;
when 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 =>
bit_pos <= bit_pos + 1;
tx <= temp_data(0);
temp_data <= '1' & temp_data(7 downto 1);
when 9 =>
tx <= '1';
bit_pos <= 0;
sending <= '0';
end case;
end if;
out_sending <= sending;
end if;
end process;
end RTL;
| bsd-3-clause | 0053235c4e11461cd265b1a07edf30e9 | 0.548885 | 3.3125 | false | false | false | false |
freecores/lq057q3dc02 | design/clk_lcd_cyc_cntr.vhd | 1 | 12,889 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: clk_lcd_cyc_cntr.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- Counts the number of CLK_LCD cycles that have occured after C_VSYNC_TVS
-- lines have passed. The output vector is then used by ENAB and the IMAGE
-- generator for pulse and data timing. This method allows for a single
-- common counter for both the ENAB and image controller blocks. THe less
-- efficient way would be to have two counters - one for each block.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY clk_lcd_cyc_cntr IS
generic (
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
port (
RSTx,
CLK_LCD,
HSYNCx,
VSYNCx : IN std_logic;
LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0)
);
END ENTITY clk_lcd_cyc_cntr;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE clk_lcd_cyc_cntr_arch OF clk_lcd_cyc_cntr IS
constant C_NUM_LCD_LINES : positive := 240; -- number of drawable lines in the LCD
constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD
--Enables/disables counter for pixel/enab counter process
signal clk_cyc_cnt_en_sig : std_logic := '0';
--Stores the number of CLK_LCD cycles that have occurred
signal clk_cyc_num_reg : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0');
---------------------------------------------------------------
-- States for CLK_Cntr_cntrl_*_PROC
---------------------------------------------------------------
--INACTIVE_WAIT_1 => wait here until new screen or new line starts
--INACTIVE_WAIT_2 => wait for HSYNCx pulse to deactivate b/c THE is measured from rising edge of HSYNCx pulse
--INACTIVE_WAIT_TVS => wait for TVS timespec to pass
--INACTIVE_WAIT_THE => wait THE timespec to pass
--ACTIVE => enable clock cycle counter
type TYPE_CLK_Cntr_sts is ( INACTIVE_WAIT_1, INACTIVE_WAIT_2,
INACTIVE_WAIT_TVS, INACTIVE_WAIT_THE,
ACTIVE );
signal CLK_Cntr_cs : TYPE_CLK_Cntr_sts;
signal CLK_Cntr_ns : TYPE_CLK_Cntr_sts;
begin
--///////////////////////--
-- CONCURRENT STATEMENTS --
--///////////////////////--
CLK_LCD_CYC_NUM <= clk_cyc_num_reg;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 1 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- only controls the reset of the state and the "current state to
-- next state" assignment.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- CLK_Cntr_cs
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_1_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
CLK_Cntr_cs <= INACTIVE_WAIT_1;
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
CLK_Cntr_cs <= CLK_Cntr_ns;
end if;
end process CLK_Cntr_cntrl_1_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 2 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- controls all of the state changes.
--
-- Inputs:
-- CLK_Cntr_cs
-- HSYNCx
-- VSYNCx
-- LINE_NUM
-- clk_cyc_num_reg
--
-- Outputs:
-- CLK_Cntr_ns
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_2_PROC : process( CLK_Cntr_cs, HSYNCx, VSYNCx, LINE_NUM, clk_cyc_num_reg )
begin
case CLK_Cntr_cs is
when INACTIVE_WAIT_1 => -- once we are in WAIT_1 we are either going to (A) be completely finished drawing the screen or (B) go to the next line.
if( HSYNCx = '0' and VSYNCx = '0' ) then -- if new frame has begun
CLK_Cntr_ns <= INACTIVE_WAIT_TVS; -- go to next state (the reason we do not have to wait for HSYNCx to go high (i.e. go to state INACTIVE_WAIT_2) is b/c LINE_NUM will not change until HSYNCx has already gone high - therefore we do not need to enter WAIT_2 state waiting for HSYNCx to go high. We can just skip that state! :-))
elsif( HSYNCx = '0' and LINE_NUM < (C_VSYNC_TVS + 1) + (C_NUM_LCD_LINES - 1) ) then --if only a new line has begun, not a whole new frame. And only if we have not drawn all the lines already (there is a delay between the last line drawn to the screen and the next VSYNCx pulse!)
CLK_Cntr_ns <= INACTIVE_WAIT_2; -- Once HSYNCx is activated we need to wait for it to deactivate before couting 'THE' CLK_LCD cycles b/c THE timespec is measured from the rising edge of the HSYNCx pulse!!!
else
CLK_Cntr_ns <= INACTIVE_WAIT_1; -- we haven't drawn a full screen yet! Get ready to send another line of data when HSYNCx activates!
end if;
when INACTIVE_WAIT_2 => -- wait for HSYNCx pulse to be deactivated (rise)
if( HSYNCx = '1' ) then
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- Once HSYNCx is deactivated we need to wait THE CLK_LCD cycles before activating again
else
CLK_Cntr_ns <= INACTIVE_WAIT_2; -- keep waiting for HSYNCx pulse to disable
end if;
when INACTIVE_WAIT_TVS =>
if( LINE_NUM = C_VSYNC_TVS + 1 ) then -- if enough lines (HSYNCx pulses) have passed after the *falling* edge of VSYNCx pulse (timespec TVS). We need to start sending exactly on the 8th line (i.e. TVS + 1)!! If we start sending even one line before or even one line after the entire screen will not be drawn!
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- go to next state
else
CLK_Cntr_ns <= INACTIVE_WAIT_TVS; -- still inactive until _after_ 7 lines (HSYNCx pulses) have passed!
end if;
when INACTIVE_WAIT_THE =>
if( clk_cyc_num_reg = C_ENAB_THE - 1 ) then -- 0 to (THE - 1) = THE clocks!
CLK_Cntr_ns <= ACTIVE; -- go to next state (PHEW! We can finally start sending data!)
else
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- still inactive until after timespec THE has passed
end if;
when ACTIVE => -- Now that ENAB is active we want it to stay active for TEP CLK_LCD cycles
if( clk_cyc_num_reg = C_ENAB_THE + C_NUM_LCD_PIXELS - 1 ) then -- C_ENAB_THE to C_ENAB_THE + (320 - 1) = C_ENAB_TEP clocks!
CLK_Cntr_ns <= INACTIVE_WAIT_1; -- once TEP clocks have passed we disable ENAB!
else
CLK_Cntr_ns <= ACTIVE; --enable counter (whose value is used by ENAB controller and image generator)
end if;
when others => --UH OH! How did we get here???
CLK_Cntr_ns <= INACTIVE_WAIT_1;
end case;
end process CLK_Cntr_cntrl_2_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 3 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- only controls the change of output values based on the current
-- state.
--
-- Inputs:
-- CLK_Cntr_cs
--
-- Outputs:
-- clk_cyc_cnt_en_sig
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_3_PROC : process( CLK_Cntr_cs )
begin
case CLK_Cntr_cs is
when INACTIVE_WAIT_1 => --reset counter when not sending data (will go to either TVS-wait if a new frame is starting or INACTIVE_WAIT_2 if just a new line is starting)
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_2 => --reset counter when not sending data (not a new frame, but we still need to wait for HSYNCx to go high, then go to THE)
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_TVS => --reset counter when waiting for 7 lines (TVS) to pass
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_THE => --count THE clock wait for ENAB
clk_cyc_cnt_en_sig <= '1';
when ACTIVE => --count number of pixels to send (320 pixels across)
clk_cyc_cnt_en_sig <= '1';
when others => --UH OH! How did we get here???
clk_cyc_cnt_en_sig <= '0';
end case;
end process CLK_Cntr_cntrl_3_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process enables/disables the pixel/enab counter dependent
-- upon the value of clk_cyc_cnt_en_sig.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- clk_cyc_num_reg
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cycle_Cntr_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
clk_cyc_num_reg <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( clk_cyc_cnt_en_sig = '1' ) then
clk_cyc_num_reg <= clk_cyc_num_reg + 1;
else
clk_cyc_num_reg <= (others => '0');
end if;
end if;
end process CLK_Cycle_Cntr_PROC;
END ARCHITECTURE clk_lcd_cyc_cntr_arch;
| gpl-2.0 | 5d42c05a9c3bf46c0cd875b7b6afa3cd | 0.518271 | 3.965846 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03600_good.vhd | 1 | 3,162 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03600_good.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset sensitive level: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03600_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Async signal
o_Q : out std_logic -- Rising edge of i_D
);
end STD_03600_good;
--CODE
architecture Behavioral of STD_03600_good is
signal D_r1 : std_logic; -- D signal registered 1 time
signal D_r2 : std_logic; -- D signal registered 2 times
signal D_re : std_logic; -- Module output
begin
P_First_Register : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
D_r1 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
end if;
end process;
P_Second_Register : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
D_r2 <= '0';
D_re <= '0';
elsif (rising_edge(i_Clock)) then
D_r2 <= D_r1;
D_re <= D_r1 and not D_r2;
end if;
end process;
o_Q <= D_re;
end Behavioral;
--CODE
| gpl-3.0 | 2dddf2dcf0b5f39e9049a01d0c97cc09 | 0.472802 | 4.244295 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/atari800core.vhd | 1 | 21,619 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
LIBRARY work;
-- There is a higher level that just wires up internal ROM/RAM/joysticks to demonstrate how to use this
-- Also see board specific top levels
ENTITY atari800core IS
GENERIC
(
cycle_length : integer := 16; -- or 32...
video_bits : integer := 8;
palette : integer :=1 -- 0:gtia colour on VIDEO_B, 1:altirra, 2:laoo
);
PORT
(
CLK : IN STD_LOGIC; -- cycle_length*1.79MHz
RESET_N : IN STD_LOGIC;
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VIDEO_VS : OUT STD_LOGIC;
VIDEO_HS : OUT STD_LOGIC;
VIDEO_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_BLANK : out std_logic;
VIDEO_BURST : out std_logic;
VIDEO_START_OF_FIELD : out std_logic;
VIDEO_ODD_LINE : out std_logic;
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
AUDIO_L : OUT std_logic_vector(15 downto 0);
AUDIO_R : OUT std_logic_vector(15 downto 0);
-- PIA
CA1_IN : IN STD_LOGIC; -- SIO Proceed
CB1_IN : IN STD_LOGIC; -- SIO IRQ
CA2_IN : IN STD_LOGIC; -- SIO Motor control
CA2_OUT : OUT STD_LOGIC;
CA2_DIR_OUT: OUT STD_LOGIC; -- 1=output mode
CB2_IN: IN STD_LOGIC;
CB2_OUT : OUT STD_LOGIC; -- SIO Command
CB2_DIR_OUT: OUT STD_LOGIC; -- 1=output mode
PORTA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- For joystick
PORTA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
PORTB_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- For bank switching on XL/XE, for joystick on 800XL
PORTB_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Pokey keyboard matrix
-- Standard component available to connect this to PS2
KEYBOARD_RESPONSE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
KEYBOARD_SCAN : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Pokey pots
POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
POT_RESET : OUT STD_LOGIC;
-- PBI
PBI_ADDR : out STD_LOGIC_VECTOR(15 DOWNTO 0);
PBI_WRITE_ENABLE : out STD_LOGIC; -- currently only for CART config...
PBI_SNOOP_DATA : out std_logic_vector(31 downto 0); -- snoop the bus (i.e. what gets feed to the CPU data in)
PBI_WRITE_DATA : out std_logic_vector(31 downto 0); -- we want to write this to external ram
PBI_WIDTH_8bit_ACCESS : out std_logic;
PBI_WIDTH_16bit_ACCESS : out std_logic;
PBI_WIDTH_32bit_ACCESS : out std_logic;
-- TODO - review this mechanism
-- Since this is intended for real carts, instead should use real timing, though perhaps that can be external...
PBI_ROM_DO : in STD_LOGIC_VECTOR(7 DOWNTO 0);
PBI_REQUEST : out STD_LOGIC;
PBI_REQUEST_COMPLETE : in STD_LOGIC;
-- TODO - also need to allow rest of PBI accesses, refresh handling etc. Can wait...
-- TODO MPD, IRQ, RDY, REFRESH, EXTSEL, RST
-- CARTRIDGE ACCESS
-- (R/W/DO on PBI)
CART_RD4 : in STD_LOGIC;
CART_RD5 : in STD_LOGIC;
CART_S4_n : out STD_LOGIC;
CART_S5_N : out STD_LOGIC;
CART_CCTL_N : out std_logic;
-- SIO
SIO_RXD : in std_logic;
SIO_TXD : out std_logic;
-- SIO_COMMAND_TX - see PIA PB2
-- TODO CLOCK IN/CLOCK OUT (unused almost everywhere...)
-- GTIA consol
-- TODO - GTIA can drive these low - used on 5200 for example!
CONSOL_OPTION : IN STD_LOGIC;
CONSOL_SELECT : IN STD_LOGIC;
CONSOL_START : IN STD_LOGIC;
GTIA_TRIG : IN STD_LOGIC_VECTOR(3 downto 0);
-- ANTIC lightpen
ANTIC_LIGHTPEN : IN std_logic;
ANTIC_REFRESH : out STD_LOGIC; -- 1 'original' cycle high when antic doing refresh cycle...
-----------------------
-- After here all FPGA implementation specific
-- e.g. need to write up RAM/ROM
-- we can dma from memory space
-- etc.
-- External RAM/ROM - adhere to standard memory map
-- TODO - lower/upper memory split defined by generic
-- (TODO SRAM lower ram, SDRAM upper ram - no overlap?)
---- SRAM memory map (512k) (if USE_SDRAM=0)
---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
---- SDRAM memory map (8MB) (lower 512k if USE_SDRAM=1)
---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
---- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
---- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
---- SCRATCH - 4MB+64k-5MB
---- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
--SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
---- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
--SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
--SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
---- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
-- TODO - review if we need to pass out so many of these
-- Perhaps we can simplify address decoder and have an external layer?
SDRAM_REQUEST : OUT std_logic;
SDRAM_REQUEST_COMPLETE : IN std_logic;
SDRAM_READ_ENABLE : out STD_LOGIC;
SDRAM_WRITE_ENABLE : out std_logic;
SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
RAM_DO : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
RAM_REQUEST : OUT STD_LOGIC;
RAM_REQUEST_COMPLETE : IN STD_LOGIC;
RAM_WRITE_ENABLE : OUT STD_LOGIC;
ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
ROM_DO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ROM_REQUEST : OUT STD_LOGIC;
ROM_REQUEST_COMPLETE : IN STD_LOGIC;
-- DMA memory map differs
-- e.g. some special addresses to read behind hardware registers
-- 0x0000-0xffff: Atari registers + 3 mirrors (bit 16/17)
-- 23 downto 21:
-- 001 : SRAM,512k
-- 010|011 : ROM, 4MB
-- 10xx : SDRAM, 8MB (If you have more, its unmapped for now... Can bank switch! Atari can't access this much anyway...)
DMA_FETCH : in STD_LOGIC; -- we want to read/write
DMA_READ_ENABLE : in std_logic;
DMA_32BIT_WRITE_ENABLE : in std_logic;
DMA_16BIT_WRITE_ENABLE : in std_logic;
DMA_8BIT_WRITE_ENABLE : in std_logic;
DMA_ADDR : in std_logic_vector(23 downto 0);
DMA_WRITE_DATA : in std_logic_vector(31 downto 0);
MEMORY_READY_DMA : out std_logic; -- op complete
-- Special config params
RAM_SELECT : in std_logic_vector(2 downto 0); -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB
ROM_SELECT : in std_logic_vector(5 downto 0); -- 16KB ROM Bank - 0 is illegal (slot used for BASIC!) TODO FIXME, change stupid slot 0 thing...
CART_EMULATION_SELECT : in std_logic_vector(6 downto 0); -- from where
CART_EMULATION_ACTIVATE : in std_logic; -- to where? TODO, these needs redoing and wiring up!
PAL : in STD_LOGIC;
USE_SDRAM : in STD_LOGIC;
ROM_IN_RAM : in std_logic;
THROTTLE_COUNT_6502 : in STD_LOGIC_VECTOR(5 DOWNTO 0);
HALT : in std_logic
);
END atari800core;
ARCHITECTURE bdf_type OF atari800core IS
-- ANTIC
SIGNAL ANTIC_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL ANTIC_AN : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ANTIC_COLOUR_CLOCK_OUT : STD_LOGIC;
SIGNAL ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_ANTIC_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ANTIC_FETCH : STD_LOGIC;
SIGNAL ANTIC_HIGHRES_COLOUR_CLOCK_OUT : STD_LOGIC;
SIGNAL ANTIC_ORIGINAL_COLOUR_CLOCK_OUT : STD_LOGIC;
SIGNAL ANTIC_RDY : STD_LOGIC;
SIGNAL ANTIC_WRITE_ENABLE : STD_LOGIC;
SIGNAL BREAK_PRESSED : STD_LOGIC;
signal hcount_temp : std_logic_vector(7 downto 0);
signal vcount_temp : std_logic_vector(8 downto 0);
signal ANTIC_REFRESH_CYCLE : STD_LOGIC;
-- GTIA
SIGNAL GTIA_SOUND : STD_LOGIC;
SIGNAL GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_GTIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL GTIA_WRITE_ENABLE : STD_LOGIC;
signal COLOUR : std_logic_vector(7 downto 0);
-- GTIA PALETTE
signal VIDEO_R_WIDE : std_logic_vector(7 downto 0);
signal VIDEO_G_WIDE : std_logic_vector(7 downto 0);
signal VIDEO_B_WIDE : std_logic_vector(7 downto 0);
-- CPU
SIGNAL CPU_6502_RESET : STD_LOGIC;
SIGNAL CPU_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CPU_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CPU_FETCH : STD_LOGIC;
SIGNAL IRQ_n : STD_LOGIC;
SIGNAL NMI_n : STD_LOGIC;
SIGNAL R_W_N : STD_LOGIC;
-- CLOCKING STUFF
-- TODO - review/explain what all these are for
SIGNAL CPU_SHARED_ENABLE : STD_LOGIC;
SIGNAL ENABLE_179_MEMWAIT : STD_LOGIC;
SIGNAL ANTIC_ENABLE_179 : STD_LOGIC;
-- POKEY
SIGNAL POKEY_IRQ : STD_LOGIC;
SIGNAL POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_POKEY_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC;
signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
SIGNAL POKEY2_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CACHE_POKEY2_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL POKEY2_WRITE_ENABLE : STD_LOGIC;
signal POKEY2_CHANNEL0 : std_logic_vector(3 downto 0);
signal POKEY2_CHANNEL1 : std_logic_vector(3 downto 0);
signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
-- COVOX (after market DAC)
signal covox_write_enable : std_logic;
signal covox_channel0 : std_logic_vector(7 downto 0);
signal covox_channel1 : std_logic_vector(7 downto 0);
signal covox_channel2 : std_logic_vector(7 downto 0);
signal covox_channel3 : std_logic_vector(7 downto 0);
-- MEMORY IS READY - input to all devices
SIGNAL MEMORY_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL MEMORY_READY_ANTIC : STD_LOGIC;
SIGNAL MEMORY_READY_CPU : STD_LOGIC;
SIGNAL WRITE_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL WIDTH_16BIT_ACCESS : STD_LOGIC;
SIGNAL WIDTH_32BIT_ACCESS : STD_LOGIC;
SIGNAL WIDTH_8BIT_ACCESS : STD_LOGIC;
-- PIA
SIGNAL PIA_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PIA_IRQA : STD_LOGIC;
SIGNAL PIA_IRQB : STD_LOGIC;
SIGNAL PIA_READ_ENABLE : STD_LOGIC;
SIGNAL PIA_WRITE_ENABLE : STD_LOGIC;
SIGNAL PORTB_OUT_INT : STD_LOGIC_VECTOR(7 downto 0);
-- PBI
SIGNAL PBI_ADDR_INT : std_logic_vector(15 downto 0);
BEGIN
PBI_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
PBI_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
PBI_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
PBI_WRITE_DATA <= WRITE_DATA;
PBI_SNOOP_DATA <= MEMORY_DATA;
enables : entity work.shared_enable
GENERIC MAP(cycle_length => cycle_length)
PORT MAP(CLK => CLK,
RESET_N => RESET_N,
MEMORY_READY_CPU => MEMORY_READY_CPU,
MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
ANTIC_REFRESH => ANTIC_REFRESH_CYCLE,
PAUSE_6502 => HALT,
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
oldcpu_enable => ENABLE_179_MEMWAIT,
CPU_ENABLE_OUT => CPU_SHARED_ENABLE);
CPU_6502_RESET <= NOT(RESET_N);
cpu6502 : entity work.cpu
PORT MAP(CLK => CLK,
RESET => CPU_6502_RESET,
ENABLE => RESET_N,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
MEMORY_READY => MEMORY_READY_CPU,
THROTTLE => CPU_SHARED_ENABLE,
RDY => ANTIC_RDY,
DI => MEMORY_DATA(7 DOWNTO 0),
R_W_n => R_W_N,
CPU_FETCH => CPU_FETCH,
A => CPU_ADDR,
DO => CPU_DO);
antic1 : entity work.antic
GENERIC MAP(cycle_length => cycle_length)
PORT MAP(CLK => CLK,
WR_EN => ANTIC_WRITE_ENABLE,
RESET_N => RESET_N,
MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
MEMORY_READY_CPU => MEMORY_READY_CPU,
ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
PAL => PAL,
lightpen => ANTIC_LIGHTPEN,
ADDR => PBI_ADDR_INT(3 DOWNTO 0),
CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
NMI_N_OUT => NMI_n,
ANTIC_READY => ANTIC_RDY,
COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
dma_fetch_out => ANTIC_FETCH,
hcount_out => hcount_temp,
vcount_out => vcount_temp,
refresh_out => ANTIC_REFRESH_CYCLE,
AN => ANTIC_AN,
DATA_OUT => ANTIC_DO,
dma_address_out => ANTIC_ADDR);
pokey_mixer_l : entity work.pokey_mixer
PORT MAP(CLK => CLK,
GTIA_SOUND => GTIA_SOUND,
CHANNEL_0 => POKEY1_CHANNEL0,
CHANNEL_1 => POKEY1_CHANNEL1,
CHANNEL_2 => POKEY1_CHANNEL2,
CHANNEL_3 => POKEY1_CHANNEL3,
CHANNEL_ENABLE => "1111",
COVOX_CHANNEL_0 => covox_channel0,
COVOX_CHANNEL_1 => covox_channel1,
VOLUME_OUT => AUDIO_L);
pokey_mixer_r : entity work.pokey_mixer
PORT MAP(CLK => CLK,
GTIA_SOUND => GTIA_SOUND,
CHANNEL_0 => POKEY2_CHANNEL0,
CHANNEL_1 => POKEY2_CHANNEL1,
CHANNEL_2 => POKEY2_CHANNEL2,
CHANNEL_3 => POKEY2_CHANNEL3,
COVOX_CHANNEL_0 => covox_channel2,
COVOX_CHANNEL_1 => covox_channel3,
CHANNEL_ENABLE => "1111",
VOLUME_OUT => AUDIO_R);
pokey2 : entity work.pokey
PORT MAP(CLK => CLK,
ENABLE_179 => ENABLE_179_MEMWAIT,
WR_EN => POKEY2_WRITE_ENABLE,
RESET_N => RESET_N,
ADDR => PBI_ADDR_INT(3 DOWNTO 0),
DATA_IN => WRITE_DATA(7 DOWNTO 0),
CHANNEL_0_OUT => POKEY2_CHANNEL0,
CHANNEL_1_OUT => POKEY2_CHANNEL1,
CHANNEL_2_OUT => POKEY2_CHANNEL2,
CHANNEL_3_OUT => POKEY2_CHANNEL3,
DATA_OUT => POKEY2_DO,
SIO_IN1 => '1',
SIO_IN2 => '1',
SIO_IN3 => '1',
keyboard_response => "00",
pot_in=>"00000000");
pia1 : entity work.pia
PORT MAP(CLK => CLK,
EN => PIA_READ_ENABLE,
WR_EN => PIA_WRITE_ENABLE,
RESET_N => RESET_N,
CA1 => CA1_IN,
CB1 => CB1_IN,
CA2_DIR_OUT => CA2_DIR_OUT,
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
ADDR => PBI_ADDR_INT(1 DOWNTO 0),
CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
IRQA_N => PIA_IRQA,
IRQB_N => PIA_IRQB,
DATA_OUT => PIA_DO,
PORTA_IN => PORTA_IN,
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => PORTB_DIR_OUT,
PORTB_OUT => PORTB_OUT_INT);
mmu1 : entity work.address_decoder
PORT MAP(CLK => CLK,
CPU_FETCH => CPU_FETCH,
CPU_WRITE_N => R_W_N,
ANTIC_FETCH => ANTIC_FETCH,
DMA_FETCH => DMA_FETCH,
DMA_READ_ENABLE => DMA_READ_ENABLE,
DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
CART_REQUEST_COMPLETE => PBI_REQUEST_COMPLETE,
reset_n => RESET_N,
CART_RD4 => CART_RD4,
CART_RD5 => CART_RD5,
use_sdram => USE_SDRAM,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
ANTIC_ADDR => ANTIC_ADDR,
ANTIC_DATA => ANTIC_DO,
CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
CART_ROM_DATA => PBI_ROM_DO,
CPU_ADDR => CPU_ADDR,
CPU_WRITE_DATA => CPU_DO,
GTIA_DATA => GTIA_DO,
CACHE_GTIA_DATA => CACHE_GTIA_DO,
PIA_DATA => PIA_DO,
POKEY2_DATA => POKEY2_DO,
CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
POKEY_DATA => POKEY_DO,
CACHE_POKEY_DATA => CACHE_POKEY_DO,
PORTB => PORTB_OUT_INT,
RAM_DATA => RAM_DO,
ram_select => RAM_SELECT(2 downto 0),
ROM_DATA => ROM_DO,
rom_select => ROM_SELECT,
SDRAM_DATA => SDRAM_DO,
DMA_ADDR => DMA_ADDR,
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
MEMORY_READY_DMA => MEMORY_READY_DMA,
MEMORY_READY_CPU => MEMORY_READY_CPU,
GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
PIA_WR_ENABLE => PIA_WRITE_ENABLE,
PIA_RD_ENABLE => PIA_READ_ENABLE,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
PBI_WR_ENABLE => PBI_WRITE_ENABLE,
RAM_REQUEST => RAM_REQUEST,
ROM_REQUEST => ROM_REQUEST,
CART_REQUEST => PBI_REQUEST,
CART_S4_n => CART_S4_n,
CART_S5_n => CART_S5_N,
CART_CCTL_n => CART_CCTL_N,
WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
SDRAM_READ_EN => SDRAM_READ_ENABLE,
SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
SDRAM_REQUEST => SDRAM_REQUEST,
MEMORY_DATA => MEMORY_DATA,
PBI_ADDR => PBI_ADDR_INT,
RAM_ADDR => RAM_ADDR,
ROM_ADDR => ROM_ADDR,
SDRAM_ADDR => SDRAM_ADDR,
WRITE_DATA => WRITE_DATA,
d6_wr_enable => covox_write_enable,
cart_select => CART_EMULATION_SELECT,
cart_activate => CART_EMULATION_ACTIVATE,
rom_in_ram => ROM_IN_RAM);
pokey1 : entity work.pokey
PORT MAP(CLK => CLK,
ENABLE_179 => ENABLE_179_MEMWAIT,
WR_EN => POKEY_WRITE_ENABLE,
RESET_N => RESET_N,
SIO_IN1 => SIO_RXD,
SIO_IN2 => '1',
SIO_IN3 => '1',
ADDR => PBI_ADDR_INT(3 DOWNTO 0),
DATA_IN => WRITE_DATA(7 DOWNTO 0),
keyboard_response => KEYBOARD_RESPONSE,
POT_IN => POT_IN,
IRQ_N_OUT => POKEY_IRQ,
SIO_OUT1 => SIO_TXD,
SIO_OUT2 => open,
SIO_OUT3 => open,
POT_RESET => POT_RESET,
CHANNEL_0_OUT => POKEY1_CHANNEL0,
CHANNEL_1_OUT => POKEY1_CHANNEL1,
CHANNEL_2_OUT => POKEY1_CHANNEL2,
CHANNEL_3_OUT => POKEY1_CHANNEL3,
DATA_OUT => POKEY_DO,
keyboard_scan => KEYBOARD_SCAN);
gtia1 : entity work.gtia
PORT MAP(CLK => CLK,
WR_EN => GTIA_WRITE_ENABLE,
ANTIC_FETCH => ANTIC_FETCH, -- for first pmg fetch
CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT, -- for subsequent pmg fetches
RESET_N => RESET_N,
PAL => PAL,
COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
TRIG0 => GTIA_TRIG(0),
TRIG1 => GTIA_TRIG(1),
TRIG2 => GTIA_TRIG(2),
TRIG3 => GTIA_TRIG(3),
ADDR => PBI_ADDR_INT(4 DOWNTO 0),
AN => ANTIC_AN,
CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
VSYNC => VIDEO_VS,
HSYNC => VIDEO_HS,
BLANK => VIDEO_BLANK,
BURST => VIDEO_BURST,
START_OF_FIELD => VIDEO_START_OF_FIELD,
ODD_LINE => VIDEO_ODD_LINE,
sound => GTIA_SOUND,
COLOUR_out => COLOUR,
DATA_OUT => GTIA_DO);
-- colour palette
-- Color Value Color Value
--Black 0, 0 Medium blue 8, 128
--Rust 1, 16 Dark blue 9, 144
--Red-orange 2, 32 Blue-grey 10, 160
--Dark orange 3, 48 Olive green 11, 176
--Red 4, 64 Medium green 12, 192
--Dk lavender 5, 80 Dark green 13, 208
--Cobalt blue 6, 96 Orange-green 14, 224
--Ultramarine 7, 112 Orange 15, 240
gen_palette_none : if palette=0 generate
VIDEO_B_WIDE <= COLOUR;
VIDEO_R_WIDE <= (others => '0');
VIDEO_G_WIDE <= (others => '0');
end generate;
gen_palette_altirra : if palette=1 generate
palette1 : entity work.gtia_palette(altirra)
port map (ATARI_COLOUR=>COLOUR, R_next=>VIDEO_R_WIDE, G_next=>VIDEO_G_WIDE, B_next=>VIDEO_B_WIDE);
end generate;
gen_palette_laoo : if palette=2 generate
palette2 : entity work.gtia_palette(laoo)
port map (ATARI_COLOUR=>COLOUR, R_next=>VIDEO_R_WIDE, G_next=>VIDEO_G_WIDE, B_next=>VIDEO_B_WIDE);
end generate;
VIDEO_R(video_bits-1 downto 0) <= VIDEO_R_WIDE(7 downto 8-video_bits);
VIDEO_G(video_bits-1 downto 0) <= VIDEO_G_WIDE(7 downto 8-video_bits);
VIDEO_B(video_bits-1 downto 0) <= VIDEO_B_WIDE(7 downto 8-video_bits);
irq_glue1 : entity work.irq_glue
PORT MAP(pokey_irq => POKEY_IRQ,
pia_irqa => PIA_IRQA,
pia_irqb => PIA_IRQB,
combined_irq => IRQ_n);
-- TODO - generic ram infer?
pokey1_mirror : entity work.reg_file
generic map(BYTES=>16,WIDTH=>4)
port map(
CLK => CLK,
ADDR => PBI_ADDR_INT(3 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
WR_EN => POKEY_WRITE_ENABLE,
DATA_OUT => CACHE_POKEY_DO
);
pokey2_mirror : entity work.reg_file
generic map(BYTES=>16,WIDTH=>4)
port map(
CLK => CLK,
ADDR => PBI_ADDR_INT(3 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
WR_EN => POKEY2_WRITE_ENABLE,
DATA_OUT => CACHE_POKEY2_DO
);
gtia_mirror : entity work.reg_file
generic map(BYTES=>32,WIDTH=>5)
port map(
CLK => CLK,
ADDR => PBI_ADDR_INT(4 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
WR_EN => GTIA_WRITE_ENABLE,
DATA_OUT => CACHE_GTIA_DO
);
antic_mirror : entity work.reg_file
generic map(BYTES=>16,WIDTH=>4)
port map(
CLK => CLK,
ADDR => PBI_ADDR_INT(3 downto 0),
DATA_IN => WRITE_DATA(7 downto 0),
WR_EN => ANTIC_WRITE_ENABLE,
DATA_OUT => CACHE_ANTIC_DO
);
covox1 : entity work.covox
PORT map
(
clk => clk,
addr => pbi_addr_int(1 downto 0),
data_in => WRITE_DATA(7 DOWNTO 0),
wr_en => covox_write_enable,
covox_channel0 => covox_channel0,
covox_channel1 => covox_channel1,
covox_channel2 => covox_channel2,
covox_channel3 => covox_channel3
);
-- outputs
PBI_ADDR <= PBI_ADDR_INT;
PORTB_OUT <= PORTB_OUT_INT;
ANTIC_REFRESH <= ANTIC_REFRESH_CYCLE;
END bdf_type;
| gpl-3.0 | c5c1d919757978d5a6a979f569b5d5e5 | 0.653545 | 2.829712 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/Heater.vhd | 1 | 1,081 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Heater is
port(
rst : in std_logic;
clk50Mhz : in std_logic;
pulseWidth : in std_logic_vector(7 downto 0);
heaterEnable : out std_logic
);
end Heater;
architecture Behavioral of Heater is
signal counter : integer range 0 to 255;
signal pulseWidthReg : integer range 0 to 255;
signal heaterEnableSignal : std_logic;
attribute keep : string;
attribute keep of heaterEnable: signal is "true";
attribute S: string;
attribute S of heaterEnable: signal is "yes";
begin
heaterEnable <= heaterEnableSignal;
process(clk50Mhz,rst,counter)
begin
if rst='1' or counter = 255 then
counter <= 0;
elsif clk50Mhz'event and clk50Mhz = '1' then
counter <= counter + 1;
end if;
end process;
process(clk50Mhz,rst)
begin
if rst = '1' then
pulseWidthReg <= 0;
elsif clk50Mhz'event and clk50Mhz = '1' then
pulseWidthReg <= to_integer(unsigned(pulseWidth));
end if;
end process;
heaterEnableSignal <= '1' when pulseWidthReg > counter else '0';
end Behavioral;
| mit | 00e52e1e5509064c21ef6f8725874840 | 0.707678 | 3.124277 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/ppi/i82c55.vhd | 1 | 21,192 | --
-- A simulation model of Scramble hardware
-- Copyright (c) MikeJ - Feb 2007
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity I82C55 is
port (
I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0
I_DATA : in std_logic_vector(7 downto 0); -- D7-D0
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_CS_L : in std_logic;
I_RD_L : in std_logic;
I_WR_L : in std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
I_PC : in std_logic_vector(7 downto 0);
O_PC : out std_logic_vector(7 downto 0);
RESET : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
CLK : in std_logic
);
end;
architecture RTL of I82C55 is
-- registers
signal bit_mask : std_logic_vector(7 downto 0);
signal r_porta : std_logic_vector(7 downto 0);
signal r_portb : std_logic_vector(7 downto 0);
signal r_portc : std_logic_vector(7 downto 0);
signal r_control : std_logic_vector(7 downto 0);
--
signal porta_we : std_logic;
signal portb_we : std_logic;
signal porta_re : std_logic;
signal portb_re : std_logic;
--
signal porta_we_t1 : std_logic;
signal portb_we_t1 : std_logic;
signal porta_re_t1 : std_logic;
signal portb_re_t1 : std_logic;
--
signal porta_we_rising : boolean;
signal portb_we_rising : boolean;
signal porta_re_rising : boolean;
signal portb_re_rising : boolean;
--
signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper
signal groupb_mode : std_logic; -- port b/c lower
--
signal porta_read : std_logic_vector(7 downto 0);
signal portb_read : std_logic_vector(7 downto 0);
signal portc_read : std_logic_vector(7 downto 0);
signal control_read : std_logic_vector(7 downto 0);
signal mode_clear : std_logic;
--
signal a_inte1 : std_logic;
signal a_inte2 : std_logic;
signal b_inte : std_logic;
--
signal a_intr : std_logic;
signal a_obf_l : std_logic;
signal a_ibf : std_logic;
signal a_ack_l : std_logic;
signal a_stb_l : std_logic;
signal a_ack_l_t1 : std_logic;
signal a_stb_l_t1 : std_logic;
--
signal b_intr : std_logic;
signal b_obf_l : std_logic;
signal b_ibf : std_logic;
signal b_ack_l : std_logic;
signal b_stb_l : std_logic;
signal b_ack_l_t1 : std_logic;
signal b_stb_l_t1 : std_logic;
--
signal a_ack_l_rising : boolean;
signal a_stb_l_rising : boolean;
signal b_ack_l_rising : boolean;
signal b_stb_l_rising : boolean;
--
signal porta_ipreg : std_logic_vector(7 downto 0);
signal portb_ipreg : std_logic_vector(7 downto 0);
begin
--
-- mode 0 - basic input/output
-- mode 1 - strobed input/output
-- mode 2/3 - bi-directional bus
--
-- control word (write)
--
-- D7 mode set flag 1 = active
-- D6..5 GROUPA mode selection (mode 0,1,2)
-- D4 GROUPA porta 1 = input, 0 = output
-- D3 GROUPA portc upper 1 = input, 0 = output
-- D2 GROUPB mode selection (mode 0 ,1)
-- D1 GROUPB portb 1 = input, 0 = output
-- D0 GROUPB portc lower 1 = input, 0 = output
--
-- D7 bit set/reset 0 = active
-- D6..4 x
-- D3..1 bit select
-- d0 1 = set, 0 - reset
--
-- all output registers including status are reset when mode is changed
--1. Port A:
--All Modes: Output data is cleared, input data is not cleared.
--2. Port B:
--Mode 0: Output data is cleared, input data is not cleared.
--Mode 1 and 2: Both output and input data are cleared.
--3. Port C:
--Mode 0:Output data is cleared, input data is not cleared.
--Mode 1 and 2: IBF and INTR are cleared and OBF# is set.
--Outputs in Port C which are not used for handshaking or interrupt signals are cleared.
--Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled.
p_bit_mask : process(I_DATA)
begin
bit_mask <= x"01";
case I_DATA(3 downto 1) is
when "000" => bit_mask <= x"01";
when "001" => bit_mask <= x"02";
when "010" => bit_mask <= x"04";
when "011" => bit_mask <= x"08";
when "100" => bit_mask <= x"10";
when "101" => bit_mask <= x"20";
when "110" => bit_mask <= x"40";
when "111" => bit_mask <= x"80";
when others => null;
end case;
end process;
p_write_reg_reset : process(RESET, CLK)
variable r_portc_masked : std_logic_vector(7 downto 0);
variable r_portc_setclr : std_logic_vector(7 downto 0);
begin
if (RESET = '1') then
r_porta <= x"00";
r_portb <= x"00";
r_portc <= x"00";
r_control <= x"9B"; -- 10011011
mode_clear <= '1';
elsif rising_edge(CLK) then
r_portc_masked := (not bit_mask) and r_portc;
for i in 0 to 7 loop
r_portc_setclr(i) := bit_mask(i) and I_DATA(0);
end loop;
if (ENA = '1') then
mode_clear <= '0';
if (I_CS_L = '0') and (I_WR_L = '0') then
case I_ADDR is
when "00" => r_porta <= I_DATA;
when "01" => r_portb <= I_DATA;
when "10" => r_portc <= I_DATA;
when "11" => if (I_DATA(7) = '0') then -- set/clr
r_portc <= r_portc_masked or r_portc_setclr;
else
--svo: uncommented
mode_clear <= '1';
r_porta <= x"00";
r_portb <= x"00"; -- clear port b input reg
r_portc <= x"00"; -- clear control sigs
r_control <= I_DATA; -- load new mode
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_decode_control : process(r_control)
begin
groupa_mode <= r_control(6 downto 5);
groupb_mode <= r_control(2);
end process;
p_oe : process(I_CS_L, I_RD_L)
begin
O_DATA_OE_L <= '1';
if (I_CS_L = '0') and (I_RD_L = '0') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process(I_ADDR, I_CS_L, I_RD_L, porta_read, portb_read, portc_read, control_read)
begin
-- O_DATA <= x"00"; -- default
-- if (I_CS_L = '0') and (I_RD_L = '0') then -- not required
case I_ADDR is
when "00" => O_DATA <= porta_read;
when "01" => O_DATA <= portb_read;
when "10" => O_DATA <= portc_read;
when "11" => O_DATA <= control_read;
when others => null;
end case;
-- end if;
end process;
control_read(7) <= '1'; -- always 1
control_read(6 downto 0) <= r_control(6 downto 0);
p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR)
begin
porta_we <= '0';
portb_we <= '0';
porta_re <= '0';
portb_re <= '0';
if (I_CS_L = '0') and (I_ADDR = "00") then
porta_we <= not I_WR_L;
porta_re <= not I_RD_L;
end if;
if (I_CS_L = '0') and (I_ADDR = "01") then
portb_we <= not I_WR_L;
portb_re <= not I_RD_L;
end if;
end process;
p_rw_control_reg : process
begin
wait until rising_edge(CLK);
if (ENA = '1') then
porta_we_t1 <= porta_we;
portb_we_t1 <= portb_we;
porta_re_t1 <= porta_re;
portb_re_t1 <= portb_re;
a_stb_l_t1 <= a_stb_l;
a_ack_l_t1 <= a_ack_l;
b_stb_l_t1 <= b_stb_l;
b_ack_l_t1 <= b_ack_l;
end if;
end process;
porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted
portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- "
porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted
portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- "
--
a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0');
a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0');
b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0');
b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0');
--
-- GROUP A
-- in mode 1
--
-- d4=1 (porta = input)
-- pc7,6 io (d3=1 input, d3=0 output)
-- pc5 output a_ibf
-- pc4 input a_stb_l
-- pc3 output a_intr
--
-- d4=0 (porta = output)
-- pc7 output a_obf_l
-- pc6 input a_ack_l
-- pc5,4 io (d3=1 input, d3=0 output)
-- pc3 output a_intr
--
-- GROUP B
-- in mode 1
-- d1=1 (portb = input)
-- pc2 input b_stb_l
-- pc1 output b_ibf
-- pc0 output b_intr
--
-- d1=0 (portb = output)
-- pc2 input b_ack_l
-- pc1 output b_obf_l
-- pc0 output b_intr
-- WHEN AN INPUT
--
-- stb_l a low on this input latches input data
-- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L
-- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L
-- inte A controlled by bit/set PC4
-- inte B controlled by bit/set PC2
-- WHEN AN OUTPUT
--
-- obf_l output will go low when cpu has written data
-- ack_l input - a low on this clears obf_l
-- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L
-- inte A controlled by bit/set PC6
-- inte B controlled by bit/set PC2
-- GROUP A
-- in mode 2
--
-- porta = IO
--
-- control bits 2..0 still control groupb/c lower 2..0
--
--
-- PC7 output a_obf
-- PC6 input a_ack_l
-- PC5 output a_ibf
-- PC4 input a_stb_l
-- PC3 is still interrupt out
p_control_flags : process(RESET, CLK)
variable we : boolean;
variable set1 : boolean;
variable set2 : boolean;
begin
if (RESET = '1') then
a_obf_l <= '1';
a_inte1 <= '0';
a_ibf <= '0';
a_inte2 <= '0';
a_intr <= '0';
--
b_inte <= '0';
b_obf_l <= '1';
b_ibf <= '0';
b_intr <= '0';
elsif rising_edge(CLK) then
we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0');
if (ENA = '1') then
if (mode_clear = '1') then
a_obf_l <= '1';
a_inte1 <= '0';
a_ibf <= '0';
a_inte2 <= '0';
a_intr <= '0';
--
b_inte <= '0';
b_obf_l <= '1';
b_ibf <= '0';
b_intr <= '0';
else
if (bit_mask(7) = '1') and we then
a_obf_l <= I_DATA(0);
else
if porta_we_rising then
a_obf_l <= '0';
elsif (a_ack_l = '0') then
a_obf_l <= '1';
end if;
end if;
--
if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input?
--
if (bit_mask(5) = '1') and we then
a_ibf <= I_DATA(0);
else
if porta_re_rising then
a_ibf <= '0';
elsif (a_stb_l = '0') then
a_ibf <= '1';
end if;
end if;
--
if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output?
--
set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1');
set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1');
--
if (bit_mask(3) = '1') and we then
a_intr <= I_DATA(0);
else
if (groupa_mode(1) = '1') then
if (porta_we = '1') or (porta_re = '1') then
a_intr <= '0';
elsif set1 or set2 then
a_intr <= '1';
end if;
else
if (r_control(4) = '0') then -- output
if (porta_we = '1') then -- falling ?
a_intr <= '0';
elsif set1 then
a_intr <= '1';
end if;
elsif (r_control(4) = '1') then -- input
if (porta_re = '1') then -- falling ?
a_intr <= '0';
elsif set2 then
a_intr <= '1';
end if;
end if;
end if;
end if;
--
if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set?
if (bit_mask(1) = '1') and we then
b_obf_l <= I_DATA(0);
else
if (r_control(1) = '0') then -- output
if portb_we_rising then
b_obf_l <= '0';
elsif (b_ack_l = '0') then
b_obf_l <= '1';
end if;
else
if portb_re_rising then
b_ibf <= '0';
elsif (b_stb_l = '0') then
b_ibf <= '1';
end if;
end if;
end if;
if (bit_mask(0) = '1') and we then
b_intr <= I_DATA(0);
else
if (r_control(1) = '0') then -- output
if (portb_we = '1') then -- falling ?
b_intr <= '0';
elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then
b_intr <= '1';
end if;
else
if (portb_re = '1') then -- falling ?
b_intr <= '0';
elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then
b_intr <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_porta : process(r_porta, r_control, groupa_mode, I_PA, porta_ipreg, a_ack_l)
begin
-- D4 GROUPA porta 1 = input, 0 = output
O_PA <= x"FF"; -- if not driven, float high
porta_read <= x"00";
if (groupa_mode = "00") then -- simple io
if (r_control(4) = '0') then -- output
O_PA <= r_porta;
end if;
porta_read <= I_PA;
elsif (groupa_mode = "01") then -- strobed
if (r_control(4) = '0') then -- output
O_PA <= r_porta;
end if;
porta_read <= porta_ipreg;
else -- if (groupa_mode(1) = '1') then -- bi dir
if (a_ack_l = '0') then -- output enable
O_PA <= r_porta;
end if;
porta_read <= porta_ipreg; -- latched data
end if;
end process;
p_portb : process(r_portb, r_control, groupb_mode, I_PB, portb_ipreg)
begin
O_PB <= x"FF"; -- if not driven, float high
portb_read <= x"00";
if (groupb_mode = '0') then -- simple io
if (r_control(1) = '0') then -- output
O_PB <= r_portb;
end if;
portb_read <= I_PB;
else -- strobed mode
if (r_control(1) = '0') then -- output
O_PB <= r_portb;
end if;
portb_read <= portb_ipreg;
end if;
end process;
p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode,
a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr)
begin
O_PC <= x"FF"; -- if not driven, float high
-- bits 7..4
if (groupa_mode = "00") then -- simple io
if (r_control(3) = '0') then -- output
O_PC (7 downto 4) <= r_portc(7 downto 4);
end if;
elsif (groupa_mode = "01") then -- mode1
if (r_control(4) = '0') then -- port a output
O_PC (7) <= a_obf_l;
-- 6 is ack_l input
if (r_control(3) = '0') then -- port c output
O_PC (5 downto 4) <= r_portc(5 downto 4);
end if;
else -- port a input
if (r_control(3) = '0') then -- port c output
O_PC (7 downto 6) <= r_portc(7 downto 6);
end if;
O_PC (5) <= a_ibf;
-- 4 is stb_l input
end if;
else -- if (groupa_mode(1) = '1') then -- mode2
O_PC (7) <= a_obf_l;
-- 6 is ack_l input
O_PC (5) <= a_ibf;
-- 4 is stb_l input
end if;
-- bit 3 (controlled by group a)
if (groupa_mode = "00") then -- group a steals this bit
--if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this
if (r_control(0) = '0') then -- ouput (note, groupb control bit)
O_PC (3) <= r_portc(3);
end if;
--
else -- stolen
O_PC (3) <= a_intr;
end if;
-- bits 2..0
if (groupb_mode = '0') then -- simple io
if (r_control(0) = '0') then -- output
O_PC (2 downto 0) <= r_portc(2 downto 0);
end if;
else
-- mode 1
-- 2 is input
if (r_control(1) = '0') then -- output
O_PC (1) <= b_obf_l;
else -- input
O_PC (1) <= b_ibf;
end if;
O_PC (0) <= b_intr;
end if;
end process;
p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l,
a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr)
begin
portc_read <= x"00";
a_stb_l <= '1';
a_ack_l <= '1';
b_stb_l <= '1';
b_ack_l <= '1';
if (groupa_mode = "01") then -- mode1 or 2
if (r_control(4) = '0') then -- port a output
a_ack_l <= I_PC(6);
else -- port a input
a_stb_l <= I_PC(4);
end if;
elsif (groupa_mode(1) = '1') then -- mode 2
a_ack_l <= I_PC(6);
a_stb_l <= I_PC(4);
end if;
if (groupb_mode = '1') then
if (r_control(1) = '0') then -- output
b_ack_l <= I_PC(2);
else -- input
b_stb_l <= I_PC(2);
end if;
end if;
if (groupa_mode = "00") then -- simple io
portc_read(7 downto 3) <= I_PC(7 downto 3);
elsif (groupa_mode = "01") then
if (r_control(4) = '0') then -- port a output
portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr;
else -- input
portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr;
end if;
else -- mode 2
portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr;
end if;
if (groupb_mode = '0') then -- simple io
portc_read(2 downto 0) <= I_PC(2 downto 0);
else
if (r_control(1) = '0') then -- output
portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr;
else -- input
portc_read(2 downto 0) <= b_inte & b_ibf & b_intr;
end if;
end if;
end process;
p_ipreg : process
begin
wait until rising_edge(CLK);
-- pc4 input a_stb_l
-- pc2 input b_stb_l
if (ENA = '1') then
if (a_stb_l = '0') then
porta_ipreg <= I_PA;
end if;
if (mode_clear = '1') then
portb_ipreg <= (others => '0');
elsif (b_stb_l = '0') then
portb_ipreg <= I_PB;
end if;
end if;
end process;
end architecture RTL;
-- $Id: i82c55.vhd 294 2008-02-12 20:27:35Z svofski $
| gpl-3.0 | 244bdb132fc9fb2582bad4cc45cafbfe | 0.5042 | 3.10551 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/alf/src/alf.vhd | 1 | 6,936 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alf is
Port (
CLK50 : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end alf;
architecture rtl of alf is
signal CLK : std_logic;
signal VGA_CLK : std_logic;
signal LOCKED : std_logic;
signal RESET : std_logic;
signal TICK : unsigned(3 downto 0);
signal CPU_CLK : std_logic;
signal CPU_INT : std_logic;
signal CPU_MREQ : std_logic;
signal CPU_IORQ : std_logic;
signal CPU_RD : std_logic;
signal CPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal ROM_A : std_logic_vector(19 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal VRAM_VA : std_logic_vector(12 downto 0);
signal VRAM_VD : std_logic_vector(7 downto 0);
signal BORDERCOLOR : std_logic_vector(2 downto 0);
signal RAM1_DO : std_logic_vector(7 downto 0);
signal RAM1_WR : std_logic_vector(0 downto 0);
signal RAM2_DO : std_logic_vector(7 downto 0);
signal RAM2_WR : std_logic_vector(0 downto 0);
signal RAM3_DO : std_logic_vector(7 downto 0);
signal RAM3_WR : std_logic_vector(0 downto 0);
signal KEYB_DO : std_logic_vector(4 downto 0);
signal ROM_REG : std_logic_vector(7 downto 0);
signal KB_RESET : std_logic;
signal BEEPER : std_logic;
begin
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK,
VGA_CLK => VGA_CLK,
LOCKED => LOCKED );
u_VIDEO : entity work.video
port map(
VGA_CLK => VGA_CLK,
RESET => '0',
BORDERCOLOR => BORDERCOLOR,
INT => CPU_INT,
VA => VRAM_VA,
VD => VRAM_VD,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
u_CPU : entity work.T80se
port map(
RESET_n => not RESET,
CLK_n => CLK,
CLKEN => CPU_CLK,
WAIT_n => '1',
INT_n => CPU_INT,
NMI_n => '1',
BUSRQ_n => '1',
M1_n => OPEN,
MREQ_n => CPU_MREQ,
IORQ_n => CPU_IORQ,
RD_n => CPU_RD,
WR_n => CPU_WR,
RFSH_n => OPEN,
HALT_n => OPEN,
BUSAK_n => OPEN,
A => CPU_A,
DI => CPU_DI,
DO => CPU_DO );
--u_ROM : entity work.rom
--port map(
-- clka => CLK,
-- addra => CPU_A(13 downto 0),
-- douta => ROM_DO );
u_RAM1 : entity work.vram
port map(
clka => CLK,
wea => RAM1_WR,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => RAM1_DO,
clkb => VGA_CLK,
web => "0",
addrb => '0' & VRAM_VA,
dinb => "00000000",
doutb => VRAM_VD );
u_RAM2 : entity work.ram
port map(
clka => CLK,
wea => RAM2_WR,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => RAM2_DO );
u_RAM3 : entity work.ram
port map(
clka => CLK,
wea => RAM3_WR,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => RAM3_DO );
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
KEYB_DATA => KEYB_DO,
RESET_TICK => KB_RESET );
reset_and_clock : process(CLK)
begin
if rising_edge(CLK) then
if LOCKED = '0' or KB_RESET = '1' then
TICK <= "0000";
RESET <= '1';
CPU_CLK <= '0';
else
CPU_CLK <= '0';
TICK <= TICK + 1;
if TICK = "1111" then
CPU_CLK <= '1';
RESET <= '0';
end if;
end if;
end if;
end process;
SOUND_L <= BEEPER;
SOUND_R <= BEEPER;
CPU_DI <= ROM_DO when CPU_A(15 downto 14) = "00" and CPU_MREQ = '0' and ROM_REG(7) = '0'
else ROM_DO when CPU_A(15 downto 14) = "00" and CPU_MREQ = '0' and ROM_REG(6 downto 4) = "000"
else RAM1_DO when CPU_A(15 downto 14) = "01" and CPU_MREQ = '0'
else RAM2_DO when CPU_A(15 downto 14) = "10" and CPU_MREQ = '0'
else RAM3_DO when CPU_A(15 downto 14) = "11" and CPU_MREQ = '0'
else "000" & KEYB_DO when CPU_A(5) = '0' and CPU_RD = '0' and CPU_IORQ = '0'
else "11111111" when CPU_A(0) = '0' and CPU_RD = '0' and CPU_IORQ = '0'
else "11111111";
RAM1_WR <= "1" when CPU_A(15 downto 14) = "01" and CPU_MREQ = '0' and CPU_WR = '0' else "0";
RAM2_WR <= "1" when CPU_A(15 downto 14) = "10" and CPU_MREQ = '0' and CPU_WR = '0' else "0";
RAM3_WR <= "1" when CPU_A(15 downto 14) = "11" and CPU_MREQ = '0' and CPU_WR = '0' else "0";
ROM_A <= ROM_REG(7) & '0' & ROM_REG(3 downto 0) & CPU_A(13 downto 0);
SRAM_A <= ROM_A(18 downto 1);
SRAM_WE <= '1';
SRAM_OE <= '0';
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_CE0 <= ROM_A(19);
SRAM_CE1 <= not ROM_A(19);
SRAM_D <= "ZZZZZZZZZZZZZZZZ";
ROM_DO <= SRAM_D(7 downto 0) when ROM_A(0) = '0' else SRAM_D(15 downto 8);
romreg : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
ROM_REG <= "00000000";
else
if CPU_IORQ = '0' and CPU_WR = '0' and CPU_A(5) = '0' then
ROM_REG <= CPU_DO;
end if;
if CPU_IORQ = '0' and CPU_WR = '0' and CPU_A(0) = '0' then
BEEPER <= CPU_DO(4);
BORDERCOLOR <= CPU_DO(2 downto 0);
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 5e2235480241a13c875d6696b10926a4 | 0.462226 | 3.120108 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_00700_good.vhd | 1 | 3,044 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-01 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_00700_good.vhd
-- File Creation date : 2015-04-01
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of signal name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_00700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_00700_good;
--CODE
architecture Behavioral of STD_00700_good is
signal D : std_logic; -- First Flip-Flop output
signal Q : std_logic; -- Block output
begin
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => D,
o_Q_n => open
);
P_FlipFlop : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= D;
end if;
end process;
end Behavioral;
--CODE
| gpl-3.0 | 34b9587258fee2c6b15792d902cdd603 | 0.467477 | 4.456808 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_pkg.vhd | 1 | 5,808 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains necessary types, constants, and functions for the parameterized average
/ calculator design.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.adder_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package average_calculator_pkg is
/* function 1 */
/**************************************************************************************************/
-- function average_calculator_CHECKS()
-- return integer;
function average_calculator_IH(
s : positive;
p : positive;
input_high : integer)
return integer;
function average_calculator_IL(
round_to_bit_opt : integer_exc;
input_low : integer)
return integer;
function average_calculator_OH(
unsigned_2comp_opt : boolean;
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
s : positive;
p : positive;
input_high : integer;
input_low : integer)
return integer;
function average_calculator_OL(
unsigned_2comp_opt : boolean;
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
s : positive;
p : positive;
input_high : integer;
input_low : integer)
return integer;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body average_calculator_pkg is
/********************************************************************************************** 1 */
function average_calculator_IH(
s : positive;
p : positive;
input_high : integer)
return integer is
begin
return adder_OH(integer'low,
s,
p,
input_high);
end function;
function average_calculator_IL(
round_to_bit_opt : integer_exc;
input_low : integer)
return integer is
begin
return adder_OL(round_to_bit_opt,
input_low);
end function;
function average_calculator_OH(
unsigned_2comp_opt : boolean;
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
s : positive;
p : positive;
input_high : integer;
input_low : integer)
return integer is
constant inter_high : integer := average_calculator_IH(s,
p,
input_high);
constant inter_low : integer := average_calculator_IL(round_to_bit_opt,
input_low);
constant constants : real_v(1 to 1) := (1 => 1.0/real(p*s));
begin
return real_const_mult_OH(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
inter_high,
inter_low,
not unsigned_2comp_opt);
end function;
function average_calculator_OL(
unsigned_2comp_opt : boolean;
round_style_opt : T_round_style;
round_to_bit_opt : integer_exc;
max_error_pct_opt : real_exc;
s : positive;
p : positive;
input_high : integer;
input_low : integer)
return integer is
constant inter_high : integer := average_calculator_IH(s,
p,
input_high);
constant inter_low : integer := average_calculator_IL(round_to_bit_opt,
input_low);
constant constants : real_v(1 to 1) := (1 => 1.0/real(p*s));
begin
return real_const_mult_OL(round_style_opt,
round_to_bit_opt,
max_error_pct_opt,
constants,
inter_low,
not unsigned_2comp_opt);
end function;
end package body; | mit | e9c3d4f60bdf4c4ade320b002c52df96 | 0.39089 | 4.981881 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/atari_bak.vhd | 1 | 11,292 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ATARI is
port(
CLK_50 : in std_logic;
KB_CLK : in std_logic;
KB_DAT : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end ATARI;
architecture RTL of ATARI is
-- System
signal CLK : std_logic;
signal PLL_LOCKED : std_logic;
signal RESET_N : std_logic;
-- Video
signal HSYNC : std_logic;
signal VSYNC : std_logic;
-- Audio
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
-- Gamepads
signal GAMEPAD0 : std_logic_vector(7 downto 0);
signal GAMEPAD1 : std_logic_vector(7 downto 0);
signal JOY1_n : std_logic_vector(7 downto 0);
signal JOY2_n : std_logic_vector(7 downto 0);
-- Keyboard
signal KEYBOARD_SCAN : std_logic_vector(5 downto 0);
signal KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
signal CONSOL_START : std_logic;
signal CONSOL_SELECT : std_logic;
signal CONSOL_OPTION : std_logic;
signal FKEYS : std_logic_vector(11 downto 0);
-- PIA
signal CA2_OUT : std_logic;
signal CA2_DIR_OUT : std_logic;
signal CB2_OUT : std_logic;
signal CB2_DIR_OUT : std_logic;
signal CA2_IN : std_logic;
signal CB2_IN : std_logic;
signal PORTA_IN : std_logic_vector(7 downto 0);
signal PORTA_OUT : std_logic_vector(7 downto 0);
signal PORTA_DIR_OUT : std_logic_vector(7 downto 0);
signal PORTB_IN : std_logic_vector(7 downto 0);
signal PORTB_OUT : std_logic_vector(7 downto 0);
-- PBI
signal PBI_WRITE_DATA : std_logic_vector(31 downto 0);
signal PBI_WIDTH_32BIT_ACCESS : std_logic;
signal PBI_WIDTH_16BIT_ACCESS : std_logic;
signal PBI_WIDTH_8BIT_ACCESS : std_logic;
signal GTIA_TRIG : std_logic_vector(3 downto 0);
signal ANTIC_LIGHTPEN : std_logic;
-- INTERNAL ROM/RAM
signal RAM_ADDR : std_logic_vector(18 downto 0);
signal RAM_DO : std_logic_vector(15 downto 0);
signal RAM_REQUEST : std_logic;
signal RAM_REQUEST_COMPLETE : std_logic;
signal RAM_WRITE_ENABLE : std_logic;
signal ROM_ADDR : std_logic_vector(21 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal ROM_REQUEST : std_logic;
signal ROM_REQUEST_COMPLETE : std_logic;
-- DMA/Virtual drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
signal ZPU_OUT2 : std_logic_vector(31 downto 0);
signal ZPU_OUT3 : std_logic_vector(31 downto 0);
signal ZPU_OUT4 : std_logic_vector(31 downto 0);
signal ZPU_POKEY_ENABLE : std_logic;
signal ZPU_SIO_TXD : std_logic;
signal ZPU_SIO_RXD : std_logic;
signal ZPU_SIO_COMMAND : std_logic;
-- System control from ZPU
signal RAM_SELECT : std_logic_vector(2 downto 0);
signal ROM_SELECT : std_logic_vector(5 downto 0);
signal RESET_ATARI : std_logic;
signal PAUSE_ATARI : std_logic;
signal SPEED_6502 : std_logic_vector(5 downto 0);
begin
u_PLL : entity work.PLL
port map (
CLKIN => CLK_50,
CLKOUT => CLK,
LOCKED => PLL_LOCKED );
u_DAC_L : entity work.dac
port map (
clk_i => CLK,
res_n_i => RESET_N,
dac_i => AUDIO_L_PCM,
dac_o => SOUND_L );
u_DAC_R : entity work.dac
port map (
clk_i => CLK,
res_n_i => RESET_N,
dac_i => AUDIO_R_PCM,
dac_o => SOUND_R );
u_KEYBOARD : entity work.ps2_to_atari800
port map (
CLK => CLK,
RESET_N => RESET_N,
PS2_CLK => KB_CLK,
PS2_DAT => KB_DAT,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
FKEYS => FKEYS );
u_JOYSTICKS : entity work.nes_gamepad
port map(
CLK => CLK,
RESET => not RESET_N,
JOY_CLK => JOY_CLK,
JOY_LOAD => JOY_LOAD,
JOY_DATA0 => JOY_DATA0,
JOY_DATA1 => JOY_DATA1,
JOY0_BUTTONS => GAMEPAD0,
JOY1_BUTTONS => GAMEPAD1,
JOY0_CONNECTED => OPEN,
JOY1_CONNECTED => OPEN );
u_INTROMRAM : entity work.internalromram
generic map (
internal_rom => 1,
internal_ram => 16384 )
port map (
clock => CLK,
reset_n => RESET_N,
ROM_ADDR => ROM_ADDR,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
ROM_REQUEST => ROM_REQUEST,
ROM_DATA => ROM_DO,
RAM_ADDR => RAM_ADDR,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_REQUEST => RAM_REQUEST,
RAM_DATA => RAM_DO(7 downto 0) );
u_ATARI800 : entity work.atari800core
generic map (
cycle_length => 16,
video_bits => 4 )
port map (
CLK => CLK,
RESET_N => RESET_N,
VIDEO_VS => VSYNC,
VIDEO_HS => HSYNC,
VIDEO_B => VGA_B,
VIDEO_G => VGA_G,
VIDEO_R => VGA_R,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
CA1_IN => '1',
CB1_IN => '1',
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CA2_DIR_OUT => CA2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
PORTA_IN => PORTA_IN,
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => OPEN,
PORTB_OUT => PORTB_OUT,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => "00000000",
POT_RESET => OPEN,
PBI_ADDR => OPEN,
PBI_WRITE_ENABLE => OPEN,
PBI_SNOOP_DATA => OPEN,
PBI_WRITE_DATA => PBI_WRITE_DATA,
PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
PBI_ROM_DO => "11111111",
PBI_REQUEST => OPEN,
PBI_REQUEST_COMPLETE => '1',
CART_RD4 => '0',
CART_RD5 => '0',
CART_S4_n => OPEN,
CART_S5_N => OPEN,
CART_CCTL_N => OPEN,
SIO_RXD => '0',
SIO_TXD => OPEN,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
GTIA_TRIG => GTIA_TRIG,
ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
SDRAM_REQUEST => OPEN,
SDRAM_REQUEST_COMPLETE => '1',
SDRAM_READ_ENABLE => OPEN,
SDRAM_WRITE_ENABLE => OPEN,
SDRAM_ADDR => OPEN,
SDRAM_DO => (others=>'1'),
ANTIC_REFRESH => OPEN,
RAM_ADDR => RAM_ADDR,
RAM_DO => RAM_DO,
RAM_REQUEST => RAM_REQUEST,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
ROM_ADDR => ROM_ADDR,
ROM_DO => ROM_DO,
ROM_REQUEST => ROM_REQUEST,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
DMA_32BIT_WRITE_ENABLE => '0',
DMA_16BIT_WRITE_ENABLE => '0',
DMA_8BIT_WRITE_ENABLE => '0',
DMA_ADDR => (others=>'1'),
DMA_WRITE_DATA => (others=>'1'),
MEMORY_READY_DMA => OPEN,
PBI_SNOOP_DATA => OPEN,
RAM_SELECT => "000",
ROM_SELECT => "000001",
CART_EMULATION_SELECT => "0000000",
CART_EMULATION_ACTIVATE => '0',
PAL => '1',
USE_SDRAM => '0',
ROM_IN_RAM => '0',
THROTTLE_COUNT_6502 => "000001",
HALT => '0' );
u_ZPU : entity work.zpucore
generic map (
platform => 1,
spi_clock_div => 1 ) -- 28MHz/2. Max for SD cards is 25MHz...
port map (
CLK => CLK,
RESET_N => RESET_N,
ZPU_ADDR_FETCH => dma_addr_fetch,
ZPU_DATA_OUT => dma_write_data,
ZPU_FETCH => dma_fetch,
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
ZPU_READ_ENABLE => dma_read_enable,
ZPU_MEMORY_READY => dma_memory_ready,
ZPU_MEMORY_DATA => dma_memory_data,
ZPU_ADDR_ROM => zpu_addr_rom,
ZPU_ROM_DATA => zpu_rom_data,
ZPU_SD_DAT0 => SD_MISO,
ZPU_SD_CLK => SD_SCK,
ZPU_SD_CMD => SD_MOSI,
ZPU_SD_DAT3 => SD_CS,
ZPU_POKEY_ENABLE => zpu_pokey_enable,
ZPU_SIO_TXD => zpu_sio_txd,
ZPU_SIO_RXD => zpu_sio_rxd,
ZPU_SIO_COMMAND => zpu_sio_command,
ZPU_IN1 => X"00000"& FKEYS,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"00000000",
ZPU_OUT1 => ZPU_OUT1,
ZPU_OUT2 => ZPU_OUT2,
ZPU_OUT3 => ZPU_OUT3,
ZPU_OUT4 => ZPU_OUT4 );
u_ZPUROM : entity work.zpu_rom
port map (
clock => clk,
address => zpu_addr_rom(13 downto 2),
q => zpu_rom_data );
u_ZPU_POKEY : entity work.enable_divider
generic map (
COUNT => 16)
port map(
clk => clk,
reset_n => reset_n,
enable_in => '1',
enable_out => zpu_pokey_enable );
RESET_N <= PLL_LOCKED;
VGA_HSYNC <= not(HSYNC or VSYNC);
VGA_VSYNC <= not(HSYNC or VSYNC);
CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
PORTB_IN <= PORTB_OUT;
PORTA_IN <= ((JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
ANTIC_LIGHTPEN <= JOY2_n(7) and JOY1_n(7);
GTIA_TRIG <= "01"&JOY2_n(7)&JOY1_n(7);
JOY1_n <= not GAMEPAD0; -- FRLDU
JOY2_n <= not GAMEPAD1; -- FRLDU
PAUSE_ATARI <= ZPU_OUT1(0);
RESET_ATARI <= ZPU_OUT1(1);
SPEED_6502 <= ZPU_OUT1(7 downto 2);
RAM_SELECT <= ZPU_OUT1(10 downto 8);
ROM_SELECT <= ZPU_OUT1(16 downto 11);
end RTL;
| gpl-3.0 | 033a951d4fe08d4800c71cdb185397e0 | 0.552604 | 2.985722 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/example_design/mips_vram_exdes.vhd | 1 | 5,405 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY mips_vram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END mips_vram_exdes;
ARCHITECTURE xilinx OF mips_vram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT mips_vram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : mips_vram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-3.0 | 97ad9960af2fa319de7f7ecd0272309e | 0.551156 | 4.572758 | false | false | false | false |
freecores/lq057q3dc02 | design/video_controller.vhd | 1 | 6,709 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: video_controller.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- This file instantiates the components which control HSYNCx, VSYNCx, ENAB,
-- and the CLK_LCD cycle counter.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.components.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY video_controller IS
generic (
--Video Controller
C_RL_STATUS,
C_UD_STATUS,
C_VQ_STATUS : STD_LOGIC;
--VSYNC Controller (pass thru)
C_VSYNC_TV,
C_VSYNC_TVP,
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
--HSYNCx Controller (pass thru)
C_HSYNC_TH,
C_HSYNC_THP,
C_NUM_CLKS_WIDTH,
--CLK_LCD Cycle Counter (pass thru)
C_CLK_LCD_CYC_NUM_WIDTH,
--ENAB Controller (pass thru)
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
port (
RSTx,
CLK_LCD : IN std_logic;
LINE_NUM : OUT std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
HSYNCx,
VSYNCx,
ENAB,
RL,
UD,
VQ : OUT std_logic
);
END ENTITY video_controller;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE video_controller_arch OF video_controller IS
--Connecting wires between components
signal HSYNCx_wire : std_logic := '1';
signal VSYNCx_wire : std_logic := '1';
signal LINE_NUM_wire : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0');
signal CLK_LCD_CYC_NUM_wire : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0');
begin
--///////////////////////--
-- CONCURRENT STATEMENTS --
--///////////////////////--
RL <= C_RL_STATUS;
UD <= C_UD_STATUS;
VQ <= C_VQ_STATUS;
HSYNCx <= HSYNCx_wire;
VSYNCx <= VSYNCx_wire;
LINE_NUM <= LINE_NUM_wire; -- line number required by image generator used at top-level
CLK_LCD_CYC_NUM <= CLK_LCD_CYC_NUM_wire; -- pixel number required by image generator used at top-level
--//////////////////////////--
-- COMPONENT INSTANTIATIONS --
--//////////////////////////--
----------------------
-- HSYNCx Control
----------------------
HSYNCx_C : hsyncx_control
generic map (
C_HSYNC_TH => C_HSYNC_TH,
C_HSYNC_THP => C_HSYNC_THP,
C_NUM_CLKS_WIDTH => C_NUM_CLKS_WIDTH
)
port map (
RSTx => RSTx,
CLK_LCD => CLK_LCD,
--OUTPUTS
HSYNCx => HSYNCx_wire
);
----------------------
-- VSYNCx Control
----------------------
VSYNCx_C : vsyncx_control
generic map (
C_VSYNC_TV => C_VSYNC_TV,
C_VSYNC_TVP => C_VSYNC_TVP,
C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH
)
port map (
RSTx => RSTx,
CLK_LCD => CLK_LCD,
HSYNCx => HSYNCx_wire,
--OUTPUTS
LINE_NUM => LINE_NUM_wire,
VSYNCx => VSYNCx_wire
);
---------------------------
-- CLK_LCD Cycle Counter
---------------------------
CLK_LCD_CYCLE_Cntr : clk_lcd_cyc_cntr
GENERIC MAP (
C_VSYNC_TVS => C_VSYNC_TVS,
C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP => C_ENAB_TEP,
C_ENAB_THE => C_ENAB_THE
)
PORT MAP (
RSTx => RSTx,
CLK_LCD => CLK_LCD,
LINE_NUM => LINE_NUM_wire,
HSYNCx => HSYNCx_wire,
VSYNCx => VSYNCx_wire,
--OUTPUTS
CLK_LCD_CYC_NUM => CLK_LCD_CYC_NUM_wire
);
----------------------
-- ENAB Control
----------------------
ENAB_C : enab_control
generic map (
C_VSYNC_TVS => C_VSYNC_TVS,
C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP => C_ENAB_TEP,
C_ENAB_THE => C_ENAB_THE
)
port map (
RSTx => RSTx,
CLK_LCD => CLK_LCD,
CLK_LCD_CYC_NUM => CLK_LCD_CYC_NUM_wire,
-- OUTPUTS
ENAB => ENAB
);
END ARCHITECTURE video_controller_arch;
| gpl-2.0 | 9a12cc12258a4e2e12a79fcaf5d7f039 | 0.486511 | 3.70663 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/heatersLogicTB.vhd | 1 | 1,831 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY heatersLogicTB IS
END heatersLogicTB;
ARCHITECTURE behavior OF heatersLogicTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT heatersLogic
PORT(
rsDataIn : IN std_logic_vector(7 downto 0);
rsRdy : IN std_logic;
rst : IN std_logic;
clk50Mhz : IN std_logic
);
END COMPONENT;
--Inputs
signal rsDataIn : std_logic_vector(7 downto 0) := (others => '0');
signal rsRdy : std_logic := '0';
signal rst : std_logic := '0';
signal clk50Mhz : std_logic := '0';
-- Clock period definitions
constant clk50Mhz_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: heatersLogic PORT MAP (
rsDataIn => rsDataIn,
rsRdy => rsRdy,
rst => rst,
clk50Mhz => clk50Mhz
);
-- Clock process definitions
clk50Mhz_process :process
begin
clk50Mhz <= '0';
wait for clk50Mhz_period/2;
clk50Mhz <= '1';
wait for clk50Mhz_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk50Mhz_period*10;
rsDataIn <= X"22";
rsRdy <= '1';
wait for clk50Mhz_period;
rsDataIn <= X"00";
rsRdy <= '0';
wait for 3*clk50Mhz_period;
rsDataIn <= X"55";
rsRdy <= '1';
wait for clk50Mhz_period;
rsDataIn <= X"00";
rsRdy <= '0';
wait for 3*clk50Mhz_period;
rsDataIn <= X"01";
rsRdy <= '1';
wait for clk50Mhz_period;
rsDataIn <= X"00";
rsRdy <= '0';
wait for 3*clk50Mhz_period;
rsDataIn <= X"FF";
rsRdy <= '1';
wait for clk50Mhz_period;
rsDataIn <= X"00";
rsRdy <= '0';
wait for 3*clk50Mhz_period;
wait;
end process;
END;
| mit | e958d5820aad1c02ba59ca89798620b2 | 0.589295 | 3.098139 | false | false | false | false |
simpway/HDLC-ICEC | firmware/HDLC_TXRX_WRAPPER.vhd | 1 | 11,541 | --!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
--! Physics Department --
--! Omega Group --
--!-----------------------------------------------------------------------------
--|
--! author: Kai Chen ([email protected])
--!
--!
--!-----------------------------------------------------------------------------
--
-- Create Date: 21:33:01 2015/11/18
-- Design Name:
-- Module Name: HDLC_TXRX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: The MODULE to send data to IC/EC bit, and receive data from
-- IC/EC bit. The data encoding and decoding to/from HDLC shold
-- be done in software. This module only send and receive data
-- to a multi-bytes register. users can change its width.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.pcie_package.all;
use work.FELIX_gbt_package.all;
entity HDLC_TXRX_WRAPPER is
generic (
REG_WIDTH : integer := 256;
GBT_NUM : integer := 24
);
port (
txclk_40m : in std_logic;
rxclk_40m : in std_logic;
ICECBUSY : out std_logic_vector(15 downto 0);
ICEC_INT_RX_DATA : out txrx64b_24ch_type;
register_map_control: in register_map_control_type;
ICEC_RX_4b : in txrx4b_type;
ICEC_TX_4b : out txrx4b_type
);
end HDLC_TXRX_WRAPPER;
architecture behv of HDLC_TXRX_WRAPPER is
type txrx256b_24ch_type is array (23 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
signal rx_ic_reg : txrx256b_24ch_type;
signal tx_ic_reg : txrx256b_24ch_type;
signal rx_ec_reg : txrx256b_24ch_type;
signal tx_ec_reg : txrx256b_24ch_type;
signal ic_trig : std_logic_vector(23 downto 0);
signal ec_trig : std_logic_vector(23 downto 0);
signal IC_RX_REG_BUF : std_logic_vector(REG_WIDTH-1 downto 0);
signal EC_RX_REG_BUF : std_logic_vector(REG_WIDTH-1 downto 0);
signal ic_ch_sel : std_logic_vector(4 downto 0);
signal ec_ch_sel : std_logic_vector(4 downto 0);
signal ICEC_TX_4b_i : txrx4b_type(0 to GBT_NUM-1);
signal ICEC_RX_4b_i : txrx4b_type(0 to GBT_NUM-1);
signal ic_trig_i : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_r : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_2r : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_3r : std_logic_vector(23 downto 0):=x"000000";
signal ic_sel_rx_i : std_logic_vector(23 downto 0):=x"000000";
signal IC_busy_pull : std_logic_vector(23 downto 0):=x"000000";
signal ic_int : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_i : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_r : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_2r : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_3r : std_logic_vector(23 downto 0):=x"000000";
signal EC_busy_pull : std_logic_vector(23 downto 0):=x"000000";
signal ec_int : std_logic_vector(23 downto 0):=x"000000";
signal muxsel : std_logic_vector(23 downto 0);
begin
ic_trig_i(4 downto 0) <= register_map_control.ICEC_TRIG(4 downto 0);
ic_sel_rx_i(4 downto 0) <= register_map_control.ICEC_TRIG(20 downto 16);
ec_trig_i(4 downto 0) <= register_map_control.ICEC_TRIG(12 downto 8);
tx_ec_reg(0) <= register_map_control.EC_TXDATA03 & register_map_control.EC_TXDATA02
& register_map_control.EC_TXDATA01 & register_map_control.EC_TXDATA00;
tx_ec_reg(1) <= register_map_control.EC_TXDATA13 & register_map_control.EC_TXDATA12
& register_map_control.EC_TXDATA11 & register_map_control.EC_TXDATA10;
tx_ec_reg(2) <= register_map_control.EC_TXDATA23 & register_map_control.EC_TXDATA22
& register_map_control.EC_TXDATA21 & register_map_control.EC_TXDATA20;
tx_ec_reg(3) <= register_map_control.EC_TXDATA33 & register_map_control.EC_TXDATA32
& register_map_control.EC_TXDATA31 & register_map_control.EC_TXDATA30;
tx_ec_reg(4) <= register_map_control.EC_TXDATA43 & register_map_control.EC_TXDATA42
& register_map_control.EC_TXDATA41 & register_map_control.EC_TXDATA40;
ch_gen : for i in GBT_NUM-1 downto 0 generate
tx_ic_reg(i) <= register_map_control.IC_TXDATA03 & register_map_control.IC_TXDATA02
& register_map_control.IC_TXDATA01 & register_map_control.IC_TXDATA00;
process (txclk_40m)
begin
if txclk_40m'event and txclk_40m='1' then
ic_trig_r(i) <= ic_trig_i(i);
ic_trig_2r(i) <= ic_trig_r(i);
ic_trig_3r(i) <= ic_trig_2r(i);
IC_busy_pull(i) <= ic_trig_r(i) and (not ic_trig_3r(i));
ic_trig(i) <= ic_trig_r(i) and (not ic_trig_2r(i));
ec_trig_r(i) <= ec_trig_i(i);
ec_trig_2r(i) <= ec_trig_r(i);
ec_trig_3r(i) <= ec_trig_2r(i);
EC_busy_pull(i) <= ec_trig_r(i) and (not ec_trig_3r(i));
ec_trig(i) <= ec_trig_r(i) and (not ec_trig_2r(i));
end if;
end process;
process(rxclk_40m)
begin
if rxclk_40m'event and rxclk_40m='1' then
if ic_busy_pull(i) = '1' then
ICECBUSY(i) <= '1';
elsif ic_int(i)='1' then
ICECBUSY(i) <= '0';
end if;
if ec_busy_pull(i)= '1' then
ICECBUSY(i+8) <= '1';
elsif ec_int(i)='1' then
ICECBUSY(i+8) <= '0';
end if;
end if;
end process;
end generate;
ICEC_INT_RX_DATA(3) <= IC_RX_REG_BUF(255 downto 192);
ICEC_INT_RX_DATA(2) <= IC_RX_REG_BUF(191 downto 128);
ICEC_INT_RX_DATA(1) <= IC_RX_REG_BUF(127 downto 64);
ICEC_INT_RX_DATA(0) <= IC_RX_REG_BUF(63 downto 0);
ICEC_INT_RX_DATA(7) <= rx_ec_reg(0)(255 downto 192);
ICEC_INT_RX_DATA(6) <= rx_ec_reg(0)(191 downto 128);
ICEC_INT_RX_DATA(5) <= rx_ec_reg(0)(127 downto 64);
ICEC_INT_RX_DATA(4) <= rx_ec_reg(0)(63 downto 0);
ICEC_INT_RX_DATA(11) <= rx_ec_reg(1)(255 downto 192);
ICEC_INT_RX_DATA(10) <= rx_ec_reg(1)(191 downto 128);
ICEC_INT_RX_DATA(9) <= rx_ec_reg(1)(127 downto 64);
ICEC_INT_RX_DATA(8) <= rx_ec_reg(1)(63 downto 0);
ICEC_INT_RX_DATA(15) <= rx_ec_reg(2)(255 downto 192);
ICEC_INT_RX_DATA(14) <= rx_ec_reg(2)(191 downto 128);
ICEC_INT_RX_DATA(13) <= rx_ec_reg(2)(127 downto 64);
ICEC_INT_RX_DATA(12) <= rx_ec_reg(2)(63 downto 0);
ICEC_INT_RX_DATA(19) <= rx_ec_reg(3)(255 downto 192);
ICEC_INT_RX_DATA(18) <= rx_ec_reg(3)(191 downto 128);
ICEC_INT_RX_DATA(17) <= rx_ec_reg(3)(127 downto 64);
ICEC_INT_RX_DATA(16) <= rx_ec_reg(3)(63 downto 0);
ICEC_INT_RX_DATA(23) <= rx_ec_reg(4)(255 downto 192);
ICEC_INT_RX_DATA(22) <= rx_ec_reg(4)(191 downto 128);
ICEC_INT_RX_DATA(21) <= rx_ec_reg(4)(127 downto 64);
ICEC_INT_RX_DATA(20) <= rx_ec_reg(4)(63 downto 0);
IC_RX_REG_BUF <= rx_ic_reg(0) when ic_sel_rx_i(0) = '1' else
rx_ic_reg(1) when ic_sel_rx_i(1) = '1' else
rx_ic_reg(2) when ic_sel_rx_i(2) = '1' else
rx_ic_reg(3) when ic_sel_rx_i(3) = '1' else
rx_ic_reg(4) when ic_sel_rx_i(4) = '1' else
IC_RX_REG_BUF;
-- EC_RX_REG_BUF <= rx_ec_reg(0) when ec_ch_sel = "00000" else
-- rx_ec_reg(1) when ec_ch_sel = "00001" else
-- rx_ec_reg(2) when ec_ch_sel = "00010" else
-- rx_ec_reg(3) when ec_ch_sel = "00011" else
-- rx_ec_reg(4) when ec_ch_sel = "00100" else
-- rx_ec_reg(5) when ec_ch_sel = "00101" else
-- rx_ec_reg(6) when ec_ch_sel = "00110" else
-- rx_ec_reg(7) when ec_ch_sel = "00111" else
-- rx_ec_reg(8) when ec_ch_sel = "01000" else
-- rx_ec_reg(9) when ec_ch_sel = "01001" else
-- rx_ec_reg(10) when ec_ch_sel = "01010" else
-- rx_ec_reg(11) when ec_ch_sel = "01011" else
-- rx_ec_reg(12) when ec_ch_sel = "01100" else
-- rx_ec_reg(13) when ec_ch_sel = "01101" else
-- rx_ec_reg(14) when ec_ch_sel = "01110" else
-- rx_ec_reg(15) when ec_ch_sel = "01111" else
-- rx_ec_reg(16) when ec_ch_sel = "10000" else
-- rx_ec_reg(17) when ec_ch_sel = "10001" else
-- rx_ec_reg(18) when ec_ch_sel = "10010" else
-- rx_ec_reg(19) when ec_ch_sel = "10011" else
-- rx_ec_reg(20) when ec_ch_sel = "10100" else
-- rx_ec_reg(21) when ec_ch_sel = "10101" else
-- rx_ec_reg(22) when ec_ch_sel = "10110" else
-- rx_ec_reg(23) when ec_ch_sel = "10111" else
-- rx_ec_reg(0);
ICEC_HDLC_TXRX_GEN : for i in GBT_NUM-1 downto 0 generate
IC_HDLC_TXRX_inst : entity work.HDLC_TXRX
generic map(
REG_WIDTH => REG_WIDTH
)
port map(
rx_long_data_reg_o => rx_ic_reg(i),
tx_long_data_reg_i => tx_ic_reg(i),
tx_trig_i => ic_trig(i), --one tx40m cycle
rx_trig_o => ic_int(i), --one rx40m cycle
txclk_40m => txclk_40m,
rxclk_40m => rxclk_40m,
IC_RX_2b => ICEC_RX_4b(i)(3 downto 2),
IC_TX_2b => ICEC_TX_4b(i)(3 downto 2)
);
EC_HDLC_TXRX_inst : entity work.HDLC_TXRX
generic map(
REG_WIDTH => 256
)
port map(
rx_long_data_reg_o => rx_ec_reg(i),
tx_long_data_reg_i => tx_ec_reg(i),
tx_trig_i => ec_trig(i), --one tx40m cycle
rx_trig_o => ec_int(i), --one rx40m cycle
txclk_40m => txclk_40m,
rxclk_40m => rxclk_40m,
IC_RX_2b => ICEC_RX_4b_i(i)(1 downto 0),
IC_TX_2b => ICEC_TX_4b_i(i)(1 downto 0)
);
process(rxclk_40m)
begin
if rxclk_40m'event and rxclk_40m='1' then
--if muxsel(i)='0' then
ICEC_RX_4b_i(i)(1) <= ICEC_RX_4b(i)(0);
ICEC_RX_4b_i(i)(0) <= ICEC_RX_4b(i)(1);
--else
-- ICEC_RX_4b_i(i)(0) <= ICEC_RX_4b(i)(0);
--ICEC_RX_4b_i(i)(1) <= ICEC_RX_4b(i)(1);
--end if;
end if;
end process;
ICEC_TX_4b(i)(0) <= ICEC_TX_4b_i(i)(1);
ICEC_TX_4b(i)(1) <= ICEC_TX_4b_i(i)(0);
end generate;
end behv;
| gpl-3.0 | e2d6541aa96a03c14706c80f9ab6b37a | 0.503683 | 2.96379 | false | false | false | false |
APastorG/APG | permutation/perm_sp_core.vhd | 1 | 8,047 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.counter_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity perm_sp_core is
generic(
dimensions : positive;
p_dimensions : positive;
serial_dim : natural;
parallel_dim : natural;
left_ps_latency : natural;
right_ps_latency : natural;
input_high : natural;
input_low : natural
);
port(
clk : in std_ulogic;
start : in std_ulogic;
input : in sulv_v;
finish : out std_ulogic;
output : out sulv_v(input_high downto input_low)
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture perm_sp_core_1 of perm_sp_core is
--parallel dimensions
constant P : natural := p_dimensions;
--serial dimensions
constant S : natural := dimensions - P;
constant LATENCY : positive := integer((2.0**serial_dim)/(2.0**P));
--latencies after removing delays whenever there are 2 consecutive sp permutations
constant LATENCY_0 : natural := LATENCY - minimum(right_ps_latency, LATENCY);
constant LATENCY_1 : natural := LATENCY - minimum(left_ps_latency, LATENCY);
constant common_LATENCY : natural := LATENCY_0;
signal count_is_not_zero : std_ulogic;
signal counter_out : std_ulogic;
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
(2 ** S)- 1, --TARGET_dep,
true, --TARGET_WITH_COUNT_opt = t_true,
false, --USE_SET,
1) - 1 --SET_TO_dep)
downto 0); --only the serial indexes (N downto P) mapped to downto 0
signal control : std_ulogic;
signal start_delayed : std_ulogic_vector(0 to common_LATENCY);
/*================================================================================================*/
/*================================================================================================*/
begin
count_is_not_zero <= '1' when to_integer(unsigned(count)) /= 0 else
'0';
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_wrap,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => (2 ** S)- 1,
TARGET_WITH_COUNT_opt => t_true,
TARGET_BLOCKING_opt => t_false,
USE_SET => false,
--SET_TO_dep => ,
USE_RESET => true,
--SET_RESET_PRIORITY_opt => ,
USE_LOAD => false
)
port map(
clk => clk,
enable => count_is_not_zero or start_delayed(0),
--set => ,
reset => counter_out,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count,
count_is_TARGET(1) => counter_out
);
control <= count(serial_dim - P);
generate_serial_parallel_permutation:
for i in 1 to 2**(P-1) generate
constant index0 : natural := calculate_indexes(integer(i-1), P, parallel_dim, 0);
constant index1 : natural := calculate_indexes(integer(i-1), P, parallel_dim, 1);
signal in0, in1 : std_ulogic_vector(input(input'left)'range);
signal inter0 : sulv_v(0 to LATENCY_0-1)(input(input'left)'range);
signal inter1 : sulv_v(0 to LATENCY_1-1)(input(input'left)'range);
begin
in0 <= input(index0);
in1 <= input(index1);
more_than_one_register_in_0:
if LATENCY_0 > 0 generate
begin
process (clk) is
begin
if rising_edge(clk) then
if LATENCY_1 > 0 then
inter0(0) <= in0 when control='0' else
inter1(LATENCY_1 - 1);
inter1(0) <= in1;
if LATENCY_1 > 1 then
inter1(1 to LATENCY_1 - 1) <= inter1(0 to LATENCY_1 - 2);
end if;
end if;
if LATENCY_0 > 1 then
inter0(1 to LATENCY_0 - 1) <= inter0(0 to LATENCY_0 - 2);
end if;
end if;
end process;
output(index0) <= inter0(LATENCY_0 - 1);
latency_1_is_not_zero:
if LATENCY_1 > 0 generate
begin
output(index1) <= inter1(LATENCY_1 - 1) when control = '0' else
in0;
end;
else generate
begin
output(index1) <= in1 when control='0' else
in0;
end;
end generate;
end;
else generate
begin
more_than_one_register_in_1:
if LATENCY_1 > 0 generate
begin
process (clk) is
begin
if rising_edge(clk) then
inter1(0) <= in1;
inter1(1 to LATENCY_1 - 1) <= inter1(0 to LATENCY_1 - 2);
end if;
end process;
output(index1) <= inter1(LATENCY_1 - 1) when control = '0' else
in0;
output(index0) <= in0 when control='0' else
inter1(LATENCY_1 - 1);
end;
else generate
begin
output(index1) <= in1 when control='0' else
in0;
output(index0) <= in0 when control='0' else
in1;
end;
end generate;
end;
end generate;
end;
end generate;
finish <= start_delayed(common_LATENCY);
start_delayed(0) <= start;
process (clk) is
begin
if rising_edge(clk) then
if common_LATENCY > 0 then
start_delayed(1 to common_LATENCY) <= start_delayed(0 to common_LATENCY-1);
end if;
end if;
end process;
end architecture; | mit | f8214f76b4f6af84b89791c7ab33892f | 0.398477 | 4.680491 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/PulseTimer.vhd | 1 | 1,491 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:10:19 03/15/2015
-- Design Name:
-- Module Name: PulseTimer - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PulseTimer is
port(
clk : in std_logic;
enable : in std_logic;
start : in std_logic;
match : in std_logic_vector(7 downto 0);
pulse : out std_logic := '0'
);
end PulseTimer;
architecture RTL of PulseTimer is
signal counter : std_logic_vector(7 downto 0) := (others => '0');
signal enabled : boolean := false;
signal match_cache : std_logic_vector(7 downto 0);
begin
process(clk, enable, start, match) begin
if (start = '1' and enable = '1') then
enabled <= true;
elsif rising_edge(clk) then
if (enabled) then
if (counter = "00000000") then
match_cache <= match;
counter <= counter + 1;
elsif (counter = match_cache) then
pulse <= '0';
enabled <= false;
counter <= (others => '0');
else
pulse <= '1';
counter <= counter + 1;
end if;
else
pulse <= '0';
counter <= (others => '0');
end if;
end if;
end process;
end RTL;
| bsd-3-clause | 780d03b84a371a915c71ac71d3b51990 | 0.545272 | 3.313333 | false | false | false | false |
APastorG/APG | permutation/permutation_s.vhd | 1 | 4,168 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
entity permutation_s is
generic (
INPUT_INDEXES : integer_v := (0 => 0); --default
OUTPUT_INDEXES : integer_v --compulsory
);
port(
Clk : in std_ulogic;
input : in u_sfixed_v;
start : in std_ulogic;
output : out u_sfixed_v;
finish : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
architecture permutation_s_1 of permutation_s is
function corrected_input_indexes
return integer_v is
variable result : integer_v(0 to OUTPUT_INDEXES'length-1);
begin
if INPUT_INDEXES'length = 1 and INPUT_INDEXES(0) = 0 then
for i in 0 to INPUT_INDEXES'length-1 loop
result(i) := OUTPUT_INDEXES'length - 1 - i;
end loop;
return result;
else
return INPUT_INDEXES;
end if;
end function;
constant INPUT_INDEXES_corrected : integer_v := corrected_input_indexes;
--normal order for the second dimension is descending
signal corrected_input_d : sulv_v(input'range)(input'element'length-1 downto 0);
signal corrected_output_d : sulv_v(input'range)(input'element'length-1 downto 0);
signal corrected_input_a : sulv_v(input'range)(0 to input'element'length-1);
signal corrected_output_a : sulv_v(input'range)(0 to input'element'length-1);
constant asc : boolean := input'ascending;
/*================================================================================================*/
/*================================================================================================*/
begin
ascending_or_descending:
if asc generate
signal i : integer;
begin
generate_corrected_signals_a:
for i in input'range generate
begin
corrected_input_a(i) <= to_sulv(input(input'high-i+input'low));
output(input'high-i+input'low) <= to_sfixed(corrected_output_a(i), input(i));
end;
end generate;
end;
else generate
signal i : integer;
begin
generate_corrected_signals_d:
for i in input'range generate
begin
corrected_input_d(i) <= to_sulv(input(i));
output(i) <= to_sfixed(corrected_output_d(i), input(i));
end;
end generate;
end;
end generate;
ascending_or_descending_core:
if asc generate
permutation_core_a:
entity work.permutation_core
generic map(
INPUT_INDEXES => INPUT_INDEXES_corrected,
OUTPUT_INDEXES => OUTPUT_INDEXES,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => corrected_input_a,
start => start,
output => corrected_output_a,
finish => finish
);
else generate
permutation_core_d:
entity work.permutation_core
generic map(
INPUT_INDEXES => INPUT_INDEXES_corrected,
OUTPUT_INDEXES => OUTPUT_INDEXES,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => corrected_input_d,
start => start,
output => corrected_output_d,
finish => finish
);
end generate;
end architecture;
| mit | c707230ec400dc83a30fa834db9e623c | 0.478647 | 4.486545 | false | false | false | false |
APastorG/APG | int_const_mult/int_const_mult_u.vhd | 1 | 3,404 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an int_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_u is
generic(
SPEED_opt : T_speed := t_min; --exception: value not set
MULTIPLICANDS : integer_v --compulsory
);
port(
input : in u_ufixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_u1 of int_const_mult_u is
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(MULTIPLICANDS);
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_u2:
entity work.real_const_mult_core_u
generic map(
--SPEED_opt => SPEED_opt,
--ROUND_STYLE_opt => ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_real,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | f8d7aba80cebc1a835cf83442cb15a31 | 0.412463 | 4.547908 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04500_bad.vhd | 1 | 3,893 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-- V1.1: 2018-09-20 : Florent Manni (CNES) : updated to trigger simulation mistake in Modelsim
-------------------------------------------------------------------------------------------------
-- File name : STD_04500_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Clock reassignment: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_04500_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
-- D Flip-flop 3 stages pipeline
-- D Flip-Flop A
i_DA : in std_logic; -- Input signal
o_QA : out std_logic; -- Output signal
-- D Flip-flop B
o_QB : out std_logic; -- Output signal
-- D Flip-Flop C
o_QC : out std_logic -- Output signal
);
end STD_04500_bad;
architecture Behavioral of STD_04500_bad is
signal ClockA : std_logic; -- Clock input for A Flip-Flop
signal ClockB : std_logic; -- Clock input for B Flip-Flop
signal ClockC : std_logic; -- Clock input for C Flip-Flop
signal QA : std_logic;
signal QB : std_logic;
begin
ClockC <= ClockB;
ClockB <= ClockA;
ClockA <= i_Clock;
-- First Flip-Flop
P_FlipFlopA : process(ClockA, i_Reset_n)
begin
if (i_Reset_n = '0') then
QA <= '0';
elsif (rising_edge(ClockA)) then
QA <= i_DA;
end if;
end process;
-- Second Flip-Flop
P_FlipFlopB: process(ClockB, i_Reset_n)
begin
if (i_Reset_n = '0') then
QB <= '0';
elsif (rising_edge(ClockB)) then
QB <= QA;
end if;
end process;
-- Third Flip-Flop
P_FlipFlopC: process(ClockC, i_Reset_n)
begin
if (i_Reset_n = '0') then
o_QC <= '0';
elsif (rising_edge(ClockC)) then
o_QC <= QB;
end if;
end process;
o_QA <= QA;
o_QB <= QB;
end Behavioral;
--CODE
| gpl-3.0 | c0af768a6bc409b0279a37c8f7e32a18 | 0.493707 | 4.181525 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06600_bad.vhd | 1 | 3,438 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06600_bad.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Dimension of comparison elements: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06600_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06600_bad;
--CODE
architecture Behavioral of STD_06600_bad is
signal Count : signed(7 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
| gpl-3.0 | d787d6f22eb7040dda76976df0cd6492 | 0.509308 | 4.523684 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/zpu_config_regs.vhdl | 1 | 10,575 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY zpu_config_regs IS
GENERIC
(
platform : integer := 1; -- So ROM can detect which type of system...
spi_clock_div : integer := 4 -- Quite conservative by default - probably want to use 1 with 28MHz input clock, 2 for 57MHz input clock, 4 for 114MHz input clock etc
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
POKEY_ENABLE : in std_logic;
ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
WR_EN : IN STD_LOGIC;
-- GENERIC INPUT REGS (need to synchronize upstream...)
IN1 : in std_logic_vector(31 downto 0);
IN2 : in std_logic_vector(31 downto 0);
IN3 : in std_logic_vector(31 downto 0);
IN4 : in std_logic_vector(31 downto 0);
-- GENERIC OUTPUT REGS
OUT1 : out std_logic_vector(31 downto 0);
OUT2 : out std_logic_vector(31 downto 0);
OUT3 : out std_logic_vector(31 downto 0);
OUT4 : out std_logic_vector(31 downto 0);
-- SDCARD
SDCARD_CLK : out std_logic;
SDCARD_CMD : out std_logic;
SDCARD_DAT : in std_logic;
SDCARD_DAT3 : out std_logic;
-- SD DMA
sd_addr : out std_logic_vector(15 downto 0);
sd_data : out std_logic_vector(7 downto 0);
sd_write : out std_logic;
-- ATARI interface (in future we can also turbo load by directly hitting memory...)
SIO_DATA_IN : out std_logic;
SIO_COMMAND : in std_logic;
SIO_DATA_OUT : in std_logic;
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
PAUSE_ZPU : out std_logic
);
END zpu_config_regs;
ARCHITECTURE vhdl OF zpu_config_regs IS
function vectorize(s: std_logic) return std_logic_vector is
variable v: std_logic_vector(0 downto 0);
begin
v(0) := s;
return v;
end;
signal addr_decoded : std_logic_vector(15 downto 0);
signal out1_next : std_logic_vector(31 downto 0);
signal out1_reg : std_logic_vector(31 downto 0);
signal out2_next : std_logic_vector(31 downto 0);
signal out2_reg : std_logic_vector(31 downto 0);
signal out3_next : std_logic_vector(31 downto 0);
signal out3_reg : std_logic_vector(31 downto 0);
signal out4_next : std_logic_vector(31 downto 0);
signal out4_reg : std_logic_vector(31 downto 0);
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_busy : std_logic;
signal spi_enable : std_logic;
signal spi_chip_select : std_logic_vector(0 downto 0);
signal spi_clk_out : std_logic;
signal spi_tx_data : std_logic_vector(7 downto 0);
signal spi_rx_data : std_logic_vector(7 downto 0);
signal spi_addr_next : std_logic;
signal spi_addr_reg : std_logic;
signal spi_addr_reg_integer : integer;
signal spi_speed_next : std_logic_vector(7 downto 0);
signal spi_speed_reg : std_logic_vector(7 downto 0);
signal spi_speed_reg_integer : integer;
signal pokey_data_out : std_logic_vector(7 downto 0);
signal wr_en_pokey : std_logic;
signal pause_next : std_logic_vector(31 downto 0);
signal pause_reg : std_logic_vector(31 downto 0);
signal paused_next : std_logic;
signal paused_reg : std_logic;
signal spi_dma_addr_next : std_logic_vector(15 downto 0);
signal spi_dma_addrend_next : std_logic_vector(15 downto 0);
signal spi_dma_wr : std_logic;
signal spi_dma_next : std_logic;
signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
signal spi_dma_reg : std_logic;
begin
-- register
process(clk,reset_n)
begin
if (reset_n='0') then
out1_reg <= (others=>'0');
out2_reg <= (others=>'0');
out3_reg <= (others=>'0');
out4_reg <= (others=>'0');
spi_addr_reg <= '1';
spi_speed_reg <= X"80";
pause_reg <= (others=>'0');
paused_reg <= '0';
spi_dma_addr_reg <= (others=>'0');
spi_dma_addrend_reg <= (others=>'0');
spi_dma_reg <= '0';
elsif (clk'event and clk='1') then
out1_reg <= out1_next;
out2_reg <= out2_next;
out3_reg <= out3_next;
out4_reg <= out4_next;
spi_addr_reg <= spi_addr_next;
spi_speed_reg <= spi_speed_next;
pause_reg <= pause_next;
paused_reg <= paused_next;
spi_dma_addr_reg <= spi_dma_addr_next;
spi_dma_addrend_reg <= spi_dma_addrend_next;
spi_dma_reg <= spi_dma_next;
end if;
end process;
-- decode address
decode_addr1 : entity work.complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
-- spi - for sd card access without bit banging...
-- 200KHz to start with - probably fine for 8-bit, can up it later after init
spi_master1 : entity work.spi_master
generic map(slaves=>1,d_width=>8)
port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
rx_data=>spi_rx_data,busy=>spi_busy);
-- spi-programming model:
-- reg for write/read
-- data (send/receive)
-- busy
-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
-- chip select
-- uart - another Pokey! Running at atari frequency.
wr_en_pokey <= addr(4) and wr_en;
pokey1 : entity work.pokey
port map (clk=>clk,ENABLE_179=>pokey_enable,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>wr_en_pokey,
reset_n=>reset_n,keyboard_response=>"11",pot_in=>X"00",
sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
data_out=>pokey_data_out,
sio_out1=>sio_data_in);
-- hardware regs for ZPU
--
-- 0-3: GENERIC INPUT (RO)
-- 4-7: GENERIC OUTPUT (R/W)
-- 8: PAUSE
-- 9: SPI_DATA
-- SPI_DATA (DONE)
-- W - write data (starts transmission)
-- R - read data (wait for complete first)
-- 10: SPI_STATE
-- SPI_STATE/SPI_CTRL (DONE)
-- R: 0=busy
-- W: 0=select_n, speed
-- 11: SIO
-- SIO
-- R: 0=CMD
-- 12: TYPE
-- FPGA board (DONE)
-- R(32 bits) 0=DE1
-- 13 : SPI_DMA
-- W(15 downto 0 = addr),(31 downto 16 = endAddr)
-- 16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
-- Writes to registers
process(cpu_data_in,wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, pause_reg, pokey_enable, spi_dma_addr_reg, spi_dma_addrend_reg, spi_dma_reg, spi_busy, spi_dma_addr_next)
begin
spi_speed_next <= spi_speed_reg;
spi_addr_next <= spi_addr_reg;
spi_tx_data <= (others=>'0');
spi_enable <= '0';
out1_next <= out1_reg;
out2_next <= out2_reg;
out3_next <= out3_reg;
out4_next <= out4_reg;
paused_next <= '0';
pause_next <= pause_reg;
if (not(pause_reg = X"00000000")) then
if (POKEY_ENABLE='1') then
pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
end if;
paused_next <= '1';
end if;
spi_dma_addr_next <= spi_dma_addr_reg;
spi_dma_addrend_next <= spi_dma_addrend_reg;
spi_dma_wr <= '0';
spi_dma_next <= spi_dma_reg;
if (spi_dma_reg = '1') then
paused_next <= '1';
if (spi_busy = '0') then
spi_dma_wr <= '1';
spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+1);
spi_dma_next <= '0';
if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then
spi_tx_data <= X"ff";
spi_enable <= '1';
spi_dma_next <= '1';
end if;
end if;
end if;
if (wr_en = '1' and addr(4) = '0') then
if(addr_decoded(4) = '1') then
out1_next <= cpu_data_in;
end if;
if(addr_decoded(5) = '1') then
out2_next <= cpu_data_in;
end if;
if(addr_decoded(6) = '1') then
out3_next <= cpu_data_in;
end if;
if(addr_decoded(7) = '1') then
out4_next <= cpu_data_in;
end if;
if(addr_decoded(8) = '1') then
pause_next <= cpu_data_in;
paused_next <= '1';
end if;
if(addr_decoded(9) = '1') then
-- TODO, check overrun?
spi_tx_data <= cpu_data_in(7 downto 0);
spi_enable <= '1';
end if;
if(addr_decoded(10) = '1') then
spi_addr_next <= cpu_data_in(0);
if (cpu_data_in(1) = '1') then
spi_speed_next <= X"80"; -- slow, for init
else
spi_speed_next <= std_logic_vector(to_unsigned(spi_clock_div,8)); -- turbo - up to 25MHz for SD, 20MHz for MMC I believe... If 1 then clock is half input, if 2 then clock is 1/4 input etc.
end if;
end if;
if(addr_decoded(13) = '1') then
paused_next <= '1';
spi_dma_addr_next <= cpu_data_in(15 downto 0);
spi_dma_addrend_next <= cpu_data_in(31 downto 16);
spi_dma_next <= '1';
spi_tx_data <= X"ff";
spi_enable <= '1';
end if;
end if;
end process;
-- Read from registers
process(addr,addr_decoded, in1, in2, in3, in4, out1_reg, out2_reg, out3_reg, out4_reg, SIO_COMMAND, spi_rx_data, spi_busy, pokey_data_out)
begin
data_out <= (others=>'0');
if (addr(4) = '0') then
if (addr_decoded(0) = '1') then
data_out <= in1;
end if;
if (addr_decoded(1) = '1') then
data_out <= in2;
end if;
if (addr_decoded(2) = '1') then
data_out <= in3;
end if;
if (addr_decoded(3) = '1') then
data_out <= in4;
end if;
if (addr_decoded(4) = '1') then
data_out <= out1_reg;
end if;
if (addr_decoded(5) = '1') then
data_out <= out2_reg;
end if;
if (addr_decoded(6) = '1') then
data_out <= out3_reg;
end if;
if (addr_decoded(7) = '1') then
data_out <= out4_reg;
end if;
if (addr_decoded(9) = '1') then
data_out(7 downto 0) <= spi_rx_data;
end if;
if (addr_decoded(10) = '1') then
data_out(0) <= spi_busy;
end if;
if(addr_decoded(11) = '1') then
data_out(0) <= SIO_COMMAND;
end if;
if (addr_decoded(12) = '1') then
data_out <= std_logic_vector(to_unsigned(platform,32));
end if;
else
data_out(7 downto 0) <= pokey_data_out;
end if;
end process;
-- outputs
PAUSE_ZPU <= paused_reg;
out1 <= out1_reg;
out2 <= out2_reg;
out3 <= out3_reg;
out4 <= out4_reg;
SDCARD_CLK <= spi_clk_out;
SDCARD_CMD <= spi_mosi;
spi_miso <= SDCARD_DAT; -- INPUT!! XXX
SDCARD_DAT3 <= spi_chip_select(0);
sd_addr <= spi_dma_addr_reg;
sd_data <= spi_rx_data;
sd_write <= spi_dma_wr;
end vhdl;
| gpl-3.0 | a021884282f0d6ab2d72b7aeca83b521 | 0.617872 | 2.654367 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03000_bad.vhd | 1 | 2,854 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03000_bad.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Comments for objects declaration statements: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03000_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03000_bad;
--CODE
architecture Behavioral of STD_03000_bad is
signal Q : std_logic;
begin
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable = '1') then
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
| gpl-3.0 | f12a0c9dfd33ed3e0e2f2c5e4d46a2b4 | 0.471969 | 4.544586 | false | false | false | false |
APastorG/APG | int_const_mult/int_const_mult.vhd | 1 | 3,216 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an int_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MULTIPLICANDS : integer_v --compulsory
);
port(
input : in std_ulogic_vector;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out sulv_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult1 of int_const_mult is
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(MULTIPLICANDS);
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult2:
entity work.real_const_mult
generic map(
SPEED_opt => SPEED_opt,
--ROUND_STYLE_opt => ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => MULTIPLICANDS_real
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | 0b68171b23da1a9a5af254408da6faa0 | 0.400063 | 4.763473 | false | false | false | false |
APastorG/APG | permutation/permutation.vhd | 1 | 2,295 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
entity permutation is
generic (
INPUT_INDEXES : integer_v := (0 => 0); --default
OUTPUT_INDEXES : integer_v --compulsory
);
port(
Clk : in std_ulogic;
input : in sulv_v;
start : in std_ulogic;
output : out sulv_v;
finish : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
architecture permutation_1 of permutation is
function corrected_input_indexes
return integer_v is
variable result : integer_v(0 to OUTPUT_INDEXES'length-1);
begin
if INPUT_INDEXES'length = 1 and INPUT_INDEXES(0) = 0 then
for i in 0 to INPUT_INDEXES'length-1 loop
result(i) := OUTPUT_INDEXES'length - 1 - i;
end loop;
return result;
else
return INPUT_INDEXES;
end if;
end function;
constant INPUT_INDEXES_corrected : integer_v := corrected_input_indexes;
/*================================================================================================*/
/*================================================================================================*/
begin
permutation_core:
entity work.permutation_core
generic map(
INPUT_INDEXES => INPUT_INDEXES_corrected,
OUTPUT_INDEXES => OUTPUT_INDEXES,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input,
start => start,
output => output,
finish => finish
);
end architecture;
| mit | 3b698fc1fd7696f69486e35f66bb3021 | 0.419172 | 4.841772 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/cpu_6510.vhd | 1 | 3,780 | -- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- 6510 wrapper for 65xx core
-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu_6510 is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean;
emulate_bitfade : boolean
);
port (
clk : in std_logic;
ena_1khz : in std_logic := '0';
enable : in std_logic;
halt : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
we : out std_logic;
a : out unsigned(15 downto 0);
d : in unsigned(7 downto 0);
q : out unsigned(7 downto 0);
diIO : in unsigned(7 downto 0);
doIO : out unsigned(7 downto 0);
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0);
debug_flags : out unsigned(7 downto 0);
debug_io : out unsigned(7 downto 0)
);
end cpu_6510;
-- -----------------------------------------------------------------------
architecture rtl of cpu_6510 is
signal localA : unsigned(15 downto 0);
signal localD : unsigned(7 downto 0);
signal localQ : unsigned(7 downto 0);
signal localWe : std_logic;
signal currentIO : unsigned(7 downto 0);
signal ioDir : unsigned(7 downto 0);
signal ioData : unsigned(7 downto 0);
signal accessIO : std_logic;
signal ioFade : unsigned(7 downto 0) := (others => '0');
begin
cpuInstance: entity work.cpu_65xx
generic map (
pipelineOpcode => pipelineOpcode,
pipelineAluMux => pipelineAluMux,
pipelineAluOut => pipelineAluOut
)
port map (
clk => clk,
enable => enable,
halt => halt,
reset => reset,
nmi_n => nmi_n,
irq_n => irq_n,
d => localD,
q => localQ,
addr => localA,
we => localWe,
debugOpcode => debugOpcode,
debugPc => debugPc,
debugA => debugA,
debugX => debugX,
debugY => debugY,
debugS => debugS,
debug_flags => debug_flags
);
process(localA)
begin
accessIO <= '0';
if localA(15 downto 1) = 0 then
accessIO <= '1';
end if;
end process;
process(d, localA, ioDir, currentIO, accessIO)
begin
localD <= d;
if accessIO = '1' then
if localA(0) = '0' then
localD <= ioDir;
else
localD <= currentIO;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if accessIO = '1' then
if localWe = '1'
and enable = '1' then
if localA(0) = '0' then
ioDir <= localQ;
else
ioData <= localQ;
end if;
end if;
end if;
if reset = '1' then
ioDir <= (others => '0');
end if;
end if;
end process;
process(ioDir, ioData, diIO)
begin
for i in 0 to 7 loop
if ioDir(i) = '0' then
currentIO(i) <= diIO(i);
else
currentIO(i) <= ioData(i);
end if;
end loop;
if emulate_bitfade then
currentIO(7) <= ioFade(7);
currentIO(6) <= ioFade(6);
currentIO(3) <= ioFade(3);
end if;
end process;
-- Cunnect zee wires
a <= localA;
q <= localQ;
we <= localWe;
doIO <= currentIO;
debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
end architecture;
| gpl-3.0 | 982d22ead556cb5e509dd3550bc37cf8 | 0.547884 | 3.118812 | false | false | false | false |
sonologic/gmzpu | vhdl/zpu_small.vhdl | 1 | 22,984 | ------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded
signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(OPCODE_W-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode := to_01( b_i(31 downto 24));
when 1 =>
topcode := to_01( b_i(23 downto 16));
when 2 =>
topcode := to_01( b_i(15 downto 8));
when others => -- 3
topcode := to_01( b_i(7 downto 0));
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
a_addr_r <= sp_r;
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
| bsd-3-clause | 49df47ecf13322a0ca4a63847ba38413 | 0.346763 | 4.458584 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/mlite_cpu.vhd | 1 | 12,772 | ---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a three or four stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #1:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #2:
-- 2. The memory returns the opcode.
-- Stage #3:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #4 (part of stage #3 if using three stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #4b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a three stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in mem_byte_we Stages
-- ns mem_address mem_data_w mem_data_r 40 44 48 4c 50
-- 3500 0 0 00000040 00000000 00000000 0 0 1
-- 3600 0 0 00000044 00000000 34040041 0 0 2 1
-- 3700 0 0 00000048 00000000 3405FFFF 0 0 3 2 1
-- 3800 0 0 0000004C 00000000 A0A40000 0 0 3 2 1
-- 3900 0 0 0000FFFC 41414141 00000000 1 0 3 2
-- 4000 0 0 00000050 41414141 XXXXXX41 0 0 4b 3 1
-- 4100 0 0 00000054 00000000 00000000 0 0 2
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mlite_cpu is
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 3); --3 or 4
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
architecture logic of mlite_cpu is
--When using a three stage pipeline "sigD <= sig".
--When using a four stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc_future : std_logic_vector(31 downto 2);
signal pc_current : std_logic_vector(31 downto 2);
signal pc_plus4 : std_logic_vector(31 downto 2);
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
or intr_signal = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
mem_address(1 downto 0) <= "00";
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
intr_signal <= '0';
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
--don't try to interrupt a multi-cycle instruction
if pause_any = '0' then
if intr_in = '1' and intr_enable = '1' and
pc_source = FROM_INC4 then
--the epc will contain pc+4
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end if;
end process;
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_future => pc_future,
pc_current => pc_current,
pc_plus4 => pc_plus4);
u2_mem_ctrl: mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
mem_address => mem_address(31 downto 2),
mem_data_w => mem_data_w,
mem_data_r => mem_data_r,
mem_byte_we => mem_byte_we);
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
mem_source_out=> mem_source);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch);
u6_alu: alu
generic map (alu_type => alu_type)
port map (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
u7_shifter: shifter
generic map (shifter_type => shifter_type)
port map (
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
u8_mult: mult
generic map (mult_type => mult_type)
port map (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
pipeline3: if pipeline_stages <= 3 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
reg_destD <= reg_dest;
pause_pipeline <= '0';
end generate; --pipeline2
pipeline4: if pipeline_stages > 3 generate
--When operating in four stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline4
end; --architecture logic
| gpl-3.0 | 371eb8e8f937b51310d919d5c21f2865 | 0.542202 | 3.489617 | false | false | false | false |
sonologic/gmzpu | vhdl/gmzpu/gmzpu.vhdl | 1 | 11,506 | ------------------------------------------------------------------------------
---- ----
---- gmZPU core
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
---- medium version, the PHI I/O basic layout, a program BRAM and a. ----
---- wishbone controller. ----
---- ----
---- To Do: ----
---- - Add interrupt controller. ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: gmZPU ----
---- File name: gmzpu.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
library gmzpu;
use gmzpu.zwishbone.all;
use gmzpu.soc.all;
library zetaio;
use zetaio.pic.all;
use zetaio.tim.all;
-- RAM declaration
library work;
use work.zpu_memory.all;
entity gmZPU is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='X'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=9600; -- RS232 baudrate
ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
interrupt_i: in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end entity gmZPU;
architecture Structural of gmZPU is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- 0 = memory, 1= I/O
constant ZW_BIT : integer:=ADDR_W-2; -- Address bit to determine zwishbone from phiIO
-- 0 = phiIO, 1 = zwishbone
constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
-- zwishbone
constant CS_WIDTH : natural:=4;
-- devices on the bus
constant WB_CS_PIC : natural:=0;
-- PIC interrupt mapping
--constant PIC_INT_EXT : natural:=0;
--constant PIC_INT_ZWC : natural:=1;
--constant PIC_INT_UNUSED : natural:=2;
-- I/O & memory (ZPU)
signal mem_busy : std_logic;
signal mem_read : unsigned(WORD_SIZE-1 downto 0);
signal mem_write : unsigned(WORD_SIZE-1 downto 0);
signal mem_addr : unsigned(ADDR_W-1 downto 0);
signal mem_we : std_logic;
signal mem_re : std_logic;
-- Memory (SinglePort_RAM)
signal ram_busy : std_logic;
signal ram_read : unsigned(WORD_SIZE-1 downto 0);
signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram_we : std_logic;
signal ram_re : std_logic;
signal ram_ready_r : std_logic:='0';
-- I/O (ZPU_IO)
signal phi_io_busy : std_logic;
signal phi_io_re : std_logic;
signal phi_io_we : std_logic;
signal phi_io_read : unsigned(WORD_SIZE-1 downto 0);
signal phi_io_ready : std_logic;
signal phi_io_reading_r : std_logic:='0';
signal phi_io_addr : unsigned(2 downto 0);
-- I/O (zwishbone)
signal zw_busy : std_logic;
signal zw_ready : std_logic;
signal zw_addr : unsigned(ADDR_W-3 downto 0);
signal zw_re : std_logic;
signal zw_we : std_logic;
signal zw_dat_i : unsigned(WORD_SIZE-1 downto 0);
signal zw_dat_o : unsigned(WORD_SIZE-1 downto 0);
--
signal wb_dat_i : unsigned(WORD_SIZE-1 downto 0);
signal wb_dat_o : unsigned(WORD_SIZE-1 downto 0);
signal wb_tgd_i : unsigned(WORD_SIZE-1 downto 0);
signal wb_tgd_o : unsigned(WORD_SIZE-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_adr_o : unsigned(ADDR_W-4-CS_WIDTH downto 0);
signal wb_cyc_o : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_lock_o : std_logic;
signal wb_rty_i : std_logic;
signal wb_sel_o : std_logic_vector(WORD_SIZE-1 downto 0);
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_tga_o : unsigned(ADDR_W-4-CS_WIDTH downto 0);
signal wb_tgc_o : unsigned(WORD_SIZE-1 downto 0); -- size correct?
signal wb_we_o : std_logic;
-- interrupt
signal irq_r : std_logic;
begin
memory: SinglePortRAM
generic map(
WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
port map(
clk_i => clk_i,
we_i => ram_we, re_i => ram_re, addr_i => ram_addr,
write_i => mem_write, read_o => ram_read, busy_o => ram_busy);
ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS);
ram_we <= mem_we and not(mem_addr(IO_BIT));
ram_re <= mem_re and not(mem_addr(IO_BIT));
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
BRDIVISOR => BRDIVISOR,
LOG_FILE => "zpu_med1_io.log"
)
port map(
clk_i => clk_i,
reset_i => rst_i,
busy_o => phi_io_busy,
we_i => phi_io_we,
re_i => phi_io_re,
data_i => mem_write,
data_o => phi_io_read,
addr_i => phi_io_addr,
rs232_rx_i => rs232_rx_i,
rs232_tx_o => rs232_tx_o,
br_clk_i => '1',
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir
);
phi_io_addr <= mem_addr(4 downto 2);
-- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
-- Note: We define the address space as 256 kB, so writing to 0x80A00xx
-- will be as wrting to 0x200xx and hence we decode it as I/O space.
phi_io_we <= mem_we and mem_addr(IO_BIT) and not mem_addr(ZW_BIT);
phi_io_re <= mem_re and mem_addr(IO_BIT) and not mem_addr(ZW_BIT);
phi_io_ready <= (phi_io_reading_r or phi_io_re) and not phi_io_busy;
-- I/O: zwishbone
zwc0: zwc
generic map(
DATA_WIDTH => WORD_SIZE, ADR_WIDTH => ADDR_W-2, CS_WIDTH => 4
)
port map(
clk_i => clk_i, rst_i => rst_i, re_i => zw_re, busy_o => zw_busy, ready_o => zw_ready, irq_o => irq_r,
adr_i => zw_addr, we_i => zw_we, dat_i => zw_dat_i, dat_o => zw_dat_o,
int_i => interrupt_i
);
-- ADDR_W = 18, IO_BIT = 17, ZW_BIT = 16
zw_we <= mem_we and mem_addr(IO_BIT) and mem_addr(ZW_BIT);
zw_re <= mem_re and mem_addr(IO_BIT) and mem_addr(ZW_BIT);
zw_addr <= mem_addr(ADDR_W-3 downto 0);
zw_dat_i <= mem_write;
-- interrupt line connect
--int_r(WORD_SIZE-1 downto PIC_INT_UNUSED) <= (others => '0');
--int_r(PIC_INT_EXT) <= interrupt_i;
--int_r(PIC_INT_ZWC) <= zwc_irq_r;
zpu : ZPUMediumCore
generic map(
WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
D_CARE_VAL => D_CARE_VAL)
port map(
clk_i => clk_i, reset_i => rst_i, interrupt_i => irq_r, enable_i => '1',
break_o => break_o, dbg_o => dbg_o,
-- Memory
mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write,
addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re);
mem_busy <= (phi_io_busy or ram_busy) or zw_busy;
-- Memory reads either come from IO or DRAM. We need to pick the right one.
memory_control:
process (ram_read, ram_ready_r, phi_io_ready, phi_io_read, zw_dat_o, zw_ready)
begin
mem_read <= (others => '0');
if ram_ready_r='1' then
mem_read <= ram_read;
end if;
if phi_io_ready='1' then
mem_read <= phi_io_read;
end if;
if zw_ready='1' then
mem_read <= unsigned(zw_dat_o);
end if;
end process memory_control;
memory_control_sync:
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
phi_io_reading_r <= '0';
ram_ready_r <= '0';
else
phi_io_reading_r <= phi_io_busy or phi_io_re;
ram_ready_r <= ram_re;
end if;
end if;
end process memory_control_sync;
end architecture Structural; -- Entity: gmZPU
| bsd-3-clause | e78070fb7554fa70a87ac8d3a6396592 | 0.437337 | 3.76136 | false | false | false | false |
ComputerArchitectureGroupPWr/SimulationCore | src/main.vhd | 1 | 3,741 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity SimCore is
port(
rs232rx : in std_logic;
rst : in std_logic;
clk : in std_logic;
rs232tx : out std_logic;
led : out std_logic_vector(7 downto 0);
CLKMULOUT : out std_logic;
CLK2XOUT : out std_logic
);
end SimCore;
architecture Behavioral of SimCore is
component thermometersLogic
port(
rsTxBusy : IN std_logic;
rst : IN std_logic;
clk50Mhz : IN std_logic;
clk3kHz : IN std_logic;
rsDataOut : OUT std_logic_vector(7 downto 0);
rsTxStart : OUT std_logic;
led : OUT std_logic_vector(7 downto 0)
);
end component;
component heatersLogic
port(
rsDataIn : in std_logic_vector(7 downto 0);
rsRdy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
readyOut : out std_logic
);
end component;
component RS232
port(
rs232_rxd : in std_logic;
txdi : in std_logic_vector(7 downto 0);
txstart : in std_logic;
reset : in std_logic;
clk_50Mhz : in std_logic;
clk_sys : in std_logic;
rs232_txd : out std_logic;
rxdo : out std_logic_vector(7 downto 0);
rxrdy : out std_logic;
txbusy : out std_logic
);
end component;
component FeqDiv
generic( width : integer );
port(
clkIn : IN std_logic;
clkOut : OUT std_logic
);
end component;
COMPONENT ClockGenerator
PORT(
clk100Mhz : IN std_logic;
reset : IN std_logic;
clk50Mhz : OUT std_logic
);
END COMPONENT;
COMPONENT HeaterClockGenerator
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic
);
END COMPONENT;
signal clk50Mhz : std_logic;
signal clk3kHz : std_logic;
signal rsDataOut : std_logic_vector(7 downto 0);
signal rsDataIn : std_logic_vector(7 downto 0);
signal rsTxStart : std_logic;
signal rsTxBusy : std_logic;
signal rsRxRdy : std_logic;
signal heatersLogicReady : std_logic;
signal clkfx : std_logic;
attribute keep : string;
attribute keep of heatersLogicReady: signal is "True";
attribute keep_hierarchy : string;
attribute keep_hierarchy of thermometersLogic: component is "TRUE";
attribute keep_hierarchy of heatersLogic: component is "TRUE";
attribute keep_hierarchy of FeqDiv: component is "TRUE";
attribute keep_hierarchy of RS232: component is "TRUE";
begin
InstFeqDiv: FeqDiv generic map( width => 14 )
port map(
clkIn => clk50MHz,
clkOut => clk3kHz
);
InstThermometersLogic: thermometersLogic
port map(
rsTxBusy => rsTxBusy,
rst => rst,
clk50Mhz => clk50Mhz,
clk3kHz => clk3kHz,
rsDataOut => rsDataOut,
rsTxStart => rsTxStart,
led => led
);
InstHeatersLogic: heatersLogic PORT MAP(
rsDataIn => rsDataIn,
rsRdy => rsRxRdy,
rst => rst,
clk50Mhz => clk50Mhz,
readyOut => heatersLogicReady
);
InstRS232: RS232 port map(
rs232_rxd => rs232rx,
txdi => rsDataOut,
txstart => rsTxStart,
reset => rst,
clk_50Mhz => clk50Mhz,
clk_sys => clk50Mhz,
rs232_txd => rs232tx,
rxdo => rsDataIn,
rxrdy => rsRxRdy,
txbusy => rsTxBusy
);
Inst_ClockGenerator: ClockGenerator PORT MAP(
clk100Mhz => clk,
reset => rst,
clk50Mhz => clk50Mhz
);
Inst_SystemClockGenerator: HeaterClockGenerator PORT MAP(
CLKIN_IN => clk,
RST_IN => rst,
CLKFX_OUT => clkfx,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2x_OUT => open
);
CLKMULOUT <= clkfx;
Inst_SystemClockGenerator2: HeaterClockGenerator PORT MAP(
CLKIN_IN => clkfx,
RST_IN => rst,
CLKFX_OUT => open,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2X_OUT => CLK2XOUT
);
end Behavioral; | mit | d9cd97d67fb287955df709b1a9409f20 | 0.66934 | 2.9 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/Stopwatch.vhd | 1 | 1,667 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:47:55 03/25/2015
-- Design Name:
-- Module Name: Stopwatch - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Stopwatch is
port(
clk : in std_logic;
stamp_and_reset : in std_logic;
time_stamp : out std_logic_vector(7 downto 0)
);
end Stopwatch;
architecture RTL of Stopwatch is
signal counter : std_logic_vector(11 downto 0) := (others => '0');
type sw_state is (idle, should_stamp, should_reset, counting);
signal state : sw_state := idle;
begin
process(clk, state, counter, stamp_and_reset) begin
if (stamp_and_reset = '1') then
state <= should_stamp; -- pXª§¿ºªèAÌNbNÅ^CX^vAXÉÌNbNÅZbg
else
if (rising_edge(clk)) then
if (state = should_stamp) then
time_stamp <= counter(11 downto 4);
state <= should_reset;
elsif (state = should_reset) then
counter <= (others => '0');
state <= counting;
elsif (counter = "111111111111") then
counter <= (others => '0');
time_stamp <= (others => '0');
state <= idle;
elsif (state = counting) then
counter <= counter + 1;
else
counter <= counter;
end if;
end if;
end if;
end process;
end RTL;
| bsd-3-clause | f29847ce6bb9c122bfb63eba5ded7fcc | 0.55249 | 3.009025 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/alf/src/vram/vram.vhd | 1 | 6,155 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| gpl-3.0 | 16ad7b6e59f37901820e549038028c0e | 0.522177 | 3.893106 | false | false | false | false |
Subsets and Splits