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marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahb_mst_iface.vhd | 1 | 5,006 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb_mst_iface
-- File: ahb_mst_iface.vhd
-- Author: Marko Isomaki - Aeroflex Gaisler
-- Description: General AHB master interface for DMA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
entity ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end entity;
architecture rtl of ahb_mst_iface is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( vendor, device, 0, revision, 0),
others => zero32);
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, msti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable vretry : std_ulogic;
variable vready : std_ulogic;
variable verror : std_ulogic;
variable vgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; vready := '0'; vretry := '0';
verror := '0'; vgrant := '0';
hsize := HSIZE_WORD;
hwdata := msti.data;
hbusreq := msti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := msti.addr; hwrite := msti.write;
if (msti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (msti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
vgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => vready := '1';
when HRESP_SPLIT | HRESP_RETRY => vretry := '1';
when HRESP_ERROR => verror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
msto.data <= ahbreadword(ahbmi.hrdata);
msto.error <= verror;
msto.retry <= vretry;
msto.ready <= vready;
msto.grant <= vgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= ahbdrivedata(hwdata);
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
end architecture;
| gpl-2.0 | 5f3be32e1b80fff487dd0ff67572195d | 0.565322 | 3.630167 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/startBtn/simulation/bmg_stim_gen.vhd | 1 | 12,585 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (9999 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"startBtn.mif",
DEFAULT_DATA,
12,
10000);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>10000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 10000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 2242d584a41b3f7eda8f1e914bc6ebdf | 0.547954 | 3.688453 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-3s1500/testbench.vhd | 1 | 12,498 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 16; -- system clock period
comboard : integer := 1 -- Comms. adapter board attached
);
port (
pci_rst : out std_logic;
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end component;
signal clk : std_logic := '0';
constant ct : integer := clkperiod/2;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal tx, rx : std_logic;
signal dsutx, dsurx : std_logic;
signal leds : std_logic_vector(7 downto 0);
signal switches : std_logic_vector(5 downto 0);
constant lresp : boolean := false;
signal sram_oe_l, sram_we_l : std_logic;
signal sram_cs_l : std_logic_vector(1 downto 0);
signal sram_ben_l : std_logic_vector(0 to 3);
signal sram_dq : std_logic_vector(31 downto 0);
signal flash_cs_l, flash_rst_l : std_logic;
signal iosn : std_logic;
signal phy_txck : std_logic;
signal phy_rxck : std_logic;
signal phy_rxd : std_logic_vector(3 downto 0);
signal phy_rxdt : std_logic_vector(7 downto 0);
signal phy_rxdv : std_logic;
signal phy_rxer : std_logic;
signal phy_col : std_logic;
signal phy_crs : std_logic;
signal phy_txd : std_logic_vector(3 downto 0);
signal phy_txdt : std_logic_vector(7 downto 0);
signal phy_txen : std_logic;
signal phy_txer : std_logic;
signal phy_mdc : std_logic;
signal phy_mdio : std_logic;
signal phy_reset_l : std_logic;
signal phy_gtx_clk : std_logic := '0';
signal video_clk : std_logic := '0';
signal comp_sync : std_logic;
signal blank : std_logic;
signal video_out : std_logic_vector(23 downto 0);
signal msclk : std_logic;
signal msdata : std_logic;
signal kbclk : std_logic;
signal kbdata : std_logic;
signal dsurst : std_logic;
signal disp_seg1 : std_logic_vector(7 downto 0);
signal disp_seg2 : std_logic_vector(7 downto 0);
signal baddr : std_logic_vector(27 downto 0) := (others => '0');
signal can_txd : std_logic;
signal can_rxd : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
switches(0) <= '1'; -- DSUEN
switches(4) <= not dsurst; -- reset
switches(5) <= '0'; -- DSUBRE
dsutx <= tx; rx <= dsurx;
pci_rst <= phy_reset_l;
phy_reset_l <= 'H';
video_clk <= not video_clk after 20 ns;
can_rxd <= can_txd;
sddqm(3) <= sram_ben_l(0); sddqm(2) <= sram_ben_l(1);
sddqm(1) <= sram_ben_l(2); sddqm(0) <= sram_ben_l(3);
cpu : leon3mp
generic map (fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (clk, sdclk, leds, switches, baddr(24 downto 0),
sram_ben_l, sram_cs_l, sram_oe_l, sram_we_l, sram_dq,
flash_cs_l, flash_rst_l, iosn, sdclk, sdrasn, sdcasn, sdcke, sdcsn,
tx, rx, can_txd, can_rxd, phy_txck, phy_rxck, phy_rxd, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txd, phy_txen, phy_txer, phy_mdc,
phy_mdio, phy_reset_l,
video_clk, comp_sync, blank, video_out,
msclk, msdata, kbclk, kbdata, disp_seg1, disp_seg2,
pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66);
-- One 32-bit SRAM bank on main board
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(17 downto 0), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(0), sram_we_l, sram_oe_l);
end generate;
phy_mdio <= 'H';
phy_rxd <= phy_rxdt(3 downto 0);
phy_txdt <= "0000" & phy_txd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(dsurst, phy_mdio, phy_txck, phy_rxck, phy_rxdt, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txdt, phy_txen, phy_txer, phy_mdc, phy_gtx_clk);
-- optional communications adapter
comms : if (comboard = 1) generate
-- 32-bit flash prom
flash0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => promfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
flash_cs_l, flash_cs_l, flash_cs_l, sram_we_l, sram_oe_l);
end generate;
-- second SRAM bank
sram1 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(1), sram_we_l, sram_oe_l);
end generate;
sdwen <= sram_we_l;
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sram_dq(31 downto 16), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sram_dq(15 downto 0), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
test0 : grtestmod
port map ( dsurst, clk, leds(0), baddr(21 downto 2), sram_dq,
iosn, sram_oe_l, sram_we_l, open);
leds(0) <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(leds(0)) = '0' then wait on leds; end if;
assert (to_x01(leds(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sram_dq <= buskeep(sram_dq), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 0025ac63b6b6126aef0b9a072c4e4ce0 | 0.596976 | 3.050525 | false | false | false | false |
IamVNIE/Hardware-Security | Hardware Trojan Insertion Lab/Low_level_modelling_code.vhd | 2 | 8,626 | ----------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 15:20:34 05/28/2013
-- Design Name: Ring_Oscillator_Manual_Placement_Design
-- Module Name: RO_Design_File - Behavioral
-- Project Name: FPGA Trojan Detection
-- Target Devices: 90nm Devices, 65nm-Virtex 5, 28nm-Virtex 7
-- Tool versions:
-- Description: This file describes a 7 stage ring oscillator in single slice.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Right_RO_Design_File is
generic (SLICE_NUM1: string := "SLICE_X10Y0";
SLICE_NUM2: string := "SLICE_X11Y0";
OSC_SLICE_NUM: string := "SLICE_X11Y1"
);
port( osc_out : out std_logic;
reset : in std_logic );
end Right_RO_Design_File;
architecture Behavioral of Right_RO_Design_File is
--------------------------- 7 STAGE RING OSCILLATOR -----------------
---------------------- Remove 1 slice also for 4 inv------
signal ring_delay1 : std_logic;
signal ring_delay2 : std_logic;
signal ring_delay3 : std_logic;
signal ring_delay4 : std_logic;
signal ring_invert : std_logic;
signal ring_delay5 : std_logic;
signal ring_delay6 : std_logic;
signal ring_delay7 : std_logic;
signal ring_delay1_f : std_logic;
signal ring_delay2_f : std_logic;
signal ring_delay3_f : std_logic;
signal ring_delay4_f : std_logic;
signal ring_invert_F : std_logic;
signal ring_delay5_f : std_logic;
signal ring_delay6_f : std_logic;
signal ring_delay7_f : std_logic;
--
-- Attributes to stop delay logic from being optimised.
--
attribute S : string;
attribute S of ring_invert : signal is "true";
attribute S of ring_delay1 : signal is "true";
attribute S of ring_delay2 : signal is "true";
attribute S of ring_delay3 : signal is "true";
attribute S of ring_delay4 : signal is "true";
attribute S of ring_delay5 : signal is "true";
attribute S of ring_delay6 : signal is "true";
attribute S of ring_delay7 : signal is "true";
------------------ MAPPING LUT's---------------------------------->>>
attribute LOC : string;
attribute LOC of invert_lut : label is SLICE_NUM1;
attribute LOC of delay1_lut : label is SLICE_NUM1;
attribute LOC of delay2_lut : label is SLICE_NUM1;
attribute LOC of delay3_lut : label is SLICE_NUM1;
attribute LOC of delay4_lut : label is SLICE_NUM2;
attribute LOC of delay5_lut : label is SLICE_NUM2;
attribute LOC of delay6_lut : label is SLICE_NUM2;
attribute LOC of delay7_lut : label is SLICE_NUM2;
attribute LOC of osc_out_lut : label is OSC_SLICE_NUM;
----
attribute lock_pins: string;
attribute lock_pins of invert_lut: label is "all";
attribute lock_pins of delay1_lut: label is "all";
attribute lock_pins of delay2_lut: label is "all";
attribute lock_pins of delay3_lut: label is "all";
attribute lock_pins of delay4_lut: label is "all";
attribute lock_pins of delay5_lut: label is "all";
attribute lock_pins of delay6_lut: label is "all";
attribute lock_pins of delay7_lut: label is "all";
attribute lock_pins of osc_out_lut: label is "all";
attribute bel : string;
attribute bel of invert_lut: label is "D6LUT";
attribute bel of delay1_lut: label is "C6LUT";
attribute bel of delay2_lut: label is "B6LUT";
attribute bel of delay3_lut: label is "A6LUT";
attribute bel of delay4_lut: label is "D6LUT";
attribute bel of delay5_lut: label is "C6LUT";
attribute bel of delay6_lut: label is "B6LUT";
attribute bel of delay7_lut: label is "A6LUT";
attribute bel of osc_out_lut: label is "D6LUT";
attribute syn_keep : boolean;
attribute KEEP : string;
attribute syn_keep of ring_delay1 : signal is true;
attribute syn_keep of ring_delay2 : signal is true;
attribute syn_keep of ring_delay3 : signal is true;
attribute syn_keep of ring_delay4 : signal is true;
attribute syn_keep of ring_delay5 : signal is true;
attribute syn_keep of ring_delay6 : signal is true;
attribute syn_keep of ring_delay7 : signal is true;
attribute syn_keep of ring_invert : signal is true;
attribute KEEP of ring_delay1 : signal is "TRUE";
attribute KEEP of ring_delay2 : signal is "TRUE";
attribute KEEP of ring_delay3 : signal is "TRUE";
attribute KEEP of ring_delay4 : signal is "TRUE";
attribute KEEP of ring_delay5 : signal is "TRUE";
attribute KEEP of ring_delay6 : signal is "TRUE";
attribute KEEP of ring_delay7 : signal is "TRUE";
attribute KEEP of ring_invert : signal is "TRUE";
begin
osc_out_lut : LUT6
generic map(
INIT => X"0000FFFF0000FFFF"
)
port map (
I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I5 => '1',
I4 => ring_delay4_f,
O => osc_out
);
invert_lut : LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBBB"
)
port map (
I0 => reset,
I1 => ring_delay7,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_invert_f
);
delay1_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_invert,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay1_f
);
delay2_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay1,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay2_f
);
delay3_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay2,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay3_f
);
delay4_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay3,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay4_f
);
delay5_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay4,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay5_f
);
delay6_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay5,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay6_f
);
delay7_lut : LUT6
generic map(
INIT => X"4444444444444444"
)
port map (
I0 => '0',
I1 => ring_delay6,
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O => ring_delay7_f
);
LDCE_inst : LDCE
port map (
Q => ring_invert, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_invert_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst2 : LDCE
port map (
Q => ring_delay1, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay1_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst3 : LDCE
port map (
Q => ring_delay2, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay2_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst4 : LDCE
port map (
Q => ring_delay3, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay3_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst5 : LDCE
port map (
Q => ring_delay4, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay4_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst6 : LDCE
port map (
Q => ring_delay5, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay5_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst7 : LDCE
port map (
Q => ring_delay6, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay6_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
LDCE_inst8 : LDCE
port map (
Q => ring_delay7, -- Data output
CLR => '0', -- Asynchronous clear/reset input
D => ring_delay7_f, -- Data input
G => '1', -- Gate input
GE => '1' -- Gate enable input
);
end Behavioral;
| mit | fd9afdaa41367e4483ae4ffe7dfbd11a | 0.574658 | 3.156239 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd | 3 | 38,399 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_strm.vhd.vhd
-- Description: This entity is the AXI Status Stream Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_srl_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_strm is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_SKID : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
s2mm_rxlength_valid : out std_logic ; --
s2mm_rxlength_clr : in std_logic ; --
s2mm_rxlength : out std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
stsstrm_fifo_rden : in std_logic ; --
stsstrm_fifo_empty : out std_logic ; --
stsstrm_fifo_dout : out std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_sts_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status Stream FIFO Depth
constant STSSTRM_FIFO_DEPTH : integer := 16;
-- Status Stream FIFO Data Count Width (Unsused)
constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_full : std_logic := '0';
signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_sinit : std_logic := '0';
signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_cdc_from : std_logic := '0';
signal rxlength_valid_trdy : std_logic := '0';
--signal sts_tvalid_re : std_logic := '0';-- CR565502
--signal sts_tvalid_d1 : std_logic := '0';-- CR565502
signal sts_tvalid : std_logic := '0';
signal sts_tready : std_logic := '0';
signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sts_tlast : std_logic := '0';
signal m_tvalid : std_logic := '0';
signal m_tready : std_logic := '0';
signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_tlast : std_logic := '0';
signal tag_stripped : std_logic := '0';
signal mask_tag_write : std_logic := '0';
--signal mask_tag_hold : std_logic := '0';-- CR565502
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal s2mm_stop_d1 : std_logic := '0';
signal s2mm_stop_re : std_logic := '0';
signal sts_rden : std_logic := '0';
signal follower_empty : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
begin
-- Generate Synchronous FIFO
-- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0.sync_fifo_fg
-- generic map (
-- C_FAMILY => C_FAMILY ,
-- C_MEMORY_TYPE => USE_LOGIC_FIFOS,
-- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_READ_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_PORTS_DIFFER => 0,
-- C_HAS_DCOUNT => 1, --req for proper fifo operation
-- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_RD_ACK => 0,
-- C_HAS_RD_ERR => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_ERR => 0,
-- C_RD_ACK_LOW => 0,
-- C_RD_ERR_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_ERR_LOW => 0,
-- C_PRELOAD_REGS => 1,-- 1 = first word fall through
-- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- -- C_USE_EMBEDDED_REG => 1 -- 0 ;
-- )
-- port map (
--
-- Clk => m_axi_sg_aclk ,
-- Sinit => fifo_sinit ,
-- Din => fifo_din ,
-- Wr_en => fifo_wren ,
-- Rd_en => stsstrm_fifo_rden ,
-- Dout => stsstrm_fifo_dout ,
-- Full => fifo_full ,
-- Empty => stsstrm_fifo_empty ,
-- Almost_full => open ,
-- Data_count => open ,
-- Rd_ack => open ,
-- Rd_err => open ,
-- Wr_ack => open ,
-- Wr_err => open
--
-- );
I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => fifo_sinit ,
FIFO_Write => fifo_wren ,
Data_In => fifo_din ,
FIFO_Read => sts_rden, --sts_queue_rden ,
Data_Out => fifo_out, --sts_queue_dout ,
FIFO_Empty => fifo_empty, --sts_queue_empty ,
FIFO_Full => fifo_full ,
Addr => open
);
sts_rden <= (not fifo_empty) and follower_empty;
stsstrm_fifo_empty <= follower_empty;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then
follower_empty <= '1';
elsif (sts_rden = '1') then
follower_empty <= '0';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1') then
stsstrm_fifo_dout <= (others => '0');
elsif (sts_rden = '1') then
stsstrm_fifo_dout <= fifo_out;
end if;
end if;
end process;
fifo_sinit <= not m_axi_sg_aresetn;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write;
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
--
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif((sts_tvalid_re = '1' and tag_stripped = '0')
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
end if;
end if;
end process REG_RXLENGTH;
s2mm_rxlength_valid <= rxlength_valid_cdc_from;
s2mm_rxlength <= rxlength_cdc_from;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- register stop to create re pulse
REG_STOP : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
s2mm_stop_d1 <= '0';
else
s2mm_stop_d1 <= s2mm_stop;
end if;
end if;
end process REG_STOP;
s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1;
skid_rst <= not m_axi_sg_aresetn;
ENABLE_SKID : if C_ENABLE_SKID = 1 generate
begin
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate ENABLE_SKID;
DISABLE_SKID : if C_ENABLE_SKID = 0 generate
begin
sts_tvalid <= s_axis_s2mm_sts_tvalid;
s_axis_s2mm_sts_tready <= sts_tready;
sts_tdata <= s_axis_s2mm_sts_tdata;
sts_tkeep <= s_axis_s2mm_sts_tkeep;
sts_tlast <= s_axis_s2mm_sts_tlast;
end generate DISABLE_SKID;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal s2mm_stop_reg : std_logic := '0'; -- CR605883
signal p_s2mm_stop_d1_cdc_tig : std_logic := '0';
signal p_s2mm_stop_d2 : std_logic := '0';
signal p_s2mm_stop_d3 : std_logic := '0';
signal p_s2mm_stop_re : std_logic := '0';
--ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true";
begin
-- Generate Asynchronous FIFO
I_STSSTRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 ,
-- C_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH ,
C_DEPTH => 15 ,
C_CNT_WIDTH => 4 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_sinit ,
AFIFO_Wr_clk => axi_prmry_aclk ,
AFIFO_Wr_en => fifo_wren ,
AFIFO_Din => fifo_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => stsstrm_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => stsstrm_fifo_dout ,
AFIFO_Full => fifo_full ,
AFIFO_Empty => stsstrm_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
fifo_sinit <= not p_reset_n;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid -- valid data
and not fifo_full -- fifo has room
and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length
and not mask_tag_write; -- not masking off tag word
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
--
-- elsif(sts_tvalid_re = '1'
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
signal rxlength_clr_d1_cdc_tig : std_logic := '0';
signal rxlength_clr_d2 : std_logic := '0';
signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_d1_cdc_to : std_logic := '0';
signal rxlength_valid_d2_cdc_from : std_logic := '0';
signal rxlength_valid_d3 : std_logic := '0';
signal rxlength_valid_d4 : std_logic := '0';
signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0';
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true";
begin
-- Double register from secondary clock domain to primary
S2P_CLK_CROSS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_rxlength_clr,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_clr_d2,
scndry_vect_out => open
);
-- S2P_CLK_CROSS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0')then
-- rxlength_clr_d1_cdc_tig <= '0';
-- rxlength_clr_d2 <= '0';
-- else
-- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr;
-- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig;
-- end if;
-- end if;
-- end process S2P_CLK_CROSS;
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
TRDY_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or rxlength_clr_d2 = '1')then
rxlength_valid_trdy <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_valid_trdy <= '1';
end if;
end if;
end process TRDY_RXLENGTH;
REG_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
elsif (rxlength_valid_d2_back = '1') then
rxlength_valid_cdc_from <= '0';
end if;
end if;
end process REG_RXLENGTH;
SYNC_RXLENGTH : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_d2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_back,
scndry_vect_out => open
);
-- SYNC_RXLENGTH : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
--
-- rxlength_valid_d1_back_cdc_to <= '0';
-- rxlength_valid_d2_back <= '0';
-- else
-- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from;
-- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to;
--
-- end if;
-- end if;
-- end process SYNC_RXLENGTH;
-- Double register from primary clock domain to secondary
P2S_CLK_CROSS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_cdc_from,
scndry_vect_out => open
);
P2S_CLK_CROSS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => rxlength_cdc_from,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => rxlength_d2
);
P2S_CLK_CROSS1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then
-- rxlength_d1_cdc_to <= (others => '0');
-- rxlength_d2 <= (others => '0');
-- rxlength_valid_d1_cdc_to <= '0';
-- rxlength_valid_d2_cdc_from <= '0';
rxlength_valid_d3 <= '0';
else
-- rxlength_d1_cdc_to <= rxlength_cdc_from;
-- rxlength_d2 <= rxlength_d1_cdc_to;
-- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from;
-- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to;
rxlength_valid_d3 <= rxlength_valid_d2_cdc_from;
end if;
end if;
end process P2S_CLK_CROSS1;
process (m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_valid_d4 <= '0';
elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then
rxlength_valid_d4 <= '1';
end if;
end if;
end process;
s2mm_rxlength <= rxlength_d2;
-- s2mm_rxlength_valid <= rxlength_valid_d2;
s2mm_rxlength_valid <= rxlength_valid_d4;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop_reg <= '0';
else
s2mm_stop_reg <= s2mm_stop;
end if;
end if;
end process REG_STOP;
-- double register s2mm error into primary clock domain
REG_ERR2PRMRY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_s2mm_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_s2mm_stop_d1_cdc_tig <= '0';
-- p_s2mm_stop_d2 <= '0';
p_s2mm_stop_d3 <= '0';
else
--p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883
-- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg;
-- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig;
p_s2mm_stop_d3 <= p_s2mm_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY1;
p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 | cb79f75716cbb70b3c4d2991e2648ca9 | 0.446887 | 4.007828 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_register.vhd | 1 | 52,030 | -------------------------------------------------------------------------------
-- axi_cdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_cdma_register is
generic(
C_CDMA_BUILD_MODE : integer range 0 to 1 := 0 ;
C_NUM_REGISTERS : integer range 0 to 16 := 6 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
-- Input Clock
axi_aclk : in std_logic ;
-- Input Reset (active high)
axi_reset : in std_logic ;
-- AXI Interface Control
axi2ip_wrce : in std_logic_vector
(C_NUM_REGISTERS-1 downto 0) ;
-- AXI Interface Write Data
axi2ip_wrdata : in std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- Composite Interrupt Output
introut : out std_logic ;
-- Composite error Output
error_out : out std_logic ;
-- Soft Reset Set Control
soft_reset_request : out std_logic ;
-- Soft Reset Clear
soft_reset_clr : in std_logic ;
-- DMA Go Control
dma_go : Out std_logic ;
-- SG Mode control
dma_sg_mode : Out std_logic ;
-- Key Hole Read
dma_keyhole_read : Out std_logic ;
-- Key Hole Write
dma_keyhole_write : Out std_logic ;
-- Key Hole Write
dma_cyclic : Out std_logic ;
-- CDMASR Idle bit set
idle_set : in std_logic ;
-- CDMASR Idle bit clear
idle_clr : in std_logic ;
-- CDMASR Idle bit clear
ioc_irq_set : in std_logic ;
-- CDMASR Delay Interrupt set
dly_irq_set : in std_logic ;
-- CDMASR Delay Interrupt Counter value
irqdelay_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value
irqthresh_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value write enable
irqthresh_wren : out std_logic ;
-- CDMASR Delay Interrupt Counter value write enable
irqdelay_wren : out std_logic ;
-- Composite DataMover Internal Error flag
dma_interr_set : in std_logic ;
-- Composite DataMover Slave Error flag
dma_slverr_set : in std_logic ;
-- Composite DataMover Decode Error flag
dma_decerr_set : in std_logic ;
-- SG Descriptor Fetch internal error flag
ftch_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
ftch_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
ftch_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
ftch_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG Descriptor Update internal error flag
updt_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
updt_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
updt_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
updt_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG CURDESC Update (in from SG)
update_curdesc : in std_logic ;
-- SG CURDESC Update address value
new_curdesc : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- Tailpointer Register Updated flag
tailpntr_updated : out std_logic ;
-- Current Descriptor Register Updated flag
currdesc_updated : out std_logic ;
-- CDMA Control Register value
dmacr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Status Register value
dmasr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register LS value
curdesc_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register MS value
curdesc_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Tailpointer Register LS value
taildesc_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Tailpointer Register MS value
taildesc_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Source Address Register LS value
src_addr_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Source Address Register MS value
src_addr_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA destination Register LS value
dest_addr_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA destination Register MS value
dest_addr_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA BTT Register value
btt : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0)
);
end axi_cdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant SA_LSB_INDEX : integer := 6; -- SA LSB Reg index
constant SA_MSB_INDEX : integer := 7; -- SA MSB Reg index
constant DA_LSB_INDEX : integer := 8; -- DA LSB Reg index
constant DA_MSB_INDEX : integer := 9; -- DA MSB Reg index
constant BTT_INDEX : integer := 10; -- BTT Reg index
constant BTT_WIDTH : integer := 23; -- BTT Field width
constant BTT_RSVD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH -
BTT_WIDTH; -- BTT Reserved field width
constant BTT_RESERVED_BITS : std_logic_vector(BTT_RSVD_WIDTH-1 downto 0) :=
(others => '0'); -- Set the reserved value
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
Constant SIMPLE_DISABLE : boolean := (C_CDMA_BUILD_MODE = 0);
-- 0 = Simple mode only
-- Used to reset registers not
-- used in Simple DMA only mode
Constant ALWAYS_DISABLE : boolean := TRUE; -- Used to disable
Constant DMACR_THRESH_WIDTH : integer := 8;
Constant THRESH_DEFAULT : std_logic_vector(DMACR_IRQTHRESH_MSB_BIT downto
DMACR_IRQTHRESH_LSB_BIT) :=
STD_LOGIC_VECTOR(
TO_UNSIGNED(C_CDMA_BUILD_MODE,
DMACR_THRESH_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal idle : std_logic := '0';
signal sig_composite_error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sig_sg_included : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
signal sig_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_sa_register_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sa_register_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_da_register_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_da_register_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_register : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dma_go : std_logic := '0';
signal sig_dma_go_set : std_logic := '0';
signal sig_dma_go_clr : std_logic := '0';
signal sig_dma_sg_mode : std_logic := '0';
signal sig_dly_irqen_masked : std_logic := '0';
signal sig_dly_irqen_reg : std_logic := '0';
signal sig_ioc_irqen_reg : std_logic := '0';
signal sig_err_irqen_reg : std_logic := '0';
signal sig_dma_khwrite_mode : std_logic;
signal sig_dma_khread_mode : std_logic;
signal sig_dma_cyclic_mode : std_logic;
signal sig_btt_register_del : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
taildesc_msb <= taildesc_msb_i ;
dma_sg_mode <= sig_dma_sg_mode ;
dma_keyhole_write <= sig_dma_khwrite_mode;
dma_keyhole_read <= sig_dma_khread_mode;
dma_cyclic <= sig_dma_cyclic_mode;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= THRESH_DEFAULT;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Key Hole READ Mode Bit (Bit 4)
-------------------------------------------------------------------------------
DMAKHR_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
dmacr_i(DMACR_KHREAD_BIT) <= '0';
dmacr_i(DMACR_CYCLIC_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KHREAD_BIT) <= axi2ip_wrdata(DMACR_KHREAD_BIT);
dmacr_i(DMACR_CYCLIC_BIT) <= axi2ip_wrdata(DMACR_CYCLIC_BIT);
end if;
end if;
end process DMAKHR_MODE;
sig_dma_cyclic_mode <= dmacr_i(DMACR_CYCLIC_BIT);
sig_dma_khread_mode <= dmacr_i(DMACR_KHREAD_BIT);
-------------------------------------------------------------------------------
-- DMACR - Key Hole WRITE Mode Bit (Bit 5)
-------------------------------------------------------------------------------
DMAKHW_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
dmacr_i(DMACR_KHWRITE_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KHWRITE_BIT) <= axi2ip_wrdata(DMACR_KHWRITE_BIT);
end if;
end if;
end process DMAKHW_MODE;
sig_dma_khwrite_mode <= dmacr_i(DMACR_KHWRITE_BIT);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DMACR_SIMPLE
--
-- If Generate Description:
-- Implement the DMA Control Register discrete bits
-- for Simple DMA only build case. The Delay interrupt
-- enable bit is unused and always '0'.
--
------------------------------------------------------------
GEN_DMACR_SIMPLE : if (C_CDMA_BUILD_MODE = 0) generate
begin
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
DMACR_REGISTER_SIMPLE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED7_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED7_BIT) <=
ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 15
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& '0' -- bit 13 (always 0 in Simple only)
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_RESERVED11_BIT downto
DMACR_RESERVED7_BIT);-- bits 11 downto 4
end if;
end if;
end process DMACR_REGISTER_SIMPLE;
end generate GEN_DMACR_SIMPLE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DMACR_SG
--
-- If Generate Description:
-- Implement the DMA Control Register discrete bits
-- for SG Enabled build case. The Delay interrupt
-- enable bit is active when not in Simple Mode.
--
------------------------------------------------------------
GEN_DMACR_SG : if (C_CDMA_BUILD_MODE = 1) generate
begin
dmacr_i(DMACR_RESERVED15_BIT) <= '0' ;
dmacr_i(DMACR_ERR_IRQEN_BIT) <= sig_err_irqen_reg;
dmacr_i(DMACR_DLY_IRQEN_BIT) <= sig_dly_irqen_reg;
dmacr_i(DMACR_IOC_IRQEN_BIT) <= sig_ioc_irqen_reg;
dmacr_i(DMACR_RESERVED11_BIT downto
DMACR_RESERVED7_BIT ) <= (others => '0') ;
-------------------------------------------------------------------------------
-- DMACR - Delay Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_DLY_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sig_dly_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_dly_irqen_reg <= axi2ip_wrdata(DMACR_DLY_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_DLY_IRQEN;
-------------------------------------------------------------------------------
-- DMACR - IOC Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_IOC_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
sig_ioc_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_ioc_irqen_reg <= axi2ip_wrdata(DMACR_IOC_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_IOC_IRQEN;
-------------------------------------------------------------------------------
-- DMACR - Error Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_ERR_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
sig_err_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_err_irqen_reg <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_ERR_IRQEN;
end generate GEN_DMACR_SG;
-------------------------------------------------------------------------------
-- DMACR - Tail Pointer Enable Bit (Bit 1)
-- Fixed at 0 for simple dma only
-- Fixed at 1 (when SG included) for this release of
-- axi cdma.
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1'
when C_CDMA_BUILD_MODE = 1
else '0';
-------------------------------------------------------------------------------
-- DMACR - Reset Bit (Bit 2)
-------------------------------------------------------------------------------
DMACR_RESET : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
Elsif (dmacr_i(DMACR_RESET_BIT) = '1') Then
dmacr_i(DMACR_RESET_BIT) <= '1'; -- can't clear by write once set
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_request <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- DMACR - SG Mode Bit (Bit 3)
-------------------------------------------------------------------------------
DMASG_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_SGMODE_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SGMODE_BIT) <= axi2ip_wrdata(DMACR_SGMODE_BIT);
end if;
end if;
end process DMASG_MODE;
sig_dma_sg_mode <= dmacr_i(DMACR_SGMODE_BIT);
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
-- Run/Stop removed from CDMA
dmacr_i(DMACR_RESERVED0_BIT) <= '0';
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1)
--
-- Set by cdma controller indicating DMA is active (= 0)
-- or stopped (= 1).
---------------------------------------------------------------------------
DMASR_IDLE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1'or
idle_clr = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status SG Included (BIT 3)
---------------------------------------------------------------------------
-- Set the DMASR.SGIncld bit
sig_sg_included <= '1'
when C_CDMA_BUILD_MODE = 1
else '0';
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
sig_composite_error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= sig_composite_error;
ERROR_DEL : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process ERROR_DEL;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 13)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or -- clear if in Simple Mode
SIMPLE_DISABLE)then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 14)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
error_d1 <= '0';
else
error_d1 <= sig_composite_error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= sig_composite_error and not error_d1;
DMASR_ERRIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Status IRQ Threshold (BIT 23 - 16)
---------------------------------------------------------------------------
sig_irqthresh_status <= (others => '0')
when SIMPLE_DISABLE
Else irqthresh_status;
---------------------------------------------------------------------------
-- DMA Status IRQ Delay (BIT 31 - 24)
---------------------------------------------------------------------------
sig_irqdelay_status <= (others => '0')
when SIMPLE_DISABLE
Else irqdelay_status;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= sig_irqdelay_status -- Bits 31 downto 24
& sig_irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& sig_sg_included -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& '0'; -- Bit 0
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
currdesc_updated <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set <= '1';
currdesc_updated <= '0';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- currdesc_updated <= '0';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set <= '0';
currdesc_updated <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_IDLE_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
currdesc_updated <= '1';
else
currdesc_updated <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_IDLE_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
---------------------------------------------------------------------------
-- Simple DMA Source Address (SA) LSB Register
---------------------------------------------------------------------------
SA_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_sa_register_lsb <= (others => '0');
elsif(axi2ip_wrce(SA_LSB_INDEX) = '1')then
sig_sa_register_lsb <= axi2ip_wrdata;
end if;
end if;
end process SA_LSB_REGISTER;
src_addr_lsb <= sig_sa_register_lsb;
---------------------------------------------------------------------------
-- Simple DMA Source Address (SA) MSB Register
---------------------------------------------------------------------------
sig_sa_register_msb <= (others => '0');
src_addr_msb <= sig_sa_register_msb;
---------------------------------------------------------------------------
-- Simple DMA Destination Address (DA) LSB Register
---------------------------------------------------------------------------
DA_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_da_register_lsb <= (others => '0');
elsif(axi2ip_wrce(DA_LSB_INDEX) = '1')then
sig_da_register_lsb <= axi2ip_wrdata;
end if;
end if;
end process DA_LSB_REGISTER;
dest_addr_lsb <= sig_da_register_lsb;
---------------------------------------------------------------------------
-- Simple DMA Destination Address (DA) MSB Register
---------------------------------------------------------------------------
sig_da_register_msb <= (others => '0');
dest_addr_msb <= sig_da_register_msb;
---------------------------------------------------------------------------
-- Simple DMA Bytes to Transfer (BTT) Register
---------------------------------------------------------------------------
BTT_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_btt_register <= (others => '0');
elsif(axi2ip_wrce(BTT_INDEX) = '1')then
sig_btt_register(BTT_WIDTH-1 downto 0) <=
axi2ip_wrdata(BTT_WIDTH-1 downto 0);
end if;
end if;
end process BTT_REGISTER;
PULSE_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_btt_register_del <= '0';
else
sig_btt_register_del <= axi2ip_wrce(BTT_INDEX);
end if;
end if;
end process PULSE_REGISTER;
--sig_dma_go_set <= axi2ip_wrce(BTT_INDEX);
sig_dma_go_set <= axi2ip_wrce(BTT_INDEX) and (not sig_btt_register_del);
btt <= BTT_RESERVED_BITS &
sig_btt_register(BTT_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Simple DMA GO Control
---------------------------------------------------------------------------
IMP_DMA_GO_REG : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_go_clr = '1')then
sig_dma_go <= '0';
elsif(sig_dma_go_set = '1')then
sig_dma_go <= '1';
end if;
end if;
end process IMP_DMA_GO_REG;
sig_dma_go_clr <= idle_clr ; -- Clear the GO when IDLE is cleared
dma_go <= sig_dma_go; -- assign the dma_go output
end implementation;
| gpl-3.0 | 8858931a7ead677571f4cc522e2116f8 | 0.43498 | 4.620371 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-arrow-bemicro-sdk/testbench.vhd | 1 | 7,275 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : mt46v16m16
generic map (index => -1, fname => sdramfile)
port map(
Dq => ram_d(15 downto 0), Dqs => ram_dqs(1 downto 0), Addr => ram_a(12 downto 0),
Ba => ram_ba, Clk => ram_ck_p, Clk_n => ram_ck_n, Cke => ram_cke,
Cs_n => ram_cs_n, Ras_n => ram_ras_n, Cas_n => ram_cas_n, We_n => ram_ws_n,
Dm => ram_dm(1 downto 0));
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | b0343959dbb23d8d012ae50b7a70ad85 | 0.576632 | 3.377437 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/bscanregsbd.vhd | 1 | 3,105 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregsbd
-- File: bscanregsbd.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, bi-directional IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregsbd is
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output
);
end;
architecture rtl of bscanregsbd is
signal ltdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable = 0 generate
pado <= coreo;
padoen <= coreoen;
corei <= padi;
tdo <= '0';
ltdi <= (others => '0');
end generate;
engen: if enable /= 0 generate
g: for x in 0 to nsigs-1 generate
r: scanregio
generic map (tech,hzsup)
port map (pado(x),padoen(x),padi(x),coreo(x),coreoen(x),corei(x),
tck,tckn,ltdi(x),ltdi(x+1),bsshft,bscapt,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
ltdi(0) <= tdi;
tdo <= ltdi(nsigs);
end generate;
end;
| gpl-2.0 | 9786ef235aed2b7fe0b63e3a89901471 | 0.600644 | 3.86675 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/example_design/road_exdes.vhd | 1 | 4,312 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: road_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY road_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END road_exdes;
ARCHITECTURE xilinx OF road_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT road IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : road
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | b8006b3544caa5d42a52967ecd2b68c4 | 0.573284 | 4.79644 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_cols_V_channel1.vhd | 2 | 4,636 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_channel1_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel1_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel1 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel1 is
component FIFO_image_filter_p_src_cols_V_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_channel1_shiftReg : FIFO_image_filter_p_src_cols_V_channel1_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 3e6c4614c3e1142733a3a2e41b8fd5ae | 0.540121 | 3.475262 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml50x/leon3mp.vhd | 1 | 39,642 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
use work.pcie.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
clk_33 : in std_ulogic; -- 33 MHz
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(12 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
iic_scl_video : inout std_logic;
iic_sda_video : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(15 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_PCIEXP;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of clk_33_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clk_33_pad : clkpad generic map (tech => padtech)
port map (clk_33, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
-- D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => CFG_BOARD_SELECTION,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
txd2 <= '0'; -- Second UART is unused
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr_ad(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr_ba(1 downto 0), ddr2_ras_n => ddr_rasb,
ddr2_cas_n => ddr_casb, ddr2_we_n => ddr_web,
ddr2_cs_n => ddr_csb(CS_NUM-1 downto 0), ddr2_odt => ddr_odt(0 downto 0),
ddr2_cke => ddr_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr_dqsp(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr_dqsn(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr_clk((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr_clkb((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
led(5) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; led(5) <= '0'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_d, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(
memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_video, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_video, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
gpioi.din(12 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hslvndx => 6,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 10,
paddr => 10,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE)
);
end generate;
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
dapbndx => 13, dapbaddr => 13,dapbirq => 13, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 6, apbndx => 10, apbaddr => 10, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(13),
dahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(6)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 6, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 10, paddr => 10,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10)
);
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(CFG_BOARD_SELECTION),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 9ff3d346a663ae8d824ee1161574e40a | 0.564528 | 3.345034 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/score/example_design/score_prod.vhd | 1 | 9,898 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: score_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : score.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 12000
-- C_READ_DEPTH_A : 12000
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 12000
-- C_READ_DEPTH_B : 12000
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY score_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END score_prod;
ARCHITECTURE xilinx OF score_prod IS
COMPONENT score_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : score_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 5b3df5ff4c9ea845268364fae215b3bd | 0.494342 | 3.837922 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml40x/leon3mp.vhd | 1 | 27,951 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
sysace_clk_in : in std_ulogic; -- System ACE clock
plb_error : out std_logic; -- IU error mode
opb_error : out std_logic; -- DSU active
flash_a23 : out std_ulogic;
sram_flash_addr : out std_logic_vector(22 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(26 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_int_n : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_preserve of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo2.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(21) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 2));
addr23_pad : outpad generic map (tech => padtech)
port map (flash_a23, gnd(0));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
-- phyiconf => 1 = no diff pads for DDR clock pairs
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 27)
port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
gpioi.din(26 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (phy_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 2fbd052333a55779a283ad1fde909ea4 | 0.579443 | 3.411571 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/memory_virtex.vhd | 1 | 13,502 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_virtex.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Memory generators for Xilinx Virtex rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB4 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits <= 32)) generate
r0 : RAMB4_S16_S16 port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if (((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits > 32)) or (abits = 8)) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16 port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8 port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4 port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2 port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1 port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-2.0 | 652f3b522e8d6ebe2db56e37bace8c0b | 0.599911 | 2.942253 | false | false | false | false |
Yuriu5/MiniBlaze | src/hw1/single_port_BRAM.vhd | 1 | 3,251 | -- ************************************************************************************************
-- Project : MiniBlaze
-- Author : B.Lemoine
-- Module : ram_single_port.vhd
-- Date : 07/07/2016
--
-- Description : Single-Port BRAM
-- No-change mode : Data output does not change while new contents are loaded into RAM
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 25/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_single_port is
generic (
ADDR_WIDTH : integer := 15;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
di : in std_logic_vector(DATA_WIDTH-1 downto 0);
do : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end ram_single_port;
architecture behavioral of ram_single_port is
constant SIZE : natural := 2**ADDR_WIDTH;
type ram_type is array (SIZE-1 downto 0) of std_logic_vector (NB_COL*COL_WIDTH-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
process (clk)
begin
if rising_edge(clk) then
if (we = '0') then
do <= RAM(conv_integer(addr));
end if;
if we = '1' then
RAM(conv_integer(addr)) <= di;
end if;
end if;
end process;
end behavioral; | mit | cb16a3a7598ca9159bde53b95e91f9da | 0.514918 | 4.405149 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/libmmu.vhd | 1 | 11,294 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
subtype mmu_gpsz_typ is integer range 0 to 3;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
--# fault, todo: should we flush on a fault?
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
variable pagesize : integer range 0 to 3;
begin
--# merge data
transdata := (others => '0');
pagesize := MMU_getpagesize(mmupgsz, mmctrl);
case pagesize is
when 1 =>
-- 8k
case LVL is
when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 2 =>
-- 16k
case LVL is
when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 3 =>
-- 32k
case LVL is
when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when others =>
-- 4k
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ is
variable pagesize : mmu_gpsz_typ;
begin
if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
else pagesize := mmupgsz; end if;
return pagesize;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
| gpl-2.0 | d22dfca915de50e46ce6c367d01d1fbc | 0.530104 | 3.57179 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/grlfpw_net.vhd | 1 | 37,764 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
strtxii : if (tech = altera) or (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| gpl-2.0 | 120729599b89e0b125c71597e9ae3715 | 0.639524 | 2.594394 | false | false | false | false |
zxcmehran/FPGADisplay-ipcore | hdl/vhdl/ClockMaker.vhd | 1 | 3,341 | --
--
-- FPGA Display Handler IP Core By Mehran Ahadi (http://mehran.ahadi.me)
-- This IP allows you to draw shapes and print texts on VGA screen.
-- Copyright (C) 2015-2016 Mehran Ahadi
-- This work is released under MIT License.
--
-- Display Clock Generator File
--
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM.vhd
-- /___/ /\ Timestamp : 11/27/2014 23:29:17
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st G:\FPGAProject\test10\DCM.xaw G:\FPGAProject\test10\DCM
--Design Name: DCM
--Device: xc2vp30-ff896-7
--
-- Module DCM
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_INST = 0.03 UI
-- Period Jitter (Peak-to-Peak) for block DCM_INST = 1.10 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity ClockMaker is
generic (
multiplier: integer;
divider: integer
);
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end ClockMaker;
architecture BEHAVIORAL of ClockMaker is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
--CLKIN_IBUFG_INST : IBUFG
-- port map (I=>CLKIN_IN,
-- O=>CLKIN_IBUFG);
-- No buffer allowed because CPU itself places a buffer before clock,
-- and it's not allowed to put two buffers in parallel. So, a direct connection would be enough.
CLKIN_IBUFG <= CLKIN_IN;
DCM_INST : DCM
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => divider,
CLKFX_MULTIPLY => multiplier,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| mit | 3f5f1d8208ba981edf39f744fc0196fd | 0.506435 | 3.787982 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 4 | 20,288 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| gpl-3.0 | a0bfd630e65d444a8225ea8c72677623 | 0.426114 | 4.965247 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd | 1 | 16,737 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex6 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml605 is
constant nCS_PER_RANK : integer := 1;
constant BANK_WIDTH : integer := 3;
constant CK_WIDTH : integer := 1;
constant CKE_WIDTH : integer := 1;
constant COL_WIDTH : integer := 10;
constant CS_WIDTH : integer := 1;
constant DM_WIDTH : integer := 8;
constant DQ_WIDTH : integer := 64;
constant DQS_WIDTH : integer := 8;
constant ROW_WIDTH : integer := 13;
constant PAYLOAD_WIDTH : integer := 64;
constant ADDR_WIDTH : integer := 27;
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_mask : std_logic_vector((4*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_end : std_logic;
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_rdy : std_logic;
app_wdf_rdy : std_logic;
app_rd_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component ahb2mig_ml605
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml605.all;
entity ahb2mig_ml605 is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml605 is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 15) of std_logic_vector(31 downto 0);
type wrm is array(0 to 15) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(511 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(3 downto 2) is
when "00" => rdata := r.hrdata(127 downto 0);
when "01" => rdata := r.hrdata(255 downto 128);
when "10" => rdata := r.hrdata(383 downto 256);
when others => rdata := r.hrdata(511 downto 384);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(31 downto 0) & rdata(63 downto 32) & rdata(95 downto 64) & rdata(127 downto 96);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(95 downto 64) & rdata(127 downto 96);
else va.hrdata(63 downto 0) := rdata(31 downto 0) & rdata(63 downto 32); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(3 downto 0) = "0000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(5 downto 2) = "1111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(5 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
ddr_ctrl : process(rst, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(31 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_end : std_ulogic;
variable app_wdf_data : std_logic_vector(255 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000";
app_wdf_wren := '0'; app_wdf_mask := ra.write(7) & ra.write(6) & ra.write(5) &
ra.write(4) & ra.write(3) & ra.write(2) & ra.write(1) & ra.write(0);
app_wdf_data := ra.hwdata(7) & ra.hwdata(6) & ra.hwdata(5) & ra.hwdata(4) &
ra.hwdata(3) & ra.hwdata(2) & ra.hwdata(1) & ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_wdf_end := '0'; v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if startsd = '1' then app_en := '1'; end if;
if (migo.app_rdy and app_en) = '1' then
if ra.acc.hwrite = '0' then v.dstate := dread;
else v.dstate := dwrite; end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 0) := migo.app_rd_data;
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(511 downto 256) := migo.app_rd_data;
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
if migo.app_wdf_rdy = '1' then
v.dstate := whold1;
end if;
when whold1 =>
app_wdf_wren := '1'; app_wdf_end := '1';
app_wdf_mask := ra.write(15) & ra.write(14) & ra.write(13) &
ra.write(12) & ra.write(11) & ra.write(10) & ra.write(9) & ra.write(8);
app_wdf_data := ra.hwdata(15) & ra.hwdata(14) & ra.hwdata(13) & ra.hwdata(12) &
ra.hwdata(11) & ra.hwdata(10) & ra.hwdata(9) & ra.hwdata(8);
if migo.app_wdf_rdy = '1' then
v.startsd := not r.startsd;
v.dstate := midle;
end if;
when others =>
end case;
-- reset
if rst = '0' then
v.startsd := '0';
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_end <= app_wdf_end;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "mig2ahb" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | 1ede42520eb2414e8df9d1d20223f6cb | 0.570174 | 3.279193 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_mul_8ns_25ns_32_3.vhd | 2 | 2,706 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(25 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(25 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(25 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_mul_8ns_25ns_32_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_mul_8ns_25ns_32_3 is
component image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
image_filter_mul_8ns_25ns_32_3_MAC3S_1_U : component image_filter_mul_8ns_25ns_32_3_MAC3S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | 2510863f80145c470d307e0c85e5c654 | 0.551367 | 3.209964 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/stratixii/stratixii_ddr_phy.vhd | 1 | 39,095 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0)
);
END altdqs_stxii;
ARCHITECTURE RTL OF altdqs_stxii IS
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "none";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
SIGNAL dqs_busout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
TYPE periodtype IS ARRAY(10 TO 20) of STRING(1 TO 6);
CONSTANT period : periodtype := (
"9999ps", "9090ps", "8333ps", "7692ps", -- 100-130 MHz
"7143ps", "6667ps", "6250ps", "5882ps", -- 140-170 MHz
"5556ps", "5263ps", "5000ps"); -- 180-200 MHz
FUNCTION buffer_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "high"; ELSE RETURN "low"; END IF;
END buffer_mode;
FUNCTION out_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "delay_chain4";
ELSE RETURN "delay_chain3"; END IF;
END out_mode;
FUNCTION chain_length(MHz : INTEGER) RETURN INTEGER IS
BEGIN
IF MHz > 175 THEN RETURN 16; ELSE RETURN 12; END IF;
END chain_length;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
subtype v4 is std_logic_vector(3 downto 0);
type vv4 is array (width-1 downto 0) of v4;
signal dqslocal : vv4;
signal gnd : std_logic;
BEGIN
gnd <= '0';
dqinclk <= not dqs_busout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => buffer_mode(MHz),
DELAY_CHAIN_LENGTH => chain_length(MHz),
INPUT_FREQUENCY => period(MHz/10),
OFFSETCTRLOUT_MODE => "static",
DELAYCTRLOUT_MODE => "normal",
JITTER_REDUCTION => "false",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => delay_ctrl
);
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "false",
DQS_DELAY_BUFFER_MODE => buffer_mode(MHz),
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period(MHz/10),
DQS_OFFSETCTRL_ENABLE => "false",
DQS_OUT_MODE => out_mode(MHz),
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "true",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 36,
SIM_DQS_INTRINSIC_DELAY => 900,
SIM_DQS_OFFSET_INCREMENT => 0,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
datain => dqs_datain_h(i),
ddiodatain => dqs_datain_l(i),
delayctrlin => delay_ctrl,
dqsbusout => dqs_busout(i),
oe => oe(i),
outclk => outclk(i),
padio => dqs_padio(i)
);
-- clkbuf : global
-- port map (a_in => dqsbusout(i), a_out => dqs_busout(i));
-- dqslocal(i) <= "000" & dqsbusout(i);
-- clkbuf : stratixii_clkctrl generic map (clock_type => "global clock")
-- port map (inclk => dqslocal(i), outclk => dqs_busout(i));
END GENERATE loop0;
END RTL; --altdqs_stxii
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdq_stxii IS
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END altdq_stxii;
ARCHITECTURE RTL OF altdq_stxii IS
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO width-1 GENERATE
dq_ioa : stratixii_io
GENERIC MAP (
DDIO_MODE => "bidir",
DDIOINCLK_INPUT => "negated_inclk",
EXTEND_OE_DISABLE => "false",
-- INCLK_INPUT => "dqs_bus",
INPUT_ASYNC_RESET => "none",
INPUT_POWER_UP => "low",
INPUT_REGISTER_MODE => "register",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register"
)
PORT MAP (
datain => datain_h(i),
ddiodatain => datain_l(i),
ddioregout => dataout_l(i),
inclk => inclock,
oe => oe,
outclk => outclock,
padio => padio(i),
regout => dataout_h(i)
);
END GENERATE loop0;
END RTL; --altdq_stxii
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera;
library altera_mf;
--pragma translate_off
use altera_mf.altpll;
use altera_mf.altddio_out;
use altera_mf.altddio_bidir;
--pragma translate_on
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altdqs_stxii
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk0r, dataout => ddr_csb);
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk0r, dataout => ddr_cke);
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba, datain_l => ba, oe => vcc,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk90r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsnv <= (others => oe);
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
--library stratixii;
use altera_mf.altera_mf_components.all;
--use stratixii.stratixii_pll;
------------------------------------------------------------------
-- STRATIX2 DDR2 PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr2_phy is
signal vcc, gnd : std_logic;
signal ckel, odtl : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_120r, clk_180r, clk_270r : std_ulogic;
signal locked, lockl, vlockl : std_ulogic;
signal clk5 : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal gndv : std_logic_vector (dbits/8-1 downto 0);
signal dqsnv : std_logic_vector (dbits/8-1 downto 0);
signal dqsoe : std_logic_vector (dbits/8-1 downto 0);
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinl : std_logic_vector (dbits*2-1 downto 0);
signal dqoe : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; Mhz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
component altdq_stxii
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
type phasevec is array (1 to 4) of string(1 to 4);
type phasevecarr is array (13 to 20) of phasevec;
constant phasearr : phasevecarr := (
("1923", "2564", "3846", "5769"), -- 130 MHz
("1786", "2381", "3571", "5357"), -- 140 MHz
("1667", "2222", "3333", "5000"), -- 150 MHz
("1562", "2083", "3125", "4687"), -- 160 MHz
("1471", "1961", "2941", "4412"), -- 160 MHz
("1389", "1852", "2778", "4167"), -- 180 MHz
("1316", "1754", "2632", "3947"), -- 190 MHz
("1250", "1667", "2500", "3750")); -- 200 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
begin
clkout <= clk_0r;
vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk4_phase_shift => phasearr(DDR_FREQ/10)(4),
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => clk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_120r, clk(3) => clk_180r,
clk(4) => clk_270r, clk(5) => clk5, locked => lockl);
rstdel : process (clk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(clk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_180r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_180r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
odtl(i) <= odt(i) and locked;
end generate;
dqsreg : process (clk_180r)
begin
if rising_edge(clk_180r) then
dqsoe <= (others => not dqsoen);
dqsnv <= (others => not oen);
end if;
end process;
dqinreg : process (clk_120r)
begin
if rising_edge(clk_120r) then
dqin <= dqinl;
end if;
end process;
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clkb(i));
end generate;
-- Control signal pads
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk_180r, dataout => ddr_cke);
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk_180r, dataout => ddr_csb);
odtpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => odtl, datain_l => odtl, oe => vcc,
outclock => clk_180r, dataout => ddr_odt);
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_web);
bapads : altddio_out generic map (width => 2+eightbanks,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba(1+eightbanks downto 0),
datain_l => ba(1+eightbanks downto 0),
oe => vcc,
outclock => clk_180r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk_180r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk_0r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk_0r, oe => dqsoe, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqoe <= not oen;
dqgen : for i in 0 to dbits/8-1 generate
altdq : altdq_stxii generic map (width => 8)
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i),
outclock => clk_270r, oe => dqoe,
dataout_h => dqinl(i*8+7 downto i*8),
dataout_l => dqinl(i*8+7+dbits downto dbits+i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
-- Data mask
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/4-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk_270r, dataout => ddr_dm
);
end;
| gpl-2.0 | 9322f39ca8100f3a8f8ff2cf65c2508b | 0.580509 | 3.128351 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/game_cores/cl_check.vhd | 1 | 4,399 | --------------------------------------------------------------------------------
--
-- Title : cl_check.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_check is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- vga XoY coordinates:
cnt_yy : in std_logic_vector(2 downto 0); --! counter for Y data
cnt_xx : in std_logic_vector(2 downto 0); --! counter for X data
--data_hide : in std_logic;
display : in std_logic; --! display enable
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_check;
architecture cl_check of cl_check is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="111";
signal comp_yy : std_logic_vector(3 downto 0);
signal comp_xx : std_logic_vector(3 downto 0);
signal data_x, data_y : std_logic;
begin
---------------- stage 1: Get XoY ----------------
y_charz <= y_char(3 downto 0) when rising_edge(clk);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
comp_yy <= '0' & cnt_yy;
comp_xx <= '0' & cnt_xx;
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
---------------- stage 2: Convert XY ----------------
pr_select: process(clk, reset) is
begin
if reset = '0' then
data_x <= '0';
data_y <= '0';
elsif rising_edge(clk) then
if display = '1' then
if (x_in = (xstart + comp_xx)) then
data_x <= '1';
else
data_x <= '0';
end if;
if (y_in = (ystart + comp_yy)) then
data_y <= '1';
else
data_y <= '0';
end if;
else
data_x <= '0';
data_y <= '0';
end if;
end if;
end process;
---------------- stage 3: Data ROM ----------------
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (data_x = '1' and data_y = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FF";
when x"1" => data_rom <= x"81";
when x"2" => data_rom <= x"81";
when x"3" => data_rom <= x"81";
when x"4" => data_rom <= x"81";
when x"5" => data_rom <= x"81";
when x"6" => data_rom <= x"81";
when x"7" => data_rom <= x"81";
when x"8" => data_rom <= x"81";
when x"9" => data_rom <= x"81";
when x"A" => data_rom <= x"81";
when x"B" => data_rom <= x"81";
when x"C" => data_rom <= x"81";
when x"D" => data_rom <= x"83";
when x"E" => data_rom <= x"87";
when others => data_rom <= x"FF";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
---------------- stage 4: RGB DATA ----------------
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_check;
| mit | 61f35ec8c56f88ca0e0b1d8f4d79d3cb | 0.48852 | 2.90363 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/outpad_ds.vhd | 1 | 3,628 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ds
-- File: outpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential output pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of outpad_ds is
signal gnd, oen : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 generate
padp <= i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_outpad_ds generic map (level, slew, voltage) port map (padp, padn, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_outpad_ds port map (padp, padn, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity outpad_dsv is
generic (tech : integer := 0; level : integer := x33v;
voltage : integer := lvds; width : integer := 1;
oepol : integer := 0; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : outpad_ds generic map (tech, level, voltage, oepol, slew)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-2.0 | febcb4b95214ee7eb15a747dca0cdf8d | 0.636714 | 3.512101 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/config.vhd | 1 | 5,552 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | e9d7f836ea9319b3c36f591d13e6449a | 0.644633 | 3.657444 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_FAST_t_opr_core_buf_val_0_V.vhd | 2 | 3,695 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 11;
mem_size : integer := 1927
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of image_filter_FAST_t_opr_core_buf_val_0_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1)) := d1;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 1927;
AddressWidth : INTEGER := 11);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_FAST_t_opr_core_buf_val_0_V is
component image_filter_FAST_t_opr_core_buf_val_0_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC);
end component;
begin
image_filter_FAST_t_opr_core_buf_val_0_V_ram_U : component image_filter_FAST_t_opr_core_buf_val_0_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1);
end architecture;
| gpl-3.0 | 7ed242ee52b53bd3a19b0633dfcde4b7 | 0.546143 | 3.386801 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/digit/example_design/digit_exdes.vhd | 1 | 4,318 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: digit_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY digit_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END digit_exdes;
ARCHITECTURE xilinx OF digit_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT digit IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : digit
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 81fd49c7bcb31d9922b8e91efde3ae6f | 0.573877 | 4.835386 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-pci-xc5v/testbench.vhd | 1 | 17,854 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := '1';
pci_66 : in std_logic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_logic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
-- GRUSB_DCL test signals
signal ddelay : std_ulogic := '0';
signal dstart : std_ulogic := '0';
signal drw : std_ulogic;
signal daddr : std_logic_vector(31 downto 0);
signal dlen : std_logic_vector(14 downto 0);
signal ddi : grusb_dcl_debug_data;
signal ddone : std_ulogic;
signal ddo : grusb_dcl_debug_data;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
eth_macclk <= not eth_macclk after 4 ns;
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1,
txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd, erx_dv, erx_er,
erx_col, erx_crs, emdintn, etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn,
usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn
);
-- optional sdram
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_MCTRL_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 1)
port map(rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
usbdevsim: if (CFG_GRUSBDC = 1) generate
u0: grusbdcsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir);
end generate usbdevsim;
usb_dclsim: if (CFG_GRUSB_DCL = 1) generate
u0: grusb_dclsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
ddelay, dstart, drw, daddr, dlen, ddi, ddone, ddo);
usb_dcl_proc : process
begin
wait for 10 ns;
Print("GRUSB_DCL test started");
wait until rising_edge(ddone);
-- Write 128 bytes to memory
daddr <= X"40000000";
dlen <= conv_std_logic_vector(32,15);
for i in 0 to 127 loop
ddi(i) <= conv_std_logic_vector(i+8,8);
end loop; -- i
grusb_dcl_write(usb_clkout, drw, dstart, ddone);
-- Read back written data
grusb_dcl_read(usb_clkout, drw, dstart, ddone);
-- Compare data
for i in 0 to 127 loop
if ddo(i) /= ddi(i) then
Print("ERROR: Data mismatch using GRUSB_DCL");
end if;
end loop;
Print("GRUSB_DCL test finished");
wait;
end process;
end generate usb_dclsim;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | cf627bad567721dffff6a4f6bf89e35b | 0.576565 | 3.076684 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ambatest/ahbtbp.vhd | 1 | 37,009 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
| gpl-2.0 | 44da056b0c868a2e0529e1c7cfa4c816 | 0.52544 | 3.83871 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-vc707/sgmii_vc707.vhd | 1 | 24,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.net.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_vc707 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
autonegotiation : integer := 1
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
button : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_vc707;
architecture top_level of sgmii_vc707 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii
port(
-- Transceiver Interface
------------------------
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
cplllock : out std_logic;
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
rxoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
rxuserclk : in std_logic; -- 125MHz clock.
rxuserclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
mmcm_locked : in std_logic; -- Locked signal from MMCM
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
--CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
--CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
--CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
--CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
--CLKOUT3_USE_FINE_PS : boolean := FALSE;
--CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
--CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
--CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
--CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
--SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component BUFGMUX -----
component BUFGMUX
generic (
CLK_SEL_TYPE : string := "ASYNC"
);
port (
O : out std_ulogic := '0';
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic := '0'
);
end component;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal rxoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
signal rxuserclk : std_logic;
signal rxuserclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
signal gmii_txd_int : std_logic_vector(7 downto 0);
signal gmii_tx_en_int : std_logic;
signal gmii_tx_er_int : std_logic;
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
begin
-----------------------------------------------------------------------------
-- Default for VC707
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1 or button = '1') else "00000";
--an_adv_config_vector <= x"4001";
--an_adv_config_vector <= "0000000000100001";
an_adv_config_vector <= "0001100000000001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= status_vector_apb;
gmiii.gtx_clk <= userclk2;
gmiii.tx_clk <= userclk2;
gmiii.rx_clk <= userclk2;
gmii_txd <= gmiio.txd;
gmii_tx_en <= gmiio.tx_en;
gmii_tx_er <= gmiio.tx_er;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
gmiii.rmii_clk <= sgmii_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk,
ODIV2 => open
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
--CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
--CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
--CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
--CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_rxuserclk: BUFG
port map (
I => rxoutclk,
O => rxuserclk
);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii
port map (
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
resetdone => resetdone,
cplllock => OPEN ,
txoutclk => txoutclk,
rxoutclk => rxoutclk ,
userclk => userclk,
userclk2 => userclk2,
rxuserclk => rxuserclk ,
rxuserclk2 => rxuserclk ,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
mmcm_locked => mmcm_locked,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect,
gt0_qplloutclk_in => '0',
gt0_qplloutrefclk_in => '0'
);
-----------------------------------------------------------------------------
-- SGMII clock logic
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
sgmii_clk_int <= sgmii_clk_r;
end if;
end process;
bufgmux_sgmiiclk: BUFGMUX
generic map ("ASYNC")
port map (
O => sgmii_clk,
I0 => userclk2,
I1 => sgmii_clk_int,
S => speed_is_10_100
);
-----------------------------------------------------------------------------
-- Extra registers to ease IOB placement
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
status_vector <= status_vector_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
end top_level;
| gpl-2.0 | c6498a7ea83e42ec7a679861c4b3dc09 | 0.461811 | 4.279346 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_FAST_t_opr.vhd | 2 | 486,243 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_FAST_t_opr is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_full_n : IN STD_LOGIC;
p_mask_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_FAST_t_opr is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st39_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_6 : STD_LOGIC_VECTOR (10 downto 0) := "00000000110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv9_14 : STD_LOGIC_VECTOR (8 downto 0) := "000010100";
constant ap_const_lv9_1EC : STD_LOGIC_VECTOR (8 downto 0) := "111101100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv4_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv8_14 : STD_LOGIC_VECTOR (7 downto 0) := "00010100";
constant ap_const_lv32_FFFFFFEC : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111101100";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_2_reg_515 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it1 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_48 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal exitcond_reg_5147 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_5156 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_61 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal or_cond4_reg_5201 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppstg_p_2_reg_515_pp0_it2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it3 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it5 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it6 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it7 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it8 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it9 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it10 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it11 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it12 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it13 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it14 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it15 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it16 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it17 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it18 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it19 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it20 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it21 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it22 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it23 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it24 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it25 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it26 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it27 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it28 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it29 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it30 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it31 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_782_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_reg_5098 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_180 : BOOLEAN;
signal tmp_15_fu_786_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_15_reg_5103 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_fu_790_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_reg_5108 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_fu_796_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_reg_5113 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond1_fu_802_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_196 : BOOLEAN;
signal i_V_fu_807_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_5122 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_7_fu_813_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_5127 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_5132 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_5137 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_fu_840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_reg_5142 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_851_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal j_V_reg_5151 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_addr_reg_5161 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_addr_reg_5167 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_addr_reg_5173 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_addr_reg_5179 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_addr_reg_5185 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_addr_reg_5191 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond1_fu_883_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond1_reg_5197 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal win_val_0_V_2_1_reg_5205 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_3_reg_5210 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_3_reg_5215 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_3_reg_5220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_3_reg_5225 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_3_reg_5230 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_2_reg_5235 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_fu_1252_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal lhs_V_reg_5240 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_1260_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_reg_5252 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp1_fu_1278_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp1_reg_5261 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_20_fu_1286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_5266 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_s_fu_1296_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_s_reg_5271 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_1_fu_1314_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_1_reg_5280 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_fu_1322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_5285 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_2_fu_1332_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_2_reg_5290 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_2_fu_1350_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_2_reg_5299 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_fu_1358_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_5304 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_3_fu_1368_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_3_reg_5309 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_3_fu_1386_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_3_reg_5318 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_fu_1394_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_5323 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_4_fu_1404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_4_reg_5328 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_4_fu_1410_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_4_reg_5337 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_fu_1416_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_reg_5343 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_1426_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_5_reg_5348 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_5_fu_1432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_5_reg_5357 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_fu_1438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_reg_5363 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_6_fu_1448_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_6_reg_5368 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_6_fu_1454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_6_reg_5377 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_fu_1460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_reg_5383 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_7_fu_1470_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_7_reg_5388 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_7_fu_1476_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_7_reg_5397 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_fu_1482_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_reg_5403 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_fu_1516_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_reg_5408 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_s_fu_1521_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_s_reg_5417 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_fu_1539_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_reg_5422 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_23_fu_1547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_5427 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_1_fu_1557_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_1_reg_5432 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_1_fu_1568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_1_reg_5441 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_fu_1574_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_reg_5447 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_2_fu_1584_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_2_reg_5452 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_2_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_2_reg_5461 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_fu_1601_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_reg_5467 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_3_fu_1611_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_3_reg_5472 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_fu_1626_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_reg_5483 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_fu_1654_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_reg_5494 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_fu_1682_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_reg_5505 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_fu_1710_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_reg_5516 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_13_fu_1726_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_13_reg_5527 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_39_fu_1740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_39_reg_5532 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_fu_1746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_reg_5537 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_fu_1764_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_reg_5543 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_fu_1782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_reg_5548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_fu_1800_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_reg_5553 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_fu_1818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_reg_5559 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_fu_1824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_reg_5566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_fu_1830_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_reg_5572 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_fu_1836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_reg_5578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_fu_1842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_reg_5584 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_0_op_op87_op_fu_1848_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_0_op_op87_op_reg_5590 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_fu_1856_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_reg_5595 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_40_fu_1864_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_40_reg_5600 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_fu_1870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_reg_5605 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_fu_1876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_reg_5610 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_fu_1882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_reg_5615 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_fu_1888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_reg_5620 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_3_fu_1930_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_3_reg_5625 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_fu_1962_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_reg_5631 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_4_fu_1970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_4_reg_5638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_fu_1975_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_reg_5644 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_fu_1980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_reg_5649 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_fu_1985_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_reg_5655 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_1990_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_5660 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_6_fu_2036_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_6_reg_5665 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond10_fu_2055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond10_reg_5670 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_7_fu_2061_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_7_reg_5675 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond11_fu_2075_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond11_reg_5681 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_fu_2081_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_reg_5687 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_fu_2087_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_reg_5693 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_fu_2093_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_reg_5699 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_fu_2097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_reg_5704 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_10_fu_2131_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_10_reg_5709 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_fu_2163_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_reg_5715 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_7_fu_2171_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_7_reg_5722 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_fu_2176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_reg_5728 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_fu_2186_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_reg_5733 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_fu_2251_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_reg_5738 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_9_fu_2257_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_9_reg_5743 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond3_demorgan_fu_2286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_demorgan_reg_5748 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_s_fu_2292_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_s_reg_5753 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond14_fu_2310_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond14_reg_5759 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_fu_2316_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_reg_5764 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_fu_2322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_reg_5769 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_fu_2328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_reg_5775 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_2334_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_reg_5781 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp5_reg_5781_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_fu_2391_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_reg_5786 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_fu_2435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_reg_5791 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_fu_2464_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_reg_5796 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_fu_2470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_reg_5801 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_fu_2476_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_3_reg_5806 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond17_fu_2494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond17_reg_5811 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_fu_2500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_reg_5816 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_fu_2511_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_reg_5821 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_fu_2516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_reg_5827 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_fu_2581_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_reg_5832 : STD_LOGIC_VECTOR (0 downto 0);
signal count_3_fu_2594_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_3_reg_5837 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_fu_2600_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_reg_5842 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp4_fu_2606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_5847 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_2610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_reg_5852 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_2614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_reg_5857 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_fu_2653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_reg_5862 : STD_LOGIC_VECTOR (0 downto 0);
signal count_4_fu_2666_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_4_reg_5867 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_fu_2678_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_reg_5872 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp3_fu_2689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_5878 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_2694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_reg_5883 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp12_reg_5883_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_fu_2725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_reg_5888 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_fu_2743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_reg_5893 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_14_fu_2755_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_14_reg_5898 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp13_fu_2762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_reg_5904 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_fu_2787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_reg_5909 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_fu_2805_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_reg_5914 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_fu_2817_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_reg_5919 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_fu_2822_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_reg_5924 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_2828_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_5929 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_2833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_5934 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp11_reg_5934_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_2837_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_reg_5939 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_2861_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_reg_5944 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_fu_2870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_reg_5949 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_1_reg_5953 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_1_reg_5959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_7_reg_5965 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_7_reg_5971 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_fu_3031_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_reg_5977 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_fu_3045_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_1_reg_5987 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_1_reg_5993 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_5_reg_5999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_5_reg_6005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_fu_3143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_reg_6011 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_9_reg_6017 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_9_reg_6023 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_1_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_1_reg_6036 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_fu_3262_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_43_reg_6043 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_fu_3268_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_reg_6048 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_3_reg_6053 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_3_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_7_reg_6065 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_7_reg_6071 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_fu_3434_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_reg_6077 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_fu_3447_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_6083 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_3454_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_48_reg_6088 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_fu_3473_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_reg_6093 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_3486_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_3493_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_reg_6104 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_2_fu_3497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_2_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_3_reg_6115 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_3_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_fu_3505_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_fu_3517_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_fu_3529_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_fu_3541_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_fu_3554_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_fu_3568_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_fu_3582_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_fu_3596_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_fu_3609_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_fu_3621_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_fu_3633_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_fu_3645_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_1_fu_3666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_1_reg_6195 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_s_fu_3680_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_s_reg_6200 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_1_fu_3686_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_1_reg_6206 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_s_fu_3713_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_s_reg_6211 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_1_fu_3725_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_1_reg_6217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_3732_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_57_reg_6222 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_s_fu_3754_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_s_reg_6227 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_1_fu_3766_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_1_reg_6233 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_3773_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_83_reg_6238 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_4_fu_3777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_4_reg_6243 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_5_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_5_reg_6256 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_fu_3788_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_tmp_232_1_reg_6263 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_2_fu_3794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_2_reg_6269 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_239_1_fu_3808_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_239_1_reg_6274 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_2_fu_3814_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_2_reg_6280 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_fu_3841_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_reg_6285 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_2_fu_3853_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_2_reg_6291 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_fu_3860_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_59_reg_6296 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_2_fu_3882_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_reg_6301 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_2_fu_3894_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_2_reg_6307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_3901_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_reg_6312 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_6_fu_3905_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_7_reg_6323 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_7_reg_6330 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_fu_3916_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_tmp_232_2_reg_6337 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_3_fu_3922_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_3_reg_6343 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_tmp_239_2_fu_3936_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_tmp_239_2_reg_6348 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_3_fu_3942_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_3_reg_6354 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_fu_3969_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_reg_6359 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_3_fu_3981_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_3_reg_6365 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_3988_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_61_reg_6370 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_3_fu_4010_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_reg_6375 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_3_fu_4022_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_3_reg_6381 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_4029_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_reg_6386 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_8_fu_4033_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_8_reg_6391 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_9_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_9_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_fu_4044_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_tmp_232_3_reg_6411 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_4_fu_4050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_4_reg_6417 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_tmp_239_3_fu_4064_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_tmp_239_3_reg_6422 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_4_fu_4070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_4_reg_6428 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_fu_4097_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_reg_6433 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_4_fu_4109_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_4_reg_6439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_4116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_63_reg_6444 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_4_fu_4138_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_reg_6449 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_4_fu_4150_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_4_reg_6455 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_89_fu_4157_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_89_reg_6460 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_s_fu_4161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_s_reg_6465 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_s_reg_6471 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_s_reg_6478 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_fu_4172_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_tmp_232_4_reg_6485 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_5_fu_4178_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_5_reg_6491 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_tmp_239_4_fu_4192_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_tmp_239_4_reg_6496 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_5_fu_4198_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_5_reg_6502 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_fu_4225_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_reg_6507 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_5_fu_4237_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_5_reg_6513 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_4244_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_reg_6518 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_5_fu_4266_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_reg_6523 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_5_fu_4278_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_5_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_4285_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_91_reg_6534 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_11_fu_4289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_11_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_1_reg_6545 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_1_reg_6552 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_fu_4300_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_tmp_232_5_reg_6559 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_6_fu_4306_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_6_reg_6565 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_tmp_239_5_fu_4320_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_tmp_239_5_reg_6570 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_6_fu_4326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_6_reg_6576 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_fu_4353_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_reg_6581 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_6_fu_4365_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_6_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_4372_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_reg_6592 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_6_fu_4394_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_reg_6597 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_6_fu_4406_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_6_reg_6603 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_fu_4413_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_reg_6608 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_13_fu_4417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_13_reg_6613 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_2_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_2_reg_6626 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_fu_4428_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_tmp_232_6_reg_6633 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_7_fu_4434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_7_reg_6639 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_tmp_239_6_fu_4448_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_tmp_239_6_reg_6644 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_7_fu_4454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_7_reg_6650 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_fu_4481_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_reg_6655 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_7_fu_4493_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_7_reg_6661 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_4500_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_reg_6666 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_7_fu_4522_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_7_reg_6671 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_7_fu_4534_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_7_reg_6676 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_4541_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_95_reg_6681 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_4545_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_reg_6686 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_fu_4557_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_reg_6691 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_4571_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_reg_6697 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_addr_reg_6702 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_addr_reg_6708 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_v_fu_4593_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_100_v_reg_6714 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_53_fu_4600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_reg_6719 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal core_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_load_reg_6724 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_load_reg_6729 : STD_LOGIC_VECTOR (7 downto 0);
signal phitmp2_fu_4606_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp19_fu_4701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_6739 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_4712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_reg_6744 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_4723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_reg_6749 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_4735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_reg_6754 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce0 : STD_LOGIC;
signal k_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce1 : STD_LOGIC;
signal k_buf_val_0_V_we1 : STD_LOGIC;
signal k_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce0 : STD_LOGIC;
signal k_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce1 : STD_LOGIC;
signal k_buf_val_1_V_we1 : STD_LOGIC;
signal k_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce0 : STD_LOGIC;
signal k_buf_val_2_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce1 : STD_LOGIC;
signal k_buf_val_2_V_we1 : STD_LOGIC;
signal k_buf_val_2_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce0 : STD_LOGIC;
signal k_buf_val_3_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce1 : STD_LOGIC;
signal k_buf_val_3_V_we1 : STD_LOGIC;
signal k_buf_val_3_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce0 : STD_LOGIC;
signal k_buf_val_4_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce1 : STD_LOGIC;
signal k_buf_val_4_V_we1 : STD_LOGIC;
signal k_buf_val_4_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce0 : STD_LOGIC;
signal k_buf_val_5_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce1 : STD_LOGIC;
signal k_buf_val_5_V_we1 : STD_LOGIC;
signal k_buf_val_5_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce0 : STD_LOGIC;
signal core_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce1 : STD_LOGIC;
signal core_buf_val_0_V_we1 : STD_LOGIC;
signal core_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce0 : STD_LOGIC;
signal core_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce1 : STD_LOGIC;
signal core_buf_val_1_V_we1 : STD_LOGIC;
signal core_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_reg_int_s_fu_542_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_547_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_552_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_557_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_562_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_567_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_572_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_577_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_582_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_587_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_592_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_597_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_602_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_607_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_612_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_617_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_622_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_627_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_632_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_637_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_642_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_647_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_652_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_657_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_662_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_667_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_672_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_677_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_682_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_687_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_692_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_697_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_702_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_707_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_712_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_717_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_722_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_727_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_732_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_737_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_742_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_747_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_752_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_757_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_762_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_767_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_772_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_777_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_ce : STD_LOGIC;
signal p_s_reg_504 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st39_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_2075 : BOOLEAN;
signal p_2_phi_fu_519_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it0 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it7 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it8 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it9 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it11 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it12 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it13 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it14 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it15 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it16 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it17 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it18 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it19 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it20 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it21 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it22 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it23 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it24 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it25 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it26 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it27 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it28 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it29 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it30 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it31 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it32 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it33 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it34 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_12_fu_867_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_4577_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal win_val_6_V_5_fu_132 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_0_V_0_fu_136 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_1_fu_140 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_2_fu_4620_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_4_fu_144 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_1_V_0_fu_148 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_1_fu_152 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_2_fu_4623_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_3_fu_156 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_0_fu_160 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_fu_164 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_2_fu_4643_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_0_V_2_3_fu_168 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_2_fu_172 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_3_fu_176 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_4_fu_180 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_5_fu_184 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_3_fu_188 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_fu_192 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_2_fu_196 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_3_fu_200 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_fu_204 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_5_fu_208 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_3_fu_212 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_fu_216 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_1_fu_220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_2_fu_224 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_3_fu_228 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_4_fu_232 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_fu_236 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_3_fu_240 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_fu_244 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_1_fu_248 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_fu_252 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_3_fu_256 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_4_fu_260 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_5_fu_264 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_3_fu_268 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_fu_272 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_1_fu_276 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_2_fu_280 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_3_fu_284 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_4_fu_288 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_fu_292 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_3_fu_296 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_fu_300 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_2_fu_304 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_3_fu_308 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_fu_312 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_5_fu_316 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_3_fu_320 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_fu_324 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_2_fu_4635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_830_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_877_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_97_fu_888_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal icmp1_fu_898_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_fu_1256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_18_fu_1266_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_1272_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_s_fu_1292_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_1_fu_1302_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_1_fu_1308_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_2_fu_1328_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_2_fu_1338_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_2_fu_1344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_3_fu_1364_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_3_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_3_fu_1380_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_4_fu_1400_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_5_fu_1422_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_6_fu_1444_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_7_fu_1466_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_fu_1512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_1527_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_1533_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_1_1_fu_1553_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_2_fu_1580_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_3_fu_1607_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_4_fu_1622_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_1638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_4_fu_1631_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_5_fu_1650_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_1666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_5_fu_1659_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_6_fu_1678_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_fu_1694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_6_fu_1687_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_7_fu_1706_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_fu_1722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_7_fu_1715_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_1_fu_1562_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_0_not_fu_1734_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_2_fu_1589_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_1_fu_1758_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_1_not_fu_1752_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_4_fu_1616_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_2_fu_1776_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_not_fu_1770_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_6_fu_1642_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_3_fu_1794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_3_not_fu_1788_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_8_fu_1670_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_4_fu_1812_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_4_not_fu_1806_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_11_fu_1698_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_25_fu_1907_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_1_fu_1900_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_28_fu_1926_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_2_fu_1919_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_3_fu_1938_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_3_fu_1943_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_1956_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_3_fu_1948_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_41_fu_2010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp42_op_cast_cast_cast_fu_2003_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_2_op_op_fu_1998_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond3_fu_1994_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_42_fu_2030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp3_cast_cast_cast_fu_2022_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_4_op_fu_2014_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_2_s_fu_1894_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_7_fu_2049_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_7_not_fu_2044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_9_fu_1911_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_8_fu_2069_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_2108_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_4_fu_2101_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_34_fu_2127_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_5_fu_2120_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_6_fu_2139_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_6_fu_2144_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_2157_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_6_fu_2149_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_185_7_fu_2181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_8_fu_2197_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_8_fu_2202_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond1_fu_2213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp4_fu_2208_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_8_fu_2224_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond2_demorgan_fu_2241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_9_fu_2235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond2_fu_2245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond12_fu_2231_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_s_fu_2265_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_s_fu_2269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond13_fu_2274_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp5_fu_2280_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_1_7_fu_2112_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_1_fu_2300_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_8_fu_2305_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_7_fu_2191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_8_fu_2218_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_38_fu_2347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_7_fu_2340_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal count_s_fu_2359_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_s_fu_2364_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_fu_2370_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_1_fu_2381_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_fu_2386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_1_fu_2397_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_fu_2407_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond12_demorgan_fu_2425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_2_fu_2413_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond12_fu_2429_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond15_fu_2403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp6_fu_2419_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_181_3_fu_2449_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_11_fu_2453_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_2_fu_2441_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond16_fu_2458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_14_fu_2351_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_4_fu_2484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_12_fu_2489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_fu_2506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_s_fu_2375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_fu_2521_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_cast_fu_2531_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal count_2_fu_2534_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_4_fu_2540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_fu_2552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp7_fu_2546_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_4_fu_2563_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_5_fu_2570_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond15_fu_2576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_5_fu_2587_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_3_fu_2526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_4_fu_2557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_6_fu_2620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond5_fu_2625_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_10_fu_2636_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_10_fu_2642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_fu_2648_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_11_fu_2659_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp9_fu_2672_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp7_fu_2685_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_6_fu_2630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_11_fu_2699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_fu_2704_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_12_fu_2715_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_fu_2720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_13_fu_2731_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_5_fu_2737_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp10_fu_2749_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_10_fu_2709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_fu_2767_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_14_fu_2777_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_fu_2782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_15_fu_2793_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_6_fu_2799_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp_fu_2811_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_12_fu_2772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_14_fu_2842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_15_fu_2846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_2850_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_2856_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_2866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_1_fu_2875_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_1_fu_2879_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_1_fu_2890_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_1_fu_2894_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_3_fu_2905_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_3_fu_2909_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_3_fu_2920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_3_fu_2924_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_5_fu_2935_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_5_fu_2939_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_5_fu_2950_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_5_fu_2954_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_7_fu_2965_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_7_fu_2969_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_7_fu_2980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_7_fu_2984_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_1_fu_2995_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_1_fu_3010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_3_fu_3025_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_3_fu_3039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_5_fu_3053_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_5_fu_3068_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_9_fu_3083_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_9_fu_3087_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_9_fu_3098_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_9_fu_3102_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_199_1_fu_3113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_1_fu_3128_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_s_fu_3146_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_s_fu_3150_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_s_fu_3161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_s_fu_3165_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_2_fu_3176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_2_fu_3180_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_2_fu_3191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_2_fu_3195_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_4_fu_3206_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_4_fu_3210_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_4_fu_3221_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_4_fu_3225_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_7_fu_3236_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_7_fu_3249_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_9_fu_3277_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_9_fu_3290_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_s_fu_3303_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_s_fu_3318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_2_fu_3333_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_2_fu_3348_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_4_fu_3363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_4_fu_3376_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_3_fu_3389_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_3_fu_3404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_0_flag_d_assign_load_5_fu_3419_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_3428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_44_fu_3424_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_9_fu_3274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_3442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_68_fu_3458_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_3467_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_80_fu_3463_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_3481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_5_fu_3500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_5_fu_3512_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_7_fu_3524_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_7_fu_3536_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_9_fu_3548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_9_fu_3562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_s_fu_3576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_s_fu_3590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_2_fu_3604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_2_fu_3616_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_4_fu_3628_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_4_fu_3640_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_3655_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_fu_3672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_3675_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_1_fu_3698_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_1_fu_3707_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_3703_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_10_fu_3692_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_1_fu_3720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_1_fu_3739_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_cast_fu_3736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_1_fu_3748_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_82_fu_3744_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_1_fu_3761_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_cast_fu_3780_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_1_fu_3783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_50_fu_3800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_1_fu_3803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_2_fu_3826_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_cast_fu_3823_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_2_fu_3835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_3831_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_12_fu_3820_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_2_fu_3848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_2_fu_3867_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_1_cast_fu_3864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_2_fu_3876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_84_fu_3872_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_2_fu_3889_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_cast_fu_3908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_2_fu_3911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_cast_fu_3928_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_2_fu_3931_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_3_fu_3954_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_cast_fu_3951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_3_fu_3963_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_3959_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_14_fu_3948_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_3_fu_3976_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_3_fu_3995_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_2_tmp_239_2_cast_fu_3992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_3_fu_4004_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_86_fu_4000_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_3_fu_4017_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_cast_fu_4036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_3_fu_4039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_cast_fu_4056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_3_fu_4059_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_4_fu_4082_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_cast_fu_4079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_4_fu_4091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_4087_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_1_fu_4076_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_4_fu_4104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_4_fu_4123_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_3_tmp_239_3_cast_fu_4120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_4_fu_4132_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_88_fu_4128_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_4_fu_4145_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_cast_fu_4164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_4_fu_4167_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_cast_fu_4184_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_4_fu_4187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_5_fu_4210_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_cast_fu_4207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_5_fu_4219_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_4215_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_3_fu_4204_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_5_fu_4232_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_5_fu_4251_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_4_tmp_239_4_cast_fu_4248_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_5_fu_4260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_90_fu_4256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_5_fu_4273_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_cast_fu_4292_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_5_fu_4295_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_cast_fu_4312_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_5_fu_4315_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_6_fu_4338_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_cast_fu_4335_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_6_fu_4347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_4343_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_5_fu_4332_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_6_fu_4360_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_6_fu_4379_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_5_tmp_239_5_cast_fu_4376_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_6_fu_4388_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_92_fu_4384_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_6_fu_4401_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_cast_fu_4420_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_6_fu_4423_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_cast_fu_4440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_6_fu_4443_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_7_fu_4466_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_cast_fu_4463_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_7_fu_4475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_77_fu_4471_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_7_fu_4460_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_7_fu_4488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_7_fu_4507_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_6_tmp_239_6_cast_fu_4504_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_7_fu_4516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_94_fu_4512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_7_fu_4529_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_cast_fu_4549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_7_fu_4552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_7_cast_fu_4563_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_7_fu_4566_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_4583_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_51_fu_4588_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_4647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_73_fu_4653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_1_fu_4659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_4706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_74_fu_4671_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_1_fu_4677_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_4717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_2_fu_4665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_4695_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_4689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_4729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_2_fu_4683_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_4775_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_4771_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_4779_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_bdd_2152 : BOOLEAN;
signal ap_sig_bdd_250 : BOOLEAN;
signal ap_sig_bdd_2159 : BOOLEAN;
signal ap_sig_bdd_2108 : BOOLEAN;
signal ap_sig_bdd_2156 : BOOLEAN;
signal ap_sig_bdd_1776 : BOOLEAN;
component image_filter_reg_int_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component image_filter_FAST_t_opr_core_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_val_0_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_0_V_address0,
ce0 => k_buf_val_0_V_ce0,
q0 => k_buf_val_0_V_q0,
address1 => k_buf_val_0_V_address1,
ce1 => k_buf_val_0_V_ce1,
we1 => k_buf_val_0_V_we1,
d1 => k_buf_val_0_V_d1);
k_buf_val_1_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_1_V_address0,
ce0 => k_buf_val_1_V_ce0,
q0 => k_buf_val_1_V_q0,
address1 => k_buf_val_1_V_address1,
ce1 => k_buf_val_1_V_ce1,
we1 => k_buf_val_1_V_we1,
d1 => k_buf_val_1_V_d1);
k_buf_val_2_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_2_V_address0,
ce0 => k_buf_val_2_V_ce0,
q0 => k_buf_val_2_V_q0,
address1 => k_buf_val_2_V_address1,
ce1 => k_buf_val_2_V_ce1,
we1 => k_buf_val_2_V_we1,
d1 => k_buf_val_2_V_d1);
k_buf_val_3_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_3_V_address0,
ce0 => k_buf_val_3_V_ce0,
q0 => k_buf_val_3_V_q0,
address1 => k_buf_val_3_V_address1,
ce1 => k_buf_val_3_V_ce1,
we1 => k_buf_val_3_V_we1,
d1 => k_buf_val_3_V_d1);
k_buf_val_4_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_4_V_address0,
ce0 => k_buf_val_4_V_ce0,
q0 => k_buf_val_4_V_q0,
address1 => k_buf_val_4_V_address1,
ce1 => k_buf_val_4_V_ce1,
we1 => k_buf_val_4_V_we1,
d1 => k_buf_val_4_V_d1);
k_buf_val_5_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_5_V_address0,
ce0 => k_buf_val_5_V_ce0,
q0 => k_buf_val_5_V_q0,
address1 => k_buf_val_5_V_address1,
ce1 => k_buf_val_5_V_ce1,
we1 => k_buf_val_5_V_we1,
d1 => k_buf_val_5_V_d1);
core_buf_val_0_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_0_V_address0,
ce0 => core_buf_val_0_V_ce0,
q0 => core_buf_val_0_V_q0,
address1 => core_buf_val_0_V_address1,
ce1 => core_buf_val_0_V_ce1,
we1 => core_buf_val_0_V_we1,
d1 => core_buf_val_0_V_d1);
core_buf_val_1_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_1_V_address0,
ce0 => core_buf_val_1_V_ce0,
q0 => core_buf_val_1_V_q0,
address1 => core_buf_val_1_V_address1,
ce1 => core_buf_val_1_V_ce1,
we1 => core_buf_val_1_V_we1,
d1 => core_buf_val_1_V_d1);
grp_image_filter_reg_int_s_fu_542 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_542_in_r,
ap_return => grp_image_filter_reg_int_s_fu_542_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_542_ap_ce);
grp_image_filter_reg_int_s_fu_547 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_547_in_r,
ap_return => grp_image_filter_reg_int_s_fu_547_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_547_ap_ce);
grp_image_filter_reg_int_s_fu_552 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_552_in_r,
ap_return => grp_image_filter_reg_int_s_fu_552_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_552_ap_ce);
grp_image_filter_reg_int_s_fu_557 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_557_in_r,
ap_return => grp_image_filter_reg_int_s_fu_557_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_557_ap_ce);
grp_image_filter_reg_int_s_fu_562 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_562_in_r,
ap_return => grp_image_filter_reg_int_s_fu_562_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_562_ap_ce);
grp_image_filter_reg_int_s_fu_567 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_567_in_r,
ap_return => grp_image_filter_reg_int_s_fu_567_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_567_ap_ce);
grp_image_filter_reg_int_s_fu_572 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_572_in_r,
ap_return => grp_image_filter_reg_int_s_fu_572_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_572_ap_ce);
grp_image_filter_reg_int_s_fu_577 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_577_in_r,
ap_return => grp_image_filter_reg_int_s_fu_577_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_577_ap_ce);
grp_image_filter_reg_int_s_fu_582 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_582_in_r,
ap_return => grp_image_filter_reg_int_s_fu_582_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_582_ap_ce);
grp_image_filter_reg_int_s_fu_587 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_587_in_r,
ap_return => grp_image_filter_reg_int_s_fu_587_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_587_ap_ce);
grp_image_filter_reg_int_s_fu_592 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_592_in_r,
ap_return => grp_image_filter_reg_int_s_fu_592_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_592_ap_ce);
grp_image_filter_reg_int_s_fu_597 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_597_in_r,
ap_return => grp_image_filter_reg_int_s_fu_597_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_597_ap_ce);
grp_image_filter_reg_int_s_fu_602 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_602_in_r,
ap_return => grp_image_filter_reg_int_s_fu_602_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_602_ap_ce);
grp_image_filter_reg_int_s_fu_607 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_607_in_r,
ap_return => grp_image_filter_reg_int_s_fu_607_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_607_ap_ce);
grp_image_filter_reg_int_s_fu_612 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_612_in_r,
ap_return => grp_image_filter_reg_int_s_fu_612_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_612_ap_ce);
grp_image_filter_reg_int_s_fu_617 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_617_in_r,
ap_return => grp_image_filter_reg_int_s_fu_617_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_617_ap_ce);
grp_image_filter_reg_int_s_fu_622 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_622_in_r,
ap_return => grp_image_filter_reg_int_s_fu_622_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_622_ap_ce);
grp_image_filter_reg_int_s_fu_627 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_627_in_r,
ap_return => grp_image_filter_reg_int_s_fu_627_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_627_ap_ce);
grp_image_filter_reg_int_s_fu_632 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_632_in_r,
ap_return => grp_image_filter_reg_int_s_fu_632_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_632_ap_ce);
grp_image_filter_reg_int_s_fu_637 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_637_in_r,
ap_return => grp_image_filter_reg_int_s_fu_637_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_637_ap_ce);
grp_image_filter_reg_int_s_fu_642 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_642_in_r,
ap_return => grp_image_filter_reg_int_s_fu_642_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_642_ap_ce);
grp_image_filter_reg_int_s_fu_647 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_647_in_r,
ap_return => grp_image_filter_reg_int_s_fu_647_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_647_ap_ce);
grp_image_filter_reg_int_s_fu_652 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_652_in_r,
ap_return => grp_image_filter_reg_int_s_fu_652_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_652_ap_ce);
grp_image_filter_reg_int_s_fu_657 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_657_in_r,
ap_return => grp_image_filter_reg_int_s_fu_657_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_657_ap_ce);
grp_image_filter_reg_int_s_fu_662 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_662_in_r,
ap_return => grp_image_filter_reg_int_s_fu_662_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_662_ap_ce);
grp_image_filter_reg_int_s_fu_667 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_667_in_r,
ap_return => grp_image_filter_reg_int_s_fu_667_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_667_ap_ce);
grp_image_filter_reg_int_s_fu_672 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_672_in_r,
ap_return => grp_image_filter_reg_int_s_fu_672_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_672_ap_ce);
grp_image_filter_reg_int_s_fu_677 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_677_in_r,
ap_return => grp_image_filter_reg_int_s_fu_677_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_677_ap_ce);
grp_image_filter_reg_int_s_fu_682 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_682_in_r,
ap_return => grp_image_filter_reg_int_s_fu_682_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_682_ap_ce);
grp_image_filter_reg_int_s_fu_687 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_687_in_r,
ap_return => grp_image_filter_reg_int_s_fu_687_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_687_ap_ce);
grp_image_filter_reg_int_s_fu_692 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_692_in_r,
ap_return => grp_image_filter_reg_int_s_fu_692_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_692_ap_ce);
grp_image_filter_reg_int_s_fu_697 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_697_in_r,
ap_return => grp_image_filter_reg_int_s_fu_697_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_697_ap_ce);
grp_image_filter_reg_int_s_fu_702 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_702_in_r,
ap_return => grp_image_filter_reg_int_s_fu_702_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_702_ap_ce);
grp_image_filter_reg_int_s_fu_707 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_707_in_r,
ap_return => grp_image_filter_reg_int_s_fu_707_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_707_ap_ce);
grp_image_filter_reg_int_s_fu_712 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_712_in_r,
ap_return => grp_image_filter_reg_int_s_fu_712_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_712_ap_ce);
grp_image_filter_reg_int_s_fu_717 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_717_in_r,
ap_return => grp_image_filter_reg_int_s_fu_717_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_717_ap_ce);
grp_image_filter_reg_int_s_fu_722 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_722_in_r,
ap_return => grp_image_filter_reg_int_s_fu_722_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_722_ap_ce);
grp_image_filter_reg_int_s_fu_727 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_727_in_r,
ap_return => grp_image_filter_reg_int_s_fu_727_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_727_ap_ce);
grp_image_filter_reg_int_s_fu_732 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_732_in_r,
ap_return => grp_image_filter_reg_int_s_fu_732_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_732_ap_ce);
grp_image_filter_reg_int_s_fu_737 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_737_in_r,
ap_return => grp_image_filter_reg_int_s_fu_737_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_737_ap_ce);
grp_image_filter_reg_int_s_fu_742 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_742_in_r,
ap_return => grp_image_filter_reg_int_s_fu_742_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_742_ap_ce);
grp_image_filter_reg_int_s_fu_747 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_747_in_r,
ap_return => grp_image_filter_reg_int_s_fu_747_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_747_ap_ce);
grp_image_filter_reg_int_s_fu_752 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_752_in_r,
ap_return => grp_image_filter_reg_int_s_fu_752_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_752_ap_ce);
grp_image_filter_reg_int_s_fu_757 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_757_in_r,
ap_return => grp_image_filter_reg_int_s_fu_757_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_757_ap_ce);
grp_image_filter_reg_int_s_fu_762 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_762_in_r,
ap_return => grp_image_filter_reg_int_s_fu_762_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_762_ap_ce);
grp_image_filter_reg_int_s_fu_767 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_767_in_r,
ap_return => grp_image_filter_reg_int_s_fu_767_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_767_ap_ce);
grp_image_filter_reg_int_s_fu_772 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_772_in_r,
ap_return => grp_image_filter_reg_int_s_fu_772_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_772_ap_ce);
grp_image_filter_reg_int_s_fu_777 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_777_in_r,
ap_return => grp_image_filter_reg_int_s_fu_777_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_777_ap_ce);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_lv1_0 = exitcond_fu_846_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2)) or (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it1 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_250) then
if (ap_sig_bdd_2152) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_reg_phiprechg_core_1_reg_527pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it13 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it13_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_2108) then
if (ap_sig_bdd_2159) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_reg_phiprechg_core_1_reg_527pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it34 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it34_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_1776) then
if (ap_sig_bdd_2156) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= phitmp2_fu_4606_p2;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= ap_reg_phiprechg_core_1_reg_527pp0_it33;
end if;
end if;
end if;
end process;
-- p_2_reg_515 assign process. --
p_2_reg_515_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_2_reg_515 <= j_V_reg_5151;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
p_2_reg_515 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_s_reg_504 assign process. --
p_s_reg_504_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_3)) then
p_s_reg_504 <= i_V_reg_5122;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
p_s_reg_504 <= ap_const_lv11_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))) then
a0_2_reg_6285 <= a0_2_fu_3841_p3;
b0_2_reg_6301 <= b0_2_fu_3882_p3;
tmp_232_2_reg_6291 <= tmp_232_2_fu_3853_p3;
tmp_239_2_reg_6307 <= tmp_239_2_fu_3894_p3;
tmp_59_reg_6296 <= tmp_59_fu_3860_p1;
tmp_85_reg_6312 <= tmp_85_fu_3901_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
a0_2_tmp_232_2_reg_6337 <= a0_2_tmp_232_2_fu_3916_p3;
b0_2_tmp_239_2_reg_6348 <= b0_2_tmp_239_2_fu_3936_p3;
tmp_209_3_reg_6343 <= tmp_209_3_fu_3922_p2;
tmp_221_3_reg_6354 <= tmp_221_3_fu_3942_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))) then
a0_3_reg_6359 <= a0_3_fu_3969_p3;
b0_3_reg_6375 <= b0_3_fu_4010_p3;
tmp_232_3_reg_6365 <= tmp_232_3_fu_3981_p3;
tmp_239_3_reg_6381 <= tmp_239_3_fu_4022_p3;
tmp_61_reg_6370 <= tmp_61_fu_3988_p1;
tmp_87_reg_6386 <= tmp_87_fu_4029_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
a0_3_tmp_232_3_reg_6411 <= a0_3_tmp_232_3_fu_4044_p3;
b0_3_tmp_239_3_reg_6422 <= b0_3_tmp_239_3_fu_4064_p3;
tmp_209_4_reg_6417 <= tmp_209_4_fu_4050_p2;
tmp_221_4_reg_6428 <= tmp_221_4_fu_4070_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))) then
a0_4_reg_6433 <= a0_4_fu_4097_p3;
b0_4_reg_6449 <= b0_4_fu_4138_p3;
tmp_232_4_reg_6439 <= tmp_232_4_fu_4109_p3;
tmp_239_4_reg_6455 <= tmp_239_4_fu_4150_p3;
tmp_63_reg_6444 <= tmp_63_fu_4116_p1;
tmp_89_reg_6460 <= tmp_89_fu_4157_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
a0_4_tmp_232_4_reg_6485 <= a0_4_tmp_232_4_fu_4172_p3;
b0_4_tmp_239_4_reg_6496 <= b0_4_tmp_239_4_fu_4192_p3;
tmp_209_5_reg_6491 <= tmp_209_5_fu_4178_p2;
tmp_221_5_reg_6502 <= tmp_221_5_fu_4198_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))) then
a0_5_reg_6507 <= a0_5_fu_4225_p3;
b0_5_reg_6523 <= b0_5_fu_4266_p3;
tmp_232_5_reg_6513 <= tmp_232_5_fu_4237_p3;
tmp_239_5_reg_6529 <= tmp_239_5_fu_4278_p3;
tmp_65_reg_6518 <= tmp_65_fu_4244_p1;
tmp_91_reg_6534 <= tmp_91_fu_4285_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
a0_5_tmp_232_5_reg_6559 <= a0_5_tmp_232_5_fu_4300_p3;
b0_5_tmp_239_5_reg_6570 <= b0_5_tmp_239_5_fu_4320_p3;
tmp_209_6_reg_6565 <= tmp_209_6_fu_4306_p2;
tmp_221_6_reg_6576 <= tmp_221_6_fu_4326_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))) then
a0_6_reg_6581 <= a0_6_fu_4353_p3;
b0_6_reg_6597 <= b0_6_fu_4394_p3;
tmp_232_6_reg_6587 <= tmp_232_6_fu_4365_p3;
tmp_239_6_reg_6603 <= tmp_239_6_fu_4406_p3;
tmp_75_reg_6592 <= tmp_75_fu_4372_p1;
tmp_93_reg_6608 <= tmp_93_fu_4413_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
a0_6_tmp_232_6_reg_6633 <= a0_6_tmp_232_6_fu_4428_p3;
b0_6_tmp_239_6_reg_6644 <= b0_6_tmp_239_6_fu_4448_p3;
tmp_209_7_reg_6639 <= tmp_209_7_fu_4434_p2;
tmp_221_7_reg_6650 <= tmp_221_7_fu_4454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it29) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29)))) then
a0_7_reg_6655 <= a0_7_fu_4481_p3;
b0_7_reg_6671 <= b0_7_fu_4522_p3;
tmp_232_7_reg_6661 <= tmp_232_7_fu_4493_p3;
tmp_239_7_reg_6676 <= tmp_239_7_fu_4534_p3;
tmp_78_reg_6666 <= tmp_78_fu_4500_p1;
tmp_95_reg_6681 <= tmp_95_fu_4541_p1;
tmp_96_reg_6686 <= tmp_96_fu_4545_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it30) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30)))) then
a0_7_tmp_232_7_reg_6691 <= a0_7_tmp_232_7_fu_4557_p3;
tmp_79_reg_6697 <= tmp_79_fu_4571_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))) then
a0_s_reg_6211 <= a0_s_fu_3713_p3;
b0_s_reg_6227 <= b0_s_fu_3754_p3;
tmp_232_1_reg_6217 <= tmp_232_1_fu_3725_p3;
tmp_239_1_reg_6233 <= tmp_239_1_fu_3766_p3;
tmp_57_reg_6222 <= tmp_57_fu_3732_p1;
tmp_83_reg_6238 <= tmp_83_fu_3773_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
a0_tmp_232_1_reg_6263 <= a0_tmp_232_1_fu_3788_p3;
b0_tmp_239_1_reg_6274 <= b0_tmp_239_1_fu_3808_p3;
tmp_209_2_reg_6269 <= tmp_209_2_fu_3794_p2;
tmp_221_2_reg_6280 <= tmp_221_2_fu_3814_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it10 <= ap_reg_phiprechg_core_1_reg_527pp0_it9;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it11 <= ap_reg_phiprechg_core_1_reg_527pp0_it10;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it12 <= ap_reg_phiprechg_core_1_reg_527pp0_it11;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it14 <= ap_reg_phiprechg_core_1_reg_527pp0_it13;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it15 <= ap_reg_phiprechg_core_1_reg_527pp0_it14;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it15) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it16 <= ap_reg_phiprechg_core_1_reg_527pp0_it15;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it16) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it17 <= ap_reg_phiprechg_core_1_reg_527pp0_it16;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it18 <= ap_reg_phiprechg_core_1_reg_527pp0_it17;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it18) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it19 <= ap_reg_phiprechg_core_1_reg_527pp0_it18;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it2 <= ap_reg_phiprechg_core_1_reg_527pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it19) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it20 <= ap_reg_phiprechg_core_1_reg_527pp0_it19;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it20) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it21 <= ap_reg_phiprechg_core_1_reg_527pp0_it20;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it21) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it22 <= ap_reg_phiprechg_core_1_reg_527pp0_it21;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it22) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it23 <= ap_reg_phiprechg_core_1_reg_527pp0_it22;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it23) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it24 <= ap_reg_phiprechg_core_1_reg_527pp0_it23;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it24) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it25 <= ap_reg_phiprechg_core_1_reg_527pp0_it24;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it25) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it26 <= ap_reg_phiprechg_core_1_reg_527pp0_it25;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it27 <= ap_reg_phiprechg_core_1_reg_527pp0_it26;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it27) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it28 <= ap_reg_phiprechg_core_1_reg_527pp0_it27;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it28) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it29 <= ap_reg_phiprechg_core_1_reg_527pp0_it28;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it3 <= ap_reg_phiprechg_core_1_reg_527pp0_it2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it29) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it30 <= ap_reg_phiprechg_core_1_reg_527pp0_it29;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it30) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it31 <= ap_reg_phiprechg_core_1_reg_527pp0_it30;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it31) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it32 <= ap_reg_phiprechg_core_1_reg_527pp0_it31;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it33 <= ap_reg_phiprechg_core_1_reg_527pp0_it32;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it4 <= ap_reg_phiprechg_core_1_reg_527pp0_it3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it5 <= ap_reg_phiprechg_core_1_reg_527pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it6 <= ap_reg_phiprechg_core_1_reg_527pp0_it5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it7 <= ap_reg_phiprechg_core_1_reg_527pp0_it6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it8 <= ap_reg_phiprechg_core_1_reg_527pp0_it7;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it9 <= ap_reg_phiprechg_core_1_reg_527pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 <= core_buf_val_1_V_addr_reg_6708;
ap_reg_ppstg_exitcond_reg_5147_pp0_it10 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
ap_reg_ppstg_exitcond_reg_5147_pp0_it11 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
ap_reg_ppstg_exitcond_reg_5147_pp0_it12 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
ap_reg_ppstg_exitcond_reg_5147_pp0_it13 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
ap_reg_ppstg_exitcond_reg_5147_pp0_it14 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
ap_reg_ppstg_exitcond_reg_5147_pp0_it15 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
ap_reg_ppstg_exitcond_reg_5147_pp0_it16 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
ap_reg_ppstg_exitcond_reg_5147_pp0_it17 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
ap_reg_ppstg_exitcond_reg_5147_pp0_it18 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
ap_reg_ppstg_exitcond_reg_5147_pp0_it19 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
ap_reg_ppstg_exitcond_reg_5147_pp0_it2 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
ap_reg_ppstg_exitcond_reg_5147_pp0_it20 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
ap_reg_ppstg_exitcond_reg_5147_pp0_it21 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
ap_reg_ppstg_exitcond_reg_5147_pp0_it22 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
ap_reg_ppstg_exitcond_reg_5147_pp0_it23 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
ap_reg_ppstg_exitcond_reg_5147_pp0_it24 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
ap_reg_ppstg_exitcond_reg_5147_pp0_it25 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
ap_reg_ppstg_exitcond_reg_5147_pp0_it26 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
ap_reg_ppstg_exitcond_reg_5147_pp0_it27 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
ap_reg_ppstg_exitcond_reg_5147_pp0_it28 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
ap_reg_ppstg_exitcond_reg_5147_pp0_it29 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
ap_reg_ppstg_exitcond_reg_5147_pp0_it3 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
ap_reg_ppstg_exitcond_reg_5147_pp0_it30 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
ap_reg_ppstg_exitcond_reg_5147_pp0_it31 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
ap_reg_ppstg_exitcond_reg_5147_pp0_it32 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
ap_reg_ppstg_exitcond_reg_5147_pp0_it33 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
ap_reg_ppstg_exitcond_reg_5147_pp0_it4 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
ap_reg_ppstg_exitcond_reg_5147_pp0_it5 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
ap_reg_ppstg_exitcond_reg_5147_pp0_it6 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
ap_reg_ppstg_exitcond_reg_5147_pp0_it7 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
ap_reg_ppstg_exitcond_reg_5147_pp0_it8 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
ap_reg_ppstg_exitcond_reg_5147_pp0_it9 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 <= flag_d_max2_1_reg_5959;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 <= ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 <= flag_d_max2_7_reg_5971;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 <= flag_d_max4_1_reg_5993;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 <= ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 <= flag_d_max4_5_reg_6005;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 <= ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 <= flag_d_min2_1_reg_5953;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 <= ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 <= flag_d_min2_7_reg_5965;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 <= flag_d_min4_1_reg_5987;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 <= ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 <= flag_d_min4_5_reg_5999;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 <= ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 <= flag_val_V_assign_load_1_s_reg_5417;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 <= ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 <= iscorner_2_i_s_reg_5949;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 <= not_or_cond10_demorgan_reg_5699;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 <= not_or_cond11_demorgan_reg_5704;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 <= not_or_cond6_demorgan_reg_5605;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 <= not_or_cond7_demorgan_reg_5610;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 <= not_or_cond8_demorgan_reg_5615;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 <= not_or_cond9_demorgan_reg_5620;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 <= not_or_cond_reg_5733;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 <= or_cond2_reg_5660;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 <= or_cond5_reg_5537;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 <= or_cond6_reg_5543;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 <= or_cond7_reg_5548;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 <= or_cond8_reg_5553;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 <= or_cond9_reg_5559;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it10 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
ap_reg_ppstg_or_cond_reg_5156_pp0_it11 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
ap_reg_ppstg_or_cond_reg_5156_pp0_it12 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
ap_reg_ppstg_or_cond_reg_5156_pp0_it13 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
ap_reg_ppstg_or_cond_reg_5156_pp0_it14 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
ap_reg_ppstg_or_cond_reg_5156_pp0_it15 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
ap_reg_ppstg_or_cond_reg_5156_pp0_it16 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
ap_reg_ppstg_or_cond_reg_5156_pp0_it17 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
ap_reg_ppstg_or_cond_reg_5156_pp0_it18 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
ap_reg_ppstg_or_cond_reg_5156_pp0_it19 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
ap_reg_ppstg_or_cond_reg_5156_pp0_it2 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
ap_reg_ppstg_or_cond_reg_5156_pp0_it20 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
ap_reg_ppstg_or_cond_reg_5156_pp0_it21 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
ap_reg_ppstg_or_cond_reg_5156_pp0_it22 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
ap_reg_ppstg_or_cond_reg_5156_pp0_it23 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
ap_reg_ppstg_or_cond_reg_5156_pp0_it24 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
ap_reg_ppstg_or_cond_reg_5156_pp0_it25 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
ap_reg_ppstg_or_cond_reg_5156_pp0_it26 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
ap_reg_ppstg_or_cond_reg_5156_pp0_it27 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
ap_reg_ppstg_or_cond_reg_5156_pp0_it28 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
ap_reg_ppstg_or_cond_reg_5156_pp0_it29 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
ap_reg_ppstg_or_cond_reg_5156_pp0_it3 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
ap_reg_ppstg_or_cond_reg_5156_pp0_it30 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
ap_reg_ppstg_or_cond_reg_5156_pp0_it31 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
ap_reg_ppstg_or_cond_reg_5156_pp0_it32 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
ap_reg_ppstg_or_cond_reg_5156_pp0_it33 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
ap_reg_ppstg_or_cond_reg_5156_pp0_it4 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
ap_reg_ppstg_or_cond_reg_5156_pp0_it5 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
ap_reg_ppstg_or_cond_reg_5156_pp0_it6 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
ap_reg_ppstg_or_cond_reg_5156_pp0_it7 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
ap_reg_ppstg_or_cond_reg_5156_pp0_it8 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it9 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
ap_reg_ppstg_p_2_reg_515_pp0_it10 <= ap_reg_ppstg_p_2_reg_515_pp0_it9;
ap_reg_ppstg_p_2_reg_515_pp0_it11 <= ap_reg_ppstg_p_2_reg_515_pp0_it10;
ap_reg_ppstg_p_2_reg_515_pp0_it12 <= ap_reg_ppstg_p_2_reg_515_pp0_it11;
ap_reg_ppstg_p_2_reg_515_pp0_it13 <= ap_reg_ppstg_p_2_reg_515_pp0_it12;
ap_reg_ppstg_p_2_reg_515_pp0_it14 <= ap_reg_ppstg_p_2_reg_515_pp0_it13;
ap_reg_ppstg_p_2_reg_515_pp0_it15 <= ap_reg_ppstg_p_2_reg_515_pp0_it14;
ap_reg_ppstg_p_2_reg_515_pp0_it16 <= ap_reg_ppstg_p_2_reg_515_pp0_it15;
ap_reg_ppstg_p_2_reg_515_pp0_it17 <= ap_reg_ppstg_p_2_reg_515_pp0_it16;
ap_reg_ppstg_p_2_reg_515_pp0_it18 <= ap_reg_ppstg_p_2_reg_515_pp0_it17;
ap_reg_ppstg_p_2_reg_515_pp0_it19 <= ap_reg_ppstg_p_2_reg_515_pp0_it18;
ap_reg_ppstg_p_2_reg_515_pp0_it2 <= ap_reg_ppstg_p_2_reg_515_pp0_it1;
ap_reg_ppstg_p_2_reg_515_pp0_it20 <= ap_reg_ppstg_p_2_reg_515_pp0_it19;
ap_reg_ppstg_p_2_reg_515_pp0_it21 <= ap_reg_ppstg_p_2_reg_515_pp0_it20;
ap_reg_ppstg_p_2_reg_515_pp0_it22 <= ap_reg_ppstg_p_2_reg_515_pp0_it21;
ap_reg_ppstg_p_2_reg_515_pp0_it23 <= ap_reg_ppstg_p_2_reg_515_pp0_it22;
ap_reg_ppstg_p_2_reg_515_pp0_it24 <= ap_reg_ppstg_p_2_reg_515_pp0_it23;
ap_reg_ppstg_p_2_reg_515_pp0_it25 <= ap_reg_ppstg_p_2_reg_515_pp0_it24;
ap_reg_ppstg_p_2_reg_515_pp0_it26 <= ap_reg_ppstg_p_2_reg_515_pp0_it25;
ap_reg_ppstg_p_2_reg_515_pp0_it27 <= ap_reg_ppstg_p_2_reg_515_pp0_it26;
ap_reg_ppstg_p_2_reg_515_pp0_it28 <= ap_reg_ppstg_p_2_reg_515_pp0_it27;
ap_reg_ppstg_p_2_reg_515_pp0_it29 <= ap_reg_ppstg_p_2_reg_515_pp0_it28;
ap_reg_ppstg_p_2_reg_515_pp0_it3 <= ap_reg_ppstg_p_2_reg_515_pp0_it2;
ap_reg_ppstg_p_2_reg_515_pp0_it30 <= ap_reg_ppstg_p_2_reg_515_pp0_it29;
ap_reg_ppstg_p_2_reg_515_pp0_it31 <= ap_reg_ppstg_p_2_reg_515_pp0_it30;
ap_reg_ppstg_p_2_reg_515_pp0_it4 <= ap_reg_ppstg_p_2_reg_515_pp0_it3;
ap_reg_ppstg_p_2_reg_515_pp0_it5 <= ap_reg_ppstg_p_2_reg_515_pp0_it4;
ap_reg_ppstg_p_2_reg_515_pp0_it6 <= ap_reg_ppstg_p_2_reg_515_pp0_it5;
ap_reg_ppstg_p_2_reg_515_pp0_it7 <= ap_reg_ppstg_p_2_reg_515_pp0_it6;
ap_reg_ppstg_p_2_reg_515_pp0_it8 <= ap_reg_ppstg_p_2_reg_515_pp0_it7;
ap_reg_ppstg_p_2_reg_515_pp0_it9 <= ap_reg_ppstg_p_2_reg_515_pp0_it8;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 <= r_V_1_1_reg_5432;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 <= r_V_1_2_reg_5452;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 <= r_V_1_3_reg_5472;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 <= r_V_1_4_reg_5483;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 <= r_V_1_5_reg_5494;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 <= r_V_1_6_reg_5505;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 <= r_V_1_7_reg_5516;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 <= r_V_1_reg_5408;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 <= r_V_2_reg_5290;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 <= r_V_3_reg_5309;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 <= r_V_4_reg_5328;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 <= r_V_5_reg_5348;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 <= r_V_6_reg_5368;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 <= r_V_7_reg_5388;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
ap_reg_ppstg_r_V_reg_5252_pp0_it10 <= ap_reg_ppstg_r_V_reg_5252_pp0_it9;
ap_reg_ppstg_r_V_reg_5252_pp0_it11 <= ap_reg_ppstg_r_V_reg_5252_pp0_it10;
ap_reg_ppstg_r_V_reg_5252_pp0_it12 <= ap_reg_ppstg_r_V_reg_5252_pp0_it11;
ap_reg_ppstg_r_V_reg_5252_pp0_it13 <= ap_reg_ppstg_r_V_reg_5252_pp0_it12;
ap_reg_ppstg_r_V_reg_5252_pp0_it14 <= ap_reg_ppstg_r_V_reg_5252_pp0_it13;
ap_reg_ppstg_r_V_reg_5252_pp0_it3 <= r_V_reg_5252;
ap_reg_ppstg_r_V_reg_5252_pp0_it4 <= ap_reg_ppstg_r_V_reg_5252_pp0_it3;
ap_reg_ppstg_r_V_reg_5252_pp0_it5 <= ap_reg_ppstg_r_V_reg_5252_pp0_it4;
ap_reg_ppstg_r_V_reg_5252_pp0_it6 <= ap_reg_ppstg_r_V_reg_5252_pp0_it5;
ap_reg_ppstg_r_V_reg_5252_pp0_it7 <= ap_reg_ppstg_r_V_reg_5252_pp0_it6;
ap_reg_ppstg_r_V_reg_5252_pp0_it8 <= ap_reg_ppstg_r_V_reg_5252_pp0_it7;
ap_reg_ppstg_r_V_reg_5252_pp0_it9 <= ap_reg_ppstg_r_V_reg_5252_pp0_it8;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 <= r_V_s_reg_5271;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
ap_reg_ppstg_tmp11_reg_5934_pp0_it11 <= tmp11_reg_5934;
ap_reg_ppstg_tmp12_reg_5883_pp0_it9 <= tmp12_reg_5883;
ap_reg_ppstg_tmp3_reg_5878_pp0_it10 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
ap_reg_ppstg_tmp3_reg_5878_pp0_it11 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
ap_reg_ppstg_tmp3_reg_5878_pp0_it9 <= tmp3_reg_5878;
ap_reg_ppstg_tmp5_reg_5781_pp0_it6 <= tmp5_reg_5781;
ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 <= tmp_200_3_reg_5977;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 <= tmp_210_2_reg_6169;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 <= tmp_210_4_reg_6179;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 <= tmp_210_7_reg_6139;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 <= tmp_210_9_reg_6149;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 <= tmp_210_s_reg_6159;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 <= tmp_213_3_reg_5982;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 <= tmp_225_2_reg_6174;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 <= tmp_225_4_reg_6184;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 <= tmp_225_7_reg_6144;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 <= tmp_225_9_reg_6154;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 <= tmp_225_s_reg_6164;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 <= tmp_39_reg_5532;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 <= ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 <= tmp_53_reg_6719;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppstg_exitcond_reg_5147_pp0_it1 <= exitcond_reg_5147;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 <= or_cond1_reg_5197;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 <= or_cond4_reg_5201;
ap_reg_ppstg_or_cond_reg_5156_pp0_it1 <= or_cond_reg_5156;
ap_reg_ppstg_p_2_reg_515_pp0_it1 <= p_2_reg_515;
exitcond_reg_5147 <= exitcond_fu_846_p2;
win_val_0_V_2_1_reg_5205 <= win_val_0_V_2_fu_172;
win_val_1_V_4_3_reg_5210 <= win_val_1_V_4_fu_204;
win_val_2_V_5_3_reg_5215 <= win_val_2_V_5_fu_236;
win_val_3_V_2_3_reg_5220 <= win_val_3_V_2_fu_252;
win_val_4_V_5_3_reg_5225 <= win_val_4_V_5_fu_292;
win_val_5_V_4_3_reg_5230 <= win_val_5_V_4_fu_312;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it15)))) then
b0_reg_6093 <= b0_fu_3473_p3;
p_a_0_flag_d_assign_load_5_reg_6077 <= p_a_0_flag_d_assign_load_5_fu_3434_p3;
tmp_47_reg_6083 <= tmp_47_fu_3447_p3;
tmp_48_reg_6088 <= tmp_48_fu_3454_p1;
tmp_71_reg_6099 <= tmp_71_fu_3486_p3;
tmp_81_reg_6104 <= tmp_81_fu_3493_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
b0_tmp_s_reg_6200 <= b0_tmp_s_fu_3680_p3;
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 <= p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
tmp_209_1_reg_6195 <= tmp_209_1_fu_3666_p2;
tmp_221_1_reg_6206 <= tmp_221_1_fu_3686_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31))) then
core_buf_val_0_V_addr_reg_6702 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_addr_reg_6708 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
tmp_53_reg_6719 <= tmp_53_fu_4600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) then
core_buf_val_0_V_load_reg_6724 <= core_buf_val_0_V_q0;
core_buf_val_1_V_load_reg_6729 <= core_buf_val_1_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
core_win_val_0_V_0_fu_136(0) <= core_win_val_0_V_1_fu_140(0);
core_win_val_0_V_0_fu_136(1) <= core_win_val_0_V_1_fu_140(1);
core_win_val_0_V_0_fu_136(2) <= core_win_val_0_V_1_fu_140(2);
core_win_val_0_V_0_fu_136(3) <= core_win_val_0_V_1_fu_140(3);
core_win_val_0_V_0_fu_136(4) <= core_win_val_0_V_1_fu_140(4);
core_win_val_0_V_0_fu_136(5) <= core_win_val_0_V_1_fu_140(5);
core_win_val_0_V_0_fu_136(6) <= core_win_val_0_V_1_fu_140(6);
core_win_val_0_V_0_fu_136(7) <= core_win_val_0_V_1_fu_140(7);
core_win_val_0_V_1_fu_140(0) <= core_win_val_0_V_2_fu_4620_p1(0);
core_win_val_0_V_1_fu_140(1) <= core_win_val_0_V_2_fu_4620_p1(1);
core_win_val_0_V_1_fu_140(2) <= core_win_val_0_V_2_fu_4620_p1(2);
core_win_val_0_V_1_fu_140(3) <= core_win_val_0_V_2_fu_4620_p1(3);
core_win_val_0_V_1_fu_140(4) <= core_win_val_0_V_2_fu_4620_p1(4);
core_win_val_0_V_1_fu_140(5) <= core_win_val_0_V_2_fu_4620_p1(5);
core_win_val_0_V_1_fu_140(6) <= core_win_val_0_V_2_fu_4620_p1(6);
core_win_val_0_V_1_fu_140(7) <= core_win_val_0_V_2_fu_4620_p1(7);
core_win_val_1_V_0_fu_148(0) <= core_win_val_1_V_1_fu_152(0);
core_win_val_1_V_0_fu_148(1) <= core_win_val_1_V_1_fu_152(1);
core_win_val_1_V_0_fu_148(2) <= core_win_val_1_V_1_fu_152(2);
core_win_val_1_V_0_fu_148(3) <= core_win_val_1_V_1_fu_152(3);
core_win_val_1_V_0_fu_148(4) <= core_win_val_1_V_1_fu_152(4);
core_win_val_1_V_0_fu_148(5) <= core_win_val_1_V_1_fu_152(5);
core_win_val_1_V_0_fu_148(6) <= core_win_val_1_V_1_fu_152(6);
core_win_val_1_V_0_fu_148(7) <= core_win_val_1_V_1_fu_152(7);
core_win_val_1_V_1_fu_152(0) <= core_win_val_1_V_2_fu_4623_p1(0);
core_win_val_1_V_1_fu_152(1) <= core_win_val_1_V_2_fu_4623_p1(1);
core_win_val_1_V_1_fu_152(2) <= core_win_val_1_V_2_fu_4623_p1(2);
core_win_val_1_V_1_fu_152(3) <= core_win_val_1_V_2_fu_4623_p1(3);
core_win_val_1_V_1_fu_152(4) <= core_win_val_1_V_2_fu_4623_p1(4);
core_win_val_1_V_1_fu_152(5) <= core_win_val_1_V_2_fu_4623_p1(5);
core_win_val_1_V_1_fu_152(6) <= core_win_val_1_V_2_fu_4623_p1(6);
core_win_val_1_V_1_fu_152(7) <= core_win_val_1_V_2_fu_4623_p1(7);
core_win_val_2_V_0_fu_160(0) <= core_win_val_2_V_1_fu_164(0);
core_win_val_2_V_0_fu_160(1) <= core_win_val_2_V_1_fu_164(1);
core_win_val_2_V_0_fu_160(2) <= core_win_val_2_V_1_fu_164(2);
core_win_val_2_V_0_fu_160(3) <= core_win_val_2_V_1_fu_164(3);
core_win_val_2_V_0_fu_160(4) <= core_win_val_2_V_1_fu_164(4);
core_win_val_2_V_0_fu_160(5) <= core_win_val_2_V_1_fu_164(5);
core_win_val_2_V_0_fu_160(6) <= core_win_val_2_V_1_fu_164(6);
core_win_val_2_V_0_fu_160(7) <= core_win_val_2_V_1_fu_164(7);
core_win_val_2_V_1_fu_164(0) <= core_win_val_2_V_1_2_fu_4643_p1(0);
core_win_val_2_V_1_fu_164(1) <= core_win_val_2_V_1_2_fu_4643_p1(1);
core_win_val_2_V_1_fu_164(2) <= core_win_val_2_V_1_2_fu_4643_p1(2);
core_win_val_2_V_1_fu_164(3) <= core_win_val_2_V_1_2_fu_4643_p1(3);
core_win_val_2_V_1_fu_164(4) <= core_win_val_2_V_1_2_fu_4643_p1(4);
core_win_val_2_V_1_fu_164(5) <= core_win_val_2_V_1_2_fu_4643_p1(5);
core_win_val_2_V_1_fu_164(6) <= core_win_val_2_V_1_2_fu_4643_p1(6);
core_win_val_2_V_1_fu_164(7) <= core_win_val_2_V_1_2_fu_4643_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it2)))) then
count_1_i_0_op_op87_op_reg_5590(0) <= count_1_i_0_op_op87_op_fu_1848_p3(0);
flag_val_V_assign_load_1_13_reg_5527 <= flag_val_V_assign_load_1_13_fu_1726_p3;
flag_val_V_assign_load_1_s_reg_5417 <= flag_val_V_assign_load_1_s_fu_1521_p3;
not_or_cond6_demorgan_reg_5605 <= not_or_cond6_demorgan_fu_1870_p2;
not_or_cond7_demorgan_reg_5610 <= not_or_cond7_demorgan_fu_1876_p2;
not_or_cond8_demorgan_reg_5615 <= not_or_cond8_demorgan_fu_1882_p2;
not_or_cond9_demorgan_reg_5620 <= not_or_cond9_demorgan_fu_1888_p2;
or_cond5_reg_5537 <= or_cond5_fu_1746_p2;
or_cond6_reg_5543 <= or_cond6_fu_1764_p2;
or_cond7_reg_5548 <= or_cond7_fu_1782_p2;
or_cond8_reg_5553 <= or_cond8_fu_1800_p2;
or_cond9_reg_5559 <= or_cond9_fu_1818_p2;
phitmp3_reg_5422 <= phitmp3_fu_1539_p3;
phitmp43_op_op_cast_cast_cast_reg_5595(0) <= phitmp43_op_op_cast_cast_cast_fu_1856_p3(0);
r_V_1_1_reg_5432 <= r_V_1_1_fu_1557_p2;
r_V_1_2_reg_5452 <= r_V_1_2_fu_1584_p2;
r_V_1_3_reg_5472 <= r_V_1_3_fu_1611_p2;
r_V_1_4_reg_5483 <= r_V_1_4_fu_1626_p2;
r_V_1_5_reg_5494 <= r_V_1_5_fu_1654_p2;
r_V_1_6_reg_5505 <= r_V_1_6_fu_1682_p2;
r_V_1_7_reg_5516 <= r_V_1_7_fu_1710_p2;
r_V_1_reg_5408 <= r_V_1_fu_1516_p2;
tmp_181_5_not_reg_5566 <= tmp_181_5_not_fu_1824_p2;
tmp_181_6_not_reg_5578 <= tmp_181_6_not_fu_1836_p2;
tmp_182_1_reg_5441 <= tmp_182_1_fu_1568_p2;
tmp_182_2_reg_5461 <= tmp_182_2_fu_1595_p2;
tmp_183_5_reg_5572 <= tmp_183_5_fu_1830_p2;
tmp_183_6_reg_5584 <= tmp_183_6_fu_1842_p2;
tmp_184_1_reg_5447 <= tmp_184_1_fu_1574_p2;
tmp_184_2_reg_5467 <= tmp_184_2_fu_1601_p2;
tmp_23_reg_5427 <= tmp_23_fu_1547_p2;
tmp_39_reg_5532 <= tmp_39_fu_1740_p2;
tmp_40_reg_5600 <= tmp_40_fu_1864_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it7) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it7)))) then
count_1_i_12_reg_5872 <= count_1_i_12_fu_2678_p3;
count_4_reg_5867 <= count_4_fu_2666_p2;
p_iscorner_0_i_7_reg_5862 <= p_iscorner_0_i_7_fu_2653_p2;
tmp12_reg_5883 <= tmp12_fu_2694_p2;
tmp3_reg_5878 <= tmp3_fu_2689_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it8) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it8)))) then
count_1_i_14_reg_5898 <= count_1_i_14_fu_2755_p3;
p_iscorner_0_i_11_reg_5888 <= p_iscorner_0_i_11_fu_2725_p2;
tmp13_reg_5904 <= tmp13_fu_2762_p2;
tmp_185_13_reg_5893 <= tmp_185_13_fu_2743_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it5) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it5)))) then
count_1_i_3_reg_5806 <= count_1_i_3_fu_2476_p3;
not_or_cond13_demorgan_reg_5801 <= not_or_cond13_demorgan_fu_2470_p2;
not_or_cond14_demorgan_reg_5816 <= not_or_cond14_demorgan_fu_2500_p2;
or_cond17_reg_5811 <= or_cond17_fu_2494_p2;
or_cond18_reg_5821 <= or_cond18_fu_2511_p2;
p_iscorner_0_i_1_reg_5786 <= p_iscorner_0_i_1_fu_2391_p2;
p_iscorner_0_i_2_reg_5791 <= p_iscorner_0_i_2_fu_2435_p2;
tmp6_reg_5827 <= tmp6_fu_2516_p2;
tmp_185_3_reg_5796 <= tmp_185_3_fu_2464_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it3) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it3)))) then
count_1_i_6_reg_5665 <= count_1_i_6_fu_2036_p3;
count_1_i_7_reg_5675 <= count_1_i_7_fu_2061_p3;
flag_val_V_assign_load_1_3_reg_5625 <= flag_val_V_assign_load_1_3_fu_1930_p3;
flag_val_V_assign_load_1_5_reg_5631 <= flag_val_V_assign_load_1_5_fu_1962_p3;
not_or_cond10_demorgan_reg_5699 <= not_or_cond10_demorgan_fu_2093_p2;
not_or_cond11_demorgan_reg_5704 <= not_or_cond11_demorgan_fu_2097_p2;
or_cond10_reg_5670 <= or_cond10_fu_2055_p2;
or_cond11_reg_5681 <= or_cond11_fu_2075_p2;
or_cond2_reg_5660 <= or_cond2_fu_1990_p2;
tmp_181_9_reg_5687 <= tmp_181_9_fu_2081_p2;
tmp_182_4_reg_5638 <= tmp_182_4_fu_1970_p2;
tmp_182_5_reg_5649 <= tmp_182_5_fu_1980_p2;
tmp_183_9_reg_5693 <= tmp_183_9_fu_2087_p2;
tmp_184_4_reg_5644 <= tmp_184_4_fu_1975_p2;
tmp_184_5_reg_5655 <= tmp_184_5_fu_1985_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it4) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it4)))) then
count_1_i_9_reg_5743 <= count_1_i_9_fu_2257_p3;
count_1_i_s_reg_5753 <= count_1_i_s_fu_2292_p3;
flag_val_V_assign_load_1_10_reg_5709 <= flag_val_V_assign_load_1_10_fu_2131_p3;
flag_val_V_assign_load_1_12_reg_5715 <= flag_val_V_assign_load_1_12_fu_2163_p3;
not_or_cond3_demorgan_reg_5748 <= not_or_cond3_demorgan_fu_2286_p2;
not_or_cond4_demorgan_reg_5764 <= not_or_cond4_demorgan_fu_2316_p2;
not_or_cond_reg_5733 <= not_or_cond_fu_2186_p2;
or_cond14_reg_5759 <= or_cond14_fu_2310_p2;
p_iscorner_0_i_9_reg_5738 <= p_iscorner_0_i_9_fu_2251_p2;
tmp5_reg_5781 <= tmp5_fu_2334_p2;
tmp_181_2_reg_5769 <= tmp_181_2_fu_2322_p2;
tmp_182_7_reg_5722 <= tmp_182_7_fu_2171_p2;
tmp_183_10_reg_5775 <= tmp_183_10_fu_2328_p2;
tmp_184_7_reg_5728 <= tmp_184_7_fu_2176_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)))) then
count_3_reg_5837 <= count_3_fu_2594_p2;
p_iscorner_0_i_5_reg_5832 <= p_iscorner_0_i_5_fu_2581_p2;
tmp4_reg_5847 <= tmp4_fu_2606_p2;
tmp8_reg_5852 <= tmp8_fu_2610_p2;
tmp9_reg_5857 <= tmp9_fu_2614_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)))) then
flag_d_assign_11_reg_6539 <= flag_d_assign_11_fu_4289_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)))) then
flag_d_assign_13_reg_6613 <= flag_d_assign_13_fu_4417_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)))) then
flag_d_assign_2_reg_6109 <= flag_d_assign_2_fu_3497_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)))) then
flag_d_assign_4_reg_6243 <= flag_d_assign_4_fu_3777_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)))) then
flag_d_assign_6_reg_6317 <= flag_d_assign_6_fu_3905_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)))) then
flag_d_assign_8_reg_6391 <= flag_d_assign_8_fu_4033_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)))) then
flag_d_assign_reg_6011 <= flag_d_assign_fu_3143_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)))) then
flag_d_assign_s_reg_6465 <= flag_d_assign_s_fu_4161_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949)))) then
flag_d_max2_1_reg_5959 <= grp_image_filter_reg_int_s_fu_547_ap_return;
flag_d_max2_7_reg_5971 <= grp_image_filter_reg_int_s_fu_577_ap_return;
flag_d_min2_1_reg_5953 <= grp_image_filter_reg_int_s_fu_542_ap_return;
flag_d_min2_7_reg_5965 <= grp_image_filter_reg_int_s_fu_572_ap_return;
tmp_200_3_reg_5977 <= tmp_200_3_fu_3031_p3;
tmp_213_3_reg_5982 <= tmp_213_3_fu_3045_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
flag_d_max2_9_reg_6023 <= grp_image_filter_reg_int_s_fu_607_ap_return;
flag_d_max8_1_reg_6036 <= grp_image_filter_reg_int_s_fu_617_ap_return;
flag_d_min2_9_reg_6017 <= grp_image_filter_reg_int_s_fu_602_ap_return;
flag_d_min8_1_reg_6029 <= grp_image_filter_reg_int_s_fu_612_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))) then
flag_d_max4_1_reg_5993 <= grp_image_filter_reg_int_s_fu_587_ap_return;
flag_d_max4_5_reg_6005 <= grp_image_filter_reg_int_s_fu_597_ap_return;
flag_d_min4_1_reg_5987 <= grp_image_filter_reg_int_s_fu_582_ap_return;
flag_d_min4_5_reg_5999 <= grp_image_filter_reg_int_s_fu_592_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))) then
flag_d_max4_3_reg_6059 <= grp_image_filter_reg_int_s_fu_657_ap_return;
flag_d_max4_7_reg_6071 <= grp_image_filter_reg_int_s_fu_667_ap_return;
flag_d_min4_3_reg_6053 <= grp_image_filter_reg_int_s_fu_652_ap_return;
flag_d_min4_7_reg_6065 <= grp_image_filter_reg_int_s_fu_662_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
flag_d_max8_3_reg_6122 <= grp_image_filter_reg_int_s_fu_717_ap_return;
flag_d_min8_3_reg_6115 <= grp_image_filter_reg_int_s_fu_712_ap_return;
tmp_210_2_reg_6169 <= tmp_210_2_fu_3609_p3;
tmp_210_4_reg_6179 <= tmp_210_4_fu_3633_p3;
tmp_210_5_reg_6129 <= tmp_210_5_fu_3505_p3;
tmp_210_7_reg_6139 <= tmp_210_7_fu_3529_p3;
tmp_210_9_reg_6149 <= tmp_210_9_fu_3554_p3;
tmp_210_s_reg_6159 <= tmp_210_s_fu_3582_p3;
tmp_225_2_reg_6174 <= tmp_225_2_fu_3621_p3;
tmp_225_4_reg_6184 <= tmp_225_4_fu_3645_p3;
tmp_225_5_reg_6134 <= tmp_225_5_fu_3517_p3;
tmp_225_7_reg_6144 <= tmp_225_7_fu_3541_p3;
tmp_225_9_reg_6154 <= tmp_225_9_fu_3568_p3;
tmp_225_s_reg_6164 <= tmp_225_s_fu_3596_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
flag_d_max8_5_reg_6256 <= grp_image_filter_reg_int_s_fu_727_ap_return;
flag_d_min8_5_reg_6249 <= grp_image_filter_reg_int_s_fu_722_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
flag_d_max8_7_reg_6330 <= grp_image_filter_reg_int_s_fu_737_ap_return;
flag_d_min8_7_reg_6323 <= grp_image_filter_reg_int_s_fu_732_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
flag_d_max8_9_reg_6404 <= grp_image_filter_reg_int_s_fu_747_ap_return;
flag_d_min8_9_reg_6397 <= grp_image_filter_reg_int_s_fu_742_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_5122 <= i_V_fu_807_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
icmp_reg_5142 <= icmp_fu_840_p2;
tmp_7_reg_5127 <= tmp_7_fu_813_p2;
tmp_8_reg_5132 <= tmp_8_fu_818_p2;
tmp_9_reg_5137 <= tmp_9_fu_824_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)))) then
iscorner_2_i_s_reg_5949 <= iscorner_2_i_s_fu_2870_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
j_V_reg_5151 <= j_V_fu_851_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2) and not((ap_const_lv1_0 = or_cond_fu_862_p2)))) then
k_buf_val_0_V_addr_reg_5161 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_addr_reg_5167 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_addr_reg_5173 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_addr_reg_5179 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_addr_reg_5185 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_addr_reg_5191 <= tmp_12_fu_867_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it1)))) then
lhs_V_reg_5240(0) <= lhs_V_fu_1252_p1(0);
lhs_V_reg_5240(1) <= lhs_V_fu_1252_p1(1);
lhs_V_reg_5240(2) <= lhs_V_fu_1252_p1(2);
lhs_V_reg_5240(3) <= lhs_V_fu_1252_p1(3);
lhs_V_reg_5240(4) <= lhs_V_fu_1252_p1(4);
lhs_V_reg_5240(5) <= lhs_V_fu_1252_p1(5);
lhs_V_reg_5240(6) <= lhs_V_fu_1252_p1(6);
lhs_V_reg_5240(7) <= lhs_V_fu_1252_p1(7);
phitmp1_reg_5261 <= phitmp1_fu_1278_p3;
phitmp_1_reg_5280 <= phitmp_1_fu_1314_p3;
phitmp_2_reg_5299 <= phitmp_2_fu_1350_p3;
phitmp_3_reg_5318 <= phitmp_3_fu_1386_p3;
r_V_2_reg_5290 <= r_V_2_fu_1332_p2;
r_V_3_reg_5309 <= r_V_3_fu_1368_p2;
r_V_4_reg_5328 <= r_V_4_fu_1404_p2;
r_V_5_reg_5348 <= r_V_5_fu_1426_p2;
r_V_6_reg_5368 <= r_V_6_fu_1448_p2;
r_V_7_reg_5388 <= r_V_7_fu_1470_p2;
r_V_reg_5252 <= r_V_fu_1260_p2;
r_V_s_reg_5271 <= r_V_s_fu_1296_p2;
tmp_176_4_reg_5337 <= tmp_176_4_fu_1410_p2;
tmp_176_5_reg_5357 <= tmp_176_5_fu_1432_p2;
tmp_176_6_reg_5377 <= tmp_176_6_fu_1454_p2;
tmp_176_7_reg_5397 <= tmp_176_7_fu_1476_p2;
tmp_177_4_reg_5343 <= tmp_177_4_fu_1416_p2;
tmp_177_5_reg_5363 <= tmp_177_5_fu_1438_p2;
tmp_177_6_reg_5383 <= tmp_177_6_fu_1460_p2;
tmp_177_7_reg_5403 <= tmp_177_7_fu_1482_p2;
tmp_20_reg_5266 <= tmp_20_fu_1286_p2;
tmp_24_reg_5285 <= tmp_24_fu_1322_p2;
tmp_27_reg_5304 <= tmp_27_fu_1358_p2;
tmp_29_reg_5323 <= tmp_29_fu_1394_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it9) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it9)))) then
not_or_cond11_reg_5919 <= not_or_cond11_fu_2817_p2;
p_iscorner_0_i_13_reg_5909 <= p_iscorner_0_i_13_fu_2787_p2;
tmp11_reg_5934 <= tmp11_fu_2833_p2;
tmp15_reg_5939 <= tmp15_fu_2837_p2;
tmp2_reg_5929 <= tmp2_fu_2828_p2;
tmp_185_15_reg_5914 <= tmp_185_15_fu_2805_p2;
tmp_185_16_reg_5924 <= tmp_185_16_fu_2822_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2))) then
or_cond1_reg_5197 <= or_cond1_fu_883_p2;
or_cond4_reg_5201 <= or_cond4_fu_904_p2;
or_cond_reg_5156 <= or_cond_fu_862_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond5_reg_5537_pp0_it6))) then
phitmp8_reg_5842 <= phitmp8_fu_2600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it10) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it10)))) then
tmp14_reg_5944 <= tmp14_fu_2861_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
tmp19_reg_6739 <= tmp19_fu_4701_p2;
tmp20_reg_6744 <= tmp20_fu_4712_p2;
tmp23_reg_6749 <= tmp23_fu_4723_p2;
tmp25_reg_6754 <= tmp25_fu_4735_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31)))) then
tmp_100_v_reg_6714 <= tmp_100_v_fu_4593_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
tmp_15_reg_5103 <= tmp_15_fu_786_p1;
tmp_5_reg_5113 <= tmp_5_fu_796_p2;
tmp_reg_5098 <= tmp_fu_782_p1;
tmp_s_reg_5108 <= tmp_s_fu_790_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
tmp_211_1_reg_6545 <= grp_image_filter_reg_int_s_fu_762_ap_return;
tmp_226_1_reg_6552 <= grp_image_filter_reg_int_s_fu_767_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
tmp_211_2_reg_6619 <= grp_image_filter_reg_int_s_fu_772_ap_return;
tmp_226_2_reg_6626 <= grp_image_filter_reg_int_s_fu_777_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
tmp_211_s_reg_6471 <= grp_image_filter_reg_int_s_fu_752_ap_return;
tmp_226_s_reg_6478 <= grp_image_filter_reg_int_s_fu_757_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
tmp_43_reg_6043 <= tmp_43_fu_3262_p2;
tmp_67_reg_6048 <= tmp_67_fu_3268_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it1)))) then
win_val_0_V_2_3_fu_168 <= win_val_0_V_2_1_reg_5205;
win_val_1_V_1_3_fu_188 <= win_val_1_V_1_fu_192;
win_val_1_V_1_fu_192 <= win_val_1_V_2_fu_196;
win_val_1_V_2_fu_196 <= win_val_1_V_3_fu_200;
win_val_1_V_3_fu_200 <= win_val_1_V_4_3_reg_5210;
win_val_2_V_0_3_fu_212 <= win_val_2_V_0_fu_216;
win_val_2_V_0_fu_216 <= win_val_2_V_1_fu_220;
win_val_2_V_1_fu_220 <= win_val_2_V_2_fu_224;
win_val_2_V_2_fu_224 <= win_val_2_V_3_fu_228;
win_val_2_V_3_fu_228 <= win_val_2_V_4_fu_232;
win_val_2_V_4_fu_232 <= win_val_2_V_5_3_reg_5215;
win_val_3_V_0_3_fu_240 <= win_val_3_V_0_fu_244;
win_val_3_V_0_fu_244 <= win_val_3_V_1_fu_248;
win_val_3_V_1_fu_248 <= win_val_3_V_2_3_reg_5220;
win_val_4_V_0_3_fu_268 <= win_val_4_V_0_fu_272;
win_val_4_V_0_fu_272 <= win_val_4_V_1_fu_276;
win_val_4_V_1_fu_276 <= win_val_4_V_2_fu_280;
win_val_4_V_2_fu_280 <= win_val_4_V_3_fu_284;
win_val_4_V_3_fu_284 <= win_val_4_V_4_fu_288;
win_val_4_V_4_fu_288 <= win_val_4_V_5_3_reg_5225;
win_val_5_V_1_3_fu_296 <= win_val_5_V_1_fu_300;
win_val_5_V_1_fu_300 <= win_val_5_V_2_fu_304;
win_val_5_V_2_fu_304 <= win_val_5_V_3_fu_308;
win_val_5_V_3_fu_308 <= win_val_5_V_4_3_reg_5230;
win_val_6_V_2_3_fu_320 <= win_val_6_V_2_fu_324;
win_val_6_V_2_fu_324 <= win_val_6_V_2_2_reg_5235;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_0_V_2_fu_172 <= win_val_0_V_3_fu_176;
win_val_0_V_3_fu_176 <= win_val_0_V_4_fu_180;
win_val_0_V_4_fu_180 <= win_val_0_V_5_fu_184;
win_val_0_V_5_fu_184 <= k_buf_val_0_V_q0;
win_val_1_V_4_fu_204 <= win_val_1_V_5_fu_208;
win_val_1_V_5_fu_208 <= k_buf_val_1_V_q0;
win_val_2_V_5_fu_236 <= k_buf_val_2_V_q0;
win_val_3_V_2_fu_252 <= win_val_3_V_3_fu_256;
win_val_3_V_3_fu_256 <= win_val_3_V_4_fu_260;
win_val_3_V_4_fu_260 <= win_val_3_V_5_fu_264;
win_val_3_V_5_fu_264 <= k_buf_val_3_V_q0;
win_val_4_V_5_fu_292 <= k_buf_val_4_V_q0;
win_val_5_V_4_fu_312 <= win_val_5_V_5_fu_316;
win_val_5_V_5_fu_316 <= k_buf_val_5_V_q0;
win_val_6_V_3_fu_156 <= win_val_6_V_4_fu_144;
win_val_6_V_4_fu_144 <= win_val_6_V_5_fu_132;
win_val_6_V_5_fu_132 <= p_src_data_stream_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_6_V_2_2_reg_5235 <= win_val_6_V_3_fu_156;
end if;
end if;
end process;
lhs_V_reg_5240(8) <= '0';
count_1_i_0_op_op87_op_reg_5590(3 downto 1) <= "100";
phitmp43_op_op_cast_cast_cast_reg_5595(3 downto 1) <= "011";
core_win_val_0_V_0_fu_136(15 downto 8) <= "00000000";
core_win_val_0_V_1_fu_140(15 downto 8) <= "00000000";
core_win_val_1_V_0_fu_148(15 downto 8) <= "00000000";
core_win_val_1_V_1_fu_152(15 downto 8) <= "00000000";
core_win_val_2_V_0_fu_160(15 downto 8) <= "00000000";
core_win_val_2_V_1_fu_164(15 downto 8) <= "00000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_sig_bdd_180, exitcond1_fu_802_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_180)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33)))) then
ap_NS_fsm <= ap_ST_st39_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st39_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a0_2_cast_fu_3908_p1 <= std_logic_vector(resize(unsigned(a0_2_reg_6285),32));
a0_2_fu_3841_p3 <=
a0_tmp_232_1_reg_6263 when (tmp_217_2_fu_3835_p2(0) = '1') else
tmp_58_fu_3831_p1;
a0_2_tmp_232_2_cast_fu_3951_p1 <= std_logic_vector(resize(unsigned(a0_2_tmp_232_2_reg_6337),32));
a0_2_tmp_232_2_fu_3916_p3 <=
a0_2_reg_6285 when (tmp_233_2_fu_3911_p2(0) = '1') else
tmp_59_reg_6296;
a0_3_cast_fu_4036_p1 <= std_logic_vector(resize(unsigned(a0_3_reg_6359),32));
a0_3_fu_3969_p3 <=
a0_2_tmp_232_2_reg_6337 when (tmp_217_3_fu_3963_p2(0) = '1') else
tmp_60_fu_3959_p1;
a0_3_tmp_232_3_cast_fu_4079_p1 <= std_logic_vector(resize(unsigned(a0_3_tmp_232_3_reg_6411),32));
a0_3_tmp_232_3_fu_4044_p3 <=
a0_3_reg_6359 when (tmp_233_3_fu_4039_p2(0) = '1') else
tmp_61_reg_6370;
a0_4_cast_fu_4164_p1 <= std_logic_vector(resize(unsigned(a0_4_reg_6433),32));
a0_4_fu_4097_p3 <=
a0_3_tmp_232_3_reg_6411 when (tmp_217_4_fu_4091_p2(0) = '1') else
tmp_62_fu_4087_p1;
a0_4_tmp_232_4_cast_fu_4207_p1 <= std_logic_vector(resize(unsigned(a0_4_tmp_232_4_reg_6485),32));
a0_4_tmp_232_4_fu_4172_p3 <=
a0_4_reg_6433 when (tmp_233_4_fu_4167_p2(0) = '1') else
tmp_63_reg_6444;
a0_5_cast_fu_4292_p1 <= std_logic_vector(resize(unsigned(a0_5_reg_6507),32));
a0_5_fu_4225_p3 <=
a0_4_tmp_232_4_reg_6485 when (tmp_217_5_fu_4219_p2(0) = '1') else
tmp_64_fu_4215_p1;
a0_5_tmp_232_5_cast_fu_4335_p1 <= std_logic_vector(resize(unsigned(a0_5_tmp_232_5_reg_6559),32));
a0_5_tmp_232_5_fu_4300_p3 <=
a0_5_reg_6507 when (tmp_233_5_fu_4295_p2(0) = '1') else
tmp_65_reg_6518;
a0_6_cast_fu_4420_p1 <= std_logic_vector(resize(unsigned(a0_6_reg_6581),32));
a0_6_fu_4353_p3 <=
a0_5_tmp_232_5_reg_6559 when (tmp_217_6_fu_4347_p2(0) = '1') else
tmp_66_fu_4343_p1;
a0_6_tmp_232_6_cast_fu_4463_p1 <= std_logic_vector(resize(unsigned(a0_6_tmp_232_6_reg_6633),32));
a0_6_tmp_232_6_fu_4428_p3 <=
a0_6_reg_6581 when (tmp_233_6_fu_4423_p2(0) = '1') else
tmp_75_reg_6592;
a0_7_cast_fu_4549_p1 <= std_logic_vector(resize(unsigned(a0_7_reg_6655),32));
a0_7_fu_4481_p3 <=
a0_6_tmp_232_6_reg_6633 when (tmp_217_7_fu_4475_p2(0) = '1') else
tmp_77_fu_4471_p1;
a0_7_tmp_232_7_fu_4557_p3 <=
a0_7_reg_6655 when (tmp_233_7_fu_4552_p2(0) = '1') else
tmp_78_reg_6666;
a0_cast_fu_3780_p1 <= std_logic_vector(resize(unsigned(a0_s_reg_6211),32));
a0_s_fu_3713_p3 <=
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 when (tmp_217_1_fu_3707_p2(0) = '1') else
tmp_56_fu_3703_p1;
a0_tmp_232_1_cast_fu_3823_p1 <= std_logic_vector(resize(unsigned(a0_tmp_232_1_reg_6263),32));
a0_tmp_232_1_fu_3788_p3 <=
a0_s_reg_6211 when (tmp_233_1_fu_3783_p2(0) = '1') else
tmp_57_reg_6222;
a_0_flag_d_assign_load_5_fu_3419_p3 <=
flag_d_min8_1_reg_6029 when (tmp_43_reg_6043(0) = '1') else
flag_d_assign_reg_6011;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_core_1_reg_527pp0_it0 <= "XXXXXXXX";
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(p_mask_data_stream_V_full_n, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34)
begin
ap_sig_bdd_136 <= ((p_mask_data_stream_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34));
end process;
-- ap_sig_bdd_1776 assign process. --
ap_sig_bdd_1776_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_1776 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_180 assign process. --
ap_sig_bdd_180_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_180 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_196 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_2075 assign process. --
ap_sig_bdd_2075_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2075 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_2108 assign process. --
ap_sig_bdd_2108_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it12, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_2108 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it12) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_2152 assign process. --
ap_sig_bdd_2152_assign_proc : process(exitcond_fu_846_p2, or_cond1_fu_883_p2)
begin
ap_sig_bdd_2152 <= ((ap_const_lv1_0 = exitcond_fu_846_p2) and (ap_const_lv1_0 = or_cond1_fu_883_p2));
end process;
-- ap_sig_bdd_2156 assign process. --
ap_sig_bdd_2156_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it32, ap_reg_ppstg_or_cond1_reg_5197_pp0_it32, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)
begin
ap_sig_bdd_2156 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it32)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)));
end process;
-- ap_sig_bdd_2159 assign process. --
ap_sig_bdd_2159_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, iscorner_2_i_s_fu_2870_p2)
begin
ap_sig_bdd_2159 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and (ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_250 assign process. --
ap_sig_bdd_250_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_250 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_48 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_61 assign process. --
ap_sig_bdd_61_assign_proc : process(p_src_data_stream_V_empty_n, exitcond_reg_5147, or_cond_reg_5156)
begin
ap_sig_bdd_61 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_48)
begin
if (ap_sig_bdd_48) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_196)
begin
if (ap_sig_bdd_196) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_3 assign process. --
ap_sig_cseq_ST_st39_fsm_3_assign_proc : process(ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) then
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_0;
end if;
end process;
b0_2_cast_fu_3928_p1 <= std_logic_vector(resize(signed(b0_2_reg_6301),32));
b0_2_fu_3882_p3 <=
b0_tmp_239_1_reg_6274 when (tmp_228_2_fu_3876_p2(0) = '1') else
tmp_84_fu_3872_p1;
b0_2_tmp_239_2_cast_fu_3992_p1 <= std_logic_vector(resize(signed(b0_2_tmp_239_2_reg_6348),32));
b0_2_tmp_239_2_fu_3936_p3 <=
b0_2_reg_6301 when (tmp_240_2_fu_3931_p2(0) = '1') else
tmp_85_reg_6312;
b0_3_cast_fu_4056_p1 <= std_logic_vector(resize(signed(b0_3_reg_6375),32));
b0_3_fu_4010_p3 <=
b0_2_tmp_239_2_reg_6348 when (tmp_228_3_fu_4004_p2(0) = '1') else
tmp_86_fu_4000_p1;
b0_3_tmp_239_3_cast_fu_4120_p1 <= std_logic_vector(resize(signed(b0_3_tmp_239_3_reg_6422),32));
b0_3_tmp_239_3_fu_4064_p3 <=
b0_3_reg_6375 when (tmp_240_3_fu_4059_p2(0) = '1') else
tmp_87_reg_6386;
b0_4_cast_fu_4184_p1 <= std_logic_vector(resize(signed(b0_4_reg_6449),32));
b0_4_fu_4138_p3 <=
b0_3_tmp_239_3_reg_6422 when (tmp_228_4_fu_4132_p2(0) = '1') else
tmp_88_fu_4128_p1;
b0_4_tmp_239_4_cast_fu_4248_p1 <= std_logic_vector(resize(signed(b0_4_tmp_239_4_reg_6496),32));
b0_4_tmp_239_4_fu_4192_p3 <=
b0_4_reg_6449 when (tmp_240_4_fu_4187_p2(0) = '1') else
tmp_89_reg_6460;
b0_5_cast_fu_4312_p1 <= std_logic_vector(resize(signed(b0_5_reg_6523),32));
b0_5_fu_4266_p3 <=
b0_4_tmp_239_4_reg_6496 when (tmp_228_5_fu_4260_p2(0) = '1') else
tmp_90_fu_4256_p1;
b0_5_tmp_239_5_cast_fu_4376_p1 <= std_logic_vector(resize(signed(b0_5_tmp_239_5_reg_6570),32));
b0_5_tmp_239_5_fu_4320_p3 <=
b0_5_reg_6523 when (tmp_240_5_fu_4315_p2(0) = '1') else
tmp_91_reg_6534;
b0_6_cast_fu_4440_p1 <= std_logic_vector(resize(signed(b0_6_reg_6597),32));
b0_6_fu_4394_p3 <=
b0_5_tmp_239_5_reg_6570 when (tmp_228_6_fu_4388_p2(0) = '1') else
tmp_92_fu_4384_p1;
b0_6_tmp_239_6_cast_fu_4504_p1 <= std_logic_vector(resize(signed(b0_6_tmp_239_6_reg_6644),32));
b0_6_tmp_239_6_fu_4448_p3 <=
b0_6_reg_6597 when (tmp_240_6_fu_4443_p2(0) = '1') else
tmp_93_reg_6608;
b0_7_cast_fu_4563_p1 <= std_logic_vector(resize(signed(b0_7_reg_6671),32));
b0_7_fu_4522_p3 <=
b0_6_tmp_239_6_reg_6644 when (tmp_228_7_fu_4516_p2(0) = '1') else
tmp_94_fu_4512_p1;
b0_cast_50_fu_3800_p1 <= std_logic_vector(resize(signed(b0_s_reg_6227),32));
b0_cast_fu_3672_p1 <= std_logic_vector(resize(signed(b0_reg_6093),32));
b0_fu_3473_p3 <=
ap_const_lv9_1EC when (tmp_69_fu_3467_p2(0) = '1') else
tmp_80_fu_3463_p1;
b0_s_fu_3754_p3 <=
b0_tmp_s_reg_6200 when (tmp_228_1_fu_3748_p2(0) = '1') else
tmp_82_fu_3744_p1;
b0_tmp_239_1_cast_fu_3864_p1 <= std_logic_vector(resize(signed(b0_tmp_239_1_reg_6274),32));
b0_tmp_239_1_fu_3808_p3 <=
b0_s_reg_6227 when (tmp_240_1_fu_3803_p2(0) = '1') else
tmp_83_reg_6238;
b0_tmp_239_cast_fu_3736_p1 <= std_logic_vector(resize(signed(b0_tmp_s_reg_6200),32));
b0_tmp_s_fu_3680_p3 <=
b0_reg_6093 when (tmp_72_fu_3675_p2(0) = '1') else
tmp_81_reg_6104;
core_buf_val_0_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_0_V_address1 <= core_buf_val_0_V_addr_reg_6702;
-- core_buf_val_0_V_ce0 assign process. --
core_buf_val_0_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce0 <= ap_const_logic_1;
else
core_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_0_V_ce1 assign process. --
core_buf_val_0_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce1 <= ap_const_logic_1;
else
core_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_0_V_d1 <= core_buf_val_1_V_q0;
-- core_buf_val_0_V_we1 assign process. --
core_buf_val_0_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it32)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32)))) then
core_buf_val_0_V_we1 <= ap_const_logic_1;
else
core_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_address1 <= ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
-- core_buf_val_1_V_ce0 assign process. --
core_buf_val_1_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce0 <= ap_const_logic_1;
else
core_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_1_V_ce1 assign process. --
core_buf_val_1_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce1 <= ap_const_logic_1;
else
core_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_d1 <= core_win_val_2_V_2_fu_4635_p3;
-- core_buf_val_1_V_we1 assign process. --
core_buf_val_1_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it33)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33)))) then
core_buf_val_1_V_we1 <= ap_const_logic_1;
else
core_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
core_win_val_0_V_2_fu_4620_p1 <= std_logic_vector(resize(unsigned(core_buf_val_0_V_load_reg_6724),16));
core_win_val_1_V_2_fu_4623_p1 <= std_logic_vector(resize(unsigned(core_buf_val_1_V_load_reg_6729),16));
core_win_val_2_V_1_2_fu_4643_p1 <= std_logic_vector(resize(unsigned(core_win_val_2_V_2_fu_4635_p3),16));
core_win_val_2_V_2_fu_4635_p3 <=
ap_reg_phiprechg_core_1_reg_527pp0_it34 when (ap_reg_ppstg_or_cond_reg_5156_pp0_it33(0) = '1') else
ap_const_lv8_0;
count_1_fu_2407_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_1));
count_1_i_0_op_op87_op_fu_1848_p3 <=
ap_const_lv4_8 when (or_cond5_fu_1746_p2(0) = '1') else
ap_const_lv4_9;
count_1_i_10_fu_2636_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7(0) = '1') else
phitmp8_reg_5842;
count_1_i_11_fu_2659_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond6_reg_5543_pp0_it7(0) = '1') else
count_1_i_10_fu_2636_p3;
count_1_i_12_fu_2678_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond7_reg_5548_pp0_it7(0) = '1') else
phitmp9_fu_2672_p2;
count_1_i_13_fu_2731_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond8_reg_5553_pp0_it8(0) = '1') else
count_1_i_12_reg_5872;
count_1_i_14_fu_2755_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond9_reg_5559_pp0_it8(0) = '1') else
phitmp10_fu_2749_p2;
count_1_i_15_fu_2793_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond2_reg_5660_pp0_it9(0) = '1') else
count_1_i_14_reg_5898;
count_1_i_1_fu_2397_p3 <=
ap_const_lv4_1 when (or_cond14_reg_5759(0) = '1') else
count_1_i_s_reg_5753;
count_1_i_2_fu_2441_p3 <=
ap_const_lv4_2 when (or_cond15_fu_2403_p2(0) = '1') else
phitmp6_fu_2419_p2;
count_1_i_2_op_op_fu_1998_p3 <=
phitmp43_op_op_cast_cast_cast_reg_5595 when (tmp_40_reg_5600(0) = '1') else
count_1_i_0_op_op87_op_reg_5590;
count_1_i_3_cast_fu_2531_p1 <= std_logic_vector(resize(unsigned(count_1_i_3_reg_5806),5));
count_1_i_3_fu_2476_p3 <=
ap_const_lv4_1 when (or_cond16_fu_2458_p2(0) = '1') else
count_1_i_2_fu_2441_p3;
count_1_i_4_fu_2563_p3 <=
ap_const_lv5_2 when (or_cond17_reg_5811(0) = '1') else
phitmp7_fu_2546_p2;
count_1_i_4_op_fu_2014_p3 <=
phitmp42_op_cast_cast_cast_fu_2003_p3 when (tmp_41_fu_2010_p2(0) = '1') else
count_1_i_2_op_op_fu_1998_p3;
count_1_i_5_fu_2587_p3 <=
ap_const_lv5_1 when (or_cond18_reg_5821(0) = '1') else
count_1_i_4_fu_2563_p3;
count_1_i_6_fu_2036_p3 <=
phitmp3_cast_cast_cast_fu_2022_p3 when (tmp_42_fu_2030_p2(0) = '1') else
count_1_i_4_op_fu_2014_p3;
count_1_i_7_fu_2061_p3 <=
ap_const_lv4_1 when (or_cond10_fu_2055_p2(0) = '1') else
count_1_i_6_fu_2036_p3;
count_1_i_8_fu_2224_p3 <=
ap_const_lv4_2 when (or_cond11_reg_5681(0) = '1') else
phitmp4_fu_2208_p2;
count_1_i_9_fu_2257_p3 <=
ap_const_lv4_1 when (or_cond12_fu_2231_p2(0) = '1') else
count_1_i_8_fu_2224_p3;
count_1_i_s_fu_2292_p3 <=
ap_const_lv4_2 when (or_cond13_fu_2274_p2(0) = '1') else
phitmp5_fu_2280_p2;
count_2_fu_2534_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_1));
count_3_fu_2594_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_1));
count_4_fu_2666_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_1));
count_5_fu_2737_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_1));
count_6_fu_2799_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_1));
count_8_fu_2197_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_1));
count_s_fu_2359_p2 <= std_logic_vector(unsigned(count_1_i_9_reg_5743) + unsigned(ap_const_lv4_1));
exitcond1_fu_802_p2 <= "1" when (p_s_reg_504 = tmp_5_reg_5113) else "0";
exitcond_fu_846_p2 <= "1" when (p_2_phi_fu_519_p4 = tmp_s_reg_5108) else "0";
flag_d_assign_10_fu_3692_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17),32));
flag_d_assign_11_fu_4289_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26),32));
flag_d_assign_12_fu_3820_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19),32));
flag_d_assign_13_fu_4417_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28),32));
flag_d_assign_14_fu_3948_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21),32));
flag_d_assign_1_fu_4076_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it23),32));
flag_d_assign_2_fu_3497_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it16),32));
flag_d_assign_3_fu_4204_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it25),32));
flag_d_assign_4_fu_3777_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it18),32));
flag_d_assign_5_fu_4332_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it27),32));
flag_d_assign_6_fu_3905_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it20),32));
flag_d_assign_7_fu_4460_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it29),32));
flag_d_assign_8_fu_4033_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it22),32));
flag_d_assign_9_fu_3274_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15),32));
flag_d_assign_fu_3143_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14),32));
flag_d_assign_s_fu_4161_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24),32));
flag_val_V_assign_load_1_10_fu_2131_p3 <=
phitmp1_5_fu_2120_p3 when (tmp_34_fu_2127_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_11_fu_1698_p3 <=
phitmp_6_fu_1687_p3 when (tmp_35_fu_1694_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_12_fu_2163_p3 <=
phitmp1_6_fu_2149_p3 when (tmp_36_fu_2157_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_13_fu_1726_p3 <=
phitmp_7_fu_1715_p3 when (tmp_37_fu_1722_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_14_fu_2351_p3 <=
phitmp1_7_fu_2340_p3 when (tmp_38_fu_2347_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_1_fu_1562_p3 <=
phitmp_1_reg_5280 when (tmp_24_reg_5285(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_2_fu_1589_p3 <=
phitmp_2_reg_5299 when (tmp_27_reg_5304(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_3_fu_1930_p3 <=
phitmp1_2_fu_1919_p3 when (tmp_28_fu_1926_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_4_fu_1616_p3 <=
phitmp_3_reg_5318 when (tmp_29_reg_5323(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_5_fu_1962_p3 <=
phitmp1_3_fu_1948_p3 when (tmp_30_fu_1956_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_6_fu_1642_p3 <=
phitmp_4_fu_1631_p3 when (tmp_31_fu_1638_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_7_fu_2112_p3 <=
phitmp1_4_fu_2101_p3 when (tmp_32_fu_2108_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_8_fu_1670_p3 <=
phitmp_5_fu_1659_p3 when (tmp_33_fu_1666_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_9_fu_1911_p3 <=
phitmp1_1_fu_1900_p3 when (tmp_25_fu_1907_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_s_fu_1521_p3 <=
phitmp1_reg_5261 when (tmp_20_reg_5266(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_2_s_fu_1894_p3 <=
phitmp3_reg_5422 when (tmp_23_reg_5427(0) = '1') else
ap_const_lv2_0;
-- grp_image_filter_reg_int_s_fu_542_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_542_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_542_in_r <= std_logic_vector(resize(signed(tmp_193_1_fu_2879_p3),32));
-- grp_image_filter_reg_int_s_fu_547_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_547_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_547_in_r <= std_logic_vector(resize(signed(tmp_203_1_fu_2894_p3),32));
-- grp_image_filter_reg_int_s_fu_552_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_552_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_552_in_r <= std_logic_vector(resize(signed(tmp_193_3_fu_2909_p3),32));
-- grp_image_filter_reg_int_s_fu_557_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_557_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_557_in_r <= std_logic_vector(resize(signed(tmp_203_3_fu_2924_p3),32));
-- grp_image_filter_reg_int_s_fu_562_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_562_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_562_in_r <= std_logic_vector(resize(signed(tmp_193_5_fu_2939_p3),32));
-- grp_image_filter_reg_int_s_fu_567_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_567_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_567_in_r <= std_logic_vector(resize(signed(tmp_203_5_fu_2954_p3),32));
-- grp_image_filter_reg_int_s_fu_572_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_572_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_572_in_r <= std_logic_vector(resize(signed(tmp_193_7_fu_2969_p3),32));
-- grp_image_filter_reg_int_s_fu_577_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_577_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_577_in_r <= std_logic_vector(resize(signed(tmp_203_7_fu_2984_p3),32));
-- grp_image_filter_reg_int_s_fu_582_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_582_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_582_in_r <=
grp_image_filter_reg_int_s_fu_542_ap_return when (tmp_192_1_fu_2995_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_552_ap_return;
-- grp_image_filter_reg_int_s_fu_587_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_587_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_587_in_r <=
grp_image_filter_reg_int_s_fu_547_ap_return when (tmp_202_1_fu_3010_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_557_ap_return;
-- grp_image_filter_reg_int_s_fu_592_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_592_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_592_in_r <=
grp_image_filter_reg_int_s_fu_562_ap_return when (tmp_192_5_fu_3053_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_572_ap_return;
-- grp_image_filter_reg_int_s_fu_597_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_597_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_597_in_r <=
grp_image_filter_reg_int_s_fu_567_ap_return when (tmp_202_5_fu_3068_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_577_ap_return;
-- grp_image_filter_reg_int_s_fu_602_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_602_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_602_in_r <= std_logic_vector(resize(signed(tmp_193_9_fu_3087_p3),32));
-- grp_image_filter_reg_int_s_fu_607_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_607_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_607_in_r <= std_logic_vector(resize(signed(tmp_203_9_fu_3102_p3),32));
-- grp_image_filter_reg_int_s_fu_612_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_612_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_612_in_r <=
grp_image_filter_reg_int_s_fu_582_ap_return when (tmp_199_1_fu_3113_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_592_ap_return;
-- grp_image_filter_reg_int_s_fu_617_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_617_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_617_in_r <=
grp_image_filter_reg_int_s_fu_587_ap_return when (tmp_212_1_fu_3128_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_597_ap_return;
-- grp_image_filter_reg_int_s_fu_622_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_622_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_622_in_r <= std_logic_vector(resize(signed(tmp_193_s_fu_3150_p3),32));
-- grp_image_filter_reg_int_s_fu_627_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_627_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_627_in_r <= std_logic_vector(resize(signed(tmp_203_s_fu_3165_p3),32));
-- grp_image_filter_reg_int_s_fu_632_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_632_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_632_in_r <= std_logic_vector(resize(signed(tmp_193_2_fu_3180_p3),32));
-- grp_image_filter_reg_int_s_fu_637_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_637_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_637_in_r <= std_logic_vector(resize(signed(tmp_203_2_fu_3195_p3),32));
-- grp_image_filter_reg_int_s_fu_642_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_642_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_642_in_r <= std_logic_vector(resize(signed(tmp_193_4_fu_3210_p3),32));
-- grp_image_filter_reg_int_s_fu_647_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_647_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_647_in_r <= std_logic_vector(resize(signed(tmp_203_4_fu_3225_p3),32));
-- grp_image_filter_reg_int_s_fu_652_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_652_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_652_in_r <= ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
-- grp_image_filter_reg_int_s_fu_657_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_657_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_657_in_r <= ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
-- grp_image_filter_reg_int_s_fu_662_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_662_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_662_in_r <=
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 when (tmp_192_7_fu_3236_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_602_ap_return;
-- grp_image_filter_reg_int_s_fu_667_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_667_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_667_in_r <=
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 when (tmp_202_7_fu_3249_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_607_ap_return;
-- grp_image_filter_reg_int_s_fu_672_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_672_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_672_in_r <=
flag_d_min2_9_reg_6017 when (tmp_192_9_fu_3277_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_622_ap_return;
-- grp_image_filter_reg_int_s_fu_677_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_677_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_677_in_r <=
flag_d_max2_9_reg_6023 when (tmp_202_9_fu_3290_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_627_ap_return;
-- grp_image_filter_reg_int_s_fu_682_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_682_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_682_in_r <=
grp_image_filter_reg_int_s_fu_622_ap_return when (tmp_192_s_fu_3303_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_632_ap_return;
-- grp_image_filter_reg_int_s_fu_687_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_687_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_687_in_r <=
grp_image_filter_reg_int_s_fu_627_ap_return when (tmp_202_s_fu_3318_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_637_ap_return;
-- grp_image_filter_reg_int_s_fu_692_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_692_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_692_in_r <=
grp_image_filter_reg_int_s_fu_632_ap_return when (tmp_192_2_fu_3333_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_642_ap_return;
-- grp_image_filter_reg_int_s_fu_697_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_697_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_697_in_r <=
grp_image_filter_reg_int_s_fu_637_ap_return when (tmp_202_2_fu_3348_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_647_ap_return;
-- grp_image_filter_reg_int_s_fu_702_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_702_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_702_in_r <=
grp_image_filter_reg_int_s_fu_642_ap_return when (tmp_192_4_fu_3363_p2(0) = '1') else
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15;
-- grp_image_filter_reg_int_s_fu_707_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_707_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_707_in_r <=
grp_image_filter_reg_int_s_fu_647_ap_return when (tmp_202_4_fu_3376_p2(0) = '1') else
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15;
-- grp_image_filter_reg_int_s_fu_712_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_712_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_712_in_r <=
grp_image_filter_reg_int_s_fu_652_ap_return when (tmp_199_3_fu_3389_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_662_ap_return;
-- grp_image_filter_reg_int_s_fu_717_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_717_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_717_in_r <=
grp_image_filter_reg_int_s_fu_657_ap_return when (tmp_212_3_fu_3404_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_667_ap_return;
-- grp_image_filter_reg_int_s_fu_722_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_722_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_722_in_r <= tmp_210_5_reg_6129;
-- grp_image_filter_reg_int_s_fu_727_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_727_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_727_in_r <= tmp_225_5_reg_6134;
-- grp_image_filter_reg_int_s_fu_732_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_732_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_732_in_r <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
-- grp_image_filter_reg_int_s_fu_737_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_737_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_737_in_r <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
-- grp_image_filter_reg_int_s_fu_742_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_742_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_742_in_r <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
-- grp_image_filter_reg_int_s_fu_747_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_747_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_747_in_r <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
-- grp_image_filter_reg_int_s_fu_752_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_752_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_752_in_r <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
-- grp_image_filter_reg_int_s_fu_757_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_757_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_757_in_r <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
-- grp_image_filter_reg_int_s_fu_762_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_762_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_762_in_r <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
-- grp_image_filter_reg_int_s_fu_767_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_767_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_767_in_r <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
-- grp_image_filter_reg_int_s_fu_772_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_772_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_772_in_r <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
-- grp_image_filter_reg_int_s_fu_777_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_777_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_777_in_r <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
i_V_fu_807_p2 <= std_logic_vector(unsigned(p_s_reg_504) + unsigned(ap_const_lv11_1));
icmp1_fu_898_p2 <= "1" when (tmp_97_fu_888_p4 = ap_const_lv9_0) else "0";
icmp_fu_840_p2 <= "1" when (tmp_16_fu_830_p4 = ap_const_lv9_0) else "0";
iscorner_2_i_7_fu_2191_p2 <= (tmp_185_7_fu_2181_p2 and not_or_cond_fu_2186_p2);
iscorner_2_i_s_fu_2870_p2 <= (tmp10_fu_2866_p2 or ap_reg_ppstg_tmp3_reg_5878_pp0_it11);
j_V_fu_851_p2 <= std_logic_vector(unsigned(p_2_phi_fu_519_p4) + unsigned(ap_const_lv11_1));
k_buf_val_0_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_0_V_address1 <= k_buf_val_0_V_addr_reg_5161;
-- k_buf_val_0_V_ce0 assign process. --
k_buf_val_0_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce0 <= ap_const_logic_1;
else
k_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_0_V_ce1 assign process. --
k_buf_val_0_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce1 <= ap_const_logic_1;
else
k_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_0_V_d1 <= k_buf_val_1_V_q0;
-- k_buf_val_0_V_we1 assign process. --
k_buf_val_0_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_0_V_we1 <= ap_const_logic_1;
else
k_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_address1 <= k_buf_val_1_V_addr_reg_5167;
-- k_buf_val_1_V_ce0 assign process. --
k_buf_val_1_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce0 <= ap_const_logic_1;
else
k_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_1_V_ce1 assign process. --
k_buf_val_1_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce1 <= ap_const_logic_1;
else
k_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_d1 <= k_buf_val_2_V_q0;
-- k_buf_val_1_V_we1 assign process. --
k_buf_val_1_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_1_V_we1 <= ap_const_logic_1;
else
k_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_address1 <= k_buf_val_2_V_addr_reg_5173;
-- k_buf_val_2_V_ce0 assign process. --
k_buf_val_2_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce0 <= ap_const_logic_1;
else
k_buf_val_2_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_2_V_ce1 assign process. --
k_buf_val_2_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce1 <= ap_const_logic_1;
else
k_buf_val_2_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_d1 <= k_buf_val_3_V_q0;
-- k_buf_val_2_V_we1 assign process. --
k_buf_val_2_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_2_V_we1 <= ap_const_logic_1;
else
k_buf_val_2_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_address1 <= k_buf_val_3_V_addr_reg_5179;
-- k_buf_val_3_V_ce0 assign process. --
k_buf_val_3_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce0 <= ap_const_logic_1;
else
k_buf_val_3_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_3_V_ce1 assign process. --
k_buf_val_3_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce1 <= ap_const_logic_1;
else
k_buf_val_3_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_d1 <= k_buf_val_4_V_q0;
-- k_buf_val_3_V_we1 assign process. --
k_buf_val_3_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_3_V_we1 <= ap_const_logic_1;
else
k_buf_val_3_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_address1 <= k_buf_val_4_V_addr_reg_5185;
-- k_buf_val_4_V_ce0 assign process. --
k_buf_val_4_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce0 <= ap_const_logic_1;
else
k_buf_val_4_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_4_V_ce1 assign process. --
k_buf_val_4_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce1 <= ap_const_logic_1;
else
k_buf_val_4_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_d1 <= k_buf_val_5_V_q0;
-- k_buf_val_4_V_we1 assign process. --
k_buf_val_4_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_4_V_we1 <= ap_const_logic_1;
else
k_buf_val_4_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_address1 <= k_buf_val_5_V_addr_reg_5191;
-- k_buf_val_5_V_ce0 assign process. --
k_buf_val_5_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce0 <= ap_const_logic_1;
else
k_buf_val_5_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_5_V_ce1 assign process. --
k_buf_val_5_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce1 <= ap_const_logic_1;
else
k_buf_val_5_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_d1 <= p_src_data_stream_V_dout;
-- k_buf_val_5_V_we1 assign process. --
k_buf_val_5_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_5_V_we1 <= ap_const_logic_1;
else
k_buf_val_5_V_we1 <= ap_const_logic_0;
end if;
end process;
lhs_V_fu_1252_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_2_fu_252),9));
not_or_cond10_demorgan_fu_2093_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
not_or_cond10_fu_2782_p2 <= (ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 xor ap_const_lv1_1);
not_or_cond11_demorgan_fu_2097_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
not_or_cond11_fu_2817_p2 <= (ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 xor ap_const_lv1_1);
not_or_cond12_demorgan_fu_2425_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
not_or_cond12_fu_2429_p2 <= (not_or_cond12_demorgan_fu_2425_p2 xor ap_const_lv1_1);
not_or_cond13_demorgan_fu_2470_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
not_or_cond13_fu_2521_p2 <= (not_or_cond13_demorgan_reg_5801 xor ap_const_lv1_1);
not_or_cond14_demorgan_fu_2500_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
not_or_cond14_fu_2552_p2 <= (not_or_cond14_demorgan_reg_5816 xor ap_const_lv1_1);
not_or_cond15_fu_2576_p2 <= (or_cond18_reg_5821 xor ap_const_lv1_1);
not_or_cond1_fu_2213_p2 <= (or_cond11_reg_5681 xor ap_const_lv1_1);
not_or_cond2_demorgan_fu_2241_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
not_or_cond2_fu_2245_p2 <= (not_or_cond2_demorgan_fu_2241_p2 xor ap_const_lv1_1);
not_or_cond3_demorgan_fu_2286_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
not_or_cond3_fu_2370_p2 <= (not_or_cond3_demorgan_reg_5748 xor ap_const_lv1_1);
not_or_cond4_demorgan_fu_2316_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
not_or_cond4_fu_2386_p2 <= (not_or_cond4_demorgan_reg_5764 xor ap_const_lv1_1);
not_or_cond5_fu_2625_p2 <= (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 xor ap_const_lv1_1);
not_or_cond6_demorgan_fu_1870_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
not_or_cond6_fu_2648_p2 <= (ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 xor ap_const_lv1_1);
not_or_cond7_demorgan_fu_1876_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
not_or_cond7_fu_2704_p2 <= (ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 xor ap_const_lv1_1);
not_or_cond8_demorgan_fu_1882_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
not_or_cond8_fu_2720_p2 <= (ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 xor ap_const_lv1_1);
not_or_cond9_demorgan_fu_1888_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
not_or_cond9_fu_2767_p2 <= (ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 xor ap_const_lv1_1);
not_or_cond_fu_2186_p2 <= (or_cond10_reg_5670 xor ap_const_lv1_1);
or_cond10_fu_2055_p2 <= (tmp_183_7_fu_2049_p2 or tmp_181_7_not_fu_2044_p2);
or_cond11_fu_2075_p2 <= (tmp_181_8_fu_2069_p2 or tmp_183_7_fu_2049_p2);
or_cond12_fu_2231_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
or_cond13_fu_2274_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
or_cond14_fu_2310_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
or_cond15_fu_2403_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
or_cond16_fu_2458_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
or_cond17_fu_2494_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
or_cond18_fu_2511_p2 <= (tmp_181_5_fu_2506_p2 or ap_reg_ppstg_tmp_39_reg_5532_pp0_it5);
or_cond1_fu_883_p2 <= (tmp_8_reg_5132 and tmp_17_fu_877_p2);
or_cond2_fu_1990_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
or_cond3_fu_1994_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
or_cond4_fu_904_p2 <= (icmp_reg_5142 or icmp1_fu_898_p2);
or_cond5_fu_1746_p2 <= (tmp_39_fu_1740_p2 or tmp_181_0_not_fu_1734_p2);
or_cond6_fu_1764_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
or_cond7_fu_1782_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
or_cond8_fu_1800_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
or_cond9_fu_1818_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
or_cond_fu_862_p2 <= (tmp_7_reg_5127 and tmp_11_fu_857_p2);
-- p_2_phi_fu_519_p4 assign process. --
p_2_phi_fu_519_p4_assign_proc : process(p_2_reg_515, ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, ap_reg_ppiten_pp0_it1, j_V_reg_5151)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
p_2_phi_fu_519_p4 <= j_V_reg_5151;
else
p_2_phi_fu_519_p4 <= p_2_reg_515;
end if;
end process;
p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_reg_6077),32));
p_a_0_flag_d_assign_load_5_fu_3434_p3 <=
ap_const_lv8_14 when (tmp_45_fu_3428_p2(0) = '1') else
tmp_44_fu_3424_p1;
p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_tmp_s_reg_6189),32));
p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 <=
p_a_0_flag_d_assign_load_5_reg_6077 when (tmp_49_fu_3655_p2(0) = '1') else
tmp_48_reg_6088;
p_iscorner_0_i_10_fu_2709_p2 <= (tmp_185_11_fu_2699_p2 and not_or_cond7_fu_2704_p2);
p_iscorner_0_i_11_fu_2725_p2 <= (tmp_185_12_fu_2715_p2 and not_or_cond8_fu_2720_p2);
p_iscorner_0_i_12_fu_2772_p2 <= (tmp_185_13_reg_5893 and not_or_cond9_fu_2767_p2);
p_iscorner_0_i_13_fu_2787_p2 <= (tmp_185_14_fu_2777_p2 and not_or_cond10_fu_2782_p2);
p_iscorner_0_i_14_fu_2842_p2 <= (tmp_185_15_reg_5914 and not_or_cond11_reg_5919);
p_iscorner_0_i_15_fu_2846_p2 <= (tmp2_reg_5929 and tmp_185_16_reg_5924);
p_iscorner_0_i_1_fu_2391_p2 <= (tmp_185_1_fu_2381_p2 and not_or_cond4_fu_2386_p2);
p_iscorner_0_i_2_fu_2435_p2 <= (tmp_185_2_fu_2413_p2 and not_or_cond12_fu_2429_p2);
p_iscorner_0_i_3_fu_2526_p2 <= (tmp_185_3_reg_5796 and not_or_cond13_fu_2521_p2);
p_iscorner_0_i_4_fu_2557_p2 <= (tmp_185_4_fu_2540_p2 and not_or_cond14_fu_2552_p2);
p_iscorner_0_i_5_fu_2581_p2 <= (tmp_185_5_fu_2570_p2 and not_or_cond15_fu_2576_p2);
p_iscorner_0_i_6_fu_2630_p2 <= (tmp_185_6_fu_2620_p2 and not_or_cond5_fu_2625_p2);
p_iscorner_0_i_7_fu_2653_p2 <= (tmp_185_10_fu_2642_p2 and not_or_cond6_fu_2648_p2);
p_iscorner_0_i_8_fu_2218_p2 <= (tmp_185_8_fu_2202_p2 and not_or_cond1_fu_2213_p2);
p_iscorner_0_i_9_fu_2251_p2 <= (tmp_185_9_fu_2235_p2 and not_or_cond2_fu_2245_p2);
p_iscorner_0_i_s_fu_2375_p2 <= (tmp_185_s_fu_2364_p2 and not_or_cond3_fu_2370_p2);
p_mask_data_stream_V_din <=
ap_const_lv8_FF when (tmp_26_fu_4779_p2(0) = '1') else
ap_const_lv8_0;
-- p_mask_data_stream_V_write assign process. --
p_mask_data_stream_V_write_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_mask_data_stream_V_write <= ap_const_logic_1;
else
p_mask_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
phitmp10_fu_2749_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_2));
phitmp1_1_fu_1900_p3 <=
ap_const_lv2_1 when (tmp_182_1_reg_5441(0) = '1') else
ap_const_lv2_2;
phitmp1_2_fu_1919_p3 <=
ap_const_lv2_1 when (tmp_182_2_reg_5461(0) = '1') else
ap_const_lv2_2;
phitmp1_3_fu_1948_p3 <=
ap_const_lv2_1 when (tmp_182_3_fu_1938_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_4_fu_2101_p3 <=
ap_const_lv2_1 when (tmp_182_4_reg_5638(0) = '1') else
ap_const_lv2_2;
phitmp1_5_fu_2120_p3 <=
ap_const_lv2_1 when (tmp_182_5_reg_5649(0) = '1') else
ap_const_lv2_2;
phitmp1_6_fu_2149_p3 <=
ap_const_lv2_1 when (tmp_182_6_fu_2139_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_7_fu_2340_p3 <=
ap_const_lv2_1 when (tmp_182_7_reg_5722(0) = '1') else
ap_const_lv2_2;
phitmp1_fu_1278_p3 <=
ap_const_lv2_1 when (tmp_18_fu_1266_p2(0) = '1') else
ap_const_lv2_2;
phitmp2_fu_4606_p2 <= std_logic_vector(unsigned(tmp_100_v_reg_6714) + unsigned(ap_const_lv8_FF));
phitmp3_cast_cast_cast_fu_2022_p3 <=
ap_const_lv4_2 when (or_cond3_fu_1994_p2(0) = '1') else
ap_const_lv4_3;
phitmp3_fu_1539_p3 <=
ap_const_lv2_1 when (tmp_21_fu_1527_p2(0) = '1') else
ap_const_lv2_2;
phitmp42_op_cast_cast_cast_fu_2003_p3 <=
ap_const_lv4_4 when (or_cond9_reg_5559(0) = '1') else
ap_const_lv4_5;
phitmp43_op_op_cast_cast_cast_fu_1856_p3 <=
ap_const_lv4_6 when (or_cond7_fu_1782_p2(0) = '1') else
ap_const_lv4_7;
phitmp4_fu_2208_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_2));
phitmp5_fu_2280_p2 <= std_logic_vector(unsigned(count_1_i_9_fu_2257_p3) + unsigned(ap_const_lv4_2));
phitmp6_fu_2419_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_2));
phitmp7_fu_2546_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_2));
phitmp8_fu_2600_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_2));
phitmp9_fu_2672_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_2));
phitmp_1_fu_1314_p3 <=
ap_const_lv2_1 when (tmp_176_1_fu_1302_p2(0) = '1') else
ap_const_lv2_2;
phitmp_2_fu_1350_p3 <=
ap_const_lv2_1 when (tmp_176_2_fu_1338_p2(0) = '1') else
ap_const_lv2_2;
phitmp_3_fu_1386_p3 <=
ap_const_lv2_1 when (tmp_176_3_fu_1374_p2(0) = '1') else
ap_const_lv2_2;
phitmp_4_fu_1631_p3 <=
ap_const_lv2_1 when (tmp_176_4_reg_5337(0) = '1') else
ap_const_lv2_2;
phitmp_5_fu_1659_p3 <=
ap_const_lv2_1 when (tmp_176_5_reg_5357(0) = '1') else
ap_const_lv2_2;
phitmp_6_fu_1687_p3 <=
ap_const_lv2_1 when (tmp_176_6_reg_5377(0) = '1') else
ap_const_lv2_2;
phitmp_7_fu_1715_p3 <=
ap_const_lv2_1 when (tmp_176_7_reg_5397(0) = '1') else
ap_const_lv2_2;
phitmp_fu_2811_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_2));
r_V_1_1_fu_1557_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_1_fu_1553_p1));
r_V_1_2_fu_1584_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_2_fu_1580_p1));
r_V_1_3_fu_1611_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_3_fu_1607_p1));
r_V_1_4_fu_1626_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_4_fu_1622_p1));
r_V_1_5_fu_1654_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_5_fu_1650_p1));
r_V_1_6_fu_1682_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_6_fu_1678_p1));
r_V_1_7_fu_1710_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_7_fu_1706_p1));
r_V_1_fu_1516_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_fu_1512_p1));
r_V_2_fu_1332_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_2_fu_1328_p1));
r_V_3_fu_1368_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_3_fu_1364_p1));
r_V_4_fu_1404_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_4_fu_1400_p1));
r_V_5_fu_1426_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_5_fu_1422_p1));
r_V_6_fu_1448_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_6_fu_1444_p1));
r_V_7_fu_1470_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_7_fu_1466_p1));
r_V_fu_1260_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_fu_1256_p1));
r_V_s_fu_1296_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_s_fu_1292_p1));
rhs_V_1_1_fu_1553_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_3_fu_320),9));
rhs_V_1_2_fu_1580_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_1_3_fu_296),9));
rhs_V_1_3_fu_1607_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_0_3_fu_268),9));
rhs_V_1_4_fu_1622_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_0_3_fu_240),9));
rhs_V_1_5_fu_1650_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_0_3_fu_212),9));
rhs_V_1_6_fu_1678_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_1_3_fu_188),9));
rhs_V_1_7_fu_1706_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_3_fu_168),9));
rhs_V_1_fu_1512_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_fu_324),9));
rhs_V_2_fu_1328_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_4_fu_204),9));
rhs_V_3_fu_1364_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_5_fu_236),9));
rhs_V_4_fu_1400_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_5_fu_264),9));
rhs_V_5_fu_1422_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_5_fu_292),9));
rhs_V_6_fu_1444_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_4_fu_312),9));
rhs_V_7_fu_1466_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_3_fu_156),9));
rhs_V_fu_1256_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_fu_172),9));
rhs_V_s_fu_1292_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_3_fu_176),9));
tmp10_fu_2866_p2 <= (tmp14_reg_5944 or ap_reg_ppstg_tmp11_reg_5934_pp0_it11);
tmp11_fu_2833_p2 <= (tmp13_reg_5904 or ap_reg_ppstg_tmp12_reg_5883_pp0_it9);
tmp12_fu_2694_p2 <= (p_iscorner_0_i_5_reg_5832 or p_iscorner_0_i_6_fu_2630_p2);
tmp13_fu_2762_p2 <= (p_iscorner_0_i_7_reg_5862 or p_iscorner_0_i_10_fu_2709_p2);
tmp14_fu_2861_p2 <= (tmp16_fu_2856_p2 or tmp15_reg_5939);
tmp15_fu_2837_p2 <= (p_iscorner_0_i_11_reg_5888 or p_iscorner_0_i_12_fu_2772_p2);
tmp16_fu_2856_p2 <= (tmp17_fu_2850_p2 or p_iscorner_0_i_13_reg_5909);
tmp17_fu_2850_p2 <= (p_iscorner_0_i_14_fu_2842_p2 or p_iscorner_0_i_15_fu_2846_p2);
tmp18_fu_4771_p2 <= (tmp20_reg_6744 and tmp19_reg_6739);
tmp19_fu_4701_p2 <= (tmp_52_fu_4647_p2 and tmp_9_reg_5137);
tmp20_fu_4712_p2 <= (tmp21_fu_4706_p2 and ap_reg_ppstg_tmp_53_reg_6719_pp0_it33);
tmp21_fu_4706_p2 <= (tmp_73_fu_4653_p2 and tmp_242_1_fu_4659_p2);
tmp22_fu_4775_p2 <= (tmp25_reg_6754 and tmp23_reg_6749);
tmp23_fu_4723_p2 <= (tmp24_fu_4717_p2 and tmp_242_2_fu_4665_p2);
tmp24_fu_4717_p2 <= (tmp_74_fu_4671_p2 and tmp_245_1_fu_4677_p2);
tmp25_fu_4735_p2 <= (tmp26_fu_4729_p2 and tmp_245_2_fu_4683_p2);
tmp26_fu_4729_p2 <= (tmp_55_fu_4695_p2 and tmp_54_fu_4689_p2);
tmp2_fu_2828_p2 <= (not_or_cond11_fu_2817_p2 and ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9);
tmp3_fu_2689_p2 <= (tmp7_fu_2685_p2 or tmp4_reg_5847);
tmp4_fu_2606_p2 <= (tmp6_reg_5827 or ap_reg_ppstg_tmp5_reg_5781_pp0_it6);
tmp5_fu_2334_p2 <= (iscorner_2_i_7_fu_2191_p2 or p_iscorner_0_i_8_fu_2218_p2);
tmp6_fu_2516_p2 <= (p_iscorner_0_i_9_reg_5738 or p_iscorner_0_i_s_fu_2375_p2);
tmp7_fu_2685_p2 <= (tmp9_reg_5857 or tmp8_reg_5852);
tmp8_fu_2610_p2 <= (p_iscorner_0_i_1_reg_5786 or p_iscorner_0_i_2_reg_5791);
tmp9_fu_2614_p2 <= (p_iscorner_0_i_3_fu_2526_p2 or p_iscorner_0_i_4_fu_2557_p2);
tmp_100_v_fu_4593_p3 <=
a0_7_tmp_232_7_reg_6691 when (tmp_51_fu_4588_p2(0) = '1') else
tmp_50_fu_4583_p2;
tmp_11_fu_857_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) < unsigned(tmp_15_reg_5103)) else "0";
tmp_12_fu_867_p1 <= std_logic_vector(resize(unsigned(p_2_phi_fu_519_p4),64));
tmp_14_fu_4577_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31),64));
tmp_15_fu_786_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_16_fu_830_p4 <= p_s_reg_504(10 downto 2);
tmp_176_1_fu_1302_p2 <= "1" when (signed(r_V_s_fu_1296_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_2_fu_1338_p2 <= "1" when (signed(r_V_2_fu_1332_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_3_fu_1374_p2 <= "1" when (signed(r_V_3_fu_1368_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_4_fu_1410_p2 <= "1" when (signed(r_V_4_fu_1404_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_5_fu_1432_p2 <= "1" when (signed(r_V_5_fu_1426_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_6_fu_1454_p2 <= "1" when (signed(r_V_6_fu_1448_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_7_fu_1476_p2 <= "1" when (signed(r_V_7_fu_1470_p2) > signed(ap_const_lv9_14)) else "0";
tmp_177_1_fu_1308_p2 <= "1" when (signed(r_V_s_fu_1296_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_2_fu_1344_p2 <= "1" when (signed(r_V_2_fu_1332_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_3_fu_1380_p2 <= "1" when (signed(r_V_3_fu_1368_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_4_fu_1416_p2 <= "1" when (signed(r_V_4_fu_1404_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_5_fu_1438_p2 <= "1" when (signed(r_V_5_fu_1426_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_6_fu_1460_p2 <= "1" when (signed(r_V_6_fu_1448_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_7_fu_1482_p2 <= "1" when (signed(r_V_7_fu_1470_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_17_fu_877_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) > unsigned(ap_const_lv11_5)) else "0";
tmp_181_0_not_fu_1734_p2 <= "0" when (flag_val_V_assign_load_1_s_fu_1521_p3 = flag_val_V_assign_load_1_1_fu_1562_p3) else "1";
tmp_181_1_fu_2300_p2 <= "0" when (flag_val_V_assign_load_1_5_reg_5631 = flag_val_V_assign_load_1_7_fu_2112_p3) else "1";
tmp_181_1_not_fu_1752_p2 <= "0" when (flag_val_V_assign_load_1_1_fu_1562_p3 = flag_val_V_assign_load_1_2_fu_1589_p3) else "1";
tmp_181_2_fu_2322_p2 <= "0" when (flag_val_V_assign_load_1_7_fu_2112_p3 = flag_val_V_assign_load_1_10_fu_2131_p3) else "1";
tmp_181_2_not_fu_1770_p2 <= "0" when (flag_val_V_assign_load_1_2_fu_1589_p3 = flag_val_V_assign_load_1_4_fu_1616_p3) else "1";
tmp_181_3_fu_2449_p2 <= "0" when (flag_val_V_assign_load_1_10_reg_5709 = flag_val_V_assign_load_1_12_reg_5715) else "1";
tmp_181_3_not_fu_1788_p2 <= "0" when (flag_val_V_assign_load_1_4_fu_1616_p3 = flag_val_V_assign_load_1_6_fu_1642_p3) else "1";
tmp_181_4_fu_2484_p2 <= "0" when (flag_val_V_assign_load_1_12_reg_5715 = flag_val_V_assign_load_1_14_fu_2351_p3) else "1";
tmp_181_4_not_fu_1806_p2 <= "0" when (flag_val_V_assign_load_1_6_fu_1642_p3 = flag_val_V_assign_load_1_8_fu_1670_p3) else "1";
tmp_181_5_fu_2506_p2 <= "0" when (flag_val_V_assign_load_1_14_fu_2351_p3 = ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5) else "1";
tmp_181_5_not_fu_1824_p2 <= "0" when (flag_val_V_assign_load_1_8_fu_1670_p3 = flag_val_V_assign_load_1_11_fu_1698_p3) else "1";
tmp_181_6_not_fu_1836_p2 <= "0" when (flag_val_V_assign_load_1_11_fu_1698_p3 = flag_val_V_assign_load_1_13_fu_1726_p3) else "1";
tmp_181_7_not_fu_2044_p2 <= "0" when (flag_val_V_assign_load_1_13_reg_5527 = flag_val_V_assign_load_2_s_fu_1894_p3) else "1";
tmp_181_8_fu_2069_p2 <= "0" when (flag_val_V_assign_load_2_s_fu_1894_p3 = flag_val_V_assign_load_1_9_fu_1911_p3) else "1";
tmp_181_9_fu_2081_p2 <= "0" when (flag_val_V_assign_load_1_9_fu_1911_p3 = flag_val_V_assign_load_1_3_fu_1930_p3) else "1";
tmp_181_s_fu_2265_p2 <= "0" when (flag_val_V_assign_load_1_3_reg_5625 = flag_val_V_assign_load_1_5_reg_5631) else "1";
tmp_182_1_fu_1568_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_2_fu_1595_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_3_fu_1938_p2 <= "1" when (signed(r_V_1_3_reg_5472) > signed(ap_const_lv9_14)) else "0";
tmp_182_4_fu_1970_p2 <= "1" when (signed(r_V_1_4_reg_5483) > signed(ap_const_lv9_14)) else "0";
tmp_182_5_fu_1980_p2 <= "1" when (signed(r_V_1_5_reg_5494) > signed(ap_const_lv9_14)) else "0";
tmp_182_6_fu_2139_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_182_7_fu_2171_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_183_10_fu_2328_p2 <= "1" when (flag_val_V_assign_load_1_7_fu_2112_p3 = ap_const_lv2_0) else "0";
tmp_183_11_fu_2453_p2 <= "1" when (flag_val_V_assign_load_1_10_reg_5709 = ap_const_lv2_0) else "0";
tmp_183_12_fu_2489_p2 <= "1" when (flag_val_V_assign_load_1_12_reg_5715 = ap_const_lv2_0) else "0";
tmp_183_1_fu_1758_p2 <= "1" when (flag_val_V_assign_load_1_1_fu_1562_p3 = ap_const_lv2_0) else "0";
tmp_183_2_fu_1776_p2 <= "1" when (flag_val_V_assign_load_1_2_fu_1589_p3 = ap_const_lv2_0) else "0";
tmp_183_3_fu_1794_p2 <= "1" when (flag_val_V_assign_load_1_4_fu_1616_p3 = ap_const_lv2_0) else "0";
tmp_183_4_fu_1812_p2 <= "1" when (flag_val_V_assign_load_1_6_fu_1642_p3 = ap_const_lv2_0) else "0";
tmp_183_5_fu_1830_p2 <= "1" when (flag_val_V_assign_load_1_8_fu_1670_p3 = ap_const_lv2_0) else "0";
tmp_183_6_fu_1842_p2 <= "1" when (flag_val_V_assign_load_1_11_fu_1698_p3 = ap_const_lv2_0) else "0";
tmp_183_7_fu_2049_p2 <= "1" when (flag_val_V_assign_load_2_s_fu_1894_p3 = ap_const_lv2_0) else "0";
tmp_183_8_fu_2305_p2 <= "1" when (flag_val_V_assign_load_1_5_reg_5631 = ap_const_lv2_0) else "0";
tmp_183_9_fu_2087_p2 <= "1" when (flag_val_V_assign_load_1_9_fu_1911_p3 = ap_const_lv2_0) else "0";
tmp_183_s_fu_2269_p2 <= "1" when (flag_val_V_assign_load_1_3_reg_5625 = ap_const_lv2_0) else "0";
tmp_184_1_fu_1574_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_2_fu_1601_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_3_fu_1943_p2 <= "1" when (signed(r_V_1_3_reg_5472) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_4_fu_1975_p2 <= "1" when (signed(r_V_1_4_reg_5483) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_5_fu_1985_p2 <= "1" when (signed(r_V_1_5_reg_5494) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_6_fu_2144_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_7_fu_2176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_185_10_fu_2642_p2 <= "1" when (unsigned(count_1_i_10_fu_2636_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_11_fu_2699_p2 <= "1" when (unsigned(count_4_reg_5867) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_12_fu_2715_p2 <= "1" when (unsigned(count_1_i_12_reg_5872) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_13_fu_2743_p2 <= "1" when (unsigned(count_5_fu_2737_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_14_fu_2777_p2 <= "1" when (unsigned(count_1_i_14_reg_5898) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_15_fu_2805_p2 <= "1" when (unsigned(count_6_fu_2799_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_16_fu_2822_p2 <= "1" when (unsigned(phitmp_fu_2811_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_1_fu_2381_p2 <= "1" when (unsigned(count_1_i_s_reg_5753) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_2_fu_2413_p2 <= "1" when (unsigned(count_1_fu_2407_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_3_fu_2464_p2 <= "1" when (unsigned(count_1_i_2_fu_2441_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_4_fu_2540_p2 <= "1" when (unsigned(count_2_fu_2534_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_5_fu_2570_p2 <= "1" when (unsigned(count_1_i_4_fu_2563_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_6_fu_2620_p2 <= "1" when (unsigned(count_3_reg_5837) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_7_fu_2181_p2 <= "1" when (unsigned(count_1_i_6_reg_5665) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_8_fu_2202_p2 <= "1" when (unsigned(count_8_fu_2197_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_9_fu_2235_p2 <= "1" when (unsigned(count_1_i_8_fu_2224_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_s_fu_2364_p2 <= "1" when (unsigned(count_s_fu_2359_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_188_1_fu_2875_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) < signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_188_2_fu_3176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) < signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_188_3_fu_2905_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) < signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_188_4_fu_3206_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) < signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_188_5_fu_2935_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) < signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_188_7_fu_2965_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) < signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_188_9_fu_3083_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) < signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_188_s_fu_3146_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) < signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_18_fu_1266_p2 <= "1" when (signed(r_V_fu_1260_p2) > signed(ap_const_lv9_14)) else "0";
tmp_192_1_fu_2995_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_542_ap_return) < signed(grp_image_filter_reg_int_s_fu_552_ap_return)) else "0";
tmp_192_2_fu_3333_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_632_ap_return) < signed(grp_image_filter_reg_int_s_fu_642_ap_return)) else "0";
tmp_192_3_fu_3025_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_552_ap_return) < signed(grp_image_filter_reg_int_s_fu_562_ap_return)) else "0";
tmp_192_4_fu_3363_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_642_ap_return) < signed(ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15)) else "0";
tmp_192_5_fu_3053_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_562_ap_return) < signed(grp_image_filter_reg_int_s_fu_572_ap_return)) else "0";
tmp_192_7_fu_3236_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14) < signed(grp_image_filter_reg_int_s_fu_602_ap_return)) else "0";
tmp_192_9_fu_3277_p2 <= "1" when (signed(flag_d_min2_9_reg_6017) < signed(grp_image_filter_reg_int_s_fu_622_ap_return)) else "0";
tmp_192_s_fu_3303_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_622_ap_return) < signed(grp_image_filter_reg_int_s_fu_632_ap_return)) else "0";
tmp_193_1_fu_2879_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_188_1_fu_2875_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_193_2_fu_3180_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_188_2_fu_3176_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_193_3_fu_2909_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_188_3_fu_2905_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_193_4_fu_3210_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_188_4_fu_3206_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_193_5_fu_2939_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_188_5_fu_2935_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_193_7_fu_2969_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_188_7_fu_2965_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_193_9_fu_3087_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_188_9_fu_3083_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_193_s_fu_3150_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_188_s_fu_3146_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_195_1_fu_2890_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) > signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_195_2_fu_3191_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) > signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_195_3_fu_2920_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) > signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_195_4_fu_3221_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) > signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_195_5_fu_2950_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) > signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_195_7_fu_2980_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) > signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_195_9_fu_3098_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) > signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_195_s_fu_3161_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) > signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_199_1_fu_3113_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_582_ap_return) < signed(grp_image_filter_reg_int_s_fu_592_ap_return)) else "0";
tmp_199_2_fu_3604_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_692_ap_return) < signed(ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16)) else "0";
tmp_199_3_fu_3389_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_652_ap_return) < signed(grp_image_filter_reg_int_s_fu_662_ap_return)) else "0";
tmp_199_4_fu_3628_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_702_ap_return) < signed(flag_d_min4_3_reg_6053)) else "0";
tmp_199_5_fu_3500_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16) < signed(grp_image_filter_reg_int_s_fu_672_ap_return)) else "0";
tmp_199_7_fu_3524_p2 <= "1" when (signed(flag_d_min4_7_reg_6065) < signed(grp_image_filter_reg_int_s_fu_682_ap_return)) else "0";
tmp_199_9_fu_3548_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_672_ap_return) < signed(grp_image_filter_reg_int_s_fu_692_ap_return)) else "0";
tmp_199_s_fu_3576_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_682_ap_return) < signed(grp_image_filter_reg_int_s_fu_702_ap_return)) else "0";
tmp_19_fu_1272_p2 <= "1" when (signed(r_V_fu_1260_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_200_3_fu_3031_p3 <=
grp_image_filter_reg_int_s_fu_552_ap_return when (tmp_192_3_fu_3025_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_562_ap_return;
tmp_202_1_fu_3010_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_547_ap_return) > signed(grp_image_filter_reg_int_s_fu_557_ap_return)) else "0";
tmp_202_2_fu_3348_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_637_ap_return) > signed(grp_image_filter_reg_int_s_fu_647_ap_return)) else "0";
tmp_202_3_fu_3039_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_557_ap_return) > signed(grp_image_filter_reg_int_s_fu_567_ap_return)) else "0";
tmp_202_4_fu_3376_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_647_ap_return) > signed(ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15)) else "0";
tmp_202_5_fu_3068_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_567_ap_return) > signed(grp_image_filter_reg_int_s_fu_577_ap_return)) else "0";
tmp_202_7_fu_3249_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14) > signed(grp_image_filter_reg_int_s_fu_607_ap_return)) else "0";
tmp_202_9_fu_3290_p2 <= "1" when (signed(flag_d_max2_9_reg_6023) > signed(grp_image_filter_reg_int_s_fu_627_ap_return)) else "0";
tmp_202_s_fu_3318_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_627_ap_return) > signed(grp_image_filter_reg_int_s_fu_637_ap_return)) else "0";
tmp_203_1_fu_2894_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_195_1_fu_2890_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_203_2_fu_3195_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_195_2_fu_3191_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_203_3_fu_2924_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_195_3_fu_2920_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_203_4_fu_3225_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_195_4_fu_3221_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_203_5_fu_2954_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_195_5_fu_2950_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_203_7_fu_2984_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_195_7_fu_2980_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_203_9_fu_3102_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_195_9_fu_3098_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_203_s_fu_3165_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_195_s_fu_3161_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_209_1_fu_3666_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_712_ap_return) < signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_209_2_fu_3794_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_722_ap_return) < signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_209_3_fu_3922_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_732_ap_return) < signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_209_4_fu_4050_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_742_ap_return) < signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_209_5_fu_4178_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_752_ap_return) < signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_209_6_fu_4306_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_762_ap_return) < signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_209_7_fu_4434_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_772_ap_return) < signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_20_fu_1286_p2 <= (tmp_18_fu_1266_p2 or tmp_19_fu_1272_p2);
tmp_210_2_fu_3609_p3 <=
grp_image_filter_reg_int_s_fu_692_ap_return when (tmp_199_2_fu_3604_p2(0) = '1') else
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16;
tmp_210_4_fu_3633_p3 <=
grp_image_filter_reg_int_s_fu_702_ap_return when (tmp_199_4_fu_3628_p2(0) = '1') else
flag_d_min4_3_reg_6053;
tmp_210_5_fu_3505_p3 <=
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 when (tmp_199_5_fu_3500_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_672_ap_return;
tmp_210_7_fu_3529_p3 <=
flag_d_min4_7_reg_6065 when (tmp_199_7_fu_3524_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_682_ap_return;
tmp_210_9_fu_3554_p3 <=
grp_image_filter_reg_int_s_fu_672_ap_return when (tmp_199_9_fu_3548_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_692_ap_return;
tmp_210_s_fu_3582_p3 <=
grp_image_filter_reg_int_s_fu_682_ap_return when (tmp_199_s_fu_3576_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_702_ap_return;
tmp_212_1_fu_3128_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_587_ap_return) > signed(grp_image_filter_reg_int_s_fu_597_ap_return)) else "0";
tmp_212_2_fu_3616_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_697_ap_return) > signed(ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16)) else "0";
tmp_212_3_fu_3404_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_657_ap_return) > signed(grp_image_filter_reg_int_s_fu_667_ap_return)) else "0";
tmp_212_4_fu_3640_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_707_ap_return) > signed(flag_d_max4_3_reg_6059)) else "0";
tmp_212_5_fu_3512_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16) > signed(grp_image_filter_reg_int_s_fu_677_ap_return)) else "0";
tmp_212_7_fu_3536_p2 <= "1" when (signed(flag_d_max4_7_reg_6071) > signed(grp_image_filter_reg_int_s_fu_687_ap_return)) else "0";
tmp_212_9_fu_3562_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_677_ap_return) > signed(grp_image_filter_reg_int_s_fu_697_ap_return)) else "0";
tmp_212_s_fu_3590_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_687_ap_return) > signed(grp_image_filter_reg_int_s_fu_707_ap_return)) else "0";
tmp_213_3_fu_3045_p3 <=
grp_image_filter_reg_int_s_fu_557_ap_return when (tmp_202_3_fu_3039_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_567_ap_return;
tmp_216_1_fu_3698_p3 <=
flag_d_min8_3_reg_6115 when (tmp_209_1_reg_6195(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_216_2_fu_3826_p3 <=
flag_d_min8_5_reg_6249 when (tmp_209_2_reg_6269(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_216_3_fu_3954_p3 <=
flag_d_min8_7_reg_6323 when (tmp_209_3_reg_6343(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_216_4_fu_4082_p3 <=
flag_d_min8_9_reg_6397 when (tmp_209_4_reg_6417(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_216_5_fu_4210_p3 <=
tmp_211_s_reg_6471 when (tmp_209_5_reg_6491(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_216_6_fu_4338_p3 <=
tmp_211_1_reg_6545 when (tmp_209_6_reg_6565(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_216_7_fu_4466_p3 <=
tmp_211_2_reg_6619 when (tmp_209_7_reg_6639(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_217_1_fu_3707_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1) > signed(tmp_216_1_fu_3698_p3)) else "0";
tmp_217_2_fu_3835_p2 <= "1" when (signed(a0_tmp_232_1_cast_fu_3823_p1) > signed(tmp_216_2_fu_3826_p3)) else "0";
tmp_217_3_fu_3963_p2 <= "1" when (signed(a0_2_tmp_232_2_cast_fu_3951_p1) > signed(tmp_216_3_fu_3954_p3)) else "0";
tmp_217_4_fu_4091_p2 <= "1" when (signed(a0_3_tmp_232_3_cast_fu_4079_p1) > signed(tmp_216_4_fu_4082_p3)) else "0";
tmp_217_5_fu_4219_p2 <= "1" when (signed(a0_4_tmp_232_4_cast_fu_4207_p1) > signed(tmp_216_5_fu_4210_p3)) else "0";
tmp_217_6_fu_4347_p2 <= "1" when (signed(a0_5_tmp_232_5_cast_fu_4335_p1) > signed(tmp_216_6_fu_4338_p3)) else "0";
tmp_217_7_fu_4475_p2 <= "1" when (signed(a0_6_tmp_232_6_cast_fu_4463_p1) > signed(tmp_216_7_fu_4466_p3)) else "0";
tmp_21_fu_1527_p2 <= "1" when (signed(r_V_1_fu_1516_p2) > signed(ap_const_lv9_14)) else "0";
tmp_221_1_fu_3686_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_717_ap_return) > signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_221_2_fu_3814_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_727_ap_return) > signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_221_3_fu_3942_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_737_ap_return) > signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_221_4_fu_4070_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_747_ap_return) > signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_221_5_fu_4198_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_757_ap_return) > signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_221_6_fu_4326_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_767_ap_return) > signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_221_7_fu_4454_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_777_ap_return) > signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_225_2_fu_3621_p3 <=
grp_image_filter_reg_int_s_fu_697_ap_return when (tmp_212_2_fu_3616_p2(0) = '1') else
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16;
tmp_225_4_fu_3645_p3 <=
grp_image_filter_reg_int_s_fu_707_ap_return when (tmp_212_4_fu_3640_p2(0) = '1') else
flag_d_max4_3_reg_6059;
tmp_225_5_fu_3517_p3 <=
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 when (tmp_212_5_fu_3512_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_677_ap_return;
tmp_225_7_fu_3541_p3 <=
flag_d_max4_7_reg_6071 when (tmp_212_7_fu_3536_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_687_ap_return;
tmp_225_9_fu_3568_p3 <=
grp_image_filter_reg_int_s_fu_677_ap_return when (tmp_212_9_fu_3562_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_697_ap_return;
tmp_225_s_fu_3596_p3 <=
grp_image_filter_reg_int_s_fu_687_ap_return when (tmp_212_s_fu_3590_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_707_ap_return;
tmp_227_1_fu_3739_p3 <=
flag_d_max8_3_reg_6122 when (tmp_221_1_reg_6206(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_227_2_fu_3867_p3 <=
flag_d_max8_5_reg_6256 when (tmp_221_2_reg_6280(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_227_3_fu_3995_p3 <=
flag_d_max8_7_reg_6330 when (tmp_221_3_reg_6354(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_227_4_fu_4123_p3 <=
flag_d_max8_9_reg_6404 when (tmp_221_4_reg_6428(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_227_5_fu_4251_p3 <=
tmp_226_s_reg_6478 when (tmp_221_5_reg_6502(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_227_6_fu_4379_p3 <=
tmp_226_1_reg_6552 when (tmp_221_6_reg_6576(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_227_7_fu_4507_p3 <=
tmp_226_2_reg_6626 when (tmp_221_7_reg_6650(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_228_1_fu_3748_p2 <= "1" when (signed(b0_tmp_239_cast_fu_3736_p1) < signed(tmp_227_1_fu_3739_p3)) else "0";
tmp_228_2_fu_3876_p2 <= "1" when (signed(b0_tmp_239_1_cast_fu_3864_p1) < signed(tmp_227_2_fu_3867_p3)) else "0";
tmp_228_3_fu_4004_p2 <= "1" when (signed(b0_2_tmp_239_2_cast_fu_3992_p1) < signed(tmp_227_3_fu_3995_p3)) else "0";
tmp_228_4_fu_4132_p2 <= "1" when (signed(b0_3_tmp_239_3_cast_fu_4120_p1) < signed(tmp_227_4_fu_4123_p3)) else "0";
tmp_228_5_fu_4260_p2 <= "1" when (signed(b0_4_tmp_239_4_cast_fu_4248_p1) < signed(tmp_227_5_fu_4251_p3)) else "0";
tmp_228_6_fu_4388_p2 <= "1" when (signed(b0_5_tmp_239_5_cast_fu_4376_p1) < signed(tmp_227_6_fu_4379_p3)) else "0";
tmp_228_7_fu_4516_p2 <= "1" when (signed(b0_6_tmp_239_6_cast_fu_4504_p1) < signed(tmp_227_7_fu_4507_p3)) else "0";
tmp_22_fu_1533_p2 <= "1" when (signed(r_V_1_fu_1516_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_231_1_fu_3720_p2 <= "1" when (signed(flag_d_min8_3_reg_6115) < signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_231_2_fu_3848_p2 <= "1" when (signed(flag_d_min8_5_reg_6249) < signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_231_3_fu_3976_p2 <= "1" when (signed(flag_d_min8_7_reg_6323) < signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_231_4_fu_4104_p2 <= "1" when (signed(flag_d_min8_9_reg_6397) < signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_231_5_fu_4232_p2 <= "1" when (signed(tmp_211_s_reg_6471) < signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_231_6_fu_4360_p2 <= "1" when (signed(tmp_211_1_reg_6545) < signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_231_7_fu_4488_p2 <= "1" when (signed(tmp_211_2_reg_6619) < signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_232_1_fu_3725_p3 <=
flag_d_min8_3_reg_6115 when (tmp_231_1_fu_3720_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_232_2_fu_3853_p3 <=
flag_d_min8_5_reg_6249 when (tmp_231_2_fu_3848_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_232_3_fu_3981_p3 <=
flag_d_min8_7_reg_6323 when (tmp_231_3_fu_3976_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_232_4_fu_4109_p3 <=
flag_d_min8_9_reg_6397 when (tmp_231_4_fu_4104_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_232_5_fu_4237_p3 <=
tmp_211_s_reg_6471 when (tmp_231_5_fu_4232_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_232_6_fu_4365_p3 <=
tmp_211_1_reg_6545 when (tmp_231_6_fu_4360_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_232_7_fu_4493_p3 <=
tmp_211_2_reg_6619 when (tmp_231_7_fu_4488_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_233_1_fu_3783_p2 <= "1" when (signed(a0_cast_fu_3780_p1) > signed(tmp_232_1_reg_6217)) else "0";
tmp_233_2_fu_3911_p2 <= "1" when (signed(a0_2_cast_fu_3908_p1) > signed(tmp_232_2_reg_6291)) else "0";
tmp_233_3_fu_4039_p2 <= "1" when (signed(a0_3_cast_fu_4036_p1) > signed(tmp_232_3_reg_6365)) else "0";
tmp_233_4_fu_4167_p2 <= "1" when (signed(a0_4_cast_fu_4164_p1) > signed(tmp_232_4_reg_6439)) else "0";
tmp_233_5_fu_4295_p2 <= "1" when (signed(a0_5_cast_fu_4292_p1) > signed(tmp_232_5_reg_6513)) else "0";
tmp_233_6_fu_4423_p2 <= "1" when (signed(a0_6_cast_fu_4420_p1) > signed(tmp_232_6_reg_6587)) else "0";
tmp_233_7_fu_4552_p2 <= "1" when (signed(a0_7_cast_fu_4549_p1) > signed(tmp_232_7_reg_6661)) else "0";
tmp_236_1_fu_3761_p2 <= "1" when (signed(flag_d_max8_3_reg_6122) > signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_236_2_fu_3889_p2 <= "1" when (signed(flag_d_max8_5_reg_6256) > signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_236_3_fu_4017_p2 <= "1" when (signed(flag_d_max8_7_reg_6330) > signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_236_4_fu_4145_p2 <= "1" when (signed(flag_d_max8_9_reg_6404) > signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_236_5_fu_4273_p2 <= "1" when (signed(tmp_226_s_reg_6478) > signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_236_6_fu_4401_p2 <= "1" when (signed(tmp_226_1_reg_6552) > signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_236_7_fu_4529_p2 <= "1" when (signed(tmp_226_2_reg_6626) > signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_239_1_fu_3766_p3 <=
flag_d_max8_3_reg_6122 when (tmp_236_1_fu_3761_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_239_2_fu_3894_p3 <=
flag_d_max8_5_reg_6256 when (tmp_236_2_fu_3889_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_239_3_fu_4022_p3 <=
flag_d_max8_7_reg_6330 when (tmp_236_3_fu_4017_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_239_4_fu_4150_p3 <=
flag_d_max8_9_reg_6404 when (tmp_236_4_fu_4145_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_239_5_fu_4278_p3 <=
tmp_226_s_reg_6478 when (tmp_236_5_fu_4273_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_239_6_fu_4406_p3 <=
tmp_226_1_reg_6552 when (tmp_236_6_fu_4401_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_239_7_fu_4534_p3 <=
tmp_226_2_reg_6626 when (tmp_236_7_fu_4529_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_23_fu_1547_p2 <= (tmp_21_fu_1527_p2 or tmp_22_fu_1533_p2);
tmp_240_1_fu_3803_p2 <= "1" when (signed(b0_cast_50_fu_3800_p1) < signed(tmp_239_1_reg_6233)) else "0";
tmp_240_2_fu_3931_p2 <= "1" when (signed(b0_2_cast_fu_3928_p1) < signed(tmp_239_2_reg_6307)) else "0";
tmp_240_3_fu_4059_p2 <= "1" when (signed(b0_3_cast_fu_4056_p1) < signed(tmp_239_3_reg_6381)) else "0";
tmp_240_4_fu_4187_p2 <= "1" when (signed(b0_4_cast_fu_4184_p1) < signed(tmp_239_4_reg_6455)) else "0";
tmp_240_5_fu_4315_p2 <= "1" when (signed(b0_5_cast_fu_4312_p1) < signed(tmp_239_5_reg_6529)) else "0";
tmp_240_6_fu_4443_p2 <= "1" when (signed(b0_6_cast_fu_4440_p1) < signed(tmp_239_6_reg_6603)) else "0";
tmp_240_7_fu_4566_p2 <= "1" when (signed(b0_7_cast_fu_4563_p1) < signed(tmp_239_7_reg_6676)) else "0";
tmp_242_1_fu_4659_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_1_fu_140)) else "0";
tmp_242_2_fu_4665_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_2_fu_4620_p1)) else "0";
tmp_245_1_fu_4677_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_fu_164)) else "0";
tmp_245_2_fu_4683_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_2_fu_4643_p1)) else "0";
tmp_24_fu_1322_p2 <= (tmp_176_1_fu_1302_p2 or tmp_177_1_fu_1308_p2);
tmp_25_fu_1907_p2 <= (tmp_182_1_reg_5441 or tmp_184_1_reg_5447);
tmp_26_fu_4779_p2 <= (tmp22_fu_4775_p2 and tmp18_fu_4771_p2);
tmp_27_fu_1358_p2 <= (tmp_176_2_fu_1338_p2 or tmp_177_2_fu_1344_p2);
tmp_28_fu_1926_p2 <= (tmp_182_2_reg_5461 or tmp_184_2_reg_5467);
tmp_29_fu_1394_p2 <= (tmp_176_3_fu_1374_p2 or tmp_177_3_fu_1380_p2);
tmp_30_fu_1956_p2 <= (tmp_182_3_fu_1938_p2 or tmp_184_3_fu_1943_p2);
tmp_31_fu_1638_p2 <= (tmp_176_4_reg_5337 or tmp_177_4_reg_5343);
tmp_32_fu_2108_p2 <= (tmp_182_4_reg_5638 or tmp_184_4_reg_5644);
tmp_33_fu_1666_p2 <= (tmp_176_5_reg_5357 or tmp_177_5_reg_5363);
tmp_34_fu_2127_p2 <= (tmp_182_5_reg_5649 or tmp_184_5_reg_5655);
tmp_35_fu_1694_p2 <= (tmp_176_6_reg_5377 or tmp_177_6_reg_5383);
tmp_36_fu_2157_p2 <= (tmp_182_6_fu_2139_p2 or tmp_184_6_fu_2144_p2);
tmp_37_fu_1722_p2 <= (tmp_176_7_reg_5397 or tmp_177_7_reg_5403);
tmp_38_fu_2347_p2 <= (tmp_182_7_reg_5722 or tmp_184_7_reg_5728);
tmp_39_fu_1740_p2 <= "1" when (flag_val_V_assign_load_1_s_fu_1521_p3 = ap_const_lv2_0) else "0";
tmp_40_fu_1864_p2 <= (or_cond7_fu_1782_p2 or or_cond6_fu_1764_p2);
tmp_41_fu_2010_p2 <= (or_cond9_reg_5559 or or_cond8_reg_5553);
tmp_42_fu_2030_p2 <= (or_cond3_fu_1994_p2 or or_cond2_fu_1990_p2);
tmp_43_fu_3262_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_612_ap_return) < signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_44_fu_3424_p1 <= a_0_flag_d_assign_load_5_fu_3419_p3(8 - 1 downto 0);
tmp_45_fu_3428_p2 <= "1" when (signed(a_0_flag_d_assign_load_5_fu_3419_p3) < signed(ap_const_lv32_14)) else "0";
tmp_46_fu_3442_p2 <= "1" when (signed(flag_d_min8_1_reg_6029) < signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_47_fu_3447_p3 <=
flag_d_min8_1_reg_6029 when (tmp_46_fu_3442_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_48_fu_3454_p1 <= tmp_47_fu_3447_p3(8 - 1 downto 0);
tmp_49_fu_3655_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_cast_fu_3652_p1) > signed(tmp_47_reg_6083)) else "0";
tmp_50_fu_4583_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(tmp_79_reg_6697));
tmp_51_fu_4588_p2 <= "1" when (unsigned(a0_7_tmp_232_7_reg_6691) > unsigned(tmp_50_fu_4583_p2)) else "0";
tmp_52_fu_4647_p2 <= "0" when (core_win_val_1_V_1_fu_152 = ap_const_lv16_0) else "1";
tmp_53_fu_4600_p2 <= "1" when (unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31) > unsigned(ap_const_lv11_6)) else "0";
tmp_54_fu_4689_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_0_fu_148)) else "0";
tmp_55_fu_4695_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_2_fu_4623_p1)) else "0";
tmp_56_fu_3703_p1 <= tmp_216_1_fu_3698_p3(8 - 1 downto 0);
tmp_57_fu_3732_p1 <= tmp_232_1_fu_3725_p3(8 - 1 downto 0);
tmp_58_fu_3831_p1 <= tmp_216_2_fu_3826_p3(8 - 1 downto 0);
tmp_59_fu_3860_p1 <= tmp_232_2_fu_3853_p3(8 - 1 downto 0);
tmp_5_fu_796_p2 <= std_logic_vector(unsigned(tmp_fu_782_p1) + unsigned(ap_const_lv11_4));
tmp_60_fu_3959_p1 <= tmp_216_3_fu_3954_p3(8 - 1 downto 0);
tmp_61_fu_3988_p1 <= tmp_232_3_fu_3981_p3(8 - 1 downto 0);
tmp_62_fu_4087_p1 <= tmp_216_4_fu_4082_p3(8 - 1 downto 0);
tmp_63_fu_4116_p1 <= tmp_232_4_fu_4109_p3(8 - 1 downto 0);
tmp_64_fu_4215_p1 <= tmp_216_5_fu_4210_p3(8 - 1 downto 0);
tmp_65_fu_4244_p1 <= tmp_232_5_fu_4237_p3(8 - 1 downto 0);
tmp_66_fu_4343_p1 <= tmp_216_6_fu_4338_p3(8 - 1 downto 0);
tmp_67_fu_3268_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_617_ap_return) > signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_68_fu_3458_p3 <=
flag_d_max8_1_reg_6036 when (tmp_67_reg_6048(0) = '1') else
flag_d_assign_reg_6011;
tmp_69_fu_3467_p2 <= "1" when (signed(tmp_68_fu_3458_p3) > signed(ap_const_lv32_FFFFFFEC)) else "0";
tmp_70_fu_3481_p2 <= "1" when (signed(flag_d_max8_1_reg_6036) > signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_71_fu_3486_p3 <=
flag_d_max8_1_reg_6036 when (tmp_70_fu_3481_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_72_fu_3675_p2 <= "1" when (signed(b0_cast_fu_3672_p1) < signed(tmp_71_reg_6099)) else "0";
tmp_73_fu_4653_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_0_fu_136)) else "0";
tmp_74_fu_4671_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_0_fu_160)) else "0";
tmp_75_fu_4372_p1 <= tmp_232_6_fu_4365_p3(8 - 1 downto 0);
tmp_77_fu_4471_p1 <= tmp_216_7_fu_4466_p3(8 - 1 downto 0);
tmp_78_fu_4500_p1 <= tmp_232_7_fu_4493_p3(8 - 1 downto 0);
tmp_79_fu_4571_p3 <=
tmp_95_reg_6681 when (tmp_240_7_fu_4566_p2(0) = '1') else
tmp_96_reg_6686;
tmp_7_fu_813_p2 <= "1" when (unsigned(p_s_reg_504) < unsigned(tmp_reg_5098)) else "0";
tmp_80_fu_3463_p1 <= tmp_68_fu_3458_p3(9 - 1 downto 0);
tmp_81_fu_3493_p1 <= tmp_71_fu_3486_p3(9 - 1 downto 0);
tmp_82_fu_3744_p1 <= tmp_227_1_fu_3739_p3(9 - 1 downto 0);
tmp_83_fu_3773_p1 <= tmp_239_1_fu_3766_p3(9 - 1 downto 0);
tmp_84_fu_3872_p1 <= tmp_227_2_fu_3867_p3(9 - 1 downto 0);
tmp_85_fu_3901_p1 <= tmp_239_2_fu_3894_p3(9 - 1 downto 0);
tmp_86_fu_4000_p1 <= tmp_227_3_fu_3995_p3(9 - 1 downto 0);
tmp_87_fu_4029_p1 <= tmp_239_3_fu_4022_p3(9 - 1 downto 0);
tmp_88_fu_4128_p1 <= tmp_227_4_fu_4123_p3(9 - 1 downto 0);
tmp_89_fu_4157_p1 <= tmp_239_4_fu_4150_p3(9 - 1 downto 0);
tmp_8_fu_818_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_5)) else "0";
tmp_90_fu_4256_p1 <= tmp_227_5_fu_4251_p3(9 - 1 downto 0);
tmp_91_fu_4285_p1 <= tmp_239_5_fu_4278_p3(9 - 1 downto 0);
tmp_92_fu_4384_p1 <= tmp_227_6_fu_4379_p3(9 - 1 downto 0);
tmp_93_fu_4413_p1 <= tmp_239_6_fu_4406_p3(9 - 1 downto 0);
tmp_94_fu_4512_p1 <= tmp_227_7_fu_4507_p3(9 - 1 downto 0);
tmp_95_fu_4541_p1 <= b0_7_fu_4522_p3(8 - 1 downto 0);
tmp_96_fu_4545_p1 <= tmp_239_7_fu_4534_p3(8 - 1 downto 0);
tmp_97_fu_888_p4 <= p_2_phi_fu_519_p4(10 downto 2);
tmp_9_fu_824_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_6)) else "0";
tmp_fu_782_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_s_fu_790_p2 <= std_logic_vector(unsigned(tmp_15_fu_786_p1) + unsigned(ap_const_lv11_4));
end behav;
| gpl-3.0 | 8f4c36a61cc78e6e40f1029dbfa4447d | 0.623104 | 2.384503 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/vhdl/image_filter_mul_8ns_6ns_13_3.vhd | 2 | 2,696 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_mul_8ns_6ns_13_3_MAC3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(13 - 1 downto 0));
end entity;
architecture behav of image_filter_mul_8ns_6ns_13_3_MAC3S_0 is
signal tmp_product : std_logic_vector(13 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(13 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(13 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 13));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_mul_8ns_6ns_13_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_mul_8ns_6ns_13_3 is
component image_filter_mul_8ns_6ns_13_3_MAC3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
image_filter_mul_8ns_6ns_13_3_MAC3S_0_U : component image_filter_mul_8ns_6ns_13_3_MAC3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | f5c29e9f4917f87929f04d44fdc66aaf | 0.549703 | 3.198102 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/logan.vhd | 1 | 16,907 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| gpl-2.0 | 88a63841598999cf172ddca94392c669 | 0.497368 | 3.864457 | false | false | false | false |
laurocruz/snakes_vhdl | src/snake_lib/colision.vhd | 1 | 1,617 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY colision IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10);
PORT (snake_body : IN int_array;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC;
gmap : OUT STD_LOGIC_VECTOR(0 to N*M-1);
lost : OUT STD_LOGIC);
END colision;
ARCHITECTURE Behavior OF colision IS
BEGIN
PROCESS(snake_body(0),reset)
variable i : integer range 0 to 255;
variable index : integer range 0 to M*N;
variable outl : STD_LOGIC;
BEGIN
IF (reset = '1') THEN
outl := '0';
ELSE
i := 1;
outl := '0';
WHILE (i < N*M and not(snake_body(i) = -1) and outl = '0') LOOP
IF (snake_body(0) = snake_body(i)) THEN
outl := '1';
END IF;
i := i + 1;
END LOOP;
IF (outl = '0') THEN
IF (dir = "00") THEN
IF (snake_body(0) > M*N-1) THEN
outl := '1';
END IF;
ELSIF (dir = "01") THEN
IF (snake_body(0) mod M = 0 and snake_body(1) mod M = (M-1)) THEN
outl := '1';
END IF;
ELSIF (dir = "10") THEN
IF (snake_body(0) mod M = (M-1) and snake_body(1) mod M = 0) THEN
outl := '1';
END IF;
ELSE
IF (snake_body(0) < 0) THEN
outl := '1';
END IF;
END IF;
END IF;
END IF;
IF (outl = '0') THEN
i := 0;
WHILE (i < M*N and not(snake_body(i) = -1)) LOOP
index := snake_body(i);
gmap(index) <= '1';
i := i + 1;
END LOOP;
END IF;
lost <= outl;
END PROCESS;
END Behavior;
| mit | 34118d8847598aebae058766b8109ff7 | 0.527228 | 2.623377 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/can/can.vhd | 1 | 6,902 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: can
-- File: can.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: CAN component declartions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package can is
component can_mod
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic);
end component;
component can_oc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end component;
component can_mc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end component;
component can_rd
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end component;
component canmux
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end component;
-----------------------------------------------------------------------------
-- interface type declarations for can controller
-----------------------------------------------------------------------------
type can_in_type is record
rx: std_logic_vector(1 downto 0); -- receive lines
end record;
type can_out_type is record
tx: std_logic_vector(1 downto 0); -- transmit lines
en: std_logic_vector(1 downto 0); -- transmit enables
end record;
-----------------------------------------------------------------------------
-- component declaration for grcan controller
-----------------------------------------------------------------------------
component grcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
singleirq: integer := 0; -- single irq output
txchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 1 channels
ptrwidth: integer range 16 to 16 := 16);-- 16 to 64k messages
-- 2k to 8M bits
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
-----------------------------------------------------------------------------
-- component declaration for grhcan controller
-----------------------------------------------------------------------------
component grhcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
txchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
rxchannels: integer range 1 to 1 := 1; -- 1 to 16 channels
ptrwidth: integer range 16 to 16 := 16; -- 16 to 64k messages
-- 2k to 8 m bits
singleirq: Integer := 0; -- single irq output
version: Integer := 0); -- 0=516, 1=524
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
end;
| gpl-2.0 | a6ffc7a460a3717a1dbcbd313638c12a | 0.47479 | 4.170393 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_pntr.vhd | 4 | 22,217 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic ; --
bd_eq : out std_logic
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
attribute mark_debug of ch1_fetch_address_i : signal is "true";
attribute mark_debug of ch2_fetch_address_i : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
EQUAL_BD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
bd_eq <= '0';
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
bd_eq <= '0';
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
bd_eq <= '1';
end if;
end if;
end process EQUAL_BD;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
bd_eq <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
| gpl-3.0 | 47f0c56ff41ae336478dc066e86f4a85 | 0.420534 | 4.795381 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/altera_mf/clkgen_altera_mf.vhd | 1 | 7,109 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 939657f67554d9b7032a33f0439223ed | 0.591926 | 3.476284 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/chips/cl_timer_data.vhd | 1 | 16,324 | --------------------------------------------------------------------------------
--
-- Title : cl_timer_data.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Test example for DS1302 timer settings and LCD1602 RAM loading
-- DS1302 -> LCD1602
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity cl_timer_data is
generic (
TIME_SECS : in integer range 0 to 59:=12; --! Seconds
TIME_MINS : in integer range 0 to 59:=35; --! Minutes
TIME_HRS : in integer range 0 to 23:=17; --! Hours
TIME_DTS : in integer range 0 to 30:=13; --! Dates
TIME_MTHS : in integer range 0 to 11:=07; --! Months
TIME_DAYS : in integer range 0 to 59:=17; --! Days
TIME_YRS : in integer range 0 to 99:=16; --! Years
TD : in time := 1 ns --! simulation time;
);
port(
---- Global signals ----
reset : in std_logic; --! asycnchronous reset
clk : in std_logic; --! clock 50 MHz
restart : in std_logic; --! restart timer
---- DS1302 signals ----
addr : out std_logic_vector(7 downto 0); --! address for timer
data_o : out std_logic_vector(7 downto 0); --! input data (to timer)
data_i : in std_logic_vector(7 downto 0); --! output data (from timer)
data_v : in std_logic; --! valid data (from timer)
ready : in std_logic; --! timer is ready for data
enable : out std_logic; --! timer enable
---- LCD1602 signals ----
load_ena : out std_logic; --! enable writing to LCD RAM
load_dat : out std_logic_vector(7 downto 0); --! data to LCD RAM
load_addr : out std_logic_vector(4 downto 0) --! address to LCD RAM
);
end cl_timer_data;
architecture cl_timer_data of cl_timer_data is
signal sec0_lcd : std_logic_vector(3 downto 0);
signal sec1_lcd : std_logic_vector(3 downto 0);
signal min0_lcd : std_logic_vector(3 downto 0);
signal min1_lcd : std_logic_vector(3 downto 0);
signal hrs0_lcd : std_logic_vector(3 downto 0);
signal hrs1_lcd : std_logic_vector(3 downto 0);
signal dts0_lcd : std_logic_vector(3 downto 0);
signal dts1_lcd : std_logic_vector(3 downto 0);
signal mth0_lcd : std_logic_vector(3 downto 0);
signal mth1_lcd : std_logic_vector(3 downto 0);
signal days_lcd : std_logic_vector(3 downto 0);
signal yrs0_lcd : std_logic_vector(3 downto 0);
signal yrs1_lcd : std_logic_vector(3 downto 0);
signal data_rom : std_logic_vector(3 downto 0);
signal time_addr : std_logic_vector(3 downto 0);
signal timer_v : std_logic_vector(3 downto 0);
type tdata_timer is (secs, mins, hours, dates, months, days, years, nulls); --days,
signal time_code : tdata_timer;
signal time_codex : tdata_timer;
signal time_set : std_logic_vector(4 downto 0);
signal time_get : std_logic_vector(3 downto 0);
signal mode : std_logic;
signal timer_conf : std_logic;
signal readyz : std_logic;
signal ena : std_logic;
signal load : std_logic;
signal lcd_addr : std_logic_vector(4 downto 0);
---------------- INTEGER TO STD_LOGIC_VECTOR TO BCD CONVERTER ----------------
constant n : integer:=8;
constant q : integer:=2;
function to_bcd ( bin : std_logic_vector((n-1) downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable j : integer:=1;
variable bcd : std_logic_vector(((4*q)-1) downto 0) := (others => '0');
variable bint : std_logic_vector((n-1) downto 0) := bin;
begin
for i in 0 to n-1 loop -- repeating 8 times.
bcd(((4*q)-1) downto 1) := bcd(((4*q)-2) downto 0); --shifting the bits.
bcd(0) := bint(n-1);
bint((n-1) downto 1) := bint((n-2) downto 0);
bint(0) :='0';
l1: for j in 1 to q loop
if(i < n-1 and bcd(((4*j)-1) downto ((4*j)-4)) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(((4*j)-1) downto ((4*j)-4)) := bcd(((4*j)-1) downto ((4*j)-4)) + "0011";
end if;
end loop l1;
end loop;
return bcd;
end to_bcd;
constant temp_secs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_SECS, 8)); -- Seconds
constant temp_mins : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MINS, 8)); -- Minutes
constant temp_hrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_HRS, 8)); -- Hours
constant temp_dts : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DTS, 8)); -- Dates
constant temp_mths : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_MTHS, 8)); -- Months
constant temp_days : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_DAYS, 8)); -- Days
constant temp_yrs : std_logic_vector(7 downto 0):=to_bcd(conv_std_logic_vector(TIME_YRS, 8)); -- Years
begin
readyz <= not ready after td when rising_edge(clk);
ena <= ready and readyz after td when rising_edge(clk);
enable <= ena when rising_edge(clk);
--addr <= x"8" & time_addr after td when rising_edge(clk);
pr_addr: process(clk, reset) is
begin
if (reset = '0') then
addr <= x"00";
elsif (rising_edge(clk)) then
addr <= x"8" & time_addr after td;
end if;
end process;
load_dat <= x"3" & data_rom after td when rising_edge(clk);
load_addr <= lcd_addr after td when rising_edge(clk);
load_ena <= load after td when rising_edge(clk);
timer_v <= timer_v(2 downto 0) & data_v after td when rising_edge(clk);
---------------- TIMER CONFIGURE DATA ----------------
pr_conf: process(clk, reset) is
begin
if (reset = '0') then
data_o <= x"00";
time_set <= "00000";
timer_conf <= '0';
elsif (rising_edge(clk)) then
if (restart = '0') then
time_set <= "00000" after td;
end if;
timer_conf <= time_set(4) after td;
if (ena = '1') then
if time_set(4) = '0' then
time_set <= time_set + '1' after td;
else
null;
end if;
end if;
case time_set(3 downto 0) is
when x"1" => data_o <= x"00"; -- WP: (7) bit should be '0' to enable writing data
when x"2" => data_o <= temp_yrs;--temp_yrs;
when x"3" => data_o <= temp_days;
when x"4" => data_o <= temp_mths;
when x"5" => data_o <= temp_dts;
when x"6" => data_o <= temp_hrs;
when x"7" => data_o <= temp_mins;
when x"8" => data_o <= temp_secs; -- CH: (7) bit should be '0' to start clocking
when others => data_o <= x"80"; --null;
end case;
end if;
end process;
---------------- TIMER GETTING DATA ----------------
pr_timeget: process(clk, reset) is
begin
if (reset = '0') then
time_get <= x"0";
mode <= '1';
elsif (rising_edge(clk)) then
if ((ena = '1') and (timer_conf = '1')) then
time_get <= time_get + '1' after td;
mode <= not mode after td;
end if;
end if;
end process;
pr_rom_load: process(clk, reset) is
begin
if (reset = '0') then
load <= '0';
elsif (rising_edge(clk)) then
if (timer_conf = '0') then
load <= '0' after td;
else
load <= timer_v(3) after td;
end if;
end if;
end process;
---------------- TIMER READING DATA ----------------
pr_readback: process(clk, reset) is
begin
if (reset = '0') then
time_addr <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
time_addr <= x"0" after td;
end if;
if (timer_conf = '0') then
case time_set(3 downto 0) is
when x"1" => time_addr <= x"E"; -- set write protect
when x"2" => time_addr <= x"C"; -- year
when x"3" => time_addr <= x"A"; -- day
when x"4" => time_addr <= x"8"; -- month
when x"5" => time_addr <= x"6"; -- date
when x"6" => time_addr <= x"4"; -- hour
when x"7" => time_addr <= x"2"; -- minute
when x"8" => time_addr <= x"0"; -- second
when others => time_addr <= x"E";
end case;
else
case time_get is
when x"1" | x"2" => time_addr <= x"D"; -- year
when x"3" | x"4" => time_addr <= x"B"; -- day
when x"5" | x"6" => time_addr <= x"9"; -- month
when x"7" | x"8" => time_addr <= x"7"; -- date
when x"9" | x"A" => time_addr <= x"5"; -- hour
when x"B" | x"C" => time_addr <= x"3"; -- minute
when x"D" | x"E" => time_addr <= x"1"; -- second
when others => null;
end case;
end if;
end if;
end process;
---------------- TIMER CODES ----------------
time_codex <= secs when time_addr(3 downto 1) = "000" else
mins when time_addr(3 downto 1) = "001" else
hours when time_addr(3 downto 1) = "010" else
dates when time_addr(3 downto 1) = "011" else
months when time_addr(3 downto 1) = "100" else
days when time_addr(3 downto 1) = "101" else
years when time_addr(3 downto 1) = "110" else
nulls;
time_code <= time_codex after td when rising_edge(clk);
---------------- TIMER WRITE ROM ----------------
pr_data_rom: process(clk, reset) is
begin
if (reset = '0') then
data_rom <= x"0";
elsif (rising_edge(clk)) then
if (restart = '0') then
data_rom <= x"0" after td;
end if;
if (timer_v(2) = '1') then
case time_code is
when secs =>
if mode = '0' then
lcd_addr <= "11100" after td;
data_rom <= sec0_lcd after td;
else
lcd_addr <= "11011" after td;
data_rom <= sec1_lcd after td;
end if;
when mins =>
if mode = '0' then
lcd_addr <= "11001" after td;
data_rom <= min0_lcd after td;
else
lcd_addr <= "11000" after td;
data_rom <= min1_lcd after td;
end if;
when hours =>
if mode = '0' then
lcd_addr <= "10110" after td;
data_rom <= hrs0_lcd after td;
else
lcd_addr <= "10101" after td;
data_rom <= hrs1_lcd after td;
end if;
when dates =>
if mode = '0' then
lcd_addr <= "00110" after td;
data_rom <= dts0_lcd after td;
else
lcd_addr <= "00101" after td;
data_rom <= dts1_lcd after td;
end if;
when months =>
if mode = '0' then
lcd_addr <= "01001" after td;
data_rom <= mth0_lcd after td;
else
lcd_addr <= "01000" after td;
data_rom <= mth1_lcd after td;
end if;
-- when days =>
-- data_rom <= days_lcd after td;
when years =>
if mode = '0' then
lcd_addr <= "01100" after td;
data_rom <= yrs0_lcd after td;
else
lcd_addr <= "01011" after td;
data_rom <= yrs1_lcd after td;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
---------------- SECONDS LSB ----------------
pr_conv_sec0: process(clk, reset) is
begin
if (reset = '0') then
sec0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
sec0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- SECONDS MSB ----------------
pr_conv_sec1: process(clk, reset) is
begin
if (reset = '0') then
sec1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = secs)) then
case data_i(6 downto 4) is
when "000" => sec1_lcd <= x"0" after td;
when "001" => sec1_lcd <= x"1" after td;
when "010" => sec1_lcd <= x"2" after td;
when "011" => sec1_lcd <= x"3" after td;
when "100" => sec1_lcd <= x"4" after td;
when "101" => sec1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MINUTES LSB ----------------
pr_conv_min0: process(clk, reset) is
begin
if (reset = '0') then
min0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
min0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MINUTES MSB ----------------
pr_conv_min1: process(clk, reset) is
begin
if (reset = '0') then
min1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = mins)) then
case data_i(6 downto 4) is
when "000" => min1_lcd <= x"0" after td;
when "001" => min1_lcd <= x"1" after td;
when "010" => min1_lcd <= x"2" after td;
when "011" => min1_lcd <= x"3" after td;
when "100" => min1_lcd <= x"4" after td;
when "101" => min1_lcd <= x"5" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DATES LSB ----------------
pr_conv_dts0: process(clk, reset) is
begin
if (reset = '0') then
dts0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
dts0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- DATES MSB ----------------
pr_conv_dts1: process(clk, reset) is
begin
if (reset = '0') then
dts1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = dates)) then
case data_i(5 downto 4) is
when "00" => dts1_lcd <= x"0" after td;
when "01" => dts1_lcd <= x"1" after td;
when "10" => dts1_lcd <= x"2" after td;
when "11" => dts1_lcd <= x"3" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- MONTHS LSB ----------------
pr_conv_mth0: process(clk, reset) is
begin
if (reset = '0') then
mth0_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
mth0_lcd <= data_i(3 downto 0) after td;
end if;
end if;
end process;
---------------- MONTHS MSB ----------------
pr_conv_mth1: process(clk, reset) is
begin
if (reset = '0') then
mth1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = months)) then
case data_i(4) is
when '0' => mth1_lcd <= x"0" after td;
when '1' => mth1_lcd <= x"1" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- DAYS ----------------
pr_conv_days: process(clk, reset) is
begin
if (reset = '0') then
days_lcd <= x"0";
elsif (rising_edge(clk)) then
if (time_code = days) then
case data_i(2 downto 0) is
when "000" => days_lcd <= x"1" after td;
when "001" => days_lcd <= x"2" after td;
when "010" => days_lcd <= x"3" after td;
when "011" => days_lcd <= x"4" after td;
when "100" => days_lcd <= x"5" after td;
when "101" => days_lcd <= x"6" after td;
when "110" => days_lcd <= x"7" after td;
--when "111" => days_lcd <= x"7" after td;
when others => null;
end case;
end if;
end if;
end process;
---------------- HOURS LSB ----------------
pr_conv_hrs: process(clk, reset) is
begin
if (reset = '0') then
hrs0_lcd <= x"0";
hrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = hours)) then
hrs0_lcd <= data_i(3 downto 0) after td;
hrs1_lcd <= data_i(7 downto 4) after td;
end if;
end if;
end process;
---------------- YEARS LSB ----------------
pr_conv_yrs: process(clk, reset) is
begin
if (reset = '0') then
yrs0_lcd <= x"0";
yrs1_lcd <= x"0";
elsif (rising_edge(clk)) then
if ((data_v = '1') and (time_code = years)) then
yrs0_lcd <= data_i(3 downto 0) after td;
yrs1_lcd <= data_i(7 downto 4) after td;
-- case data_i(3 downto 0) is
-- when x"0" => yrs0_lcd <= x"0" after td;
-- when x"1" => yrs0_lcd <= x"1" after td;
-- when x"2" => yrs0_lcd <= x"2" after td;
-- when x"3" => yrs0_lcd <= x"3" after td;
-- when x"4" => yrs0_lcd <= x"4" after td;
-- when x"5" => yrs0_lcd <= x"5" after td;
-- when x"6" => yrs0_lcd <= x"6" after td;
-- when x"7" => yrs0_lcd <= x"7" after td;
-- when x"8" => yrs0_lcd <= x"8" after td;
-- when x"9" => yrs0_lcd <= x"9" after td;
-- when others => null;
-- end case;
-- case data_i(7 downto 4) is
-- when x"0" => yrs1_lcd <= x"0" after td;
-- when x"1" => yrs1_lcd <= x"1" after td;
-- when x"2" => yrs1_lcd <= x"2" after td;
-- when x"3" => yrs1_lcd <= x"3" after td;
-- when x"4" => yrs1_lcd <= x"4" after td;
-- when x"5" => yrs1_lcd <= x"5" after td;
-- when x"6" => yrs1_lcd <= x"6" after td;
-- when x"7" => yrs1_lcd <= x"7" after td;
-- when x"8" => yrs1_lcd <= x"8" after td;
-- when x"9" => yrs1_lcd <= x"9" after td;
-- when others => null;
-- end case;
end if;
end if;
end process;
end cl_timer_data; | mit | fc0ee4e102d7a77113238c9a8fb7ed76 | 0.547782 | 2.665578 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-pci-xc5v/config.vhd | 1 | 9,775 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 2;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 16;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 4c24301d67ff65b9184322bfdac0c558 | 0.653197 | 3.511135 | false | false | false | false |
borti4938/sd2snes | verilog/sd2snes_sdd1/Test_Top_SDD1.vhd | 2 | 50,000 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.03.2018 22:42:12
-- Design Name:
-- Module Name: Test_FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Top_SDD1 is
-- Port ( );
end Test_Top_SDD1;
architecture Behavioral of Test_Top_SDD1 is
constant SD2SNES_PERIOD : time := 10.416 ns;
constant CLK_PERIOD : time := 46.56 ns;
constant PHI2_PERIOD : time := 6*CLK_PERIOD;
constant tBAS : time := 33 ns;
constant tADS : time := 30 ns;
constant tMDS : time := 30 ns;
constant tLATCH : time := 25 ns;
constant tDECODER : time := 25 ns;
constant ROM_tACCESS : time := 70 ns;
COMPONENT SDD1
Port( MCLK : in STD_LOGIC;
SNES_CPU_CLK : in STD_LOGIC;
SNES_REFRESH : in STD_LOGIC;
RESET : in STD_LOGIC;
SRAM_CS : out STD_LOGIC;
ROM_OE : out STD_LOGIC;
ROM_CS : out STD_LOGIC;
ROM_ADDR : out STD_LOGIC_VECTOR (21 downto 0);
ROM_DATA : in STD_LOGIC_VECTOR (15 downto 0);
SNES_ADDR : in STD_LOGIC_VECTOR (23 downto 0);
SNES_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
SNES_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
SNES_RD : in STD_LOGIC;
SNES_WR : in STD_LOGIC;
SNES_WR_End : in STD_LOGIC );
END COMPONENT;
type bit_vector_file is file of bit_vector;
type bytes_file is file of integer;
file comp_data : bit_vector_file;
file descomp_data : bytes_file;
shared variable Size : integer := 0;
type ROM_Array_t is array(65535 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal MaskROM_0 : ROM_Array_t := (others => (others => '0'));
signal MaskROM_1 : ROM_Array_t := (others => (others => '0'));
signal SD2SNES_CLK : STD_LOGIC := '0';
signal MCLK : STD_LOGIC := '0';
signal CPU_CLK : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
signal SRAM_CS : STD_LOGIC := '1';
signal ROM_OE : STD_LOGIC := '1';
signal ROM_CS : STD_LOGIC := '1';
signal ROM_ADDR : STD_LOGIC_VECTOR(21 downto 0) := (others => '0');
signal ROM_DATA : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal SNES_RD : STD_LOGIC := '1';
signal SNES_WR : STD_LOGIC := '1';
signal SNES_WR_Strobe : STD_LOGIC := '0';
signal SNES_ADDR : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal SNES_DATA_IN : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal SNES_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal CPU_RD_CYCLE : STD_LOGIC := '0';
signal CPU_WR_CYCLE : STD_LOGIC := '0';
signal CPU_ADDR : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal CPU_BANK : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal CPU_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => 'Z');
signal CPU_VDA : STD_LOGIC := '0';
signal CPU_VPA : STD_LOGIC := '0';
signal ROM_Data_tready : STD_LOGIC := '0';
signal ROM_Data_tvalid : STD_LOGIC := '0';
signal ROM_Data_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal DMA_Data_tvalid_Pipe : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal DMA_Data_tvalid : STD_LOGIC := '0';
signal DMA_Data_dword : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal Instruction_Addr : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal Compressed_Addr : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal Compressed_Size : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal Start_Decompression : STD_LOGIC := '0';
signal End_Decompression : STD_LOGIC := '0';
begin
uut : SDD1
Port map(MCLK => SD2SNES_CLK,
RESET => RESET,
SNES_CPU_CLK => CPU_CLK,
SNES_REFRESH => '0',
SRAM_CS => SRAM_CS,
ROM_OE => ROM_OE,
ROM_CS => ROM_CS,
ROM_ADDR => ROM_ADDR,
ROM_DATA => ROM_DATA,
SNES_ADDR => SNES_ADDR,
SNES_DATA_IN => SNES_DATA_IN,
SNES_DATA_OUT => SNES_DATA_OUT,
SNES_RD => SNES_RD,
SNES_WR => SNES_WR,
SNES_WR_End => SNES_WR_Strobe );
Process
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
Begin
--Size := 4194304;
--file_open(comp_data, "StarOcean.smc", READ_MODE);
--Size := 3072;
--file_open(comp_data, "sdd1_chunk_0000.bin", READ_MODE);
--Size := 4034;
--file_open(comp_data, "sdd1_chunk_1100.bin", READ_MODE);
Size := 6144;
file_open(comp_data, "sdd1_chunk_0xFED27F.bin", READ_MODE);
--Size := 2084;
--file_open(comp_data, "sdd1_chunk_0xFFD0AB.bin", READ_MODE);
--Size := 768;
--file_open(comp_data, "sdd1_chunk_0xDE84AC.bin", READ_MODE);
--Size := 896;
--file_open(comp_data, "sdd1_chunk_0xDE9AF5.bin", READ_MODE);
file_open(descomp_data, "StarOcean_core.smc", WRITE_MODE);
-- read full ROM from file to memory
for i in 0 to (Size/2)-1 loop
-- read word from file
if not endfile(comp_data) then
read(comp_data, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
MaskROM_0(i)(7 downto 0) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
end if;
read(comp_data, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
MaskROM_0(i)(15 downto 8) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
end if;
end if;
wait for 1ps;
end loop;
-- for i in 0 to 1048575 loop
-- -- read word from file
-- if not endfile(comp_data) then
-- read(comp_data, next_vector, actual_len);
-- if actual_len > next_vector'length then
-- report "vector too long";
-- else
-- MaskROM_1(i)(7 downto 0) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
-- end if;
-- read(comp_data, next_vector, actual_len);
-- if actual_len > next_vector'length then
-- report "vector too long";
-- else
-- MaskROM_1(i)(15 downto 8) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
-- end if;
-- end if;
-- wait for 1 ps;
-- end loop;
-- begin reset
RESET <= '0';
wait for 1 us;
RESET <= '1';
wait until falling_edge(MCLK);
wait for 100 ns;
wait until falling_edge(CPU_CLK);
wait for (PHI2_PERIOD-CLK_PERIOD/2);
-- decompress from $DBA078, size $0C00, code $C0238E
Instruction_Addr <= X"C0238E";
--Compressed_Addr <= X"DBA078";
Compressed_Addr <= X"C00000";
Compressed_Size <= conv_std_logic_Vector(Size, 16);
Start_Decompression <= '1';
wait until (End_Decompression = '1');
Start_Decompression <= '0';
--assert false report "NONE. End of simulation." severity failure;
wait;
End Process;
-- process to generate instructions to SDD1 core from real ROM
Process
variable Instruction_Addr_i : STD_LOGIC_VECTOR(23 downto 0);
Begin
wait until (Start_Decompression = '1');
SNES_WR_Strobe <= '0';
End_Decompression <= '0';
Instruction_Addr_i := Instruction_Addr;
-- STA $4800 = $01
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STX $4302 = $A078
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 4
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STA $4304 = $DB
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STX $4305 = $0C00
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 4
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STA $4801 = $01
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHA
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2 (SLOW)
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PLA
Instruction_Addr_i := Instruction_Addr_i+1;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3 (SLOW)
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- STA $420B = $01
Instruction_Addr_i := Instruction_Addr_i+1;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STZ $4800 = $00
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA pre-sync (0 to 7 cycles)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA setup (8 cycles)
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA transfer
for i in 1 to conv_integer(Compressed_Size) loop
DMA_Data_tvalid <= '0';
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
DMA_Data_tvalid <= '1';
wait until falling_edge(MCLK);
end loop;
SNES_ADDR <= X"C00000";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
DMA_Data_tvalid <= '0';
End_Decompression <= '1';
wait until (Start_Decompression = '0');
End Process;
-- read from MaskROM
process( ROM_OE, ROM_CS, ROM_ADDR )
Begin
if( ROM_CS = '0' AND ROM_OE = '0' ) then
ROM_DATA <= MaskROM_0(conv_integer(ROM_ADDR)) after ROM_tACCESS;
else
ROM_DATA <= (others => 'Z') after 15 ns;
end if;
End Process;
-- output data file
process( SD2SNES_CLK )
variable valor : integer;
variable DMA_Data_Idx : integer := 0;
begin
if rising_edge( SD2SNES_CLK ) then
DMA_Data_tvalid_Pipe <= DMA_Data_tvalid_Pipe(0) & DMA_Data_tvalid;
if( DMA_Data_tvalid_Pipe = "01" ) then
if( DMA_Data_Idx = 3 ) then
-- write word to disk
valor := conv_integer(SNES_DATA_OUT & DMA_Data_dword(31 downto 8));
write(descomp_data, valor);
DMA_Data_Idx := 0;
else
DMA_Data_dword <= SNES_DATA_OUT & DMA_Data_dword(31 downto 8);
DMA_Data_Idx := DMA_Data_Idx + 1;
end if;
end if;
end if;
end process;
-- clock generator
Process
Begin
MCLK <= '0';
wait for CLK_PERIOD/2;
MCLK <= '1';
wait for CLK_PERIOD/2;
End Process;
Process
Begin
CPU_CLK <= '1';
wait for PHI2_PERIOD/2;
CPU_CLK <= '0';
wait for PHI2_PERIOD/2;
End Process;
Process
Begin
wait for 3ns;
loop
SD2SNES_CLK <= '1';
wait for SD2SNES_PERIOD/2;
SD2SNES_CLK <= '0';
wait for SD2SNES_PERIOD/2;
end loop;
End Process;
end Behavioral;
| gpl-2.0 | 43e0f3451cf2b015fce409c727fec8bd | 0.479 | 2.600916 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/boards/terasic-de4/ddr2ctrl.vhd | 1 | 38,922 | -- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v13.1%
-- GENERATION: XML
-- ddr2ctrl.vhd
-- Generated using ACDS version 13.1 162 at 2013.12.06.15:39:20
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end entity ddr2ctrl;
architecture rtl of ddr2ctrl is
component ddr2ctrl_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rdn : in std_logic := 'X'; -- rdn
oct_rup : in std_logic := 'X' -- rup
);
end component ddr2ctrl_0002;
begin
ddr2ctrl_inst : component ddr2ctrl_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
avl_ready => avl_ready, -- avl.waitrequest_n
avl_burstbegin => avl_burstbegin, -- .beginbursttransfer
avl_addr => avl_addr, -- .address
avl_rdata_valid => avl_rdata_valid, -- .readdatavalid
avl_rdata => avl_rdata, -- .readdata
avl_wdata => avl_wdata, -- .writedata
avl_be => avl_be, -- .byteenable
avl_read_req => avl_read_req, -- .read
avl_write_req => avl_write_req, -- .write
avl_size => avl_size, -- .burstcount
local_init_done => local_init_done, -- status.local_init_done
local_cal_success => local_cal_success, -- .local_cal_success
local_cal_fail => local_cal_fail, -- .local_cal_fail
oct_rdn => oct_rdn, -- oct.rdn
oct_rup => oct_rup -- .rup
);
end architecture rtl; -- of ddr2ctrl
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr2_emif" version="13.1" >
-- Retrieval info: <generic name="RATE" value="Half" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="400.0" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="8" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="2x refresh rate" />
-- Retrieval info: <generic name="MEM_PD" value="Fast exit" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="Full" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="50" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="375" />
-- Retrieval info: <generic name="TIMING_TIH" value="375" />
-- Retrieval info: <generic name="TIMING_TDS" value="250" />
-- Retrieval info: <generic name="TIMING_TDH" value="250" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQHS" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="350" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.35" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="5" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="40.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="127.5" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="3" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="2" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="false" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="1" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.6" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : ddr2ctrl.vho
-- RELATED_FILES: ddr2ctrl.vhd, ddr2ctrl_0002.v, ddr2ctrl_pll0.sv, ddr2ctrl_p0_clock_pair_generator.v, ddr2ctrl_p0_read_valid_selector.v, ddr2ctrl_p0_addr_cmd_datapath.v, ddr2ctrl_p0_reset.v, ddr2ctrl_p0_acv_ldc.v, ddr2ctrl_p0_memphy.sv, ddr2ctrl_p0_reset_sync.v, ddr2ctrl_p0_new_io_pads.v, ddr2ctrl_p0_fr_cycle_shifter.v, ddr2ctrl_p0_fr_cycle_extender.v, ddr2ctrl_p0_read_datapath.sv, ddr2ctrl_p0_write_datapath.v, ddr2ctrl_p0_simple_ddio_out.sv, ddr2ctrl_p0_phy_csr.sv, ddr2ctrl_p0_iss_probe.v, ddr2ctrl_p0_addr_cmd_pads.v, ddr2ctrl_p0_flop_mem.v, ddr2ctrl_p0.sv, ddr2ctrl_p0_altdqdqs.v, altdq_dqs2_ddio_3reg_stratixiv.sv, afi_mux_ddrx.v, ddr2ctrl_s0.v, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux_002.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux_001.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_mux.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_demux_005.sv, ddr2ctrl_s0_mm_interconnect_0_rsp_xbar_demux_003.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux_005.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux_003.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_mux.sv, altera_merlin_arbitrator.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux_002.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux_001.sv, ddr2ctrl_s0_mm_interconnect_0_cmd_xbar_demux.sv, altera_merlin_reorder_memory.sv, altera_merlin_traffic_limiter.sv, ddr2ctrl_s0_mm_interconnect_0_id_router_005.sv, ddr2ctrl_s0_mm_interconnect_0_id_router_003.sv, ddr2ctrl_s0_mm_interconnect_0_id_router.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router_002.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router_001.sv, ddr2ctrl_s0_mm_interconnect_0_addr_router.sv, altera_merlin_burst_uncompressor.sv, altera_merlin_slave_agent.sv, altera_merlin_master_agent.sv, ddr2ctrl_s0_irq_mapper.sv, ddr2ctrl_s0_mm_interconnect_0.v, altera_avalon_mm_bridge.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, rw_manager_inst_ROM_no_ifdef_params.v, rw_manager_ac_ROM_no_ifdef_params.v, rw_manager_write_decoder.v, rw_manager_read_datapath.v, rw_manager_ram_csr.v, rw_manager_ram.v, rw_manager_pattern_fifo.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_lfsr72.v, rw_manager_jumplogic.v, rw_manager_inst_ROM_reg.v, rw_manager_generic.sv, rw_manager_dm_decoder.v, rw_manager_di_buffer_wrap.v, rw_manager_di_buffer.v, rw_manager_datamux.v, rw_manager_data_decoder.v, rw_manager_data_broadcast.v, rw_manager_core.sv, rw_manager_bitcheck.v, rw_manager_ac_ROM_reg.v, rw_manager_ddr2.v, sequencer_data_mgr.sv, sequencer_phy_mgr.sv, sequencer_reg_file.sv, sequencer_scc_reg_file.v, sequencer_scc_acv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_siii_wrapper.sv, sequencer_scc_mgr.sv, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v, altera_mem_if_sequencer_rst.sv, ddr2ctrl_dmaster.v, ddr2ctrl_c0.v, altera_mem_if_oct_stratixiv.sv, altera_mem_if_dll_stratixiv.sv, ddr2ctrl_mm_interconnect_0.v, altera_avalon_st_jtag_interface.v, altera_jtag_dc_streaming.v, altera_jtag_sld_node.v, altera_jtag_streaming.v, altera_pli_streaming.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_idle_remover.v, altera_avalon_st_idle_inserter.v, ddr2ctrl_dmaster_timing_adt.v, altera_avalon_sc_fifo.v, altera_avalon_st_bytes_to_packets.v, altera_avalon_st_packets_to_bytes.v, altera_avalon_packets_to_master.v, ddr2ctrl_dmaster_b2p_adapter.v, ddr2ctrl_dmaster_p2b_adapter.v, altera_reset_controller.v, altera_reset_synchronizer.v, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_ddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv
| gpl-2.0 | 0a010ae8218f5bacc658d64d0e5cfd56 | 0.611428 | 3.082931 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/pwm_test/ctrl_leds.vhd | 1 | 3,414 | --------------------------------------------------------------------------------
--
-- Title : ctrl_leds.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Controller LEDs 8x8
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_leds is
port(
-- system signals:
clk : in std_logic; --! clock
clk_dv : in std_logic; --! clock/2
reset : in std_logic; --! system reset
pwm_ena : in std_logic; --! enable PWM
-- buttons:
cbut : in std_logic_vector(5 downto 1); --! buttons
-- leds vectors:
led_x : out std_logic_vector(7 downto 0); --! LED X
led_y : out std_logic_vector(7 downto 0) --! LED y
);
end ctrl_leds;
architecture ctrl_leds of ctrl_leds is
component ctrl_led8x8_heart is
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Reset
rst_reg : in std_logic; -- Count reset
ch_freq : in std_logic; -- Change frequency
led_y : out std_logic_vector(7 downto 0); -- LED Y
led_x : out std_logic_vector(7 downto 0) -- LED X
);
end component;
component ctrl_pwm is
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Reset
rst_reg : in std_logic; -- Count reset
zoom_reg : in std_logic; -- Switch change
zoom_cnt : in std_logic; -- Switch counter
log_led : out std_logic -- Pulsed LED enable
);
end component;
component ctrl_jazz is
port(
clk : in std_logic; -- Clock
button : in std_logic; -- Button in
reset : in std_logic; -- Reset
clrbutton : out std_logic -- Button out
);
end component;
signal clbutton : std_logic_vector(5 downto 1);
signal log_led : std_logic;
signal log_hearty : std_logic_vector(7 downto 0);
signal log_heartx : std_logic_vector(7 downto 0);
begin
x_GEN_LEDX : for ii in 0 to 7 generate
led_x(ii) <= log_led or log_heartx(ii) when pwm_ena = '0' else log_heartx(ii);
end generate;
x_GEN_LEDY : for ii in 0 to 7 generate
led_y(ii) <= (log_led or log_hearty(ii)) when pwm_ena = '0' else log_hearty(ii);
end generate;
---------------- PULSE-WITDH MODULO ----------------
xCTRL_PWM : ctrl_pwm
port map (
clk => clk_dv,
rst => reset,
rst_reg => clbutton(1),
zoom_reg => clbutton(2),
zoom_cnt => clbutton(3),
log_led => log_led
);
---------------- CTRL MATRIX 8X8 ----------------
xCTRL_LED : ctrl_led8x8_heart
port map (
clk => clk_dv,
rst => reset,
rst_reg => clbutton(1),
ch_freq => clbutton(2),
led_y => log_hearty,
led_x => log_heartx
);
---------------- DEBOUNCE ----------------
xDEBOUNCE: for ii in 1 to 5 generate
x_buttons: ctrl_jazz
port map (
clk => clk,
button => cbut(ii),
reset => reset,
clrbutton => clbutton(ii)
);
end generate;
end ctrl_leds; | mit | 885768f53c1de964b3cc72410b4ed8f2 | 0.466901 | 3.061883 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/libleon3.vhd | 1 | 7,842 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libleon3
-- File: libleon3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 internal components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libfpu.all;
use gaisler.mmuiface.all;
package libleon3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (
fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
rfft : integer range 0 to 2 := 0); -- 0 - no protection, 1 - parity
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component regfile_3p_l3
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
wrfst : integer := 0;
numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
end;
| gpl-2.0 | 3e432243f881ae3923ac6f49da1bcd73 | 0.475771 | 3.832845 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml605/config.vhd | 1 | 5,982 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex6;
constant CFG_MEMTECH : integer := virtex6;
constant CFG_PADTECH : integer := virtex6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020789#;
constant CFG_ETH_ENL : integer := 16#000123#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
-- Xilinx MIG DDR2 controller
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_CLK4 : integer := 16;
end;
| gpl-2.0 | b5898584b6ba473902da50969fb2047a | 0.645603 | 3.592793 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_reg_module.vhd | 1 | 29,430 | -------------------------------------------------------------------------------
-- axi_cdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pkg.all;
use axi_cdma_v4_1.axi_cdma_lite_if;
use axi_cdma_v4_1.axi_cdma_register;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_cdma_reg_module is
generic(
C_CDMA_BUILD_MODE : integer range 0 to 1 := 0 ;
-- Indicates the as-built topology of the AXI CDMA
-- 0 = Simple DMA only support
-- 1 = Simple DMA and Scatter Gather support included
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6 ;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special AXI Lite clock for the axi lite interface
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Address width of the SG AXI Interface (bits)
);
port (
---------------------------------------------------------------------------------
-- AXI4-Lite Interface
---------------------------------------------------------------------------------
-- AXI Lite Clock (needs to be the same as axi4-lite clock when
-- C_AXI_LITE_IS_ASYNC = 0 ) -- AXI4-Lite
axi_lite_aclk : in std_logic ;-- AXI4-Lite
-- AXI Lite Bus Side Reset (synchronized to the axi_lite_aclk)
axi_lite_reset : in std_logic ;-- AXI4-Lite
-- AXI Lite Core side Reset (synchronized to the axi_aclk)
axi_lite_cside_reset : in std_logic ;-- AXI4-Lite
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- Primary Input Clock for everything other than AXI4-Lite
axi_aclk : In std_logic ;
-- Primary Input Reset synchronized to axi_aclk
axi_reg_reset : In std_logic ;
-- Composite Interrupt Output
reg_introut : out std_logic ;
-- Composite error Output
reg_error_out : out std_logic ;
-- Soft Reset Set Control
reg_soft_reset_request : out std_logic ;
-- Soft Reset Clear
reg_soft_reset_clr : in std_logic ;
-- DMA Go Control
reg_dma_go : Out std_logic ;
-- SG Mode control
reg_dma_sg_mode : Out std_logic ;
-- Key Hole read
dma_keyhole_read : Out std_logic ;
-- Key Hole write
dma_keyhole_write : Out std_logic ;
-- Cyclic feature
dma_cyclic : Out std_logic ;
-- CDMASR Idle bit set
reg_idle_set : in std_logic ;
-- CDMASR Idle bit clear
reg_idle_clr : in std_logic ;
-- CDMASR Interrupt on Complet set
reg_ioc_irq_set : in std_logic ;
-- CDMASR Delay Interrupt set
reg_dly_irq_set : in std_logic ;
-- CDMASR Delay Interrupt Counter value
reg_irqdelay_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value
reg_irqthresh_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value write enable
reg_irqthresh_wren : out std_logic ;
-- CDMASR Delay Interrupt Counter value write enable
reg_irqdelay_wren : out std_logic ;
-- Composite DataMover Internal Error flag
reg_dma_interr_set : in std_logic ;
-- Composite DataMover Slave Error flag
reg_dma_slverr_set : in std_logic ;
-- Composite DataMover Decode Error flag
reg_dma_decerr_set : in std_logic ;
-- SG Descriptor Fetch internal error flag
reg_ftch_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
reg_ftch_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
reg_ftch_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
reg_ftch_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG Descriptor Update internal error flag
reg_updt_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
reg_updt_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
reg_updt_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
reg_updt_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG CURDESC Update Write enable
reg_new_curdesc_wren : in std_logic ;
-- SG CURDESC Update address value
reg_new_curdesc : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- Tailpointer Register Updated flag
reg_tailpntr_updated : out std_logic ;
-- Current Descriptor Register Updated flag
reg_currdesc_updated : out std_logic ;
-- CDMA Control Register value
reg_dmacr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ;
-- CDMA Status Register value
reg_dmasr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register value
reg_curdesc : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- CDMA Tailpointer Register value
reg_taildesc : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- CDMA Source Address Register value
reg_src_addr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA destination Register value
reg_dest_addr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA BTT Register value
reg_btt : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0)
);
end axi_cdma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant CDMA_NUM_REG : Integer := 16;
Constant DMACR_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000001";
Constant DMASR_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000010";
Constant CURDESC_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000100";
Constant CURDESC_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000001000";
Constant TAILDESC_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000010000";
Constant TAILDESC_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000100000";
Constant SA_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000001000000";
Constant SA_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000010000000";
Constant DA_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000100000000";
Constant DA_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000001000000000";
Constant BTT_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000010000000000";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
---------------------------- ---------------------------------------------------
signal sig_axi2ip_wrce : std_logic_vector(CDMA_NUM_REG - 1 downto 0) := (others => '0');
signal sig_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi2ip_rdce : std_logic_vector(CDMA_NUM_REG - 1 downto 0) := (others => '0');
signal sig_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_curdesc_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_taildesc_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_src_addr_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dest_addr_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_btt : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_lite_bside_resetn : std_logic := '0';
signal sig_axi_lite_cside_resetn : std_logic := '0';
signal sig_interrupt_out : std_logic := '0';
signal sig_reg2out_irpt : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Reset Inversions for the AXI Lite IF
sig_axi_lite_bside_resetn <= not(axi_lite_reset);
sig_axi_lite_cside_resetn <= not(axi_lite_cside_reset);
-- Register Outputs
reg_dmacr <= sig_dmacr;
reg_dmasr <= sig_dmasr;
reg_curdesc <= sig_curdesc_lsb;
reg_taildesc <= sig_taildesc_lsb;
reg_src_addr <= sig_src_addr_lsb;
reg_dest_addr <= sig_dest_addr_lsb;
reg_btt <= sig_btt;
-- Composite Interrupt Output
reg_introut <= sig_interrupt_out ;
------------------------------------------------------------
-- Instance: I_AXI_LITE
--
-- Description:
-- Instance for the AXI Lite Interface Module
--
------------------------------------------------------------
I_AXI_LITE : entity axi_cdma_v4_1.axi_cdma_lite_if
generic map(
C_NUM_CE => CDMA_NUM_REG ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
-- AXI Lite Clock and Reset
s_axi_lite_aclk => axi_lite_aclk ,
s_axi_lite_aresetn => sig_axi_lite_bside_resetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
-- IP side Interface clock and Reset inputs
-- Used when C_AXI_LITE_IS_ASYNC = 1
ip2axi_aclk => axi_aclk ,
ip2axi_aresetn => sig_axi_lite_cside_resetn,
axi2ip_wrce => sig_axi2ip_wrce ,
axi2ip_wrdata => sig_axi2ip_wrdata ,
axi2ip_rdce => sig_axi2ip_rdce ,
axi2ip_rdaddr => open ,
ip2axi_rddata => sig_ip2axi_rddata
);
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
AXI_LITE_READ_MUX : process(sig_axi2ip_rdce ,
sig_dmacr ,
sig_dmasr ,
sig_curdesc_lsb ,
sig_taildesc_lsb ,
sig_src_addr_lsb ,
sig_dest_addr_lsb,
sig_btt)
begin
-- Read Mux
case sig_axi2ip_rdce is
---------------------------------
When DMACR_REG_CE =>
sig_ip2axi_rddata <= sig_dmacr;
---------------------------------
When DMASR_REG_CE =>
sig_ip2axi_rddata <= sig_dmasr;
---------------------------------
When CURDESC_LS_REG_CE =>
sig_ip2axi_rddata <= sig_curdesc_lsb;
---------------------------------
When TAILDESC_LS_REG_CE =>
sig_ip2axi_rddata <= sig_taildesc_lsb;
---------------------------------
When SA_LS_REG_CE =>
sig_ip2axi_rddata <= sig_src_addr_lsb;
---------------------------------
When DA_LS_REG_CE =>
sig_ip2axi_rddata <= sig_dest_addr_lsb;
---------------------------------
When BTT_REG_CE =>
sig_ip2axi_rddata <= sig_btt;
---------------------------------
when others =>
sig_ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_IRPT_RESYNC
--
-- If Generate Description:
-- The AXI clock and the AXI Lite clock are the same so
-- synchronization registers are not required.
--
------------------------------------------------------------
GEN_NO_IRPT_RESYNC : if (C_AXI_LITE_IS_ASYNC = 0) generate
begin
sig_interrupt_out <= sig_reg2out_irpt;
end generate GEN_NO_IRPT_RESYNC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_IRPT_RESYNC
--
-- If Generate Description:
-- The AXI clock and the AXI Lite clock are not the same so
-- synchronization registers are are required.
--
------------------------------------------------------------
GEN_IRPT_RESYNC : if (C_AXI_LITE_IS_ASYNC = 1) generate
ATTRIBUTE async_reg : STRING;
signal lsig_sync_reg1_cdc_tig : std_logic := '0';
signal lsig_sync_reg2 : std_logic := '0';
--ATTRIBUTE async_reg OF lsig_sync_reg1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lsig_sync_reg2 : SIGNAL IS "true";
begin
sig_interrupt_out <= lsig_sync_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_IRPT_SYNC_REG
--
-- Process Description:
-- Implements the syncronization registers for the AXI
-- to AXI Lite clock domain crossing of the interrupt out.
--
-------------------------------------------------------------
IMP_SYNC_IRPT_SYNC_REG : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_reg2out_irpt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => lsig_sync_reg2,
scndry_vect_out => open
);
-- IMP_SYNC_IRPT_SYNC_REG : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- -- if (axi_lite_reset = '1') then
--
-- -- lsig_sync_reg1 <= '0';
-- -- lsig_sync_reg2 <= '0';
--
-- -- else
--
-- lsig_sync_reg1_cdc_tig <= sig_reg2out_irpt;
-- lsig_sync_reg2 <= lsig_sync_reg1_cdc_tig;
--
-- -- end if;
-- end if;
-- end process IMP_SYNC_IRPT_SYNC_REG;
end generate GEN_IRPT_RESYNC;
------------------------------------------------------------
-- Instance: I_REGISTER_BLOCK
--
-- Description:
-- Instance of the AXI CDMA register block.
--
------------------------------------------------------------
I_REGISTER_BLOCK : entity axi_cdma_v4_1.axi_cdma_register
generic map (
C_CDMA_BUILD_MODE => C_CDMA_BUILD_MODE ,
C_NUM_REGISTERS => CDMA_NUM_REG ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-- Secondary Clock / Reset
axi_aclk => axi_aclk ,
axi_reset => axi_reg_reset ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrce => sig_axi2ip_wrce ,
axi2ip_wrdata => sig_axi2ip_wrdata ,
-- Composite Interrupt Output
introut => sig_reg2out_irpt ,
-- Composite error Output
error_out => reg_error_out ,
-- Soft Reset Control
soft_reset_request => reg_soft_reset_request ,
soft_reset_clr => reg_soft_reset_clr ,
-- DMA Go Control
dma_go => reg_dma_go ,
-- SG Mode control
dma_sg_mode => reg_dma_sg_mode ,
-- Key Hole write
dma_keyhole_write => dma_keyhole_write ,
-- Key Hole read
dma_keyhole_read => dma_keyhole_read ,
-- Key Hole read
dma_cyclic => dma_cyclic ,
-- DMASR Register bit control/status
idle_set => reg_idle_set ,
idle_clr => reg_idle_clr ,
ioc_irq_set => reg_ioc_irq_set ,
dly_irq_set => reg_dly_irq_set ,
irqdelay_status => reg_irqdelay_status ,
irqthresh_status => reg_irqthresh_status ,
irqthresh_wren => reg_irqthresh_wren ,
irqdelay_wren => reg_irqdelay_wren ,
-- DataMover Errors
dma_interr_set => reg_dma_interr_set ,
dma_slverr_set => reg_dma_slverr_set ,
dma_decerr_set => reg_dma_decerr_set ,
-- SG Descriptor Fetch errors
ftch_interr_set => reg_ftch_interr_set ,
ftch_slverr_set => reg_ftch_slverr_set ,
ftch_decerr_set => reg_ftch_decerr_set ,
ftch_error_addr => reg_ftch_error_addr ,
-- SG Descriptor Update errors
updt_interr_set => reg_updt_interr_set ,
updt_slverr_set => reg_updt_slverr_set ,
updt_decerr_set => reg_updt_decerr_set ,
updt_error_addr => reg_updt_error_addr ,
-- SG CURDESC Update (from SG)
update_curdesc => reg_new_curdesc_wren ,
new_curdesc => reg_new_curdesc ,
-- SG Detected SW Register Update
tailpntr_updated => reg_tailpntr_updated ,
currdesc_updated => reg_currdesc_updated ,
-- Register State Out
dmacr => sig_dmacr ,
dmasr => sig_dmasr ,
curdesc_lsb => sig_curdesc_lsb ,
curdesc_msb => open ,
taildesc_lsb => sig_taildesc_lsb ,
taildesc_msb => open ,
src_addr_lsb => sig_src_addr_lsb ,
src_addr_msb => open ,
dest_addr_lsb => sig_dest_addr_lsb ,
dest_addr_msb => open ,
btt => sig_btt
);
end implementation;
| gpl-3.0 | 8981ffc1d84671cec67eabdfab5cbfb6 | 0.439891 | 4.564206 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-atlys/testbench.vhd | 1 | 8,629 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
-- Modified by Aeroflex Gaisler
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library hynix;
use hynix.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_cke : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
signal ddr_csb : std_ulogic := '0';
signal txd1, rxd1 : std_logic;
signal genio : std_logic_vector(7 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0) := (others => '0');
signal led : std_logic_vector(7 downto 0);
signal button : std_logic_vector(4 downto 0) := (others => '0');
-- Ethernet
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal egtxclk : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal errorn : std_logic;
begin
-- system clock
clk <= (not clk) after clkperiod * 0.5 ns;
-- reset
rst <= '0', '1' after 2500 ns;
rxd1 <= 'H';
ps2clk <= "HH"; ps2data <= "HH";
-- enable DSU
switch(7) <= '1';
switch(6) <= '0';
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow )
port map (
resetn => rst,
clk => clk,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_odt => ddr_odt,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_dq => ddr_dq,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
txd1 => txd1,
rxd1 => rxd1,
pmoda => genio,
switch => switch,
led => led,
button => button,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etx_clk => etx_clk,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
erst => open,
egtxclk => egtxclk,
emdc => emdc,
emdio => emdio,
emdint => emdint,
kbd_clk => ps2clk(0),
kbd_data => ps2data(0),
mou_clk => ps2clk(1),
mou_data => ps2data(1),
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
tmdstx_clk_p => open,
tmdstx_clk_n => open,
tmdstx_dat_p => open,
tmdstx_dat_n => open );
prom0 : spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => 16#200000# )
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n );
-- NOTE: LEON3 expects DDR2 memory chip with eight banks, but simulation
-- model has only four banks. Therefore 2nd block of 64 MByte will alias
-- to first block.
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => false, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile, fdelay => 340)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (base1000_t_fd => 0, base1000_t_hd => 0, address => 7)
port map (rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, egtxclk);
end generate;
-- Monitor error indication.
errorn <= not led(7);
iuerr: process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- Write serial port output to stdout.
--uart0: process
-- constant bit_interval : time := 1 sec / 38400.0;
-- variable d : std_logic_vector(7 downto 0);
-- variable c : character;
-- variable lin : line;
--begin
-- rxc(txd1, d, bit_interval);
-- c := character'val(conv_integer(d));
-- if c = LF then
-- std.textio.writeline(output, lin);
-- elsif c /= CR then
-- std.textio.write(lin, c);
-- end if;
--end process;
end;
| gpl-2.0 | e9f81cb5a2d58e97797db0d2ebdb37a1 | 0.553482 | 3.443336 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/testbench.vhd | 1 | 6,521 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
romdepth : integer := 22 -- rom address depth (flash 4 MB)
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec";
constant sdramfile : string := "ram.srec";
signal clock_50 : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal key : std_logic_vector(1 downto 0);
signal sw : std_logic_vector(3 downto 0);
signal dram_ba : std_logic_vector(1 downto 0);
signal dram_dqm : std_logic_vector(1 downto 0);
signal dram_ras_n : std_ulogic;
signal dram_cas_n : std_ulogic;
signal dram_cke : std_ulogic;
signal dram_clk : std_ulogic;
signal dram_we_n : std_ulogic;
signal dram_cs_n : std_ulogic;
signal dram_dq : std_logic_vector(15 downto 0);
signal dram_addr : std_logic_vector(12 downto 0);
signal epcs_data0 : std_logic;
signal epcs_dclk : std_logic;
signal epcs_ncso : std_logic;
signal epcs_asdo : std_logic;
signal i2c_sclk : std_logic;
signal i2c_sdat : std_logic;
signal g_sensor_cs_n : std_ulogic;
signal g_sensor_int : std_ulogic;
signal adc_cs_n : std_ulogic;
signal adc_saddr : std_ulogic;
signal adc_sclk : std_ulogic;
signal adc_sdat : std_ulogic;
signal gpio_2 : std_logic_vector(12 downto 0);
signal gpio_2_in : std_logic_vector(2 downto 0);
signal gpio_1_in : std_logic_vector(1 downto 0);
signal gpio_1 : std_logic_vector(33 downto 0);
signal gpio_0_in : std_logic_vector(1 downto 0);
signal gpio_0 : std_logic_vector(33 downto 0);
begin
clock_50 <= not clock_50 after 10 ns; --50 MHz clk
key(0) <= '0', '1' after 300 ns;
key(1) <= '1'; -- DSU break, disabled
sw <= (others => 'H');
gpio_0 <= (others => 'H');
gpio_0_in <= (others => 'H');
gpio_1 <= (others => 'H');
gpio_1_in <= (others => 'H');
gpio_2 <= (others => 'H');
gpio_2_in <= (others => 'H');
led(5 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
clock_50 => clock_50,
led => led,
key => key,
sw => sw,
dram_ba => dram_ba,
dram_dqm => dram_dqm,
dram_ras_n => dram_ras_n,
dram_cas_n => dram_cas_n,
dram_cke => dram_cke,
dram_clk => dram_clk,
dram_we_n => dram_we_n,
dram_cs_n => dram_cs_n,
dram_dq => dram_dq,
dram_addr => dram_addr,
epcs_data0 => epcs_data0,
epcs_dclk => epcs_dclk,
epcs_ncso => epcs_ncso,
epcs_asdo => epcs_asdo,
i2c_sclk => i2c_sclk,
i2c_sdat => i2c_sdat,
g_sensor_cs_n => g_sensor_cs_n,
g_sensor_int => g_sensor_int,
adc_cs_n => adc_cs_n,
adc_saddr => adc_saddr,
adc_sclk => adc_sclk,
adc_sdat => adc_sdat,
gpio_2 => gpio_2,
gpio_2_in => gpio_2_in,
gpio_1_in => gpio_1_in,
gpio_1 => gpio_1,
gpio_0_in => gpio_0_in,
gpio_0 => gpio_0);
sd1 : if (CFG_SDCTRL /= 0) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => dram_dq, Addr => dram_addr, Ba => dram_ba, Clk => dram_clk,
Cke => dram_cke, Cs_n => dram_cs_n, Ras_n => dram_ras_n,
Cas_n => dram_cas_n, We_n => dram_we_n, Dqm => dram_dqm);
end generate;
dram_dq <= buskeep(dram_dq) after 5 ns;
spif : if CFG_SPIMCTRL /= 0 generate
spi0: spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => epcs_dclk,
di => epcs_asdo,
do => epcs_data0,
csn => epcs_ncso,
sd_cmd_timeout => open,
sd_data_timeout => open);
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(led(6)) = '1' then wait on led(6); end if;
assert (to_x01(led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | 8819bf9d6f4528742ff1352a4f2bd3c0 | 0.538721 | 3.532503 | false | false | false | false |
borti4938/sd2snes | verilog/sd2snes_sdd1/FIFO_AXIS.vhd | 2 | 5,067 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO_AXIS is
Generic( FIFO_DEPTH : integer := 32 );
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
din_tkeep : IN STD_LOGIC_VECTOR(1 downto 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC );
end FIFO_AXIS;
architecture Behavioral of FIFO_AXIS is
type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';
begin
Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write 2 bytes
if( din_tkeep = "11" ) then
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(0) <= din_tdata(15 downto 8);
wr_ptr <= 1;
elsif( wr_ptr = (FIFO_DEPTH-2) ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(wr_ptr+1) <= din_tdata(15 downto 8);
wr_ptr <= 0;
else
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
FIFO_Array(wr_ptr+1) <= din_tdata(15 downto 8);
wr_ptr <= wr_ptr + 2;
end if;
-- write 1 byte
elsif( din_tkeep = "01" ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(7 downto 0);
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
-- write 1 byte
elsif( din_tkeep = "10" ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata(15 downto 8);
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
end if;
-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
-- occupancy control
-- read and write colision
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
if( din_tkeep = "11" ) then
data_cnt <= data_cnt + 1;
elsif( din_tkeep = "00" ) then
data_cnt <= data_cnt - 1;
end if;
-- write only
elsif((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
if( din_tkeep = "11" ) then
data_cnt <= data_cnt + 2;
elsif( din_tkeep = "01" OR din_tkeep = "10" ) then
data_cnt <= data_cnt + 1;
end if;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;
-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;
-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-2) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
| gpl-2.0 | fe163173e8ad02e60eb10acc9c68731f | 0.528913 | 2.975338 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_scc.vhd | 13 | 42,217 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
| gpl-3.0 | c157709dd23317f06478352c8156f22e | 0.441789 | 4.720675 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahbdpram.vhd | 1 | 5,264 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahdpbram
-- File: ahbdpram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB DP ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbdpram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end;
architecture rtl of ahbdpram is
--constant abits : integer := log2(kbytes) + 8;
constant kbytes : integer := 2**(abits - 8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDPRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal bwrite : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
signal hwdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
bwrite <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ahbdrivedata(ramdata);
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
hwdata <= ahbreadword(ahbsi.hwdata, r.addr(4 downto 2));
bw : if bytewrite = 1 generate
ra : for i in 0 to 3 generate
aram : syncram_dp generic map (tech, abits, 8) port map (
clk, ramaddr, hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, bwrite(3-i),
clkdp, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable, write(3-i)
);
end generate;
end generate;
nobw : if bytewrite = 0 generate
aram : syncram_dp generic map (tech, abits, 32) port map (
clk, ramaddr, hwdata(31 downto 0), ramdata, ramsel, r.hwrite,
clkdp, address, datain, dataout, enable, write(0)
);
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdpram" & tost(hindex) &
": AHB DP SRAM Module, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 | 90c5a0c1cd33d8ec65a7145ab908b1d9 | 0.605813 | 3.372197 | false | false | false | false |
pdt/ttask | test/fpga-sim/sim/my_fpga_test_count_up_1k.vhdl | 1 | 2,009 | --
-- my_fpga_test_count_up_1k.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use work.tbmsgs.all;
entity my_fpga_test_count_up_1k is
end entity;
architecture sim of my_fpga_test_count_up_1k is
signal clk : std_logic := '0';
signal n_rst : std_logic := '0';
signal up : std_logic := '0';
signal dn : std_logic := '0';
signal cnt : std_logic_vector(31 downto 0);
signal cnt_1k : std_logic_vector(3 downto 0);
signal in1 : std_logic := '0';
signal in2 : std_logic := '0';
signal out1 : std_logic;
signal out2 : std_logic;
signal done : boolean := false;
begin
uut : entity work.my_fpga port map (
clk => clk,
n_rst => n_rst,
up => up,
dn => dn,
cnt => cnt,
cnt_1k => cnt_1k,
in1 => in1,
in2 => in2,
out1 => out1,
out2 => out2
);
test : process
variable t : time;
begin
testcase("my_fpga count up 1k", 1);
wait for 1 us;
n_rst <= '1';
wait for 1 us;
wait until falling_edge(clk);
up <= '1';
-- wait until cnt_1k output is 0x1
loop
wait until falling_edge(clk);
if cnt_1k = x"1" then
t := now;
exit;
end if;
end loop;
-- wait until cnt_1k is 0xb
loop
wait until falling_edge(clk);
if cnt_1k = x"b" then
t := now - t;
exit;
end if;
end loop;
check((t > (10 ms - 100 ns) and t < (10 ms + 100 ns)),
"cnt_1k output should count at 1KHz");
tested("count 1k output");
testcase_complete;
done <= true;
wait;
end process;
clk_gen : process
begin
loop
wait for 5 ns;
clk <= not clk;
if done then
exit;
end if;
end loop;
wait;
end process;
end;
| mit | c3176685cf478d06e304d8cbe032a8c3 | 0.467397 | 3.54321 | false | true | false | false |
medevo/howdoi | VHDL/add_unsigned.vhd | 1 | 767 | -- How do I add two std_logic_vectors unsigned
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity alu is
Port ( in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
clk : in STD_LOGIC; -- Just in case, this design is async
result : out std_logic_vector(15 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(clk,in1,in2)
variable tmp_s_16 : SIGNED (15 downto 0);
variable tmp_l_16 : std_logic_vector(15 downto 0);
tmp_s_16 := x"0000";
tmp_l_16 := x"0000";
-- Unsigned Subtract
tmp_l_16 := STD_LOGIC_VECTOR(unsigned(in1) + unsigned(in2));
tmp_s_16 := signed(tmp_l_16);
result <= std_logic_vector(tmp_s_16);
end process;
end Behavioral; | unlicense | 93610062c88c018c0c7c7e7f8aef9be1 | 0.65189 | 2.872659 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd | 1 | 6,285 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
| gpl-2.0 | a55770cd1a572dd9538afc421649fe40 | 0.58393 | 3.375403 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/3147922d/hdl/src/vhdl/mux_onehot_f.vhd | 7 | 12,551 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0;
--use proc_common_v4_0.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 | 0eb95a86163461ef5eb9fa2c6a96b009 | 0.441718 | 4.736226 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/toutpad_ds.vhd | 1 | 4,519 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-2.0 | 41f68d6a1f2c6829f9ea7ad04e3804d9 | 0.627351 | 3.497678 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_rows_V.vhd | 4 | 4,564 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_rows_V is
component FIFO_image_filter_img_1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_rows_V_shiftReg : FIFO_image_filter_img_1_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 2d29e04335a774c60c88a9bc180c1249 | 0.534619 | 3.483969 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-111/leon3mp.vhd | 1 | 16,594 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.11",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | cf88bdc839070802b1be228c2a5b0b05 | 0.533687 | 3.778233 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-pci-xc5v/leon3mp.vhd | 1 | 39,427 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRUSBHC +
CFG_GRUSBDC;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 4ded2835d1c4104b1d493bd4daf8fcbc | 0.55779 | 3.407398 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd | 1 | 28,030 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ah2mig_series7_pkg
-- File: ah2mig_series7_pkg.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: Components, types and functions for AHB2MIG Series 7 controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library gaisler;
use gaisler.all;
package ahb2mig_series7_pkg is
-------------------------------------------------------------------------------
-- AHB2MIG configuration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG interface type declarations and constant
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG Subprograms
-------------------------------------------------------------------------------
function nbrmaxmigcmds (
datawidth : integer)
return integer;
function nbrmigcmds (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function reversebyte (
data : std_logic_vector)
return std_logic_vector;
function reversebytemig (
data : std_logic_vector)
return std_logic_vector;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbselectdatanoreplica (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbdrivedatanoreplica (hdata : std_logic_vector) return std_logic_vector;
-------------------------------------------------------------------------------
-- AHB2MIG Components
-------------------------------------------------------------------------------
end;
package body ahb2mig_series7_pkg is
-- Number of Max MIG commands
function nbrmaxmigcmds(
datawidth : integer)
return integer is
variable ret : integer;
begin
case datawidth is
when 128 =>
ret:= 4;
when 64 =>
ret := 2;
when others =>
ret := 2;
end case;
return ret;
end function nbrmaxmigcmds;
-- Number of MIG commands
function nbrmigcmds(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
case datawidth is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret:= 4;
elsif (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 1;
else
ret := 1;
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
-- 32
when others =>
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
end case;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,4)) + 1;
end if;
return ret;
end function nbrmigcmds;
-- Reverses byte order.
function reversebyte(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'length-i*8-1 downto data'length-i*8-8);
end loop;
return rdata;
end function reversebyte;
-- Reverses byte order.
function reversebytemig(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'left-i*8 downto data'left-i*8-7);
end loop;
return rdata;
end function reversebytemig;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdatanoreplica (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplica
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 64 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 32 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW-1 downto AHBDW/2) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(16*(AHBDW/16)-1 downto 15*(AHBDW/16));
when "0001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(15*(AHBDW/16)-1 downto 14*(AHBDW/16));
when "0010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(14*(AHBDW/16)-1 downto 13*(AHBDW/16));
when "0011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata(13*(AHBDW/16)-1 downto 12*(AHBDW/16));
when "0100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(12*(AHBDW/16)-1 downto 11*(AHBDW/16));
when "0101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(11*(AHBDW/16)-1 downto 10*(AHBDW/16));
when "0110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(10*(AHBDW/16)-1 downto 9*(AHBDW/16));
when "0111" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 9*(AHBDW/16)-1 downto 8*(AHBDW/16));
when "1000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 8*(AHBDW/16)-1 downto 7*(AHBDW/16));
when "1001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 7*(AHBDW/16)-1 downto 6*(AHBDW/16));
when "1010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 6*(AHBDW/16)-1 downto 5*(AHBDW/16));
when "1011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 5*(AHBDW/16)-1 downto 4*(AHBDW/16));
when "1100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 4*(AHBDW/16)-1 downto 3*(AHBDW/16));
when "1101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 3*(AHBDW/16)-1 downto 2*(AHBDW/16));
when "1110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 2*(AHBDW/16)-1 downto 1*(AHBDW/16));
when others => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 1*(AHBDW/16)-1 downto 0*(AHBDW/16));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8));
when "010" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8));
when "011" => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8));
when "110" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8));
when others => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8));
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4));
when "10" => ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)) := hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4));
when others => ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)) := hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4));
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplica;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := (others => '0');
case AHBDW is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
elsif (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
-- 32
when others =>
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end case;
return ret;
end ahbselectdatanoreplicastep;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW/4-1 downto 0);
variable ret128 : std_logic_vector(128/4-1 downto 0);
begin -- ahbselectdatanoreplicamask
ret := (others => '0');
ret128 := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW/8-1 downto 0) := (others => '1');
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
else
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
elsif AHBDW = 32 then
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "001" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "010" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "011" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "100" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "101" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "110" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when others => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
end case;
ret := std_logic_vector(resize(unsigned(ret128),ret'length));
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8-1 downto AHBDW/8/2) := (others => '1');
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 0) := '1';
when "0001" => ret( 1) := '1';
when "0010" => ret( 2) := '1';
when "0011" => ret( 3) := '1';
when "0100" => ret( 0) := '1';
when "0101" => ret( 1) := '1';
when "0110" => ret( 2) := '1';
when "0111" => ret( 3) := '1';
when "1000" => ret( 0) := '1';
when "1001" => ret( 1) := '1';
when "1010" => ret( 2) := '1';
when "1011" => ret( 3) := '1';
when "1100" => ret( 0) := '1';
when "1101" => ret( 1) := '1';
when "1110" => ret( 2) := '1';
when others => ret( 3) := '1';
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(0) := '1';
when "001" => ret(1) := '1';
when "010" => ret(2) := '1';
when "011" => ret(3) := '1';
when "100" => ret(0) := '1';
when "101" => ret(1) := '1';
when "110" => ret(2) := '1';
when others => ret(3) := '1';
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(0) := '1';
when "01" => ret(1) := '1';
when "10" => ret(2) := '1';
when others => ret(3) := '1';
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplicamask;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
begin -- ahbselectdatanoreplicaoutput
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"0000000"),steps'length) + offset;
when HSIZE_DWORD =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 1)&"0000000"),steps'length) + offset;
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
end if;
when others =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 2)&"0000000"),steps'length) + offset;
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 1)&"000000"),steps'length) + offset;
elsif AHBDW = 32 then
offset := resize((unsigned(haddr(5 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
end if;
end case;
stepsint := to_integer(steps);
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
ret(AHBDW-1 downto 0) := reversebyte(hdata);
case hsize is
when HSIZE_4WORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"0000"),offset'length);
when HSIZE_DWORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"000"),offset'length);
when others =>
offset := resize(unsigned(haddr) + unsigned(counter&"00"),offset'length);
end case;
if (replica = true) then
case hsize is
when HSIZE_4WORD =>
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
if offset(3) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case offset(3 downto 2) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if offset(2) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case offset(3 downto 1) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case offset(2 downto 1) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
else
if offset(1) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case offset(3 downto 0) is
when "0000" => retrep := ahbdrivedata(ret(16*(AHBDW/16)-1 downto 15*(AHBDW/16)));
when "0001" => retrep := ahbdrivedata(ret(15*(AHBDW/16)-1 downto 14*(AHBDW/16)));
when "0010" => retrep := ahbdrivedata(ret(14*(AHBDW/16)-1 downto 13*(AHBDW/16)));
when "0011" => retrep := ahbdrivedata(ret(13*(AHBDW/16)-1 downto 12*(AHBDW/16)));
when "0100" => retrep := ahbdrivedata(ret(12*(AHBDW/16)-1 downto 11*(AHBDW/16)));
when "0101" => retrep := ahbdrivedata(ret(11*(AHBDW/16)-1 downto 10*(AHBDW/16)));
when "0110" => retrep := ahbdrivedata(ret(10*(AHBDW/16)-1 downto 9*(AHBDW/16)));
when "0111" => retrep := ahbdrivedata(ret( 9*(AHBDW/16)-1 downto 8*(AHBDW/16)));
when "1000" => retrep := ahbdrivedata(ret( 8*(AHBDW/16)-1 downto 7*(AHBDW/16)));
when "1001" => retrep := ahbdrivedata(ret( 7*(AHBDW/16)-1 downto 6*(AHBDW/16)));
when "1010" => retrep := ahbdrivedata(ret( 6*(AHBDW/16)-1 downto 5*(AHBDW/16)));
when "1011" => retrep := ahbdrivedata(ret( 5*(AHBDW/16)-1 downto 4*(AHBDW/16)));
when "1100" => retrep := ahbdrivedata(ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)));
when "1101" => retrep := ahbdrivedata(ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)));
when "1110" => retrep := ahbdrivedata(ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)));
when others => retrep := ahbdrivedata(ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)));
end case;
elsif AHBDW = 64 then
case offset(2 downto 0) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
else
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
end if;
end case;
--ret := ahbdrivedatamig(retrep);
ret :=retrep;
end if;
return ret;
end ahbselectdatanoreplicaoutput;
-- purpose: extends 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedatanoreplica (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedatanoreplica
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
data := (others => '0');
data(hdata'length-1 downto 0) := hdata;
end if;
return data;
end ahbdrivedatanoreplica;
end; | gpl-2.0 | 8e0f5c7860bffdbdf892143d257e40de | 0.545665 | 3.53557 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/can/can_mc.vhd | 1 | 6,345 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
attribute sync_set_reset of resetn : signal is "true";
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
--attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to 7 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i), ahbsi.testen);
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0');
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 | ebc1da45c5797254d82333e98fc4195a | 0.591174 | 3.480527 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c2ahbx.vhd | 1 | 18,483 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahbx
-- File: i2c2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with i2c2ahb or i2c2ahb_apb
-- before use.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a I2C memory device. To write to the core, issue the
-- following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send data to be written
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. When the core's internal FIFO is full, the core will use clock
-- stretching to stall the transfer.
--
-- To write to the core, issue the following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send repeated start condition
-- 4. Send core's I2C address with direction = read
-- 5. Read bytes
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). When the buffer is empty the core will use clock stretching
-- to stall the transfer.
--
-- The cores control/status register is accessed via address i2caddr + 1. The
-- register has the following layout:
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7:6 | Reserved, always zero (RO) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | NACK: NACK instead of using clock stretching (RW) |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filters used on SCL and SDA
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2c2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end entity i2c2ahbx;
architecture rtl of i2c2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type state_type is (idle, checkaddr, sclhold, movebyte, handshake);
type i2c2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
nack : std_ulogic;
prot : std_ulogic;
-- Transfer phase
i2caddr : std_ulogic;
ahbacc : std_ulogic;
ahbadd : std_ulogic;
rec : std_ulogic;
bcnt : std_logic_vector(1 downto 0);
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : i2c2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_I2C2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, i2ci, amo, i2c2ahbi)
variable v : i2c2ahb_reg_type;
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable slv : std_ulogic;
variable cfg : std_ulogic;
variable lb : std_ulogic;
begin
v := r; ahbreq := '0'; slv := '0'; cfg := '0'; lb := '0';
hrdata := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.state is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
if r.sreg(7 downto 1) = i2c2ahbi.slvaddr then slv := '1'; end if;
if r.sreg(7 downto 1) = i2c2ahbi.cfgaddr then cfg := '1'; end if;
v.rec := not r.sreg(0);
if (slv or cfg) = '1' then
if (slv and r.dodma) = '1' then
-- Core is busy performing DMA
if r.nack = '1' then v.state := idle;
else v.state := sclhold; end if;
else
v.state := handshake;
end if;
else
-- Slave address did not match
v.state := idle;
end if;
v.hwrite := v.rec;
if (slv and not r.dodma) = '1' then v.dodma := not v.rec; end if;
v.ahbacc := slv; v.bcnt := "00"; v.ahbadd := '0';
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the core is ready to process another
-- transfer. It is also used when a data byte has been transmitted or
-- received to keep SCL low until a DMA operation has completed.
-- In the transmit case we keep SCL low before the rising edge of the
-- first byte, so we go directly to move byte. In the receive case we
-- stretch the ACK cycle so we jump to handshake next.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if r.dodma = '0' then
if (not r.rec and not r.i2caddr) = '1' then
v.state := movebyte;
else
v.state := handshake;
end if;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if (r.i2caddr or r.rec or v.scl) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or r.rec) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.i2caddr = '1' then
v.state := checkaddr;
else
v.state := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
-- Falling edge
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
-- Also handles first byte on AHB read access
if (r.rec or r.i2caddr) = '1' then
v.sdaoen := I2C_LOW;
else
v.sdaoen := I2C_HIZ;
end if;
if (not r.i2caddr and r.rec) = '1' then
-- Control register access
v.nack := r.sreg(2);
v.hsize := r.sreg(1 downto 0);
end if;
else
-- AHB access
if r.rec = '1' then
-- First we need a 4 byte address, then we handle data.
v.bcnt := r.bcnt + 1;
if r.ahbadd = '0' then
-- We could check if the address is within the allowed memory
-- area here, and nack otherwise, but we do it when the access
-- is performed instead, to have one check for all cases.
v.haddr := r.haddr(23 downto 0) & r.sreg;
if r.bcnt = "11" then v.ahbadd := '1'; end if;
v.sdaoen := I2C_LOW;
elsif r.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.bcnt := "00"; end if;
v.sdaoen := I2C_LOW;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
end if;
end if;
-- Previous DMA is not finished yet
if (r.dodma and r.ahbacc) = '1' then
if r.nack = '0' then
-- Hold clock low and handle data when DMA is finished
v.state := sclhold;
v.scloen := I2C_LOW;
else
-- NAK byte
v.sdaoen := I2C_HIZ;
v.state := idle;
end if;
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
if r.sda = I2C_ACK then
v.state := movebyte;
else
v.state := idle;
end if;
else
if r.rec = '1' then
v.state := movebyte;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended
-- and we should wait for the master's next action. If the master
-- ACKs the byte the core we will continue to transmit data until
-- we reach the last available byte. When the last byte has been
-- transmitted we will act depending on if we are allowed to enter
-- sclhold. If we can, we enter sclhold and start a new DMA
-- operation, otherwise we stop communicating until the next start
-- condition.
v.bcnt := r.bcnt + 1;
if r.sda = I2C_ACK then
if lb = '1' then
if r.nack = '1' then
v.state := idle;
else
v.dodma := '1'; v.bcnt := "00";
v.state := sclhold;
end if;
else
v.state := movebyte;
end if;
else
v.state := idle;
end if;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
end if;
end if;
v.i2caddr := '0';
if r.ahbacc = '0' then
-- Control register access
v.sreg := zero32(7 downto 6) & r.prot & r.mexc &
r.dodma & r.nack & r.hsize;
end if;
end if;
end case;
if i2c2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((i2c2ahbi.haddr xor r.haddr) and i2c2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if i2c2ahbi.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.state := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.state := movebyte;
v.cnt := (others => '0');
v.i2caddr := '1';
end if;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.hsize := HSIZE_WORD(1 downto 0);
v.mexc := '0';
v.dodma := '0';
v.nack := '0';
v.prot := '0';
v.scl := '0';
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
if i2c2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
i2c2ahbo.dma <= r.dodma;
i2c2ahbo.wr <= r.hwrite;
i2c2ahbo.prot <= r.prot;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= i2c2ahbi.en;
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("i2c2ahb" & tost(hindex) & ": I2C to AHB bridge");
-- pragma translate_on
end architecture rtl;
| gpl-2.0 | d114a3794d55528da1a47f2b3b9865ce | 0.474815 | 3.890339 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/core/greth_rx.vhd | 1 | 11,275 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
-- attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
rxregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| gpl-2.0 | 59bc07c421ff8d72a1f99a327d6a55c3 | 0.500222 | 3.232511 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | registerFile.vhd | 1 | 1,364 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity registerFile is
Port ( we : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
dataToWrite : in STD_LOGIC_VECTOR (31 downto 0);
CRs1 : out STD_LOGIC_VECTOR (31 downto 0);
CRs2 : out STD_LOGIC_VECTOR (31 downto 0);
CRd : out STD_LOGIC_VECTOR (31 downto 0));
end registerFile;
architecture Behavioral of registerFile is
type ram_type is array (0 to 39) of std_logic_vector(31 downto 0);
signal ceros : std_logic_vector (31 downto 0) := (others=>'0');
signal regFile : ram_type := (others => x"00000000");
begin
process(rs1,rs2,rd,rst,dataToWrite)
begin
if (rst = '1') then
CRs1 <= ceros;
CRs2 <= ceros;
CRd <= ceros;
elsif (we = '1') then
if (conv_integer(rs1) = 0) then
CRs1 <= ceros;
else
CRs1 <= regFile(conv_integer(rs1));
end if;
if (conv_integer(rs2) = 0) then
CRs2 <= ceros;
else
CRs2 <= regFile(conv_integer(rs2));
end if;
if (not (rd = "00000")) then
regFile(conv_integer(rd)) <= dataToWrite;
end if;
CRd <= regFile(conv_integer(rd));
else
CRs1 <= ceros;
CRs2 <= ceros;
CRd <= ceros;
end if;
end process;
end Behavioral; | mit | 9b83bf2159179287ce6d936367889bd4 | 0.61437 | 2.883721 | false | false | false | false |
borti4938/sd2snes | verilog/sd2snes_sdd1/Output_Manager.vhd | 2 | 30,131 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 23.03.2018 07:46:09
-- Design Name:
-- Module Name: Output_Manager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Output_Manager is
Port( clk : in STD_LOGIC;
-- configuration received from DMA
DMA_In_Progress : out STD_LOGIC;
DMA_Transfer_End : in STD_LOGIC;
Header_Valid : in STD_LOGIC;
Header_BPP : in STD_LOGIC_VECTOR(1 downto 0);
-- data input from Probability Estimator
BPP_Bit_tready : out STD_LOGIC;
BPP_Bit_tuser : out STD_LOGIC_VECTOR(9 downto 0);
BPP_Bit_tvalid : in STD_LOGIC;
BPP_Bit_tdata : in STD_LOGIC;
-- data output to DMA
DMA_Data_tready : in STD_LOGIC;
DMA_Data_tvalid : out STD_LOGIC;
DMA_Data_tdata : out STD_LOGIC_VECTOR(7 downto 0) );
end Output_Manager;
architecture Behavioral of Output_Manager is
COMPONENT FIFO_B2B
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16 );
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC );
END COMPONENT;
type TipoEstado is(WAIT_HEADER, SET_MODE7_BITPLANE, SET_2_BITPLANES, SET_4_BITPLANES, SET_8_BITPLANES,
BPP0_BIT_0, BPP0_BIT_1, BPP0_BIT_2, BPP0_BIT_3, BPP0_BIT_4, BPP0_BIT_5, BPP0_BIT_6, BPP0_BIT_7,
BPP0_BIT_0_WAIT, BPP0_BIT_1_WAIT, BPP0_BIT_2_WAIT, BPP0_BIT_3_WAIT, BPP0_BIT_4_WAIT, BPP0_BIT_5_WAIT, BPP0_BIT_6_WAIT, BPP0_BIT_7_WAIT,
BPP1_BIT_0, BPP1_BIT_1, BPP1_BIT_2, BPP1_BIT_3, BPP1_BIT_4, BPP1_BIT_5, BPP1_BIT_6, BPP1_BIT_7, BPP_BIT_STALL,
BPP1_BIT_0_WAIT, BPP1_BIT_1_WAIT, BPP1_BIT_2_WAIT, BPP1_BIT_3_WAIT, BPP1_BIT_4_WAIT, BPP1_BIT_5_WAIT, BPP1_BIT_6_WAIT, BPP1_BIT_7_WAIT,
MODE7_BIT_0, MODE7_BIT_1, MODE7_BIT_2, MODE7_BIT_3, MODE7_BIT_4, MODE7_BIT_5, MODE7_BIT_6, MODE7_BIT_7, MODE7_BIT_STALL,
MODE7_BIT_0_WAIT, MODE7_BIT_1_WAIT, MODE7_BIT_2_WAIT, MODE7_BIT_3_WAIT, MODE7_BIT_4_WAIT, MODE7_BIT_5_WAIT, MODE7_BIT_6_WAIT, MODE7_BIT_7_WAIT );
signal estado : TipoEstado := WAIT_HEADER;
signal BPP0_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP1_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP2_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP3_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP4_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP5_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP6_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP7_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP0_Previous : STD_LOGIC := '0';
signal BPP1_Previous : STD_LOGIC := '0';
signal BPP2_Previous : STD_LOGIC := '0';
signal BPP3_Previous : STD_LOGIC := '0';
signal BPP4_Previous : STD_LOGIC := '0';
signal BPP5_Previous : STD_LOGIC := '0';
signal BPP6_Previous : STD_LOGIC := '0';
signal BPP7_Previous : STD_LOGIC := '0';
signal Tile_Count : integer range 0 to 7 := 0;
signal Max_BPP : integer range 0 to 7 := 0;
signal Cnt_BPP : integer range 0 to 7 := 0;
signal Cnt_Pair : integer range 0 to 3 := 0;
signal Cnt_Even : integer range 0 to 1 := 0;
signal Flag_MODE7_Bitplane : STD_LOGIC := '0';
signal FIFO_Data_tready : STD_LOGIC := '0';
signal FIFO_Data_tready_n : STD_LOGIC := '1';
signal FIFO_Data_tvalid : STD_LOGIC := '0';
signal FIFO_Data_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal FSM_BPP_Bit_tready : STD_LOGIC := '0';
signal FSM_Reset : STD_LOGIC := '1';
signal FSM_DMA_In_Progress : STD_LOGIC := '0';
signal FSM_New_MODE7 : STD_LOGIC := '0';
signal FSM_Next_BPP0 : STD_LOGIC := '0';
signal FSM_Next_BPP1 : STD_LOGIC := '0';
signal FSM_Ready_BPP0 : STD_LOGIC := '0';
signal FSM_Ready_BPP1 : STD_LOGIC := '0';
signal FSM_Ready_BPP2 : STD_LOGIC := '0';
signal FSM_Ready_BPP3 : STD_LOGIC := '0';
signal FSM_Ready_BPP4 : STD_LOGIC := '0';
signal FSM_Ready_BPP5 : STD_LOGIC := '0';
signal FSM_Ready_BPP6 : STD_LOGIC := '0';
signal FSM_Ready_BPP7 : STD_LOGIC := '0';
signal FSM_Ready_MODE7 : STD_LOGIC := '0';
signal FSM_New_Tile : STD_LOGIC := '0';
begin
-- current bitplane results from concatenation of current even/odd bitplane and
-- number of BPP0/BPP1 to decode
Cnt_BPP <= Cnt_Pair + Cnt_Pair + Cnt_Even;
-- process for controlling data planes
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' ) then
Max_BPP <= 0;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
FSM_Ready_MODE7 <= '0';
BPP0_Previous <= '0';
BPP1_Previous <= '0';
BPP2_Previous <= '0';
BPP3_Previous <= '0';
BPP4_Previous <= '0';
BPP5_Previous <= '0';
BPP6_Previous <= '0';
BPP7_Previous <= '0';
BPP0_Byte <= X"00";
BPP1_Byte <= X"00";
BPP2_Byte <= X"00";
BPP3_Byte <= X"00";
BPP4_Byte <= X"00";
BPP5_Byte <= X"00";
BPP6_Byte <= X"00";
BPP7_Byte <= X"00";
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
else
-- set counter's maximum value
if( estado = SET_2_BITPLANES ) then
Max_BPP <= 0;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_4_BITPLANES ) then
Max_BPP <= 1;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_8_BITPLANES ) then
Max_BPP <= 3;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_MODE7_BITPLANE ) then
Max_BPP <= 3;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '1';
end if;
-- when mode "11" (MODE7), each new pixel belongs to a different bitplane
if( Flag_MODE7_Bitplane = '1' ) then
if( FSM_New_MODE7 = '1' ) then
if( Cnt_Pair = Max_BPP ) then
Cnt_Pair <= 0;
else
Cnt_Pair <= Cnt_Pair + 1;
end if;
end if;
else
-- increment bitplane when each the pair BPP0/BPP1 has been complete
if( FSM_Next_BPP1 = '1' ) then
-- when 8 lines of 1 2BPP tile have been complete, change bitplane
if( Tile_Count = 7 ) then
if( Cnt_Pair = Max_BPP ) then
Cnt_Pair <= 0;
else
Cnt_Pair <= Cnt_Pair + 1;
end if;
Tile_Count <= 0;
else
Tile_Count <= Tile_Count + 1;
end if;
end if;
end if;
-- store last decoded bit in corresponding bitplane
if( BPP_Bit_tvalid = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
BPP0_Previous <= BPP0_Byte(7);
BPP0_Byte <= BPP0_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP1
when 1 =>
BPP1_Previous <= BPP1_Byte(7);
BPP1_Byte <= BPP1_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP2
when 2 =>
BPP2_Previous <= BPP2_Byte(7);
BPP2_Byte <= BPP2_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP3
when 3 =>
BPP3_Previous <= BPP3_Byte(7);
BPP3_Byte <= BPP3_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP4
when 4 =>
BPP4_Previous <= BPP4_Byte(7);
BPP4_Byte <= BPP4_Byte(6 downto 0) & BPP_Bit_tdata;
--BPP5
when 5 =>
BPP5_Previous <= BPP5_Byte(7);
BPP5_Byte <= BPP5_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP6
when 6 =>
BPP6_Previous <= BPP6_Byte(7);
BPP6_Byte <= BPP6_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP7
when 7 =>
BPP7_Previous <= BPP7_Byte(7);
BPP7_Byte <= BPP7_Byte(6 downto 0) & BPP_Bit_tdata;
end case;
end if;
-- when MODE7, a new byte is completed when BPP0 is asserted
FSM_Ready_MODE7 <= FSM_Next_BPP0 AND Flag_MODE7_Bitplane;
-- decide which BPP will go to output register when completed
if( FSM_Next_BPP0 = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
FSM_Ready_BPP0 <= '1';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
-- BPP2
when 2 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '1';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
-- BPP4
when 4 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '1';
FSM_Ready_BPP6 <= '0';
-- BPP6
when 6 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '1';
when others =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
end case;
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
elsif( FSM_Next_BPP1 = '1' ) then
case Cnt_BPP is
-- BPP1
when 1 =>
FSM_Ready_BPP1 <= '1';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
-- BPP3
when 3 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '1';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
-- BPP5
when 5 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '1';
FSM_Ready_BPP7 <= '0';
-- BPP7
when 7 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '1';
when others =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
end case;
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
else
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
end if;
end if;
end if;
End Process;
-- pre-calculate context bits and register them
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' OR Header_Valid = '1' ) then
BPP_Bit_tuser <= (others => '0');
elsif( BPP_Bit_tvalid = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
-- in any mode, if last decoded bit was BPP0, next plane is BBP1
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP1_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP1_Byte;
-- BPP1
when 1 =>
-- in 4BPP or 8BPP mode, next plane is BPP2 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP > 0 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP2_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP2_Byte;
-- in 2BPP mode, next plane is always BPP0; tile order is
-- BPP0/BPP1..(x6)..BPP0/BPP1
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
end if;
-- BPP2
when 2 =>
-- in any mode, if last decoded bit was BPP2, next plane is BBP3
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP3_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP3_Byte;
-- BPP3
when 3 =>
-- in 4BPP, next plane is BPP0 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3
if( Max_BPP = 1 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
-- in 8BPP mode or MODE7, next plane is BPP4 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
elsif( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP4_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP4_Byte;
-- in any other cases, next plane is BPP2
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP2_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP2_Byte;
end if;
-- BPP4
when 4 =>
-- in 8BPP or MODE7 mode, if last decoded bit was BPP4, next plane is BBP5
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP5_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP5_Byte;
-- BPP5
when 5 =>
-- in 8BPP mode or MODE7, next plane is BPP6 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP6_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP6_Byte;
-- in any other cases, next plane is BPP4
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP4_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP4_Byte;
end if;
-- BPP6
when 6 =>
-- in 8BPP or MODE7 mode, if last decoded bit was BPP6, next plane is BBP7
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP7_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP7_Byte;
-- BPP7
when 7 =>
-- in 8BPP mode or MODE7, next plane is BPP0 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
-- in any other cases, next plane is BPP6
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP6_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP6_Byte;
end if;
end case;
end if;
end if;
End Process;
-- output data process
Process( FSM_Ready_BPP0, FSM_Ready_BPP1, FSM_Ready_BPP2, FSM_Ready_BPP3, FSM_Ready_BPP4,
FSM_Ready_BPP5, FSM_Ready_BPP6, FSM_Ready_BPP7, BPP0_Byte, BPP1_Byte, BPP2_Byte,
BPP3_Byte, BPP4_Byte, BPP5_Byte, BPP6_Byte, BPP7_Byte, FSM_Ready_MODE7 )
Begin
FIFO_Data_tdata <= X"00";
-- send data to output register
if( FSM_Ready_MODE7 = '1' ) then
FIFO_Data_tdata(0) <= BPP0_Byte(0);
FIFO_Data_tdata(1) <= BPP1_Byte(0);
FIFO_Data_tdata(2) <= BPP2_Byte(0);
FIFO_Data_tdata(3) <= BPP3_Byte(0);
FIFO_Data_tdata(4) <= BPP4_Byte(0);
FIFO_Data_tdata(5) <= BPP5_Byte(0);
FIFO_Data_tdata(6) <= BPP6_Byte(0);
FIFO_Data_tdata(7) <= BPP7_Byte(0);
end if;
if( FSM_Ready_BPP0 = '1' ) then
FIFO_Data_tdata <= BPP0_Byte;
end if;
if( FSM_Ready_BPP1 = '1' ) then
FIFO_Data_tdata <= BPP1_Byte;
end if;
if( FSM_Ready_BPP2 = '1' ) then
FIFO_Data_tdata <= BPP2_Byte;
end if;
if( FSM_Ready_BPP3 = '1' ) then
FIFO_Data_tdata <= BPP3_Byte;
end if;
if( FSM_Ready_BPP4 = '1' ) then
FIFO_Data_tdata <= BPP4_Byte;
end if;
if( FSM_Ready_BPP5 = '1' ) then
FIFO_Data_tdata <= BPP5_Byte;
end if;
if( FSM_Ready_BPP6 = '1' ) then
FIFO_Data_tdata <= BPP6_Byte;
end if;
if( FSM_Ready_BPP7 = '1' ) then
FIFO_Data_tdata <= BPP7_Byte;
end if;
End Process;
FIFO_Data_tvalid <= FSM_Ready_MODE7 OR FSM_Ready_BPP0 OR FSM_Ready_BPP1 OR FSM_Ready_BPP2 OR FSM_Ready_BPP3 OR
FSM_Ready_BPP4 OR FSM_Ready_BPP5 OR FSM_Ready_BPP6 OR FSM_Ready_BPP7;
-- output FIFO
Output_Data : FIFO_B2B
Generic map(32, 30)
Port map(clk => clk,
srst => FSM_Reset,
din_tready => FIFO_Data_tready,
din_tvalid => FIFO_Data_tvalid,
din_tdata => FIFO_Data_tdata,
dout_tready => DMA_Data_tready,
dout_tvalid => DMA_Data_tvalid,
dout_tdata => DMA_Data_tdata,
prog_full => FIFO_Data_tready_n);
-- output signalling
BPP_Bit_tready <= FSM_BPP_Bit_tready;
DMA_In_Progress <= FSM_DMA_In_Progress;
-- finite state machine to ask for BPP bits to Probability Estimator module
Process( clk )
Begin
if rising_edge( clk ) then
if (DMA_Transfer_End = '1') then
estado <= WAIT_HEADER;
else
case estado is
-- wait until header is read from input
when WAIT_HEADER =>
if( Header_Valid = '1' ) then
-- decode 2BPP tiles
if( Header_BPP = "00" ) then
estado <= SET_2_BITPLANES;
-- decode 8BPP tiles
elsif( Header_BPP = "10" ) then
estado <= SET_4_BITPLANES;
-- decode 4BPP tiles
elsif( Header_BPP = "01" ) then
estado <= SET_8_BITPLANES;
-- decode arbitrary data
else
estado <= SET_MODE7_BITPLANE;
end if;
end if;
-- initialize number of BPP0/BPP1 loops
when SET_2_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_4_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_8_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_MODE7_BITPLANE =>
estado <= MODE7_BIT_0;
-- states to create BPP0 and BPP1
-- BPP0/BPP1 pixel 0
when BPP0_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_0_WAIT;
end if;
when BPP0_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_0;
end if;
when BPP1_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_0_WAIT;
end if;
when BPP1_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_1;
end if;
-- BPP0/BPP1 pixel 1
when BPP0_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_1_WAIT;
end if;
when BPP0_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_1;
end if;
when BPP1_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_1_WAIT;
end if;
when BPP1_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_2;
end if;
-- BPP0/BPP1 pixel 2
when BPP0_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_2_WAIT;
end if;
when BPP0_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_2;
end if;
when BPP1_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_2_WAIT;
end if;
when BPP1_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_3;
end if;
-- BPP0/BPP1 pixel 3
when BPP0_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_3_WAIT;
end if;
when BPP0_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_3;
end if;
when BPP1_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_3_WAIT;
end if;
when BPP1_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_4;
end if;
-- BPP0/BPP1 pixel 4
when BPP0_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_4_WAIT;
end if;
when BPP0_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_4;
end if;
when BPP1_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_4_WAIT;
end if;
when BPP1_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_5;
end if;
-- BPP0/BPP1 pixel 5
when BPP0_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_5_WAIT;
end if;
when BPP0_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_5;
end if;
when BPP1_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_5_WAIT;
end if;
when BPP1_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_6;
end if;
-- BPP0/BPP1 pixel 6
when BPP0_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_6_WAIT;
end if;
when BPP0_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_6;
end if;
when BPP1_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_6_WAIT;
end if;
when BPP1_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_7;
end if;
-- BPP0/BPP1 pixel 7
when BPP0_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_7_WAIT;
end if;
when BPP0_BIT_7_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_7;
end if;
when BPP1_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_7_WAIT;
end if;
when BPP1_BIT_7_WAIT =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '0' ) then
estado <= BPP0_BIT_0;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '1' ) then
estado <= BPP_BIT_STALL;
end if;
-- wait until FIFO is ready to accept data
when BPP_BIT_STALL =>
if( FIFO_Data_tready_n = '0' ) then
estado <= BPP0_BIT_0;
end if;
-- states to create 8 bitplanes in 1 byte
when MODE7_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_0_WAIT;
end if;
when MODE7_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_1;
end if;
when MODE7_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_1_WAIT;
end if;
when MODE7_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_2;
end if;
when MODE7_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_2_WAIT;
end if;
when MODE7_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_3;
end if;
when MODE7_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_3_WAIT;
end if;
when MODE7_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_4;
end if;
when MODE7_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_4_WAIT;
end if;
when MODE7_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_5;
end if;
when MODE7_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_5_WAIT;
end if;
when MODE7_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_6;
end if;
when MODE7_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_6_WAIT;
end if;
when MODE7_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_7;
end if;
when MODE7_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_7_WAIT;
end if;
when MODE7_BIT_7_WAIT =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '0' ) then
estado <= MODE7_BIT_0;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '1' ) then
estado <= MODE7_BIT_STALL;
end if;
when MODE7_BIT_STALL =>
if( FIFO_Data_tready_n = '0' ) then
estado <= MODE7_BIT_0;
end if;
end case;
end if;
end if;
End Process;
-- reset output FIFO
FSM_Reset <= '1' when estado = WAIT_HEADER else '0';
-- signals that DMA is running, so data is being outputted from S-DD1
FSM_DMA_In_Progress <= '0' when estado = WAIT_HEADER else '1';
-- strobe to signal a byte for an even bitplane has just completed
with estado select
FSM_Next_BPP0 <= BPP_Bit_tvalid when BPP0_BIT_7_WAIT,
BPP_Bit_tvalid when MODE7_BIT_7_WAIT,
'0' when others;
-- strobe to signal a byte for an odd bitplane has just completed
with estado select
FSM_Next_BPP1 <= BPP_Bit_tvalid when BPP1_BIT_7_WAIT,
'0' when others;
-- strobe to signal a new BPP pixel for MODE7 byte
with estado select
FSM_New_MODE7 <= BPP_Bit_tvalid when MODE7_BIT_1_WAIT,
BPP_Bit_tvalid when MODE7_BIT_3_WAIT,
BPP_Bit_tvalid when MODE7_BIT_5_WAIT,
BPP_Bit_tvalid when MODE7_BIT_7_WAIT,
'0' when others;
-- 2BPP tile or one 8x8 mode7 tile is finished
FSM_New_Tile <= FSM_Next_BPP1 when Tile_Count = 7 else Flag_MODE7_Bitplane;
-- indicates is an even or odd plane is being processed
with estado select
Cnt_Even <= 1 when BPP1_BIT_0,
1 when BPP1_BIT_0_WAIT,
1 when BPP1_BIT_1,
1 when BPP1_BIT_1_WAIT,
1 when BPP1_BIT_2,
1 when BPP1_BIT_2_WAIT,
1 when BPP1_BIT_3,
1 when BPP1_BIT_3_WAIT,
1 when BPP1_BIT_4,
1 when BPP1_BIT_4_WAIT,
1 when BPP1_BIT_5,
1 when BPP1_BIT_5_WAIT,
1 when BPP1_BIT_6,
1 when BPP1_BIT_6_WAIT,
1 when BPP1_BIT_7,
1 when BPP1_BIT_7_WAIT,
1 when MODE7_BIT_1,
1 when MODE7_BIT_1_WAIT,
1 when MODE7_BIT_3,
1 when MODE7_BIT_3_WAIT,
1 when MODE7_BIT_5,
1 when MODE7_BIT_5_WAIT,
1 when MODE7_BIT_7,
1 when MODE7_BIT_7_WAIT,
0 when others;
-- strobe for registering data from previous module
with estado select
FSM_BPP_Bit_tready <= '1' when BPP0_BIT_0,
'1' when BPP1_BIT_0,
'1' when BPP0_BIT_1,
'1' when BPP1_BIT_1,
'1' when BPP0_BIT_2,
'1' when BPP1_BIT_2,
'1' when BPP0_BIT_3,
'1' when BPP1_BIT_3,
'1' when BPP0_BIT_4,
'1' when BPP1_BIT_4,
'1' when BPP0_BIT_5,
'1' when BPP1_BIT_5,
'1' when BPP0_BIT_6,
'1' when BPP1_BIT_6,
'1' when BPP0_BIT_7,
'1' when BPP1_BIT_7,
'1' when MODE7_BIT_0,
'1' when MODE7_BIT_1,
'1' when MODE7_BIT_2,
'1' when MODE7_BIT_3,
'1' when MODE7_BIT_4,
'1' when MODE7_BIT_5,
'1' when MODE7_BIT_6,
'1' when MODE7_BIT_7,
'0' when others;
end Behavioral;
| gpl-2.0 | 09fc33b97cfc567740e21716e805b203 | 0.514487 | 2.617811 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys2/ahbrom.vhd | 1 | 7,460 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 432;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18C000";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"87444000";
when 16#00049# => romdata <= X"8730E01C";
when 16#0004A# => romdata <= X"8688E00F";
when 16#0004B# => romdata <= X"1280000A";
when 16#0004C# => romdata <= X"03200000";
when 16#0004D# => romdata <= X"05040E00";
when 16#0004E# => romdata <= X"8410A033";
when 16#0004F# => romdata <= X"C4204000";
when 16#00050# => romdata <= X"05000005";
when 16#00051# => romdata <= X"8410A25A";
when 16#00052# => romdata <= X"C4206004";
when 16#00053# => romdata <= X"050003FC";
when 16#00054# => romdata <= X"C4206008";
when 16#00055# => romdata <= X"05000008";
when 16#00056# => romdata <= X"82100000";
when 16#00057# => romdata <= X"80A0E000";
when 16#00058# => romdata <= X"02800005";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"82004002";
when 16#0005B# => romdata <= X"10BFFFFC";
when 16#0005C# => romdata <= X"8620E001";
when 16#0005D# => romdata <= X"3D103FFF";
when 16#0005E# => romdata <= X"BC17A3E0";
when 16#0005F# => romdata <= X"BC278001";
when 16#00060# => romdata <= X"9C27A060";
when 16#00061# => romdata <= X"03100000";
when 16#00062# => romdata <= X"81C04000";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"01000000";
when 16#00065# => romdata <= X"01000000";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"00000000";
when 16#00069# => romdata <= X"00000000";
when 16#0006A# => romdata <= X"00000000";
when 16#0006B# => romdata <= X"00000000";
when 16#0006C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 | f3f99bba698e1ac17a743749983602a5 | 0.578552 | 3.273366 | false | false | false | false |
mistryalok/Zedboard | learning/training/my/adder/hls/adder/solution1/syn/vhdl/adder.vhd | 1 | 5,790 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adder is
generic (
C_S_AXI_AXI_CTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXI_CTRL_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_AXI_CTRL_AWVALID : IN STD_LOGIC;
s_axi_AXI_CTRL_AWREADY : OUT STD_LOGIC;
s_axi_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_AXI_CTRL_WVALID : IN STD_LOGIC;
s_axi_AXI_CTRL_WREADY : OUT STD_LOGIC;
s_axi_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXI_CTRL_DATA_WIDTH/8-1 downto 0);
s_axi_AXI_CTRL_ARVALID : IN STD_LOGIC;
s_axi_AXI_CTRL_ARREADY : OUT STD_LOGIC;
s_axi_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_AXI_CTRL_RVALID : OUT STD_LOGIC;
s_axi_AXI_CTRL_RREADY : IN STD_LOGIC;
s_axi_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXI_CTRL_BVALID : OUT STD_LOGIC;
s_axi_AXI_CTRL_BREADY : IN STD_LOGIC;
s_axi_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC );
end;
architecture behav of adder is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"adder,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=150,HLS_SYN_LUT=264}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant C_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_0 : STD_LOGIC := '0';
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (31 downto 0);
signal b : STD_LOGIC_VECTOR (31 downto 0);
signal c : STD_LOGIC_VECTOR (31 downto 0);
signal c_ap_vld : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal adder_AXI_CTRL_s_axi_U_ap_dummy_ce : STD_LOGIC;
component adder_AXI_CTRL_s_axi IS
generic (
C_ADDR_WIDTH : INTEGER;
C_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
a : OUT STD_LOGIC_VECTOR (31 downto 0);
b : OUT STD_LOGIC_VECTOR (31 downto 0);
c : IN STD_LOGIC_VECTOR (31 downto 0);
c_ap_vld : IN STD_LOGIC );
end component;
begin
adder_AXI_CTRL_s_axi_U : component adder_AXI_CTRL_s_axi
generic map (
C_ADDR_WIDTH => C_S_AXI_AXI_CTRL_ADDR_WIDTH,
C_DATA_WIDTH => C_S_AXI_AXI_CTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_AXI_CTRL_AWVALID,
AWREADY => s_axi_AXI_CTRL_AWREADY,
AWADDR => s_axi_AXI_CTRL_AWADDR,
WVALID => s_axi_AXI_CTRL_WVALID,
WREADY => s_axi_AXI_CTRL_WREADY,
WDATA => s_axi_AXI_CTRL_WDATA,
WSTRB => s_axi_AXI_CTRL_WSTRB,
ARVALID => s_axi_AXI_CTRL_ARVALID,
ARREADY => s_axi_AXI_CTRL_ARREADY,
ARADDR => s_axi_AXI_CTRL_ARADDR,
RVALID => s_axi_AXI_CTRL_RVALID,
RREADY => s_axi_AXI_CTRL_RREADY,
RDATA => s_axi_AXI_CTRL_RDATA,
RRESP => s_axi_AXI_CTRL_RRESP,
BVALID => s_axi_AXI_CTRL_BVALID,
BREADY => s_axi_AXI_CTRL_BREADY,
BRESP => s_axi_AXI_CTRL_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => adder_AXI_CTRL_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
a => a,
b => b,
c => c,
c_ap_vld => c_ap_vld);
adder_AXI_CTRL_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
ap_done <= ap_start;
ap_idle <= ap_const_logic_1;
ap_ready <= ap_start;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
c <= std_logic_vector(unsigned(b) + unsigned(a));
-- c_ap_vld assign process. --
c_ap_vld_assign_proc : process(ap_start)
begin
if (not((ap_start = ap_const_logic_0))) then
c_ap_vld <= ap_const_logic_1;
else
c_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| gpl-3.0 | 6992a25ed581feb6ac8dbc37d6702049 | 0.586183 | 3.053797 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr1spax.vhd | 1 | 8,538 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax
-- File: ddr1spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR1 memory controller with asynch AHB interface
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddrphy_has_datavalid;
use techmap.gencomp.ddrphy_latency;
use techmap.gencomp.ddrphy_ptctrl;
entity ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 1;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end ddr1spax;
architecture rtl of ddr1spax is
constant REVISION : integer := 0;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
devid => GAISLER_DDRSP, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, '0', FTFE_BEID_DDR1);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => 0, revision => revision, devid => GAISLER_DDRSP)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, '0', '0', open, open, FTFE_BEID_DDR1);
end generate;
ddrc : ddr1spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, col => col, Mbyte => Mbyte,
nosync => nosync, burstlen => burstlen,
chkbits => ft*ddrbits/2, oepol => oepol, mobile => mobile,
confapi => confapi, conf0 => conf0, conf1 => conf1,
hasdqvalid => ddrphy_has_datavalid(phytech),
ddr_syncrst => ddr_syncrst, regoutput => regoutput,
readdly => ddrphy_latency(phytech)+regoutput, ddr400 => ddr400,
rstdel => rstdel, phyptctrl => ddrphy_ptctrl(phytech), scantest => scantest)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrspa: DDR controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | aa87ab547707c65c32faa2c5464e215f | 0.599204 | 3.882674 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/startBtn/simulation/startBtn_synth.vhd | 1 | 6,832 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: startBtn_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY startBtn_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE startBtn_synth_ARCH OF startBtn_synth IS
COMPONENT startBtn_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: startBtn_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 7eed8d4a230693ae12329a54c986836f | 0.580796 | 3.80825 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_1_0/sim/design_1_axi_bram_ctrl_1_0.vhd | 1 | 15,629 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_1_0;
ARCHITECTURE design_1_axi_bram_ctrl_1_0_arch OF design_1_axi_bram_ctrl_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_1_0_arch;
| gpl-3.0 | f163398239c5e0d465ea422a50d1a697 | 0.67074 | 3.100377 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/altera_mf/tap_altera_mf.vhd | 1 | 4,934 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => tapo_capt,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => tapo_upd,
virtual_state_uir => open);
end;
| gpl-2.0 | 8f2d65d342e113204fef0c34fd671c6a | 0.55756 | 3.31586 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | UnityControl.vhd | 1 | 4,687 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UnityControl is
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
we : out STD_LOGIC;
RFDest : out STD_LOGIC;
WrENMemory : out STD_LOGIC;
ReENMemory : out STD_LOGIC;
RfSource : out STD_LOGIC_VECTOR(1 downto 0);
PcSource : out STD_LOGIC_VECTOR(1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0));
end UnityControl;
architecture Behavioral of UnityControl is
signal nzvc : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin
-- Add 10 000000
-- Sub 10 000100
-- And 10 000001
-- Or 10 000010
-- Xor 10 000011
-- Orn 10 000110
-- Andn 10 000101
-- Xnor 10 000111
-- Addcc 10 010000
-- Subcc 10 010100
-- Addx 10 001000
-- Addxcc 10 011000
-- Subx 10 001100
-- Subxcc 10 011100
-- Orcc 10 010010
-- Andcc 10 010001
-- Xorcc 10 010011
-- Andncc 10 010101
-- Orncc 10 010110
-- Xnorncc 10 010111
-- SLL 10 100101
-- SRL 10 100111
-- Branchs
-- BA 00 1000
-- BN 00 0000
-- BNE 00 1001
-- BE 00 0001
-- BG 00 1010
-- BLE 00 0010
-- BGE 00 1011
-- BL 00 0011
-- BGU 00 1100
-- BLEU 00 0100
-- BCC 00 1101
-- BCS 00 0101
-- BPOS 00 1110
-- BNEG 00 0110
-- BVC 00 1111
-- BVS 00 0111
-- Jump and Link
-- jmpl 10 111000
-- Call 01 disp22
nzvc <= icc;
process(Op, Op3)
begin
case Op is
when "10" =>
case (Op3) is
when "000000" => -- Add
AluOp <= "000000";
when "000100" => -- Sub
AluOp <= "000001";
when "000001" => -- And
AluOp <= "000011";
when "000010" => -- Or
AluOp <= "000010";
when "000011" => -- Xor
AluOp <= "000100";
when "000110" => -- Orn
AluOp <= "000101";
when "000101" => -- Andn
AluOp <= "000110";
when "000111" => -- Xnor
AluOp <= "000111";
when "010000" => -- Addcc
AluOp <= "001000";
when "010100" => -- Subcc
AluOp <= "001001";
when "001000" => -- Addx
AluOp <= "001010";
when "011000" => -- Addxcc
AluOp <= "001011";
when "001100" => -- Subx
AluOp <= "001100";
when "011100" => -- Subxcc
AluOp <= "001101";
when "010010" => -- Orcc
AluOp <= "001110";
when "010001" => -- Andcc
AluOp <= "001111";
when "010011" => -- Xorcc
AluOp <= "010000";
when "010101" => -- Andncc
AluOp <= "010001";
when "010110" => -- Orncc
AluOp <= "010010";
when "010111" => -- Xnorncc
AluOp <= "010011";
when "100101" => -- SLL
AluOp <= "010100";
when "100111" => -- SRL
AluOp <= "010101";
when "111000" => -- Jmpl
AluOp <= "000000";
when others =>
AluOp <= "000000"; -- Error
end case;
if (Op3 = "111000") then
RfSource <= "01";
RFDest <= '1';
PcSource <= "11";
else
RfSource <= "00";
RFDest <= '0';
PcSource <= "00";
end if;
we <= '1';
WrENMemory <= '0';
ReENMemory <= '0';
when "01" => -- Call
we <= '1';
RFDest <= '1';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "01";
PcSource <= "10";
AluOp <= "000000";
when "00" => -- Branch
we <= '0';
RFDest <= '0';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "00";
PcSource(1) <= '0';
case cond is
when "1000" => -- BA
PcSource(0) <= '1';
when "0000" => -- BN
PcSource(0) <= '0';
when "1001" => -- BNE
PcSource(0) <= not nzvc(2);
when "0001" => -- BE
PcSource(0) <= nzvc(2);
when "1010" => -- BG
PcSource(0) <= not (nzvc(2) or (nzvc(3) xor nzvc(1)));
when "0010" => -- BLE
PcSource(0) <= nzvc(2) or (nzvc(3) xor nzvc(1));
when "1011" => -- BGE
PcSource(0) <= not (nzvc(3) xor nzvc(1));
when "0011" => -- BL
PcSource(0) <= nzvc(3) xor nzvc(1);
when "1100" => -- BGU
PcSource(0) <= not (nzvc(0) or nzvc(2));
when "0100" => -- BLEU
PcSource(0) <= nzvc(0) or nzvc(2);
when "1101" => -- BCC
PcSource(0) <= not nzvc(0);
when "0101" => -- BCS
PcSource(0) <= nzvc(0);
when "1110" => -- BPOS
PcSource(0) <= not nzvc(3);
when "0110" => -- BNEG
PcSource(0) <= nzvc(0);
when "1111" => -- BVC
PcSource(0) <= not nzvc(1);
when "0111" => -- BVS
PcSource(0) <= nzvc(1);
when others =>
PcSource(0) <= '0';
end case;
when others =>
we <= '0';
RFDest <= '0';
WrENMemory <= '0';
ReENMemory <= '0';
RfSource <= "00";
PcSource <= "00";
AluOp <= "000000";
end case;
end process;
end Behavioral; | mit | 68ee54c8c4c1b35d2a5c9561c1493f40 | 0.521229 | 2.70612 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd | 1 | 1,999 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clk50;
when "10" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 | 03454ac6ee91e89e03373aa71e840ef3 | 0.630815 | 3.829502 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/virage/memory_virage.vhd | 1 | 16,150 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
| gpl-2.0 | 323b56c2e67f6ede2b1e5675d2eff545 | 0.621238 | 2.915162 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25-eek/leon3mp.vhd | 1 | 34,070 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- DDR
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- I/O port
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
-- Connections over HSMC connector
-- LCD touch panel display
hc_vd : out std_logic;
hc_hd : out std_logic;
hc_den : out std_logic;
hc_nclk : out std_logic;
hc_lcd_data : out std_logic_vector(7 downto 0);
hc_grest : out std_logic;
hc_scen : out std_logic;
hc_sda : inout std_logic;
hc_adc_penirq_n : in std_logic;
hc_adc_dout : in std_logic;
hc_adc_busy : in std_logic;
hc_adc_din : out std_logic;
hc_adc_dclk : out std_logic;
hc_adc_cs_n : out std_logic; -- Shared with video decoder
-- Shared by video decoder and audio codec
hc_i2c_sclk : out std_logic;
hc_i2c_sdat : inout std_logic;
-- Video decoder
hc_td_d : inout std_logic_vector(7 downto 0);
hc_td_hs : in std_logic;
hc_td_vs : in std_logic;
hc_td_27mhz : in std_logic;
hc_td_reset : out std_logic;
-- Audio codec
hc_aud_adclrck : out std_logic;
hc_aud_adcdat : in std_logic;
hc_aud_daclrck : out std_logic;
hc_aud_dacdat : out std_logic;
hc_aud_bclk : out std_logic;
hc_aud_xck : out std_logic;
-- SD card
hc_sd_dat : inout std_logic;
hc_sd_dat3 : inout std_logic;
hc_sd_cmd : inout std_logic;
hc_sd_clk : inout std_logic;
-- Ethernet PHY
hc_tx_d : out std_logic_vector(3 downto 0);
hc_rx_d : in std_logic_vector(3 downto 0);
hc_tx_clk : in std_logic;
hc_rx_clk : in std_logic;
hc_tx_en : out std_logic;
hc_rx_dv : in std_logic;
hc_rx_crs : in std_logic;
hc_rx_err : in std_logic;
hc_rx_col : in std_logic;
hc_mdio : inout std_logic;
hc_mdc : out std_logic;
hc_eth_reset_n : out std_logic;
-- RX232 (console/debug UART)
hc_uart_rxd : in std_logic;
hc_uart_txd : out std_logic;
-- PS/2
hc_ps2_dat : inout std_logic;
hc_ps2_clk : inout std_logic;
-- VGA/DAC
hc_vga_data : out std_logic_vector(9 downto 0);
hc_vga_clock : out std_ulogic;
hc_vga_hs : out std_ulogic;
hc_vga_vs : out std_ulogic;
hc_vga_blank : out std_ulogic;
hc_vga_sync : out std_ulogic;
-- I2C EEPROM
hc_id_i2cscl : out std_logic;
hc_id_i2cdat : inout std_logic
);
end;
architecture rtl of leon3mp is
component serializer
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end component;
component altera_eek_clkgen
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
CFG_SVGA_ENABLE+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ps2i : ps2_in_type;
signal ps2o : ps2_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal lcdo : apbvga_out_type;
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_den : std_ulogic;
signal lcd_grest : std_ulogic;
signal lcdspii : spi_in_type;
signal lcdspio : spi_out_type;
signal lcdslvsel : std_logic_vector(1 downto 0);
signal lcdclksel : std_logic_vector(1 downto 0);
signal lcdclk : std_ulogic;
signal lcdclk3x : std_ulogic;
signal lcdclklck : std_ulogic;
signal vgao : apbvga_out_type;
signal vga_data : std_logic_vector(9 downto 0);
signal vgaclksel : std_logic_vector(1 downto 0);
signal vgaclk : std_ulogic;
signal vgaclk3x : std_ulogic;
signal vgaclklck : std_ulogic;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of lcdclk : signal is true;
attribute syn_keep of lcdclk3x : signal is true;
attribute syn_keep of vgaclk : signal is true;
attribute syn_keep of vgaclk3x : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rawrstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AVOID BUS CONTENTION --------------------------------------------
----------------------------------------------------------------------
-- This design uses the ethernet PHY and we must therefore disable the
-- video decoder and stay away from the touch panel.
-- Video coder
hc_td_reset <= '0'; -- Video Decoder Reset
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller
spimctrl0 : spimctrl
generic map (hindex => 4,
hirq => 7,
faddr => 16#b00#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (hc_sd_dat, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (hc_sd_cmd, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (hc_sd_clk, spmo.sck);
slvsel0_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- Timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
gpioi.din(i) <= gpio(i);
end generate;
gpioi.din(3) <= hc_adc_penirq_n;
gpioi.din(4) <= hc_adc_busy;
end generate;
ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
end generate;
nops2 : if CFG_PS2_ENABLE = 0 generate
apbo(4) <= apb_none; ps2o <= ps2o_none;
end generate;
ps2clk_pad : iopad generic map (tech => padtech)
port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
ps2data_pad : iopad generic map (tech => padtech)
port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 8, paddr => 8, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
-- The EEK does not use a bi-directional line for the I2C clock
i2ci.scl <= i2co.scloen; -- No clock stretch possible
-- When SCL output enable is activated the line should go low
i2c_scl_pad : outpad generic map (tech => padtech)
port map (hc_id_i2cscl, i2co.scloen);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 7,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 1,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (hc_sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
-----------------------------------------------------------------------
-- LCD touch panel ---------------------------------------------------
-----------------------------------------------------------------------
lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
lcdser0: serializer generic map (length => 8)
port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
lcdo.video_out_r, lcd_data);
lcdclksel <= "00";
lcdclkgen : altera_eek_clkgen
generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
clk1_div => 50, clk_freq => BOARD_FREQ)
port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
lcd_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vd, lcdo.vsync);
lcd_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_hd, lcdo.hsync);
lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
port map (hc_lcd_data, lcd_data);
lcd_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_nclk, lcdclk3x);
lcd_den <= lcdo.blank;
end generate;
nolcd : if CFG_LCD_ENABLE = 0 generate
apbo(11) <= apb_none; lcdo <= vgao_none;
lcd_den <= '0'; -- LCD RGB Data Enable
lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
end generate;
lcd_den_pad : outpad generic map (tech => padtech)
port map (hc_den, lcd_den);
lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
lcd_grest <= rstn;
end generate;
lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
lcd_grest <= '0';
end generate lcdalwaysreset;
lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
port map (hc_grest, lcd_grest);
touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
-- TODO:
-- Interrupt and busy signals not connected
touch3spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0,
syncram => 0, ft => 0)
port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
adc_miso_pad : inpad generic map (tech => padtech)
port map (hc_adc_dout, lcdspii.miso);
adc_mosi_pad : outpad generic map (tech => padtech)
port map (hc_adc_din, lcdspio.mosi);
lcd_adc_dclk_pad : outpad generic map (tech => padtech)
port map (hc_adc_dclk, lcdspio.sck);
hcd_sda_pad : iopad generic map (tech => padtech)
port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
lcdspii.spisel <= '1'; -- Master only
end generate;
notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
lcdslvsel <= (others => '1');
apbo(12) <= apb_none;
end generate;
hc_adc_cs_n_pad : outpad generic map (tech => padtech)
port map (hc_adc_cs_n, lcdslvsel(0));
hc_scen_pad : outpad generic map (tech => padtech)
port map (hc_scen, lcdslvsel(1));
-----------------------------------------------------------------------
-- SVGA controller ----------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
vgaclksel);
svgaser0: serializer generic map (length => 8)
port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
vgao.video_out_r, vga_data(9 downto 2));
vga_data(1 downto 0) <= (others => '0');
vgaclkgen : altera_eek_clkgen
generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
clk1_div => 5, clk_freq => BOARD_FREQ)
port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
vga_blank_pad : outpad generic map (tech => padtech)
port map (hc_vga_blank, vgao.blank);
vga_comp_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_sync, vgao.comp_sync);
vga_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_vs, vgao.vsync);
vga_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_hs, vgao.hsync);
vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
port map (hc_vga_data, vga_data);
vga_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_vga_clock, vgaclk3x);
end generate svga;
nosvga : if CFG_SVGA_ENABLE = 0 generate
apbo(13) <= apb_none; vgao <= vgao_none;
vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (hc_rx_d, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (hc_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (hc_rx_err, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (hc_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (hc_rx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (hc_tx_d, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (hc_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (hc_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (hc_eth_reset_n, rawrstn);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 2f36eb9e27825a4a9f1610a95fd8e065 | 0.548635 | 3.611023 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/techbuf.vhd | 1 | 4,672 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_fusion is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3e is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3l is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 6 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut130hbd is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_nextreme is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_n2x is generic(buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
fus : if (tech = actfus) generate
fus0 : clkbuf_fusion generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3 : if (tech = apa3) generate
pa30 : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3e : if (tech = apa3e) generate
pae30 : clkbuf_apa3e generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3l : if (tech = apa3l) generate
pa3l0 : clkbuf_apa3l generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
axc0 : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (is_unisim(tech) = 1) generate
xil0 : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
ut0 : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut13 : if (tech = ut130) generate
ut0 : clkbuf_ut130hbd generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut09 : if (tech = ut90) generate
ut0 : clkand_ut90nhbd port map(i => i, en => vcc, o => o, tsten => gnd);
end generate;
easic: if tech = easic90 generate
eas : clkbuf_nextreme generic map (buftype => buftype) port map(i => i, o => o);
end generate easic;
n2x : if tech = easic45 generate
n2x0 : clkbuf_n2x generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
| gpl-2.0 | 7e6c2bf9b55c1b71197db6b7f84c64a7 | 0.633776 | 3.497006 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/iodpad.vhd | 1 | 5,110 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
| gpl-2.0 | 3ca1b5c62c8310fe443e809b4d367039 | 0.627789 | 3.502399 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/stdlib/config_types.vhd | 1 | 2,411 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config_types
-- File: config_types.vhd
-- Description: GRLIB Global configuration types package.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package config_types is
-----------------------------------------------------------------------------
-- Configuration constants part of GRLIB configuration array
-----------------------------------------------------------------------------
-- debug level and debug mask controls debug output from tech map
constant grlib_debug_level : integer := 0;
constant grlib_debug_mask : integer := 1;
-- Defines if strict RAM techmap should be used. Otherwise small (shallow)
-- RAMs may be mapped to inferred technology.
constant grlib_techmap_strict_ram : integer := 2;
-- Expand testin vector to syncrams with additional bits
constant grlib_techmap_testin_extra : integer := 3;
-- Add synchronous resets to all registers (requires support in IP cores)
constant grlib_sync_reset_enable_all : integer := 4;
-- Use asynchronous reset, with this option enabled all registers will be
-- reset using asynchronous reset (within IP cores that support this).
constant grlib_async_reset_enable : integer := 5;
type grlib_config_array_type is array (0 to 6) of integer;
end;
| gpl-2.0 | b975a170def3a6dd94e58f371aff5043 | 0.60224 | 4.851107 | false | true | false | false |
Luisda199824/ProcesadorMonociclo | TB_Procesador.vhd | 1 | 1,067 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Procesador IS
END TB_Procesador;
ARCHITECTURE behavior OF TB_Procesador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT unionModulos
PORT(
clk : IN std_logic;
rst : IN std_logic;
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: unionModulos PORT MAP (
clk => clk,
rst => rst,
salida => salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 15 ns;
rst <= '0';
wait;
end process;
END;
| mit | 745fee21397dc2ef0a5b25931e380391 | 0.582006 | 3.616949 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/dmactrl.vhd | 1 | 19,010 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dmactrl
-- File: dmactrl.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Modified: Nils-Johan Wessman - Gaisler Research
-- Description: Simple DMA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity dmactrl is
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
blength : integer := 4
);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type
);
end;
architecture rtl of dmactrl is
constant BURST_LENGTH : integer := blength;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DMACTRL, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type state_type is(idle, read1, read2, read3, read4, read5, write1, write2, writeb, write3, write4, turn);
type rbuf_type is array (0 to 2) of std_logic_vector(31 downto 0);
type dmactrl_reg_type is record
state : state_type;
addr0 : std_logic_vector(31 downto 2);
addr1 : std_logic_vector(31 downto 2);
hmbsel : std_logic_vector(0 to NAHBAMR-1);
htrans : std_logic_vector(1 downto 0);
rbuf : rbuf_type;
write : std_logic;
start_req : std_logic;
start : std_logic;
ready : std_logic;
err : std_logic;
first0 : std_logic;
first1 : std_logic;
no_ws : std_logic; -- no wait states
blimit : std_logic; -- 1k limit
dmao_start: std_logic;
dmao_ready: std_logic; -- sets if ready responce in read4, not set two_in_buf if retry on second access in buf
two_in_buf: std_logic; -- two words in rbuf to be stored
burstl_p : std_logic_vector(BURST_LENGTH - 1 downto 0); -- pci access counter
burstl_a : std_logic_vector(BURST_LENGTH - 1 downto 0); -- amba access counter
ahb0_htrans : std_logic_vector(1 downto 0);
ahb0_hresp : std_logic_vector(1 downto 0);
ahb0_hready : std_logic;
ahb0_retry : std_logic;
ahb0_hsel : std_logic;
start_del : std_logic;
end record;
signal r,rin : dmactrl_reg_type;
signal dmai : pci_ahb_dma_in_type;
signal dmao : pci_ahb_dma_out_type;
begin
comb : process(rst,r,dmao,apbi,ahbsi0,ahbso1)
variable v : dmactrl_reg_type;
variable vdmai : pci_ahb_dma_in_type;
variable pdata : std_logic_vector(31 downto 0);
variable slvbusy : ahb_slv_out_type;
variable dma_done, pci_done : std_logic;
variable bufloc : integer range 0 to 2;
begin
slvbusy := ahbso1; v := r;
vdmai.burst := '1'; vdmai.address := r.addr0 & "00";
vdmai.write := not r.write; vdmai.start := '0'; vdmai.size := "10";
vdmai.wdata := r.rbuf(0); pdata := (others => '0');
vdmai.busy := '0'; vdmai.irq := '0';
bufloc := 0;
v.start_del := r.start;
--slvbusy.hready := '1'; slvbusy.hindex := hindex; --slvbusy.hresp := "00";
--v.ahb0_htrans := ahbsi0.htrans; v.ahb0_retry := '0';
--v.ahb0_hsel := ahbsi0.hsel(slvindex); v.ahb0_hready := ahbsi0.hready;
v.ahb0_hready := '1'; v.ahb0_hresp := HRESP_OKAY; v.ahb0_retry := '0';
slvbusy.hready := r.ahb0_hready; slvbusy.hresp := r.ahb0_hresp;
-- AMBA busy response when dma is running
--if r.ahb0_retry = '1' then slvbusy.hresp := "10";
--else slvbusy.hresp := "00"; end if;
if r.ahb0_retry = '1' then v.ahb0_hresp := HRESP_RETRY; end if;
--if r.ahb0_htrans = "10" and (r.start = '1') and r.ahb0_hsel = '1' and r.ahb0_hready = '1' then
-- slvbusy.hready := '0';
-- slvbusy.hresp := "10";
-- v.ahb0_retry := '1';
--end if;
if ahbsi0.htrans = "10" and (r.start = '1') and ahbsi0.hsel(slvindex) = '1' and ahbsi0.hready = '1' then
v.ahb0_hready := '0';
v.ahb0_hresp := HRESP_RETRY;
v.ahb0_retry := '1';
end if;
-- Done signals
if (r.burstl_a(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- AMBA access done
dma_done := '1'; else dma_done := '0'; end if;
if (r.burstl_p(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- PCI access done
pci_done := '1'; else pci_done := '0'; end if;
-- APB interface
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.start_req := apbi.pwdata(0);
v.write := apbi.pwdata(1);
v.ready := r.ready and not apbi.pwdata(2);
v.err := r.err and not apbi.pwdata(3);
v.hmbsel := apbi.pwdata(7 downto 4);
end if;
pdata := zero32(31 downto 8) & r.hmbsel & r.err & r.ready & r.write & r.start_req;
when "001" =>
if apbi.pwrite = '1' then v.addr0 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr0 & "00";
when "010" =>
if apbi.pwrite = '1' then v.addr1 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr1 & "00";
when "011" =>
if apbi.pwrite = '1' then
v.burstl_p := apbi.pwdata(BURST_LENGTH - 1 downto 0);
v.burstl_a := apbi.pwdata(BURST_LENGTH - 1 downto 0);
end if;
pdata := zero32(31 downto BURST_LENGTH) & r.burstl_p;
when others =>
end case;
end if;
-- can't start dma until AMBA slave is idle
if r.start_req = '1' and (ahbsi0.hready = '1' and (ahbsi0.htrans = "00" or ahbsi0.hsel(slvindex) = '0')) then
v.start := '1';
end if;
case r.state is
when idle =>
v.htrans := "00";
v.first0 := '1'; v.first1 := '1';
v.no_ws := '0'; v.dmao_start := '0'; v.blimit := '0';
if r.start = '1' then
if r.write = '0' then v.state := read1;
else v.state := write1; end if;
end if;
when read1 => -- Start PCI read
bufloc := 0;
v.htrans := "10";
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if r.htrans(1) = '1' then
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
else
v.htrans := "11";
v.state := read2;
end if;
end if;
elsif ahbso1.hready = '0' then
v.htrans := "11";
else
v.htrans := "00";
end if;
when read2 => -- fill rbuf (3 words)
if r.first1 = '1' then bufloc := 1; -- store 3 words
else bufloc := 2; end if;
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
--if r.htrans = "11" then
if r.htrans(1) = '1' then
v.first1 := '0';
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
elsif r.first1 = '0' then
v.htrans := "01";
v.state := read3;
v.first0 := '1';
end if;
end if;
elsif ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
v.htrans := "00";
else
if ahbso1.hresp = HRESP_RETRY then
v.htrans := "10";
else
v.htrans := "11";
end if;
end if;
when read3 => -- write to AMBA and read from PCI
vdmai.start := '1';
bufloc := 1;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else
bufloc := 2;
if dmao.active = '1' then v.no_ws := '0'; end if;
end if;
if dmao.active = '0' then v.blimit := '1';
else v.blimit := '0'; end if;
if dmao.ready = '1' then
v.first0 := '0';
v.htrans := "11";
else
v.htrans := "01";
end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY and pci_done = '1' then
v.state := read5;
v.htrans := "00";
elsif r.htrans(1) = '1' and ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
if dmao.active = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf to store
v.state := read4;
v.htrans := "01";
if bufloc = 2 then v.dmao_ready := '0'; end if;
end if;
when read4 => -- PCI retry
bufloc := 1;
--if dmao.ready = '1' then v.two_in_buf := '0'; end if;
if dmao.ready = '1' then v.two_in_buf := '0'; v.dmao_ready := '1'; end if;
if dmao.retry = '1' and r.dmao_ready = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf if retry/split
if dmao.retry = '1' then v.dmao_start := '0'; end if; -- retry last word
if dmao.start = '1' and r.two_in_buf = '0' then v.dmao_start := '1'; end if;
if r.no_ws = '1' and r.dmao_start = '1' then vdmai.start := '0';
elsif dmao.start = '1' and r.two_in_buf = '0' then v.no_ws := '1'; vdmai.start := '0';
else vdmai.start := '1'; end if;
--if dmao.ready = '1' and r.no_ws = '1' and r.two_in_buf = '0' then -- handle change of waitstates (sdram refresh)
if (dmao.ready = '1' or (dmao.active = '0' and r.dmao_start = '1')) and r.no_ws = '1' and r.two_in_buf = '0' then
v.first0 := '1';
v.first1 := '1';
v.no_ws := '0';
v.dmao_start := '0';
v.state := read1;
end if;
when read5 => -- PCI read done
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then vdmai.start := '1'; end if;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else bufloc := 2; end if;
if dmao.ready = '1' and dma_done = '1' then
v.state := turn;
end if;
when write1 => -- Read first from AMBA
bufloc := 0;
v.first1 := '1'; v.no_ws := '0';
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '1' and (r.first0 = '0' or dmao.start = '1') then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then
if dma_done = '1' then v.state := write4;
else v.state := write2; end if;
v.htrans := "10"; -- start access to PCI
end if;
when write2 => -- Read from AMBA and write to PCI
bufloc := 0;
if (dmao.ready and dmao.start) = '1' then v.no_ws := '1'; end if; -- no wait state on AMBA ?
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dmao.ready = '1' then -- Data ready write to PCI
v.htrans := "11";
if dma_done = '1' then
v.state := write4;
end if;
else v.htrans := "01"; end if;
if ahbso1.hready = '0' then
vdmai.start := '0';
if v.no_ws = '1' then bufloc := 1; end if;
if dmao.active = '0' then v.state := writeb; -- AMBA 1k limit
else v.state := write3; v.dmao_ready := '1'; end if; -- assume ready responce, change later of retry/split
elsif dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then
vdmai.start := '1';
end if;
when writeb => -- AMBA 1k limit and PCI retry
bufloc := 1;
if dmao.active = '1' then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then v.state := write3; v.dmao_ready := '1'; end if;
when write3 => -- Retry from PCI
bufloc := 1;
--if ahbso1.hready = '1' then v.htrans := "10"; -- wait for AMBA access to be done before retry
--if (ahbso1.hready and (dmao.ready or not dmao.active)) = '1' then v.htrans := "10";
if (ahbso1.hready and (dmao.ready or (not dmao.active and r.dmao_ready))) = '1' then v.htrans := "10"; -- handle retry (don't start until ready)
else v.htrans := "01"; end if;
-- handle retry/split (restart access)
if dmao.retry = '1' then v.dmao_ready := '0';
elsif dmao.ready = '1' then v.dmao_ready := '1'; end if;
if r.dmao_ready = '0' and dmao.active = '0' then vdmai.start := '1';
else vdmai.start := '0'; end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if pci_done = '1' then
v.htrans := "00";
v.state := turn;
elsif dma_done = '1' and r.burstl_a(0) = '0' then
v.htrans := "01";
v.state := write4;
else
v.htrans := "11";
v.first0 := '1';
v.state := write2;
end if;
end if;
when write4 => -- Done read AMBA
v.htrans := "11";
if pci_done = '1' and ahbso1.hready = '1' and r.htrans(1) = '1' then
v.htrans := "00";
v.state := turn;
elsif ahbso1.hready = '0' then
v.state := write3;
v.htrans := "01";
v.dmao_ready := '1';
end if;
when turn =>
v.htrans := "00";
-- can't switch off dma until AMBA slave is idle
if (ahbsi0.hsel(slvindex) = '0' and r.ahb0_retry = '0' and ahbsi0.hready = '1')
or (ahbsi0.htrans = "00" and ahbsi0.hready = '1') or r.ahb0_retry = '1' then
v.ready := '1'; v.first1 := '1'; v.start_req := '0';
v.start := '0'; v.state := idle;
end if;
end case;
if ((r.htrans(1) and ahbso1.hready) = '1' and ahbso1.hresp = HRESP_OKAY) then -- PCI access done
v.burstl_p := r.burstl_p - '1'; -- dec counter
v.addr1 := r.addr1 + '1'; -- inc address (PCI)
if (r.write = '0' or r.state = write4 or r.state = write3) then
if r.state /= read1 and r.state /= read2 and (v.no_ws = '1' or r.state = write3) and v.blimit = '0' then
v.rbuf(0) := r.rbuf(1); -- dont update if wait states
v.rbuf(1) := r.rbuf(2); --
end if;
if r.write = '0' then v.rbuf(bufloc) := ahbreadword(ahbso1.hrdata); end if; -- PCI to AMBA
end if; -- if wait states store in buf(2) else
end if; -- in buf(1). Frist word in buf(0)
if dmao.ready = '1' then -- AMBA access done
v.burstl_a := r.burstl_a - '1'; -- dec counter
v.addr0 := r.addr0 + 1; -- inc address (AMBA master)
if r.write = '1' then
if r.state /= write3 and bufloc = 0 then -- dont update if retry from PCI
v.rbuf(0) := r.rbuf(1);
v.rbuf(1) := r.rbuf(2);
end if;
v.rbuf(bufloc) := dmao.rdata; -- AMBA to PCI
elsif r.write = '0' and (r.first0 = '1' or v.state = read4 or r.state = read5 or (v.no_ws = '0' or r.blimit = '1')) then
v.rbuf(0) := r.rbuf(1); -- update when data is written if wait states or PCI retry or PCI done
v.rbuf(1) := r.rbuf(2);
end if;
end if;
--if (ahbso1.hresp = HRESP_ERROR or (dmao.mexc or dmao.retry) = '1') then
if (ahbso1.hresp = HRESP_ERROR or dmao.mexc = '1') then
v.err := '1'; v.state := turn; v.htrans := HTRANS_IDLE;
end if;
--cancel dma
if r.start = '1' and r.start_req = '0' then
v.state := turn;
end if;
if rst = '0' then
v.state := idle;
v.start := '0';
v.start_req := '0';
v.write := '0';
v.err := '0';
v.ready := '0';
v.first1 := '1';
v.two_in_buf := '0';
v.hmbsel := (others => '0');
v.addr1 := (others => '0');
end if;
if r.start = '1' then
ahbsi1.hsel <= (others => '1');
ahbsi1.hmbsel(0 to 3) <= r.hmbsel;
ahbsi1.hsize <= "010";
ahbsi1.hwrite <= r.write;
ahbsi1.htrans <= v.htrans;
-- ahbsi1.haddr <= r.addr1 & "00";
ahbsi1.haddr <= v.addr1 & "00";
ahbsi1.hburst <= "001";
ahbsi1.hwdata <= ahbdrivedata(r.rbuf(0));
ahbsi1.hready <= ahbso1.hready;
ahbsi1.hmaster <= conv_std_logic_vector(hindex,4);
ahbso0 <= slvbusy;
else
ahbsi1.hsel <= ahbsi0.hsel;
ahbsi1.hmbsel(0 to 3) <= ahbsi0.hmbsel(0 to 3);
ahbsi1.hsize <= ahbsi0.hsize;
ahbsi1.hwrite <= ahbsi0.hwrite;
ahbsi1.htrans <= ahbsi0.htrans;
ahbsi1.haddr <= ahbsi0.haddr;
ahbsi1.hburst <= ahbsi0.hburst;
ahbsi1.hwdata <= ahbsi0.hwdata;
ahbsi1.hready <= ahbsi0.hready;
ahbsi1.hmaster <= ahbsi0.hmaster;
ahbso0 <= ahbso1;
if r.ahb0_hresp = HRESP_RETRY then
ahbso0.hready <= r.ahb0_hready; ahbso0.hresp <= r.ahb0_hresp;
end if;
v.state := idle;
end if;
dmai <= vdmai;
rin <= v;
apbo.pconfig <= pconfig;
apbo.prdata <= pdata;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= v.ready and not r.ready;
apbo.pindex <= pindex;
ahbsi1.hirq <= (others => '0');
ahbsi1.hprot <= (others => '0');
ahbsi1.hmastlock <= '0';
ahbsi1.testen <= '0';
ahbsi1.testrst <= '0';
ahbsi1.scanen <= '0';
ahbsi1.testoen <= '0';
ahbsi1.testin <= ahbsi0.testin;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r <= rin;
end if;
end process;
ahbmst0 : pciahbmst generic map (hindex => hindex, devid => GAISLER_DMACTRL, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("dmactrl" & tost(pindex) &
": 32-bit DMA controller & AHB/AHB bridge rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 1062fcc0798acf333571e7387506a509 | 0.536086 | 3.190133 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/sparc/sparc.vhd | 1 | 10,265 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
constant CASA : op3_type := "111100";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FSTOD : fpop_type := "011001001";
constant FDTOS : fpop_type := "011000110";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FSMULD : fpop_type := "001101001";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
constant TT_ICERR : trap_type := "110000"; -- icache correctable error
constant TT_DCERR : trap_type := "110100"; -- dcache correctable error
constant TT_RCERR : trap_type := "111000"; -- RF correctable error
-- Alternate address space identifiers (only 5 lsb bist are used)
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
| gpl-2.0 | 09e870c3abe98d36b1dc53ba1b192b6d | 0.625329 | 3.302767 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_dst_data_stream_1_V.vhd | 2 | 4,629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_data_stream_1_V is
component FIFO_image_filter_p_dst_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_data_stream_1_V_shiftReg : FIFO_image_filter_p_dst_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 96aed9f62f3bb79f0beb3829c96bf9ed | 0.537697 | 3.449329 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/chips/rtl_ds1302.vhd | 1 | 8,690 | -------------------------------------------------------------------------------
--
-- Title : rtl_ds1302
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : There is a serial interface controller for ds1302 chip.
-- Serial interface has 3 ports (i/o, clk, enable).
-- User interface has 4 ports:
-- data_i - input data, from fpga to chip,
-- data_o - output data, from chip to fpga,
-- addr_i - sets address for read/write,
-- enable - start of operation.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rtl_ds1302 is
generic (
TD : in time; --! simulation time;
DIV_SCL : in integer --! clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; --! system frequency (50 MHz)
rstn : in std_logic; --! negative reset
-- main interface
enable : in std_logic; --! serial start (S)
addr_i : in std_logic_vector(7 downto 0); --! address Tx: 7 bit - always '1', 0 bit - R/W ('0' - write, '1' - read)
data_i : in std_logic_vector(7 downto 0); --! data (Tx)
data_o : out std_logic_vector(7 downto 0); --! data (Rx)
data_v : out std_logic; --! valid Rx
ready : out std_logic; --! ready for data
-- serial interface
ds_data_i : in std_logic; --! serial data input
ds_data_o : out std_logic; --! serial data output
ds_data_t : out std_logic; --! serial data enable
ds_clk : out std_logic; --! serial clock
ds_ena : out std_logic --! clock enable for i2c
);
end rtl_ds1302;
architecture rtl_ds1302 of rtl_ds1302 is
type fsm_serial is ( RDY, START, WAITING, DATA, ADDR,
CLK_RISE, CLK_FALL, CLK_ONE,
WRITE, CLK_WR_R, CLK_WR1, CLK_WR_F,
CLK_RD_R, CLK_RD1, CLK_RD_F, STOP);
signal STM : fsm_serial;
signal dat_s : std_logic;
signal dat_e : std_logic;
signal clk_s : std_logic;
signal clk_r : std_logic;
signal clk_f : std_logic;
signal clk_z : std_logic;
signal cnt : std_logic_vector(3 downto 0);
signal reg_iic : std_logic_vector(7 downto 0);
signal reg_in : std_logic_vector(7 downto 0);
signal clk_low : std_logic;
signal scl_cnt : integer range 0 to DIV_SCL:=0;
signal rdwr : std_logic;
signal data_b : std_logic;
signal data_vl : std_logic;
-- delete this:
--signal ena_cnt : std_logic_vector(12 downto 0);
--signal ena_stw : std_logic;
--signal ena_vld : std_logic:='0';
--signal ena_stwz : std_logic;
--signal ena_stwx : std_logic;
begin
-- test ce inactive time:
--ena_vld <= '1' when (enable = '1') else '0' when (data_vl = '1');
--pr_ce_inactive: process(clk50m, rstn) is
--begin
-- if (rstn = '0') then
-- ena_stw <= '0';
-- ena_cnt <= (others => '0');
-- elsif (rising_edge(clk50m)) then
-- if (ena_vld = '1') then
-- if ena_cnt(12) = '0' then
-- ena_stw <= '0' after td;
-- ena_cnt <= ena_cnt + 1 after td;
-- else
-- ena_stw <= '1' after td;
-- end if;
-- else
-- ena_cnt <= (others => '0') after td;
-- end if;
-- end if;
--end process;
--ena_stwz <= ena_stw after td when rising_edge(clk50m);
--ena_stwx <= (ena_stw and not ena_stwz) after td when rising_edge(clk50m);
rdwr <= addr_i(0);-- after td when rising_edge(clk);
-- clk_low generator:
pr_cnt_serial: process(clk50m, rstn) is
begin
if (rstn = '0') then
scl_cnt <= 0;
clk_low <= '0';
elsif (rising_edge(clk50m)) then
if (scl_cnt = DIV_SCL) then
scl_cnt <= 0 after td;
clk_low <= not clk_low after td;
else
scl_cnt <= scl_cnt + 1 after td;
end if;
end if;
end process;
-- clk rising/falling
clk_z <= clk_low after td when rising_edge(clk50m);
clk_r <= (not clk_z) and clk_low after td when rising_edge(clk50m);
clk_f <= (not clk_low) and clk_z after td when rising_edge(clk50m);
pr_fsm: process(clk50m, rstn) is
begin
if (rstn = '0') then
cnt <= x"0";
clk_s <= '0';
dat_s <= '0';
dat_e <= '0';
ds_ena <= '0';
ready <= '0';
reg_iic <= x"00";
reg_in <= x"00";
data_o <= x"00";
data_vl <= '0';
STM <= RDY;
elsif (rising_edge(clk50m)) then
case (STM) is
when RDY =>
data_vl <= '0' after td;
ds_ena <= '0' after td;
dat_e <= '0' after td;
--if (ena_stwx = '1') then
if (enable = '1') then
STM <= START after td;
end if;
if (clk_r = '1') then--(clk_f = '1') then
--dat_e <= '0' after td;
--ds_ena <= '0' after td;
ready <= '1' after td;
end if;
when START =>
if (clk_r = '1') then
clk_s <= '0' after td;
reg_iic <= addr_i after td;
ready <= '0' after td;
cnt <= x"1" after td;
ds_ena <= '1' after td;
STM <= ADDR after td;
end if;
when ADDR =>
if (clk_f = '1') then
dat_s <= reg_iic(0) after td;
dat_e <= '0' after td;
--ds_ena <= '1' after td;
STM <= CLK_RISE after td;
end if;
when CLK_RISE =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_ONE after td;
end if;
when CLK_ONE =>
if (clk_f = '1') then
reg_iic <= '0' & reg_iic(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_FALL after td;
else
dat_e <= rdwr after td;
--dat_s <= '0' after td;
STM <= WAITING after td;
end if;
end if;
when CLK_FALL =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= ADDR after td;
end if;
when WAITING =>
if (clk_r = '1') then
clk_s <= '0' after td;
if (rdwr = '0') then
reg_iic <= data_i after td;
reg_in <= x"00" after td;
cnt <= x"1" after td;
STM <= WRITE after td;
else
reg_iic <= x"00" after td;
cnt <= x"1" after td;
dat_s <= '0' after td;
--dat_e <= '1' after td;
reg_in <= data_b & reg_in(7 downto 1) after td;
STM <= CLK_RD_R after td;
end if;
end if;
when WRITE =>
if (clk_f = '1') then
dat_s <= reg_iic(0) after td;
STM <= CLK_WR_R after td;
end if;
when CLK_WR_R =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_WR1 after td;
end if;
when CLK_WR1 =>
if (clk_f = '1') then
reg_iic <= '0' & reg_iic(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_WR_F after td;
else
--dat_s <= '0' after td;
dat_e <= '0' after td;
STM <= STOP after td;
end if;
end if;
when CLK_WR_F =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= WRITE after td;
end if;
when CLK_RD_R =>
if (clk_r = '1') then
clk_s <= '1' after td;
STM <= CLK_RD1 after td;
end if;
if (clk_f = '1') then
reg_in <= data_b & reg_in(7 downto 1) after td;
end if;
when CLK_RD1 =>
if (clk_f = '1') then
--reg_in <= data_b & reg_in(7 downto 1) after td;
if cnt(3) = '0' then
cnt <= cnt + '1' after td;
STM <= CLK_RD_F after td;
else
--dat_e <= '0' after td;
STM <= STOP after td;
end if;
end if;
when CLK_RD_F =>
if (clk_r = '1') then
clk_s <= '0' after td;
STM <= CLK_RD_R after td;
end if;
when STOP =>
if (clk_r = '1') then
clk_s <= '0' after td;
reg_iic <= x"00" after td;
reg_in <= x"00" after td;
data_o <= reg_in after td;
--data_vl <= '1' after td;
end if;
if (clk_f = '1') then
data_vl <= '1' after td;
dat_e <= '0' after td;
STM <= RDY after td;
end if;
when others => null;
end case;
end if;
end process;
data_v <= data_vl;
data_b <= ds_data_i;-- when dat_e = '1';
ds_data_o <= dat_s;-- when dat_e = '0' else '0';
ds_data_t <= dat_e;
ds_clk <= clk_s;
end rtl_ds1302; | mit | cea4ea6211de8a2f61451a33eeb2e987 | 0.477215 | 2.717323 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1000/config.vhd | 1 | 5,269 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | e09455edc0457e6c6da14460a727998e | 0.643006 | 3.664117 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/inpad.vhd | 1 | 5,040 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad
-- File: inpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_inpad generic map (level, voltage) port map (pad, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
dar : if (tech = dare) generate
x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
pereg : if (tech = peregrine) generate
x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
end generate;
eas : if (tech = easic90) generate
x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_inpad generic map (level, voltage) port map (pad, o);
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpadv is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := 0; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpadv is
begin
v : for i in width-1 downto 0 generate
x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i));
end generate;
end;
| gpl-2.0 | ec1bb8f70b823d0eee3cc7cd9a47c08e | 0.645437 | 3.522013 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/background/example_design/background_prod.vhd | 1 | 9,933 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: background_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : background.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 76800
-- C_READ_DEPTH_A : 76800
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 76800
-- C_READ_DEPTH_B : 76800
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY background_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END background_prod;
ARCHITECTURE xilinx OF background_prod IS
COMPONENT background_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : background_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 02dd4f685014774fe45c6c794be9f991 | 0.496124 | 3.851493 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 5 | 41,873 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
Use axi_sg_v4_1.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| gpl-3.0 | c799b48114a2548192ef1d6fab9093b4 | 0.389845 | 4.804705 | false | false | false | false |
IamVNIE/Hardware-Security | DES CryptoCore/src/DES_TOP_FILE.vhd | 2 | 6,235 | --******************************************************************************
-- Copyright (c) 2017 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
----------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: DES_TOP_FILE - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY FPGAs
-- Tool versions: ISE, Vivado
-- Description: Implements DES - Complete Structural Modelling
--
-- Dependencies: Modules :-> XP- Expansion; DESXOR1,DESXOR2 - XOR; S1..S8 - S-Boxes;
-- PP - Permutation; REG32 - 32 bit register
-- Files :-> xp.vhd,desxor1.vhd,desxor2.vhd, s1.vhd...s8.vhd,pp.vhd
-- reg32.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DES_CRYPTO_CORE is port
(
reset : in std_logic;
EN : in STD_LOGIC;
clk : in std_logic;
DES_IN: in STD_LOGIC_VECTOR (63 downto 0);
USER_KEY: in STD_LOGIC_VECTOR (63 downto 0);
DES_OUT: out STD_LOGIC_VECTOR (63 downto 0)
);
end DES_CRYPTO_CORE;
architecture behavior of DES_CRYPTO_CORE is
--Cypher Text & Key Initialization
-----------------For Encoding ------------------------------
--signal ct : std_logic_vector(1 TO 64):=x"1234567890abcdef";
--signal key : std_logic_vector(1 TO 64):=x"abbcccddddeeeeef";
---------------- For Decoding -------------------------------
signal ct : std_logic_vector(1 TO 64);
signal key : std_logic_vector(1 TO 64);
signal pt : std_logic_vector(1 TO 64);
signal pt1:STD_LOGIC_VECTOR(64 downto 0);
signal k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: std_logic_vector(1 to 48);
signal
l0xa,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x
: std_logic_vector(1 to 32);
signal
r0xa,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x
: std_logic_vector(1 to 32);
component keysched
port (
key : in std_logic_vector(1 to 64);EN,CLK: in std_logic;
k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: out std_logic_vector(1 to 48)
);
end component;
component ip
port (
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end component;
component roundfunc
port (
clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32);
k : in std_logic_vector(1 to 48);
lo,ro : out std_logic_vector(1 to 32)
);
end component;
component fp
port (
l,r : in std_logic_vector(1 to 32);
pt : out std_logic_vector(1 to 64)
);
end component;
begin
process(CLK,RESET)
begin
if reset='1' then
DES_OUT<=(OTHERS=>'0');
ct<=(OTHERS=>'0');
key<=(OTHERS=>'0');
elsif rising_edge(CLK) then
DES_OUT<=pt;
ct<=DES_IN;
key<=USER_KEY;
end if;
end process;
keyscheduling: keysched port map ( key=>key,EN=>EN, CLK=>CLK,
k1x=>k1x, k2x=>k2x, k3x=>k3x, k4x=>k4x,
k5x=>k5x, k6x=>k6x, k7x=>k7x, k8x=>k8x,
k9x=>k9x, k10x=>k10x, k11x=>k11x, k12x=>k12x,
k13x=>k13x,k14x=>k14x, k15x=>k15x, k16x=>k16x );
iperm: ip port map ( ct=>ct, l0x=>l0xa, r0x=>r0xa );
round1: roundfunc port map ( clk=>clk, reset=>reset, li=>l0xa, ri=>r0xa, k=>k1x, lo=>l1x, ro=>r1x );
round2: roundfunc port map ( clk=>clk, reset=>reset, li=>l1x, ri=>r1x, k=>k2x, lo=>l2x, ro=>r2x );
round3: roundfunc port map ( clk=>clk, reset=>reset, li=>l2x, ri=>r2x, k=>k3x, lo=>l3x, ro=>r3x );
round4: roundfunc port map ( clk=>clk, reset=>reset, li=>l3x, ri=>r3x, k=>k4x, lo=>l4x, ro=>r4x );
round5: roundfunc port map ( clk=>clk, reset=>reset, li=>l4x, ri=>r4x, k=>k5x, lo=>l5x, ro=>r5x );
round6: roundfunc port map ( clk=>clk, reset=>reset, li=>l5x, ri=>r5x, k=>k6x, lo=>l6x, ro=>r6x );
round7: roundfunc port map ( clk=>clk, reset=>reset, li=>l6x, ri=>r6x, k=>k7x, lo=>l7x, ro=>r7x );
round8: roundfunc port map ( clk=>clk, reset=>reset, li=>l7x, ri=>r7x, k=>k8x, lo=>l8x, ro=>r8x );
round9: roundfunc port map ( clk=>clk, reset=>reset, li=>l8x, ri=>r8x, k=>k9x, lo=>l9x, ro=>r9x );
round10: roundfunc port map ( clk=>clk, reset=>reset, li=>l9x, ri=>r9x, k=>k10x, lo=>l10x, ro=>r10x );
round11: roundfunc port map ( clk=>clk, reset=>reset, li=>l10x, ri=>r10x, k=>k11x, lo=>l11x, ro=>r11x );
round12: roundfunc port map ( clk=>clk, reset=>reset, li=>l11x, ri=>r11x, k=>k12x, lo=>l12x, ro=>r12x );
round13: roundfunc port map ( clk=>clk, reset=>reset, li=>l12x, ri=>r12x, k=>k13x, lo=>l13x, ro=>r13x );
round14: roundfunc port map ( clk=>clk, reset=>reset, li=>l13x, ri=>r13x, k=>k14x, lo=>l14x, ro=>r14x );
round15: roundfunc port map ( clk=>clk, reset=>reset, li=>l14x, ri=>r14x, k=>k15x, lo=>l15x, ro=>r15x );
round16: roundfunc port map ( clk=>clk, reset=>reset, li=>l15x, ri=>r15x, k=>k16x, lo=>l16x, ro=>r16x );
fperm: fp port map ( l=>r16x, r=>l16x, pt=>pt );
end behavior;
| mit | f521876c93c5fd4d22671cb15642d23a | 0.631917 | 2.654321 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_dst_rows_V_channel.vhd | 2 | 4,628 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_rows_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_rows_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_rows_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_rows_V_channel is
component FIFO_image_filter_p_dst_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_rows_V_channel_shiftReg : FIFO_image_filter_p_dst_rows_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 875fbec015c951edd60d7bc48024fbdd | 0.539326 | 3.490196 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-sdr/testbench.vhd | 1 | 9,465 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 3a98c18006425af52b2eb4ad2e4e50a4 | 0.581828 | 3.138263 | false | false | false | false |
IamVNIE/Hardware-Security | PUF Lab/Students_PUFS/puf_lab_mos283_ad3572/sw2x2.vhd | 2 | 916 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:23:39 04/24/2017
-- Design Name:
-- Module Name: sw2x2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SW2x2 is
port (
In0: in std_logic;
In1: in std_logic;
Out0: out std_logic;
Out1: out std_logic;
Sel: in std_logic);
end SW2x2;
architecture Behavioral of SW2x2 is
begin
Out0 <= In0 when Sel='0' else
In1 when Sel='1' else
'0';
Out1 <= In1 when Sel='0' else
In0 when Sel='1' else
'0';
end Behavioral;
| mit | a9d0d7014dc6a937503b52d65ba47868 | 0.466157 | 3.53668 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/scanreg.vhd | 1 | 6,980 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: scanregi, scanrego, scanregio
-- File: scanreg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Technology wrapper for boundary scan registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregi is
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregi is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregi_inf generic map (intesten) port map (pad,core,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
iten: if intesten /= 0 generate
m1 : grmux2 generic map (tech) port map (pad, q1, bsdrive, core);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
end generate;
itdis: if intesten = 0 generate
core <= pad;
q1 <= '0';
d1 <= '0';
end generate;
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, o1o, bscapt, m3i);
o1 : gror2 generic map (tech) port map (pad, bshighz, o1o);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanrego is
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic
);
end;
architecture tmap of scanrego is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanrego_inf port map (pad,core,samp,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive);
end generate;
map0: if tech /= 0 generate
m1 : grmux2 generic map (tech) port map (core, q1, bsdrive, pad);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, samp, bscapt, m3i);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregto is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregto is
signal tdo1, padoenx : std_ulogic;
begin
x1: scanrego generic map (tech)
port map (pado, coreo, samp, tck, tckn, tdo1, tdo, bsshft, bscapt, bsupdo, bsdrive);
x2: scanrego generic map (tech)
port map (padoenx, coreoen, coreoen, tck, tckn, tdi, tdo1, bsshft, bscapt, bsupdo, bsdrive);
hz : if hzsup = 1 generate
x3 : if oepol = 0 generate
x33 : gror2 generic map (tech) port map (padoenx, bshighz, padoen);
end generate;
x4 : if oepol = 1 generate
x33 : grand12 generic map (tech) port map (padoenx, bshighz, padoen);
end generate;
end generate;
nohz : if hzsup = 0 generate
padoen <= padoenx;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregio is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregio is
signal tdo1, tdo2, padoenx : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregio_inf
generic map (hzsup,intesten)
port map (pado,padoen,padi,coreo,coreoen,corei,tck,tckn,tdi,tdo,
bsshft,bscapt,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
x0: scanregi generic map (tech,intesten)
port map (padi, corei, tck, tckn, tdo1, tdo, bsshft, bscapt, bsupdi, bsdrive, bshighz);
x1: scanregto generic map (tech, hzsup, oepol)
port map (pado, padoen, coreo, coreo, coreoen,
tck, tckn, tdi, tdo1, bsshft, bscapt, bsupdo, bsdrive, bshighz);
end generate;
end;
| gpl-2.0 | e7de192ca182449e084cd586426b3f3c | 0.602006 | 3.43335 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml50x/config.vhd | 1 | 7,604 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.devices.all;
package config is
-- Board selection
constant CFG_BOARD_SELECTION : system_device_type := XILINX_ML505;
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000505#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (190);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | b607299943582c16377fad8a88963e4d | 0.652157 | 3.544988 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd | 3 | 50,534 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(31 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
attribute mark_debug of s2mm_cmnd_wr : signal is "true";
attribute mark_debug of s2mm_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
attribute mark_debug of s2mm_interr : signal is "true";
attribute mark_debug of s2mm_slverr : signal is "true";
attribute mark_debug of s2mm_decerr : signal is "true";
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
| gpl-3.0 | af9adfac078d3639a64b2eaa686ff362 | 0.400621 | 4.342155 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/iopad_ds.vhd | 1 | 4,961 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
| gpl-2.0 | e2661db678495925d0e3d0b4dea586aa | 0.62951 | 3.404942 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/eclipsee/memory_eclipse.vhd | 1 | 4,667 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_eclipse.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Quicklogic Eclipse rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- translate_off
library eclipsee;
use eclipsee.all;
-- translate_on
entity eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of eclipse_syncram_2p is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
begin
gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
a7 : if (abits <= 7) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : RAM128X18_25um port map (
a1(6 downto 0), a2(6 downto 0), di1(i*18+17 downto i*18),
write, rena, wclk, rclk, gnd(0), q2(i*18+17 downto i*18));
end generate;
end generate;
a8 : if (abits = 8) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : RAM256X9_25um port map (
a1(7 downto 0), a2(7 downto 0), di1(i*9+8 downto i*9),
write, rena, wclk, rclk, gnd(0), q2(i*9+8 downto i*9));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : RAM512X4_25um port map (
a1(8 downto 0), a2(8 downto 0), di1(i*4+3 downto i*4),
write, rena, wclk, rclk, gnd(0), q2(i*4+3 downto i*4));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : RAM1024X2_25um port map (
a1(9 downto 0), a2(9 downto 0), di1(i*2+1 downto i*2),
write, rena, wclk, rclk, gnd(0), q2(i*2+1 downto i*2));
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 10 generate
x : process
begin
assert false
report "Address depth larger than 10 is not supported for Eclipse rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-2.0 | 02575fa7e95755845a08a1dcdc65ecff | 0.606171 | 3.335954 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddrintpkg.vhd | 1 | 17,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
| gpl-2.0 | 8f805c4bc06e9d0a9c524e9da0ac324f | 0.530493 | 3.608705 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pcilib.vhd | 1 | 4,718 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib
-- File: pcilib.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
package pcilib is
constant zero : std_logic_vector(31 downto 0) := (others => '0');
constant addzero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
-- Constants for PCI commands
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
-- Constants for word size
constant W_SIZE_8_n : word4 := "1110"; -- word size active low
constant W_SIZE_16_n : word4 := "1100";
constant W_SIZE_32_n : word4 := "0000";
type pci_config_command_type is record
-- ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
ser : std_logic; -- SERR error response enable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
--type pci_config_type is record
-- conf_en : std_logic;
-- bus : std_logic_vector(7 downto 0);
-- dev : std_logic_vector(4 downto 0);
-- func : std_logic_vector(2 downto 0);
-- reg : std_logic_vector(5 downto 0);
-- data : std_logic_vector(31 downto 0);
--end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
serr : std_logic;
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
oe_serr : std_logic;
end record;
end ;
| gpl-2.0 | 586ec9768a3b20487c6a5890c60431de | 0.614879 | 3.5 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | DataMemory.vhd | 1 | 984 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DataMemory is
Port ( Rst : in STD_LOGIC;
cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WrENMem : in STD_LOGIC;
RdENMem : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (31 downto 0));
end DataMemory;
architecture Behavioral of DataMemory is
type ram is array(63 downto 0) of std_logic_vector(31 downto 0);
signal memory : ram := (others => x"00000000");
begin
process(Rst, cRd, AluResult, WrENMem, RdENMem)
begin
if(Rst = '1')then
Data <= x"00000000";
memory <= (others => x"00000000");
else
if(RdENMem = '1')then
if(WrENMem = '1')then
memory(conv_integer(AluResult(5 downto 0))) <= cRD;
end if;
Data <= memory(conv_integer(AluResult(5 downto 0)));
else
Data <= x"00000000";
end if;
end if;
end process;
end Behavioral; | mit | 272c9ad578735a6808ef0c856deefd6f | 0.632114 | 3.104101 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml501/leon3mp.vhd | 1 | 35,460 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
sysace_clk_in : in std_ulogic; -- System ACE clock
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic_vector(1 downto 0);
ddr2_cs_n : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(1 downto 0);
ddr2_we_n : out std_ulogic; -- ddr write enable
ddr2_ras_n : out std_ulogic; -- ddr ras
ddr2_cas_n : out std_ulogic; -- ddr cas
ddr2_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr2_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_dqs_n : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_a : out std_logic_vector (13 downto 0); -- ddr address
ddr2_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr2_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- txd2 : out std_ulogic; -- UART2 tx data
-- rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
-- D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML501,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr2_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr2_a(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr2_ba(1 downto 0), ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n,
ddr2_cs_n => ddr2_cs_n(CS_NUM-1 downto 0), ddr2_odt => ddr2_odt(0 downto 0),
ddr2_cke => ddr2_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr2_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr2_dqs(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr2_dqs_n(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr2_ck((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr2_ck_n((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#E00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock,
clkml, clkml, ahbsi, ahbso(0),
ddr2_ck, ddr2_ck_n, ddr_clk_fb, ddr_clk_fb, ddr2_cke, ddr2_cs_n,
ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs, ddr2_dqs_n, ddr2_a, ddr2_ba, ddr2_dq, ddr2_odt);
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML501),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | f3933dc12d3f599948b81c410b46668c | 0.57366 | 3.309071 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3mp/testbench.vhd | 1 | 19,866 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| gpl-2.0 | 1b7b243c5a5747883a3a96b4e95a6fe4 | 0.575254 | 3.041801 | false | false | false | false |
Subsets and Splits