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marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1600e/config.vhd | 1 | 6,040 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3e;
constant CFG_MEMTECH : integer := spartan3e;
constant CFG_PADTECH : integer := spartan3e;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3e;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000018#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (40);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | a5a7209b77fbbdef297ec7e87d04493c | 0.643709 | 3.616766 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/tbufmem.vhd | 1 | 2,221 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem
-- File: tbufmem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit trace buffer memory (CPU/AHB)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end;
architecture rtl of tbufmem is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
signal enable : std_logic_vector(1 downto 0);
begin
enable <= di.enable & di.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data(((i*64)+63) downto (i*64)),
do.data(((i*64)+63) downto (i*64)), enable ,di.write(i*2+1 downto i*2),
di.diag);
end generate;
end;
| gpl-2.0 | 0df27dfc6a8b3c71ca624c6125a25f65 | 0.60018 | 3.973166 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-c5ekit/memifsim.vhd | 1 | 12,367 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(3 downto 0);
mem_ras_n : out std_logic_vector(0 downto 0);
mem_cas_n : out std_logic_vector(0 downto 0);
mem_we_n : out std_logic_vector(0 downto 0);
mem_reset_n : out std_logic;
mem_dq : inout std_logic_vector(31 downto 0);
mem_dqs : inout std_logic_vector(3 downto 0);
mem_dqs_n : inout std_logic_vector(3 downto 0);
mem_odt : out std_logic_vector(0 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(127 downto 0);
avl_wdata : in std_logic_vector(127 downto 0);
avl_be : in std_logic_vector(15 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of ddr3ctrl1 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_reset_n <= '0';
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_ca : out std_logic_vector(9 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(1 downto 0);
mem_dq : inout std_logic_vector(15 downto 0);
mem_dqs : inout std_logic_vector(1 downto 0);
mem_dqs_n : inout std_logic_vector(1 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(63 downto 0);
avl_wdata : in std_logic_vector(63 downto 0);
avl_be : in std_logic_vector(7 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of lpddr2ctrl1 is
signal lafi_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_reset_n <= '0';
afi_reset_export_n <= '0';
mem_ca <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
avl_ready <= '1';
avl_rdata_valid <= '1';
avl_rdata <= (others => '0');
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
variable vclk,vhclk: std_logic := '0';
begin
lafi_clk <= vclk;
afi_half_clk <= vhclk;
wait for 4 ns;
vclk := not vclk;
if vclk='0' then vhclk:=not vhclk; end if;
end process;
rstproc: process
begin
afi_reset_n <= '0';
for x in 1 to 10 loop
wait until rising_edge(lafi_clk);
end loop;
afi_reset_n <= '1';
wait;
end process;
end;
| gpl-2.0 | 29bcd84323267e4f7a26e062a0a960fa | 0.508612 | 3.33073 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/hynix/ddr2/HY5PS121621F_PACK.vhd | 3 | 17,071 | ------------------------------------------------------
-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
-- --
-- Packages for HY5PS121621F.vhd --
-- --
-- HHHH HHHH --
-- HHHH HHHH --
-- ,O0O. ,O0 .HH ,O0 .HH --
-- (O000O)(000 )H(000 )H Hynix --
-- `O0O' `O0 'HH `O0 'HH --
-- HHHH HHHH Semiconductor --
-- HHHH HHHH --
------------------------------------------------------
---------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
---------------------------------------------------------------------------------------------------
package HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
constant NUM_OF_MROPCODE : integer := 13;
constant NUM_OF_ROW_ADD : integer := 13;
constant NUM_OF_COL_ADD : integer := 10;
constant NUM_OF_BANK_ADD : integer := 2;
constant WORD_SIZE : integer := 16;
constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD;
constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD;
constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD;
constant NUM_OF_BUFFERS : integer := 3;
type PART_NUM_TYPE is (B400, B533, B667, B800);
type PART_NUM is array (B400 to B800) of time;
constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns);
constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns);
constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns);
constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns);
constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns);
constant tRRD : time := 10 ns;
constant tREF : time := 64 ms;
constant tRFC : time := 75 ns;
constant tRTP : time := 7.5 ns;
constant tXSNR : time := tRFC + 10 ns;
constant tXP : integer := 2;
constant tCKE : integer := 3;
constant tXARD : integer := 2;
constant tXARDS : integer := 2;
constant tXSRD : integer := 200;
constant tPUS : time := 200 us;
type STATE_TYPE is (
PWRDN,
PWRUP,
SLFREF,
IDLE,
RACT,
READ,
WRITE);
type COMMAND_TYPE is (
DSEL,
NOP,
MRS,
EMRS1,
EMRS2,
EMRS3,
ACT,
RD,
RDAP,
WR,
WRAP,
PCG,
PCGA,
AREF,
SREF,
SREX,
PDEN,
PDEX,
ERROR,
ILLEGAL);
type BURST_MODE_TYPE is (
SEQUENTIAL,
INTERLEAVE);
type OCD_DRIVE_MODE_TYPE is (
CAL_EXIT,
DRIVE1,
DRIVE0,
ADJUST,
CAL_DEFAULT);
subtype CL_TYPE is integer range 0 to 6;
subtype BL_TYPE is integer range 4 to 8;
subtype TWR_TYPE is integer range 2 to 6;
type DLL_RST is (
RST,
NORST);
type MODE_REGISTER is
record
CAS_LATENCY : CL_TYPE;
BURST_MODE : BURST_MODE_TYPE;
BURST_LENGTH : BL_TYPE;
DLL_STATE : DLL_RST;
SAPD : std_logic;
TWR : TWR_TYPE;
end record;
type EMR_TYPE is
record
DLL_EN : std_logic;
AL : CL_TYPE;
QOFF : std_logic;
DQSB_ENB : std_logic;
RDQS_EN : std_logic;
OCD_PGM : OCD_DRIVE_MODE_TYPE;
end record;
type EMR2_TYPE is
record
SREF_HOT : std_logic;
end record;
type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time;
type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0);
type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0);
subtype COL_DATA_TYPE is integer range 0 to 65535;
type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type RAM_PNTR is ACCESS ROW_DATA_TYPE;
type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE;
type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR;
subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0);
type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE;
type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0);
type CKE_TYPE is array (integer range -1 to 0) of std_logic;
subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0);
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE);
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER);
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE);
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE);
function REMAINDER (
val0 : in integer;
val1 : in integer) return integer;
function XOR_FUNC (
val0 : in std_logic_vector;
val1 : in std_logic_vector) return std_logic_vector;
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic;
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT;
end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package
---------------------------------------------------------------------------------------------------
package body HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE) Is
begin
case CKE (-1) is
when '1' =>
case CKE (0) is
when '0' =>
if (BankState = "0000") then
if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then
COMMAND := SREF;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
when '1' =>
if (CSB = '1') then
COMMAND := DSEL;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
COMMAND := NOP;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then
if (A10 = '0') then
COMMAND := RD;
else
COMMAND := RDAP;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then
if (A10 = '0') then
COMMAND := WR;
else
COMMAND := WRAP;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
COMMAND := ACT;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then
if (A10 = '0') then
COMMAND := PCG;
else
COMMAND := PCGA;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
COMMAND := AREF;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
if (BankState = "0000") then
if (Bank_Add = "00") then
COMMAND := MRS;
elsif (Bank_Add = "01") then
COMMAND := EMRS1;
elsif (Bank_Add = "10") then
COMMAND := EMRS2;
elsif (Bank_Add = "11") then
COMMAND := EMRS3;
end if;
else
COMMAND := ILLEGAL;
end if;
end if;
when others =>
COMMAND := ERROR;
end case;
when '0' =>
case CKE (0) is
when '0' =>
COMMAND := NOP;
when '1' =>
if (State = PWRUP) then
COMMAND := NOP;
elsif (CSB = '1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
else
COMMAND := ERROR;
end if;
when others =>
COMMAND := ERROR;
end case;
when others =>
COMMAND := ERROR;
end case;
end COMMAND_DECODE;
------------------------------------------------------------------------------------------------
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER) is
begin
if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 2;
elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 3;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 4;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 5;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(3) = '0' then
MR.BURST_MODE := SEQUENTIAL;
elsif MROPCODE(3) = '1' then
MR.BURST_MODE := INTERLEAVE;
end if;
if MROPCODE(8) = '0' then
MR.DLL_STATE := NORST;
elsif MROPCODE(8) = '1' then
MR.DLL_STATE := RST;
end if;
if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then
MR.BURST_LENGTH := 4;
elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then
MR.BURST_LENGTH := 8;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!"
severity ERROR;
end if;
if MROPCODE(12) = '0' then
MR.SAPD := '0';
elsif MROPCODE(12) = '1' then
MR.SAPD := '1';
end if;
if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 2;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then
MR.TWR := 3;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then
MR.TWR := 4;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then
MR.TWR := 5;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!"
severity ERROR;
end if;
end MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE) is
begin
if (MROPCODE(0) = '0') then
EMR.DLL_EN := '1';
elsif (MROPCODE(0) = '1') then
EMR.DLL_EN := '0';
end if;
if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 0;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 1;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then
EMR.AL := 2;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then
EMR.AL := 3;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 4;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 5;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(12) = '0' then
EMR.QOFF := '0';
elsif MROPCODE(12) = '1' then
EMR.QOFF := '1';
end if;
if MROPCODE(10) = '0' then
EMR.DQSB_ENB := '0';
elsif MROPCODE(10) = '1' then
EMR.DQSB_ENB := '1';
end if;
if MROPCODE(11) = '0' then
EMR.RDQS_EN := '0';
elsif MROPCODE(11) = '1' then
EMR.RDQS_EN := '1';
end if;
if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := CAL_EXIT;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then
EMR.OCD_PGM := DRIVE1;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then
EMR.OCD_PGM := DRIVE0;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := ADJUST;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then
EMR.OCD_PGM := CAL_DEFAULT;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!"
severity ERROR;
end if;
end EXT_MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE) is
begin
if (MROPCODE(7) = '0') then
EMR.SREF_HOT := '0';
elsif (MROPCODE(7) = '1') then
EMR.SREF_HOT := '1';
end if;
end EXT_MODE_REGISTER_SET2;
------------------------------------------------------------------------------------------------
function REMAINDER (val0 : in integer; val1 : in integer) return integer is
variable Result : integer;
begin
Result := val0;
loop
exit when Result < val1;
Result := Result - val1;
end loop;
return Result;
end REMAINDER;
------------------------------------------------------------------------------------------------
function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is
variable Result : std_logic_vector(2 downto 0);
variable j : integer := 0;
begin
for i in val0'RANGE LOOP
if (val0(i) /= val1(i)) then
Result(i) := '1';
else
Result(i) := '0';
end if;
j := j + 1;
end loop;
return Result((j - 1) downto 0);
end XOR_FUNC;
------------------------------------------------------------------------------------------------
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic is
variable r : std_logic;
begin
case c is
when '0' => r := '0';
when 'L' => r := 'L';
when '1' => r := '1';
when 'H' => r := 'H';
when 'W' => r := 'W';
when 'Z' => r := 'Z';
when 'U' => r := 'U';
when '-' => r := '-';
when others => r := 'X';
end case;
return r;
end CHAR_TO_STD_LOGIC;
------------------------------------------------------------------------------------------------
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is
variable Result: BIT;
begin
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' | 'Z' | 'U' | '-' =>
Result := '0';
end case;
return Result;
end STD_LOGIC_TO_BIT;
------------------------------------------------------------------------------------------------
end HY5PS121621F_PACK;
| gpl-2.0 | 138eca33ee86695e85a1e489d7a18d85 | 0.47402 | 3.39789 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahbtrace.vhd | 1 | 2,278 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtrace is
begin
ahbt0 : ahbtrace_mb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
ahbfilt => ahbfilt)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmi => ahbmi,
tahbsi => ahbsi);
end;
| gpl-2.0 | 6e61c17c4f52932fb8e0ccd989e77b2f | 0.575505 | 4.017637 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/buffer_unisim.vhd | 1 | 2,757 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-2.0 | d2d54c9febd1b3ec4ac322915e6c5d79 | 0.620239 | 3.75102 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/gr1553b/simtrans1553.vhd | 1 | 3,690 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: simtrans1553
-- File: simtrans1553.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: 1553 Transceiver simulation model
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end;
architecture b of simtrans1553_single is
signal bw_rxd, bw_txd: wire1553;
begin
bw_rxd <= transport buswire after rxdelay;
buswire <= bw_txd after txdelay;
rxpr: process(bw_rxd,rxen)
variable p,n: std_ulogic;
begin
p:='U'; n:='U';
case rxen is
when '0' => p:='0'; n:='0';
when '1' =>
case bw_rxd is
when 'U' => null;
when 'X' => p := 'X'; n := 'X';
when '0' => p := '0'; n := '0';
when '+' => p := '1'; n := '0';
when '-' => p := '0'; n := '1';
end case;
when 'X' => p:='X'; n:='X';
when others => null;
end case;
rxP <= p;
rxN <= n;
end process;
txpr: process(txin, txP, txN)
variable w: wire1553;
begin
w := 'U';
if txin='1' or (txP='0' and txN='0') or (txP='1' and txN='1') then
w := '0';
elsif txin='0' and txP='1' and txN='0' then
w := '+';
elsif txin='0' and txP='0' and txN='1' then
w := '-';
elsif txin='X' or txP='X' or txN='X' then
w := 'X';
elsif txin='U' or (txP='U' and txN='U') then
w := 'U';
else
w := 'X';
end if;
bw_txd <= w;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end;
architecture s of simtrans1553 is
begin
at: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busA,rxenA,txinA,txAP,txAN,rxAP,rxAN);
bt: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busB,rxenB,txinB,txBP,txBN,rxBP,rxBN);
end;
| gpl-2.0 | 5592a9d1493f2217edde1d134690819c | 0.561789 | 3.419833 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/clkgen_unisim.vhd | 1 | 18,422 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
--use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
-- component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
constant FREQ_MHZ : integer := freq/1000;
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
-- x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
--pragma translate_off
assert false report "PCIDLL = 1 currently not supported for virtex5_clkgen"
severity failure;
--pragma translate_on
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
-- HMODE_dll0 : if (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
-- dll0 : DCM
-- generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
-- CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
-- LMODE_dll0 : if not (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
clk2xgen : if (CLK2XEN /= 0) generate
-- HMODE_dll2x : if ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
-- dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
-- CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
-- LMODE_dll2x : if not ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
-- HMODE_dll1 : if ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
-- dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
-- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
-- port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
-- LOCKED => dll1lock);
-- end generate;
-- LMODE_dll1 : if not ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
-- end generate;
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex7 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use UNISIM.vcomponents.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex7 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 200000 -- clock frequency in KHz
);
port (
clkin : in std_ulogic;
clk : out std_ulogic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_virtex7 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
constant VERSION : integer := 1;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal int_rst : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
int_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => cgo.clklock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clkin,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => int_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
cgo.pcilock <= '0';
bufgclk0 : BUFG port map (I => clk_nobuf, O => clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => clk90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => clkio);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex7" & ": virtex-7 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex7" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-2.0 | 84aad10c54f1dfb16576f3f05baba44a | 0.56438 | 3.417177 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd | 3 | 30,514 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
| gpl-3.0 | 9f9ea00202212e89b3e97678d602f678 | 0.403356 | 4.911315 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_afifo_autord.vhd | 3 | 17,911 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 | 22208a35fc5ccb8783b5d129aa75dbc2 | 0.475853 | 4.081814 | false | false | false | false |
Yuriu5/MiniBlaze | src/hw1/Sequencer.vhd | 1 | 29,275 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : Sequencer
-- Date : 07/25/2016
--
-- Description : Sequencer of the core. Fetch, decode, execute and store.
-- This implementation (v1) does not aim to be fast. There is
-- no pipeline, memory access are slow. The goal is to have
-- a functionnal core that can be played with.
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/25/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/25/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ALU_pkg.all;
use work.spec_reg_pkg.all;
entity sequencer is
generic(
D_WIDTH : natural := 32
);
port(
-- Clock and reset
clk : in std_logic;
reset_n : in std_logic;
-- Interface memory in
data_mem_in_i : in std_logic_vector(D_WIDTH-1 downto 0);
data_mem_in_en_i : in std_logic;
addr_mem_in_o : out std_logic_vector(D_WIDTH-1 downto 0);
rd_en_mem_in_o : out std_logic;
-- Interface memory out
addr_mem_out_o : out std_logic_vector(D_WIDTH-1 downto 0);
data_mem_out_o : out std_logic_vector(D_WIDTH-1 downto 0);
wr_en_mem_out_o : out std_logic_vector(3 downto 0)
);
end sequencer;
architecture rtl of sequencer is
-- Components declaration
component ALU is
generic(
DATA_WIDTH : natural := D_WIDTH
);
port(
param_i : in t_param_alu;
carry_i : in std_logic;
operandA_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandB_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandD_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
status_o : out t_status_alu_out
);
end component;
-- Signals declaration
type fsm_seq is (st_fetch, st_decode, st_execute);
signal r_fsm_seq : fsm_seq := st_fetch;
signal r_last_state : fsm_seq;
-- Special purpose registers
signal r_ProgramCounter : unsigned(D_WIDTH-1 downto 0) := (others => '0');
signal r_LastProgramCounter : unsigned(D_WIDTH-1 downto 0) := (others => '0');
signal r_MSR : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal r_imm : std_logic_vector(D_WIDTH/2-1 downto 0) := (others => '0');
-- General purpose registers
type vect_32x32b is array (0 to 31) of std_logic_vector(D_WIDTH-1 downto 0);
signal v_GeneralReg : vect_32x32b := (others => (others => '0'));
-- Mem in
signal r_addr_mem_in : unsigned(D_WIDTH-1 downto 0) := (others => '0');
signal r_rd_en_mem_in : std_logic := '0';
signal s_instruction : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal r_instruction : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
-- Mem out
signal r_wr_en_mem_out : std_logic_vector(3 downto 0) := (others => '0');
signal r_addr_mem_out : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal r_data_mem_out : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
-- ALU
signal r_input_alu_A : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal r_input_alu_B : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal s_input_alu_B : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal r_param_alu : t_param_alu := c_param_alu_null;
signal s_carry_alu_in : std_logic := '0';
signal s_output_alu : std_logic_vector(D_WIDTH-1 downto 0) := (others => '0');
signal s_status_alu : t_status_alu_out := c_status_alu_out_null;
-- Sequencer
signal r_wr_carry_output : std_logic := '0';
signal r_allow_next_instruction : std_logic := '0';
signal r_isInstructionBranchDelay : std_logic := '0';
signal r_last_op_was_imm : std_logic := '0';
signal r_is_imm_instruction : std_logic := '0';
signal r_is_branch_cond : std_logic := '0';
signal r_is_branch_uncond : std_logic := '0';
signal r_is_load_instruction : std_logic := '0';
signal r_is_store_instruction : std_logic := '0';
signal r_load_store_exclusive : std_logic := '0';
signal r_rD_address : std_logic_vector(4 downto 0) := (others => '0');
signal r_return_from_subroutine : std_logic := '0';
signal r_branch_op : std_logic_vector(3 downto 0) := (others => '0');
signal r_op_load_store : std_logic_vector(1 downto 0) := (others => '0');
signal r_step_load : unsigned(1 downto 0) := (others => '0');
signal r_step_fetch : std_logic := '0';
type fsm_fetch is (st_set_address, st_wait_data);
signal r_fsm_fetch : fsm_fetch := st_set_address;
signal r_fsm_load : fsm_fetch := st_set_address;
begin
s_instruction <= data_mem_in_i;
p_seq : process(clk)
variable v_instruction_6_5 : std_logic_vector(1 downto 0);
variable v_addr_mem_in_1_0 : unsigned(1 downto 0);
variable v_output_alu_1_0 : std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if reset_n = '0' then
r_fsm_seq <= st_fetch;
r_last_state <= st_fetch;
r_ProgramCounter <= (others => '0');
r_LastProgramCounter <= (others => '0');
r_fsm_fetch <= st_set_address;
r_fsm_load <= st_set_address;
else
-- Default values
r_rd_en_mem_in <= '0';
r_wr_en_mem_out <= (others => '0');
r_last_state <= r_fsm_seq;
case r_fsm_seq is
when st_fetch =>
-- Fetch instruction
case r_fsm_fetch is
when st_set_address =>
if r_isInstructionBranchDelay = '1' then
r_addr_mem_in <= r_LastProgramCounter + 4;
else
r_addr_mem_in <= r_ProgramCounter;
end if;
r_rd_en_mem_in <= '1';
r_fsm_fetch <= st_wait_data;
when st_wait_data =>
if data_mem_in_en_i = '1' then
r_fsm_seq <= st_decode;
r_instruction <= s_instruction;
r_fsm_fetch <= st_set_address;
end if;
when others =>
r_fsm_fetch <= st_set_address;
end case;
when st_decode =>
report " ---- ";
report integer'image(to_integer(r_ProgramCounter));
--default value
r_input_alu_A <= v_GeneralReg(to_integer(unsigned(r_instruction(20 downto 16))));
r_param_alu.ctrl_op.whichCarry <= CARRY_INPUT;
r_param_alu.ctrl_op.ctrlShift <= LEFT_SHIFT;
r_param_alu.ctrl_op.negOperandA <= '0';
r_param_alu.ctrl_op.negOperandB <= '0';
r_param_alu.ctrl_op.multType <= LSW;
r_wr_carry_output <= '0';
r_allow_next_instruction <= '0';
r_is_branch_cond <= '0';
r_is_branch_uncond <= '0';
r_is_load_instruction <= '0';
r_is_store_instruction <= '0';
r_load_store_exclusive <= '0';
r_return_from_subroutine <= '0';
r_is_imm_instruction <= '0';
r_fsm_load <= st_set_address;
-- Next stage
r_fsm_seq <= st_execute;
-- Type A / Type B instruction
if r_instruction(29) = '0' then -- rB
r_input_alu_B <= v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11))));
else -- imm
r_input_alu_B <= std_logic_vector(resize(unsigned(r_instruction(15 downto 0)), D_WIDTH));
end if;
-- Store rD address
r_rD_address <= r_instruction(25 downto 21);
-- add, addc, addk, addkc, addi, addic, addik, addikc
-- rsub, rsubi
if (r_instruction(31 downto 30) = "00") then
r_param_alu.operation <= OP_ADD;
if r_instruction(27) = '1' then -- C Bit
r_param_alu.ctrl_op.whichCarry <= CARRY_INPUT;
else
if r_instruction(26) = '1' then -- sub
r_param_alu.ctrl_op.whichCarry <= CARRY_ONE;
else -- add
r_param_alu.ctrl_op.whichCarry <= CARRY_ZERO;
end if;
end if;
if r_instruction(26) = '1' then -- Substrate bit
r_param_alu.ctrl_op.negOperandA <= '1';
end if;
r_wr_carry_output <= not r_instruction(28);
-- and, andi
elsif r_instruction(31 downto 30) = "10" and r_instruction(28 downto 26) = "001" then
r_param_alu.operation <= OP_AND;
-- andn, andni
elsif r_instruction(31 downto 30) = "10" and r_instruction(28 downto 26) = "011" then
r_param_alu.operation <= OP_AND;
r_param_alu.ctrl_op.negOperandB <= r_instruction(27);
-- or, ori
elsif r_instruction(31 downto 30) = "10" and r_instruction(28 downto 26) = "000" then
r_param_alu.operation <= OP_OR;
-- xor, xori
elsif r_instruction(31 downto 30) = "10" and r_instruction(28 downto 26) = "010" then
r_param_alu.operation <= OP_XOR;
-- conditional branch instructions
elsif (r_instruction(31 downto 30) = "10") and (r_instruction(28 downto 26) = "111") then
-- D bit, allow following instruction to complete exection
r_allow_next_instruction <= r_instruction(25);
r_is_branch_cond <= '1';
r_branch_op <= r_instruction(24 downto 21);
r_param_alu.operation <= OP_PTA;
-- unconditional branch instructions
elsif (r_instruction(31 downto 30) = "10") and (r_instruction(28 downto 26) = "110") then
r_allow_next_instruction <= r_instruction(20);
r_is_branch_uncond <= '1';
r_branch_op <= r_instruction(19 downto 16);
r_param_alu.operation <= OP_PTB;
-- Barrel Shift : bsrl, bsra, bsll
elsif (r_instruction(31 downto 30) = "01") and (r_instruction(28 downto 26) = "001") then
r_param_alu.operation <= OP_BS;
if r_instruction(10) = '1' then -- bit S (Side bit)
r_param_alu.ctrl_op.ctrlShift <= LEFT_SHIFT;
else
if r_instruction(9) = '1' then -- bit T (Type bit)
r_param_alu.ctrl_op.ctrlShift <= RIGHT_SHIFT_ARITH;
else
r_param_alu.ctrl_op.ctrlShift <= RIGHT_SHIFT_LOGIC;
end if;
end if;
-- Integer Compare : cmp, cmpu
elsif r_instruction(31 downto 26) = "000101" then
r_param_alu.operation <= OP_ADD;
r_param_alu.ctrl_op.whichCarry <= CARRY_ONE;
r_param_alu.ctrl_op.negOperandA <= '1';
-- Immediate : imm
elsif r_instruction(31 downto 26) = "101100" then
r_is_imm_instruction <= '1';
r_param_alu.operation <= OP_PTB;
-- Load/Store instruction
elsif r_instruction(31 downto 30) = "11" then
r_is_load_instruction <= not r_instruction(28);
r_is_store_instruction <= r_instruction(28);
r_op_load_store <= r_instruction(27 downto 26);
r_param_alu.operation <= OP_ADD;
r_param_alu.ctrl_op.whichCarry <= CARRY_ZERO;
if r_instruction(10) = '1' and r_instruction(29) = '0' then
r_load_store_exclusive <= '1';
end if;
-- Multipy instruction : only mul, muli (C_USE_HW_MUL = '1')
elsif r_instruction(31 downto 30) = "01" and r_instruction(28 downto 26) = "000" then
r_param_alu.operation <= OP_MULT;
-- Return from Subroutine
elsif (r_instruction(31 downto 25) = "1011011") then
r_allow_next_instruction <= '1';
r_param_alu.operation <= OP_ADD;
r_param_alu.ctrl_op.whichCarry <= CARRY_ZERO;
r_return_from_subroutine <= '1';
-- Sign Extend Halfword / Byte and Shift
elsif (r_instruction(31 downto 26) = "100100") then
if r_instruction(0) = '1' then
v_instruction_6_5 := r_instruction(6 downto 5);
case v_instruction_6_5 is
-- SRA
when "00" => r_param_alu.operation <= OP_SHIFT;
r_param_alu.ctrl_op.whichCarry <= CARRY_ARITH;
-- SRC
when "01" => r_param_alu.operation <= OP_SHIFT;
r_param_alu.ctrl_op.whichCarry <= CARRY_INPUT;
r_wr_carry_output <= '1';
-- SRL
when "10" => r_param_alu.operation <= OP_SHIFT;
r_param_alu.ctrl_op.whichCarry <= CARRY_ZERO;
r_wr_carry_output <= '1';
-- SEXT16
when others => r_param_alu.operation <= OP_SEXT16;
r_param_alu.ctrl_op.whichCarry <= CARRY_ZERO;
end case;
else
r_param_alu.operation <= OP_SEXT8;
end if;
end if;
when st_execute =>
-- Go to fecth step unless we wait for a memory access
r_fsm_seq <= st_fetch;
r_isInstructionBranchDelay <= '0';
r_last_op_was_imm <= '0';
-- Increment r_ProgramCounter of 4 to fetch the next instruction
-- Overwrite the value after if a branch is requested
if(r_last_state /= st_execute and r_isInstructionBranchDelay = '0') then
r_ProgramCounter <= r_ProgramCounter + 4;
end if;
-- Store ALU output
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= s_output_alu;
-- Change MSR carry bit if needed
if r_wr_carry_output = '1' then
r_MSR(MSR_C) <= s_status_alu.carry;
end if;
-- Branch execution cond
if r_is_branch_cond = '1' then
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
if r_branch_op = "0000" and s_status_alu.zero = '1' then -- Branch if Equal
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
elsif r_branch_op = "0101" and ((s_status_alu.negative = '0') or (s_status_alu.zero = '1')) then -- Branch if Greater or Equal
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
elsif r_branch_op = "0100" and s_status_alu.negative = '0' then -- Branch if Greater Than
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
elsif r_branch_op = "0011" and ((s_status_alu.negative = '1') or (s_status_alu.zero = '1')) then -- Branch if Less or Equal
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
elsif r_branch_op = "0010" and s_status_alu.negative = '1' then -- Branch if Less Than
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
elsif r_branch_op = "0001" and s_status_alu.zero = '0' then -- Branch if Not Equal
r_ProgramCounter <= r_ProgramCounter + unsigned(v_GeneralReg(to_integer(unsigned(r_instruction(15 downto 11)))));
end if;
if r_allow_next_instruction = '1' then
r_isInstructionBranchDelay <= '1';
r_LastProgramCounter <= r_ProgramCounter;
end if;
-- Return from subroutine
elsif r_return_from_subroutine = '1' then
r_ProgramCounter <= unsigned(s_output_alu);
-- Branch execution uncond
elsif r_is_branch_uncond = '1' then
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
if r_branch_op(2) = '1' then -- L bit
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= std_logic_vector(r_ProgramCounter);
end if;
if r_branch_op(3) = '1' then -- A bit
r_ProgramCounter <= unsigned(s_output_alu);
else
r_ProgramCounter <= r_ProgramCounter + unsigned(s_output_alu);
end if;
if r_allow_next_instruction = '1' then
r_isInstructionBranchDelay <= '1';
r_LastProgramCounter <= r_ProgramCounter;
end if;
-- Note : Load & Write this way only works for one cycle access memory
-- Load execution
elsif r_is_load_instruction = '1' then
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
r_fsm_seq <= st_execute;
case r_fsm_load is
when st_set_address =>
r_addr_mem_in <= unsigned(s_output_alu);
r_rd_en_mem_in <= '1';
r_fsm_load <= st_wait_data;
when st_wait_data =>
if data_mem_in_en_i = '1' then
r_fsm_seq <= st_fetch;
if r_op_load_store = "00" then
v_addr_mem_in_1_0 := r_addr_mem_in(1 downto 0);
case v_addr_mem_in_1_0 is
when "00" =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"000000" & data_mem_in_i(7 downto 0);
when "01" =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"000000" & data_mem_in_i(15 downto 8);
when "10" =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"000000" & data_mem_in_i(23 downto 16);
when others =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"000000" & data_mem_in_i(31 downto 24);
end case;
elsif r_op_load_store = "01" then
v_addr_mem_in_1_0 := r_addr_mem_in(1 downto 0);
case v_addr_mem_in_1_0 is
when "00" =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"0000" & data_mem_in_i(15 downto 0);
when "10" =>
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= x"0000" & data_mem_in_i(31 downto 16);
when others =>
assert false report "Address non-aligned on 16b access" severity error;
end case;
elsif r_op_load_store = "10" then
if r_addr_mem_in(1 downto 0) = "00" then
v_GeneralReg(to_integer(unsigned(r_rD_address)))(31 downto 0) <= data_mem_in_i(31 downto 0);
else
assert false report "Address non-aligned on 32b access" severity error;
end if;
if r_load_store_exclusive = '1' then
r_MSR(MSR_C) <= '0';
end if;
end if;
end if;
when others =>
r_fsm_load <= st_set_address;
end case;
-- Store execution
elsif r_is_store_instruction = '1' then
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
r_addr_mem_out <= s_output_alu;
if r_op_load_store = "00" then
r_wr_en_mem_out(to_integer(unsigned(s_output_alu(1 downto 0)))) <= '1'; -- others are at '0'
v_output_alu_1_0 := s_output_alu(1 downto 0);
case v_output_alu_1_0 is
when "00" =>
r_data_mem_out(7 downto 0) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(7 downto 0);
when "01" =>
r_data_mem_out(15 downto 8) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(7 downto 0);
when "10" =>
r_data_mem_out(23 downto 16) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(7 downto 0);
when others =>
r_data_mem_out(31 downto 24) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(7 downto 0);
end case;
elsif r_op_load_store = "01" then
if s_output_alu(1) = '0' then
r_wr_en_mem_out <= "0011";
else
r_wr_en_mem_out <= "1100";
end if;
v_output_alu_1_0 := s_output_alu(1 downto 0);
case v_output_alu_1_0 is
when "00" =>
r_data_mem_out(15 downto 0) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(15 downto 0);
when others =>
r_data_mem_out(31 downto 16) <= v_GeneralReg(to_integer(unsigned(r_rD_address)))(15 downto 0);
end case;
elsif r_op_load_store = "10" then
r_wr_en_mem_out <= "1111";
r_data_mem_out <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
if r_load_store_exclusive = '1' then
r_MSR(MSR_C) <= '0';
end if;
end if;
elsif r_is_imm_instruction = '1' then
v_GeneralReg(to_integer(unsigned(r_rD_address))) <= v_GeneralReg(to_integer(unsigned(r_rD_address)));
r_imm <= s_output_alu(15 downto 0);
r_last_op_was_imm <= '1';
end if;
end case;
end if;
end if;
end process;
-- Type B instruction, ALU input B depends of the precedent instruction
s_input_alu_B <= r_input_alu_B when r_last_op_was_imm = '0' else (r_imm & r_input_alu_B(15 downto 0));
-- Carry input of the ALU depends of the bit C of the MSR
s_carry_alu_in <= r_MSR(MSR_C);
-- ALU
i_ALU : ALU
generic map(
DATA_WIDTH => D_WIDTH
)
port map(
param_i => r_param_alu,
carry_i => s_carry_alu_in,
operandA_i => r_input_alu_A,
operandB_i => s_input_alu_B,
operandD_o => s_output_alu,
status_o => s_status_alu
);
-- ===============================
-- Mapping output
-- ===============================
addr_mem_in_o <= std_logic_vector(r_addr_mem_in);
rd_en_mem_in_o <= r_rd_en_mem_in;
addr_mem_out_o <= r_addr_mem_out;
data_mem_out_o <= r_data_mem_out;
wr_en_mem_out_o <= r_wr_en_mem_out;
end rtl;
| mit | ce0cac8770c3f29c474c5a8523ed4fcf | 0.439522 | 4.172011 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_0_cols_V_channel.vhd | 4 | 4,628 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_cols_V_channel is
component FIFO_image_filter_img_0_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_cols_V_channel_shiftReg : FIFO_image_filter_img_0_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 0cff247708909cf76ad3ff91aad77838 | 0.539326 | 3.490196 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_lite_if.vhd | 3 | 61,552 | -------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
library lib_cdc_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
| gpl-3.0 | a49b7840501260aa0af25dbe2a11f8f6 | 0.426306 | 4.126575 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/leon3mp.vhd | 1 | 35,477 | -----------------------------------------------------------------------------
-- LEON3 Xilinx SP605 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.ODDR2;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.pcie.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk27 : in std_ulogic; -- 27 MHz clock
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
clk33 : in std_ulogic; -- 32 MHz clock from sysace
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_reset_n : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqs_n : inout std_logic_vector (1 downto 0); -- ddr dqs_n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
button : inout std_logic_vector(3 downto 0); -- I/O port
switch : inout std_logic_vector(3 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_mii_int_n : in std_ulogic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
--pcie
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
--attribute syn_netlist_hierarchy : boolean;
--attribute syn_netlist_hierarchy of rtl : architecture is false;
component ODDR2
generic (
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 33000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_GRACECTRL;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
signal video_clk : std_ulogic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
ethclk <= lclk;
clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open);
reset_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= button(3);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp605 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 4, paddr => 4,
vgamst => CFG_SVGA_ENABLE, vgaburst => 64)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_reset_n=> ddr_reset_n,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n=> ddr_dqs_n(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqs_n(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_p => clk200p,
clk_mem_n => clk200n,
clk_125 => egtx_clk,
clk_50 => video_clk
);
end generate;
led(2) <= calib_done;
led(3) <= lock;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP:pcie_master_target_sp605
generic map (
master => CFG_PCIE_SIM_MAS,
hmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
hslvndx => 7,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG)
);
end generate;
----------------------------------------------------------------------
-----------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf_dma : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
dapbndx => 7, dapbaddr => 7,dapbmask => 16#FFF#, dapbirq => 4, blength => 12,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
slvndx => 7, apbndx => 5, apbaddr => 5, apbmask =>16#FFF#, haddr => 16#A00#, hmask => 16#FFF#,
nsync => 2, pcie_bar_mask => 16#FFE#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(7),
dahbmo =>ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG),
apbi =>apbi,
apbo =>apbo(5),
ahbmi =>ahbmi,
ahbsi =>ahbsi,
ahbso =>ahbso(7)
);
end generate;
pcie_mf: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_sp605
generic map (
memtech => memtech,
hslvndx => 7,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#A00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#)
port map(
rst => rstn,
clk => clkm,
-- System In
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Expre
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 5, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(16);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 8, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT, mode => 2)
port map (rstn, clkm, lclk, ahbsi, ahbso(8), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 8)
port map (sysace_d, aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
-- b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 6 generate
pio_pad : iopad generic map (tech => padtech)
port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
negtx_clk <= not egtx_clk;
x0 : ODDR2 port map ( Q => phy_gtx_clk, C0 => egtx_clk,
C1 => negtx_clk, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14),
ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_mii_int_n, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx SP605 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | b2967103dc4375399875203242fe750e | 0.548496 | 3.498373 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_dst_data_stream_2_V.vhd | 2 | 4,629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_data_stream_2_V is
component FIFO_image_filter_p_dst_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_data_stream_2_V_shiftReg : FIFO_image_filter_p_dst_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | ca92a440104dd9b08a2d0a544f2277b9 | 0.537697 | 3.449329 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/srl_fifo.vhd | 6 | 11,823 | -------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v4_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
| gpl-3.0 | ba29c0ebc30e926b5a221414e80d0cf0 | 0.438806 | 4.375648 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_sm.vhd | 4 | 47,863 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
signal fetch_tag : std_logic_vector(3 downto 0) := (others => '0');
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
signal ch2_pause_fetch1 : std_logic := '0';
signal ch2_pause_fetch2 : std_logic := '0';
signal ch2_pause_fetch3 : std_logic := '0';
signal ch2_updt_done1 : std_logic := '0';
signal ch2_updt_done2 : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
attribute mark_debug of ch1_active_i : signal is "true";
attribute mark_debug of ch2_active_i : signal is "true";
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
attribute mark_debug of ch1_stale_descriptor : signal is "true";
attribute mark_debug of ch2_stale_descriptor : signal is "true";
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
ftch_ns <= IDLE;
-- coverage on
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
ch2_pause_fetch1 <= ch2_pause_fetch;
ch2_pause_fetch2 <= ch2_pause_fetch1;
ch2_pause_fetch3 <= ch2_pause_fetch2;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
MCDMA : if (C_ENABLE_MULTI_CHANNEL = 1) generate
NOQUEUE : if (C_SG_FTCH_DESC2QUEUE = 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch3 = '0' -- No fetch pause
else '0';
end generate NOQUEUE;
QUEUE : if (C_SG_FTCH_DESC2QUEUE /= 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
end generate QUEUE;
end generate MCDMA;
NO_MCDMA : if (C_ENABLE_MULTI_CHANNEL = 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
end generate NO_MCDMA;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
fetch_tag <= "0001" when ch1_active_i = '1'
else "0000";
-- When command by sm, drive command to ftch_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ftch_cmnd_wr <= '0';
-- ftch_cmnd_data <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
-- ftch_cmnd_wr <= '1';
-- ftch_cmnd_data <= FETCH_CMD_RSVD
-- & fetch_tag
-- & fetch_cmd_addr
-- & FETCH_MSB_IGNORED
-- & FETCH_CMD_TYPE
-- & FETCH_LSB_IGNORED
-- & fetch_cmd_btt;
-- else
-- ftch_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
ftch_cmnd_wr <= write_cmnd_cmb;
ftch_cmnd_data <= FETCH_CMD_RSVD
& fetch_tag
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= fetch_cmd_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
ftch_error_addr (5 downto 0) <= "000000";
end implementation;
| gpl-3.0 | b55ba81ac6a6813173f6ca17fd630a17 | 0.425652 | 4.418259 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc6s/config.vhd | 1 | 9,158 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 1;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 8bc0f6dcefa0c908858f33a164a816c7 | 0.65451 | 3.560653 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/example_design/road_prod.vhd | 1 | 9,891 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: road_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : road.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 99200
-- C_READ_DEPTH_A : 99200
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 99200
-- C_READ_DEPTH_B : 99200
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY road_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END road_prod;
ARCHITECTURE xilinx OF road_prod IS
COMPONENT road_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : road_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 13a290a1984d223526d26f30b16742b5 | 0.493984 | 3.818919 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/amba/amba.vhd | 1 | 44,534 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: amba
-- File: amba.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified by: Jan Andersson, Aeroflex Gaisler
-- Description: AMBA 2.0 bus signal definitions + support for plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
package amba is
-------------------------------------------------------------------------------
-- AMBA configuration
-------------------------------------------------------------------------------
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant AHBDW : integer := CFG_AHBDW;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CORE_ACDM : integer := CFG_AHB_ACDM;
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
-- Number of test vector bits
constant NTESTINBITS : integer := 4+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
-------------------------------------------------------------------------------
-- AMBA interface type declarations and constant
-------------------------------------------------------------------------------
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- split completion
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_mst_in_vector_type is array (natural range <>) of ahb_mst_in_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
type ahb_slv_in_vector_type is array (natural range <>) of ahb_slv_in_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zahbdw : std_logic_vector(AHBDW-1 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant ztestin : std_logic_vector(NTESTINBITS-1 downto 0) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zahbdw, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_in_none : ahb_mst_in_type := ((others => '0'), '0', (others => '0'),
zahbdw, zxirq(NAHBIRQ-1 downto 0), '0', '0', '0', '0', ztestin);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zahbdw, zx(NAHBMST-1 downto 0), zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zahbdw,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0', ztestin);
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
constant apb_slv_in_none : apb_slv_in_type := ((others => '0'), '0', (others => '0'),
'0', (others => '0'), (others => '0'),
'0', '0', '0', '0', ztestin);
-------------------------------------------------------------------------------
-- Subprograms
-------------------------------------------------------------------------------
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic;
function ahb_membar_size (addrmask : ahb_addr_type) return integer;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer;
function ahbdrivedata (hdata : std_logic_vector) return std_logic_vector;
function ahbselectdata (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0));
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0));
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic);
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic);
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic);
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahbctrl
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- print config to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0;
fourgslv : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end component;
component apbctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2; -- print config to console
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end component;
component ahbctrl_mb
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
busndx : integer range 0 to 3 := 0;
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersect
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0 --AMBA compliant data muxing (for hsize > word)
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_bus_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_bus_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end component;
component ahbdefmst
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end component;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(AHBDW-1 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(2 downto 0);
end record;
type ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 1;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-- pragma translate_off
component ahbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
err : out std_ulogic);
end component;
component apbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
pslvdisable : integer := 0;
napb : integer range 0 to NAPBSLV := NAPBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
component ambamon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
pslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
napb : integer range 0 to NAPBSLV := NAPBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
subtype vendor_description is string(1 to 24);
subtype device_description is string(1 to 31);
type device_table_type is array (0 to 1023) of device_description;
type vendor_library_type is record
vendorid : amba_vendor_type;
vendordesc : vendor_description;
device_table : device_table_type;
end record;
type device_array is array (0 to 255) of vendor_library_type;
-- pragma translate_on
end;
package body amba is
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
case cfgver is
when 0 =>
cfg(31 downto 24) := std_logic_vector(to_unsigned(vendor, 8));
cfg(23 downto 12) := std_logic_vector(to_unsigned(device, 12));
cfg(11 downto 10) := std_logic_vector(to_unsigned(cfgver, 2));
cfg( 9 downto 5) := std_logic_vector(to_unsigned(version, 5));
cfg( 4 downto 0) := std_logic_vector(to_unsigned(interrupt, 5));
when others => cfg := (others => '0');
end case;
return(cfg);
end;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "00" & prefetch & cache;
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0010";
return(cfg);
end;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
if enable /= 0 then
return (ahb_membar(memaddr, prefetch, cache, addrmask));
else return(cfg); end if;
end;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0011";
return(cfg);
end;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0001";
return(cfg);
end;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic is
variable hcache : std_ulogic;
variable ctbl : std_logic_vector(15 downto 0);
begin
hcache := '0'; ctbl := (others => '0');
if cached = 0 then
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if (ahbso(i).hconfig(j)(16) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000")
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
hcache := '1';
end if;
end if;
end loop;
end loop;
else
ctbl := conv_std_logic_vector(cached, 16);
hcache := ctbl(conv_integer(haddr(31 downto 28)));
end if;
return(hcache);
end;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic is
variable pfetch : std_ulogic;
begin
pfetch := '0';
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if ((ahbso(i).hconfig(j)(17) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000"))
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
pfetch := '1';
end if;
end if;
end loop;
end loop;
return(pfetch);
end;
function ahb_membar_size (addrmask : ahb_addr_type) return integer is
begin
if addrmask = 0 then return 0; end if;
return (4096 - addrmask) * 1024 * 1024;
end;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer is
begin
return (4096 - addrmask) * 256;
end;
-- purpose: Duplicates 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedata (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedata
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
for i in 0 to AHBDW/hdata'length-1 loop
data(hdata'length-1+hdata'length*i downto hdata'length*i) := hdata;
end loop;
end if;
return data;
end ahbdrivedata;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdata
ret := hdata;
case hsize is
when HSIZE_8WORD =>
if AHBDW = 256 then ret := hdata; end if;
when HSIZE_4WORD =>
if AHBDW = 256 then
if haddr(4) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when HSIZE_DWORD =>
if AHBDW = 256 then
case haddr(4 downto 3) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 128 then
if haddr(3) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when others =>
if AHBDW = 256 then
case haddr(4 downto 2) is
when "000" => ret := ahbdrivedata(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret := ahbdrivedata(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret := ahbdrivedata(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret := ahbdrivedata(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret := ahbdrivedata(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret := ahbdrivedata(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret := ahbdrivedata(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if haddr(2) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
end case;
return ret;
end ahbselectdata;
-- Description of ahbread* functions and procedures.
--
-- The ahbread* subprograms with an 'haddr' input selects the valid slice of
-- data from the AHB data vector, 'hdata', based on the 'haddr' input if
-- CORE_ACDM is set to 1 (see top of this package). Otherwise the low part of
-- the AHB data vector will be returned.
--
-- The ahbread* subprograms that do not have a 'haddr' input will always
-- return the low slice of the 'hdata' input. These subprograms will assert a
-- failure if CORE_ACDM is set to 1.
--
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
if CORE_ACDM = 1 then data := ahbselectdata(hdata, haddr, HSIZE_WORD)(31 downto 0);
else data := hdata(31 downto 0); end if;
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata, haddr);
end ahbreadword;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
-- pragma translate_off
assert CORE_ACDM = 0
report "ahbreadword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data := hdata(31 downto 0);
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata);
end ahbreadword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/4-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/4-1 downto 0);
else
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 64 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata, haddr);
end ahbreaddword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
assert CORE_ACDM = 0
report "ahbreaddword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 64 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata);
end ahbreaddword;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata, haddr);
end ahbread4word;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread4word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata);
end ahbread4word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
-- pragma translate_on
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) := ahbselectdata(hdata, haddr, HSIZE_8WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata, haddr);
end ahbread8word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread8word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata);
end ahbread8word;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata, haddr);
when HSIZE_4WORD =>
return ahbread4word(hdata, haddr);
when HSIZE_DWORD =>
return ahbreaddword(hdata, haddr);
when others => null;
end case;
return ahbreadword(hdata, haddr);
end ahbreaddata;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata);
when HSIZE_4WORD =>
return ahbread4word(hdata);
when HSIZE_DWORD =>
return ahbreaddword(hdata);
when others => null;
end case;
return ahbreadword(hdata);
end ahbreaddata;
-- a*mux below drives their amba output records with the amba input record if
-- the en input is '1'. Otherwise the amba output record is driven to an idle
-- state. Plug'n'play information is kept constant.
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbm_none; end if;
ao.haddr <= ai.haddr;
ao.hwrite <= ai.hwrite;
ao.hsize <= ai.hsize;
ao.hprot <= ai.hprot;
ao.hwdata <= ai.hwdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbmomux;
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbs_none; end if;
ao.hrdata <= ai.hrdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbsomux;
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= apb_none; end if;
ao.prdata <= ai.prdata;
ao.pconfig <= ai.pconfig;
ao.pindex <= ai.pindex;
end apbsomux;
end;
| gpl-2.0 | 9d5c050131f8e8a5152e5affb134c3e3 | 0.609422 | 3.623596 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/can/can_oc.vhd | 1 | 5,690 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_oc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end;
architecture rtl of can_oc is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
dataout := data_out(0);
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(0), irqo(0), can_rxi, can_txo, ahbsi.testen);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 | 22ce04b3418fb65c9d819c4e90870528 | 0.595079 | 3.540759 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/clkmux.vhd | 1 | 3,820 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkmux
-- File: clkmux.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Glitch-free clock multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkmux is
generic(tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end entity;
architecture rtl of clkmux is
signal seli, sel0, sel1, cg0, cg1 : std_ulogic;
begin
rs : if rsel = 1 generate
rsproc : process(i0)
begin
if rising_edge(i0) then seli <= sel; end if;
end process;
end generate;
cs : if rsel = 0 generate seli <= sel; end generate;
tec : if has_clkmux(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
buf : clkmux_unisim port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
rhl : if tech = rhlib18t generate
buf : clkmux_rhlib18t port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
ut13 : if tech = ut130 generate
x0 : clkmux_ut130hbd port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
n2x : if tech = easic45 generate
mux : clkmux_n2x port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
ut90n : if tech = ut90 generate
x0 : clkmux_ut90nhbd port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
saed : if tech = saed32 generate
x0 : clkmux_saed32 port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
dar : if tech = dare generate
x0 : clkmux_dare port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
rhu : if tech = rhumc generate
x0 : clkmux_rhumc port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
noxil : if not((is_unisim(tech) = 1) or (tech = rhlib18t) or (tech = ut130) or
(tech = easic45) or (tech = ut90) or (tech = saed32) or (tech = dare) or (tech = rhumc)) generate
o <= i0 when seli = '0' else i1;
end generate;
end generate;
gen : if has_clkmux(tech) = 0 generate
p0 : process(i0, rst)
begin
if rst = '0' then
sel0 <= '1';
elsif falling_edge(i0) then
sel0 <= (not seli) and (not sel1);
end if;
end process;
p1 : process(i1, rst)
begin
if rst = '0' then
sel1 <= '0';
elsif falling_edge(i1) then
sel1 <= seli and (not sel0);
end if;
end process;
cg0 <= i0 and sel0;
cg1 <= i1 and sel1;
o <= cg0 or cg1;
end generate;
end architecture;
| gpl-2.0 | 1639a995be2e00c463b01be3ed9b8272 | 0.564398 | 3.475887 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd | 1 | 27,300 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.avnet_eval.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
clk_50mhz : in std_ulogic;
clk_200p : in std_ulogic;
clk_200n : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0);
phy_done : out std_ulogic;
rst_done : out std_ulogic
);
end;
architecture rtl of leon3mp is
component mig_36_1
port(
cntrl0_ddr_dq : inout std_logic_vector(15 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
init_done : out std_logic;
sys_reset_in_n : in std_logic;
cntrl0_clk_tb : out std_logic;
cntrl0_reset_tb : out std_logic;
cntrl0_wdf_almost_full : out std_logic;
cntrl0_af_almost_full : out std_logic;
cntrl0_read_data_valid : out std_logic;
cntrl0_app_wdf_wren : in std_logic;
cntrl0_app_af_wren : in std_logic;
cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);
cntrl0_app_af_addr : in std_logic_vector(35 downto 0);
cntrl0_app_wdf_data : in std_logic_vector(31 downto 0);
cntrl0_read_data_fifo_out : out std_logic_vector(31 downto 0);
cntrl0_app_mask_data : in std_logic_vector(3 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(1 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal lclk50 : std_logic;
signal rst0_tb, rst0_tbn, clk0_tb : std_logic;
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal init_done : std_ulogic;
signal migrst : std_ulogic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstneg;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk50_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk50);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk50, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
sh : if CFG_GRFPUSH = 1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 100, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_avnet_eval
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#FE0#,
MHz => 100, Mbyte => 32)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, rst_50 => rstneg,
clk_ahb => clkm, clk_ddr => clk0_tb, clk_50 => lclk50,
init_done => init_done, ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
port map(
cntrl0_ddr_dq => ddr_dq,
cntrl0_ddr_a => ddr_ad(12 downto 0),
cntrl0_ddr_ba => ddr_ba,
cntrl0_ddr_cke => ddr_cke0,
cntrl0_ddr_cs_n => ddr_cs0b,
cntrl0_ddr_ras_n => ddr_rasb,
cntrl0_ddr_cas_n => ddr_casb,
cntrl0_ddr_we_n => ddr_web,
cntrl0_ddr_dm => ddr_dm,
sys_clk_p => clk_100mhz, clk200_p => clk_200p,
sys_clk_n => clk_100mhz, clk200_n => clk_200n,
init_done => init_done,
sys_reset_in_n => migi.mig_rst,
cntrl0_reset_tb => rst0_tb, cntrl0_clk_tb => clk0_tb,
cntrl0_wdf_almost_full => migo.app_wdf_afull,
cntrl0_af_almost_full => migo.app_af_afull,
cntrl0_read_data_valid => migo.app_rd_data_valid,
cntrl0_app_wdf_wren => migi.app_wdf_wren,
cntrl0_app_af_wren => migi.app_en,
cntrl0_app_af_addr => migi.app_addr,
cntrl0_app_wdf_data => migi.app_wdf_data,
cntrl0_read_data_fifo_out => migo.app_rd_data,
cntrl0_app_mask_data => migi.app_wdf_mask,
cntrl0_ddr_dqs => ddr_dqs,
cntrl0_ddr_ck => ddr_clk(0 downto 0),
cntrl0_ddr_ck_n => ddr_clkb(0 downto 0)
);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
rst0_tbn <= not rst0_tb;
-- lock <= cgo.clklock;
lock <= init_done and rst0_tbn;
-- led(7) <= init_done;
end generate;
phy_done <= init_done;
rst_done <= migi.mig_rst;
noddr : if (CFG_DDRSP + CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-2.0 | 13680519433fc03e4e1d02e8ac4e7e28 | 0.540769 | 3.570961 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/ddr_oreg.vhd | 1 | 2,899 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_oreg
-- File: ddr_oreg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR output reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_oreg is generic (tech : integer; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ddr_oreg is
begin
inf : if not ((tech = lattice) or (is_unisim(tech) = 1) or
(tech = axcel) or (tech = axdsp) or (tech = apa3) or
(tech = apa3e) or (tech = apa3l)) generate
inf0 : gen_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
ax0 : axcel_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
lat : if tech = lattice generate
lat0 : ec_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_oddr_reg generic map (tech, arch)
port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_oreg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end;
| gpl-2.0 | 952085e6fb4099146053c2fddacba297 | 0.595723 | 3.378788 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/explosion/simulation/explosion_tb.vhd | 1 | 4,361 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: explosion_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY explosion_tb IS
END ENTITY;
ARCHITECTURE explosion_tb_ARCH OF explosion_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
explosion_synth_inst:ENTITY work.explosion_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 373bafdd3956c4a7a5150380a33cf84a | 0.620958 | 4.684211 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3sl150/config.vhd | 1 | 6,555 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 82a354c034b7a1272106bb76758cda6f | 0.645919 | 3.550921 | false | false | false | false |
freecores/usb_fpga_1_11 | examples/usb-fpga-2.16/2.16b/ucecho/fpga-vivado/ucecho.vhd | 4 | 738 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
signal clk : std_logic;
begin
clk_buf : IBUFG
port map (
I => fxclk_in,
O => clk
);
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 | 9bbe0a9a7f3b9c80a6a6ab1b5e6491ec | 0.566396 | 3.167382 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/leon4_net.vhd | 1 | 22,827 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon4_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end ;
architecture rtl of leon4_net is
signal disasen : std_ulogic;
component leon4_ut90nhbd
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
hclken: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(127 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(127 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(127 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
disasen : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(127 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(127 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(127 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig: ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON4, 0, 0, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbox.hconfig <= hconfig;
ahbox.hindex <= hindex;
ut09 : if fabtech = ut90 generate
wrp: leon4_ut90nhbd
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize, smp => smp)
port map(
clk => clk,
gclk => gclk,
hclken => hclken,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
disasen => disasen);
end generate;
ahbi_hgrant(0) <= ahbix.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbix.hready;
ahbi_hresp <= ahbix.hresp;
ahbi_hrdata(127 mod AHBDW downto 0) <= ahbix.hrdata(127 mod AHBDW downto 0);
ahbi_hirq <= ahbix.hirq;
ahbi_testen <= ahbix.testen;
ahbi_testrst <= ahbix.testrst;
ahbi_scanen <= ahbix.scanen;
ahbi_testoen <= ahbix.testoen;
ahbox.hbusreq <= ahbo_hbusreq;
ahbox.hlock <= ahbo_hlock;
ahbox.htrans <= ahbo_htrans;
ahbox.haddr <= ahbo_haddr;
ahbox.hwrite <= ahbo_hwrite;
ahbox.hsize <= ahbo_hsize(2 downto 0);
ahbox.hburst <= "00" & ahbo_hburst(0);
ahbox.hprot <= ahbo_hprot;
ahbox.hwdata(127 mod AHBDW downto 0) <= ahbo_hwdata(127 mod AHBDW downto 0);
ahbox.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsix.hsel;
ahbsi_haddr <= ahbsix.haddr;
ahbsi_hwrite <= ahbsix.hwrite;
ahbsi_htrans <= ahbsix.htrans;
ahbsi_hsize <= ahbsix.hsize;
ahbsi_hburst <= ahbsix.hburst;
ahbsi_hwdata(127 mod AHBDW downto 0) <= ahbsix.hwdata(127 mod AHBDW downto 0);
ahbsi_hprot <= ahbsix.hprot;
ahbsi_hready <= ahbsix.hready;
ahbsi_hmaster <= ahbsix.hmaster;
ahbsi_hmastlock <= ahbsix.hmastlock;
ahbsi_hmbsel <= ahbsix.hmbsel;
ahbsi_hirq <= ahbsix.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON3FT netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
| gpl-2.0 | 2c0572cc3831a9777e4ece175637f1c8 | 0.51093 | 3.878845 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/memctrl.vhd | 1 | 19,714 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
end;
| gpl-2.0 | 8afada040e4673d6eacc2b645b4c65bf | 0.516232 | 3.476896 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd | 1 | 3,543 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de2 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
| gpl-2.0 | a4552d87309f27ee42d3a7ae1fbd753c | 0.594694 | 3.675311 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_pkg.vhd | 1 | 12,302 | -------------------------------------------------------------------------------
-- axi_cdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
package axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width1 (dwidth,
burst_size,
btt_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL : integer := 18;
constant NUM_REG_PER_CHANNEL : integer := 6;
constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
--constant CMD_BASE_WIDTH : integer := 40;
constant CMD_BASE_WIDTH : integer := 104;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
constant MTBF_STAGES : integer := 4;
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RESERVED0_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SGMODE_BIT : integer := 3;
constant DMACR_KHREAD_BIT : integer := 4;
constant DMACR_KHWRITE_BIT : integer := 5;
--constant DMACR_RESERVED4_BIT : integer := 4;
--constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_CYCLIC_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- BTT
constant BTT_MSB_BIT : integer := 22;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_cdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width1 ( dwidth,
burst_size,
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width1;
end package body axi_cdma_pkg;
| gpl-3.0 | 908a75919102bf41140864f6033b3401 | 0.569257 | 4.379494 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1000/leon3mp.vhd | 1 | 16,901 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
error : out std_ulogic;
address : out std_logic_vector(19 downto 2);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (1 downto 0);
mben : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
-- switch : in std_logic_vector(7 downto 0); -- switches
-- button : in std_logic_vector(2 downto 0); -- buttons
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+
CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, nerror : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkval : std_logic_vector(1 downto 0);
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
signal stati : ahbstat_in_type;
signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
nerror <= not dbgo(0).error;
error_pad : outpad generic map (tech => padtech) port map (error, nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
rommask => 16#000#, iomask => 16#000#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 18, tech => padtech)
port map (address, memo.address(19 downto 2));
ramsa_pad : outpad generic map (tech => padtech)
port map (ramsn(0), memo.ramsn(0));
ramsb_pad : outpad generic map (tech => padtech)
port map (ramsn(1), memo.ramsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
mben_pads : outpadv generic map (tech => padtech, width => 4)
port map (mben, memo.mben);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (data, memo.data(31 downto 0),
memo.vbdrive(31 downto 0), memi.data(31 downto 0));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
dac_clk <= not video_clk;
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 20000, clk2 => 25000)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : iopadvv generic map (width => 18, tech => padtech)
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
gpioi.din(17 downto 0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 5836097d76ace44c6de57a8e42d6c0ef | 0.558251 | 3.663776 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml50x/grlib_config.vhd | 1 | 2,564 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
end;
| gpl-2.0 | e8136af418a0f6882007fc933bf21ebd | 0.654446 | 4.175896 | false | true | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3/leon3.vhd | 1 | 35,770 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
iact : std_ulogic;
index : std_logic_vector(3 downto 0);
hrdrst : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
idle : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
diag : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end component;
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
end record;
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
| gpl-2.0 | 252274f86c21776ab5c1dcc41fc45efb | 0.52544 | 3.440746 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_cols_V_2_loc_channel1.vhd | 2 | 4,684 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_2_loc_channel1 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_2_loc_channel1 is
component FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg : FIFO_image_filter_p_src_cols_V_2_loc_channel1_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | ed81fefe4a44812fb1a09e70427df479 | 0.541418 | 3.42899 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_sf.vhd | 1 | 40,689 | -------------------------------------------------------------------------------
-- axi_cdma_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sf.vhd
--
-- Description:
-- This file implements the AXI CDMA store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control interfaces. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full. On the AXI Write side, the Write Master is
-- only allowed to post AXI WRite Requests if the associated write data needed
-- to complete the Write Data transfer is present in the Data FIFO. In
-- addition, the Write side logic is such that Write transfer requests can
-- be pipelined to the AXI bus based on the Data FIFO contents but ahead of
-- the actual Write Data transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_cdma_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock input
aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
reset : in std_logic;
-- Reset used for the internal syncronization logic
-- DataMover Read Side Address Pipelining Control Interface ---------------
ok_to_post_rd_addr : Out Std_logic;
-- Indicates that the transfer token pool has at least
-- one token available to borrow
rd_addr_posted : In std_logic;
-- Indication that a read address has been posted to AXI4
rd_xfer_cmplt : In std_logic;
-- Indicates that the Datamover has completed a Read Data
-- transfer on the AXI4
-- Read Side Stream In from DataMover MM2S -----------------------------------
sf2sin_tready : Out Std_logic;
-- DRE Stream READY input
sin2sf_tvalid : In std_logic;
-- DRE Stream VALID Output
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- DRE Stream DATA input
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- DRE Stream STRB input
sin2sf_tlast : In std_logic;
-- DRE Xfer LAST input
-- DataMover Write Side Address Pipelining Control Interface --------------
ok_to_post_wr_addr : Out Std_logic;
-- Indicates that the internal FIFO has enough data
-- physically present to supply one more max length
-- burst transfer or a completion burst
-- (tlast asserted)
wr_addr_posted : In std_logic;
-- Indication that a write address has been posted to AXI4
wr_xfer_cmplt : In Std_logic;
-- Indicates that the Datamover has completed a Write Data
-- transfer on the AXI4
wr_ld_nxt_len : in std_logic;
-- Active high pulse indicating a new transfer LEN qualifier
-- has been queued to the DataMover Write Data Controller
wr_len : in std_logic_vector(7 downto 0);
-- The actual LEN qualifier value that has been queued to the
-- DataMover Write Data Controller
-- Write Side Stream Out to DataMover S2MM -------------------------------
sout2sf_tready : In std_logic;
-- Write READY input from the Stream Master
sf2sout_tvalid : Out std_logic;
-- Write VALID output to the Stream Master
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tlast : Out std_logic
-- Write LAST output to the Stream Master
);
end entity axi_cdma_sf;
architecture implementation of axi_cdma_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbcntr_width
--
-- Function Description:
-- simple function to set the width of the burst counter
-- based on the parameterized max burst length.
--
-------------------------------------------------------------------
function funct_get_dbcntr_width (max_burst_length : integer)
return integer is
Variable temp_width : integer := 0;
begin
case max_burst_length is
when 2 =>
temp_width := 1;
when 4 =>
temp_width := 2;
when 8 =>
temp_width := 3;
when 16 =>
temp_width := 4;
when 32 =>
temp_width := 5;
when 64 =>
temp_width := 6;
when 128 =>
temp_width := 7;
when others => -- 256 beats
temp_width := 8;
end case;
Return (temp_width);
end function funct_get_dbcntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_STREAM_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_STREAM_DWIDTH+
WSTB_WIDTH +
TLAST_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_STREAM_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant DBEAT_CNTR_WIDTH : integer := funct_get_dbcntr_width(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, DBEAT_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DBEAT_CNTR_WIDTH);
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(C_DRE_IS_USED ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CMTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CMTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CMTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthotized post occurs.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
TSTRB_OUT_LSB_INDEX);
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_cdma_v4_1.axi_cdma_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
| gpl-3.0 | ec7a13ef49b119d66341a495658075c9 | 0.482047 | 4.521 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_reg_int_s.vhd | 2 | 1,002 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_reg_int_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of image_filter_reg_int_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
begin
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
ap_return <= in_r;
end if;
end if;
end process;
end behav;
| gpl-3.0 | c8cc7babbf2badb0221072fe0044b77d | 0.522954 | 3.515789 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx60/config.vhd | 1 | 6,156 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 23c4bee071778e2625c35685fe26dc45 | 0.643437 | 3.608441 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp601/ahb2mig_sp601.vhd | 1 | 17,376 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp601
-- File: ahb2mig_sp601.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp601 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_n : in std_logic;
clk_mem_p : in std_logic
);
end ;
architecture rtl of ahb2mig_sp601 is
component mig_37
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
-- C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
-- C3_MC_CALIB_BYPASS => "YES"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
| gpl-2.0 | 70231b66c9d79aa795f970bf84697229 | 0.493669 | 3.176019 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/tap_unisim.vhd | 1 | 24,308 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
| gpl-2.0 | 1640683f72e97b87baadca2d0fb807dc | 0.498025 | 3.750656 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/wrapper/greth_gbit_gen.vhd | 1 | 13,434 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit_gen
-- File: greth_gbit_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Gigabit Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end entity;
architecture rtl of greth_gbit_gen is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => gtx_clk,
tx_clk => tx_clk,
rx_clk => rx_clk,
rxd => rxd,
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd,
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed,
gbit => gbit);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
| gpl-2.0 | 3d9798233e8e5d196a98a32334ec7c8a | 0.511389 | 4.173346 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/syncram128bw.vhd | 1 | 6,251 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(16*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(16*custombits-1 downto 0));
end;
architecture rtl of syncram128bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component tm65gplus_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic
);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0);
nocust: if syncram_has_customif(tech)=0 or has_sram128bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s64 : if has_sram128bw(tech) = 1 generate
xc2v : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
ut09: if tech = ut90 generate
x0 : ut90nhbd_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
customout(16*custombits-1 downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128bw: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos64 : if has_sram128bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
end generate;
end;
| gpl-2.0 | 9ef54fad13e42c996b112a7b005de961 | 0.633019 | 3.647025 | false | true | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/clkinv.vhd | 1 | 1,888 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-2.0 | 331f74a4d9d6a2042672d8262450854c | 0.601695 | 4.15859 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/game_over/simulation/bmg_stim_gen.vhd | 1 | 12,587 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (19199 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"game_over.mif",
DEFAULT_DATA,
12,
19200);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>19200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 19200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 72965741547e82cdc9b11f7b91e6c288 | 0.547946 | 3.686878 | false | false | false | false |
borti4938/sd2snes | verilog/sd2snes_sdd1/Golomb_N_Decoder.vhd | 2 | 3,249 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 20.03.2018 18:42:09
-- Design Name:
-- Module Name: Golomb_Decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Golomb_N_Decoder is
Generic( N : integer);
Port( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(N DOWNTO 0);
din_tuser : OUT STD_LOGIC_VECTOR(2 downto 0);
dout_tready : IN STD_LOGIC;
dout_tdata : OUT STD_LOGIC;
dout_tlast : OUT STD_LOGIC);
end Golomb_N_Decoder;
architecture Behavioral of Golomb_N_Decoder is
signal zero_count : integer range 0 to 2**N-1 := 0;
signal max_count : integer range 0 to 2**N-1 := 0;
signal LPS_Flag : STD_LOGIC := '0';
signal end_bit : STD_LOGIC := '0';
begin
-- number of zero bits and tail bit
max_count <= 2**N - conv_integer(din_tdata(N downto 1)) - 1 when din_tdata(0) = '1' else
2**N - 1;
LPS_Flag <= '0' when din_tdata(0) = '0' else '1';
Process( clk )
Begin
if rising_edge( clk ) then
if( rst = '1' ) then
zero_count <= 0;
end_bit <= '0';
else
-- each new output bit run, counter is loaded with number of consecutive zeros
-- and input code is registered
if( dout_tready = '1' ) then
if( zero_count = 0 ) then
end_bit <= LPS_Flag;
zero_count <= max_count;
else
zero_count <= zero_count-1;
end if;
end if;
end if;
end if;
End Process;
-- select how many input bits to shift
Process( zero_count, dout_tready, LPS_Flag )
Begin
if( zero_count = 0 ) then
din_tready <= dout_tready;
-- if input bit is '0', shift 1 bit, else shift N bits
if( LPS_Flag = '0' ) then
din_tuser <= "000";
else
din_tuser <= conv_std_logic_vector(N, 3);
end if;
else
din_tready <= '0';
din_tuser <= "000";
end if;
End Process;
-- select output data depending on run counter
Process( zero_count, max_count, end_bit )
Begin
-- new input code must be read to generate run
if( zero_count = 0 ) then
if( max_count = 0 ) then
dout_tdata <= '1';
dout_tlast <= '1';
else
dout_tdata <= '0';
dout_tlast <= '0';
end if;
elsif( zero_count = 1 ) then
dout_tdata <= end_bit;
dout_tlast <= '1';
else
dout_tdata <= '0';
dout_tlast <= '0';
end if;
End Process;
end Behavioral;
| gpl-2.0 | e213b287267fc78c14198eeec1c825a5 | 0.556479 | 3.056444 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s06v2/hls/solution1/syn/vhdl/axi_stream_gpio.vhd | 3 | 4,500 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity axi_stream_gpio is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
inputData_V : IN STD_LOGIC_VECTOR (0 downto 0);
inputData_V_ap_vld : IN STD_LOGIC;
outputData_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
outputData_TVALID : IN STD_LOGIC;
outputData_TREADY : OUT STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of axi_stream_gpio is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"axi_stream_gpio,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=0.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_19 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_19 assign process. --
ap_sig_bdd_19_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_19 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_19)
begin
if (ap_sig_bdd_19) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
outputData_TREADY <= ap_const_logic_0;
end behav;
| gpl-3.0 | 922eca5f1f107d07adddc208e1ac1319 | 0.574222 | 3.028264 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/image_filter_Loop_1_proc.vhd | 2 | 51,389 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Loop_1_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
img_1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_0_V_full_n : IN STD_LOGIC;
img_1_data_stream_0_V_write : OUT STD_LOGIC;
img_1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_1_V_full_n : IN STD_LOGIC;
img_1_data_stream_1_V_write : OUT STD_LOGIC;
img_1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_2_V_full_n : IN STD_LOGIC;
img_1_data_stream_2_V_write : OUT STD_LOGIC;
img_0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_0_V_empty_n : IN STD_LOGIC;
img_0_data_stream_0_V_read : OUT STD_LOGIC;
img_0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_1_V_empty_n : IN STD_LOGIC;
img_0_data_stream_1_V_read : OUT STD_LOGIC;
img_0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_2_V_empty_n : IN STD_LOGIC;
img_0_data_stream_2_V_read : OUT STD_LOGIC;
buffer_val_0_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce0 : OUT STD_LOGIC;
buffer_val_0_we0 : OUT STD_LOGIC;
buffer_val_0_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce1 : OUT STD_LOGIC;
buffer_val_0_we1 : OUT STD_LOGIC;
buffer_val_0_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce0 : OUT STD_LOGIC;
buffer_val_1_we0 : OUT STD_LOGIC;
buffer_val_1_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce1 : OUT STD_LOGIC;
buffer_val_1_we1 : OUT STD_LOGIC;
buffer_val_1_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce0 : OUT STD_LOGIC;
buffer_val_2_we0 : OUT STD_LOGIC;
buffer_val_2_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce1 : OUT STD_LOGIC;
buffer_val_2_we1 : OUT STD_LOGIC;
buffer_val_2_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end;
architecture behav of image_filter_Loop_1_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_pp0_stg1_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_pp0_stg2_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st7_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_25 : BOOLEAN;
signal col_reg_269 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_281_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_sig_bdd_104 : BOOLEAN;
signal tmp_2_fu_285_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal buffer_val_0_addr_gep_fu_159_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_0_addr_reg_551 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_0_addr_1_gep_fu_167_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_0_addr_1_reg_556 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_gep_fu_175_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_reg_561 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_1_gep_fu_183_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_1_reg_566 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_gep_fu_191_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_reg_571 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_1_gep_fu_199_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_1_reg_577 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_0_addr_2_gep_fu_207_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_0_addr_2_reg_582 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_2_gep_fu_215_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_1_addr_2_reg_587 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_2_gep_fu_223_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_val_2_addr_2_reg_592 : STD_LOGIC_VECTOR (1 downto 0);
signal exitcond2_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_134 : BOOLEAN;
signal row_1_fu_298_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal row_1_reg_602 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond1_fu_308_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_reg_607 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_145 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_159 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal col_1_fu_313_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal col_1_reg_611 : STD_LOGIC_VECTOR (10 downto 0);
signal icmp_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_reg_616 : STD_LOGIC_VECTOR (0 downto 0);
signal scl_val_0_reg_624 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg1_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_180 : BOOLEAN;
signal ap_sig_bdd_190 : BOOLEAN;
signal scl_val_1_reg_630 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_2_reg_636 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_0_load_reg_643 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_1_load_reg_649 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_2_load_reg_655 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_0_load_1_reg_660 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_1_load_1_reg_665 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_val_2_load_1_reg_670 : STD_LOGIC_VECTOR (7 downto 0);
signal c_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_reg_675 : STD_LOGIC_VECTOR (0 downto 0);
signal ult_fu_341_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ult_reg_681 : STD_LOGIC_VECTOR (0 downto 0);
signal rev1_fu_353_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev1_reg_686 : STD_LOGIC_VECTOR (0 downto 0);
signal c_1_fu_359_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_1_reg_691 : STD_LOGIC_VECTOR (0 downto 0);
signal ult2_fu_365_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ult2_reg_697 : STD_LOGIC_VECTOR (0 downto 0);
signal rev3_fu_377_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev3_reg_702 : STD_LOGIC_VECTOR (0 downto 0);
signal c_2_fu_383_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_2_reg_707 : STD_LOGIC_VECTOR (0 downto 0);
signal ult4_fu_389_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ult4_reg_713 : STD_LOGIC_VECTOR (0 downto 0);
signal ult5_fu_395_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ult5_reg_718 : STD_LOGIC_VECTOR (0 downto 0);
signal p_val_0_1_fu_427_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_0_1_reg_723 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg2_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal p_val_1_1_fu_460_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_1_1_reg_728 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_0_2_fu_499_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_0_2_reg_733 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp2_fu_505_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_738 : STD_LOGIC_VECTOR (0 downto 0);
signal p_val_1_2_fu_510_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_val_1_2_reg_744 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_521_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_749 : STD_LOGIC_VECTOR (7 downto 0);
signal row_reg_258 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st7_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_257 : BOOLEAN;
signal col_phi_fu_273_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal row_cast_fu_289_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal col_cast_fu_304_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_3_fu_319_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal ult1_fu_347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ult3_fu_371_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev_fu_401_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_0_not_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_fu_417_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_fu_411_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_val_0_load_scl_val_0_fu_421_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rev2_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_0_not_1_fu_439_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_1_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_1_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_val_1_load_scl_val_1_fu_454_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rev4_fu_467_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_0_not_2_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev5_fu_483_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_2_fu_488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_2_fu_477_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_val_2_load_p_val_2_fu_493_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp9_fu_516_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond2_fu_293_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond1_fu_308_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond2_fu_293_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond2_fu_293_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((exitcond1_reg_607 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- col_reg_269 assign process. --
col_reg_269_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
col_reg_269 <= col_1_reg_611;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond2_fu_293_p2 = ap_const_lv1_0))) then
col_reg_269 <= ap_const_lv11_0;
end if;
end if;
end process;
-- row_reg_258 assign process. --
row_reg_258_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_104))) then
row_reg_258 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5)) then
row_reg_258 <= row_1_reg_602;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190)))) then
buffer_val_0_load_1_reg_660 <= buffer_val_0_q1;
buffer_val_0_load_reg_643 <= buffer_val_0_q0;
buffer_val_1_load_1_reg_665 <= buffer_val_1_q1;
buffer_val_1_load_reg_649 <= buffer_val_1_q0;
buffer_val_2_load_1_reg_670 <= buffer_val_2_q1;
buffer_val_2_load_reg_655 <= buffer_val_2_q0;
c_1_reg_691 <= c_1_fu_359_p2;
c_2_reg_707 <= c_2_fu_383_p2;
c_reg_675 <= c_fu_335_p2;
p_val_2_reg_636 <= img_0_data_stream_2_V_dout;
rev1_reg_686 <= rev1_fu_353_p2;
rev3_reg_702 <= rev3_fu_377_p2;
scl_val_0_reg_624 <= img_0_data_stream_0_V_dout;
scl_val_1_reg_630 <= img_0_data_stream_1_V_dout;
ult2_reg_697 <= ult2_fu_365_p2;
ult4_reg_713 <= ult4_fu_389_p2;
ult5_reg_718 <= ult5_fu_395_p2;
ult_reg_681 <= ult_fu_341_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
col_1_reg_611 <= col_1_fu_313_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
exitcond1_reg_607 <= exitcond1_fu_308_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond1_fu_308_p2 = ap_const_lv1_0))) then
icmp_reg_616 <= icmp_fu_329_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4))) then
p_val_0_1_reg_723 <= p_val_0_1_fu_427_p3;
p_val_0_2_reg_733 <= p_val_0_2_fu_499_p3;
p_val_1_1_reg_728 <= p_val_1_1_fu_460_p3;
p_val_1_2_reg_744 <= p_val_1_2_fu_510_p3;
sel_tmp2_reg_738 <= sel_tmp2_fu_505_p2;
tmp_6_reg_749 <= tmp_6_fu_521_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
row_1_reg_602 <= row_1_fu_298_p2;
end if;
end if;
end process;
buffer_val_0_addr_reg_551(1 downto 0) <= "01";
buffer_val_0_addr_1_reg_556(1 downto 0) <= "10";
buffer_val_1_addr_reg_561(1 downto 0) <= "01";
buffer_val_1_addr_1_reg_566(1 downto 0) <= "10";
buffer_val_2_addr_reg_571(1 downto 0) <= "01";
buffer_val_2_addr_1_reg_577(1 downto 0) <= "10";
buffer_val_0_addr_2_reg_582(1 downto 0) <= "00";
buffer_val_1_addr_2_reg_587(1 downto 0) <= "00";
buffer_val_2_addr_2_reg_592(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_104, exitcond2_fu_293_p2, exitcond1_fu_308_p2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_bdd_190)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_104)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond2_fu_293_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if ((not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond1_fu_308_p2 = ap_const_lv1_0)))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_3;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond1_fu_308_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg1_fsm_3 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_4;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_3;
end if;
when ap_ST_pp0_stg2_fsm_4 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
when ap_ST_st7_fsm_5 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond2_fu_293_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond2_fu_293_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond2_fu_293_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond2_fu_293_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_104 assign process. --
ap_sig_bdd_104_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_104 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_134 assign process. --
ap_sig_bdd_134_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_134 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_145 assign process. --
ap_sig_bdd_145_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_145 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_159 assign process. --
ap_sig_bdd_159_assign_proc : process(img_1_data_stream_0_V_full_n, img_1_data_stream_1_V_full_n, img_1_data_stream_2_V_full_n, exitcond1_reg_607)
begin
ap_sig_bdd_159 <= (((img_1_data_stream_0_V_full_n = ap_const_logic_0) and (exitcond1_reg_607 = ap_const_lv1_0)) or ((exitcond1_reg_607 = ap_const_lv1_0) and (img_1_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond1_reg_607 = ap_const_lv1_0) and (img_1_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_180 assign process. --
ap_sig_bdd_180_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_180 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_190 assign process. --
ap_sig_bdd_190_assign_proc : process(img_0_data_stream_0_V_empty_n, img_0_data_stream_1_V_empty_n, img_0_data_stream_2_V_empty_n, exitcond1_reg_607)
begin
ap_sig_bdd_190 <= (((exitcond1_reg_607 = ap_const_lv1_0) and (img_0_data_stream_0_V_empty_n = ap_const_logic_0)) or ((exitcond1_reg_607 = ap_const_lv1_0) and (img_0_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond1_reg_607 = ap_const_lv1_0) and (img_0_data_stream_2_V_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_25 assign process. --
ap_sig_bdd_25_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_25 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_257 assign process. --
ap_sig_bdd_257_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_257 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_145)
begin
if (ap_sig_bdd_145) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_pp0_stg1_fsm_3 assign process. --
ap_sig_cseq_ST_pp0_stg1_fsm_3_assign_proc : process(ap_sig_bdd_180)
begin
if (ap_sig_bdd_180) then
ap_sig_cseq_ST_pp0_stg1_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg1_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_pp0_stg2_fsm_4 assign process. --
ap_sig_cseq_ST_pp0_stg2_fsm_4_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_pp0_stg2_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg2_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_25)
begin
if (ap_sig_bdd_25) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_134)
begin
if (ap_sig_bdd_134) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_5 assign process. --
ap_sig_cseq_ST_st7_fsm_5_assign_proc : process(ap_sig_bdd_257)
begin
if (ap_sig_bdd_257) then
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_0;
end if;
end process;
brmerge1_1_fu_450_p2 <= (rev3_reg_702 or c_1_reg_691);
brmerge1_2_fu_488_p2 <= (rev5_fu_483_p2 or c_2_reg_707);
brmerge1_fu_417_p2 <= (rev1_reg_686 or c_reg_675);
brmerge_1_fu_444_p2 <= (rev2_fu_434_p2 or c_0_not_1_fu_439_p2);
brmerge_2_fu_477_p2 <= (rev4_fu_467_p2 or c_0_not_2_fu_472_p2);
brmerge_fu_411_p2 <= (rev_fu_401_p2 or c_0_not_fu_406_p2);
buffer_val_0_addr_1_gep_fu_167_p3 <= ap_const_lv64_2(2 - 1 downto 0);
buffer_val_0_addr_2_gep_fu_207_p3 <= ap_const_lv64_0(2 - 1 downto 0);
buffer_val_0_addr_gep_fu_159_p3 <= ap_const_lv64_1(2 - 1 downto 0);
-- buffer_val_0_address0 assign process. --
buffer_val_0_address0_assign_proc : process(buffer_val_0_addr_reg_551, buffer_val_0_addr_1_reg_556, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4))) then
buffer_val_0_address0 <= buffer_val_0_addr_1_reg_556;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)))) then
buffer_val_0_address0 <= buffer_val_0_addr_reg_551;
else
buffer_val_0_address0 <= "XX";
end if;
end process;
buffer_val_0_address1 <= buffer_val_0_addr_2_reg_582;
-- buffer_val_0_ce0 assign process. --
buffer_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_0_ce0 <= ap_const_logic_1;
else
buffer_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_0_ce1 assign process. --
buffer_val_0_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_0_ce1 <= ap_const_logic_1;
else
buffer_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_0_d0 assign process. --
buffer_val_0_d0_assign_proc : process(buffer_val_0_q1, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, buffer_val_0_load_reg_643, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
buffer_val_0_d0 <= buffer_val_0_load_reg_643;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
buffer_val_0_d0 <= buffer_val_0_q1;
else
buffer_val_0_d0 <= "XXXXXXXX";
end if;
else
buffer_val_0_d0 <= "XXXXXXXX";
end if;
end process;
buffer_val_0_d1 <= img_0_data_stream_0_V_dout;
buffer_val_0_load_scl_val_0_fu_421_p3 <=
buffer_val_0_load_reg_643 when (brmerge1_fu_417_p2(0) = '1') else
scl_val_0_reg_624;
-- buffer_val_0_we0 assign process. --
buffer_val_0_we0_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_0_we0 <= ap_const_logic_1;
else
buffer_val_0_we0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_0_we1 assign process. --
buffer_val_0_we1_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_0_we1 <= ap_const_logic_1;
else
buffer_val_0_we1 <= ap_const_logic_0;
end if;
end process;
buffer_val_1_addr_1_gep_fu_183_p3 <= ap_const_lv64_2(2 - 1 downto 0);
buffer_val_1_addr_2_gep_fu_215_p3 <= ap_const_lv64_0(2 - 1 downto 0);
buffer_val_1_addr_gep_fu_175_p3 <= ap_const_lv64_1(2 - 1 downto 0);
-- buffer_val_1_address0 assign process. --
buffer_val_1_address0_assign_proc : process(buffer_val_1_addr_reg_561, buffer_val_1_addr_1_reg_566, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4))) then
buffer_val_1_address0 <= buffer_val_1_addr_1_reg_566;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)))) then
buffer_val_1_address0 <= buffer_val_1_addr_reg_561;
else
buffer_val_1_address0 <= "XX";
end if;
end process;
buffer_val_1_address1 <= buffer_val_1_addr_2_reg_587;
-- buffer_val_1_ce0 assign process. --
buffer_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_1_ce0 <= ap_const_logic_1;
else
buffer_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_1_ce1 assign process. --
buffer_val_1_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_1_ce1 <= ap_const_logic_1;
else
buffer_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_1_d0 assign process. --
buffer_val_1_d0_assign_proc : process(buffer_val_1_q1, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, buffer_val_1_load_reg_649, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
buffer_val_1_d0 <= buffer_val_1_load_reg_649;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
buffer_val_1_d0 <= buffer_val_1_q1;
else
buffer_val_1_d0 <= "XXXXXXXX";
end if;
else
buffer_val_1_d0 <= "XXXXXXXX";
end if;
end process;
buffer_val_1_d1 <= img_0_data_stream_1_V_dout;
buffer_val_1_load_scl_val_1_fu_454_p3 <=
buffer_val_1_load_reg_649 when (brmerge1_1_fu_450_p2(0) = '1') else
scl_val_1_reg_630;
-- buffer_val_1_we0 assign process. --
buffer_val_1_we0_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_1_we0 <= ap_const_logic_1;
else
buffer_val_1_we0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_1_we1 assign process. --
buffer_val_1_we1_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_1_we1 <= ap_const_logic_1;
else
buffer_val_1_we1 <= ap_const_logic_0;
end if;
end process;
buffer_val_2_addr_1_gep_fu_199_p3 <= ap_const_lv64_2(2 - 1 downto 0);
buffer_val_2_addr_2_gep_fu_223_p3 <= ap_const_lv64_0(2 - 1 downto 0);
buffer_val_2_addr_gep_fu_191_p3 <= ap_const_lv64_1(2 - 1 downto 0);
-- buffer_val_2_address0 assign process. --
buffer_val_2_address0_assign_proc : process(buffer_val_2_addr_reg_571, buffer_val_2_addr_1_reg_577, buffer_val_2_addr_2_reg_592, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
buffer_val_2_address0 <= buffer_val_2_addr_2_reg_592;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
buffer_val_2_address0 <= buffer_val_2_addr_1_reg_577;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
buffer_val_2_address0 <= buffer_val_2_addr_reg_571;
else
buffer_val_2_address0 <= "XX";
end if;
else
buffer_val_2_address0 <= "XX";
end if;
end process;
-- buffer_val_2_address1 assign process. --
buffer_val_2_address1_assign_proc : process(buffer_val_2_addr_reg_571, buffer_val_2_addr_2_reg_592, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
buffer_val_2_address1 <= buffer_val_2_addr_reg_571;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
buffer_val_2_address1 <= buffer_val_2_addr_2_reg_592;
else
buffer_val_2_address1 <= "XX";
end if;
else
buffer_val_2_address1 <= "XX";
end if;
end process;
-- buffer_val_2_ce0 assign process. --
buffer_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_2_ce0 <= ap_const_logic_1;
else
buffer_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_2_ce1 assign process. --
buffer_val_2_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_2_ce1 <= ap_const_logic_1;
else
buffer_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_2_d0 assign process. --
buffer_val_2_d0_assign_proc : process(buffer_val_2_q0, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, p_val_2_reg_636, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
buffer_val_2_d0 <= p_val_2_reg_636;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
buffer_val_2_d0 <= buffer_val_2_q0;
else
buffer_val_2_d0 <= "XXXXXXXX";
end if;
else
buffer_val_2_d0 <= "XXXXXXXX";
end if;
end process;
buffer_val_2_d1 <= buffer_val_2_q1;
buffer_val_2_load_p_val_2_fu_493_p3 <=
buffer_val_2_load_reg_655 when (brmerge1_2_fu_488_p2(0) = '1') else
p_val_2_reg_636;
-- buffer_val_2_we0 assign process. --
buffer_val_2_we0_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190, ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)))) then
buffer_val_2_we0 <= ap_const_logic_1;
else
buffer_val_2_we0 <= ap_const_logic_0;
end if;
end process;
-- buffer_val_2_we1 assign process. --
buffer_val_2_we1_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190))))) then
buffer_val_2_we1 <= ap_const_logic_1;
else
buffer_val_2_we1 <= ap_const_logic_0;
end if;
end process;
c_0_not_1_fu_439_p2 <= (c_1_reg_691 xor ap_const_lv1_1);
c_0_not_2_fu_472_p2 <= (c_2_reg_707 xor ap_const_lv1_1);
c_0_not_fu_406_p2 <= (c_reg_675 xor ap_const_lv1_1);
c_1_fu_359_p2 <= "1" when (unsigned(buffer_val_1_q1) > unsigned(img_0_data_stream_1_V_dout)) else "0";
c_2_fu_383_p2 <= "1" when (unsigned(buffer_val_2_q1) > unsigned(img_0_data_stream_2_V_dout)) else "0";
c_fu_335_p2 <= "1" when (unsigned(buffer_val_0_q1) > unsigned(img_0_data_stream_0_V_dout)) else "0";
col_1_fu_313_p2 <= std_logic_vector(unsigned(col_phi_fu_273_p4) + unsigned(ap_const_lv11_1));
col_cast_fu_304_p1 <= std_logic_vector(resize(unsigned(col_phi_fu_273_p4),12));
-- col_phi_fu_273_p4 assign process. --
col_phi_fu_273_p4_assign_proc : process(col_reg_269, exitcond1_reg_607, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it1, col_1_reg_611)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
col_phi_fu_273_p4 <= col_1_reg_611;
else
col_phi_fu_273_p4 <= col_reg_269;
end if;
end process;
exitcond1_fu_308_p2 <= "1" when (col_cast_fu_304_p1 = tmp_2_fu_285_p1) else "0";
exitcond2_fu_293_p2 <= "1" when (row_cast_fu_289_p1 = tmp_fu_281_p1) else "0";
icmp_fu_329_p2 <= "0" when (tmp_3_fu_319_p4 = ap_const_lv10_0) else "1";
-- img_0_data_stream_0_V_read assign process. --
img_0_data_stream_0_V_read_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190)))) then
img_0_data_stream_0_V_read <= ap_const_logic_1;
else
img_0_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- img_0_data_stream_1_V_read assign process. --
img_0_data_stream_1_V_read_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190)))) then
img_0_data_stream_1_V_read <= ap_const_logic_1;
else
img_0_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- img_0_data_stream_2_V_read assign process. --
img_0_data_stream_2_V_read_assign_proc : process(exitcond1_reg_607, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_sig_bdd_190)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_190)))) then
img_0_data_stream_2_V_read <= ap_const_logic_1;
else
img_0_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img_1_data_stream_0_V_din <=
p_val_0_1_reg_723 when (sel_tmp2_reg_738(0) = '1') else
p_val_0_2_reg_733;
-- img_1_data_stream_0_V_write assign process. --
img_1_data_stream_0_V_write_assign_proc : process(exitcond1_reg_607, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_1_data_stream_0_V_write <= ap_const_logic_1;
else
img_1_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_1_data_stream_1_V_din <=
p_val_1_1_reg_728 when (sel_tmp2_reg_738(0) = '1') else
p_val_1_2_reg_744;
-- img_1_data_stream_1_V_write assign process. --
img_1_data_stream_1_V_write_assign_proc : process(exitcond1_reg_607, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_1_data_stream_1_V_write <= ap_const_logic_1;
else
img_1_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_1_data_stream_2_V_din <= tmp_6_reg_749;
-- img_1_data_stream_2_V_write assign process. --
img_1_data_stream_2_V_write_assign_proc : process(exitcond1_reg_607, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_159, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond1_reg_607 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_159 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_1_data_stream_2_V_write <= ap_const_logic_1;
else
img_1_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_val_0_1_fu_427_p3 <=
buffer_val_0_load_scl_val_0_fu_421_p3 when (brmerge_fu_411_p2(0) = '1') else
buffer_val_0_load_1_reg_660;
p_val_0_2_fu_499_p3 <=
p_val_0_1_fu_427_p3 when (icmp_reg_616(0) = '1') else
scl_val_0_reg_624;
p_val_1_1_fu_460_p3 <=
buffer_val_1_load_scl_val_1_fu_454_p3 when (brmerge_1_fu_444_p2(0) = '1') else
buffer_val_1_load_1_reg_665;
p_val_1_2_fu_510_p3 <=
p_val_1_1_fu_460_p3 when (icmp_reg_616(0) = '1') else
scl_val_1_reg_630;
rev1_fu_353_p2 <= (ult1_fu_347_p2 xor ap_const_lv1_1);
rev2_fu_434_p2 <= (ult2_reg_697 xor ap_const_lv1_1);
rev3_fu_377_p2 <= (ult3_fu_371_p2 xor ap_const_lv1_1);
rev4_fu_467_p2 <= (ult4_reg_713 xor ap_const_lv1_1);
rev5_fu_483_p2 <= (ult5_reg_718 xor ap_const_lv1_1);
rev_fu_401_p2 <= (ult_reg_681 xor ap_const_lv1_1);
row_1_fu_298_p2 <= std_logic_vector(unsigned(row_reg_258) + unsigned(ap_const_lv11_1));
row_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(row_reg_258),12));
sel_tmp2_fu_505_p2 <= (icmp_reg_616 and brmerge_2_fu_477_p2);
sel_tmp9_fu_516_p3 <=
buffer_val_2_load_1_reg_670 when (icmp_reg_616(0) = '1') else
p_val_2_reg_636;
tmp_2_fu_285_p1 <= cols(12 - 1 downto 0);
tmp_3_fu_319_p4 <= col_phi_fu_273_p4(10 downto 1);
tmp_6_fu_521_p3 <=
buffer_val_2_load_p_val_2_fu_493_p3 when (sel_tmp2_fu_505_p2(0) = '1') else
sel_tmp9_fu_516_p3;
tmp_fu_281_p1 <= rows(12 - 1 downto 0);
ult1_fu_347_p2 <= "1" when (unsigned(img_0_data_stream_0_V_dout) < unsigned(buffer_val_0_q0)) else "0";
ult2_fu_365_p2 <= "1" when (unsigned(buffer_val_1_q1) < unsigned(buffer_val_1_q0)) else "0";
ult3_fu_371_p2 <= "1" when (unsigned(img_0_data_stream_1_V_dout) < unsigned(buffer_val_1_q0)) else "0";
ult4_fu_389_p2 <= "1" when (unsigned(buffer_val_2_q1) < unsigned(buffer_val_2_q0)) else "0";
ult5_fu_395_p2 <= "1" when (unsigned(img_0_data_stream_2_V_dout) < unsigned(buffer_val_2_q0)) else "0";
ult_fu_341_p2 <= "1" when (unsigned(buffer_val_0_q1) < unsigned(buffer_val_0_q0)) else "0";
end behav;
| gpl-3.0 | 19f7bf2117513b45b54b97634b37387e | 0.599486 | 2.58978 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_ise/hw/xps_proj/pcores/logicvc_v3_00_a/doc/logicvc_comp.vhd | 1 | 22,930 |
package logicbricks is
-- START COMPONENT
component logicvc is
generic (
-- Version generics
C_IP_LICENSE_TYPE : integer := 0; -- IP encryption type: 0 = source, 1 = evaluation, 2 = release, 3 = university evaluation
C_IP_MAJOR_REVISION : integer := 0; -- IP major revision: 0 - 31; vXX_yy_z
C_IP_MINOR_REVISION : integer := 0; -- IP minor revision: 0 - 31; vxx_YY_z
C_IP_PATCH_LEVEL : integer := 0; -- IP patch level: 0 - 25; vxx_yy_Z
C_IP_LICENSE_CHECK : integer := 0; -- IP license check: 0 = no, 1 = yes
C_IP_TIME_BEFORE_BREAK : integer := 0; -- IP time before break: 0 = infinite, 1 = 1h, 2 = 12h, 3 = 24h
C_FAMILY : string := "spartan6";
-- Video memory generics
C_VMEM_INTERFACE : integer := 0; -- Use PLB, XMB or AXI to access video memory: 0 - PLB, 1 - XMB, 2 - AXI
C_VMEM_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_VMEM_HIGHADDR : std_logic_vector := x"00000000";
C_MEM_BURST : integer := 4; -- Memory burst width; 4, 5 or 6. (4 means burst lasts 16 transfers), Used for XMB and AXI
C_MEM_BYTE_SWAP : integer := 0; -- Memory access byte swap: 0 - Do not swap, 1 - Swap
C_MEM_LITTLE_ENDIAN : integer := 1; -- Memory access endianness: 0 - Big endian, 1 - Little endian
C_INCREASE_FIFO : integer := 1; -- FIFO size multiplication factor: 1=1x, 2=2x, 4=4x, 8=8x
-- Master PLB generics
C_MPLB_NUM_MASTERS : integer := 8;
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 64;
C_MPLB_PRIORITY : integer := 3;
C_MPLB_SMALLEST_SLAVE : integer := 32;
-- XMB generics
C_XMB_DATA_BUS_WIDTH : integer := 64; -- XMB Memory interface data bus width
-- Master AXI generics
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_M_AXI_DATA_WIDTH : integer := 64;
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Registers generics
C_REGS_INTERFACE : integer := 0; -- Use OPB, PLB or AXI interface for registers: 0 - OPB, 1 - PLB, 2 - AXI
C_READABLE_REGS : integer := 1; -- Are logiCVC registers readable?: 0 - no, 1 - yes
C_REG_BYTE_SWAP : integer := 0; -- Registers access byte swap: 0 - Do not swap, 1 - Swap
-- OPB generics
C_REGS_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_REGS_HIGHADDR : std_logic_vector := x"00000000";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
-- Slave PLB generics
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 1;
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
-- AXI4-Lite Slave generics
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
-- Output format
C_PIXEL_DATA_WIDTH : integer := 24; -- Output data width: 12, 15, 16, 18 or 24
C_USE_VCLK2 : integer := 1; -- pix_clk rising edge will be in the middle of the DDR RGB data eye or synchronous if not used
C_ROW_STRIDE : integer := 1024; -- Row stride in number of pixels
C_XCOLOR : integer := 0;
C_USE_SIZE_POSITION : integer := 0; -- Use layer size, position and offset functionality: 0 - no, 1 - yes
C_DISPLAY_INTERFACE : integer := 0; -- Select output interface type: 0 - parallel only, 1 - ITU656, 2 - LVDS 4bit, 3 - camera link, 4 - LVDS 3bit, 5 - DVI
C_DISPLAY_COLOR_SPACE : integer := 0; -- Select output interface color space: 0 - RGB, 1 - YCbCr 4:2:2, 2 - YCbCr 4:4:4
C_LVDS_DATA_WIDTH : integer := 4; -- 3 or 4
C_VCLK_PERIOD : integer := 25000; -- vclk clock period in ps
-- Multilayer generics
C_NUM_OF_LAYERS : positive := 3; -- Number of logiCVC layers: 1, 2, 3, 4 or 5
C_LAYER_0_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_1_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha
C_LAYER_2_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_3_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha
C_LAYER_4_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr
C_LAYER_0_DATA_WIDTH : positive := 16; -- Layer 0 data width: 8, 16, 24 bit
C_LAYER_1_DATA_WIDTH : positive := 16; -- Layer 1 data width: 8, 16, 24 bit
C_LAYER_2_DATA_WIDTH : positive := 16; -- Layer 2 data width: 8, 16, 24 bit
C_LAYER_3_DATA_WIDTH : positive := 16; -- Layer 3 data width: 8, 16, 24 bit
C_LAYER_4_DATA_WIDTH : positive := 16; -- Layer 4 data width: 8, 16, 24 bit
C_LAYER_0_ALPHA_MODE : integer := 0; -- Layer 0 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_1_ALPHA_MODE : integer := 0; -- Layer 1 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_2_ALPHA_MODE : integer := 0; -- Layer 2 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_3_ALPHA_MODE : integer := 0; -- Layer 3 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_LAYER_4_ALPHA_MODE : integer := 0; -- Layer 4 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24
C_USE_BACKGROUND : integer := 0; -- configure last layer as background: 0 - no, 1 - yes
C_USE_XTREME_DSP : integer := 2; -- enable or disable use of DSP resources: 0 - no, 1 - yes, 2 - auto
C_USE_MULTIPLIER : integer := 2; -- control way in which multipliers in blender are implemented: 0 - lut, 1 - block, 2 - auto
C_LAYER_0_OFFSET : natural := 0; -- address offset for layer 0 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_1_OFFSET : natural := 2048; -- address offset for layer 1 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_2_OFFSET : natural := 4096; -- address offset for layer 2 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_3_OFFSET : natural := 6144; -- address offset for layer 3 in 2k steps for 16bpp and 1k steps for 8bpp
C_LAYER_4_OFFSET : natural := 8192; -- address offset for layer 4 in 2k steps for 16bpp and 1k steps for 8bpp
C_BUFFER_0_OFFSET : natural := 1024; -- address offset for layer 0 double buffer relative to LAYER_0_OFFSET
C_BUFFER_1_OFFSET : natural := 1024; -- address offset for layer 1 double buffer relative to LAYER_1_OFFSET
C_BUFFER_2_OFFSET : natural := 1024; -- address offset for layer 2 double buffer relative to LAYER_2_OFFSET
C_BUFFER_3_OFFSET : natural := 1024; -- address offset for layer 3 double buffer relative to LAYER_3_OFFSET
C_BUFFER_4_OFFSET : natural := 1024; -- address offset for layer 4 double buffer relative to LAYER_4_OFFSET
-- Extern parallel input generics
C_USE_E_PARALLEL_INPUT : integer := 0; -- Syncronize logiCVC to external parallel input and use data as one layer: 0 - no, 1 - yes
C_USE_E_VCLK_BUFGMUX : integer := 1; -- Use BUFGMUX for switching video clock to e_vclk, else use vclk
C_E_LAYER : integer := 0; -- External parallel input layer: 0, 1, 2, 3, 4
C_E_DATA_WIDTH : integer := 24 -- External parallel input data width: 8, 16, 24 bit
);
port(
rst : in std_logic; -- Global reset
mclk : in std_logic; -- Memory clock
vclk : in std_logic; -- Video clock
vclk2 : in std_logic; -- Video clock x2
itu_clk_in : in std_logic; -- It has to be 27 MHz and synchronous to vclk
lvds_clk : in std_logic; -- lvds clock is 3.5x video clock
lvds_clkn : in std_logic; -- Inverted lvds_clk
-- Xylon Memory Bus (XMB)
mem_req : out std_logic;
mem_wr : out std_logic;
mem_ack : in std_logic := '0';
mem_addr : out std_logic_vector(31 downto 0);
mem_data : out std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0);
mem_data_be : out std_logic_vector(C_XMB_DATA_BUS_WIDTH / 8 - 1 downto 0);
mem_wrack : in std_logic := '0';
mem_burst : out std_logic_vector(C_MEM_BURST - 1 downto 0);
mem_data_valid : in std_logic := '0';
mem_data_in : in std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0) := (others => '0');
-- PLB --------------
-- Master
mplb_rst : in std_logic;
plb_maddrack : in std_logic;
plb_mrearbitrate : in std_logic;
plb_mssize : in std_logic_vector(0 to 1);
plb_mbusy : in std_logic;
plb_mrderr : in std_logic;
plb_mwrerr : in std_logic;
plb_mtimeout : in std_logic;
plb_mirq : in std_logic;
m_request : out std_logic;
m_priority : out std_logic_vector(0 to 1);
m_buslock : out std_logic;
m_rnw : out std_logic;
m_be : out std_logic_vector(0 to (C_MPLB_DWIDTH / 8) - 1);
m_size : out std_logic_vector(0 to 3);
m_type : out std_logic_vector(0 to 2);
m_msize : out std_logic_vector(0 to 1);
m_tattribute : out std_logic_vector(0 to 15);
m_lockerr : out std_logic;
m_abort : out std_logic;
m_abus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1));
m_uabus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1));
plb_mwrdack : in std_logic;
plb_mwrbterm : in std_logic;
m_wrburst : out std_logic;
m_wrdbus : out std_logic_vector(0 to (C_MPLB_DWIDTH - 1));
plb_mrddack : in std_logic;
plb_mrdbterm : in std_logic;
plb_mrdwdaddr : in std_logic_vector(0 to 3);
plb_mrddbus : in std_logic_vector(0 to (C_MPLB_DWIDTH - 1));
m_rdburst : out std_logic;
-- AXI --------------
-- Master
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH / 8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
----------------------
-- OPB --------------
-- Slave
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH / 8 - 1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1);
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
----------------------
-- PLB --------------
-- Slave
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH - 1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH / 8 - 1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_tattribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH - 1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH - 1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1);
----------------------
-- AXI4-Lite --------
-- Slave
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
----------------------
-- Video Outputs --------------
pix_clk_i : in std_logic; -- Pixel clock
pix_clk_o : out std_logic; -- Pixel clock
pix_clk_t : out std_logic; -- Pixel clock
pix_clk_n_i : in std_logic; -- Pixel clock inverted
pix_clk_n_o : out std_logic; -- Pixel clock inverted
pix_clk_n_t : out std_logic; -- Pixel clock inverted
d_pix_i : in std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus
d_pix_o : out std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus
d_pix_t : out std_logic; -- Pixel data bus
hsync_i : in std_logic; -- Hsync
hsync_o : out std_logic; -- Hsync
hsync_t : out std_logic; -- Hsync
vsync_i : in std_logic; -- Vsync
vsync_o : out std_logic; -- Vsync
vsync_t : out std_logic; -- Vsync
blank_i : in std_logic; -- Blank
blank_o : out std_logic; -- Blank
blank_t : out std_logic; -- Blank
itu656_clk_o : out std_logic; -- ITU656 clock output
itu656_data_o : out std_logic_vector(7 downto 0); -- ITU656 data output
lvds_data_out_p : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, positive
lvds_data_out_n : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, negative
lvds_clk_out_p : out std_logic; -- lvds clk, positive
lvds_clk_out_n : out std_logic; -- lvds clk, negative
pllvclk_locked : in std_logic; -- PLL_BASE LOCKED (spartan6, LVDS clk gen)
dvi_clk_p : out std_logic; -- DVI clock, positive
dvi_clk_n : out std_logic; -- DVI clock, negative
dvi_data_p : out std_logic_vector(2 downto 0); -- DVI data, positive
dvi_data_n : out std_logic_vector(2 downto 0); -- DVI data, negative
----------------------
-- External parallel input --------------
e_vclk : in std_logic; -- External video clock
e_vsync : in std_logic; -- External vsync
e_hsync : in std_logic; -- External hsync
e_blank : in std_logic; -- External blank
e_data : in std_logic_vector(C_E_DATA_WIDTH - 1 downto 0); -- External data
e_video_present : in std_logic; -- External video present flag
----------------------
-- Other --------------
e_curr_vbuff : in std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Current external stream vbuffer
e_next_vbuff : out std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Next external stream vbuffer to write to
e_sw_vbuff : in std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Switch video buffers from external source
e_sw_grant : out std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Video buffers switch req granted
vcdivsel : out std_logic_vector(1 downto 0); -- vclk div select bits
vclksel : out std_logic_vector(2 downto 0); -- vclk select bits
en_vdd : out std_logic; -- vdd enable
en_blight : out std_logic; -- backlight enable
v_en : out std_logic; -- Enable display control/data signals
en_vee : out std_logic; -- vee enable
interrupt : out std_logic -- logiCVC interrupt signal, level sensitive, high active
);
end component;
end logicbricks;
| gpl-3.0 | 8401381d27bcbb1e092e55e94ffd8307 | 0.477191 | 3.73879 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/game_over/simulation/game_over_tb.vhd | 1 | 4,361 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: game_over_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY game_over_tb IS
END ENTITY;
ARCHITECTURE game_over_tb_ARCH OF game_over_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
game_over_synth_inst:ENTITY work.game_over_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | cbf1c1d0d8b8a830a73ec550143d30f2 | 0.619583 | 4.629512 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-cpci-xc2v6000/testbench.vhd | 1 | 19,150 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := 'L';
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to 1);
can_rxd : in std_logic_vector(0 to 1);
can_stb : out std_logic_vector(0 to 1);
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal gtx_clk : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to 1);
signal can_rxd : std_logic_vector(0 to 1);
signal can_stb : std_logic_vector(0 to 1);
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => '1');
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_rxd, spw_rxdn, spw_rxs, spw_rxsn,
spw_txd, spw_txdn, spw_txs, spw_txsn);
-- optional sdram
sd0 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 12c0ed14a007a9f163086fb1c4602f3f | 0.568982 | 3.038236 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ahb2avl_async.vhd | 1 | 5,671 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
end;
| gpl-2.0 | a508829e566544e37fe4e673029fb8bc | 0.59478 | 3.924567 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_data_stream_0_V.vhd | 2 | 4,629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_data_stream_0_V_shiftReg;
architecture rtl of FIFO_image_filter_p_src_data_stream_0_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_data_stream_0_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_data_stream_0_V is
component FIFO_image_filter_p_src_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_data_stream_0_V_shiftReg : FIFO_image_filter_p_src_data_stream_0_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 3b3269b788d2112b5acdb7f5e67b62da | 0.537697 | 3.449329 | false | false | false | false |
laurocruz/snakes_vhdl | src/snake_lib/make_map.vhd | 1 | 2,607 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
-- controlador do mapa do jogo
ENTITY make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock : IN STD_LOGIC;
-- reseta o jogo
reset : IN STD_LOGIC;
-- aumento do tamanho
eaten : IN STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
-- direcao para onde a cobra esta se movendo
-- 11 : cima
-- 00 : baixo
-- 10 : esquerda
-- 01 : direita
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- posicoes da cobra no mapa
snake_body : OUT int_array);
END make_map;
ARCHITECTURE Behavior OF make_map IS
-- Vetor de estruturas de dois inteiros que representam a posição de cada parte da cobra (l,c)
--TYPE snake_body IS array (0 to N*M-1) OF INTEGER RANGE 0 TO N*M-1;
--SIGNAL snake : snake_body;
SIGNAL snake : int_array;
SIGNAL dir_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
snake_body <= snake;
dir_s <= dir;
PROCESS (clock, reset, eaten)
VARIABLE j : INTEGER RANGE 0 TO N*M;
VARIABLE DIF : INTEGER RANGE 0 TO M;
--VARIABLE index : INTEGER RANGE 0 TO N*M;
--VARIABLE map_s : STD_LOGIC_VECTOR(0 TO N*M-1);
BEGIN
IF (reset = '1') THEN
FOR i in 0 to INITIAL_SIZE-1 LOOP
snake(i) <= (N/2) + (i+M/2)*M;
END LOOP;
FOR i in INITIAL_SIZE to N*M-1 LOOP
snake(i) <= -1;
END LOOP;
ELSIF (eaten = '1') THEN
DIF := snake(snake_size-1) - snake(snake_size-2);
snake(snake_size) <= snake(snake_size-1) + DIF;
ELSIF (clock'EVENT and clock = '1') THEN
j := 0;
WHILE (j+1 < M*N and not(snake(j+1) = -1)) LOOP
snake(j+1) <= snake(j);
j := j + 1;
END LOOP;
--FOR i IN 0 TO snake_size-2 LOOP
-- snake(i+1) <= snake(i);
--END LOOP;
IF (dir_s = "00") THEN
snake(0) <= snake(0) + M;
ELSIF (dir_s = "01") THEN
snake(0) <= snake(0) + 1;
ELSIF (dir_s = "10") THEN
snake(0) <= snake(0) - 1;
ELSE
snake(0) <= snake(0) - M;
END IF;
--map_s := (OTHERS => '0');
--j := 0;
--WHILE (j < M*N and not(snake(j) = -1)) LOOP
-- index := snake(j);
-- map_s(index) := '1';
-- j := j + 1;
--END LOOP;
END IF;
--gmap <= map_s;
END PROCESS;
END Behavior;
| mit | afd52d16422faa9ad2870e4a05a62c08 | 0.508065 | 2.955732 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-nuhorizons-3s1500/testbench.vhd | 1 | 13,633 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8+8*CFG_MCTRL_RAM16BIT; -- rom data width (8/16)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal flash_d : std_logic_vector(15 downto 0);
signal romsn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal ereset : std_logic;
signal led : std_logic_vector(8 downto 1);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal ba : std_logic_vector(3 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal pb_sw : std_logic_vector(4 downto 1);
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_en : std_ulogic;
signal lcd_backl: std_ulogic;
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal smsc_addr : std_logic_vector(21 downto 0);
signal smsc_data : std_logic_vector(31 downto 0);
signal smsc_nbe : std_logic_vector(3 downto 0);
signal smsc_resetn : std_ulogic;
signal smsc_ardy : std_ulogic;
signal smsc_intr : std_ulogic;
signal smsc_nldev : std_ulogic;
signal smsc_nrd : std_ulogic;
signal smsc_nwr : std_ulogic;
signal smsc_ncs : std_ulogic;
signal smsc_aen : std_ulogic;
signal smsc_lclk : std_ulogic;
signal smsc_wnr : std_ulogic;
signal smsc_rdyrtn : std_ulogic;
signal smsc_cycle : std_ulogic;
signal smsc_nads : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1'; error <= led(8); sa(14 downto 12) <= "000";
pb_sw <= rst & "00" & dsubre;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (pb_sw, clk, led, address(21 downto 1), flash_d,
sa(11 downto 0), sd, ba, sddqm, sdclk, sdcke, sdcsn, sdwen, sdrasn,
sdcasn, txd1, rxd1, open, gnd, dsutx, dsurx, open, gnd,
oen, writen, romsn, open, vcc, open, open,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, emdc, gnd, ereset, gpio,
-- lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_backl,
can_txd, can_rxd,
smsc_addr(14 downto 0), smsc_data, smsc_nbe, smsc_resetn, smsc_ardy,-- smsc_intr,
smsc_nldev, smsc_nrd, smsc_nwr, smsc_ncs, smsc_aen, smsc_lclk,
smsc_wnr, smsc_rdyrtn, smsc_cycle, smsc_nads);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => ba(1 downto 0), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => ba(3 downto 2), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
rom8 : if romwidth /= 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= flash_d(15);
end generate;
rom16 : if romwidth = 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= '0';
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
flash_d <= buskeep(flash_d) after 5 ns;
sd <= buskeep(sd) after 5 ns;
smsc_data <= buskeep(smsc_data) after 5 ns;
smsc_addr(21 downto 15) <= (others => '0');
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), smsc_data,
smsc_ncs, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | a6ef3c9b1ea70705254894133c477b6a | 0.591946 | 3.045119 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-3s1500/leon3mp.vhd | 1 | 26,269 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design for AVNET Spartan3 Evaluation Board
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.can.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
horiz_sync : out std_logic;
vert_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant mahbmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_PCI+
CFG_SVGA_ENABLE + CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(23 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal abus : std_logic_vector(17 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clk, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_logic;
signal pllref, errorn, pci_rst : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal dac_clk, clk25, clk_66mhzl, pci_lclk : std_logic;
signal can_ltx, can_lrx : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk : signal is true;
attribute syn_preserve of clk : signal is true;
attribute keep of clk : signal is true;
signal switchesl : std_logic_vector(5 downto 0);
constant padlevel : integer := 0;
constant IOAEN : integer := CFG_CAN;
constant BOARD_FREQ : integer := 66667; -- input frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ * CFG_CLKMUL) / CFG_CLKDIV;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
---------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0'); pllref <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, 66000)
port map (clk_66mhzl, pci_lclk, clk, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 8)
port map (sdclk, sdclkl);
clk_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_66mhz, clk_66mhzl);
clk2_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_socket, open);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
rst0 : rstgen generic map (acthigh => 1)
port map (switchesl(4), clk, cgo.clklock, rstn, rstraw);
flash_rst_l_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_rst_l, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => mahbmax, nahbs => 8, ioen => IOAEN)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
dsui.break <= switchesl(5);
dsui.enable <= '1';
dsuact_pad : outpad generic map (tech => padtech, level => padlevel)
port map (leds(1), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
dcompads : if CFG_AHB_UART = 1 generate
dsurx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, duo.txd);
u1i.rxd <= '1';
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.mctrl_avnet generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
pageburst => CFG_MCTRL_PAGE, avnetmezz => mezz)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- no SDRAM controller
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (casn, sdo.casn);
-- sddqm_pad : outpadv generic map (width =>4, tech => padtech)
-- port map (sddqm, sdo.dqm);
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, vcc(1 downto 0));
end generate;
mgpads : if CFG_MCTRL_LEON2 /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (level => padlevel, width => 25, tech => padtech)
port map (sram_a, memo.address(24 downto 0));
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, memo.ramsn(1 downto 0));
flash_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_cs_l, memo.romsn(0));
oen_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_oe_l, memo.oen);
iosn_pad : outpad generic map (level => padlevel, tech => padtech)
port map (iosn, memo.iosn);
wri_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_we_l, memo.writen);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (level => padlevel, tech => padtech, width => 8)
port map (sram_dq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
ben_pad : outpadv generic map (level => padlevel, width => 4, tech => padtech)
port map (sram_ben_l, memo.mben);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1pads : if CFG_AHB_UART = 0 generate
rx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, u1i.rxd);
tx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, u1o.txd);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clk, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clk, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clk, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbclk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbdata, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (msclk,mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (msdata, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clk, clk25, apbi, apbo(6), vgao);
vgaclk0 : entity techmap.clkmul_virtex2 generic map (3, 8) -- 25 MHz video clock
port map (rstn, clk, dac_clk, open);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 39722, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 5)
port map(rstn, clk, clk25, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
clk25 <= not dac_clk;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
video_clk_pad : inpad generic map (tech => padtech)
port map (video_clk, dac_clk);
blank_pad : outpad generic map (tech => padtech)
port map (blank, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (comp_sync, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vert_sync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (horiz_sync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(23 downto 16), vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(15 downto 8), vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(7 downto 0), vgao.video_out_b);
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clk, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 9, paddr => 9, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clk, pciclk, pcii, pcio, apbi, apbo(9),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 9, apbaddr => 9, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clk, pciclk, pcii, pcio, apbo(9), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clk, pciclk, pcii, apbi, apbo(8));
end generate;
end generate;
pcipads0 : pcipads
generic map (padtech => padtech, noreset => 1, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 0) generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech, level => padlevel)
port map (phy_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_txck, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_rxck, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxer, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => padlevel)
port map ( phy_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_mdc, etho.mdc);
phy_reset_pad : iodpad generic map (tech => padtech, level => padlevel)
port map (phy_reset_l, rstn, pci_rst);
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clk, ahbsi, ahbso(6), can_lrx, can_ltx );
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clk, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Misc ----------------------------------------------------------
-----------------------------------------------------------------------
errorn <= not dbgo(0).error;
led0_pad : outpad generic map (level => padlevel, tech => padtech)
port map (leds(0), errorn);
led2_7_pad : outpadv generic map (level => padlevel, width => 6, tech => padtech)
port map (leds(7 downto 2), gnd(5 downto 0));
disp_seg1_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg1, gnd(7 downto 0));
disp_seg2_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg2, gnd(7 downto 0));
switche_pad : inpadv generic map (tech => padtech, level => padlevel, width => 6)
port map (switches, switchesl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+ CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nam2 : if CFG_PCI > 1 generate
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG-1+CFG_SVGA_ENABLE) <= ahbm_none;
end generate;
nap0 : for i in 12 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Spartan3-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | ae2f0752b35c0665c97991a184f71a9f | 0.582017 | 3.421334 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de2-115/leon3mp.vhd | 1 | 26,071 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clock_50 : in std_logic;
sma_clkout : out std_ulogic;
errorn : out std_logic;
fl_addr : out std_logic_vector(22 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dq : inout std_logic_vector(31 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_dqm : out std_logic_vector (3 downto 0); -- sdram dqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic;
dsuact : out std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_wp_n : out std_logic;
fl_ce_n : out std_logic;
-- gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpio : inout std_logic_vector(35 downto 0); -- I/O port
enet0_mdio : inout std_logic; -- ethernet PHY interface
enet0_gtx_clk : in std_logic;
enet0_rx_clk : in std_logic;
enet0_tx_clk : in std_logic;
enet0_rx_data: in std_logic_vector(3 downto 0);
enet0_rx_dv : in std_logic;
enet0_rx_er : in std_logic;
enet0_rx_col : in std_logic;
enet0_rx_crs : in std_logic;
enet0_int_n : in std_logic;
enet0_rst_n : out std_logic;
enet0_tx_data: out std_logic_vector(3 downto 0);
enet0_tx_en : out std_logic;
enet0_tx_er : out std_logic;
enet0_mdc : out std_logic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1);
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal dsubren : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ, clk2xen => 1)
port map (clkin => clock_50, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => sma_clkout, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
-- dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (fl_addr, memo.address(22 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen);
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn);
fl_wp_pad : outpad generic map (tech => padtech)
port map (fl_wp_n, vcc(0));
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 13)
port map (dram_addr, memo.sa(12 downto 0));
ba_pad : outpadv generic map (width => 2)
port map (dram_ba, memo.sa(14 downto 13));
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (dram_dq(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (dram_dqm, sdo.dqm(3 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, vcc(0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd; u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when sw(0) = '1' else duo.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : iopad generic map (tech => padtech)
port map (gpio(35), spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (gpio(34), spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (gpio(33), spio.sck, spio.sckoen, spii.sck);
slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(32), slvsel(0), gnd(0), open);
end generate spic;
spibridge : if CFG_SPI2AHB /= 0 generate -- SPI to AHB bridge
withapb : if CFG_SPI2AHB_APB /= 0 generate
spi2ahb0 : spi2ahb_apb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
resen => CFG_SPI2AHB_RESEN, pindex => 11, paddr => 11, pmask => 16#fff#,
pirq => 11, filter => CFG_SPI2AHB_FILTER, cpol => CFG_SPI2AHB_CPOL,
cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi, apbo(11), spislvi, spislvo);
end generate;
woapb : if CFG_SPI2AHB_APB = 0 generate
spi2ahb0 : spi2ahb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
filter => CFG_SPI2AHB_FILTER,
cpol => CFG_SPI2AHB_CPOL, cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
spislvi, spislvo);
end generate;
spislv_miso_pad : iopad generic map (tech => padtech)
port map (gpio(31), spislvo.miso, spislvo.misooen, spislvi.miso);
spislvl_mosi_pad : iopad generic map (tech => padtech)
port map (gpio(30), spislvo.mosi, spislvo.mosioen, spislvi.mosi);
spislv_sck_pad : iopad generic map (tech => padtech)
port map (gpio(29), spislvo.sck, spislvo.sckoen, spislvi.sck);
spislv_slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(28), gnd(0), vcc(0), spislvi.spisel);
end generate;
nospibridge : if CFG_SPI2AHB = 0 or CFG_SPI2AHB_APB = 0 generate
apbo(11) <= apb_none;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 16,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (enet0_gtx_clk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (enet0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (enet0_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (enet0_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (enet0_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (enet0_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (enet0_rx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (enet0_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (enet0_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (enet0_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (enet0_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (enet0_mdc, etho.mdc);
eth0_rst_pad : odpad generic map (tech => padtech)
port map (enet0_rst_n, rstn);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerAsic DE2_115 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | e81010a8f1a28a3cd8e3a6a467d9191a | 0.56933 | 3.459528 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc3s-1500/testbench.vhd | 1 | 16,236 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk3 : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal read : std_ulogic;
signal iosn : std_ulogic;
signal bexcn : std_ulogic;
signal brdyn : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal wdogn : std_logic;
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0);
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal pllref : std_ulogic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal errorn : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt : std_logic_vector(7 downto 0);
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal eth_macclk : std_ulogic := '0';
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal clk3 : std_ulogic := '0';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_ulogic := '0';
signal usb_d : std_logic_vector(15 downto 0);
signal usb_linestate : std_logic_vector(1 downto 0);
signal usb_opmode : std_logic_vector(1 downto 0);
signal usb_reset : std_ulogic;
signal usb_rxactive : std_ulogic;
signal usb_rxerror : std_ulogic;
signal usb_rxvalid : std_ulogic;
signal usb_suspend : std_ulogic;
signal usb_termsel : std_ulogic;
signal usb_txready : std_ulogic;
signal usb_txvalid : std_ulogic;
signal usb_validh : std_logic;
signal usb_xcvrsel : std_ulogic;
signal usb_vbus : std_ulogic;
signal rhvalid : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk3 <= not clk3 after 20 ns;
rst <= dsurst and wdogn;
dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0'; pllref <= sdclk;
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
usb_clkout <= not usb_clkout after 8.33 ns; -- ~60MHz
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk3, pllref, errorn, wdogn, address(27 downto 0), data,
ramsn, ramoen, rwen, oen, writen, read, iosn, bexcn, brdyn, romsn,
sdclk, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsuen, dsubre, dsuact,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, emdint,
etxd, etx_en, etx_er, emdc, ps2clk, ps2data, vid_clock, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b, spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn, usb_clkout,
usb_d, usb_linestate, usb_opmode, usb_reset, usb_rxactive, usb_rxerror,
usb_rxvalid, usb_suspend, usb_termsel, usb_txready, usb_txvalid, usb_validh,
usb_xcvrsel, usb_vbus
);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn(0),
writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, errorn, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | 456e6f19334e203846d3dff024196a53 | 0.587645 | 3.038742 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pci_mt.vhd | 1 | 28,846 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbreadword(ahbsi.hwdata)(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata(31 downto 0); v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= ahbdrivedata(r2.hrdata);
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbreadword(ahbsi.hwdata);
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
| gpl-2.0 | a0aade0367da5dc8ec3a8464ebf7f985 | 0.559003 | 2.923186 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/pcitrace/pcitrace.vhd | 1 | 7,716 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32, sepclk => 1)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16, sepclk => 1)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
| gpl-2.0 | 7ae560b08ee462505ecd501da85a4bba | 0.57776 | 3.335927 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/esa/memoryctrl/memoryctrl.vhd | 1 | 2,669 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
| gpl-2.0 | 65e3d6fcbdf13c82464e1995c4dea5ae | 0.553391 | 3.936578 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/mmu_dcache.vhd | 1 | 66,774 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_dcache
-- File: mmu_dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libmmu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end;
architecture rtl of mmu_dcache is
constant M_EN : boolean := (mmuen = 1);
constant DSNOOP2 : integer := dsnoop mod 4;
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant M_TLB_TYPE : integer range 0 to 1 := -- either split or combined
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(1, 2));
constant M_TLB_FASTWRITE : integer range 0 to 3 := -- fast writebuffer
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(2, 2));
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(ilramstart, 8);
constant DIR_BITS : integer := log2x(DSETS);
constant bend : std_logic_vector(4 downto 2) := "101";
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory,
sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
smask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, rburst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
efaddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- error flush address
dstate : dstatetype; -- FSM vector
hit, valid : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
bmexc : std_ulogic; -- latched mexc from burst read
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
flushl2 : std_ulogic;
tadj, dadj, sadj : std_logic_vector(1 downto 0);
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
dlock : std_logic;
su : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
reqst : std_logic;
set : integer range 0 to DSETS-1;
noflush : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag address
mask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
snhit : std_logic_vector(0 to MAXSETS-1);
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0);
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else
xset(0) := xlru(0);
end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset: std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'),
data1 => (others => '0'),
data2 => (others => '0'),
size => (others => '0'),
asi => (others => '0'),
read => '0',
lock => '0',
smask => (others => '0')
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : dcache_control_type := (
read => '0',
size => (others => '0'),
req => '0',
burst => '0',
rburst => '0',
holdn => '1',
nomds => '0',
stpend => '0',
xaddress => (others => '0'),
paddress => (others => '0'),
faddr => (others => '0'),
efaddr => (others => '0'),
dstate => idle,
hit => '0',
valid => '0',
flush => '0',
flush2 => '1',
mexc => '0',
bmexc => '0',
wb => write_buffer_none,
asi => (others => '0'),
icenable => '0',
rndcnt => (others => '0'),
setrepl => (others => '0'),
lrr => '0',
dsuset => (others => '0'),
lock => '0',
lramrd => '0',
ilramen => '0',
cctrl => cctrl_none,
cctrlwr => '0',
flushl2 => '0',
tadj => (others => '0'),
dadj => (others => '0'),
sadj => (others => '0'),
mmctrl1 => mmctrl_type1_none,
mmctrl1wr => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
vaddr => (others => '0'),
ready => '0',
wbinit => '0',
cache => '0',
dlock => '0',
su => '0',
trans_op => '0',
flush_op => '0',
diag_op => '0',
reqst => '0',
set => 0,
noflush => '0'
);
constant SRES : snoop_reg_type := (
snoop => '0',
addr => (others => '0'),
mask => (others => '0'),
snhit => (others => '0')
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco, ahbso)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable flushaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set, eset : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validraw : std_logic_vector(0 to DSETS-1);
variable validv, hitv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe, snhit : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable lrusetval: std_logic_vector(SETBITS-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable cache : std_ulogic;
variable ctx : ctxdatatype;
variable flushl : std_ulogic;
variable miscdata : std_logic_vector(31 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable su : std_logic;
variable mmuisdis : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
variable pagesize : integer range 0 to 3;
begin
-- init local variables
v := r; vs := rs; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; v.flush2 := r.flush;
snhit := (others => '0');
pagesize := MMU_getpagesize(mmupgsz,r.mmctrl1);
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
v.mmctrl1wr := '0';
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0;
vs.snoop := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
flushaddr := r.xaddress(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); hitv := (others => '0'); cache := '0';
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
ctx := (others => (others => '0'));
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
v.flushl2 := dci.flushl and not r.flush;
newptag := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP2 /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and (not mcdo.bg or r.mmctrl1.e)) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
if (r.mmctrl1.e = '1') and (mcdo.bg = '1') then vs.mask := r.wb.smask;
else vs.mask := (others => '1'); end if;
end if;
if DSNOOP /= 0 then
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
end if;
for i in DSETS-1 downto 0 loop
if ((rs.snoop and not (r.flush or r.flush2)) = '1') then
if (DSNOOP2 /= 0) and (rs.mask(i) = '1') and
((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW))
)
then
if DSNOOPSEP then flushaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
else snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); end if;
snoopwe := '1'; snoopset := i; snhit(i) := '1';
end if;
end if;
end loop;
end if;
vs.snhit := snhit; -- not needed, debug only
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read and not r.dlock;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read and not dci.lock;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
if (dsnoop = 6) and (r.cctrl.dsnoop = '0') then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
senable := enable;
end if;
lrusetval := lru_set(rl.lru(conv_integer(maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- generate cache hit and valid bits
if (r.mmctrl1.e = '0') then hcache := ahb_slv_dec_cache(dci.maddress, ahbso, cached);
else hcache := '1'; end if;
forcemiss := (not dci.asi(3)) or dci.lock;
if (M_EN and (dci.asi(4 downto 0) = ASI_MMU_BP)) or (r.cctrl.dcs(0) = '0') or
((r.flush or r.flush2) = '1')
then hcache := '0'; end if;
hit := '0'; set := 0;
for i in DSETS-1 downto 0 loop
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := '1'; end if;
validv(i) := hcache and hitv(i) and (not r.flush) and (not r.flush2) and dcramov.tag(i)(dlinesize-1);
validraw(i) := dcramov.tag(i)(dlinesize-1);
end loop;
if drepl = dir then
hit := hitv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1))) and not r.flush and (not r.flush2);
valid := validv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1)));
else
hit := orv(hitv) and not r.flush and (not r.flush2);
valid := orv(validv);
end if;
-- force cache miss if mmu-enabled but off or BYPASS, or on flush
if ((M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP)) or (r.cctrl.dcs(0) = '0') or ((r.flush or r.flush2) = '1')
then hit := '0'; end if;
if DSETS > 1 then
if drepl = dir then
set := conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1));
else
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then set := i; end if;
end loop;
end if;
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
v.su := dci.msu; v.set := set;
v.valid := valid; v.dlock := dci.lock;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(LINE_HIGH downto 2) := r.wb.addr(LINE_HIGH downto 2) + 1;
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (r.cctrlwr and not dci.nullify) = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.noflush := dci.maddress(30);
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
if (memtech = rhlib18t) and (r.xaddress(7 downto 2) = "000001") and (dci.read = '0') then
v.tadj := dci.maddress(5 downto 4);
v.sadj := dci.maddress(3 downto 2);
v.dadj := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
v.nomds := r.nomds and not eholdn; v.bmexc := '0';
if ((r.reqst = '0') and (r.stpend = '0')) or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock and not dci.nullify and ico.hold;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and
((M_TLB_FASTWRITE /= 0) or ((dci.enaddr and eholdn and dci.lock and not dci.read) = '1')))
then
if (dci.enaddr and eholdn and dci.lock and not dci.read) = '1' then -- skip address translation on store in LDST
v.wb.addr := r.wb.addr(31 downto 8) & dci.maddress(7 downto 0);
newptag := r.wb.addr(TAG_HIGH downto TAG_LOW);
else
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (dci.read and hcache) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => if M_EN then rdatasel := dctx; end if;
when ASI_MMUREGS => if M_EN then rdatasel := misc; end if;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
v.cctrlwr := not dci.read and not (dci.dsuen and not dci.eenaddr);
when ASI_MMUREGS =>
if M_EN then
if (dsu = 0) or dci.dsuen = '0' then
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
end if;
end if;
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := asi_idtag; v.ilramen := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') then -- No access on flush
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if DSNOOPSEP then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if dci.read = '0' then iflush := '1'; end if;
if M_EN then
if dci.read = '0' then
flush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
v.rburst := hcache; -- and not forcemiss;
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if not ((hit and valid and not forcemiss) = '1') then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := hcache;
if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
-- cache disabled if mmu-enabled but off or BYPASS
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then
v.req := '1'; v.burst := v.rburst;
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.wbinit := '1'; -- wb init in idle
v.burst := v.rburst;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
cache := '1';
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := dblwrite; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1'))
then -- wait for store queue
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0'; v.wb.read := r.wb.read;
end if;
else
-- ## mmu case > false and
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and
(((mmudco.wbtransdata.accexc = '0') and (M_TLB_FASTWRITE /= 0)) or (dci.lock = '1'))
then
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
-- ## < mmu case
end if;
end if;
if (hit and valid) = '1' then -- write hit
dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
eset := set;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (andv(validraw) = '0') and (drepl /= dir) and false then
for i in DSETS-1 downto 0 loop
if validraw(i) = '0' then eset := i; end if;
end loop;
v.setrepl := conv_std_logic_vector(eset, SETBITS);
elsif ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := dci.maddress(OFFSET_HIGH+log2x(DSETS) downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lrusetval;
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
v.rburst := r.rburst and v.cache;
if r.wbinit = '1' then
v.wb.addr := v.paddress; --mmudco.transdata.data;
v.req := '1';
v.burst := v.rburst;
if v.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
if drepl=lru and mcdo.ready='0' and r.hit='0' then
v.setrepl := lrusetval;
end if;
taddr := r.wb.addr(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if (r.rburst) = '1' then
if (mcdo.grant = '1') and (r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW))
and not ((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0'))
then
v.burst := '0';
else v.burst := r.burst; end if;
end if;
if mcdo.ready = '1' then
if (r.cache or r.hit) = '0' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
else
if r.wb.addr(LINE_HIGH downto LINE_LOW) = r.xaddress(LINE_HIGH downto LINE_LOW) then
mds := '0';
end if;
end if;
dwrite := r.cache and r.cctrl.dcs(1); rdatasel := memory;
mexc := mcdo.mexc;
v.bmexc := r.bmexc or mcdo.mexc or dci.flushl;
if r.req = '0' then
twrite := r.cache and r.cctrl.dcs(1); tagclear := v.bmexc;
if (((dci.enaddr and not mds) = '1') or (dci.flushl = '1') or ((dci.enaddr and twrite) = '1'))
and ((r.cctrl.dcs(0) = '1') or (dlram = 1))
then v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; v.holdn := '1'; end if;
else v.nomds := not r.cache; end if;
tpwrite := twrite;
end if;
v.mexc := mcdo.mexc and not r.rburst; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.wb.addr := paddress;
v.wb.size := r.size;
v.burst := r.rburst;
if r.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
if (r.flushl2 and dci.enaddr) = '1' then
v.holdn := '0';
else
v.dstate := idle;
end if;
when dblwrite => -- second part of double store cycle
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if r.hit = '1' then dwrite := r.valid; end if;
v.wb.data2 := dci.edata;
end if;
if (dci.flushl and ico.hold) = '1' then
v.dstate := loadpend; v.holdn := '0';
elsif ico.hold = '0' then v.reqst := '0';
else v.dstate := idle; end if;
when asi_idtag => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; v.ilramen := '0';
if (dsu = 0) or ((dsu = 1) and (dci.dsuen = '0')) then
mds := not r.read;
end if;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
if (dci.nullify = '0')
then
v.req := '1'; v.stpend := '1';
else v.reqst := '1'; end if;
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
if (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := r.valid;
end if;
end if;
end if;
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (
(dci.lock = '1')) and (dci.nullify = '1') then
v.dstate := idle; v.wb.lock := '0';
elsif ((v.ready or (mcdo.ready and not r.req)) = '1') or (
(dci.lock = '1')) then -- store queue emptied
if (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := r.valid;
end if;
v.dstate := idle;
v.burst := r.size(1) and r.size(0);
if (dci.nullify = '0') then v.reqst := '1'; end if;
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
v.wb.smask := (others => '1');
if r.hit = '1' then v.wb.smask(r.set) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
v.req := v.req or v.reqst; v.stpend := v.stpend or v.reqst; v.reqst := '0';
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if DSNOOPSEP then snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag; senable := (others => '1');
when ASI_DDATA =>
if M_EN then
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
end if;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
when ASI_MMUREGS =>
rdatasel := misc;
when others =>
end case;
end if;
-- read
if M_EN then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0001";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(MMCTRL_TLBSEP) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
miscdata(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D) := conv_std_logic_vector(pagesize,2); -- r.mmctrl1.pagesize;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
end if;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
if M_EN then set := 0; rdatav(0) := miscdata; end if;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0;
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" =>
rdatav(0)(30) := r.noflush;
rdatav(0)(23) := r.cctrl.dsnoop;
if dsnoop > 4 then rdatav(0)(17) := '1'; end if;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "01" =>
rdatav(0)(7 downto 0) := "00" & r.tadj & r.sadj & r.dadj;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, mmuen);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
if r.wb.read = '0' then
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
else
v.burst := ((r.rburst) and not andv(r.wb.addr(LINE_HIGH downto LINE_LOW))) or
(not r.rburst and r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2));
end if;
end if;
-- Generate new valid bits
if r.flush = '1' then twrite := '0'; dwrite := '0'; end if;
vmask := (others => (others => '1'));
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if r.mmctrl1wr = '1' then
case r.xaddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
v.mmctrl1.e := dci.maddress(MMCTRL_E);
v.mmctrl1.nf := dci.maddress(MMCTRL_NF);
v.mmctrl1.pso := dci.maddress(MMCTRL_PSO);
v.mmctrl1.tlbdis := dci.maddress(MMCTRL_TLBDIS);
v.mmctrl1.pagesize := dci.maddress(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := dci.maddress(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := dci.maddress(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
if ((dci.flush or dci.flushl or flush) = '1') and (dcen /= 0) then
v.flush := not r.noflush; v.faddr := (others => '0');
if (dci.flushl = '1') then v.flush := '1'; v.faddr := r.efaddr; end if;
end if;
if eholdn = '1' then v.efaddr := v.xaddress(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag := (others => '0');
if DSNOOPSEP then flushaddr := r.faddr; end if;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if ((r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) or r.flushl2) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop
ddatainv(i) := mcdo.data;
end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if DSNOOPSEP then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if DSNOOPSEP then
ctpwrite := (others => '1');
end if;
end if;
csnoopwe := (others => '0'); flushl := '0';
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe := snhit; end if;
if DSNOOPSEP then
csnoopwe := csnoopwe or ctwrite;
if orv(snhit) = '1' then flushl := '1'; end if; -- flush tag on snoop hit
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.tadj := (others => '0'); v.dadj := (others => '0');
v.sadj := (others => '0');
--if M_EN then
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.pagesize := (others => '0');
--end if;
v.mmctrl1.bar := (others => '0');
v.faddr := (others => '0');
v.reqst := '0';
v.cache := '0'; v.wb.lock := '0';
v.wb.data1 := (others => '0'); v.wb.data2 := (others => '0');
v.noflush := '0'; v.mexc := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
if not M_EN then v.mmctrl1 := mmctrl_type1_none; end if; -- kill MMU regs if not enabled
-- Drive signals
c <= v; cs <= vs; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag; -- virtual tag
dcrami.ptag <= ptag; -- physical tag
dcrami.ctx <= ctx; -- context
dcrami.tenable <= enable; -- virtual tag ram enable
dcrami.twrite <= ctwrite; -- virtual tag ram write (port 1)
dcrami.tpwrite <= ctpwrite; -- virtual tag ram write (port 2)
dcrami.flush <= r.flush or flushl;
dcrami.senable <= senable; -- physical tag ram enable
dcrami.swrite <= csnoopwe; -- physical tag ram write
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.faddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.faddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= flushaddr;
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr) and not mcdo.scanen;
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
dcrami.tdiag <= mcdo.testen & mcdo.scanen & r.tadj;
dcrami.sdiag <= mcdo.testen & mcdo.scanen & r.sadj;
dcrami.ddiag <= mcdo.testen & mcdo.scanen & r.dadj;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= r.cache;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.cache <= cache;
dco.hit <= r.hit;
if r.dstate = idle then dco.idle <= not r.stpend;
else dco.idle <= '0'; end if;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
mmudci.testin <= ahbsi.testin;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin
if rising_edge(sclk) then
rs <= cs;
if RESET_ALL and (rst = '0') then rs <= SRES; end if;
end if;
end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.addr <= (others => '0');
rs.snhit <= (others => '0'); rs.mask <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then rl <= LRES; end if;
end if;
end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 ways"
severity failure;
assert not ((DSETS = 3) and (drepl = dir)) report
"Wrong data cache configuration detected: Direct replacement requires 2 or 4 ways"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| gpl-2.0 | d36eb533fdb306c9a622c23fd50e5223 | 0.525459 | 3.459434 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/core/greth_tx.vhd | 1 | 16,823 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
--attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
txregs : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if rst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 973ac5f4e1aab69ee8e232873648b935 | 0.518219 | 3.187382 | false | false | false | false |
IamVNIE/Hardware-Security | Interfaces/UART_Version_2/UART_TX_CTRL.vhd | 2 | 2,829 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 21:49:51 11/23/2016
-- Design Name:
-- Module Name: UART_TX_CTRL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
signal bitDone : std_logic;
signal bitIndex : natural;
signal txBit : std_logic := '1';
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY => if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT => txState <= SEND_BIT;
when SEND_BIT => if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others => txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else '0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit | 23db18ab165ad173b060d3e5b8cae399 | 0.557441 | 3.101974 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml403/testbench.vhd | 1 | 9,339 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
u1 : mt46v16m16
generic map (index => 1, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
u2 : mt46v16m16
generic map (index => 0, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(3 downto 2));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | ca4f30b67ae6e86b93bcd355f5017c25 | 0.617732 | 3.002894 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/config.vhd | 1 | 7,716 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-2.0 | ffac693043ecfe0ca72e94b345579e7c | 0.653836 | 3.577191 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de2-115/config.vhd | 1 | 6,811 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- SPI to AHB bridge
constant CFG_SPI2AHB : integer := 0;
constant CFG_SPI2AHB_APB : integer := 0;
constant CFG_SPI2AHB_ADDRH : integer := 16#0#;
constant CFG_SPI2AHB_ADDRL : integer := 16#0#;
constant CFG_SPI2AHB_MASKH : integer := 16#0#;
constant CFG_SPI2AHB_MASKL : integer := 16#0#;
constant CFG_SPI2AHB_RESEN : integer := 0;
constant CFG_SPI2AHB_FILTER : integer := 2;
constant CFG_SPI2AHB_CPOL : integer := 0;
constant CFG_SPI2AHB_CPHA : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 18a0146aa5da1eace81484ea15ac513c | 0.648069 | 3.582851 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/openchip/sui/apbsui.vhd | 3 | 5,854 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: sui
-- File: apbsui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface
--
-- Single Peripheral containting the following:
-- Input:
-- Switches 0..31
-- Buttons 0..31
-- Output
-- LED 7 Segment, 4 digits non multiplexed, 32 digits in multiplexed mode
-- Single LED 0..31
-- Buzzer
-- Character LCD
--
-- Version 0: All functions are software assisted, IP Core has minimal
-- intelligence providing bit-bang access to all the connected hardware
--
--
--
--
--
--
--
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library openchip;
use openchip.sui.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbsui is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end;
architecture rtl of apbsui is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBSUI, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type suiregs is record
ledreg : std_logic_vector(31 downto 0); -- Output Latch, single LEDs
led7reg : std_logic_vector(31 downto 0); -- Output Latch, 7 Seg LEDs
lcdreg : std_logic_vector(15 downto 0); -- Output Latch LCD
buzreg : std_logic_vector(0 downto 0); -- Buzzer
sw_inreg : std_logic_vector(31 downto 0); -- Switches in
btn_inreg : std_logic_vector(31 downto 0); -- Buttons in
irq : std_ulogic; -- interrupt (internal), not used
end record;
signal r, rin : suiregs;
begin
comb : process(rst, r, apbi, suii )
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : suiregs;
begin
v := r;
v.sw_inreg := suii.switch_in;
v.btn_inreg := suii.button_in;
irq := (others => '0');
--irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- read/write registers
case apbi.paddr(4 downto 2) is
when "100" =>
rdata(31 downto 0) := r.sw_inreg; -- read switches
when "101" =>
rdata(31 downto 0) := r.btn_inreg; -- read buttons
when others =>
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
v.ledreg := apbi.pwdata(31 downto 0);
when "001" =>
v.led7reg := apbi.pwdata(31 downto 0);
when "010" =>
v.lcdreg(15 downto 0) := apbi.pwdata(15 downto 0);
when "011" =>
v.buzreg(0) := apbi.pwdata(0);
when others =>
end case;
end if;
-- reset operation
if rst = '0' then
v.ledreg := (others => '0');
v.led7reg := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
suio.lcd_out <= r.lcdreg(7 downto 0);
suio.lcd_en <= r.lcdreg(11 downto 8);
suio.lcd_rs <= r.lcdreg(12);
suio.lcd_r_wn <= r.lcdreg(13);
suio.lcd_backlight <= r.lcdreg(14);
suio.lcd_oe <= r.lcdreg(15);
suio.buzzer <= r.buzreg(0);
suio.led_out <= r.ledreg;
suio.led_a_out(0) <= r.led7reg(0);
suio.led_b_out(0) <= r.led7reg(1);
suio.led_c_out(0) <= r.led7reg(2);
suio.led_d_out(0) <= r.led7reg(3);
suio.led_e_out(0) <= r.led7reg(4);
suio.led_f_out(0) <= r.led7reg(5);
suio.led_g_out(0) <= r.led7reg(6);
suio.led_dp_out(0) <= r.led7reg(7);
suio.led_a_out(1) <= r.led7reg(8);
suio.led_b_out(1) <= r.led7reg(9);
suio.led_c_out(1) <= r.led7reg(10);
suio.led_d_out(1) <= r.led7reg(11);
suio.led_e_out(1) <= r.led7reg(12);
suio.led_f_out(1) <= r.led7reg(13);
suio.led_g_out(1) <= r.led7reg(14);
suio.led_dp_out(1) <= r.led7reg(15);
suio.led_a_out(2) <= r.led7reg(16);
suio.led_b_out(2) <= r.led7reg(17);
suio.led_c_out(2) <= r.led7reg(18);
suio.led_d_out(2) <= r.led7reg(19);
suio.led_e_out(2) <= r.led7reg(20);
suio.led_f_out(2) <= r.led7reg(21);
suio.led_g_out(2) <= r.led7reg(22);
suio.led_dp_out(2) <= r.led7reg(23);
suio.led_a_out(3) <= r.led7reg(24);
suio.led_b_out(3) <= r.led7reg(25);
suio.led_c_out(3) <= r.led7reg(26);
suio.led_d_out(3) <= r.led7reg(27);
suio.led_e_out(3) <= r.led7reg(28);
suio.led_f_out(3) <= r.led7reg(29);
suio.led_g_out(3) <= r.led7reg(30);
suio.led_dp_out(3) <= r.led7reg(31);
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbsui" & tost(pindex) &
": SUI rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 | 5e297fc5a1e962c7915a5d71a917af30 | 0.572429 | 2.800957 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-asic/config.vhd | 1 | 7,517 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := saed32;
constant CFG_MEMTECH : integer := saed32;
constant CFG_PADTECH : integer := saed32;
constant CFG_NOASYNC : integer := 1;
constant CFG_SCAN : integer := 1;
-- JTAG boundary-scan chain
constant CFG_BOUNDSCAN_EN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := saed32;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (6);
constant CFG_SPICTRL_FIFO : integer := (4);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (4);
constant CFG_GPT_SW : integer := (12);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (6);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 8064b9bb4555c1b609cdd60b728670b1 | 0.65159 | 3.624397 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 3 | 24,145 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (31 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(31 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (31 downto 0) := (others => '0');
signal current_bd : std_logic_vector (31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
ftch_tdata_new (95 downto 0) <= data_concat;-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (127 downto 96) <= current_bd;
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd;
end generate DMA_FIELDS;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
m_axis_ftch_tdata_new <= ftch_tdata_new;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_new <= ftch_tdata_new;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| gpl-3.0 | da623fee8672d69ff718078824956efc | 0.440712 | 4.263641 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_blk_mem_gen_0_0/synth/design_1_blk_mem_gen_0_0.vhd | 1 | 14,879 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_0;
ARCHITECTURE design_1_blk_mem_gen_0_0_arch OF design_1_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_0_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_0_arch;
| gpl-3.0 | 0e8296ab2425a358859afdb1e1b0bae9 | 0.636131 | 3.032817 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_0/synth/design_1_axi_bram_ctrl_0_0.vhd | 1 | 16,618 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | c5bb4866f0060cd796ab1f7cbc087b66 | 0.676014 | 3.060969 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/stratixii/clkgen_stratixii.vhd | 1 | 6,703 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity stratix2_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix2_pll is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component stratix2_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix2_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 216a35e308b2eed49aed647efc545b3f | 0.584962 | 3.513103 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc6s/leon3mp.vhd | 1 | 47,744 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- dip swtich 7
-- dsubre : in std_ulogic; -- switch 9
-- dsuact : out std_ulogic; -- led (0)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
-- SD Card interface (SD SPI interface)
-- sdata : inout std_ulogic_vector(3 downto 0);
-- sd_clk : out std_ulogic;
-- spi_cmd : out std_ulogic;
-- sd_prot : in std_logic;
-- sd_detect : in std_logic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal leds : std_logic_vector(3 downto 0); -- I/O port
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125 : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (15, 16#010# , 16#ff0#, fabtech, CFG_GRETH1G, 1, 0, 1)
port map (rstn, rgmiii.gtx_clk, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk125, rgmiii.gtx_clk);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 42623f44201ae3d4dee6d39fef66336d | 0.553221 | 3.425456 | false | false | false | false |
capitanov/Stupid_watch | src/top/top_xc3s500e_ex.vhd | 1 | 14,017 | --------------------------------------------------------------------------------
--
-- Title : top_xc3s500e_ex.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Top level for timer based on Spartan3E Starter Kit
--
-- Xilinx Spartan3e - XC3S500E-4FG320C
-- Switches, LEDs, TIMER (ds1302), display (lcd1602)
--
-- SW<0> - RESET
-- SW<1> - ENABLE
-- SW<2> - PWM
-- SW<3> - START
--
--
--------------------------------------------------------------------------------
library IEEE; --! main standard libs
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNISIM; --! xilinx unusim libs
use UNISIM.VCOMPONENTS.ALL;
library WORK; --! user work libs
use WORK.ctrl_types_pkg.all;
entity top_xc3s500e_ex is
generic (
TD : in time := 1 ns ; --! simulation time;
DIV_SCL : in integer := 100 --! clock division for logic counters
);
port(
---- SWITCHES ----
RESET : in std_logic; --! asycnchronous reset: SW(0)
PWM : in std_logic; --! PWM Enable : SW(1)
LCD : in std_logic; --! LCD/LED Switch : SW(2)
START : in std_logic; --! LCD Controller Start : SW(3)
RESTART : in std_logic; --! RESTART Timer DS1302
TEST_LCD : in std_logic; --! TEST LCD DISPLAY
---- PS/2 IO ----
PS2_CLK : in std_logic; --! PS/2 clk (keyboard)
PS2_DATA : in std_logic; --! PS/2 data (keyboad)
---- CLOCK 50 MHz ----
CLK : in std_logic; --! main clock 50 MHz
---- VGA SYNC ----
VGA_HSYNC : out std_logic; --! horiztonal sync
VGA_VSYNC : out std_logic; --! vertical sync
VGA_R : out std_logic; --! VGA Red
VGA_G : out std_logic; --! VGA Green
VGA_B : out std_logic; --! VGA Blue
---- LED DISPLAY ----
LED_X : out std_logic_vector(7 downto 3); --! LEDs Y
--LED_Y : out std_logic_vector(7 downto 0); --! LEDs X
---- BUTTONS ----
KB : in std_logic_vector(5 downto 1); --! Five Buttons
---- SERIAL TIMER ----
T_DT : inout std_logic; --! timer serial data
T_CK : out std_logic; --! timer serial clock (~1 MHz)
T_CE : out std_logic; --! timer serial enable
-- LCD1602 INTERFACE
LCD_DT : out std_logic_vector(7 downto 0); --! LCD Data
LCD_EN : out std_logic; --! LCD Enable
LCD_RW : out std_logic; --! LCD R/W (write - '0', read - '1')
LCD_RS : out std_logic; --! LCD RS (command - '0', data - '1')
-- TEST POINTS
TST : out std_logic_vector(2 downto 0); --! Test points
---- DOORBELL ----
BELL : out std_logic --! BELL (tie to VCC)
);
end top_xc3s500e_ex;
architecture top_xc3s500e_ex of top_xc3s500e_ex is
---------------- SIGNALS DECLARATION ----------------
signal ps2_clock : std_logic;
signal ps2_din : std_logic;
signal sys_reset : std_logic;
signal reset_v : std_logic_vector(6 downto 0);
signal rst : std_logic;
signal rstz : std_logic;
signal RGB : std_logic_vector(2 downto 0);
signal clk_fb : std_logic;
signal clk0 : std_logic;
signal clk_in : std_logic;
signal locked : std_logic;
signal clk_dv : std_logic;
signal rst_dcm : std_logic;
signal v, h : std_logic;
--signal leds : std_logic_vector(8 downto 1);
signal led_hearty : std_logic_vector(7 downto 0);
signal led_heartx : std_logic_vector(7 downto 0);
signal pwm_ena : std_logic;
signal button : std_logic_vector(5 downto 1);
signal switch_lcd : std_logic;
signal time_addr : std_logic_vector(7 downto 0);
signal time_data_i : std_logic_vector(7 downto 0);
signal time_data_o : std_logic_vector(7 downto 0);
signal time_data_v : std_logic;
signal time_rdy : std_logic;
signal time_enable : std_logic;
signal disp_dt : std_logic_vector(7 downto 0);
signal disp_en : std_logic;
signal disp_rw : std_logic;
signal disp_rs : std_logic;
signal disp_start : std_logic;
signal disp_rdy : std_logic;
signal disp_init : std_logic;
signal disp_data : std_logic_vector(7 downto 0);
signal disp_com : std_logic:='0';
signal disp_ena : std_logic;
signal buff_dt : std_logic_vector(7 downto 0);
signal buff_en : std_logic;
signal buff_rw : std_logic;
signal buff_rs : std_logic;
signal buff_xx : std_logic_vector(7 downto 3);
--signal cnt : std_logic_vector(5 downto 0):="000000";
signal rstart : std_logic;
signal disp_rdyz : std_logic;
signal disp_rdyt : std_logic;
signal ds_data_i : std_logic;
signal ds_data_o : std_logic;
signal ds_data_t : std_logic;
signal ds_data_tn : std_logic;
signal load_ena : std_logic;
signal load_dat : std_logic_vector(7 downto 0);
signal load_addr : std_logic_vector(4 downto 0);
signal test_mode : std_logic;
begin
disp_rdyz <= not disp_rdy after td when rising_edge(clk_in);
disp_rdyt <= disp_rdyz and disp_rdy after td when rising_edge(clk_in);
---------------- TIMER TRANSFER ----------------
x_SET_TIME: cl_timer_data
generic map (
TIME_SECS => 47, -- seconds
TIME_MINS => 59, -- minutes
TIME_HRS => 13, -- hours
TIME_DTS => 19, -- dates
TIME_MTHS => 09, -- months
TIME_DAYS => 06, -- days
TIME_YRS => 15, -- years
TD => TD -- simulation time;
)
port map(
---- Global signals ----
reset => reset_v(0), -- asycnchronous reset
clk => clk_in, -- clock 50 MHz
restart => rstart, -- restart timer
---- DS1302 signals ----
addr => time_addr, -- address for timer
data_o => time_data_i, -- input data (to timer)
data_i => time_data_o, -- output data (from timer)
data_v => time_data_v, -- valid data (from timer)
ready => time_rdy, -- timer is ready for data
enable => time_enable, -- timer enable
---- LCD1602 signals ----
load_ena => load_ena, -- enable writing to LCD RAM
load_dat => load_dat, -- data to LCD RAM
load_addr => load_addr -- address to LCD RAM
);
---------------- LCD1602 TRANSFER ----------------
x_LCD_TST: cl_lcd_data
generic map (
TD => TD -- simulation time;
)
port map(
reset => reset_v(1), -- system frequency (50 MHz)
clk => clk_in, -- '0' - negative reset
test_mode => test_mode, -- select mode: test message or timer
load_ena => load_ena, -- load new data
load_dat => load_dat, -- new data;
load_addr => load_addr, -- new address;
disp_data => disp_data, -- data to display
disp_ena => disp_ena, -- enable for data
disp_init => disp_init, -- ready for data
disp_rdyt => disp_rdyt -- valid pulse for data
);
---------------- LCD1602 CONTROLLER ----------------
x_LCD1602: rtl_lcd1602
generic map (
TD => TD, -- simulation time;
DIV_SCL => 5000 -- clock division for SCL: clk50m/DIV_SCL
)
port map(
-- global ports
clk50m => clk_in, -- system frequency (50 MHz)
rstn => reset_v(2), -- '0' - negative reset
-- main interface
start => disp_start, -- start
data_ena => disp_ena, -- data enable (S)
data_int => disp_data, -- data Tx
data_sel => disp_com, -- select: '0' - data, '1' - command
data_rw => '0', -- WRITE ONLY;
lcd_ready => disp_rdy, -- ready for data
lcd_init => disp_init, -- lcd initialization complete
-- lcd1602 interface
lcd_dt => disp_dt, -- lcd data
lcd_en => disp_en, -- lcd clock enable
lcd_rw => disp_rw, -- lcd r/w: write - '0', read - '1'
lcd_rs => disp_rs -- lcd set: command - '0', data - '1'
);
---------------- DS1302 CONTROLLER ----------------
x_DS1302: rtl_ds1302
generic map (
TD => TD, -- simulation time;
DIV_SCL => DIV_SCL -- clock division for SCL: clk50m/DIV_SCL
)
port map(
-- global ports
clk50m => clk_in, -- system frequency (50 MHz)
rstn => reset_v(3), -- '0' - negative reset
-- main interface
enable => time_enable, -- i2c start (S)
addr_i => time_addr, -- address Tx: 7 bit - always '1', 0 bit - R/W ('0' - write, '1' - read)
data_i => time_data_i, -- data Tx
data_o => time_data_o, -- data Rx
data_v => time_data_v, -- valid Rx
ready => time_rdy, -- ready
-- serial interface
--ds_data => T_DT,--ds_data, -- serial data
ds_data_i => ds_data_i, -- serial data input
ds_data_o => ds_data_o, -- serial data output
ds_data_t => ds_data_t, -- serial data enable
ds_clk => T_CK, -- serial clock
ds_ena => T_CE -- clock enable for i2c
);
---------------- MINESWEEPER GAME ----------------
x_MAIN_BLOCK : rtl_game_int
port map(
clk => clk_dv, -- 25 MHz freq;
reset => reset_v(4), -- GLOBAL RESET
ps2_clk => ps2_clock, -- PS/2 CLOCK
ps2_data => ps2_din, -- PS/2 SERIAL DATA
h_vga => H, -- HORIZONTAL
v_vga => V, -- VERTICAL
rgb => RGB -- (R-G-B)
--leds => LEDS -- LEDs
);
---------------- HEART XY 8X8 ----------------
pr_lcd_sw: process(clk_in, reset_v(5)) is
begin
if (reset_v(5) = '0') then
buff_dt <= x"00";
buff_en <= '0';
buff_rw <= '0';
buff_rs <= '0';
elsif rising_edge(clk_in) then
if switch_lcd = '1' then
buff_dt <= disp_dt;
buff_en <= disp_en;
buff_rw <= disp_rw;
buff_rs <= disp_rs;
else
x_rev: for ii in 0 to 7 loop
buff_dt(ii) <= led_hearty(7-ii);
end loop;
buff_rs <= led_heartx(0);
buff_rw <= led_heartx(1);
buff_en <= led_heartx(2);
buff_xx <= led_heartx(7 downto 3);
end if;
end if;
end process;
ds_data_tn <= ds_data_t;
---------------- I/O BUFFERS ----------------
TST(0) <= ds_data_o;
TST(1) <= ds_data_tn;
TST(2) <= ds_data_i;
xDSIO: iobuf port map(i => ds_data_o, o => ds_data_i, io => T_DT, t => ds_data_tn);
xPS2C: ibuf port map(i => ps2_clk, o => ps2_clock);
xPS2D: ibuf port map(i => ps2_data, o => ps2_din);
xRESET: ibuf port map(i => RESET, o => rst);
xPWM: ibuf port map(i => PWM, o => pwm_ena);
xSTART: ibuf port map(i => START, o => disp_start);
xRESTART: ibuf port map(i => RESTART, o => rstart);
xBELL: obuf port map(i => '1', o => BELL);
xVGA_v: obuf port map(i => v, o => VGA_VSYNC);
xVGA_h: obuf port map(i => h, o => VGA_HSYNC);
xVGA_R: obuf port map(i => RGB(2), o => VGA_R);
xVGA_G: obuf port map(i => RGB(1), o => VGA_G);
xVGA_B: obuf port map(i => RGB(0), o => VGA_B);
xLCD_EN: obuf port map(i => buff_en, o => LCD_EN);
xLCD_RW: obuf port map(i => buff_rw, o => LCD_RW);
xLCD_RS: obuf port map(i => buff_rs, o => LCD_RS);
xLCD_DT: for ii in 0 to 7 generate
xLCD_DATA: obuf port map(i => buff_dt(ii), o => LCD_DT(ii));
end generate;
xLCD_SW: ibuf port map(i => LCD, o => switch_lcd);
xLCD_TST: ibuf port map(i => TEST_LCD, o => test_mode);
xBUTS: for ii in 1 to 5 generate
xswitch: ibuf port map(i => KB(ii), o => button(ii));
end generate;
-- LEDS:
xLED_XY: for ii in 3 to 7 generate
ledx: obuf port map(i => buff_xx(ii), o => LED_X(ii));
-- ledy: obuf port map(i => led_hearty(ii), o => LED_Y(ii));
end generate;
---------------- DEBOUNCE ----------------
xCTRL_8x8 : ctrl_leds
port map (
-- System signals:
clk => clk0,
clk_dv => clk_dv,
reset => reset_v(6),
pwm_ena => pwm_ena,
-- Buttons:
cbut => button,
-- Leds vectors:
led_x => led_heartx,
led_y => led_hearty
);
---------------- DCM CLOCK ----------------
xCLKFB: bufg port map(i => clk0, o => clk_fb);
xCLKIN: ibufg port map(i => clk,o => clk_in);
sys_reset <= (rstz and locked) after td when rising_edge(clk_in);
xFD_RST: ctrl_fanout
generic map(
FD_WIDTH => 7)
port map(
clk => clk_in,
data_in => sys_reset,
data_out => reset_v
);
--xgen_rst: for ii in 0 to 7 generate
--reset_v(ii) <= sys_reset after td when rising_edge(clk_in);
--end generate;
xSRL_RESET: srlc16
generic map (
init => x"0000"
)
port map(
Q15 => rstz,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CLK => clk_in,
D => rst -- '1',
);
rst_dcm <= not rst;
---------------- CLOCK GENERATOR - DCM ----------------
xDCM_CLK_VGA : dcm
generic map(
--DCM_AUTOCALIBRATION => FALSE, -- DCM ADV
CLKDV_DIVIDE => 2.0, -- clk divide for CLKIN: Fdv = Fclkin / CLK_DIV
CLKFX_DIVIDE => 2, -- clk divide for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKFX_MULTIPLY => 2, -- clk multiply for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKIN_DIVIDE_BY_2 => FALSE, -- divide clk / 2 before DCM block
CLKIN_PERIOD => 20.0, -- clk period in ns (for DRC)
CLKOUT_PHASE_SHIFT => "NONE", -- phase shift mode: NONE, FIXED, VARIABLE
CLK_FEEDBACK => "1X", -- freq on the feedback clock: 1x, 2x, None
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- clk delay alignment
DFS_FREQUENCY_MODE => "LOW", -- freq mode CLKFX and CLKFX180: LOW, HIGH
DLL_FREQUENCY_MODE => "LOW", -- freq mode CLKIN: LOW, HIGH
DUTY_CYCLE_CORRECTION => TRUE, -- 50% duty-cycle correction for the CLK0, CLK90, CLK180 and CLK270: TRUE, FALSE
PHASE_SHIFT => 0 -- phase shift (with CLKOUT_PHASE_SHIFT): -255 to 255
)
port map(
clk0 => clk0,
-- clk180 => clk180,
-- clk270 => clk270,
-- clk2x => clk2x,
-- clk2x180 => clk2x180,
-- clk90 => clk90,
clkdv => clk_dv,
-- clkfx => clkfx,
-- clkfx180 => clkfx180,
locked => locked,
-- status => status,
-- psdone => psdone,
clkfb => clk_fb,
clkin => clk_in,
-- dssen => dssen,
-- psclk => psclk,
psen => '0',
psincdec => '0',
rst => rst_dcm
);
end top_xc3s500e_ex; | mit | b99a5ab849e596536e7280c5a4b1aef8 | 0.538346 | 2.693505 | false | false | false | false |
IamVNIE/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RC5encryptAllSteps.vhd | 2 | 6,997 | Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_enc Is
Port
(
clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(63 downto 0);
di_vld : in std_logic;
key_rdy : in std_logic;
skey : in rom;
dout : out std_logic_vector(63 downto 0);
do_rdy : out std_logic
);
End rc5_enc;
Architecture rtl of rc5_enc is
signal i_cnt : Std_logic_vector(3 downto 0); --Signals
signal ab_xor : Std_logic_vector(31 downto 0);
signal a_rot : Std_logic_vector(31 downto 0);
signal a : Std_logic_vector(31 downto 0);
signal a_pre : Std_logic_vector(31 downto 0);
signal a_reg : Std_logic_vector(31 downto 0);
signal ba_xor : Std_logic_vector(31 downto 0);
signal b_rot : Std_logic_vector(31 downto 0);
signal b : Std_logic_vector(31 downto 0);
signal b_pre : Std_logic_vector(31 downto 0);
signal b_reg : Std_logic_vector(31 downto 0);
--RC5 State Machine
Type StateType is --Type for state machine
(
ST_idle,
ST_pre_round,
ST_round_op,
ST_ready
);
Signal state_en : StateType; --Signal type of state machine
Begin
ab_xor <= a_reg XOR b_reg; --A_reg _reg XOR
With b_reg(4 downto 0) Select --Rotate left XOR result
a_rot <= ab_xor(30 downto 0) & ab_xor(31) when "00001",
ab_xor(29 downto 0) & ab_xor(31 downto 30) when "00010",
ab_xor(28 downto 0) & ab_xor(31 downto 29) when "00011",
ab_xor(27 downto 0) & ab_xor(31 downto 28) when "00100",
ab_xor(26 downto 0) & ab_xor(31 downto 27) when "00101",
ab_xor(25 downto 0) & ab_xor(31 downto 26) when "00110",
ab_xor(24 downto 0) & ab_xor(31 downto 25) when "00111",
ab_xor(23 downto 0) & ab_xor(31 downto 24) when "01000",
ab_xor(22 downto 0) & ab_xor(31 downto 23) when "01001",
ab_xor(21 downto 0) & ab_xor(31 downto 22) when "01010",
ab_xor(20 downto 0) & ab_xor(31 downto 21) when "01011",
ab_xor(19 downto 0) & ab_xor(31 downto 20) when "01100",
ab_xor(18 downto 0) & ab_xor(31 downto 19) when "01101",
ab_xor(17 downto 0) & ab_xor(31 downto 18) when "01110",
ab_xor(16 downto 0) & ab_xor(31 downto 17) when "01111",
ab_xor(15 downto 0) & ab_xor(31 downto 16) when "10000",
ab_xor(14 downto 0) & ab_xor(31 downto 15) when "10001",
ab_xor(13 downto 0) & ab_xor(31 downto 14) when "10010",
ab_xor(12 downto 0) & ab_xor(31 downto 13) when "10011",
ab_xor(11 downto 0) & ab_xor(31 downto 12) when "10100",
ab_xor(10 downto 0) & ab_xor(31 downto 11) when "10101",
ab_xor(9 downto 0) & ab_xor(31 downto 10) when "10110",
ab_xor(8 downto 0) & ab_xor(31 downto 9) when "10111",
ab_xor(7 downto 0) & ab_xor(31 downto 8) when "11000",
ab_xor(6 downto 0) & ab_xor(31 downto 7) when "11001",
ab_xor(5 downto 0) & ab_xor(31 downto 6) when "11010",
ab_xor(4 downto 0) & ab_xor(31 downto 5) when "11011",
ab_xor(3 downto 0) & ab_xor(31 downto 4) when "11100",
ab_xor(2 downto 0) & ab_xor(31 downto 3) when "11101",
ab_xor(1 downto 0) & ab_xor(31 downto 2) when "11110",
ab_xor(0) & ab_xor(31 downto 1) when "11111",
ab_xor when others;
a_pre <= din(63 downto 32) + skey(0); --A_pre output after add din and skey
a <= a_rot + skey(CONV_INTEGER(i_cnt & '0')); --A output after add left rotate and skey
ba_xor <= b_reg XOR a; --B_reg XOR with A
with a(4 downto 0) Select --Rotate left result of XOR
b_rot <= ba_xor(30 downto 0) & ba_xor(31) when "00001",
ba_xor(29 downto 0) & ba_xor(31 downto 30) when "00010",
ba_xor(28 downto 0) & ba_xor(31 downto 29) when "00011",
ba_xor(27 downto 0) & ba_xor(31 downto 28) when "00100",
ba_xor(26 downto 0) & ba_xor(31 downto 27) when "00101",
ba_xor(25 downto 0) & ba_xor(31 downto 26) when "00110",
ba_xor(24 downto 0) & ba_xor(31 downto 25) when "00111",
ba_xor(23 downto 0) & ba_xor(31 downto 24) when "01000",
ba_xor(22 downto 0) & ba_xor(31 downto 23) when "01001",
ba_xor(21 downto 0) & ba_xor(31 downto 22) when "01010",
ba_xor(20 downto 0) & ba_xor(31 downto 21) when "01011",
ba_xor(19 downto 0) & ba_xor(31 downto 20) when "01100",
ba_xor(18 downto 0) & ba_xor(31 downto 19) when "01101",
ba_xor(17 downto 0) & ba_xor(31 downto 18) when "01110",
ba_xor(16 downto 0) & ba_xor(31 downto 17) when "01111",
ba_xor(15 downto 0) & ba_xor(31 downto 16) when "10000",
ba_xor(14 downto 0) & ba_xor(31 downto 15) when "10001",
ba_xor(13 downto 0) & ba_xor(31 downto 14) when "10010",
ba_xor(12 downto 0) & ba_xor(31 downto 13) when "10011",
ba_xor(11 downto 0) & ba_xor(31 downto 12) when "10100",
ba_xor(10 downto 0) & ba_xor(31 downto 11) when "10101",
ba_xor(9 downto 0) & ba_xor(31 downto 10) when "10110",
ba_xor(8 downto 0) & ba_xor(31 downto 9) when "10111",
ba_xor(7 downto 0) & ba_xor(31 downto 8) when "11000",
ba_xor(6 downto 0) & ba_xor(31 downto 7) when "11001",
ba_xor(5 downto 0) & ba_xor(31 downto 6) when "11010",
ba_xor(4 downto 0) & ba_xor(31 downto 5) when "11011",
ba_xor(3 downto 0) & ba_xor(31 downto 4) when "11100",
ba_xor(2 downto 0) & ba_xor(31 downto 3) when "11101",
ba_xor(1 downto 0) & ba_xor(31 downto 2) when "11110",
ba_xor(0) & ba_xor(31 downto 1) when "11111",
ba_xor when others;
b_pre <= din(31 downto 0) + skey(1); --B output when add din and skey 1
b <= b_rot + skey(CONV_INTEGER(i_cnt & '1')); --B output when add left rotate and skey
--Register A --Register A
Process(clr, clk) Begin
If(clr='0') Then
a_reg <= (Others => '0');
elsif(clk'Event and clk='1') Then
If (state_en=ST_pre_round) Then
a_reg <= a_pre;
Elsif (state_en=ST_round_op) Then
a_reg <= a;
End if;
End If;
End Process;
--Register B --Register B
Process(clr, clk) Begin
If(clr='0') Then
b_reg <= (Others => '0');
Elsif(clk'Event and clk='1') Then
If (state_en=ST_pre_round) Then
b_reg <= b_pre;
Elsif (state_en=ST_round_op) Then
b_reg <= b;
End if;
End If;
End Process;
Process (clr, clk) --State Machine
Begin
If (clr='0') Then
state_en <= ST_idle;
Elsif (clk'Event And clk = '1') Then
Case state_en is
When ST_idle => If (di_vld='1' and key_rdy='1') Then state_en <= ST_pre_round; End If;
When ST_pre_round => state_en <= ST_round_op;
When ST_round_op => If (i_cnt="1100") Then state_en <= ST_ready; End If;
When ST_ready => state_en <= ST_idle;
End Case;
End If;
End Process;
Process(clr, clk) Begin --Round Counter
If(clr='0') Then
i_cnt <= "0001";
Elsif(clk'Event And clk='1') Then
If (state_en = ST_round_op) Then
If(i_cnt="1100") Then
i_cnt <= "0001";
Else
i_cnt <= i_cnt + '1';
End If;
End If;
End If;
End Process;
dout <= a_reg & b_reg;
With state_en Select
do_rdy <= '1' When ST_ready,
'0' When Others;
End rtl; | mit | cfba38df647b19f195c6d5db4b11a2ce | 0.605688 | 2.629463 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | TB_DataMemory.vhd | 1 | 1,459 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TB_DataMemory IS
END TB_DataMemory;
ARCHITECTURE behavior OF TB_DataMemory IS
COMPONENT DataMemory
PORT(
Rst : IN std_logic;
cRD : IN std_logic_vector(31 downto 0);
AluResult : IN std_logic_vector(31 downto 0);
WrENMem : IN std_logic;
RdENMem : IN std_logic;
Data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Rst : std_logic := '0';
signal cRD : std_logic_vector(31 downto 0) := (others => '0');
signal AluResult : std_logic_vector(31 downto 0) := (others => '0');
signal WrENMem : std_logic := '0';
signal RdENMem : std_logic := '0';
--Outputs
signal Data : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataMemory PORT MAP (
Rst => Rst,
cRD => cRD,
AluResult => AluResult,
WrENMem => WrENMem,
RdENMem => RdENMem,
Data => Data
);
-- Stimulus process
stim_proc: process
begin
Rst <= '1';
cRD <= x"00000001";
AluResult <= x"00000001";
WrENMem <= '0';
RdENMem <= '0';
wait for 10 ns;
Rst <= '0';
WrENMem <= '1';
RdENMem <= '1';
wait for 10 ns;
WrENMem <= '0';
RdENMem <= '1';
wait for 10 ns;
WrENMem <= '0';
RdENMem <= '0';
wait;
end process;
END;
| mit | 3c61aa91b42709073a05b2b8e3429871 | 0.566827 | 3.199561 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-asic/leon3mp.vhd | 1 | 18,140 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 4,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 4,
uart_padstrength => 4,
dsu_padstrength => 4,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
| gpl-2.0 | be52bbfa08be7ddf5a9b876e0ae35b59 | 0.463286 | 3.690743 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | unionModulos.vhd | 1 | 9,234 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity unionModulos is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
salida : out STD_LOGIC_VECTOR (31 downto 0));
end unionModulos;
architecture Behavioral of unionModulos is
signal SumDisp22, SumDisp30, aux1, PcCounterPlus, PC, aux2, address, instruction, Crs1, Crs2, cRD, aux7, AluResult, aux10, DataToMem, DataToReg, SEU_Disp30_Out, SEU_Disp22_Out, nPC_Source: std_logic_vector(31 downto 0) := (others => '0');
signal AluOp, Op3, NRs1, NRs2, NRd, Mux_NRd: std_logic_vector(5 downto 0) := (others => '0');
signal rs1, rs2, rd : std_logic_vector(4 downto 0) := (others => '0');
signal Op, PcSource, RfSource: std_logic_vector(1 downto 0) := (others => '0');
signal ncwp, cwp, Carry, weRF, RFDest, ReENMemory, WrENMemory: std_logic := '0';
signal imm13: std_logic_vector(12 downto 0) := (others => '0');
signal NZVC, cond, icc: std_logic_vector(3 downto 0) := (others => '0');
signal disp30 : std_logic_vector(29 downto 0) := (others => '0');
signal disp22 : std_logic_vector(21 downto 0) := (others => '0');
component ProgrammingCounter
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dato : in STD_LOGIC_VECTOR (31 downto 0); -- addres
PCOut : out STD_LOGIC_VECTOR (31 downto 0) -- sig
);
end component;
component RD_Mux
Port (
RfDest : in STD_LOGIC;
RD : in STD_LOGIC_VECTOR (5 downto 0);
nRD : out STD_LOGIC_VECTOR (5 downto 0));
end component;
component DataMemory
Port ( Rst : in STD_LOGIC;
cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WrENMem : in STD_LOGIC;
RdENMem : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component Sumador32B
port (
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
SumOut : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component instructionMemory
port (
address : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
outInstruction : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component registerFile
Port ( we : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
dataToWrite : in STD_LOGIC_VECTOR (31 downto 0);
CRs1 : out STD_LOGIC_VECTOR (31 downto 0);
CRs2 : out STD_LOGIC_VECTOR (31 downto 0);
CRd : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component UnityControl
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
we : out STD_LOGIC;
RFDest : out STD_LOGIC;
WrENMemory : out STD_LOGIC;
ReENMemory : out STD_LOGIC;
RfSource : out STD_LOGIC_VECTOR(1 downto 0);
PcSource : out STD_LOGIC_VECTOR(1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0)
);
end component;
component Alu
Port ( AluOp : in STD_LOGIC_VECTOR (5 downto 0);
rs1 : in STD_LOGIC_VECTOR (31 downto 0);
rs2 : in STD_LOGIC_VECTOR (31 downto 0);
c : in STD_LOGIC;
AluResult : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component WindowsManager
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
cwp : in STD_LOGIC;
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
ncwp : out STD_LOGIC;
nrd : out STD_LOGIC_VECTOR (5 downto 0));
end component;
component PSR_Modifier
Port ( AluOp : in STD_LOGIC_VECTOR (5 downto 0);
Crs1 : in STD_LOGIC_VECTOR (31 downto 0);
Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
ALU_Result : in STD_LOGIC_VECTOR (31 downto 0);
nzvc : out STD_LOGIC_VECTOR (3 downto 0);
rst: in STD_LOGIC);
end component;
component PSR
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ncwp: in STD_LOGIC;
cond : in STD_LOGIC_VECTOR (3 downto 0);
carry : out STD_LOGIC;
cwp : out STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Mux32B
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
Sc : in STD_LOGIC;
MuxOut : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component SignExtender
Port ( A : in STD_LOGIC_VECTOR (12 downto 0);
SEOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component SEU_Disp30
Port ( Disp30 : in STD_LOGIC_VECTOR (29 downto 0);
SEU_Disp30_Out : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component SEU_Disp22
Port ( Disp22 : in STD_LOGIC_VECTOR (21 downto 0);
Seu_Disp22_Out : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component PC_Mux
Port ( clk : in STD_LOGIC;
PcSource : in STD_LOGIC_VECTOR (1 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
Pc : in STD_LOGIC_VECTOR (31 downto 0);
Pc_Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
Pc_Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
nPC_Source : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component DataRF_Mux
Port ( clk : in STD_LOGIC;
RfSource : in STD_LOGIC_VECTOR (1 downto 0);
DataToMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
DataToReg : out STD_LOGIC_VECTOR (31 downto 0));
end component;
begin
Inst_pc_next: ProgrammingCounter port map (
clk => clk,
rst => rst,
dato => nPC_Source,
PCOut => aux1
);
Inst_pc: ProgrammingCounter port map (
clk => clk,
rst => rst,
dato => aux1,
PCOut => address
);
Inst_sumPC: Sumador32B port map (
A => aux1,
B => x"00000001",
SumOut => PcCounterPlus
);
Inst_instructionMemory: instructionMemory port map (
address => address,
rst => rst,
outInstruction => instruction
);
rs1 <= instruction(18 downto 14);
rs2 <= instruction(4 downto 0);
rd <= instruction(29 downto 25);
Op <= instruction(31 downto 30);
Op3 <= instruction(24 downto 19);
imm13 <= instruction(12 downto 0);
cond <= instruction(28 downto 25);
disp30 <= instruction(29 downto 0);
disp22 <= instruction(21 downto 0);
Inst_WindowsManager: WindowsManager Port Map (
rs1 => rs1,
rs2 => rs2,
rd => rd,
cwp => cwp,
op3 => Op3,
op => Op,
nrs1 => NRs1,
nrs2 => NRs2,
ncwp => ncwp,
nrd => NRd
);
Inst_RD_Mux: RD_Mux Port Map (
RfDest => RfDest,
RD => NRd,
nRD => Mux_NRd
);
Inst_PSR: PSR Port Map (
nzvc => NZVC,
rst => rst,
clk => clk,
ncwp => ncwp,
cond => cond,
carry => Carry,
cwp => cwp,
icc => icc
);
Inst_register_file: registerFile port map(
we => weRF,
rs1 => NRs1,
rs2 => NRs2,
rd => Mux_NRd,
rst => rst,
dataToWrite => DataToReg,
CRs1 => Crs1,
CRs2 => aux7,
CRd => cRD
);
Inst_UC: UnityControl Port Map(
Op => Op,
Op3=> Op3,
AluOp => AluOp,
cond => cond,
icc => icc,
we => weRF,
RFDest => RFDest,
WrENMemory => WrENMemory,
ReENMemory => ReENMemory,
RfSource => RfSource,
PcSource => PcSource
);
Inst_Sign_ext_unit: SignExtender port map (
A => imm13,
SEOut => aux10
);
Inst_PSR_Modifier: PSR_Modifier Port Map (
AluOp => AluOp,
Crs1 => Crs1,
Crs2 => Crs2,
ALU_Result => AluResult,
nzvc => NZVC,
rst => rst
);
Inst_mux32b: Mux32B port map (
A => aux7,
B => aux10,
Sc => instruction(13),
MuxOut => Crs2
);
Inst_ALU: Alu port map (
AluOp => AluOp,
rs1 => Crs1,
rs2 => Crs2,
c => Carry,
AluResult => AluResult
);
Inst_DataMemory: DataMemory port map (
Rst => Rst,
cRD => cRD,
AluResult => AluResult,
WrENMem => WrENMemory,
RdENMem => ReENMemory,
Data => DataToMem
);
Inst_DataRf_Mux: DataRF_Mux port map (
clk => clk,
RfSource => RfSource,
DataToMem => DataToMem,
AluResult => AluResult,
PC => address,
DataToReg => DataToReg
);
Inst_SeuDisp30: SEU_Disp30 port map (
Disp30 => disp30,
SEU_Disp30_Out => SEU_Disp30_Out
);
Inst_Disp30_Sumador : Sumador32B port map(
A => SEU_Disp30_Out,
B => PcCounterPlus,
SumOut => SumDisp30
);
Inst_SeuDisp22: SEU_Disp22 port map (
Disp22 => disp22,
Seu_Disp22_Out => Seu_Disp22_Out
);
Inst_Disp22_Sumador : Sumador32B port map(
A => SEU_Disp22_Out,
B => PcCounterPlus,
SumOut => SumDisp22
);
Inst_PcMux: PC_Mux port map (
clk => clk,
PcSource => PcSource,
AluResult => AluResult,
Pc => PcCounterPlus,
Pc_Disp22 => SumDisp22,
Pc_Disp30 => SumDisp30,
nPC_Source => nPC_Source
);
salida <= AluResult;
end Behavioral; | mit | e150619ca85e6eb989d174d75c236aaf | 0.603964 | 2.987383 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml510/leon3mp.vhd | 1 | 51,575 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_PCI;
-- Set this constant to 1 to include an APB bridge with the Logan logic
-- analyzer attached to the PCI signals
constant CFG_LOGAN : integer := 0;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apbi1 : apb_slv_in_type;
signal apbo, apbo1 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal opb_bus_errorl, plb_bus_errorl : std_ulogic;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
-- Logan signals
signal signals : std_logic_vector(63*CFG_LOGAN downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11 + CFG_LOGAN)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE,
CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
opb_bus_errorl <= not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#D00#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= not gpioo.val(0); -- Position on on GPIO DIP switch
plb_bus_errorl <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; plb_bus_errorl <= '0';
end generate;
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, opb_bus_errorl);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, plb_bus_errorl);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if CFG_MCTRL_LEON2 = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0, ahbsi, ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(63 downto 32*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1, ahbsi, ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_pads : iopadvv generic map (tech => padtech, width => 3, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 0), gpioo.dout(2 downto 0), gpioo.oen(2 downto 0),
gpioi.din(2 downto 0));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 7, pindex => 4, paddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH), ahbsi, ahbso(7));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech,
dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1,
dapbndx => 5, dapbaddr => 5, blength => blength,
mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 7, apbndx => 4, apbaddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5),
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
ahbsi, ahbso(7));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 12, paddr => 16#100#, pmask => 16#f00#)
port map (rstn, clkm, pciclk, pcii, apbi, apbo(12));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_PCI = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_PCI /= 2 and CFG_PCI /= 3 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- APB bridge with LOGAN --------------------------------------------
-----------------------------------------------------------------------
-- log: if CFG_LOGAN = 1 generate -- Logan is enabled by constant
-- -- declared above
-- apb0 : apbctrl -- AHB/APB bridge
-- generic map (hindex => 11, haddr => 16#F00#, nslaves => 1)
-- port map (rstn, clkm, ahbsi, ahbso(11), apbi1, apbo1);
-- logan0 : logan -- Logic analyzer
-- generic map (dbits => 64, depth => 4096, trigl => 2, usereg => 1,
-- usequal => 0, pindex => 0, paddr => 0, pmask => 16#F00#,
-- memtech => memtech)
-- port map (rstn, clkm, pciclk, apbi1, apbo1(0), signals);
-- signals(0) <= pcii.rst;
-- signals(1) <= pcii.gnt;
-- signals(2) <= pcii.idsel;
-- signals(34 downto 3) <= pcii.ad;
-- signals(38 downto 35) <= pcii.cbe;
-- signals(39) <= pcii.frame;
-- signals(40) <= pcii.irdy;
-- signals(41) <= pcii.trdy;
-- signals(42) <= pcii.devsel;
-- signals(43) <= pcii.stop;
-- signals(44) <= pcii.lock;
-- signals(45) <= pcii.perr;
-- signals(46) <= pcii.serr;
-- signals(47) <= pcii.par;
-- signals(48) <= pcii.host;
-- signals(49) <= pcii.pci66;
-- signals(53 downto 50) <= pcii.int;
-- signals(58 downto 54) <= pci_arb_gnt(0 to 4);
-- signals(63 downto 59) <= pci_arb_req(0 to 4);
-- end generate log;
nolog: if CFG_LOGAN /= 1 generate
signals <= (others => '0');
end generate nolog;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 8bce9f6dc6b440b040d0b761063a1433 | 0.577625 | 3.272525 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-pci-xc2v3000/config.vhd | 1 | 6,842 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000006#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 4ab635ae78549d1763696474c8b9d6f5 | 0.645718 | 3.593487 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/ddr_phy_inferred.vhd | 1 | 16,449 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
| gpl-2.0 | 1328c5422d4e0923954c845bb1fc363e | 0.500334 | 3.732471 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/bftLib/core_transform.vhdl | 1 | 3,812 | --/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. This notice
--// refers to original work by Xilinx, Inc. which may be derivitive
--// of other work distributed under license of the authors. In the
--// case of derivitive work, nothing in this notice overrides the
--// original author's license agreeement. Where applicable, the
--// original license agreement is included in it's original
--// unmodified form immediately below this header.
--//
--// Xilinx, Inc.
--// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
--// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
--// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
--// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
--// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
--// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
--// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
--// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
--// AND FITNESS FOR A PARTICULAR PURPOSE.
--//
--/////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity coreTransform is
generic (
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
x, xStep, u : in std_logic_vector (DATA_WIDTH-1 downto 0);
xOut, xOutStep : out std_logic_vector (DATA_WIDTH-1 downto 0)
);
--synthesis packing can change the resutls greatly
--setting up some attributes to force the mapping I want
--attribute register_duplication : string;
--attribute register_duplication of coreTransform : entity is "yes";
--attribute register_balancing : string;
--attribute register_balancing of coreTransform : entity is "yes";
----force a mapping to DSP48s
attribute use_dsp48 : string;
attribute use_dsp48 of coreTransform : entity is "yes";
----turn off resource sharing
----with resource sharing off this will map to two dsp48s. With it on, a dsp48 and some logic.
attribute resource_sharing : string;
attribute resource_sharing of coreTransform : entity is "no";
end entity coreTransform;
architecture aCT of coreTransform is
signal xReg, xStepReg, uReg : std_logic_vector (DATA_WIDTH-1 downto 0);
signal xOutReg, xOutStepReg, xOutRegTemp, xOutStepRegTemp: std_logic_vector (2*DATA_WIDTH -1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
xStepReg <= xStep;
uReg <= u;
xReg <= x;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
xOutReg <= SXT(xReg, 2*DATA_WIDTH) + uReg*xStepReg;
xOutStepReg <= SXT(xReg, 2*DATA_WIDTH) - uReg*xStepReg;
end if;
end process;
-- xOut <= xOutReg(DATA_WIDTH-1 downto 0) xor xOutReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
-- xOutStep <= xOutStepReg(DATA_WIDTH-1 downto 0) xor xOutStepReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
xOut <= xOutReg(DATA_WIDTH-1 downto 0) xor xOutReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
xOutStep <= xOutStepReg(DATA_WIDTH-1 downto 0) xor xOutStepReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
end architecture aCT;
| gpl-2.0 | 930514b635ec052c7721e634aec449ab | 0.650839 | 3.92585 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddrphy_wrap.vhd | 1 | 57,878 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_phy
-- File: ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Wrapper entities for techmap ddrphy/ddr2phy
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY wrapper -------------------------------------------------------
------------------------------------------------------------------
entity ddrphy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap is
begin
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(13 downto 0), sdo.ba(1 downto 0),
sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0),
sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke, sdo.sdck(2 downto 0), sdo.moben,
sdi.datavalid, testen, testrst, scanen, testoen);
drvdata : if dbits < 64 generate
sdi.data(127 downto dbits*2) <= (others => '0');
end generate;
sdi.cb <= (others => '0'); sdi.regrdata <= (others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddrphy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
chkbits: integer := 0; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(abits-1 downto 0), sdo.ba(1 downto 0),
dqin, dqout,
dqm, sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke, sdck, sdo.moben,sdi.datavalid,
testen,testrst,scanen,testoen);
sdi.regrdata <= (others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddrphy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0; mobile : integer := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy_wo_pads
generic map (
tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew,
abits => abits, nclk => nclk, ncs => ncs, mobile => mobile, scantest => scantest, phyiconf => phyiconf)
port map (
rst => rst, clk => clk, clkout => clkout, clkoutret => clkoutret,
lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba(1 downto 0), dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, ck => sdck, moben => sdo.moben, dqvalid => sdi.datavalid,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
sdi.regrdata <= (others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY wrapper -----------------------------------------------
------------------------------------------------------------------
-------------------------------------------------------------------------------
-- There are three variants of the PHY wrapper depending on pads/checkbits:
-- 1. ddr2phy_wrap:
-- This provides pads and outputs checkbits on separate vectors
-- 2. ddr2phy_wrap_cbd:
-- This provides pads and merges checkbits+data on same vector
-- 3. ddr2phy_wrap_cbd_wo_pads:
-- This does not provide pads and merges checkbits+data on same vectors
--
-- Variants (1),(3) can not be used when ddr2phy_builtin_pads(tech)=1
-------------------------------------------------------------------------------
entity ddr2phy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector ((dbits+padbits)-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture rtl of ddr2phy_wrap is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_ulogic;
signal lddr_cke,lddr_csb,lddr_odt: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_ulogic;
signal lddr_dm,lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector((dbits+padbits+chkbits)/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits+padbits+chkbits-1 downto 0);
begin
-- Instantiate PHY without pads via other wrapper
w0: ddr2phy_wrap_cbd_wo_pads
generic map (tech,MHz,rstdelay,dbits,padbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,ddelayb4,ddelayb5,ddelayb6,ddelayb7,
cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,
numidelctrl,norefclk,odten,rskew,
eightbanks,dqsse,abits,nclk,ncs,chkbits,resync,custombits,scantest)
port map (
rst,clk,clkref200,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,
lddr_odt,
sdi,sdo,customclk,customdin,customdout,testen,testrst,scanen,testoen);
-- Instantiate pads for control signals and data bus
p0: ddr2pads
generic map (tech,dbits+padbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (
ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,
ddr_dm,ddr_dqs,ddr_dqsn,ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,
lddr_dm(dbits/8+padbits/8-1 downto 0),
lddr_dqs_in(dbits/8+padbits/8-1 downto 0),
lddr_dqs_out(dbits/8+padbits/8-1 downto 0),
lddr_dqs_oen(dbits/8+padbits/8-1 downto 0),
lddr_ad,lddr_ba,
lddr_dq_in(dbits+padbits-1 downto 0),
lddr_dq_out(dbits+padbits-1 downto 0),
lddr_dq_oen(dbits+padbits-1 downto 0),
lddr_odt);
-- Instantiate pads for checkbit bus
cbdqpad: iopadvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits)
port map (pad => ddr_cbdq,
i => lddr_dq_out(dbits+padbits+chkbits-1 downto dbits+padbits),
en => lddr_dq_oen(dbits+padbits+chkbits-1 downto dbits+padbits),
o => lddr_dq_in(dbits+padbits+chkbits-1 downto dbits+padbits));
cbdqmpad: outpadv
generic map (tech => tech, slew => 1, level => sstl18_i, width => chkbits/8)
port map (pad => ddr_cbdm,
i => lddr_dm(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
cbdqspad: iopad_dsvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits/8)
port map (padp => ddr_cbdqs, padn => ddr_cbdqsn,
i => lddr_dqs_out(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
en => lddr_dqs_oen(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
o => lddr_dqs_in(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddr2phy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8; extraio : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs,
ctrl2en => ctrl2en, resync => resync, custombits => custombits, extraio => extraio,
scantest => scantest)
port map (
rst, clk, clkref200, clkout, clkoutret, clkresync, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
sdo.address(abits-1 downto 0), sdo.ba,
dqin, dqout,
dqm, sdo.bdrive, sdo.nbdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke,
cal_en, cal_inc,
sdo.cal_pll, sdo.cal_rst, odt, sdo.oct, sdo.read_pend,
sdo.regwdata, sdo.regwrite, sdi.regrdata, sdi.datavalid,
customclk, customdin, customdout,
ddr_web2, ddr_rasb2, ddr_casb2, ddr_ad2, ddr_ba2,
testen, testrst, scanen, testoen
);
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy_wo_pads
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs, resync => resync, custombits => custombits,
scantest => scantest)
port map (
rst => rst, clk => clk, clkref => clkref200, clkout => clkout, clkoutret => clkoutret,
clkresync => clkresync, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
ddr_odt => ddr_odt,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba, dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive, noen => sdo.nbdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, cal_en => cal_en, cal_inc => cal_inc, cal_pll => sdo.cal_pll, cal_rst => sdo.cal_rst, odt => odt,
oct => sdo.oct, read_pend => sdo.read_pend, regwdata => sdo.regwdata, regwrite => sdo.regwrite,
regrdata => sdi.regrdata, dqin_valid => sdi.datavalid,
customclk => customclk, customdin => customdin, customdout => customdout,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
end;
------------------------------------------------------------------
-- LPDDR2/LPDDR3 PHY with checkbits merged on data bus, no pads --
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of lpddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits+padbits+chkbits,
nclk => nclk,
ncs => ncs,
clkratio => 1,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => sdo.ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dqm,
ckstop => sdo.sdck(0),
boot => sdo.boot,
wrpend => sdo.wrpend,
rdpend => sdo.read_pend,
wrreq(0) => sdi.writereq,
rdvalid(0) => sdi.datavalid,
refcal => '0',
refcalwu => '0',
refcaldone => open,
phycmd => "00000000",
phycmden => '0',
phycmdin => x"00000000",
phycmdout => open,
testen => '0',
testrst => '1',
scanen => '0',
testoen => '0'
);
sdi.regrdata <= (others => '0');
end;
| gpl-2.0 | 8bab2567d3f9b14edb2e70c0cf7281f8 | 0.570441 | 3.393609 | false | false | false | false |
Yuriu5/MiniBlaze | src/peripherals/UART.vhd | 1 | 11,862 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : UART
-- Date : 07/25/2016
--
-- Description :
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/25/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/25/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART is
generic (
CLK_IN : integer := 10000000;
BAUDRATE : integer := 115200;
DATA_BITS : integer := 8;
STOP_BITS : integer := 1;
USE_PARITY : integer := 0;
ODD_PARITY : integer := 0
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- User intf
data_in : in std_logic_vector(DATA_BITS-1 downto 0);
data_in_en : in std_logic;
data_in_ack : out std_logic;
data_out : out std_logic_vector(DATA_BITS-1 downto 0);
data_out_en : out std_logic;
frame_error : out std_logic;
parity_error : out std_logic;
-- TX/RX
RX : in std_logic;
TX : out std_logic
);
end UART;
architecture rtl of UART is
function CALC_RATIO ( C_BAUDRATE : integer; C_CLKIN : integer) return integer is
constant C_RATIO : integer := C_CLKIN/C_BAUDRATE;
constant C_REMAIN : integer := C_CLKIN rem C_BAUDRATE;
begin
if C_BAUDRATE/2 < C_REMAIN then
return C_RATIO;
else
return C_RATIO + 1;
end if;
end function CALC_RATIO;
constant c_nb_clk_per_bit : integer := CALC_RATIO(BAUDRATE, CLK_IN);
constant c_nb_clk_per_bit_div2 : integer := c_nb_clk_per_bit/2;
-- RX
type fsm_rx is (st_wait_start_bit, st_get_data, st_get_stop_bit);
signal r_fsm_rx : fsm_rx := st_wait_start_bit;
signal r_RX : std_logic := '0';
signal r2_RX : std_logic := '0';
signal r_data_rx : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_data_rx_en : std_logic := '0';
signal r_cnt_bit_uart : unsigned(31 downto 0) := (others => '0');
signal r_cnt_data : unsigned(31 downto 0) := (others => '0');
signal r_cnt_stop : unsigned(31 downto 0) := (others => '0');
signal r_frame_error : std_logic := '0';
-- TX
type fsm_tx is (st_wait_data, st_send_start, st_send_data, st_send_stop, st_wait_1b_for_ack);
signal r_fsm_tx : fsm_tx := st_wait_data;
signal r_cnt_bit_uart_tx : unsigned(31 downto 0) := (others => '0');
signal r_cnt_data_tx : unsigned(31 downto 0) := (others => '0');
signal r_cnt_stop_tx : unsigned(31 downto 0) := (others => '0');
signal r_data_in : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_data_in_en : std_logic := '0';
signal r_TX : std_logic := '1';
signal r_data_tx : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_tx_ack : std_logic := '0';
begin
-- ---------------------------------------------
-- RX side
-- ---------------------------------------------
p_pipe_in : process(clk) -- Two pipes to avoid metastability
begin
if rising_edge(clk) then
r_RX <= RX;
r2_RX <= r_RX;
end if;
end process;
p_RX : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
r_fsm_rx <= st_wait_start_bit;
r_data_rx_en <= '0';
else
-- default values
r_data_rx_en <= '0';
case r_fsm_rx is
when st_wait_start_bit =>
if r2_RX = '0' then
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
else
r_cnt_bit_uart <= (others => '0');
end if;
if r_cnt_bit_uart = c_nb_clk_per_bit_div2 - 1 then
r_fsm_rx <= st_get_data;
r_cnt_bit_uart <= (others => '0');
r_cnt_data <= (others => '0');
r_cnt_stop <= (others => '0');
r_frame_error <= '0';
end if;
when st_get_data => -- Sample at the center of each bit
if r_cnt_bit_uart = c_nb_clk_per_bit - 1 then
r_data_rx(to_integer(r_cnt_data)) <= r2_RX;
r_cnt_bit_uart <= (others => '0');
if r_cnt_data = DATA_BITS - 1 then
r_fsm_rx <= st_get_stop_bit;
else
r_cnt_data <= r_cnt_data + 1;
end if;
else
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
end if;
when st_get_stop_bit =>
if r_cnt_bit_uart = c_nb_clk_per_bit - 1 then
if r2_RX = '0' then -- NOK
r_cnt_bit_uart <= (others => '0');
r_fsm_rx <= st_wait_start_bit;
r_frame_error <= '1';
else -- OK
if r_cnt_stop = STOP_BITS - 1 then
r_fsm_rx <= st_wait_start_bit;
r_data_rx_en <= '1';
else
r_cnt_stop <= r_cnt_stop + 1;
r_cnt_bit_uart <= (others => '0');
end if;
end if;
else
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
end if;
when others =>
r_fsm_rx <= st_wait_start_bit;
end case;
end if;
end if;
end process;
data_out <= r_data_rx;
data_out_en <= r_data_rx_en;
-- ---------------------------------------------
-- TX side
-- ---------------------------------------------
p_pipe_tx_in : process(clk)
begin
if rising_edge(clk) then
r_data_in <= data_in;
r_data_in_en <= data_in_en;
end if;
end process;
p_TX : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_data_tx <= (others => '0');
r_cnt_stop_tx <= (others => '0');
r_fsm_tx <= st_wait_data;
r_TX <= '1';
else
-- Default values
r_tx_ack <= '0';
case r_fsm_tx is
when st_wait_data =>
r_TX <= '1';
if r_data_in_en = '1' then
r_data_tx <= r_data_in;
r_fsm_tx <= st_send_start;
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_data_tx <= (others => '0');
r_cnt_stop_tx <= (others => '0');
end if;
when st_send_start =>
r_TX <= '0';
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_bit_uart_tx <= (others => '0');
r_fsm_tx <= st_send_data;
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
when st_send_data =>
if r_cnt_data_tx = DATA_BITS then
r_fsm_tx <= st_send_stop;
r_TX <= '1';
else
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_data_tx <= r_cnt_data_tx + 1;
r_cnt_bit_uart_tx <= (others => '0');
r_data_tx <= r_data_tx(0) & r_data_tx(DATA_BITS - 1 downto 1);
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
r_TX <= r_data_tx(0);
end if;
end if;
when st_send_stop =>
r_TX <= '1';
if r_cnt_stop_tx = STOP_BITS -1 then
r_fsm_tx <= st_wait_1b_for_ack;
r_cnt_bit_uart_tx <= (others => '0');
else
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_stop_tx <= r_cnt_stop_tx + 1;
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
end if;
when st_wait_1b_for_ack =>
r_TX <= '1';
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_fsm_tx <= st_wait_data;
r_tx_ack <= '1';
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
when others =>
r_fsm_tx <= st_wait_data;
end case;
end if;
end if;
end process;
TX <= r_TX;
data_in_ack <= r_tx_ack;
end;
| mit | 63f42e87b07217dded5d300758df35df | 0.386023 | 3.999326 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_scc_wr.vhd | 13 | 44,376 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc_wr.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc_wr is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc_wr;
architecture implementation of axi_sg_scc_wr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_cmd2addr_valid1 : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= (others => '1'); --sig_next_strt_strb; -- always F
mstr2data_last_strb <= (others => '1'); --sig_next_end_strb; -- always F
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
-- mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_cmd_valid <= sig_cmd2addr_valid1; --sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
WR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00000000" when sig_cmd_tag_reg (0) = '1'
else "00000101"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate WR_EXTRA_FIELDS;
NOWR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000000";
end generate NOWR_EXTRA_FIELDS;
-- sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd2addr_valid1 <= '1';
sig_cmd_burst_reg <= sig_next_burst;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
elsif (sig_btt_is_zero_reg = '1') then
sm_set_error <= '1';
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
-- sm_set_error <= sm_set_error_ns ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
| gpl-3.0 | 96fe44f55d29501cc9aff291722adf2f | 0.440891 | 4.716837 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/example_design/side_prod.vhd | 1 | 9,891 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: side_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : side.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 76800
-- C_READ_DEPTH_A : 76800
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 76800
-- C_READ_DEPTH_B : 76800
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY side_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END side_prod;
ARCHITECTURE xilinx OF side_prod IS
COMPONENT side_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : side_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 647cf060539644620b57709379457c62 | 0.493984 | 3.835207 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/mul_inferred.vhd | 1 | 4,244 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
| gpl-2.0 | 3f2f71ec8eb001a17149b935abd97ace | 0.56951 | 3.566387 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/keyboard/debounce.vhd | 1 | 2,498 | --------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 3/26/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity debounce is
generic(
counter_size : integer --! counter size (19 bits gives 10.5ms with 50MHz clock)
);
port(
clk : in std_logic; --! input clock
button : in std_logic; --! input signal to be debounced
result : out std_logic --! debounced signal
);
end debounce;
architecture debounce of debounce is
signal flipflops : std_logic_vector(1 downto 0); --input flip flops
signal counter_set : std_logic; --sync reset to zero
signal counter_out : std_logic_vector(counter_size downto 0) := (others => '0'); --counter output
begin
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
pr_deb: process(clk)
begin
if (clk'event and clk = '1') then
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
if (counter_set = '1') then --reset counter because input is changing
counter_out <= (others => '0');
elsif (counter_out(counter_size) = '0') then --stable input time is not yet met
counter_out <= counter_out + 1;
else --stable input time is met
result <= flipflops(1);
end if;
end if;
end process;
end debounce; | mit | ab0d1eb681b87232402c4178e26f1512 | 0.580064 | 4.321799 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-sdr/config.vhd | 1 | 5,586 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 43a50b3a7ca53553a0e7258e17f2a461 | 0.645184 | 3.670171 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-115/testbench.vhd | 1 | 7,756 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library hynix;
use hynix.components.all;
use hynix.HY5PS121621F_PACK.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_zio : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(2 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.05 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
u0 : HY5PS121621F
generic map (TimingCheckFlag => false, PUSCheckFlag => false,
index => 0, bbits => 16, fname => sdramfile,
fdelay => 115, part_number => B800)
port map (DQ => mcb3_dram_dq,
LDQS => mcb3_dram_dqs, LDQSB => mcb3_dram_dqs_n,
UDQS => mcb3_dram_udqs, UDQSB => mcb3_dram_udqs_n,
LDM => mcb3_dram_dm, WEB => mcb3_dram_we_n,
CASB => mcb3_dram_cas_n, RASB => mcb3_dram_ras_n,
CSB => csb, BA => mcb3_dram_ba(1 downto 0), ADDR => mcb3_dram_a,
CKE => mcb3_dram_cke, CLK => mcb3_dram_ck,
CLKB => mcb3_dram_ck_n, UDM => mcb3_dram_udm);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | 855131504a4f344108d4444e2b14a596 | 0.54835 | 3.318785 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/image_filter_Mat2AXIvideo.vhd | 2 | 23,118 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Mat2AXIvideo is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of image_filter_Mat2AXIvideo is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_sig_bdd_60 : BOOLEAN;
signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0);
signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_85 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_99 : BOOLEAN;
signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0);
signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_130 : BOOLEAN;
signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0';
signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_cast_35_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. --
ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_3_reg_170 assign process. --
p_3_reg_170_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
p_3_reg_170 <= j_V_fu_213_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then
p_3_reg_170 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_s_reg_159 assign process. --
p_s_reg_159_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then
p_s_reg_159 <= i_V_reg_276;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
p_s_reg_159 <= ap_const_lv12_0;
end if;
end if;
end process;
-- tmp_user_V_fu_96 assign process. --
tmp_user_V_fu_96_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
tmp_user_V_fu_96 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
tmp_user_V_fu_96 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then
axi_last_V_reg_290 <= axi_last_V_fu_223_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
exitcond4_reg_281 <= exitcond4_fu_208_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_276 <= i_V_fu_202_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then
op2_assign_reg_267 <= op2_assign_fu_186_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_60)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st5_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st5_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout);
OUTPUT_STREAM_TDEST <= ap_const_lv1_0;
OUTPUT_STREAM_TID <= ap_const_lv1_0;
OUTPUT_STREAM_TKEEP <= ap_const_lv4_F;
OUTPUT_STREAM_TLAST <= axi_last_V_reg_290;
OUTPUT_STREAM_TSTRB <= ap_const_lv4_0;
OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96;
-- OUTPUT_STREAM_TVALID assign process. --
OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then
OUTPUT_STREAM_TVALID <= ap_const_logic_1;
else
OUTPUT_STREAM_TVALID <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_60 assign process. --
ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_85 assign process. --
ap_sig_bdd_85_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_99 assign process. --
ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281)
begin
ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_3 assign process. --
ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. --
ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then
ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
else
ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end if;
end process;
axi_last_V_fu_223_p2 <= "1" when (tmp_cast_35_fu_219_p1 = op2_assign_reg_267) else "0";
exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0";
exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0";
i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1));
-- img_data_stream_0_V_read assign process. --
img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_0_V_read <= ap_const_logic_1;
else
img_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- img_data_stream_1_V_read assign process. --
img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_1_V_read <= ap_const_logic_1;
else
img_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- img_data_stream_2_V_read assign process. --
img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
img_data_stream_2_V_read <= ap_const_logic_1;
else
img_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1));
op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF));
tmp_cast_35_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13));
tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13));
end behav;
| gpl-3.0 | ab320e548b93e556b0b39b0d0b86ba4f | 0.592093 | 2.795067 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/micron/ddr_sdram/mt46v16m16.vhd | 1 | 62,181 | -----------------------------------------------------------------------------------------
--
-- File Name: MT46V16M16.VHD
-- Version: 3.1
-- Date: January 14th, 2002
-- Model: Behavioral
-- Simulator: NCDesktop - http://www.cadence.com
-- ModelSim PE - http://www.model.com
--
-- Dependencies: None
--
-- Email: [email protected]
-- Company: Micron Technology, Inc.
-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
--
-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
--
-- Limitation: Doesn't model internal refresh counter
--
-- Note:
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Date Changes
-- --- ---------------------------- ---------- -------------------------------------
-- 2.1 SH 01/14/2002 - Fix Burst_counter
-- Micron Technology, Inc.
--
-- 2.0 SH 11/08/2001 - Second release
-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
-- 3.1 Craig Hanson cahanson 05/28/2003 - update all models to release version 3.1
-- @micron.com (no changes to this model)
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY MT46V16M16 IS
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
bbits : INTEGER := 16;
fdelay : INTEGER := 0;
chktiming : boolean := true -- Perform timing checks
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END MT46V16M16;
ARCHITECTURE behave OF MT46V16M16 IS
-- Array for Read pipeline
TYPE Array_Read_cmnd IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Read_bank IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Read_cols IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Write pipeline
TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Auto Precharge
TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-- Array for Manual Precharge
TYPE Array_A10_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Bank_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Cmnd_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC;
-- Array for Burst Terminate
TYPE Array_Cmnd_bst IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC;
-- Array for Memory Access
TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
TYPE Array_ram_pntr IS ACCESS Array_ram_type;
TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-- Data pair
SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-- Mode Register
SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Command Decode Variables
SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-- Burst Length Decode Variables
SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-- Cas Latency Decode Variables
SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-- Internal Control Signals
SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-- System Clock
SIGNAL Sys_clk : STD_LOGIC := '0';
-- Dqs buffer
SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
BEGIN
-- Strip the strength
Cs_in <= To_X01 (Cs_n);
Ras_in <= To_X01 (Ras_n);
Cas_in <= To_X01 (Cas_n);
We_in <= To_X01 (We_n);
-- Commands Decode
Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-- Dqs buffer
Dqs <= Dqs_out;
--
-- System Clock
--
int_clk : PROCESS (Clk, Clk_n)
VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
begin
IF Clk = '1' AND Clk_n = '0' THEN
ClkZ := '1';
CkeZ := Cke;
ELSIF Clk = '0' AND Clk_n = '1' THEN
ClkZ := '0';
END IF;
Sys_clk <= CkeZ AND ClkZ;
END PROCESS;
--
-- Main Process
--
state_register : PROCESS
-- Precharge Variables
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-- Activate Variables
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-- Data IO variables
VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-- Internal address mux variables
VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-- DLL Reset variables
VARIABLE DLL_enable : STD_LOGIC := '0';
VARIABLE DLL_reset : STD_LOGIC := '0';
VARIABLE DLL_done : STD_LOGIC := '0';
VARIABLE DLL_count : INTEGER := 0;
-- Timing Check
VARIABLE MRD_chk : TIME := 0 ns;
VARIABLE RFC_chk : TIME := 0 ns;
VARIABLE RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-- Read pipeline variables
VARIABLE Read_cmnd : Array_Read_cmnd;
VARIABLE Read_bank : Array_Read_bank;
VARIABLE Read_cols : Array_Read_cols;
-- Write pipeline variables
VARIABLE Write_cmnd : Array_Write_cmnd;
VARIABLE Write_bank : Array_Write_bank;
VARIABLE Write_cols : Array_Write_cols;
-- Auto Precharge variables
VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-- Manual Precharge variables
VARIABLE A10_precharge : Array_A10_precharge;
VARIABLE Bank_precharge : Array_Bank_precharge;
VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-- Burst Terminate variable
VARIABLE Cmnd_bst : Array_Cmnd_bst;
-- Memory Banks
VARIABLE Bank0 : Array_ram_stor;
VARIABLE Bank1 : Array_ram_stor;
VARIABLE Bank2 : Array_ram_stor;
VARIABLE Bank3 : Array_ram_stor;
-- Burst Counter
VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Internal Dqs initialize
VARIABLE Dqs_int : STD_LOGIC := '0';
-- Data buffer for DM Mask
VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE Bank_Load : std_logic_vector ( 1 DOWNTO 0);
VARIABLE Rows_Load : std_logic_vector (addr_bits-1 DOWNTO 0);
VARIABLE Cols_Load : std_logic_vector ( cols_bits-1 DOWNTO 0);
VARIABLE Data_Load : std_logic_vector (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable file_loaded : boolean := false;
variable dump : std_logic := '0';
variable ch : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
--
-- Initialize empty rows
--
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
--
-- Burst Counter
--
PROCEDURE Burst_decode IS
VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance burst counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Cols_temp := Cols_addr + 1;
ELSIF Mode_reg (3) = '1' THEN
Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Cols_addr (0) := Cols_temp (0);
ELSIF Burst_length_4 = '1' THEN
Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
ELSE
Cols_addr := Cols_temp;
END IF;
-- Data counter
IF Burst_length_2 = '1' THEN
IF conv_integer(Burst_counter) >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF conv_integer(Burst_counter) >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF conv_integer(Burst_counter) >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk;
--
-- Manual Precharge Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- A10 Precharge Pipeline
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := A10_precharge(4);
A10_precharge(4) := A10_precharge(5);
A10_precharge(5) := A10_precharge(6);
A10_precharge(6) := A10_precharge(7);
A10_precharge(7) := A10_precharge(8);
A10_precharge(8) := '0';
-- Bank Precharge Pipeline
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := Bank_precharge(4);
Bank_precharge(4) := Bank_precharge(5);
Bank_precharge(5) := Bank_precharge(6);
Bank_precharge(6) := Bank_precharge(7);
Bank_precharge(7) := Bank_precharge(8);
Bank_precharge(8) := "00";
-- Command Precharge Pipeline
Cmnd_precharge(0) := Cmnd_precharge(1);
Cmnd_precharge(1) := Cmnd_precharge(2);
Cmnd_precharge(2) := Cmnd_precharge(3);
Cmnd_precharge(3) := Cmnd_precharge(4);
Cmnd_precharge(4) := Cmnd_precharge(5);
Cmnd_precharge(5) := Cmnd_precharge(6);
Cmnd_precharge(6) := Cmnd_precharge(7);
Cmnd_precharge(7) := Cmnd_precharge(8);
Cmnd_precharge(8) := '0';
-- Terminate Read if same bank or all banks
IF ((Cmnd_precharge (0) = '1') AND
(Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
(Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Burst Terminate Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Burst Terminate pipeline
Cmnd_bst (0) := Cmnd_bst (1);
Cmnd_bst (1) := Cmnd_bst (2);
Cmnd_bst (2) := Cmnd_bst (3);
Cmnd_bst (3) := Cmnd_bst (4);
Cmnd_bst (4) := Cmnd_bst (5);
Cmnd_bst (5) := Cmnd_bst (6);
Cmnd_bst (6) := Cmnd_bst (7);
Cmnd_bst (7) := Cmnd_bst (8);
Cmnd_bst (8) := '0';
-- Terminate current Read
IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Dq and Dqs Drivers
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Read Command Pipeline
Read_cmnd (0) := Read_cmnd (1);
Read_cmnd (1) := Read_cmnd (2);
Read_cmnd (2) := Read_cmnd (3);
Read_cmnd (3) := Read_cmnd (4);
Read_cmnd (4) := Read_cmnd (5);
Read_cmnd (5) := Read_cmnd (6);
Read_cmnd (6) := Read_cmnd (7);
Read_cmnd (7) := Read_cmnd (8);
Read_cmnd (8) := '0';
-- Read Bank Pipeline
Read_bank (0) := Read_bank (1);
Read_bank (1) := Read_bank (2);
Read_bank (2) := Read_bank (3);
Read_bank (3) := Read_bank (4);
Read_bank (4) := Read_bank (5);
Read_bank (5) := Read_bank (6);
Read_bank (6) := Read_bank (7);
Read_bank (7) := Read_bank (8);
Read_bank (8) := "00";
-- Read Column Pipeline
Read_cols (0) := Read_cols (1);
Read_cols (1) := Read_cols (2);
Read_cols (2) := Read_cols (3);
Read_cols (3) := Read_cols (4);
Read_cols (4) := Read_cols (5);
Read_cols (5) := Read_cols (6);
Read_cols (6) := Read_cols (7);
Read_cols (7) := Read_cols (8);
Read_cols (8) := (OTHERS => '0');
-- Initialize Read command
IF Read_cmnd (0) = '1' THEN
Data_out_enable := '1';
Bank_addr := Read_bank (0);
Cols_addr := Read_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Toggle Dqs during Read command
IF Data_out_enable = '1' THEN
Dqs_int := '0';
IF Dqs_out = "00" THEN
Dqs_out <= "11";
ELSIF Dqs_out = "11" THEN
Dqs_out <= "00";
ELSE
Dqs_out <= "00";
END IF;
ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
Dqs_out <= "ZZ";
END IF;
-- Initialize Dqs for Read command
IF Read_cmnd (2) = '1' THEN
IF Data_out_enable = '0' THEN
Dqs_int := '1';
Dqs_out <= "00";
END IF;
END IF;
-- Read Latch
IF Data_out_enable = '1' THEN
-- Initialize Memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Output Data
CASE Bank_addr IS
WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Increase Burst Counter
Burst_decode;
ELSE
Dq <= (OTHERS => 'Z');
END IF;
END IF;
--
-- Write FIFO and DM Mask Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Write command pipeline
Write_cmnd (0) := Write_cmnd (1);
Write_cmnd (1) := Write_cmnd (2);
Write_cmnd (2) := '0';
-- Write command pipeline
Write_bank (0) := Write_bank (1);
Write_bank (1) := Write_bank (2);
Write_bank (2) := "00";
-- Write column pipeline
Write_cols (0) := Write_cols (1);
Write_cols (1) := Write_cols (2);
Write_cols (2) := (OTHERS => '0');
-- Initialize Write command
IF Write_cmnd (0) = '1' THEN
Data_in_enable := '1';
Bank_addr := Write_bank (0);
Cols_addr := Write_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Write data
IF Data_in_enable = '1' THEN
-- Initialize memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Write first data
IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (0) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
END IF;
IF Dm_pair (1) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- Write second data
IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (2) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
END IF;
IF Dm_pair (3) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- tWR start and tWTR check
IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
CASE Bank_addr IS
WHEN "00" => WR_chk0 := NOW;
WHEN "01" => WR_chk1 := NOW;
WHEN "10" => WR_chk2 := NOW;
WHEN OTHERS => WR_chk3 := NOW;
END CASE;
-- tWTR check
ASSERT (Read_enable = '0')
REPORT "tWTR violation during Read"
SEVERITY WARNING;
END IF;
END IF;
END IF;
--
-- Auto Precharge Calculation
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Precharge counter
IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. BL/2 cycles after command
IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Read_precharge(0) := '0';
END IF;
END IF;
IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Read_precharge(1) := '0';
END IF;
END IF;
IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Read_precharge(2) := '0';
END IF;
END IF;
IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Read_precharge(3) := '0';
END IF;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. Two clock after last burst
-- Since tWR is time base, the model will compensate tRP
IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW - ((2 * tCK) - tWR);
Write_precharge(0) := '0';
END IF;
END IF;
IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW - ((2 * tCK) - tWR);
Write_precharge(1) := '0';
END IF;
END IF;
IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW - ((2 * tCK) - tWR);
Write_precharge(2) := '0';
END IF;
END IF;
IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW - ((2 * tCK) - tWR);
Write_precharge(3) := '0';
END IF;
END IF;
END IF;
--
-- DLL Counter
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
IF (DLL_Reset = '1' AND DLL_done = '0') THEN
DLL_count := DLL_count + 1;
IF (DLL_count >= 200) THEN
DLL_done := '1';
END IF;
END IF;
END IF;
--
-- Control Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RFC_chk >= tRFC) or (not chktiming)
REPORT "tRFC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
-- Record current tRFC time
RFC_chk := NOW;
END IF;
-- Extended Load Mode Register
IF Ext_mode_enable = '1' THEN
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
IF (Addr (0) = '0') THEN
DLL_enable := '1';
ELSE
DLL_enable := '0';
END IF;
END IF;
-- Precharge to EMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Extended Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming)
REPORT "tRP violation during Extended Load Register"
SEVERITY WARNING;
-- LMR/EMR to EMR
ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming)
REPORT "tMRD violation during Extended Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
-- Register mode
Mode_reg <= Addr;
-- DLL Reset
IF (DLL_enable = '1' AND Addr (8) = '1') THEN
DLL_reset := '1';
DLL_done := '0';
DLL_count := 0;
ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
ASSERT (FALSE)
REPORT "DLL is ENABLE: DLL RESET is require"
SEVERITY WARNING;
ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
ASSERT (FALSE)
REPORT "DLL is DISABLE: DLL RESET will be ignored"
SEVERITY WARNING;
END IF;
-- Precharge to LMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Load Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming)
REPORT "tRP violation during Load Mode Register"
SEVERITY WARNING;
-- LMR/ELMR to LMR
ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid Burst Length
ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
(Addr (2 DOWNTO 0) = "010") OR -- BL = 4
(Addr (2 DOWNTO 0) = "011")) -- BL = 8
REPORT "Invalid Burst Length during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid CAS Latency
ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
(Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
REPORT "Invalid CAS Latency during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
-- Activate an OPEN bank can corrupt data
ASSERT ((Ba = "00" AND Act_b0 = '0') OR
(Ba = "01" AND Act_b1 = '0') OR
(Ba = "10" AND Act_b2 = '0') OR
(Ba = "11" AND Act_b3 = '0'))
REPORT "Bank is already activated - data can be corrupted"
SEVERITY WARNING;
-- Activate Bank 0
IF Ba = "00" AND Pc_b0 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk0 >= tRC) or (not chktiming)
REPORT "tRC violation during Activate Bank 0"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk0 >= tRP) or (not chktiming)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := Addr;
RC_chk0 := NOW;
RCD_chk0 := NOW;
RAS_chk0 := NOW;
RAP_chk0 := NOW;
END IF;
-- Activate Bank 1
IF Ba = "01" AND Pc_b1 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk1 >= tRC) or (not chktiming)
REPORT "tRC violation during Activate Bank 1"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk1 >= tRP) or (not chktiming)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := Addr;
RC_chk1 := NOW;
RCD_chk1 := NOW;
RAS_chk1 := NOW;
RAP_chk1 := NOW;
END IF;
-- Activate Bank 2
IF Ba = "10" AND Pc_b2 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk2 >= tRC) or (not chktiming)
REPORT "tRC violation during Activate Bank 2"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk2 >= tRP) or (not chktiming)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := Addr;
RC_chk2 := NOW;
RCD_chk2 := NOW;
RAS_chk2 := NOW;
RAP_chk2 := NOW;
END IF;
-- Activate Bank 3
IF Ba = "11" AND Pc_b3 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk3 >= tRC) or (not chktiming)
REPORT "tRC violation during Activate Bank 3"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk3 >= tRP) or (not chktiming)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := Addr;
RC_chk3 := NOW;
RCD_chk3 := NOW;
RAS_chk3 := NOW;
RAP_chk3 := NOW;
END IF;
-- Activate Bank A to Activate Bank B
IF (Prev_bank /= Ba) THEN
ASSERT (NOW - RRD_chk >= tRRD) or (not chktiming)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- AutoRefresh to Activate
ASSERT (NOW - RFC_chk >= tRFC) or (not chktiming)
REPORT "tRFC violation during Activate"
SEVERITY WARNING;
-- Record Variables for Checking Violation
RRD_chk := NOW;
Prev_bank := Ba;
END IF;
-- Precharge Block - Consider NOP if bank already precharged or in process of precharging
IF Prech_enable = '1' THEN
-- EMR or LMR to Precharge
ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming)
REPORT "tMRD violation during Precharge"
SEVERITY WARNING;
-- Precharge Bank 0
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
Act_b0 := '0';
Pc_b0 := '1';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS) or (not chktiming)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk0 >= tWR) or (not chktiming)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 1
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
Act_b1 := '0';
Pc_b1 := '1';
RP_chk1 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk1 >= tRAS) or (not chktiming)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk1 >= tWR) or (not chktiming)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 2
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
Act_b2 := '0';
Pc_b2 := '1';
RP_chk2 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk2 >= tRAS) or (not chktiming)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk2 >= tWR) or (not chktiming)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 3
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
Act_b3 := '0';
Pc_b3 := '1';
RP_chk3 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk3 >= tRAS) or (not chktiming)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk3 >= tWR) or (not chktiming)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Pipeline for READ
IF CAS_latency_15 = '1' THEN
A10_precharge (3) := Addr(10);
Bank_precharge (3) := Ba;
Cmnd_precharge (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
A10_precharge (4) := Addr(10);
Bank_precharge (4) := Ba;
Cmnd_precharge (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
A10_precharge (5) := Addr(10);
Bank_precharge (5) := Ba;
Cmnd_precharge (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
A10_precharge (6) := Addr(10);
Bank_precharge (6) := Ba;
Cmnd_precharge (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
A10_precharge (8) := Addr(10);
Bank_precharge (8) := Ba;
Cmnd_precharge (8) := '1';
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Pipeline for Read
IF CAS_latency_15 = '1' THEN
Cmnd_bst (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
Cmnd_bst (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
Cmnd_bst (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
Cmnd_bst (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
Cmnd_bst (8) := '1';
END IF;
-- Terminate Write
ASSERT (Data_in_enable = '0')
REPORT "It's illegal to Burst Terminate a Write"
SEVERITY WARNING;
-- Terminate Read with Auto Precharge
ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
Read_precharge (2) = '0' AND Read_precharge (3) = '0')
REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_15 = '1' THEN
Read_cmnd (3) := '1';
Read_bank (3) := Ba;
Read_cols (3) := Addr (cols_bits-1 DOWNTO 0);
ELSIF Cas_latency_2 = '1' THEN
Read_cmnd (4) := '1';
Read_bank (4) := Ba;
Read_cols (4) := Addr (cols_bits-1 DOWNTO 0);
ELSIF Cas_latency_25 = '1' THEN
Read_cmnd (5) := '1';
Read_bank (5) := Ba;
Read_cols (5) := Addr (cols_bits-1 DOWNTO 0);
ELSIF Cas_latency_3 = '1' THEN
Read_cmnd (6) := '1';
Read_bank (6) := Ba;
Read_cols (6) := Addr (cols_bits-1 DOWNTO 0);
ELSIF Cas_latency_4 = '1' THEN
Read_cmnd (8) := '1';
Read_bank (8) := Ba;
Read_cols (8) := Addr (cols_bits-1 DOWNTO 0);
END IF;
-- Write to Read: Terminate Write Immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Interrupting a Read with Auto Precharge (same bank only)
ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Read with Auto Precharge"
SEVERITY WARNING;
-- Activate to Read
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Read"
SEVERITY WARNING;
-- Activate to Read without Auto Precharge
IF Addr (10) = '0' THEN
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD)) or (not chktiming)
REPORT "tRCD violation during Read"
SEVERITY WARNING;
END IF;
-- Activate to Read with Auto Precharge
IF Addr (10) = '1' THEN
ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
(Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
(Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
(Ba = "11" AND NOW - RAP_chk3 >= tRAP)) or (not chktiming)
REPORT "tRAP violation during Read"
SEVERITY WARNING;
END IF;
-- Auto precharge
IF Addr (10) = '1' THEN
Read_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
-- DLL Check
IF (DLL_reset = '1') THEN
ASSERT (DLL_done = '1')
REPORT "DLL RESET not complete"
SEVERITY WARNING;
END IF;
END IF;
-- Write Command
IF Write_enable = '1' THEN
-- Pipeline for Write
Write_cmnd (2) := '1';
Write_bank (2) := Ba;
Write_cols (2) := Addr (cols_bits-1 DOWNTO 0);
-- Interrupting a Write with Auto Precharge (same bank only)
ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Write with Auto Precharge"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Write"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD)) or (not chktiming)
REPORT "tRCD violation during Write"
SEVERITY WARNING;
-- Auto precharge
IF Addr (10) = '1' THEN
Write_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
END IF;
END IF;
IF (now >= (fdelay * 1 us)) and not file_loaded THEN --'
file_loaded := true;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
when "0111" =>
hread(l, recaddr);
-- if (index = 0) then print("Start address : " & tost(recaddr)); end if;
next;
when others => next;
end case;
case bbits is
when 64 => -- 64-bit bank with four 16-bit DDRs
recaddr(31 downto 18+cols_bits) := (others => '0');
hread(l, recdata);
Bank_Load := recaddr(17+cols_bits downto 16+cols_bits);
Rows_Load := recaddr(15+cols_bits downto 3+cols_bits);
Cols_Load := recaddr(2+cols_bits downto 3);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
END IF;
when 32 => -- 32-bit bank with two 16-bit DDRs
recaddr(31 downto 17+cols_bits) := (others => '0');
hread(l, recdata);
Bank_Load := recaddr(16+cols_bits downto 15+cols_bits);
Rows_Load := recaddr(14+cols_bits downto 2+cols_bits);
Cols_Load := recaddr(1+cols_bits downto 2);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
END IF;
when others => -- 16-bit bank with one 16-bit DDR
hread(l, recdata);
recaddr(31 downto 16+cols_bits) := (others => '0');
Bank_Load := recaddr(15+cols_bits downto 14+cols_bits);
Rows_Load := recaddr(13+cols_bits downto 1+cols_bits);
Cols_Load := recaddr(cols_bits downto 1);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
END IF;
END case;
END IF;
END LOOP;
END IF;
END PROCESS;
--
-- Dqs Receiver
--
dqs_rcvrs : PROCESS
VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
BEGIN
WAIT ON Dqs;
-- Latch data at posedge Dqs
IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
Dq_temp := Dq;
Dm_temp := Dm;
END IF;
-- Latch data at negedge Dqs
IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
Dq_pair <= (Dq & Dq_temp);
Dm_pair <= (Dm & Dm_temp);
END IF;
END PROCESS;
--
-- Setup timing checks
--
Setup_check : PROCESS
BEGIN
WAIT ON Sys_clk;
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIS) or (not chktiming)
REPORT "CKE Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIS) or (not chktiming)
REPORT "CS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIS) or (not chktiming)
REPORT "CAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIS) or (not chktiming)
REPORT "RAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIS) or (not chktiming)
REPORT "WE# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIS) or (not chktiming)
REPORT "ADDR Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIS) or (not chktiming)
REPORT "BA Setup time violation -- tIS"
SEVERITY WARNING;
END IF;
END PROCESS;
--
-- Hold timing checks
--
Hold_check : PROCESS
BEGIN
WAIT ON Sys_clk'DELAYED (tIH);
IF Sys_clk'DELAYED (tIH) = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIH) or (not chktiming)
REPORT "CKE Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIH) or (not chktiming)
REPORT "CS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIH) or (not chktiming)
REPORT "CAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIH) or (not chktiming)
REPORT "RAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIH) or (not chktiming)
REPORT "WE# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIH) or (not chktiming)
REPORT "ADDR Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIH) or (not chktiming)
REPORT "BA Hold time violation -- tIH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
| gpl-2.0 | 26e31580908490c833985e09ba8542f4 | 0.450765 | 3.993385 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/net/net.vhd | 1 | 13,684 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for network cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package net is
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
rx_clk : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable: std_ulogic;
end record;
constant eth_in_none : eth_in_type :=
('0', '0', '0', '0', (others => '0'), '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type :=
('0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
type eth_sgmii_in_type is record
clkp : std_ulogic;
clkn : std_ulogic;
rxp : std_ulogic;
rxn : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
end record;
type eth_sgmii_out_type is record
reset : std_ulogic;
txp : std_ulogic;
txn : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
end record;
component eth_arb
generic(
fullduplex : integer := 0;
mdiomaster : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
ethi : in eth_in_type;
etho : out eth_out_type;
methi : in eth_out_type;
metho : out eth_in_type;
dethi : in eth_out_type;
detho : out eth_in_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
extclk : integer := 0;
clkdiv2 : integer := 0;
debugmem : integer := 0
);
port (
rstn : in std_ulogic;
clk_tx_g : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type ;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
end;
| gpl-2.0 | 4dbd3d0c6638b59a4e7b3c17b31216e0 | 0.48005 | 3.825552 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pci_target.vhd | 1 | 16,673 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_target
-- File: pci_target.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple PCI target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity pci_target is
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of pci_target is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_PCITRG, 0, REVISION, 0),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant zero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant pci_memory_read_m : word4 := "1100"; -- Aliased to Memory Read
constant pci_memory_read_l : word4 := "1110"; -- Aliased to Memory Read
constant pci_memory_write_i: word4 := "1111"; -- Aliased to Memory Write
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
data : std_logic_vector(31 downto 0);
cmd : std_logic_vector(3 downto 0);
state : pci_target_state_type;
csel : std_logic;
msel : std_logic;
read : std_logic;
devsel : std_logic;
trdy : std_logic;
stop : std_logic;
par : std_logic;
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
men : std_logic;
twist : std_logic;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
lsize : std_logic_vector(2 downto 0);
lwrite : std_logic;
start : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
end record;
type cpu_state_type is (idle, sync1, busy, sync2);
type cpu_reg_type is record
data : std_logic_vector(31 downto 0);
state : cpu_state_type;
start : std_logic_vector(csync downto 0);
sync : std_logic;
rready : std_logic;
wready : std_logic;
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is -- FIXME: this may need to be swaped
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := r.lsize; --"010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.lwrite; vdmai.irq := '0';
v.start(0) := r2.start(csync); v.start(csync) := r.start;
case r2.state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.lwrite = '1' then v.state := sync1; v.wready := '0';
else v.state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.lwrite; v.data := dmao.rdata(31 downto 0); v.state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
if rst = '0' then
v.state := idle; v.rready := '0'; v.wready := '1';
end if;
r2in <= v; dmai <= vdmai;
end process;
-- PCI target core (PCI clock domain)
pcicomb : process(pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite, mwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_ctrl, oe_par, oe_ad : std_ulogic;
begin
v := r; v.trdy := '1'; v.stop := '1'; voe_ad := roe_ad;
v.oe_ad := '1'; v.devsel := '1'; mwrite := '0';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
-- address decoding
--if (r.state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
if (r.state = turn_ar) and ((pr.irdy or pr.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
v.twist := pr.ad(0);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
mwrite := r.msel;
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.men; cdata(26) := '1';
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.men := cwdata(1);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write)
or (pr.cbe = pci_memory_read_m) or (pr.cbe = pci_memory_read_l) or (pr.cbe = pci_memory_write_i))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.state is
when idle =>
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.state := idle; end if;
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.state := idle; end if;
end case;
if ((r.state = s_data) or (r.state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.lwrite := not r.read; v.start := '1';
-- Added little/big endian support
v.laddr := v.laddr(31 downto 2) & set_addr_from_cbe(pr.cbe, r.twist);
v.ldata := byte_twist(v.ldata, r.twist);
v.lsize := '0' & set_size_from_cbe(pr.cbe);
end if;
end if;
if (v.state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
v.oe_par := r.oe_ad;
if r.csel = '1' then v.data := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
v.data(31 downto MADDR_WIDTH-1) := r.page;
v.data(MADDR_WIDTH-2 downto 0) := (others => '0');
v.data(0) := r.twist; -- Addded little/bit endian support
--else v.data := r2.data; end if;
else v.data := byte_twist(r2.data, r.twist); end if;
v.par := xorv(r.data & pcii.cbe);
if (v.state = s_data) or (r.state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
v.noe_ctrl := not v.oe_ctrl; v.noe_ad := not v.oe_ad; v.noe_par := not v.oe_par;
if oepol = 1 then
oe_ctrl := r.noe_ctrl; oe_ad := r.noe_ad; oe_par := r.noe_par;
voe_ad := (others => v.noe_ad);
else
oe_ctrl := r.oe_ctrl; oe_ad := r.oe_ad; oe_par := r.oe_par;
voe_ad := (others => v.oe_ad);
end if;
if pr.rst = '0' then
v.state := idle; v.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0');
v.page(31 downto 30) := "01";
v.twist := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.ctrlen <= oe_ctrl;
pcio.trdy <= r.trdy;
pcio.trdyen <= oe_ctrl;
pcio.stop <= r.stop;
pcio.stopen <= oe_ctrl;
pcio.devsel <= r.devsel;
pcio.devselen <= oe_ctrl;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.aden <= oe_ad;
pcio.ad <= r.data;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst, r2)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_ad <= '1';
r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_ad <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.cbeen <= (others => '1');
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.reqen <= not pcii.rst;
pcio.frameen <= '1';
pcio.irdyen <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.cbeen <= (others => '0');
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.reqen <= pcii.rst;
pcio.frameen <= '0';
pcio.irdyen <= '0';
pcio.locken <= '0';
end generate;
pcio.vaden <= roe_ad;
pcio.cbe <= "1111";
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
pcio.req <= '1';
pcio.frame <= '1';
pcio.irdy <= '1';
ahbmst0 : ahbmst generic map (hindex => hindex, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_target" & tost(hindex) &
": 32-bit PCI Target rev " & tost(REVISION) &
", " & tost(abits) & "-bit PCI memory BAR" );
-- pragma translate_on
end;
| gpl-2.0 | 1e9fbc3cc3e9c22dfa07ce2221726183 | 0.55179 | 2.974135 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_lite_if.vhd | 1 | 61,561 | -------------------------------------------------------------------------------
-- axi_cdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_cdma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_cdma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
-- ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
-- ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
-- ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
-- ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
-- ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
| gpl-3.0 | 95b0bfed1971dc1bff3addd4772f3fdd | 0.426374 | 4.122204 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_queue.vhd | 3 | 53,827 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
attribute mark_debug of updt_tvalid : signal is "true";
attribute mark_debug of updt2_tvalid : signal is "true";
attribute mark_debug of updt_tlast : signal is "true";
attribute mark_debug of updt2_tlast : signal is "true";
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_mm2s : signal is "true";
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_s2mm : signal is "true";
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
| gpl-3.0 | d9b76d8b94797ff9db15832593634ecb | 0.433834 | 4.277416 | false | false | false | false |
laurocruz/snakes_vhdl | src/snake_lib/snake_pack.vhd | 1 | 2,402 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE snake_pack IS
--TYPE int_s IS INTEGER RANGE -20 TO 255;
TYPE int_array IS array (0 to 127) OF INTEGER RANGE -20 TO 255;
COMPONENT conv_7seg IS
PORT (digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END COMPONENT;
COMPONENT create_food IS
-- Altura e comprimento do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
width : INTEGER := 6);
PORT (reset : IN STD_LOGIC;
eaten : IN STD_LOGIC;
gmap : IN STD_LOGIC_VECTOR(0 TO N*M-1);
new_food : OUT INTEGER RANGE 0 TO N*M-1);
END COMPONENT;
COMPONENT gclock IS
-- Frequencia de 1Hz
-- clock do hardware
PORT (CLOCK_27 : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
clock_out : OUT STD_LOGIC) ;
END COMPONENT;
COMPONENT make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock : IN STD_LOGIC;
-- reseta o jogo
reset : IN STD_LOGIC;
-- aumento do tamanho
eaten : IN STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
-- direcao para onde a cobra esta se movendo
-- 11 : cima
-- 00 : baixo
-- 10 : esquerda
-- 01 : direita
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- posicoes da cobra no mapa
snake_body : OUT int_array);
END COMPONENT;
COMPONENT size_counter IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (reset : IN STD_LOGIC;
food_pos : IN INTEGER RANGE -20 TO 255;
--food_pos : IN INTEGER RANGE 0 TO N*M-1;
snake_head : IN INTEGER RANGE -20 TO 255;
snake_size : OUT INTEGER RANGE 0 TO N*M;
eaten : OUT STD_LOGIC);
END COMPONENT;
COMPONENT colision IS
-- Dimensoes do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10);
PORT (snake_body : IN int_array;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC;
gmap : OUT STD_LOGIC_VECTOR(0 to N*M-1);
lost : OUT STD_LOGIC);
END COMPONENT ;
COMPONENT snake_dir IS
PORT (reset : IN STD_LOGIC;
snake_turn : IN STD_LOGIC_VECTOR(1 downto 0);
dir : BUFFER STD_LOGIC_VECTOR(0 to 1));
END COMPONENT;
END snake_pack;
| mit | a8b2d5bc443f1aa2e8a0963a5fdcf925 | 0.592083 | 3.137255 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/leon3x.vhd | 1 | 9,494 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: leon3x
-- File: leon3x.vhd
-- Author: Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3v3 component with all options
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
entity leon3x is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end;
architecture rtl of leon3x is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
constant IRFWT : integer := 1;--regfile_3p_write_through(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := (fpu mod 32) / 16;
constant fpushared : boolean := (fpu / 32) /= 0;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (
hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac, pclow,
notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram, ilramsize,
ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp,
cached, clk2x, scantest, mmupgsz, bp)
port map (gclk2, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, clk, clk2, clken);
-- IU register file
rf0 : regfile_3p_l3 generic map (memtech, IRFBITS, 32, IRFWT, IREGNUM,
scantest)
port map (gclk2, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk2, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2,
rfi.diag
);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen, scantest
)
port map (gclk2, crami, cramo, clk2);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem generic map (memtech, tbuf, scantest)
port map (gclk2, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo <= fpc_out_none; end generate;
fpshare : if fpushared generate
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (memtech, pclow, dsu, disas, hindex
)
port map (rst, gclk2, holdn, fpi, fpo, fpui, fpuo);
end generate;
nogrfpw0gen : if not ((fpuarch > 0) and (fpuarch < 8)) generate
fpui <= grfpu_in_none;
end generate;
end generate;
nofpshare : if not fpushared generate
grfpw1gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, memtech, (fpuarch-1), pclow, dsu, disas,
fpunet, hindex)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
mfpw1gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (memtech, pclow, dsu, disas
)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
grlfpc1gen : if (fpuarch >=8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (memtech, pclow, dsu, disas,
(fpuarch-8), fpunet, hindex)
port map (rst, gfclk2, holdn, fpi, fpo);
end generate;
fpui <= grfpu_in_none;
end generate;
-- CP
cpo <= fpc_out_none;
-- 1-clock reset delay
rstreg : process(gclk2)
begin if rising_edge(gclk2) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION)
, "leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| gpl-2.0 | c33522c587c113e9d4c1b2da8b7e0df5 | 0.545818 | 3.651538 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_dmask_rows_V.vhd | 2 | 4,564 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_dmask_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_dmask_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_dmask_rows_V is
component FIFO_image_filter_dmask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_dmask_rows_V_shiftReg : FIFO_image_filter_dmask_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 3fb169d8ab8ec045492127b1db970526 | 0.536372 | 3.505376 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/pwm_test/ctrl_led8x8_heart.vhd | 1 | 3,940 | -------------------------------------------------------------------------------
--
-- Title : ctrl_led8x8_heart
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Controller for LED Matrix
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ctrl_led8x8_heart is
port (
clk : in std_logic; --! clock
rst : in std_logic; --! reset
rst_reg : in std_logic; --! count reset
ch_freq : in std_logic; --! change frequency
led_y : out std_logic_vector(7 downto 0); --! LED Y
led_x : out std_logic_vector(7 downto 0) --! LED X
);
end ctrl_led8x8_heart;
architecture ctr_led8x8 of ctrl_led8x8_heart is
constant Nled : integer:=12; -- 12
signal cnt_led : std_logic_vector(Nled downto 0);
signal cnt_cmd : std_logic_vector(2 downto 0);
signal led_cmd : std_logic_vector(3 downto 0);
signal data_led : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
signal ch_freqz : std_logic;
signal ch_freqx : std_logic;
signal case_cnt : std_logic_vector(1 downto 0);
begin
ch_freqz <= ch_freq after 1 ns when rising_edge(clk);
ch_freqx <= ch_freq and not ch_freqz when rising_edge(clk);
led_y <= data_led;
led_x <= en_xhdl;
pr_case: process(clk, rst) is
begin
if rst = '0' then
case_cnt <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- case_cnt <= (others => '0');
-- elsif ch_freqx = '1' then
-- case_cnt <= case_cnt + '1';
-- else
-- null;
-- end if;
if ch_freqx = '1' then
case_cnt <= case_cnt + '1';
else
null;
end if;
end if;
end process;
pr_cnt: process(clk, rst) is
begin
if rst = '0' then
cnt_led <= (others => '0');
elsif rising_edge(clk) then
if rst_reg = '0' then
cnt_led <= (others => '0');
else
case case_cnt is
when "00" => cnt_led <= cnt_led + '1';
when "01" => cnt_led <= cnt_led + "10";
when "10" => cnt_led <= cnt_led + "11";
when others => cnt_led <= cnt_led + "100";
end case;
end if;
end if;
end process;
cnt_cmd <= cnt_led(Nled downto Nled-2);
pr_3x8: process(cnt_cmd) is
begin
case cnt_cmd is
when "000" => en_xhdl <= "11111110";
when "001" => en_xhdl <= "11111101";
when "010" => en_xhdl <= "11111011";
when "011" => en_xhdl <= "11110111";
when "100" => en_xhdl <= "11101111";
when "101" => en_xhdl <= "11011111";
when "110" => en_xhdl <= "10111111";
when "111" => en_xhdl <= "01111111";
when others => en_xhdl <= "11111110";
end case;
end process;
pr_8x4: process(en_xhdl) is
begin
case en_xhdl is
when "11111110" => led_cmd <= "0000";
when "11111101" => led_cmd <= "0001";
when "11111011" => led_cmd <= "0010";
when "11110111" => led_cmd <= "0011";
when "11101111" => led_cmd <= "0100";
when "11011111" => led_cmd <= "0101";
when "10111111" => led_cmd <= "0110";
when "01111111" => led_cmd <= "0111";
when others => led_cmd <= "1000";
end case;
end process;
pr_4x8: process(led_cmd) is
begin
case led_cmd is
when "0000" =>
data_led <= "11111111";
when "0001" =>
data_led <= "11100111";
when "0010" =>
data_led <= "11011011";
when "0011" =>
data_led <= "10111101";
when "0100" =>
data_led <= "01111110";
when "0101" =>
data_led <= "01100110";
when "0110" =>
data_led <= "10011001";
when "0111" =>
data_led <= "11111111";
when others =>
data_led <= "11111111";
end case;
end process;
end ctr_led8x8; | mit | 156f237b05a6f1a94777b462ae738bd9 | 0.523604 | 2.730423 | false | false | false | false |
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