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tommylommykins/logipi-midi-player | hdl/rtl-debugging/debug_contents_count.vhd | 1 | 1220 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.ws2812_data.all;
use virtual_button_lib.ws2812_constant_colours.all;
entity debug_contents_count is
generic (spi_tx_ram_depth : integer);
port(
ctrl : in ctrl_t;
contents_count : in integer range 0 to spi_tx_ram_depth;
contents_count_debug : out ws2812_array_t(0 to 7)
);
end;
architecture rtl of debug_contents_count is
constant debug_colour : ws2812_t := ws2812_yellow;
constant num_debug_leds : integer := 8;
constant contents_per_led : integer := spi_tx_ram_depth / num_debug_leds;
begin
debug_fullness : for i in 1 to 8 generate
go : process(ctrl.clk) is
constant threshold : integer range 0 to spi_tx_ram_depth := contents_per_led * i;
begin
if rising_edge(ctrl.clk) then
if contents_count > threshold or contents_count = spi_tx_ram_depth then
contents_count_debug(i - 1) <= debug_colour;
else
contents_count_debug(i - 1) <= ws2812_clear;
end if;
end if;
end process;
end generate;
end;
| bsd-2-clause |
w0rp/ale | test/test-files/hdl_server/with_git/files/foo.vhd | 388981 | 1 | bsd-2-clause |
|
eliza411/pygments | tests/examplefiles/test.vhdl | 75 | 4446 | library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd | 19 | 4781 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_strb_gen2.vhd | 1 | 102358 | -------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_strb_gen2.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for lines 2404 through 2964
-- by removing commented-out code.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
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| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_proc_sys_reset_0/sim/daala_zynq_proc_sys_reset_0.vhd | 1 | 5857 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY daala_zynq_proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END daala_zynq_proc_sys_reset_0;
ARCHITECTURE daala_zynq_proc_sys_reset_0_arch OF daala_zynq_proc_sys_reset_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF daala_zynq_proc_sys_reset_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END daala_zynq_proc_sys_reset_0_arch;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd | 2 | 23791 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
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| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/correct_one_bit.vhd | 1 | 8861 | -------------------------------------------------------------------------------
-- correct_one_bit.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description: Identifies single bit to correct in 32-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/input_blk.vhd | 2 | 28006 | `protect begin_protected
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`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd | 2 | 10218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
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`protect end_protected
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/reset_builtin.vhd | 2 | 19078 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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if7WZyXwTg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_cmd_status.vhd | 1 | 20648 | -------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_cmd_status.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
Use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_cmd_status;
architecture implementation of axi_datamover_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
CACHE_ENABLE : if C_ENABLE_CACHE_USER = 1 generate
begin
I_CACHE_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
end generate;
CACHE_DISABLE : if C_ENABLE_CACHE_USER = 0 generate
begin
cache2mstr_command <= (others => '0');
end generate CACHE_DISABLE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
| bsd-2-clause |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/cda_scale_cntr/_primary.vhd | 1 | 548 | library verilog;
use verilog.vl_types.all;
entity cda_scale_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
high : in vl_logic_vector(31 downto 0);
low : in vl_logic_vector(31 downto 0);
initial_value : in vl_logic_vector(31 downto 0);
mode : in vl_logic_vector(48 downto 1);
ph_tap : in vl_logic_vector(31 downto 0)
);
end cda_scale_cntr;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/reservation_alu2_entry/_primary.vhd | 1 | 3079 | library verilog;
use verilog.vl_types.all;
entity reservation_alu2_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGISTER_VALID : in vl_logic;
oINFO_REGIST_LOCK: out vl_logic;
iREGISTER_DESTINATION_SYSREG: in vl_logic;
iREGISTER_WRITEBACK: in vl_logic;
iREGISTER_CMD : in vl_logic_vector(4 downto 0);
iREGISTER_AFE : in vl_logic_vector(3 downto 0);
iREGISTER_SYS_REG: in vl_logic;
iREGISTER_LOGIC : in vl_logic;
iREGISTER_SHIFT : in vl_logic;
iREGISTER_ADDER : in vl_logic;
iREGISTER_FLAGS_OPT_VALID: in vl_logic;
iREGISTER_FLAGS_REGNAME: in vl_logic_vector(3 downto 0);
iREGISTER_SOURCE0_VALID: in vl_logic;
iREGISTER_SOURCE0: in vl_logic_vector(31 downto 0);
iREGISTER_SOURCE1_VALID: in vl_logic;
iREGISTER_SOURCE1: in vl_logic_vector(31 downto 0);
iREGISTER_PCR : in vl_logic_vector(31 downto 0);
iREGISTER_LOGIC_DEST: in vl_logic_vector(4 downto 0);
iREGISTER_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iREGISTER_COMMIT_TAG: in vl_logic_vector(5 downto 0);
iALU1_VALID : in vl_logic;
iALU1_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU1_WRITEBACK : in vl_logic;
iALU1_DATA : in vl_logic_vector(31 downto 0);
iALU2_VALID : in vl_logic;
iALU2_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU2_WRITEBACK : in vl_logic;
iALU2_DATA : in vl_logic_vector(31 downto 0);
iALU3_VALID : in vl_logic;
iALU3_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU3_DATA : in vl_logic_vector(31 downto 0);
iEXOUT_VALID : in vl_logic;
oINFO_ENTRY_VALID: out vl_logic;
oINFO_MATCHING : out vl_logic;
oINFO_DESTINATION_SYSREG: out vl_logic;
oINFO_WRITEBACK : out vl_logic;
oINFO_CMD : out vl_logic_vector(4 downto 0);
oINFO_AFE : out vl_logic_vector(3 downto 0);
oINFO_SYS_REG : out vl_logic;
oINFO_LOGIC : out vl_logic;
oINFO_SHIFT : out vl_logic;
oINFO_ADDER : out vl_logic;
oINFO_FLAGS_OPT_VALID: out vl_logic;
oINFO_FLAGS_REGNAME: out vl_logic_vector(3 downto 0);
oINFO_SOURCE0_VALID: out vl_logic;
oINFO_SOURCE0 : out vl_logic_vector(31 downto 0);
oINFO_SOURCE1_VALID: out vl_logic;
oINFO_SOURCE1 : out vl_logic_vector(31 downto 0);
oINFO_PCR : out vl_logic_vector(31 downto 0);
oINFO_LOGIC_DEST: out vl_logic_vector(4 downto 0);
oINFO_DESTINATION_REGNAME: out vl_logic_vector(5 downto 0);
oINFO_COMMIT_TAG: out vl_logic_vector(5 downto 0)
);
end reservation_alu2_entry;
| bsd-2-clause |
cpulabs/mist1032sa | sim/inst_level/work/stratix_tx_outclk/_primary.vhd | 1 | 859 | library verilog;
use verilog.vl_types.all;
entity stratix_tx_outclk is
generic(
deserialization_factor: integer := 4;
bypass_serializer: string := "FALSE";
invert_clock : string := "FALSE";
use_falling_clock_edge: string := "FALSE"
);
port(
tx_in : in vl_logic_vector(9 downto 0);
tx_fastclk : in vl_logic;
tx_enable : in vl_logic;
tx_out : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of bypass_serializer : constant is 1;
attribute mti_svvh_generic_type of invert_clock : constant is 1;
attribute mti_svvh_generic_type of use_falling_clock_edge : constant is 1;
end stratix_tx_outclk;
| bsd-2-clause |
jrrk2/greth_library | greth_library/rocketlib/misc/reset_glb.vhd | 2 | 1703 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief System reset former.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! @brief NoC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[in] inPllLock PLL status.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
entity reset_global is
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
inPllLock : in std_ulogic;
outReset : out std_ulogic
);
end;
architecture arch_reset_global of reset_global is
type reg_type is record
delay_cnt : std_logic_vector(7 downto 0);
end record;
signal r : reg_type;
begin
proc_rst : process (inSysClk, inSysReset, inPllLock, r)
variable wb_delay_cnt : std_logic_vector(7 downto 0);
variable sys_reset : std_logic;
begin
sys_reset := inSysReset or not inPllLock;
wb_delay_cnt := r.delay_cnt;
if r.delay_cnt(7) = '0' then
wb_delay_cnt := r.delay_cnt + 1;
end if;
if sys_reset = '1' then
r.delay_cnt <= (others => '0');
elsif rising_edge(inSysClk) then
r.delay_cnt <= wb_delay_cnt;
end if;
end process;
outReset <= not r.delay_cnt(7);
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/techmap/mem/syncram_2p_tech.vhd | 2 | 2051 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific dual-port RAM.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of syncram_2p_tech is
component syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
inf : if tech = inferred generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xilinx6 : if tech = virtex6 or tech = kintex7 or tech = artix7 generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/techmap/bufg/bufgmux_micron180.vhd | 3 | 671 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Mikron 180 nm.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity bufgmux_micron180 is
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_micron180 is
begin
O <= I1 when S = '0' else I2;
-- TODO: clock buffer
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/techmap/mem/bootrom_inferred.vhd | 2 | 2310 | ----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: [email protected]
-- DESCRIPTION: This file contains copy of the firmware image
------------------------------------------------------------------------------
-- WARNING:
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity BootRom_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of BootRom_inferred is
constant ROM_ADDR_WIDTH : integer := 13;
constant ROM_LENGTH : integer := 2**(ROM_ADDR_WIDTH - log2(CFG_NASTI_DATA_BYTES));
type rom_block is array (0 to ROM_LENGTH-1) of std_logic_vector(31 downto 0);
type rom_type is array (0 to CFG_WORDS_ON_BUS-1) of rom_block;
type local_addr_arr is array (0 to CFG_WORDS_ON_BUS-1) of integer;
impure function init_rom(file_name : in string) return rom_type is
file rom_file : text open read_mode is file_name;
variable rom_line : line;
variable temp_bv : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable temp_mem : rom_type;
begin
for i in 0 to (ROM_LENGTH-1) loop
readline(rom_file, rom_line);
hread(rom_line, temp_bv);
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
temp_mem(n)(i) := temp_bv((n+1)*32-1 downto 32*n);
end loop;
end loop;
return temp_mem;
end function;
constant rom : rom_type := init_rom(hex_filename);
begin
reg : process (clk)
variable t_adr : local_addr_arr;
begin
if rising_edge(clk) then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
t_adr(n) := conv_integer(address(n)(ROM_ADDR_WIDTH-1 downto log2(CFG_NASTI_DATA_BYTES)));
data(32*(n+1)-1 downto 32*n) <= rom(n)(t_adr(n));
end loop;
end if;
end process;
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/rocketlib/tilelink/htifserdes.vhd | 2 | 5057 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'htifserdes' module.
--! @details Used only for system with enabled L2-cache.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Uncore messages serializer/deserializer.
--! @details There is implemented logic of conversion of the 128-bit
--! 'Uncore' messages on chunks of HTIF_WIDTH bits size (default 16
--! bits). Message is formed using HostIO signal request.
entity htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end;
architecture arch_htif_serdes of htif_serdes is
--! @name Uncore message IDs specific for HostIO interface.
--! @brief Used See htif.scala, class Htif, line about 105.
--! @{
--! Reading from physical memory. Not used in this SOC.
constant HTIF_CMD_READ_MEMORY : std_logic_vector(3 downto 0) := X"0";
--! Writting into physical memory. Not used in this SOC.
constant HTIF_CMD_WRITE_MEMORY : std_logic_vector(3 downto 0) := X"1";
--! Reading Control Register (CSR).
constant HTIF_CMD_READ_CONTROL_REG : std_logic_vector(3 downto 0) := X"2";
--! Writting Control Register (CSR).
constant HTIF_CMD_WRITE_CONTROL_REG : std_logic_vector(3 downto 0) := X"3";
--! Handshake success.
constant HTIF_CMD_ACK : std_logic_vector(3 downto 0) := X"4";
--! Handshake error.
constant HTIF_CMD_NACK : std_logic_vector(3 downto 0) := X"5";
--! @}
constant HTIF_DATA_EMPTY :
std_logic_vector(HTIF_WIDTH-1 downto 0) := (others => '1');
type state_type is (wait_cmd, transmit, response, resp_ready);
type registers is record
state : state_type;
muxCnt : integer range 0 to 128/HTIF_WIDTH + 1;
cmd : std_logic_vector(127 downto 0);
seqno : std_logic_vector(7 downto 0);
end record;
signal r, rin: registers;
function functionMakeMessage( r : registers;
hst : host_out_type)
return std_logic_vector is
variable ret : std_logic_vector(127 downto 0);
begin
ret(127 downto 64) := hst.csr_req_bits_data;
ret(63 downto 44) := conv_std_logic_vector(core_idx, 20);
ret(43 downto 36) := X"00";
ret(35 downto 24) := hst.csr_req_bits_addr;
ret(23 downto 16) := r.seqno;
ret(15 downto 4) := X"001"; -- total number of words
if hst.csr_req_bits_rw = '1' then
ret(3 downto 0) := HTIF_CMD_WRITE_CONTROL_REG;
else
ret(3 downto 0) := HTIF_CMD_READ_CONTROL_REG;
end if;
return ret;
end;
begin
comblogic : process(hostoi, srdi, r)
variable v : registers;
variable vo : host_in_type;
begin
v := r;
vo.grant := (others => '0');
vo.csr_req_ready := '0';
vo.csr_resp_valid := '0';
vo.csr_resp_bits := (others => '0');
vo.debug_stats_csr := '0';
case r.state is
when wait_cmd =>
vo.csr_req_ready := '1';
if hostoi.csr_req_valid = '1' then
v.state := transmit;
v.seqno := r.seqno + 1;
v.cmd := functionMakeMessage(r, hostoi);
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
when transmit =>
--! Multiplexer of the command into HTIF bus
if srdi.ready = '1' then
v.muxCnt := r.muxCnt + 1;
end if;
v.cmd := HTIF_DATA_EMPTY & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := response;
v.muxCnt := 0;
end if;
srdo.valid <= '1';
srdo.ready <= '0';
srdo.bits <= r.cmd(HTIF_WIDTH-1 downto 0);
when response =>
if srdi.valid = '1' then
v.muxCnt := r.muxCnt + 1;
v.cmd := srdi.bits & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := resp_ready;
end if;
end if;
srdo.valid <= '0';
srdo.ready <= '1';
srdo.bits <= (others => '0');
when resp_ready =>
if hostoi.csr_resp_ready = '1' then
v.state := wait_cmd;
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
vo.csr_resp_valid := '1';
vo.csr_resp_bits := r.cmd(127 downto 64);
when others =>
end case;
rin <= v;
hostio <= vo;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= wait_cmd;
r.muxCnt <= 0;
r.cmd <= (others => '0');
r.seqno <= X"01";
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/rocketlib/tilelink/starter.vhd | 2 | 4189 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allow to start CPU
--! execution. This resetting cycle is ongoing upto external
--! write 0-value into this MRESET register.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Hard-reset initialization module.
--! @details L2-cached system implementing Uncore module must be switched
--! from resetting state that is done by this module.
--! param[in] HTIF interface clock.
--! param[in] Reset signal with the active LOW level.
--! param[in] i_host HostIO input signals.
--! param[out] o_host HostIO output signals.
entity starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end;
architecture arch_starter of starter is
type state_type is (init_reset, init_cmd, wait_ready, wait_resp, disable);
type registers is record
state : state_type;
init_ena : std_logic;
cmdCnt : integer range 0 to 3;
end record;
signal r, rin: registers;
begin
comblogic : process(i_host, r)
variable v : registers;
begin
v := r;
case r.state is
when init_reset =>
v.state := init_cmd;
o_host.reset <= '1';
o_host.id <= '0';
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
o_host.csr_resp_ready <= '1';
when init_cmd =>
o_host.reset <= '0';
--! Select CSR write command
case r.cmdCnt is
when 0 =>
-- PLL divide. One Tile at once.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"03f";
o_host.csr_req_bits_data <= X"0000000000020005";
when 1 =>
-- Set CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000001";
when 2 =>
-- Clear CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000000";
when 3 =>
-- Write MRESET
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"782";
o_host.csr_req_bits_data <= X"0000000000000000";
when others =>
v.state := disable;
end case;
if i_host.csr_req_ready = '0' then
v.state := wait_ready;
else
v.state := wait_resp;
end if;
when wait_ready =>
if i_host.csr_req_ready = '1' then
v.state := wait_resp;
o_host.csr_req_valid <= '0';
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.cmdCnt := r.cmdCnt + 1;
if r.cmdCnt = 3 then
v.state := disable;
v.init_ena := '0';
else
v.state := init_cmd;
end if;
end if;
when others =>
end case;
rin <= v;
end process;
o_init_ena <= r.init_ena;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= init_reset;
r.init_ena <= '1';
r.cmdCnt <= 0;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/rocketlib/misc/nasti_gpio.vhd | 1 | 4437 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Controller of the GPIOs with the AMBA AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_dip : in std_logic_vector(3 downto 0);
o_led : out std_logic_vector(7 downto 0)
);
end;
architecture arch_nasti_gpio of nasti_gpio is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPIO,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type bank_type is record
led : std_logic_vector(31 downto 0);
dip : std_logic_vector(31 downto 0);
reg32_2 : std_logic_vector(31 downto 0);
reg32_3 : std_logic_vector(31 downto 0);
reg32_4 : std_logic_vector(31 downto 0);
reg32_5 : std_logic_vector(31 downto 0);
reg32_6 : std_logic_vector(31 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
constant RESET_VALUE : registers := (
NASTI_SLAVE_BANK_RESET,
((others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'))
);
signal r, rin : registers;
begin
comblogic : process(i, i_dip, r, nrst)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := r.bank0.led;
when 1 => tmp := r.bank0.dip;
when 2 => tmp := r.bank0.reg32_2;
when 3 => tmp := r.bank0.reg32_3;
when 4 => tmp := r.bank0.reg32_4;
when 5 => tmp := r.bank0.reg32_5;
when 6 => tmp := r.bank0.reg32_6;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i.w_data(32*(n+1)-1 downto 32*n);
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
case waddr_reg(n) is
when 0 => v.bank0.led := tmp;
--when 1 => v.bank0.dip := tmp;
when 2 => v.bank0.reg32_2 := tmp;
when 3 => v.bank0.reg32_3 := tmp;
when 4 => v.bank0.reg32_4 := tmp;
when 5 => v.bank0.reg32_5 := tmp;
when 6 => v.bank0.reg32_6 := tmp;
when others =>
end case;
end if;
end loop;
end if;
o <= functionAxi4Output(r.bank_axi, rdata);
v.bank0.dip(3 downto 0) := i_dip;
if nrst = '0' then
v := RESET_VALUE;
end if;
rin <= v;
end process;
cfg <= xconfig;
o_led <= r.bank0.led(7 downto 0);
-- registers:
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause |
jrrk2/greth_library | greth_library/rocketlib/tilelink/htifctrl.vhd | 2 | 2317 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details Implementation of the Host Controller device.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief HostIO (HTIF) bus controller.
entity htifctrl is
port (
clk : in std_logic;
nrst : in std_logic;
srcsi : in host_out_vector;
srcso : out host_out_type;
htifii : in host_in_type;
htifio : out host_in_type
);
end;
architecture arch_htifctrl of htifctrl is
constant HTIF_ZERO : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0) := (others => '0');
type reg_type is record
idx : integer range 0 to CFG_HTIF_SRC_TOTAL-1;
srcsel : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
end record;
signal rin, r : reg_type;
begin
comblogic : process(srcsi, htifii, r)
variable v : reg_type;
variable idx : integer range 0 to CFG_HTIF_SRC_TOTAL-1;
variable srcsel : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
variable req : std_logic;
begin
v := r;
req := '0';
idx := 0;
srcsel := r.srcsel;
for n in 0 to CFG_HTIF_SRC_TOTAL-1 loop
if req = '0' and srcsi(n).csr_req_valid = '1' then
idx := n;
req := '1';
end if;
end loop;
if (srcsel = HTIF_ZERO) or (htifii.csr_resp_valid and srcsi(r.idx).csr_resp_ready) = '1' then
srcsel(r.idx) := '0';
srcsel(idx) := req;
v.idx := idx;
else
idx := r.idx;
end if;
v.srcsel := srcsel;
rin <= v;
srcso <= srcsi(idx);
htifio.grant <= srcsel;
htifio.csr_req_ready <= htifii.csr_req_ready;
htifio.csr_resp_valid <= htifii.csr_resp_valid;
htifio.csr_resp_bits <= htifii.csr_resp_bits;
htifio.debug_stats_csr <= htifii.debug_stats_csr;
end process;
reg0 : process(clk, nrst) begin
if nrst = '0' then
r.idx <= 0;
r.srcsel <= (others =>'0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/cdcfifo.vhd | 3 | 10355 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cdcfifo.vhd when simulating
-- the core, cdcfifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cdcfifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END cdcfifo;
ARCHITECTURE cdcfifo_a OF cdcfifo IS
-- synthesis translate_off
COMPONENT wrapped_cdcfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cdcfifo USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 2048,
c_rd_freq => 1,
c_rd_pntr_width => 11,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cdcfifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty
);
-- synthesis translate_on
END cdcfifo_a;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/bytefifo/simulation/bytefifo_pctrl.vhd | 3 | 20422 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF bytefifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/bytefifoFPGA_synth.vhd | 3 | 4432 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE spartan6 OF bytefifoFPGA IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/example_design/rtl/mcb_raw_wrapper.vhd | 9 | 299135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:04 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
-- Rev 1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
-- Rev 1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010
-- Rev 1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
-- CDC static timing issue. 2-14-2011
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
--CR 596422
constant allzero : std_logic_vector(127 downto 0) := (others => '0');
--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
----------------------------------------------------------------------------
-- signal Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal selfrefresh_mode_sig : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
signal uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
signal uo_done_cal_sig : std_logic;
signal wait_200us_counter : std_logic_vector(15 downto 0);
signal cke_train_reg : std_logic;
signal wait_200us_done_r1 : std_logic;
signal wait_200us_done_r2 : std_logic;
signal syn1_sys_rst : std_logic;
signal syn2_sys_rst : std_logic;
signal selfrefresh_enter_r1 : std_logic;
signal selfrefresh_enter_r2 : std_logic;
signal selfrefresh_enter_r3 : std_logic;
signal gated_pll_lock : std_logic;
signal soft_cal_selfrefresh_req : std_logic;
signal normal_operation_window : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Assign the output signals with corresponding intermediate signals
uo_done_cal <= uo_done_cal_sig;
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
syn_uiclk_pll_lock <= pll_lock;
end if;
end if;
end process;
-- logic to determine if Memory is SELFREFRESH mode operation or NORMAL mode.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
normal_operation_window <= '1';
elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
normal_operation_window <= '0';
elsif ((selfrefresh_enter_r2 = '0') and (selfrefresh_mode_sig = '0')) then
normal_operation_window <= '1';
else
normal_operation_window <= normal_operation_window;
end if;
end if;
end process;
process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
begin
if (normal_operation_window = '1') then
gated_pll_lock <= pll_lock;
else
gated_pll_lock <= syn_uiclk_pll_lock;
end if;
end process;
-- int_sys_rst will be asserted if pll lose lock during normal operation.
-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
-- reset will not be generated.
int_sys_rst <= sys_rst or not(gated_pll_lock);
-- synchronize the selfrefresh_enter
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
selfrefresh_enter_r1 <= '0';
selfrefresh_enter_r2 <= '0';
selfrefresh_enter_r3 <= '0';
else
selfrefresh_enter_r1 <= selfrefresh_enter;
selfrefresh_enter_r2 <= selfrefresh_enter_r1;
selfrefresh_enter_r3 <= selfrefresh_enter_r2;
end if;
end if;
end process;
-- The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
-- It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
-- This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
soft_cal_selfrefresh_req <= '0';
elsif (selfrefresh_enter_r3 = '1') then
soft_cal_selfrefresh_req <= '1';
elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then
soft_cal_selfrefresh_req <= '0';
else
soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
end if;
end if;
end process;
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(7 downto 4);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
--process(ui_clk)
--begin
--if (ui_clk'event and ui_clk = '1') then
-- syn1_sys_rst <= sys_rst;
-- syn2_sys_rst <= syn1_sys_rst;
--end if;
--end process;
uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
--RST => syn2_sys_rst,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
--PLL_LOCK => pll_lock,
PLL_LOCK => gated_pll_lock,
--SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_REQ => soft_cal_selfrefresh_req, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode_sig, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
selfrefresh_mode_sig <= '0';
-- synthesis translate_off
init_sequence: if (C_SIMULATION = "FALSE") generate
-- synthesis translate_on
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
wait_200us_counter <= (others => '0');
elsif (ui_clk'event and ui_clk = '1') then -- UI_CLK maximum is up to 100 MHz
if (wait_200us_counter(15) = '1') then
wait_200us_counter <= wait_200us_counter;
else
wait_200us_counter <= wait_200us_counter + '1';
end if;
end if;
end process;
-- synthesis translate_off
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
wait_200us_counter <= X"FFFF";
process
begin
report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
wait;
end process;
end generate;
-- synthesis translate_on
gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
process (ui_clk)
begin
-- When wait_200us_[13] and wait_200us_[14] are both asserted,
-- 200 us wait should have been passed.
if (ui_clk'event and ui_clk = '1') then
if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
wait_200us_done_r1 <= '1';
else
wait_200us_done_r1 <= '0';
end if;
wait_200us_done_r2 <= wait_200us_done_r1;
end if;
end process;
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
cke_train_reg <= '0';
elsif (ui_clk'event and ui_clk = '1') then
if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
cke_train_reg <= '1';
elsif (uo_done_cal_sig = '1') then
cke_train_reg <= '0';
end if;
end if;
end process;
cke_train <= cke_train_reg;
end generate;
gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
cke_train <= '0';
end generate;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
selfrefresh_mode <= selfrefresh_mode_sig;
end aarch;
| bsd-2-clause |
LaurentCabaret/pyVhdl2Sch | datas/test_files/C8.vhd | 1 | 515 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ShiftRegister is
Port ( CLK : in STD_LOGIC;
signalOutput : out My_STD_LOGIC_VECTOR); -- missing `(7 downto 0)` here
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal Q : STD_LOGIC_VECTOR (7 downto 0) := "10011000";
begin
Output <= Q;
process (CLK)
begin
if (CLK'event and CLK = '1') then
Q(7 downto 0) <= Q(6 downto 0) & Q(7);
end if;
end process;
end Behavioral; | bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/edidram_synth.vhd | 3 | 4441 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 --
-- --
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
-- direct drop-in replacement. It should be used in all new Xilinx --
-- designs. The core supports RAM and ROM functions over a wide range of --
-- widths and depths. Use this core to generate block memories with --
-- symmetric or asymmetric read and write port widths, as well as cores --
-- which can perform simultaneous write operations to separate --
-- locations, and simultaneous read operations from the same location. --
-- For more information on differences in interface and feature support --
-- between this core and the Dual Port Block Memory and Single Port --
-- Block Memory LogiCOREs, please consult the data sheet. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- CLK.ACLK
-- AXI4 Interconnect Clock Input
-- RST.ARESETN
-- AXI4 Interconnect Reset Input
-- AXI_SLAVE_S_AXI
-- AXI_SLAVE
-- AXILite_SLAVE_S_AXI
-- AXILite_SLAVE
-- BRAM_PORTA
-- BRAM_PORTA
-- BRAM_PORTB
-- BRAM_PORTB
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY edidram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END edidram;
ARCHITECTURE spartan6 OF edidram IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/bytefifo_synth.vhd | 3 | 4420 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Synthesized Netlist Wrapper
-- This file is provided to wrap around the synthesized netlist (if appropriate)
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bytefifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifo;
ARCHITECTURE spartan6 OF bytefifo IS
BEGIN
-- WARNING: This file provides an entity declaration with empty architecture, it
-- does not support direct instantiation. Please use an instantiation
-- template (VHO) to instantiate the IP within a design.
END spartan6;
| bsd-2-clause |
mithro/HDMI2USB | hdl/usb/cdc_in.vhd | 3 | 8928 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
entity cdc_in is
port (
-- USB signals
ifclk : in std_logic;
faddr : in std_logic_vector(1 downto 0);
cdcin : in std_logic_vector(1 downto 0);
slwr : out std_logic;
pktend : out std_logic;
fdata : out std_logic_vector(7 downto 0);
cdc_in_free : out std_logic;
-- EDID structure
edid0_byte : in std_logic_vector(7 downto 0);
edid0_byte_en : in std_logic;
edid1_byte : in std_logic_vector(7 downto 0);
edid1_byte_en : in std_logic;
-- status inputs
resX0 : in std_logic_vector(15 downto 0);
resY0 : in std_logic_vector(15 downto 0);
resX1 : in std_logic_vector(15 downto 0);
resY1 : in std_logic_vector(15 downto 0);
jpeg_error : in std_logic;
rgb_de0 : in std_logic; -- to check activity on hdmi
rgb_de1 : in std_logic; -- to check activity on hdmi
-- command signals
status : in std_logic_vector(4 downto 0);
usb_cmd : in std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : in std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : in std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
hdmi_cmd : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
--debug
debug_byte : in std_logic_vector(7 downto 0);
debug_index : out integer range 0 to 15;
-- clk,rst
rst : in std_logic;
clk : in std_logic
);
end entity cdc_in;
architecture rtl of cdc_in is
--------- components
COMPONENT edidram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT cdcfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC
);
END COMPONENT;
--------- Signals
signal edid_we : std_logic_vector(0 downto 0);
signal edid_write_data : std_logic_vector(7 downto 0);
signal edid_read_data : std_logic_vector(7 downto 0);
signal edid_write_add_edid0 : std_logic_vector(6 downto 0);
signal edid_write_add_edid1 : std_logic_vector(6 downto 0);
signal edid_write_add : std_logic_vector(7 downto 0);
signal edid_read_add : std_logic_vector(7 downto 0);
signal status_q : std_logic_vector(4 downto 0);
signal counter : std_logic_vector(8 downto 0);
signal working : std_logic;
signal din : std_logic_vector(7 DOWNTO 0);
signal wr_en : std_logic;
signal rd_en : std_logic;
signal dout : std_logic_vector(7 DOWNTO 0);
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal pktend_i : std_logic;
begin -- of architecture
debug_index <= conv_integer(unsigned(counter));
----------- Sync Logic
usbFifoProcess:process(rst,clk)
begin
if rst = '1' then
working <= '0';
counter <= (others => '0');
edid_read_add <= (others => '0');
elsif rising_edge(clk) then
wr_en <= '0';
if working = '0' then
working <= or_reduce(status);
status_q <= status;
counter <= (others=>'0');
else -- write data to fifo
counter <= counter + 1;
if status_q(0) = '1' then -- USB
wr_en <= '1';
din <= ("00000" & usb_cmd);
working <= '0';
elsif status_q(1) = '1' then -- jpeg_encoder_cmd
wr_en <= '1';
din <= ("000000" & jpeg_encoder_cmd);
working <= '0';
elsif status_q(2) = '1' then -- selector_cmd
if counter = 0 then
wr_en <= '1';
din <= selector_cmd(7 downto 0);
elsif counter = 1 then
wr_en <= '1';
din <= ("000" & selector_cmd(12 downto 8));
elsif counter = 2 then
working <= '0';
end if;
elsif status_q(3) = '1' then -- hdmi_cmd_i
if counter = 256 then
wr_en <= '1';
din <= ("000000" & hdmi_cmd);
elsif counter = 257 then
wr_en <= '1';
din <= resX0(15 downto 8);
elsif counter = 258 then
wr_en <= '1';
din <= resX0(7 downto 0);
elsif counter = 259 then
wr_en <= '1';
din <= resY0(15 downto 8);
elsif counter = 260 then
wr_en <= '1';
din <= resY0(7 downto 0);
elsif counter = 261 then
wr_en <= '1';
din <= resX1(15 downto 8);
elsif counter = 262 then
wr_en <= '1';
din <= resX1(7 downto 0);
elsif counter = 263 then
wr_en <= '1';
din <= resY1(15 downto 8);
elsif counter = 264 then
wr_en <= '1';
din <= resY1(7 downto 0);
elsif counter = 265 then
working <= '0';
else
edid_read_add <= counter(7 downto 0);
din <= edid_read_data;
wr_en <= '1';
end if;
elsif status_q(4) = '1' then
if counter = 14 then
working <= '0';
else
wr_en <= '1';
din <= debug_byte;
end if;
end if;
end if; -- if working = '0' then
end if;-- clk
end process usbFifoProcess;
usbProcess:process(rst,ifclk)
begin
if rst = '1' then
cdc_in_free <= '1';
rd_en <= '0';
slwr <= '1';
pktend <= '1';
pktend_i <= '0';
elsif falling_edge(ifclk) then
cdc_in_free <= '1';
rd_en <= '0';
slwr <= '1';
pktend <= '1';
pktend_i <= '0';
fdata <= dout;
if faddr = cdcin then
if empty = '0' then
cdc_in_free <= '0';
rd_en <= '1';
slwr <= '0';
pktend_i <= '1';
elsif pktend_i = '1' then
pktend <= '0';
cdc_in_free <= '0';
end if;
end if;
end if;
end process usbProcess;
edidprocess:process(rst,clk)
begin
if rst = '1' then
edid_write_data <= (others => '0');
edid_write_add <= (others => '0');
edid_write_add_edid0 <= (others => '0');
edid_write_add_edid1 <= (others => '0');
edid_we <= "0";
elsif rising_edge(clk) then
edid_we <= "0";
if edid0_byte_en = '1' then
edid_we <= "1";
edid_write_data <= edid0_byte;
edid_write_add <= ('0' & edid_write_add_edid0);
edid_write_add_edid0 <= edid_write_add_edid0 + 1;
elsif edid1_byte_en = '1' then
edid_we <= "1";
edid_write_data <= edid1_byte;
edid_write_add <= ('1' & edid_write_add_edid1);
edid_write_add_edid1 <= edid_write_add_edid1 + 1;
end if;
end if;
end process edidprocess;
--------- components
edidram_comp : edidram
PORT MAP (
clka => clk,
wea => edid_we,
addra => edid_write_add,
dina => edid_write_data,
clkb => clk,
addrb => edid_read_add,
doutb => edid_read_data
);
cdcfifo_comp : cdcfifo
PORT MAP (
rst => rst,
wr_clk => clk,
rd_clk => ifclk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty
);
end architecture rtl;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/cdcfifo/simulation/cdcfifo_pkg.vhd | 3 | 11447 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cdcfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cdcfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cdcfifo_pkg;
PACKAGE BODY cdcfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cdcfifo_pkg;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/cmdfifo/simulation/cmdfifo_synth.vhd | 3 | 11373 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cmdfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cmdfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cmdfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 16,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cmdfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cmdfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 8,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cmdfifo_inst : cmdfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/bytefifo/simulation/bytefifo_rng.vhd | 3 | 3887 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY bytefifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF bytefifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/image_selector_fifo/simulation/image_selector_fifo_rng.vhd | 3 | 3920 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY image_selector_fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF image_selector_fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/bytefifo/example_design/bytefifo_exdes.vhd | 3 | 5869 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity bytefifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end bytefifo_exdes;
architecture xilinx of bytefifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component bytefifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : bytefifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/init_mem_pattern_ctr.vhd | 20 | 25087 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: init_mem_pattern_ctr.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel has a small FSM to control the operation of
-- mcb_traffic_gen module.It first fill up the memory with a selected
-- DATA pattern and then starts the memory testing state.
-- Reference:
-- Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
-- and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
-- The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
-- 1.2 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY init_mem_pattern_ctr IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
TST_MEM_INSTR_MODE : STRING := "R_W_INSTR_MODE";
MEM_BURST_LEN : INTEGER := 8;
CMD_PATTERN : STRING := "CGEN_ALL";
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
CMD_SEED_VALUE : std_logic_vector(31 downto 0) := X"12345678";
DATA_SEED_VALUE : std_logic_vector(31 downto 0) := X"ca345675";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
PORT_MODE : STRING := "BI_MODE";
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
mcb_cmd_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_en_i : IN STD_LOGIC;
mcb_cmd_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_wr_en_i : IN STD_LOGIC;
vio_modify_enable : IN STD_LOGIC;
vio_data_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_addr_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_bl_mode_value : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
vio_fixed_bl_value : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_init_done_i : IN STD_LOGIC;
cmp_error : IN STD_LOGIC;
run_traffic_o : OUT STD_LOGIC;
start_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_o : OUT STD_LOGIC;
addr_mode_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_o : OUT STD_LOGIC;
fixed_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END init_mem_pattern_ctr;
ARCHITECTURE trans OF init_mem_pattern_ctr IS
constant IDLE : std_logic_vector(4 downto 0) := "00001";
constant INIT_MEM_WRITE : std_logic_vector(4 downto 0) := "00010";
constant INIT_MEM_READ : std_logic_vector(4 downto 0) := "00100";
constant TEST_MEM : std_logic_vector(4 downto 0) := "01000";
constant CMP_ERROR1 : std_logic_vector(4 downto 0) := "10000";
constant BRAM_ADDR : std_logic_vector(1 downto 0) := "00";
constant FIXED_ADDR : std_logic_vector(2 downto 0) := "001";
constant PRBS_ADDR : std_logic_vector(2 downto 0) := "010";
constant SEQUENTIAL_ADDR : std_logic_vector(2 downto 0) := "011";
constant BRAM_INSTR_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_INSTR_MODE : std_logic_vector(3 downto 0) := "0001";
constant FIXED_INSTR_MODE_WITH_REFRESH : std_logic_vector(3 downto 0) := "0110";
constant R_W_INSTR_MODE : std_logic_vector(3 downto 0) := "0010";
constant RP_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0011";
constant R_RP_W_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0100";
constant R_RP_W_WP_REF_INSTR_MODE : std_logic_vector(3 downto 0) := "0101";
constant BRAM_BL_MODE : std_logic_vector(1 downto 0) := "00";
constant FIXED_BL_MODE : std_logic_vector(1 downto 0) := "01";
constant PRBS_BL_MODE : std_logic_vector(1 downto 0) := "10";
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
constant RD_INSTR : std_logic_vector(2 downto 0) := "001";
constant RDP_INSTR : std_logic_vector(2 downto 0) := "011";
constant WR_INSTR : std_logic_vector(2 downto 0) := "000";
constant WRP_INSTR : std_logic_vector(2 downto 0) := "010";
constant REFRESH_INSTR : std_logic_vector(2 downto 0) := "100";
constant NOP_WR_INSTR : std_logic_vector(2 downto 0) := "101";
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL mcb_init_done_reg : STD_LOGIC;
SIGNAL mcb_init_done_reg1 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL mcb_cmd_en_r : STD_LOGIC;
SIGNAL mcb_cmd_bl_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL end_addr_reached : STD_LOGIC;
SIGNAL run_traffic : STD_LOGIC;
SIGNAL current_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fix_bl_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL data_mode_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL addr_mode_sel : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_mode : STD_LOGIC_VECTOR(2 DOWNTO 0);
-- SIGNAL data_mode1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL FIXEDBL : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL FIXED_BL_VALUE : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL bram_mode_enable : STD_LOGIC;
SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_mem_instr_mode : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_mode_o_xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL data_mode_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
"0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
(TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
"0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
"0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6") else
"0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6")else
"0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
FAMILY = "SPARTAN6") else
"0010" ;
-- Drive referenced outputs
bl_mode_o <= bl_mode_o_xhdl0;
FIXEDBL <= "000000";
xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
INC_COUNTS <= "00000100000";
ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
INC_COUNTS <= "00000010000";
ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
INC_COUNTS <= "00000001000";
ELSIF (DWIDTH = 32) THEN
INC_COUNTS <= "00000000100";
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_address <= BEGIN_ADDRESS;
ELSIF (
-- ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
(mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
(mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
) THEN
current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
ELSE
current_address <= current_address;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
upper_end_matched <= '0';
ELSIF (mcb_cmd_en_i = '1') THEN
upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
END IF;
END IF;
END PROCESS;
FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE
"0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
('0' & FIXEDBL);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
lower_end_matched <= '1';
ELSE
lower_end_matched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_i = '1') THEN
mcb_cmd_bl_r <= mcb_cmd_bl_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR
(upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
end_addr_reached <= '1';
ELSE
end_addr_reached <= '0';
END IF;
END IF;
END PROCESS;
fixed_addr_o <= "00000000000000000001001000110100";
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mcb_init_done_reg1 <= mcb_init_done_i;
mcb_init_done_reg <= mcb_init_done_reg1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_o <= run_traffic;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_state <= "00001";
ELSE
current_state <= next_state;
END IF;
END IF;
END PROCESS;
start_addr_o <= BEGIN_ADDRESS;
end_addr_o <= END_ADDRESS;
cmd_seed_o <= CMD_SEED_VALUE;
data_seed_o <= DATA_SEED_VALUE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
syn1_vio_data_mode_value <= "011";
syn1_vio_addr_mode_value <= "011";
ELSIF (vio_modify_enable = '1') THEN
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
addr_mode_sel <= "011";
ELSIF (vio_modify_enable = '1') THEN
data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
addr_mode_sel <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
ELSIF (vio_modify_enable = '1') THEN
fix_bl_value <= vio_fixed_bl_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
IF (FAMILY = "VIRTEX6") THEN
bl_mode_sel <= FIXED_BL_MODE;
ELSE
bl_mode_sel <= PRBS_BL_MODE;
END IF;
ELSIF (vio_modify_enable = '1') THEN
bl_mode_sel <= vio_bl_mode_value;
END IF;
END IF;
END PROCESS;
data_mode_o <= data_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_reg <= data_mode_sel;
addr_mode_o <= addr_mode;
IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
bram_mode_enable <= '1';
ELSE
bram_mode_enable <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
BEGIN
load_seed_o <= '0';
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
addr_mode <= (others => '0');
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
instr_mode_o <= (others => '0');
ELSE
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
bl_mode_o_xhdl0 <= (others => '0');
ELSE
bl_mode_o_xhdl0 <= FIXED_BL_MODE;
END IF;
-- data_mode1 <= WALKING1_DATA_MODE;
IF (FAMILY = "VIRTEX6") THEN
fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
-- PRBS mode
else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
fixed_bl_o <= "000000";-- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
mode_load_o <= '0';
run_traffic <= '0';
next_state <= IDLE;
IF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
CASE current_state IS
WHEN IDLE =>
IF (mcb_init_done_reg = '1') THEN
IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
next_state <= INIT_MEM_WRITE;
mode_load_o <= '1';
run_traffic <= '0';
load_seed_o <= '1';
ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
run_traffic <= '1';
load_seed_o <= '1';
END IF;
ELSE
next_state <= IDLE;
run_traffic <= '0';
load_seed_o <= '0';
END IF;
WHEN INIT_MEM_WRITE =>
IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
run_traffic <= '1';
ELSE
next_state <= INIT_MEM_WRITE;
run_traffic <= '1';
mode_load_o <= '0';
load_seed_o <= '0';
IF (EYE_TEST = "TRUE") THEN
addr_mode <= FIXED_ADDR;
ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
addr_mode <= "000";
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
END IF;
WHEN INIT_MEM_READ =>
IF (end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
ELSE
next_state <= INIT_MEM_READ;
run_traffic <= '0';
mode_load_o <= '0';
load_seed_o <= '0';
END IF;
WHEN TEST_MEM =>
IF (cmp_error = '1') THEN
next_state <= CMP_ERROR1;
ELSE
next_state <= TEST_MEM;
END IF;
run_traffic <= '1';
IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
fixed_instr_o <= WR_INSTR;
ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
if (FAMILY = "VIRTEX6") then
fixed_bl_o <= fix_bl_value; --"000010"; 2
else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
fixed_bl_o <= "000000"; -- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
bl_mode_o_xhdl0 <= bl_mode_sel;
IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
addr_mode <= PRBS_ADDR;
ELSE
addr_mode <= addr_mode_sel;
END IF;
IF (PORT_MODE = "BI_MODE") THEN
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
WHEN CMP_ERROR1 =>
next_state <= CMP_ERROR1;
bl_mode_o_xhdl0 <= bl_mode_sel;
fixed_instr_o <= RD_INSTR;
addr_mode <= SEQUENTIAL_ADDR;
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
run_traffic <= '1';
WHEN OTHERS =>
next_state <= IDLE;
END CASE;
END PROCESS;
END trans;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/write_data_path.vhd | 20 | 9135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/cdcfifo/simulation/cdcfifo_tb.vhd | 3 | 6334 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
ENTITY cdcfifo_tb IS
END ENTITY;
ARCHITECTURE cdcfifo_arch OF cdcfifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from cdcfifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of cdcfifo_synth
cdcfifo_synth_inst:cdcfifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 12
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | hdl/jpeg_encoder/design/ByteStuffer.vhd | 5 | 9374 | -------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ByteStuffer is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
-- HOST IF
sof : in std_logic;
num_enc_bytes : out std_logic_vector(23 downto 0);
outram_base_addr : in std_logic_vector(9 downto 0);
-- Huffman
huf_buf_sel : out std_logic;
huf_fifo_empty : in std_logic;
huf_rd_req : out std_logic;
huf_packed_byte : in std_logic_vector(7 downto 0);
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity ByteStuffer;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ByteStuffer is
signal huf_data_val : std_logic_vector(3 downto 0);
signal wdata_reg : std_logic_vector(15 downto 0);
signal wraddr : unsigned(23 downto 0):=(others=>'0');
signal wr_n_cnt : unsigned(1 downto 0):=(others=>'0');
signal huf_buf_sel_s : std_logic:='0';
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal huf_rd_req_s : std_logic:='0';
signal latch_byte : std_logic_vector(7 downto 0):=(others=>'0');
signal data_valid : std_logic:='0';
signal wait_for_ndata : std_logic:='0';
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
huf_buf_sel <= huf_buf_sel_s;
huf_rd_req <= huf_rd_req_s;
-------------------------------------------------------------------
-- CTRL_SM
-------------------------------------------------------------------
p_ctrl_sm : process(CLK, RST)
begin
if RST = '1' then
wr_n_cnt <= (others => '0');
ready_pb <= '0';
huf_rd_req_s <= '0';
huf_data_val <= (others => '0');
rd_en <= '0';
rd_en_d1 <= '0';
wdata_reg <= (others => '0');
ram_wren <= '0';
wraddr <= (others => '0');
ram_wraddr <= (others => '0');
ram_byte <= (others => '0');
latch_byte <= (others => '0');
wait_for_ndata <= '0';
data_valid <= '0';
elsif CLK'event and CLK = '1' then
huf_rd_req_s <= '0';
ready_pb <= '0';
huf_data_val <= huf_data_val(huf_data_val'length-2 downto 0) & huf_rd_req_s;
rd_en_d1 <= rd_en;
ram_wren <= '0';
data_valid <= '0';
if start_pb = '1' then
rd_en <= '1';
end if;
-- read FIFO until it becomes empty. wait until last byte read is
-- serviced
if rd_en_d1 = '1' and wait_for_ndata = '0' then
-- FIFO empty
if huf_fifo_empty = '1' then
rd_en <= '0';
rd_en_d1 <= '0';
ready_pb <= '1';
else
huf_rd_req_s <= '1';
wait_for_ndata <= '1';
end if;
end if;
-- show ahead FIFO, capture data early
if huf_rd_req_s = '1' then
latch_byte <= huf_packed_byte;
data_valid <= '1';
end if;
if huf_data_val(1) = '1' then
wait_for_ndata <= '0';
end if;
-- data from FIFO is valid
if data_valid = '1' then
-- stuffing necessary
if latch_byte = X"FF" then
-- two writes are necessary for byte stuffing
wr_n_cnt <= "10";
wdata_reg <= X"FF00";
-- no stuffing
else
wr_n_cnt <= "01";
wdata_reg <= X"00" & latch_byte;
end if;
end if;
if wr_n_cnt > 0 then
wr_n_cnt <= wr_n_cnt - 1;
ram_wren <= '1';
wraddr <= wraddr + 1;
end if;
-- delayed to make address post-increment
ram_wraddr <= std_logic_vector(wraddr);
-- stuffing
if wr_n_cnt = 2 then
ram_byte <= wdata_reg(15 downto 8);
elsif wr_n_cnt = 1 then
ram_byte <= wdata_reg(7 downto 0);
end if;
if sof = '1' then
wraddr <= to_unsigned(C_HDR_SIZE,wraddr'length);
end if;
end if;
end process;
-------------------------------------------------------------------
-- HUFFMAN buf_sel
-------------------------------------------------------------------
p_huf_buf_sel : process(CLK, RST)
begin
if RST = '1' then
huf_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
huf_buf_sel_s <= not huf_buf_sel_s;
end if;
end if;
end process;
-------------------------------------------------------------------
-- num_enc_bytes
-------------------------------------------------------------------
p_num_enc_bytes : process(CLK, RST)
begin
if RST = '1' then
num_enc_bytes <= (others => '0');
elsif CLK'event and CLK = '1' then
-- plus 2 for EOI marker last bytes
num_enc_bytes <= std_logic_vector(wraddr + 2);
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/image_selector_fifo/simulation/image_selector_fifo_synth.vhd | 3 | 11486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY image_selector_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF image_selector_fifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: image_selector_fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 24,
C_DOUT_WIDTH => 24,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: image_selector_fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 24,
C_DIN_WIDTH => 24,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: image_selector_fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 24,
C_DIN_WIDTH => 24,
C_WR_PNTR_WIDTH => 8,
C_RD_PNTR_WIDTH => 8,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
image_selector_fifo_inst : image_selector_fifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/ddr2ram/example_design/rtl/memc3_wrapper.vhd | 6 | 46600 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/clkGen.vhd | 3 | 6638 | -- file: clkGen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____50.000______0.000______50.0______600.000____150.000
-- CLK_OUT3____10.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clkGen is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end clkGen;
architecture xilinx of clkGen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clkGen,clk_wiz_v3_6,{component_name=clkGen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 10.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkfx);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkdv);
end xilinx;
| bsd-2-clause |
mithro/HDMI2USB | ipcore_dir/cmdfifo/simulation/cmdfifo_pkg.vhd | 3 | 11502 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE cmdfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT cmdfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cmdfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cmdfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT cmdfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cmdfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT cmdfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END cmdfifo_pkg;
PACKAGE BODY cmdfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END cmdfifo_pkg;
| bsd-2-clause |
kennethlyn/ZYBOTemplate | hdl/vhdl/test.vhdl | 1 | 273 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity first is
Port(
led : out std_logic_vector(3 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end first;
architecture Behavioralfirst of first is
begin
led <= btn;
end Behavioralfirst;
| bsd-2-clause |
Alix82/mip32vhdl | alu.vhd | 1 | 15179 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mips_constants.all;
Entity alu is
port(clk : in std_logic;
reset : in std_logic;
pcF : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(5 downto 0);
func : in std_logic_vector(5 downto 0);
shamt : in std_logic_vector(4 downto 0);
InstReg1 : in std_logic_vector(4 downto 0);
InstReg2 : in std_logic_vector(4 downto 0);
InstReg3 : in std_logic_vector(4 downto 0);
instructionExt : in std_logic_vector(31 downto 0);
control : in std_logic_vector(11 downto 0);
fetch : in std_logic;
inwriteregdata : in std_logic_vector(31 downto 0);
inwritereg : in std_logic;
memtoreg : out std_logic;
memread : out std_logic;
memwrite : out std_logic;
outZero : out std_logic;
outAluResult : out std_logic_vector(31 downto 0);
outwriteData : out std_logic_vector(31 downto 0);
alu_pause : out std_logic
);
End alu;
Architecture rtl of alu is
component mult is
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component mult;
type register_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal register_memory: register_array := (
X"00000000", -- $zero 0
X"00000000", -- $at Reserved for Assembler 1
X"00000000", -- $v0 First return value 2
X"00000000", -- $v1 Second return value 3
X"00000000", -- $a0 Function arguments 4
X"00000000", -- $a1 ... 5
X"00000000", -- $a2 ... 6
X"00000000", -- $a3 ... 7
X"00000000", -- $t0 Temp Registers 8
X"00000000", -- $t1 9
X"00000000", -- $t2 10
X"00000000", -- $t3 11
X"00000000", -- $t4 12
X"00000000", -- $t5 13
X"00000000", -- $t6 14
X"00000000", -- $t7 15
X"00000000", -- $s0 Save Registers 16
X"00000000", -- $s1 17
X"00000000", -- $s2 18
X"00000000", -- $s3 19
X"00000000", -- $s4 20
X"00000000", -- $s5 21
X"00000000", -- $s6 22
X"00000000", -- $s7 23
X"00000000", -- $t8 Temp Registers 24
X"00000000", -- $t9 25
X"00000000", -- $k0 Reserved for OS 26
X"00000000", -- $k1 Reserved for OS 27
X"00000000", -- $gp Global Pointer 28
X"7FFFFFFF", -- $sp Stack Pointer 29
X"00000000", -- $fp Frame pointer 30
X"00000000");-- $ra Return address 31
signal alu_actual_func : std_logic_vector(5 downto 0) := (others => '0');
signal alu_actual_op : std_logic_vector(5 downto 0) := (others => '0');
signal debug_nreg1 : std_logic_vector(4 downto 0) := (others => '0');
signal debug_nreg2 : std_logic_vector(4 downto 0) := (others => '0');
signal debug_reg1data : std_logic_vector(31 downto 0) := (others => '0');
signal debug_reg2data : std_logic_vector(31 downto 0) := (others => '0');
signal debug_write_res : std_logic_vector(31 downto 0) := (others => '0');
signal debug_write_reg : std_logic_vector(4 downto 0) := (others => '0');
signal debug_control : std_logic_vector(11 downto 0) := (others => '0');
signal debug_alu_pc : std_logic_vector(31 downto 0) := (others => '0');
signal req_bit : std_logic := '0';
signal alu_counter : integer := 0;
signal write_reg_save : std_logic_vector(4 downto 0) := (others => '0');
signal alu_a, alu_b : std_logic_vector(31 downto 0):= (others => '0');
signal alu_mult_func : mult_function_type := (others => '0');
signal alu_mult_res : std_logic_vector(31 downto 0):= (others => '0');
signal alu_mult_pause : std_logic := '0';
begin
MULT0: mult port map (clk, reset, alu_a, alu_b, alu_mult_func, alu_mult_res, alu_mult_pause);
alu_pause <= alu_mult_pause;
process(clk)
Variable Res : std_logic_vector (31 downto 0);
Variable inReg1 : std_logic_vector (31 downto 0);
Variable inReg2 : std_logic_vector (31 downto 0);
Variable Res64 : std_logic_vector (63 downto 0);
Variable Zero : std_logic;
Variable Write_Reg : std_logic_vector(4 downto 0);
Variable Read1 : std_logic_vector(4 downto 0);
Variable Read2 : std_logic_vector(4 downto 0);
begin
if rising_edge(clk) then
debug_alu_pc <= pcF;
if inwritereg = '1' then
register_memory(to_integer(unsigned(write_reg_save))) <= inwriteregdata;
end if;
if alu_mult_pause = '1' then
alu_mult_func <= MULT_NOTHING;
elsif fetch = '1' then
Read1 := "00000";
Read2 := "00000";
inReg1 := X"00000000";
inReg2 := X"00000000";
debug_control <= control;
inReg1 := inwriteregdata;
Read1 := InstReg1;
if inwritereg = '1' and Read1 = write_reg_save then
inReg1 := inwriteregdata;
else
inReg1 := register_memory(to_integer(unsigned(Read1)));
end if;
if control(REG2OPERATION) = '0' then
if control(ALUSRC) = '1' then
inReg2 := instructionExt;
else
Read2 := InstReg2;
if inwritereg = '1' and Read2 = write_reg_save then
inReg2 := inwriteregdata;
else
inReg2 := register_memory(to_integer(unsigned(Read2)));
end if;
end if;
else
inReg2(4 downto 0) := InstReg2;
inReg2(31 downto 5) := ( others => '0');
end if;
--inReg2 := inReg1;
Res := "00000000000000000000000000000000";
Res64 := "0000000000000000000000000000000000000000000000000000000000000000";
Zero := '0';
debug_nreg1 <= Read1;
debug_nreg2 <= Read2;
debug_reg1data <= inReg1;
debug_reg2data <= inReg2;
alu_actual_func <= func;
alu_actual_op <= opcode;
case opcode is
when "000000" =>
case func is
when "001000" => Res := inReg1;
-- R-TYPE
when "100000" => Res := inReg1 + inReg2; -- add FIXME_ Trap
when "100001" => Res := inReg1 + inReg2; -- addu
when "100100" => Res := inReg1 and inReg2; -- and
when "100010" => Res := inReg1 - inReg2; -- sub
when "100011" => Res := inReg1 - inReg2; -- subu
when "100110" => Res := inReg1 xor inReg2;
-- SHIFTS
-- SLL
when "000000" => Res(31 downto to_integer(unsigned(shamt))) := inReg2(31 - to_integer(unsigned(shamt)) downto 0);
-- SRL
when "000010" => Res(31 - to_integer(unsigned(shamt)) downto 0) := inReg2(31 downto to_integer(unsigned(shamt)));
-- SLLV
when "000100" => Res(31 downto to_integer(unsigned(inReg1))) := inReg2(31 - to_integer(unsigned(inReg1)) downto 0);
-- SRLV
when "000110" => Res(31 - to_integer(unsigned(inReg1)) downto 0) := inReg2(31 downto to_integer(unsigned(inReg1)));
-- SRA
when "000011" =>
Res(31 - to_integer(unsigned(shamt)) downto 0) := inReg2(31 downto to_integer(unsigned(shamt)));
Res(0) := inReg2(31);
when "011011" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_DIVIDE;
when "011010" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_SIGNED_DIVIDE;
when "011000" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_SIGNED_MULT;
when "011001" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_MULT;
when "010000" =>
alu_mult_func <= MULT_READ_HI;
Res := alu_mult_res;
when "010010" =>
alu_mult_func <= MULT_READ_LO;
Res := alu_mult_res;
when others => null;
end case;
-- I-TYPE
when "001000" => Res := inReg1 + inReg2; -- ADDI
when "001001" => Res := inReg1 + inReg2; -- ADDIU
when "101011" => Res := inReg1 + inReg2; -- SW
when "100011" => Res := inReg1 + inReg2; -- LW
when "101000" => Res := inReg1 + inReg2; -- SB
when "100000" => Res := inReg1 + inReg2; -- LB
when "001110" => Res := inReg1 xor inReg2; -- XORI
when "001101" => Res := inReg1 or inReg2; -- ORI
when "001111" => Res(31 downto 16) := inReg2(15 downto 0); -- LUI
--- Branch
when "000100" => -- BEQ
if inReg1 = inReg2 then
Zero := '1';
else
Zero := '0';
end if;
when "000101" => -- BNE
if inReg1 = inReg2 then
Zero := '0';
else
Zero := '1';
end if;
--- inReg2 contains the branch operation to be performed
when "000001" => -- BGEZ/BGEZAL
case inReg2(3 downto 0) is
when "0001" => -- This includes 0 0001(BGEZ) and 1 0001(BGEZAL)
if inReg1 >= 0 then
Zero := '1';
else
Zero := '0';
end if;
when "0000" => -- This includes 1 0000(BLTZAL) and 0 0001(BLTZ)
if inReg1 < 0 then
Zero := '1';
else
Zero := '0';
end if;
when others => null;
end case;
--- BGTZ
when "000111" =>
if inReg1 > 0 then
Zero := '1';
else
Zero := '0';
end if;
--- BLEZ
when "000110" =>
if inReg1 <= 0 then
Zero := '1';
else
Zero := '0';
end if;
when others => null;
end case;
if control(MEM_TO_REG) = '0' then
if control(REG_WRITE) = '1' then
Write_Reg := InstReg2;
debug_write_res <= Res;
debug_write_reg <= Write_Reg;
register_memory(to_integer(unsigned(Write_Reg))) <= Res;
end if;
memtoreg <= '0';
else
memtoreg <= '1';
end if;
memread <= control(MEM_READ);
memwrite <= control(MEM_WRITE);
if control(MEM_READ) = '1' then
if control(REG_DEST) = '0' then
write_reg_save <= InstReg2;
else
write_reg_save <= InstReg3;
end if;
end if;
if control(MEM_WRITE) = '1' then
Read2 := InstReg2;
inReg2 := register_memory(to_integer(unsigned(Read2)));
outwriteData <= inReg2;
else
outwriteData <= (others => '0');
end if;
if control(LINK_RET) = '1' then
register_memory(31) <= pcF + 8;
end if;
outAluResult <= Res(31 downto 0);
outZero <= Zero;
else
memtoreg <= '0';
memread <= '0';
memwrite <= '0';
outZero <= '0';
outAluResult <= X"00000000";
alu_actual_func <= (others => '0');
end if;
end if;
end process;
end;
| bsd-2-clause |
lowRISC/greth-library | greth_library/techmap/mem/sram8_inferred_init.vhd | 2 | 2273 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
--! @details This module absolutely similar to the 'inferred' implementation
--! but it support initialization of the SRAM.
--! This feature is very useful during RTL simulation so that
--! current FW supports skipping of the copying FwImage state.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred_init is
generic (
abits : integer := 12;
byte_idx : integer := 0;
init_file : string
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred_init of sram8_inferred_init is
constant FILE_IMAGE_LINES_TOTAL : integer := 16384;
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(127 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv((byte_idx+1)*8-1 downto 8*byte_idx);
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type := init_ram(init_file);
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
| bsd-2-clause |
lowRISC/greth-library | greth_library/techmap/bufg/iobuf_tech.vhd | 2 | 1642 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual IO buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity iobuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end;
architecture rtl of iobuf_tech is
component iobuf_inferred is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_virtex6 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_micron180 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
begin
inf0 : if generic_tech = inferred generate
bufinf : iobuf_inferred port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
xv6 : if generic_tech = virtex6 or generic_tech = kintex7 or generic_tech = artix7 generate
bufv6 : iobuf_virtex6 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
m180 : if generic_tech = micron180 generate
bufm : iobuf_micron180 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
end;
| bsd-2-clause |
lowRISC/greth-library | greth_library/techmap/mem/romimage_tech.vhd | 2 | 1403 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific ROM Image with the Firmware
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity RomImage_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture arch_RomImage_tech of RomImage_tech is
component RomImage_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
begin
genrom0 : if memtech = inferred or is_fpga(memtech) /= 0 generate
infer0 : RomImage_inferred generic map (
hex_filename => sim_hexfile
) port map (clk, address, data);
end generate;
end;
| bsd-2-clause |
lowRISC/greth-library | greth_library/techmap/pll/clkp90_tech.vhd | 2 | 2149 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Virtual clock phase offset generator (90 deg)
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
--! clock frequency in KHz
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_tech;
architecture rtl of clkp90_tech is
component clkp90_virtex6 is
port (
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic
);
end component;
component clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
begin
xv6 : if tech = virtex6 generate
v1 : clkp90_virtex6 port map (
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90
);
o_clk2x <= '0';
o_lock <= '0';
end generate;
xl7 : if tech = kintex7 or tech = artix7 or tech = zynq7000 generate
v1 : clkp90_kintex7 generic map (
freq => freq
) port map (
i_rst => i_rst,
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90,
o_clk2x => o_clk2x,
o_lock => o_lock
);
end generate;
inf : if tech = inferred generate
o_clk <= i_clk;
o_clkp90 <= i_clk;
o_clk2x <= '0';
o_lock <= '0';
end generate;
m180 : if tech = micron180 generate
end generate;
end;
| bsd-2-clause |
lowRISC/greth-library | greth_library/rocketlib/eth/greth_rx.vhd | 2 | 11635 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
v.mcasthash := (others => '0');
v.dataout := (others => '0');
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
| bsd-2-clause |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/src/vgagraph_fifo/synth/vgagraph_fifo.vhd | 1 | 38941 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY vgagraph_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END vgagraph_fifo;
ARCHITECTURE vgagraph_fifo_arch OF vgagraph_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF vgagraph_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF vgagraph_fifo_arch : ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=16,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" &
"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_T" &
"HRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=2048,C_RD_FREQ=1,C_RD_PNTR_WIDTH=11,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTE" &
"RFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_W" &
"IDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_T" &
"YPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C" &
"_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=" &
"10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=" &
"1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_AS" &
"SERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 16,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 2048,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 11,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END vgagraph_fifo_arch;
| bsd-2-clause |
tristanseifert/68komputer | BusRouter.vhd | 1 | 7686 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BusRouter is
PORT(
SW: IN std_logic_vector(9 downto 0);
KEY: IN std_logic_vector(3 downto 0);
LEDR: OUT std_logic_vector(9 downto 0) := (others => '0');
LEDG: OUT std_logic_vector(7 downto 0) := (others => '0');
CLOCK_24: IN std_logic_vector(1 downto 0);
CLOCK_27: IN std_logic_vector(1 downto 0);
CLOCK_50: IN std_logic;
-- video
VGA_R: OUT std_logic_vector(3 downto 0);
VGA_G: OUT std_logic_vector(3 downto 0);
VGA_B: OUT std_logic_vector(3 downto 0);
VGA_VS: OUT std_logic := '0';
VGA_HS: OUT std_logic := '0';
-- SRAM
SRAM_ADDR: OUT std_logic_vector(17 downto 0);
SRAM_DQ: INOUT std_logic_vector(15 downto 0);
SRAM_CE_N: OUT std_logic;
SRAM_OE_N: OUT std_logic;
SRAM_WE_N: OUT std_logic;
SRAM_LB_N: OUT std_logic;
SRAM_UB_N: OUT std_logic;
-- SDRAM
DRAM_CS_N: OUT std_logic;
DRAM_WE_N: OUT std_logic;
DRAM_CAS_N: OUT std_logic;
DRAM_RAS_N: OUT std_logic;
DRAM_ADDR: OUT std_logic_vector(11 downto 0);
DRAM_BA_0: OUT std_logic;
DRAM_BA_1: OUT std_logic;
DRAM_CKE: OUT std_logic;
DRAM_CLK: OUT std_logic;
DRAM_DQ: INOUT std_logic_vector(15 downto 0);
DRAM_LDQM: OUT std_logic;
DRAM_UDQM: OUT std_logic;
-- Flash memory
FL_ADDR: OUT std_logic_vector(21 downto 0);
FL_DQ: INOUT std_logic_vector(7 downto 0);
FL_OE_N: OUT std_logic := '1';
FL_RST_N: OUT std_logic := '1';
FL_WE_N: OUT std_logic := '1';
-- PS2
PS2_CLK: INOUT std_logic;
PS2_DAT: INOUT std_logic;
-- SD card
SD_MISO: IN std_logic;
SD_MOSI: OUT std_logic;
SD_SCLK: OUT std_logic;
SD_CS: OUT std_logic;
-- UART
UART_RXD: IN std_logic;
UART_TXD: OUT std_logic;
-- audio codec
I2C_SCLK: INOUT std_logic;
I2C_SDAT: INOUT std_logic;
AUD_ADCDAT: IN std_logic;
AUD_ADCLRCK: OUT std_logic;
AUD_BCLK: OUT std_logic;
AUD_XCK: OUT std_logic;
AUD_DACDAT: OUT std_logic;
AUD_DACLRCK: OUT std_logic;
-- seven segment displays
HEX0: OUT std_logic_vector(6 downto 0);
HEX1: OUT std_logic_vector(6 downto 0);
HEX2: OUT std_logic_vector(6 downto 0);
HEX3: OUT std_logic_vector(6 downto 0)
);
end BusRouter;
architecture behavioral of BusRouter is
signal clk_cpu: std_logic;
signal clk_sdram: std_logic;
signal sys_reset: std_logic := '1';
-- 68k bus: system control
signal bus_reset: std_logic := '1';
signal bus_clk: std_logic; -- CPU clock
signal bus_halt: std_logic := '1';
signal bus_error: std_logic := '1';
-- 68k bus: data
signal bus_data: std_logic_vector(15 downto 0) := (others => 'Z');
signal bus_addr: std_logic_vector(23 downto 0) := (others => '0');
-- 68k bus: bus control
signal bus_as: std_logic := '1';
signal bus_rw: std_logic := '1'; -- read = 1, write = 0
signal bus_uds: std_logic := '1'; -- upper and lower byte strobes
signal bus_lds: std_logic := '1';
signal bus_dtack: std_logic := '1'; -- data acknowledge, driven by peripheral
-- 68k bus: bus arbitration
signal bus_br: std_logic := '1'; -- assert to request bus
signal bus_bg: std_logic := '1'; -- asserted when bus is free
signal bus_bgack: std_logic := '1'; -- assert to acknowledge bus request
-- 68k bus: interrupt control
signal bus_irq: std_logic_vector(2 downto 0) := (others => '1');
-- 68k bus: processor status
signal bus_fc: std_logic_vector(3 downto 0);
-- 5Hz blink clock generator
signal blink_clk: std_logic;
-- chip selects for various HW (low active)
signal cs_rom: std_logic := '1';
signal cs_ram: std_logic := '1';
signal cs_video: std_logic := '1';
begin
-- VDP
u_VideoController: entity work.VideoController(behavioral)
port map(
reset => sys_reset,
In_Clk_24 => CLOCK_24(0),
Out_R => VGA_R,
Out_G => VGA_G,
Out_B => VGA_B,
Out_HSync => VGA_HS,
Out_VSync => VGA_VS,
SRAM_Addr => SRAM_ADDR,
SRAM_Data => SRAM_DQ,
SRAM_CE => SRAM_CE_N,
SRAM_OE => SRAM_OE_N,
SRAM_WE => SRAM_WE_N,
SRAM_LB => SRAM_LB_N,
SRAM_UB => SRAM_UB_N,
-- bus interface
bus_clk => bus_clk,
bus_data => bus_data,
bus_address => bus_addr(18 downto 0),
bus_rw => bus_rw,
bus_as => bus_as,
bus_dtack => bus_dtack,
bus_uds => bus_uds,
bus_lds => bus_lds,
bus_cs => cs_video
);
-- SDRAM controller
u_sdram: entity work.BusSDRAM(behavioral)
port map(
reset => sys_reset,
reset_n => bus_reset,
sdram_clk => clk_sdram,
bus_cs => cs_ram,
bus_clk => clk_cpu,
bus_address => bus_addr (22 downto 0),
bus_data => bus_data,
bus_rw => bus_rw,
bus_as => bus_as,
bus_dtack => bus_dtack,
bus_uds => bus_uds,
bus_lds => bus_lds,
DRAM_CS_N => DRAM_CS_N,
DRAM_WE_N => DRAM_WE_N,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA_0 => DRAM_BA_0,
DRAM_BA_1 => DRAM_BA_1,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_DQ => DRAM_DQ,
DRAM_LDQM => DRAM_LDQM,
DRAM_UDQM => DRAM_UDQM
);
-- bus PLL
u_buspll: entity work.BusPLL(SYN)
port map(
areset => sys_reset,
inclk0 => CLOCK_50,
c0 => clk_cpu,
c1 => clk_sdram
);
-- debug monitor
u_monitor: entity work.BusMonitor(behavioral)
port map(
clk_cpu => clk_cpu,
blink_clk => blink_clk,
sys_reset => sys_reset,
bus_reset => bus_reset,
bus_clk => bus_clk,
bus_halt => bus_halt,
bus_error => bus_error,
bus_data => bus_data,
bus_addr => bus_addr,
bus_as => bus_as,
bus_rw => bus_rw,
bus_uds => bus_uds,
bus_lds => bus_lds,
bus_dtack => bus_dtack,
bus_br => bus_br,
bus_bg => bus_bg,
bus_bgack => bus_bgack,
bus_irq => bus_irq,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
SW => SW,
KEY => KEY,
LEDR => LEDR,
LEDG => LEDG
);
-- Address decoder: tied to the FALLING edge of bus_clk
process (bus_clk, sys_reset, bus_as)
begin
-- if reset, make sure everything is deselected
if sys_reset='1' then
-- decode address
elsif falling_edge(bus_clk) then
-- is the address on the bus valid?
if bus_as='0' then
-- decode high nybble
case bus_addr(23 downto 20) is
when x"0" =>
cs_rom <= '0';
when x"1" =>
cs_ram <= '0';
when x"2" =>
cs_ram <= '0';
when x"3" =>
cs_ram <= '0';
when x"4" =>
cs_ram <= '0';
when x"5" =>
cs_ram <= '0';
when x"6" =>
cs_ram <= '0';
when x"7" =>
cs_ram <= '0';
when x"8" =>
cs_ram <= '0';
when x"9" => -- video controller
cs_video <= '0';
when x"A" =>
when x"B" =>
when x"C" =>
when x"D" =>
when x"E" =>
when x"F" =>
end case;
else
-- address invalid
cs_rom <= '1';
cs_ram <= '1';
cs_video <= '1';
end if;
end if;
end process;
-- LED blink clock generator
process (clk_cpu, sys_reset)
variable cnt: integer := 0;
begin
if sys_reset='1'
then
cnt := 0;
elsif rising_edge(clk_cpu) then
if cnt = 741337
then
blink_clk <= NOT blink_clk;
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end process;
-- reset logic
bus_reset <= NOT sys_reset;
end behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/backup/stage_polynomial_calc.vhd | 1 | 3067 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc
-- Module Name: Stage_Polynomial_Calc
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the school book algorithm of powering x
-- and multiplying by the respective polynomial coefficient and adding into the accumulator.
-- This method is not appropriate for this computation, so in stage_polynomial_calc_v2
-- Horner scheme is applied to reduce circuits costs.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_x_pow : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc;
architecture Behavioral of stage_polynomial_calc is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_a : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_b : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_o : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal sigma_i_1 : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
begin
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_sigma : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_sigma_a,
b => mult_sigma_b,
o => mult_sigma_o
);
mult_x_a <= value_x;
mult_x_b <= value_x_pow;
mult_sigma_a <= value_polynomial_coefficient;
mult_sigma_b <= value_x_pow;
sigma_i_1 <= mult_sigma_o;
new_value_x_pow <= mult_x_o;
new_value_acc <= sigma_i_1 xor value_acc;
end Behavioral;
| bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_file.vhd | 1 | 4218 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM
-- Module Name: RAM_File
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM. Only used for tests.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
memory_ram(to_integer(unsigned(address))) <= data_in;
end if;
data_out <= memory_ram(to_integer(unsigned(address)));
end if;
end process;
end file_load; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/backup/solving_key_equation_1_v2.vhd | 1 | 22450 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1_v2
-- Module Name: Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is the second circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version with a pipeline approach was made called solving_key_equation_2.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_1_v2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_load_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_1_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_1_v2;
architecture Behavioral of solving_key_equation_1_v2 is
component controller_solving_key_equation_1_v2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
sel_new_value_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_address_FB_ce : out STD_LOGIC;
ctr_address_FB_load : out STD_LOGIC;
ctr_address_GC_ce : out STD_LOGIC;
ctr_address_GC_load : out STD_LOGIC;
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component counter_decrement_load_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_load : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_d : STD_LOGIC;
signal sel_ctr_i_rst_value : STD_LOGIC;
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_rst : STD_LOGIC;
signal reg_j_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_FB : STD_LOGIC;
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_GC : STD_LOGIC;
signal ctr_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_F_ce : STD_LOGIC;
signal ctr_degree_F_load : STD_LOGIC;
signal ctr_degree_F_rst : STD_LOGIC;
constant ctr_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_ce : STD_LOGIC;
signal ctr_degree_B_load : STD_LOGIC;
signal ctr_degree_B_rst : STD_LOGIC;
constant ctr_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal ctr_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_degree_B : STD_LOGIC;
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_load_new_value_FB : STD_LOGIC;
signal int_new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal address_i_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_G : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_minus_j_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC;
signal ctr_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_FB_ce : STD_LOGIC;
signal ctr_address_FB_load : STD_LOGIC;
signal ctr_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_ce : STD_LOGIC;
signal ctr_address_GC_load : STD_LOGIC;
signal ctr_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal BC_calculation : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal sel_new_value_inv : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_1_v2
Port Map(
clk => clk,
rst => rst,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
sel_new_value_inv => sel_new_value_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_load => ctr_i_load,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
sel_ctr_i_d => sel_ctr_i_d,
reg_j_ce => reg_j_ce,
reg_j_rst => reg_j_rst,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
sel_reg_FB => sel_reg_FB,
sel_load_new_value_FB => sel_load_new_value_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
sel_reg_GC => sel_reg_GC,
ctr_degree_F_ce => ctr_degree_F_ce,
ctr_degree_F_load => ctr_degree_F_load,
ctr_degree_F_rst => ctr_degree_F_rst,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
ctr_degree_B_ce => ctr_degree_B_ce,
ctr_degree_B_load => ctr_degree_B_load,
ctr_degree_B_rst => ctr_degree_B_rst,
sel_ctr_degree_B => sel_ctr_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
ctr_address_FB_ce => ctr_address_FB_ce,
ctr_address_FB_load => ctr_address_FB_load,
ctr_address_GC_ce => ctr_address_GC_ce,
ctr_address_GC_load => ctr_address_GC_load,
BC_calculation => BC_calculation,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_d,
clk => clk,
ce => ctr_i_ce,
load => ctr_i_load,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
rst => reg_j_rst,
rst_value => reg_j_rst_value,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
ctr_degree_F : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_F_d,
clk => clk,
ce => ctr_degree_F_ce,
load => ctr_degree_F_load,
rst => ctr_degree_F_rst,
rst_value => ctr_degree_F_rst_value,
q => ctr_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
ctr_degree_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_B_d,
clk => clk,
ce => ctr_degree_B_ce,
load => ctr_degree_B_load,
rst => ctr_degree_B_rst,
rst_value => ctr_degree_B_rst_value,
q => ctr_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
ctr_address_FB : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_FB_d,
clk => clk,
ce => ctr_address_FB_ce,
load => ctr_address_FB_load,
q => ctr_address_FB_q
);
ctr_address_GC : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_GC_d,
clk => clk,
ce => ctr_address_GC_ce,
load => ctr_address_GC_load,
q => ctr_address_GC_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_d <= ctr_degree_F_q when sel_ctr_i_d = '1' else
degree_C_plus_j;
ctr_i_rst_value <= ctr_i_rst_value_F when sel_ctr_i_rst_value = '1' else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(ctr_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= (base_mult_o xor reg_FB_q) when sel_load_new_value_FB = '1' else
std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_FB = '1' else
int_value_FB;
reg_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_GC = '1' else
int_value_GC;
ctr_degree_F_d <= reg_degree_G_q;
reg_degree_G_d <= ctr_degree_F_q;
ctr_degree_B_d <= degree_C_plus_j when sel_ctr_degree_B = '1' else
reg_degree_C_q;
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= ctr_degree_B_q;
reg_swap_d <= not reg_swap_q;
int_new_value_FB <= reg_FB_q;
int_new_value_GC <= reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= int_new_value_FB when sel_new_value_inv = '1' else
int_new_value_GC;
new_value_FB <= int_new_value_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_FB;
new_value_GC <= int_new_value_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_GC;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_i_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_FB'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_F <= ctr_degree_F_q;
address_degree_G <= reg_degree_G_q;
address_i_minus_j_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_minus_j_GC'length) + unsigned(i_minus_j)) when BC_calculation = '1' else
i_minus_j;
ctr_address_FB_d <= address_degree_F when sel_address_FB = '1' else
address_i_FB;
ctr_address_GC_d <= address_degree_G when sel_address_GC = '1' else
address_i_minus_j_GC;
address_FB <= ctr_address_GC_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_FB_q;
address_GC <= ctr_address_FB_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_GC_q;
FB_equal_zero <= '1' when (int_new_value_FB = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(ctr_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (ctr_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(ctr_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral;
| bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_rst_nbits.vhd | 1 | 1748 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_n_bits
-- Module Name: Counter_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only increments when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_rst_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_rst_nbits;
architecture Behavioral of counter_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
| bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_rst_set_nbits.vhd | 1 | 1985 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_set_n_bits
-- Module Name: Counter_rst_set_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset and set signal, that only increments when ce equals to 1.
-- The reset and set are synchronous.
-- The value loaded during reset is defined by reset_value.
-- The value loaded during set is defined by set_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_rst_set_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_rst_set_nbits;
architecture Behavioral of counter_rst_set_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(set = '1') then
internal_value <= unsigned(set_value);
elsif(ce = '1') then
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/backup/controller_syndrome_calculator_2_pipe_v3_slave.vhd | 1 | 18645 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2_pipe_v3_slave
-- Module Name: Controller_Syndrome_Calculator_2_pipe_v3_slave
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n_pipe_v3_slave
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2_pipe_v3_slave is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end controller_syndrome_calculator_2_pipe_v3_slave;
architecture Behavioral of controller_syndrome_calculator_2_pipe_v3_slave is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, wait_for_other_units, prepare_synd, prepare_synd_2, prepare_synd_3, load_store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, reg_codeword_q, start_calculation, last_syndrome, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when load_counters =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when prepare_values =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when load_values =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when wait_for_other_units =>
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_2 =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_3 =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when load_store_synd =>
if(last_syndrome = '1') then
if(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when final =>
ready_calculation <= '1';
finished_calculation <= '1';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '1';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when others =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, reg_codeword_q, start_calculation, last_syndrome, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= jump_codeword;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= jump_codeword;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
else
next_state <= clear_remaining_units;
end if;
when wait_for_other_units =>
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
when prepare_synd =>
next_state <= prepare_synd_2;
when prepare_synd_2 =>
next_state <= prepare_synd_3;
when prepare_synd_3 =>
next_state <= load_store_synd;
when load_store_synd =>
if(last_syndrome = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= jump_codeword;
end if;
else
next_state <= load_store_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/tb_find_correct_errors_n_v4.vhd | 1 | 26854 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v4
-- Module Name: Tb_Find_Correct_Errors_N_v4
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for polynomial_syndrome_computing_n_v2 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the size of the pipeline.
-- This is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
-- x_memory_file :
--
-- File that holds the values to be evaluated on the polynomial. Support elements L.
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
--
-- resp_memory_file :
--
-- File that holds all evaluations of support L on polynomial sigma.
-- This file holds the output of the circuit,
-- it is needed to detect if polynomial evaluator circuit worked properly.
--
-- dump_acc_memory_file :
--
-- File that will hold the output of all support L evaluations on polynomial sigma,
-- that were done by the circuit.
--
-- codeword_memory_file :
--
-- File that holds the ciphertext that will be corrected according to the polynomial
-- sigma roots that were found.
--
-- message_memory_file :
--
-- File that holds the ciphertext already corrected.
-- This file is necessary to detect
-- if the ciphertext correction was performed correctly by the circuit.
--
-- dump_codeword_memory_file :
--
-- File that will hold the ciphertext corrected by the circuit.
--
-- dump_error_memory_file :
--
-- File that will hold the errors found on the ciphertext by the circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n_v2 Rev 1.0
-- ram Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_find_correct_errors_n_v4 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- sigma_degree : integer := 4;
-- size_sigma_degree : integer := 2;
-- length_support_elements: integer := 52;
-- size_support_elements : integer := 6;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_52_28_4_6.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_52_28_4_6.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 4;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 27;
-- size_sigma_degree : integer := 5;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1751_27_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1751_27_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1751_27_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 50;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1498_50_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1498_50_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1498_50_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 66;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_3307_2515_66_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_3307_2515_66_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_3307_2515_66_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 33;
size_pipeline_size : integer := 6;
gf_2_m : integer range 1 to 20 := 12;
sigma_degree : integer := 32;
size_sigma_degree : integer := 6;
length_support_elements: integer := 2528;
size_support_elements : integer := 12;
x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12.dat";
resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2528_2144_32_12.dat";
dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2528_2144_32_12.dat";
dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2816_2048_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_3328_2560_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 129;
-- size_pipeline_size : integer := 8;
-- gf_2_m : integer range 1 to 20 := 13;
-- sigma_degree : integer := 128;
-- size_sigma_degree : integer := 8;
-- length_support_elements: integer := 7296;
-- size_support_elements : integer := 13;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_7296_5632_128_13.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_7296_5632_128_13.dat"
);
end tb_find_correct_errors_n_v4;
architecture Behavioral of tb_find_correct_errors_n_v4 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component polynomial_syndrome_computing_n_v2
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
number_of_errors : integer;
size_number_of_errors : integer;
number_of_support_elements : integer;
size_number_of_support_elements : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal mode_polynomial_syndrome : STD_LOGIC;
signal computation_finalized : STD_LOGIC;
signal address_value_polynomial : STD_LOGIC_VECTOR((size_sigma_degree - 1) downto 0);
signal address_value_x : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_sigma_degree) downto 0);
signal address_value_error : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_acc : STD_LOGIC;
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_value_error : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_error : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant test_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant true_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant error_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant x_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant sigma_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant true_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant test_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
signal test_codeword_dump : std_logic := '0';
signal true_codeword_dump : std_logic := '0';
signal x_dump : std_logic := '0';
signal sigma_dump : std_logic := '0';
signal true_acc_dump : std_logic := '0';
signal test_acc_dump : std_logic := '0';
signal error_dump : std_logic := '0';
signal test_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal test_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_value : STD_LOGIC_VECTOR (((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal true_codeword_value : STD_LOGIC_VECTOR ((number_of_pipelines - 1) downto 0);
signal error_acc : STD_LOGIC;
signal error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for true_codeword : ram_bank use entity work.ram_bank(file_load);
for test_codeword : ram_double_bank use entity work.ram_double_bank(file_load);
for x : ram_bank use entity work.ram_bank(file_load);
for sigma : ram use entity work.ram(file_load);
for true_acc : ram_bank use entity work.ram_bank(file_load);
for test_acc : ram_double_bank use entity work.ram_double_bank(simple);
for error : ram_bank use entity work.ram_bank(simple);
begin
test_codeword : ram_double_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => dump_codeword_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_message,
rw_a => '0',
rw_b => write_enable_new_value_message,
clk => clk,
rst => rst,
dump => test_codeword_dump,
address_a => test_codeword_address,
address_b => address_new_value_message,
rst_value => test_codeword_rst_value,
data_out_a => value_message,
data_out_b => open
);
error : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_error_memory_file
)
Port Map(
data_in => value_error,
rw => write_enable_value_error,
clk => clk,
rst => rst,
dump => error_dump,
address => address_value_error,
rst_value => error_rst_value,
data_out => open
);
true_codeword : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_codeword_dump,
address => true_codeword_address,
rst_value => true_codeword_rst_value,
data_out => true_codeword_value
);
x : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => x_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => x_dump,
address => address_value_x,
rst_value => x_rst_value,
data_out => value_x
);
true_acc : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => resp_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_acc_dump,
address => true_acc_address,
rst_value => true_acc_rst_value,
data_out => true_acc_value
);
test_acc : ram_double_bank
Generic Map(
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_acc_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_acc,
rw_a => '0',
rw_b => write_enable_new_value_acc,
clk => clk,
rst => rst,
dump => test_acc_dump,
address_a => test_acc_address,
address_b => address_new_value_acc,
rst_value => test_acc_rst_value,
data_out_a => value_acc,
data_out_b => open
);
sigma : ram
Generic Map (
ram_address_size => size_sigma_degree,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => sigma_dump,
address => address_value_polynomial,
rst_value => sigma_rst_value,
data_out => value_polynomial
);
poly : polynomial_syndrome_computing_n_v2
Generic Map(
number_of_pipelines => number_of_pipelines,
pipeline_size => pipeline_size,
size_pipeline_size => size_pipeline_size,
gf_2_m => gf_2_m,
number_of_support_elements => length_support_elements,
size_number_of_support_elements => size_support_elements,
number_of_errors => sigma_degree,
size_number_of_errors => size_sigma_degree
)
Port Map(
value_x => value_x,
value_acc => value_acc,
value_polynomial => value_polynomial,
value_message => value_message,
value_h => value_h,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
rst => rst,
computation_finalized => computation_finalized,
address_value_polynomial => address_value_polynomial,
address_value_x => address_value_x,
address_value_acc => address_value_acc,
address_value_message => address_value_message,
address_new_value_message => address_new_value_message,
address_new_value_acc => address_new_value_acc,
address_new_value_syndrome => address_new_value_syndrome,
address_value_error => address_value_error,
write_enable_new_value_acc => write_enable_new_value_acc,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_value_error => write_enable_value_error,
new_value_syndrome => new_value_syndrome,
new_value_acc => new_value_acc,
new_value_message => new_value_message,
value_error => value_error
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
test_acc_address <= address_value_acc when computation_finalized = '0' else
true_acc_address;
test_codeword_address <= address_value_x when computation_finalized = '0' else
true_codeword_address;
mode_polynomial_syndrome <= '0';
process
variable i : integer;
begin
true_acc_address <= (others => '0');
true_codeword_address <= (others => '0');
rst <= '1';
error_acc <= '0';
error_message <= '0';
wait for PERIOD*2;
rst <= '0';
wait until computation_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_support_elements)) loop
error_message <= '0';
error_acc <= '0';
true_acc_address <= std_logic_vector(to_unsigned(i, true_acc_address'Length));
true_codeword_address <= std_logic_vector(to_unsigned(i, true_codeword_address'Length));
wait for PERIOD*2;
if (true_acc_value = value_acc) then
error_acc <= '0';
else
error_acc <= '1';
report "Computed values do not match expected ones";
end if;
if (true_codeword_value = value_message) then
error_message <= '0';
else
error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_acc <= '0';
error_message <= '0';
wait for PERIOD;
i := i + number_of_pipelines;
end loop;
error_message <= '0';
error_acc <= '0';
test_acc_dump <= '1';
test_codeword_dump <= '1';
wait for PERIOD;
test_acc_dump <= '0';
test_codeword_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/controller_polynomial_syndrome_computing.vhd | 1 | 37642 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Syndrome_Computing
-- Module Name: Controller_Polynomial_Syndrome_Computing
-- Project Name: McEliece Goppa decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit is the state machine for polynomial_syndrome_computing_n_v2.
-- This state machine is for both during syndrome computation and polynomial sigma
-- evaluation and roots search.
--
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_syndrome_computing is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_syndrome_ce : out STD_LOGIC;
ctr_address_polynomial_syndrome_load : out STD_LOGIC;
ctr_address_polynomial_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_polynomial_syndrome_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_mode_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
computation_finalized : out STD_LOGIC
);
end controller_polynomial_syndrome_computing;
architecture Behavioral of controller_polynomial_syndrome_computing is
type State is (reset, poly_load_counter, poly_load_first_polynomial_coefficient, poly_reset_first_polynomial_coefficient, poly_prepare_load_polynomial_coefficient, poly_load_polynomial_coefficient, poly_reset_polynomial_coefficient, poly_load_x, poly_load_x_write_x, poly_last_load_x_write_x, poly_write_x, poly_final,
synd_load_counter, synd_load_L_syndrome_values, synd_prepare_write_load_L_values, synd_write_load_L_values, synd_prepare_write_L_values, synd_write_L_values, synd_write_syndrome_values, synd_last_write_syndrome_values, synd_final_write_syndrome_values, synd_final_last_write_syndrome_values, synd_final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_load_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '1';
when synd_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_load_L_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_load_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
ctr_load_x_address_ce <= '0';
else
ctr_load_x_address_ce <= '1';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_L_values =>
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_ce <= '1';
else
reg_final_syndrome_evaluation_ce <= '0';
end if;
if(last_store_x_values = '1') then
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
reg_store_temporary_syndrome_ce <= '1';
shift_polynomial_ce_rst <= '1';
else
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
reg_store_temporary_syndrome_ce <= '0';
shift_polynomial_ce_rst <= '0';
end if;
evaluation_data_in <= '1';
ctr_load_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '0';
shift_polynomial_ce_ce <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_last_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_write_syndrome_values =>
if(final_syndrome_evaluation = '1' and last_syndrome_value = '0') then
write_enable_new_value_syndrome <= '0';
else
write_enable_new_value_syndrome <= '1';
end if;
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_rst <= '1';
else
reg_final_syndrome_evaluation_rst <= '0';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_last_write_syndrome_values =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, mode_polynomial_syndrome, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
if(mode_polynomial_syndrome = '1') then
next_state <= synd_load_counter;
else
next_state <= poly_load_counter;
end if;
when poly_load_counter =>
next_state <= poly_load_first_polynomial_coefficient;
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_first_polynomial_coefficient;
else
next_state <= poly_load_first_polynomial_coefficient;
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_first_polynomial_coefficient;
end if;
when poly_prepare_load_polynomial_coefficient =>
next_state <= poly_load_polynomial_coefficient;
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_polynomial_coefficient;
else
next_state <= poly_load_polynomial_coefficient;
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_polynomial_coefficient;
end if;
when poly_load_x =>
next_state <= poly_load_x_write_x;
when poly_load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= poly_last_load_x_write_x;
else
next_state <= poly_prepare_load_polynomial_coefficient;
end if;
else
next_state <= poly_load_x_write_x;
end if;
when poly_last_load_x_write_x =>
next_state <= poly_write_x;
when poly_write_x =>
if(last_store_x_values = '1') then
next_state <= poly_final;
else
next_state <= poly_write_x;
end if;
when poly_final =>
next_state <= poly_final;
when synd_load_counter =>
next_state <= synd_load_L_syndrome_values;
when synd_load_L_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_prepare_write_load_L_values;
else
next_state <= synd_load_L_syndrome_values;
end if;
when synd_prepare_write_load_L_values =>
next_state <= synd_write_load_L_values;
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
next_state <= synd_prepare_write_L_values;
else
next_state <= synd_write_load_L_values;
end if;
when synd_prepare_write_L_values =>
next_state <= synd_write_L_values;
when synd_write_L_values =>
if(last_store_x_values = '1') then
if(final_syndrome_evaluation = '1' or last_syndrome_value = '1') then
next_state <= synd_final_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
else
next_state <= synd_write_L_values;
end if;
when synd_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_last_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
when synd_last_write_syndrome_values =>
next_state <= synd_write_load_L_values;
when synd_final_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_final_last_write_syndrome_values;
else
next_state <= synd_final_write_syndrome_values;
end if;
when synd_final_last_write_syndrome_values =>
next_state <= synd_final;
when synd_final =>
next_state <= synd_final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/backup/mceliece_qd_goppa_decrypt_v2.vhd | 1 | 26241 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v2
-- Module Name: McEliece_QD-Goppa_Decrypt_v2
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Roots.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, polynomial_syndrome_computing_n, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_4, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, polynomial_syndrome_computing_n, find the roots of polynomial sigma
-- and correct respective errors in the ciphertext and obtains plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_4.
-- This circuit was made outside of solving_key_equation_4 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n Rev 1.0
-- solving_key_equation_4 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- register_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
polynomial_evaluator_syndrome_pipeline_size : integer := 18;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt_v2;
architecture Behavioral of mceliece_qd_goppa_decrypt_v2 is
component polynomial_syndrome_computing_n
Generic (
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR(((gf_2_m) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component solving_key_equation_4
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
signal polynomial_evaluator_syndrome_value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_mode_polynomial_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_rst : STD_LOGIC;
signal polynomial_evaluator_syndrome_computation_finalized : STD_LOGIC;
signal polynomial_evaluator_syndrome_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_x : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal polynomial_evaluator_syndrome_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_message : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_value_error : STD_LOGIC;
signal polynomial_evaluator_syndrome_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
polynomial_evaluator_syndrome : polynomial_syndrome_computing_n
Generic Map(
number_of_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors,
number_of_support_elements => length_codeword,
size_number_of_support_elements => size_codeword
)
Port Map(
value_x => polynomial_evaluator_syndrome_value_x,
value_acc => polynomial_evaluator_syndrome_value_acc,
value_polynomial => polynomial_evaluator_syndrome_value_polynomial,
value_message => polynomial_evaluator_syndrome_value_message,
value_h => polynomial_evaluator_syndrome_value_h,
mode_polynomial_syndrome => polynomial_evaluator_syndrome_mode_polynomial_syndrome,
clk => clk,
rst => polynomial_evaluator_syndrome_rst,
computation_finalized => polynomial_evaluator_syndrome_computation_finalized,
address_value_polynomial => polynomial_evaluator_syndrome_address_value_polynomial,
address_value_x => polynomial_evaluator_syndrome_address_value_x,
address_value_acc => polynomial_evaluator_syndrome_address_value_acc,
address_value_message => polynomial_evaluator_syndrome_address_value_message,
address_new_value_message => polynomial_evaluator_syndrome_address_new_value_message,
address_new_value_acc => polynomial_evaluator_syndrome_address_new_value_acc,
address_new_value_syndrome => polynomial_evaluator_syndrome_address_new_value_syndrome,
address_value_error => polynomial_evaluator_syndrome_address_value_error,
write_enable_new_value_acc => polynomial_evaluator_syndrome_write_enable_new_value_acc,
write_enable_new_value_syndrome => polynomial_evaluator_syndrome_write_enable_new_value_syndrome,
write_enable_new_value_message => polynomial_evaluator_syndrome_write_enable_new_value_message,
write_enable_value_error => polynomial_evaluator_syndrome_write_enable_value_error,
new_value_syndrome => polynomial_evaluator_syndrome_new_value_syndrome,
new_value_acc => polynomial_evaluator_syndrome_new_value_acc,
new_value_message => polynomial_evaluator_syndrome_new_value_message,
value_error => polynomial_evaluator_syndrome_value_error
);
solving_key_equation : solving_key_equation_4
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_F => solving_key_equation_value_F,
value_G => solving_key_equation_value_G,
value_B => solving_key_equation_value_B,
value_C => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_F => solving_key_equation_write_enable_F,
write_enable_G => solving_key_equation_write_enable_G,
write_enable_B => solving_key_equation_write_enable_B,
write_enable_C => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_F => solving_key_equation_new_value_F,
new_value_B => solving_key_equation_new_value_B,
new_value_G => solving_key_equation_new_value_G,
new_value_C => solving_key_equation_new_value_C,
address_value_F => solving_key_equation_address_value_F,
address_value_G => solving_key_equation_address_value_G,
address_value_B => solving_key_equation_address_value_B,
address_value_C => solving_key_equation_address_value_C,
address_new_value_F => solving_key_equation_address_new_value_F,
address_new_value_G => solving_key_equation_address_new_value_G,
address_new_value_B => solving_key_equation_address_new_value_B,
address_new_value_C => solving_key_equation_address_new_value_C
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
reg_syndrome_finalized : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => "1",
clk => clk,
ce => polynomial_evaluator_syndrome_computation_finalized,
rst => rst,
rst_value => "0",
q(0) => syndrome_finalized
);
polynomial_evaluator_syndrome_value_x <= value_L;
polynomial_evaluator_syndrome_value_acc <= value_sigma_evaluated;
polynomial_evaluator_syndrome_value_polynomial <= value_sigma;
polynomial_evaluator_syndrome_value_message <= value_codeword;
polynomial_evaluator_syndrome_value_h <= value_h;
polynomial_evaluator_syndrome_mode_polynomial_syndrome <= not syndrome_finalized;
polynomial_evaluator_syndrome_rst <= ( (rst) or (syndrome_finalized and (not solving_key_equation_key_equation_found)));
solving_key_equation_rst <= not syndrome_finalized;
solving_key_equation_value_F <= value_syndrome;
solving_key_equation_value_G <= value_G;
solving_key_equation_value_B <= value_B;
solving_key_equation_value_C <= value_sigma;
syndrome_generation_finalized <= syndrome_finalized or polynomial_evaluator_syndrome_computation_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= polynomial_evaluator_syndrome_computation_finalized and solving_key_equation_key_equation_found;
address_value_h <= polynomial_evaluator_syndrome_address_value_acc;
address_value_L <= polynomial_evaluator_syndrome_address_value_x;
address_value_syndrome <= solving_key_equation_address_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_value_codeword <= polynomial_evaluator_syndrome_address_value_message;
address_value_G <= solving_key_equation_address_value_G;
address_value_B <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_syndrome_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_value_acc;
new_value_syndrome <= solving_key_equation_new_value_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_new_value_syndrome;
new_value_G <= solving_key_equation_new_value_G;
new_value_B <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= polynomial_evaluator_syndrome_new_value_message;
new_value_error <= polynomial_evaluator_syndrome_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_syndrome_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_write_enable_new_value_syndrome;
write_enable_new_value_G <= solving_key_equation_write_enable_G;
write_enable_new_value_B <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= polynomial_evaluator_syndrome_write_enable_new_value_message;
write_enable_new_value_error <= polynomial_evaluator_syndrome_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_new_value_G <= solving_key_equation_address_new_value_G;
address_new_value_B <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= polynomial_evaluator_syndrome_address_new_value_message;
address_new_value_error <= polynomial_evaluator_syndrome_address_value_error;
address_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_new_value_acc;
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/codeword_generator_n_m_v3.vhd | 1 | 20141 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m_v3
-- Module Name: Codeword_Generator_n_m_v3
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word with the same size as dyadic matrix rows.
-- Also, each dyadic matrix row followed by each one, in a row-wise pattern.
--
-- This circuit process n+m bits at time, each time is 1 cycle.
-- n and m are represented as number_of_multipliers_per_acc and number_of_accs parameters.
-- This circuit is efficient and does both steps at the same time:
-- Copies the first k bits.
-- Compute the last n-k bits.
--
-- The circuits parameters
--
-- The circuits parameters
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_3 Rev 1.0
-- adder_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_n_m_v3 is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_multipliers_per_acc : integer := 32;
-- number_of_accs : integer := 32;
-- length_message : integer := 2144;
-- size_message : integer := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 5;
-- number_dyadic_matrices : integer := 804;
-- size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_multipliers_per_acc : integer := 64;
number_of_accs : integer := 64;
length_message : integer := 5632;
size_message : integer := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
size_dyadic_matrix : integer := 7;
number_dyadic_matrices : integer := 572;
size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
new_codeword_copy : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_new_codeword_copy : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end codeword_generator_n_m_v3;
architecture RTL of codeword_generator_n_m_v3 is
component controller_codeword_generator_3
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
reg_address_new_codeword_copy_ce : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC_VECTOR := "0";
signal reg_codeword_q : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_message_d : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_d : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal external_matrix_d : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal external_matrix_ce : STD_LOGIC;
signal external_matrix_q : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal zero_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal reg_address_new_codeword_copy_d : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal reg_address_new_codeword_copy_ce : STD_LOGIC;
signal reg_address_new_codeword_copy_q : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_new_codeword_copy : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal partial_product : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal accumulated_values : STD_LOGIC_VECTOR((number_of_accs*(number_of_multipliers_per_acc+1) - 1) downto 0);
signal dyadic_matrix_address : STD_LOGIC_VECTOR(((size_dyadic_matrix)*number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
begin
controller : controller_codeword_generator_3
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
zero_ctr_address_message_q => zero_ctr_address_message_q,
write_enable_new_codeword => write_enable_new_codeword,
write_enable_new_codeword_copy => write_enable_new_codeword_copy,
external_matrix_ce => external_matrix_ce,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
reg_address_new_codeword_copy_ce => reg_address_new_codeword_copy_ce,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
cod_accumulators : for I in 0 to (number_of_accs - 1) generate
cod_multipliers : for J in 0 to (number_of_multipliers_per_acc - 1) generate
reg_matrix_I_J : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_matrix_d((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J)),
clk => clk,
ce => reg_matrix_ce,
q => reg_matrix_q((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J))
);
dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))) <= ((std_logic_vector(unsigned(ctr_dyadic_column_q)+to_unsigned(I, ctr_dyadic_column_q'length))) xor (std_logic_vector(unsigned(ctr_dyadic_row_q)+to_unsigned(J, ctr_dyadic_row_q'length)-number_of_multipliers_per_acc)));
reg_matrix_d(I*number_of_multipliers_per_acc + J) <= external_matrix_q(to_integer(unsigned(dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))))));
partial_product((I*number_of_multipliers_per_acc + J)) <= reg_message_q(J) and reg_matrix_q((I*number_of_multipliers_per_acc + J));
end generate;
end generate;
accumulators : for I in 0 to (number_of_accs - 1) generate
adder_I : adder_gf_2_m
Generic Map(
gf_2_m => 1,
number_of_elements => number_of_multipliers_per_acc+1
)
Port Map(
a => accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)),
o => internal_new_codeword(I downto I)
);
reg_acc_I : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d(I downto I),
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value => reg_codeword_rst_value,
q => reg_codeword_q(I downto I)
);
accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)) <= partial_product(((I + 1)*number_of_multipliers_per_acc - 1) downto I*number_of_multipliers_per_acc) & reg_codeword_q(I downto I);
end generate;
multipliers : for I in 0 to (number_of_multipliers_per_acc - 1) generate
reg_vector_I : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_message_d(I downto I),
clk => clk,
ce => reg_message_ce,
q => reg_message_q(I downto I)
);
end generate;
external_matrix : register_nbits
Generic Map(
size => 2**size_dyadic_matrix
)
Port Map(
d => external_matrix_d,
clk => clk,
ce => external_matrix_ce,
q => external_matrix_q
);
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_accs
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_multipliers_per_acc
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_vector : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_acc : counter_rst_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
rst => ctr_address_base_codeword_rst,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
reg_address_new_acc_copy : register_nbits
Generic Map(
size => size_message
)
Port Map(
d => reg_address_new_codeword_copy_d,
clk => clk,
ce => reg_address_new_codeword_copy_ce,
q => reg_address_new_codeword_copy_q
);
reg_address_new_codeword_copy_d <= ctr_address_base_message_q & ctr_dyadic_row_q;
external_matrix_d <= matrix;
new_codeword <= internal_new_codeword;
new_codeword_copy <= reg_message_q;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
internal_address_new_codeword_copy <= reg_address_new_codeword_copy_q;
internal_address_matrix((size_number_dyadic_matrices + size_dyadic_matrix - 1) downto size_dyadic_matrix) <= ctr_dyadic_matrices_q;
internal_address_matrix((size_dyadic_matrix - 1) downto 0) <= (others => '0');
address_codeword <= internal_address_codeword;
address_new_codeword_copy <= internal_address_new_codeword_copy;
address_message <= internal_address_message;
address_matrix <= internal_address_matrix;
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_accs, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_multipliers_per_acc, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(length_message - number_of_multipliers_per_acc, size_message)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword((size_codeword - 1) downto 0) = std_logic_vector(to_unsigned(length_codeword - number_of_accs, size_codeword)) else '0';
zero_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(0, size_message)) else '0';
end RTL; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_load_rst_nbits.vhd | 1 | 2044 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_load_rst_n_bits
-- Module Name: Counter_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only increments when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_load_rst_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_load_rst_nbits;
architecture Behavioral of counter_load_rst_nbits is
signal internal_value : unsigned((size - 1) downto 0);
begin
process(clk, ce, load, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/shift_register_nbits.vhd | 1 | 1469 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Shift_Register_n_bits
-- Module Name: Shift_Register_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Shift Register of size bits with no reset signal, that only registers
-- when ce equals to 1.
--
-- The circuits parameters
--
-- size :
--
-- The size of the shift register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register_nbits is
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end shift_register_nbits;
architecture Behavioral of shift_register_nbits is
signal internal_value : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
process(clk, ce)
begin
if(clk'event and clk = '1')then
if(ce = '1') then
internal_value <= internal_value((size - 2) downto 0) & data_in;
else
null;
end if;
end if;
end process;
data_out <= internal_value(size - 1);
q <= internal_value;
end Behavioral;
| bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_decrement_rst_nbits.vhd | 1 | 1796 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_decrement_rst_n_bits
-- Module Name: Counter_decrement_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only decrements when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- decrement_value :
--
-- The amount will be decremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_decrement_rst_nbits is
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_decrement_rst_nbits;
architecture Behavioral of counter_decrement_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; | bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_double_bank_file.vhd | 1 | 4990 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Double Bank behavioral, where it can output
-- number_of_memories at once and have 2 interfaces, so it can read and write on the same cycle
-- Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Double Bank
--
-- ram_address_size :
-- Address size of the RAM Double Bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Double Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Double Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_double_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a) + index)) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b) + index)) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a)) + index);
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b)) + index);
end loop;
end if;
end process;
end file_load;
| bsd-2-clause |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_double_multiple_access.vhd | 1 | 5296 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_double_multiple_access
-- Module Name: RAM_double_multiple_access
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
-- In this double version it is possible to read and write at same cycle.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double_multiple_access is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
address_b : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_double_multiple_access;
architecture simple of ram_double_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
| bsd-2-clause |
silence4395/CPU-Design | cpu/work/dcache/_primary.vhd | 4 | 767 | library verilog;
use verilog.vl_types.all;
entity dcache is
port(
clock : in vl_logic;
address : in vl_logic_vector(31 downto 0);
data : inout vl_logic_vector(31 downto 0);
read : in vl_logic;
write : in vl_logic;
rs_ex_ok : out vl_logic;
out_address : out vl_logic_vector(31 downto 0);
out_data : inout vl_logic_vector(31 downto 0);
out_read : out vl_logic;
out_write : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
out_databus : out vl_logic_vector(63 downto 0);
write_databus : out vl_logic
);
end dcache;
| bsd-2-clause |
mithro/HDMI2USB-litex-firmware | gateware/encoder/vhdl/OutMux.vhd | 2 | 5895 | -------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090308: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity OutMux is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
out_mux_ctrl : in std_logic;
-- ByteStuffer
bs_ram_byte : in std_logic_vector(7 downto 0);
bs_ram_wren : in std_logic;
bs_ram_wraddr : in std_logic_vector(23 downto 0);
-- JFIFGen
jfif_ram_byte : in std_logic_vector(7 downto 0);
jfif_ram_wren : in std_logic;
jfif_ram_wraddr : in std_logic_vector(23 downto 0);
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity OutMux;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of OutMux is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Mux
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ram_wren <= '0';
elsif CLK'event and CLK = '1' then
if out_mux_ctrl = '0' then
ram_wren <= jfif_ram_wren;
else
ram_wren <= bs_ram_wren;
end if;
end if;
end process;
p_data : process(CLK)
begin
if CLK'event and CLK = '1' then
if out_mux_ctrl = '0' then
ram_byte <= jfif_ram_byte;
ram_wraddr <= std_logic_vector(jfif_ram_wraddr);
else
ram_byte <= bs_ram_byte;
ram_wraddr <= bs_ram_wraddr;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
mithro/HDMI2USB-litex-firmware | gateware/encoder/vhdl/AC_ROM.vhd | 2 | 31489 | -------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_ROM : process(CLK)
begin
if CLK'event and CLK = '1' then
case rom_addr is
when X"00" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"01" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"02" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"03" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"04" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"05" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"06" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"07" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"08" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"09" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000010", VLC_AC'length);
when X"0A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000011", VLC_AC'length);
when X"11" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1100", VLC_AC'length);
when X"12" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"13" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"14" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"15" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"16" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000100", VLC_AC'length);
when X"17" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000101", VLC_AC'length);
when X"18" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000110", VLC_AC'length);
when X"19" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000111", VLC_AC'length);
when X"1A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when X"21" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11100", VLC_AC'length);
when X"22" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"23" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"24" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"25" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"26" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"27" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"28" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"29" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"2A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when X"31" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"32" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"33" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"34" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"35" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"36" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"37" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"38" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"39" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"3A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when X"41" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"42" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"43" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"44" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"45" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"46" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"47" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"48" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"49" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"4A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when X"51" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"52" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"53" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"54" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"55" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"56" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"57" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"58" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"59" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"5A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when X"61" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111011", VLC_AC'length);
when X"62" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"63" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"64" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"65" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"66" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"67" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"68" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"69" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"6A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when X"71" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111010", VLC_AC'length);
when X"72" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"73" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"74" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"75" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"76" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"77" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"78" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"79" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"7A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when X"81" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"82" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000000", VLC_AC'length);
when X"83" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"84" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"85" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"86" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"87" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"88" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"89" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"8A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when X"91" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"92" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"93" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"94" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"95" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"96" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"97" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"98" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"99" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"9A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when X"A1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"A2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"A3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"A4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"A5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"A6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"A7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"A8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"A9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"AA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when X"B1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"B2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"B3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"B4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"B5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"B6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"B7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"B8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"B9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"BA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when X"C1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"C2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"C3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"C4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"C5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"C6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"C7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"C8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"C9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"CA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when X"D1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"D2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"D3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"D4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"D5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"D6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"D7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"D8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"D9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"DA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when X"E1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"E2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"E3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"E4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"E5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"E6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"E7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"E8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"E9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"EA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when X"F0" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"F1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"F2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"F3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"F4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"F5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"F6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"F7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"F8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"F9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"FA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
mithro/HDMI2USB-litex-firmware | gateware/encoder/vhdl/RLE.vhd | 5 | 14694 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/labeling.vhd | 1 | 10535 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file labeling.vhd
--! @brief Connected Component Labeling two pass
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
--! The first pass of the labeling algorithm
entity labeling is
generic(
--! Max image width
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image height
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Output if the chain resolution stalls
stall_out : out STD_LOGIC;
--! Stall the output of the labeling
stall_in : in STD_LOGIC;
--! Pixel input 0 => background, 1=> foreground
px_in : in STD_LOGIC;
--! width of the image at the input
img_width_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
--! output data are valid
data_valid_out : out STD_LOGIC;
--! input data are valid
data_valid_in : in STD_LOGIC;
--! Signal rises if the last label of this image at output
last_lbl_out : out STD_LOGIC;
--! output of labeled image
label_out : out STD_LOGIC_VECTOR(T_LABEL'RANGE);
error_out : out STD_LOGIC;
);
end entity labeling;
--! @brief arc description
--! @details more detailed description
architecture labeling_arc of labeling is
constant C_INSTANCES : natural := 3;
type T_LABEL_VECTOR is array (C_INSTANCES - 1 downto 0) of T_LABEL;
type T_EQUI_VECTOR is array (C_INSTANCES - 1 downto 0) of T_EQUI;
-- Singals in generate statement
Signal lu_next_lbl_out_s : T_LABEL_VECTOR;
Signal lu_gen_lable_in_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal lu_equi_out_s : T_EQUI_VECTOR;
Signal lu_equi_valid_in_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal lu_ready_out_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal lu_lbl_out_s : T_LABEL_VECTOR;
Signal lu_last_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_px_valid_in_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_rd_px_in_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_rd_px_out_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_rd_valid_out_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_rd_last_out_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal st_rd_slast_out_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal use_in_st_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_out_st_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_out_st_d1_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_in_lu_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_out_lu_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_out_lu_d1_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal use_out_lu_d2_s : unsigned(log2_ceil(C_INSTANCES) - 1 downto 0);
Signal rst_lbl_cnt_s : STD_LOGIC;
Signal stall_out_s : STD_LOGIC;
Signal img_px_lbl2_s : STD_LOGIC;
Signal px_valid_lbl2_in_s : STD_LOGIC;
Signal px_valid_lbl2_d1_s : STD_LOGIC;
Signal last_lbl_s : STD_LOGIC;
Signal slast_lbl_s : STD_LOGIC;
Signal last_lbled_s : STD_LOGIC_VECTOR(C_INSTANCES - 1 downto 0);
Signal last_lbl2_s : STD_LOGIC;
Signal last_lbl2_d1_s : STD_LOGIC := '0';
Signal lookup_ready_s : STD_LOGIC;
Signal data_valid_s : STD_LOGIC;
Signal cnt_lbl2_s : T_LABEL;
Signal inc_lbl2_s : STD_LOGIC;
Signal next_gen_in_s : T_LABEL;
Signal gen_lable_out_s : STD_LOGIC;
Signal equi_out_s : T_EQUI;
Signal equi_valid_out_s : STD_LOGIC;
Signal p2_lbl_s : T_LABEL;
begin
stall_out <= '0';
last_lbl_out <= last_lbl2_d1_s;
label_out <= STD_LOGIC_VECTOR(lu_lbl_out_s(to_integer(use_out_lu_d2_s)));
lookup_ready_s <= last_lbled_s(to_integer(use_out_st_s)) and lu_ready_out_s(to_integer(use_out_lu_s));
-- arbiter for two lookup tables
next_gen_in_s <= lu_next_lbl_out_s(to_integer(use_in_st_s));
img_px_lbl2_s <= st_rd_px_out_s(to_integer(use_out_lu_s));
data_valid_s <= st_rd_valid_out_s(to_integer(use_out_lu_s));
rst_lbl_cnt_s <= rst_in or last_lbl2_s;
labeling_p1 : entity work.labeling_p1 PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stall_out => stall_out_s,
stall_in => stall_in,
px_in => px_in,
px_valid_in => data_valid_in,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in),
next_lable_in => next_gen_in_s,
gen_lable_out => gen_lable_out_s,
equi_out => equi_out_s,
equi_valid_out => equi_valid_out_s,
last_lbl_out => last_lbl_s,
slast_lbl_out => slast_lbl_s,
label_out => open
);
gen_lookup : for i in C_INSTANCES - 1 downto 0 generate
lookup_table : entity work.lookup_table PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stall_out => open,
next_lable_out => lu_next_lbl_out_s(i),
gen_lable_in => lu_gen_lable_in_s(i),
equi_in => lu_equi_out_s(i),
equi_valid_in => lu_equi_valid_in_s(i),
lookup_ready_out=> lu_ready_out_s(i),
lookup_in => p2_lbl_s,
lookup_out => lu_lbl_out_s(i),
last_look_up_in => lu_last_s(i),
error_out => error_out
);
px_store : entity work.px_storage port map(
clk_in => clk_in,
rst_in => rst_in,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in),
wr_px_in => px_in,
wr_valid_in => st_px_valid_in_s(i),
rd_px_in => st_rd_px_in_s(i),
rd_px_out => st_rd_px_out_s(i),
rd_valid_out => st_rd_valid_out_s(i),
rd_last_px_out => st_rd_last_out_s(i),
rd_slast_px_out => st_rd_slast_out_s(i)
);
lu_gen_lable_in_s(i) <= gen_lable_out_s when use_in_lu_s = i else '0';
lu_equi_valid_in_s(i) <= equi_valid_out_s when use_in_lu_s = i else '0';
st_px_valid_in_s(i) <= '1' when data_valid_in = '1' and use_in_st_s = i else '0';
st_rd_px_in_s(i) <= '1' when lookup_ready_s = '1' and use_out_st_s = i else '0';
lu_last_s(i) <= '1' when use_out_lu_d1_s = i and last_lbl2_s = '1' else '0';
lu_equi_out_s(i) <= equi_out_s when use_in_lu_s = i else (others => (others => '-'));
end generate gen_lookup;
lbl_cnt_p2 : entity work.counter PORT MAP(
clk_in => clk_in,
rst_in => rst_lbl_cnt_s,
inc_in => inc_lbl2_s,
cnt_out => cnt_lbl2_s
);
px_valid_lbl2_in_s <= data_valid_s;
labeling_p2 : entity work.labeling_p1 PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stall_out => open,
stall_in => stall_in,
px_in => img_px_lbl2_s,
px_valid_in => px_valid_lbl2_in_s,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in),
next_lable_in => cnt_lbl2_s,
gen_lable_out => inc_lbl2_s,
equi_out => open,
equi_valid_out => open,
last_lbl_out => last_lbl2_s,
label_out => p2_lbl_s
);
p_delay_last : process(clk_in)
begin
if rising_edge (clk_in) then
if rst_in = '1' then
last_lbl2_d1_s <= '0';
px_valid_lbl2_d1_s <= '0';
data_valid_out <= '0';
else
last_lbl2_d1_s <= last_lbl2_s;
px_valid_lbl2_d1_s <= px_valid_lbl2_in_s;
data_valid_out <= px_valid_lbl2_d1_s;
end if;
end if;
end process p_delay_last;
p_lu_switch : process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
use_in_st_s <= (others => '0');
use_out_lu_s <= (others => '0');
use_out_lu_d1_s <= (others => '0');
use_out_lu_d2_s <= (others => '0');
use_out_st_s <= (others => '0');
last_lbled_s <= (others => '0');
else
use_out_lu_d1_s <= use_out_lu_s;
use_out_lu_d2_s <= use_out_lu_d1_s;
use_in_lu_s <= use_in_st_s;
if slast_lbl_s = '1' then
if use_in_st_s = C_INSTANCES - 1 then
use_in_st_s <= (others => '0');
last_lbled_s(0) <= '0';
else
use_in_st_s <= use_in_st_s + 1;
last_lbled_s(to_integer(use_in_st_s + 1)) <= '0';
end if;
last_lbled_s(to_integer(use_in_st_s)) <= '1';
end if;
if st_rd_slast_out_s(to_integer(use_out_st_s)) = '1' then
if use_out_st_s = C_INSTANCES - 1 then
use_out_st_s <= (others => '0');
else
use_out_st_s <= use_out_st_s + 1;
end if;
end if;
use_out_st_d1_s <= use_out_st_s;
use_out_lu_s <= use_out_st_s;
end if; -- rst
end if; -- clk
end process p_lu_switch;
end labeling_arc;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/comparator.vhd | 1 | 8951 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file comparator.vhd
--! @brief Compares the result of the DUT and REV Implementaion
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-08-29
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
entity comparator is
generic(
--! Number of max boxes
G_MAX_BOXES : NATURAL := div_ceil(C_MAX_IMAGE_WIDTH,2)*div_ceil(C_MAX_IMAGE_WIDTH,2)
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Restart comparation
restart_in : in STD_LOGIC;
--! last box input
last_box_in : in STD_LOGIC;
--! clock for DUT in
clk1_in : in STD_LOGIC;
--! Boxes input of the DUT
box1_in : in T_BOX;
--! DUT Box valid
box1_valid_in : in STD_LOGIC;
--! Boxes input of the REV
box2_in : in T_BOX;
--! REV Box valid
box2_valid_in : in STD_LOGIC;
--! error 0 => no error
--! error 1 => DUT less BOXes as expected
--! error 2 => DUT more BOXes as expected
--! error 3 => DUT unexpected BOXes
error_code_out : out unsigned(3 downto 0);
--! rises if check is done the error_code_out is also valid
check_done_out : out STD_LOGIC
);
end entity comparator;
architecture comparator_arc of comparator is
TYPE T_STATE is (SAMPLING, COMPARE, RESET);
TYPE T_BOX2_RAM is array (0 to G_MAX_BOXES - 1) of T_BOX;
SUBTYPE T_BOX2_BITS is STD_LOGIC_VECTOR(G_MAX_BOXES - 1 downto 0);
constant C_NO_ERROR : unsigned(3 downto 0) := "0000";
constant C_DUT_LESS : unsigned(3 downto 0) := "0001";
constant C_DUT_MORE : unsigned(3 downto 0) := "0010";
constant C_DUT_WRONG : unsigned(3 downto 0) := "0011";
signal state_s : T_STATE;
signal state_d_s : T_STATE;
signal box2_ram_s : T_BOX2_RAM;
signal box2_valid_s : unsigned(log2_ceil(T_BOX2_RAM'length) - 1 downto 0);
signal box2_found_s : T_BOX2_BITS;
signal wr_cnt_s : unsigned(log2_ceil(T_BOX2_RAM'length) - 1 downto 0);
signal rd_cnt_s : unsigned(log2_ceil(T_BOX2_RAM'length) - 1 downto 0);
signal rd_cnt_d_s : unsigned(log2_ceil(T_BOX2_RAM'length) - 1 downto 0);
signal box1_s : T_BOX;
signal box1_v_s : STD_LOGIC;
signal box1_v_d_s : STD_LOGIC;
signal box1_next_s : STD_LOGIC := '0';
signal box1_empty_s : STD_LOGIC;
signal box1_fill_s : unsigned(0 to log2_ceil(G_MAX_BOXES));
signal match_done_s : STD_LOGIC;
signal restart_d_s : STD_LOGIC;
signal rst_fifo_s : STD_LOGIC;
begin
rst_fifo_s <= '1' when state_s = RESET or rst_in = '1' else '0';
--! p_state contorls the state machine
--! RESET after a external reset
--! SAMPLING reads values from box_in if valid
--! COMPARE after last_box_in gets high until every thing is compared
p_state : process(clk_in, rst_in) is
begin
if rst_in = '1' then
state_s <= SAMPLING;
elsif rising_edge(clk_in) then
if restart_in = '1' then
state_s <= SAMPLING;
else
state_d_s <= state_s;
case state_s is
when SAMPLING =>
if last_box_in = '1' then
if box1_fill_s /= wr_cnt_s then
-- box1 and box2 different number of boxes
state_s <= RESET;
else
state_s <= COMPARE;
end if;
end if;
when COMPARE =>
if box1_empty_s = '1' and match_done_s = '1' then
state_s <= RESET;
end if;
when RESET =>
if last_box_in = '0' then
state_s <= SAMPLING;
end if;
end case;
end if; --rst
end if; --clk
end process p_state;
p_write : process(clk_in, rst_in) is
variable box2_valid_v : unsigned(T_BOX2_RAM'length downto 0);
begin
if rst_in = '1' then
wr_cnt_s <= (others => '0');
rd_cnt_s <= (others => '0');
box2_valid_s <= (others => '0');
box2_found_s <= (others => '0');
box1_v_s <= '0';
box1_v_d_s <= '0';
match_done_s <= '0';
restart_d_s <= '0';
box1_next_s <= '0';
check_done_out <= '0';
elsif rising_edge(clk_in) then
box1_next_s <= '0';
check_done_out <= '0';
restart_d_s <= '0';
if restart_in = '1' then
restart_d_s <= '1';
end if;
if state_s = RESET then
wr_cnt_s <= (others => '0');
rd_cnt_s <= (others => '0');
box2_valid_s <= (others => '0');
box2_found_s <= (others => '0');
box1_v_s <= '0';
box1_v_d_s <= '0';
match_done_s <= '0';
-- box2_found_s is unary coded -> convert box2_valid_s to unary
box2_valid_v := (others => '0');
box2_valid_v(to_integer(box2_valid_s)) := '1';
box2_valid_v := box2_valid_v-1;
if restart_d_s = '0' or restart_in = '1' then
check_done_out <= '1';
if state_d_s = SAMPLING then
-- different box count
if wr_cnt_s < box1_fill_s + 1 then
error_code_out <= C_DUT_MORE;
else
error_code_out <= C_DUT_LESS;
end if;
elsif box2_valid_v /= unsigned(box2_found_s) then
error_code_out <= C_DUT_WRONG;
end if;
end if;
elsif state_s = SAMPLING then
if box2_valid_in = '1' then
box2_ram_s(to_integer(wr_cnt_s)) <= box2_in;
box2_valid_s <= box2_valid_s + 1;
wr_cnt_s <= wr_cnt_s + 1;
end if;
elsif state_s = COMPARE then
error_code_out <= C_NO_ERROR;
box1_v_d_s <= box1_v_s;
-- is the fifo output valid?
if box1_v_s = '0' then
-- read first word from buffer
-- can be removed if the fifo has first word fall through
--! TODO generate box1_next_s combinatorial to save one clock
-- is there a additional result in the fifo?
if box1_empty_s = '0' then
box1_next_s <= '1';
box1_v_s <= '1';
match_done_s <= '0';
else
match_done_s <= '1';
end if;
elsif box1_v_d_s = '1' then
if box2_ram_s(to_integer(rd_cnt_s)) = box1_s then
box2_found_s(to_integer(rd_cnt_s)) <= '1';
rd_cnt_s <= (others => '0');
rd_cnt_d_s <= (others => '1');
-- the right value was found -> the output of fifo will be
-- invalidated
box1_v_s <= '0';
elsif rd_cnt_s = rd_cnt_d_s then
-- the read counter has not changed
-- this only can happen if ther is no
-- match possible of box2 and box1
box1_v_s <= '0';
else
-- store this read counter
rd_cnt_d_s <= rd_cnt_s;
-- select next unfound box
for i in 0 to box2_found_s'high loop
if box2_found_s(i) = '0' and i > rd_cnt_s then
rd_cnt_s <= to_unsigned(i, rd_cnt_s'length);
exit;
end if;
end loop;
end if;
end if;
end if; --state
end if; --clk
end process p_write;
--! can be replaced by asynchrone fifo
--! if one of the CCL architectures needs different clock domain
box1_fifo : entity work.fifo
generic map(
G_SIZE => G_MAX_BOXES,
G_WORD_WIDTH => T_BOX'LENGTH,
G_ALMOST_FULL => G_MAX_BOXES - 1
)
port map(
rst_in => rst_fifo_s,
clk_in => clk_in,
wr_d_in => box1_in,
wr_valid_in => box1_valid_in,
almost_full_out => open,
full_out => open,
rd_d_out => box1_s,
rd_next_in => box1_next_s,
almost_empty_out => open,
empty_out => box1_empty_s,
fill_lvl_out => box1_fill_s
);
end architecture;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/labeling_box.vhd | 1 | 9506 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file labeling_box.vhd
--! @brief Connected Component Labeling two pass and computation of bound boxes
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
--! The two pass algorithem implemented in labeling.vhd
--! will be run and the output of labels used to compute
--! the bound boxes with the boundbox.vhd.
--! The boundbox has a internal heap to store boundboxes
--! if the memory is to small the the error signal will
--! rise and the output of the boxes is incompleat
entity labeling_box is
generic(
--! Max image width means 2^...
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image width means 2^...
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Output if the labeling stalls
stall_out : out STD_LOGIC;
--! Input to stall the output of the labeling
stall_in : in STD_LOGIC;
--! input data are valid
data_valid_in : in STD_LOGIC;
--! Pixel input 0 => background, 1=> foreground
px_in : in STD_LOGIC;
--! width of the image at the input
img_width_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
--! High if the boundbox output valid
box_valid_out : out STD_LOGIC;
--! output of bound box upper x
box_start_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
--! output of bound box upper y
box_start_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0);
--! output of bound box lower x
box_end_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
--! output of bound box lower y
box_end_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0);
--! high if all boxes are computed
box_done_out : out STD_LOGIC;
--! Error Type out
error_type_out : out STD_LOGIC_VECTOR(C_ERR_REF_SIZE - 1 downto 0)
);
end entity labeling_box;
--! @brief arc description
--! @details more detailed description
architecture labeling_box_arc of labeling_box is
--! How many boxing instances should be provided
constant C_BOX_INSTANCES : NATURAL := 2;
type T_BOXES is array (C_BOX_INSTANCES - 1 downto 0) of T_BOX;
--! State machine
type T_STATE is (IDLE, LABELING, BOXES, FIFO_READ);
type T_STATES is array(C_BOX_INSTANCES - 1 downto 0) of T_STATE;
signal pipe_state : T_STATES;
signal stall_lbl_s : STD_LOGIC;
signal data_valid_lbl_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal valid_lbl_out_s : STD_LOGIC;
signal last_lbl_s : STD_LOGIC;
signal label_s : STD_LOGIC_VECTOR(T_LABEL'RANGE);
signal box_rst_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal box_done_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal ff_box_out_s : T_BOXES;
signal ff_box_in_s : T_BOXES;
signal ff_wr_valid_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal ff_rd_next_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal ff_empty_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal err_lbl_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0);
signal box_out_s : T_BOX;
--! instance to use for first stage input
signal use_st_1_in_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0);
signal use_st_1_out_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0);
--! which boundbox should be used for input next
signal next_input_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0);
function inst_inc (
inst : in unsigned)
return unsigned
is
variable ret_val : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0);
begin
if inst = C_BOX_INSTANCES - 1 then
ret_val := (others => '0');
else
ret_val := inst + 1;
end if;
return ret_val;
end function inst_inc;
begin
box_start_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_START));
box_start_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_START));
box_end_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_END));
box_end_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_END));
box_out_s <= ff_box_out_s(to_integer(use_st_1_out_s));
error_type_out(0) <= '0';
p_valid_out : process(clk_in) is
begin
if rising_edge(clk_in) then
if pipe_state(to_integer(use_st_1_out_s)) = FIFO_READ and
ff_empty_s(to_integer(use_st_1_out_s)) = '0'then
box_valid_out <= '1';
else
box_valid_out <= '0';
end if;
end if;
end process;
p_pipe_state : process(clk_in) is
variable next_input_sel_v : boolean;
begin
if rising_edge(clk_in) then
if rst_in = '1' then
pipe_state <= (others => IDLE);
pipe_state(0) <= LABELING;
next_input_s <= to_unsigned(1, next_input_s'length);
use_st_1_out_s <= (others => '0');
use_st_1_in_s <= (others => '0');
box_rst_s <= (others => '1');
box_done_out <= '0';
else
next_input_sel_v := false;
box_done_out <= '0';
for i in C_BOX_INSTANCES - 1 downto 0 loop
box_rst_s(i) <= '0';
case pipe_state(i) is
when IDLE =>
if next_input_s = i and last_lbl_s = '1' then
pipe_state(i) <= LABELING;
next_input_s <= inst_inc(next_input_s);
end if;
when LABELING =>
if last_lbl_s = '1' then
pipe_state(i) <= BOXES;
use_st_1_in_s <= next_input_s;
end if;
when BOXES =>
if box_done_s(i) = '1' then
pipe_state(i) <= FIFO_READ;
box_rst_s(i) <= '1';
end if;
when FIFO_READ =>
if ff_empty_s(i) = '1' then
pipe_state(i) <= IDLE;
use_st_1_out_s <= inst_inc(use_st_1_out_s);
box_done_out <= '1';
end if;
end case;
end loop;
end if; -- rst
end if; --clk
end process p_pipe_state;
my_labeling : entity work.labeling PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stall_out => stall_lbl_s,
stall_in => stall_in,
px_in => px_in,
img_width_in => img_width_in,
img_height_in => img_height_in,
data_valid_out => valid_lbl_out_s,
data_valid_in => data_valid_in,
last_lbl_out => last_lbl_s,
label_out => label_s,
error_out => error_lbl_s
);
gen_boxes : for i in C_BOX_INSTANCES - 1 downto 0 generate
boundbox : entity work.boundbox PORT MAP(
clk_in => clk_in,
rst_in => box_rst_s(i),
stall_in => stall_in,
lbl_valid_in => data_valid_lbl_s(i),
label_in => UNSIGNED(label_s),
box_valid_out => ff_wr_valid_s(i),
box_out => ff_box_in_s(i),
box_done_out => box_done_s(i),
error_out => open,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in)
);
box_fifo : entity work.fifo
GENERIC MAP(
G_SIZE => G_MAX_IMG_WIDTH/2*G_MAX_IMG_HEIGHT/2,
G_WORD_WIDTH => T_BOX'LENGTH,
G_ALMOST_EMPTY => 1,
G_ALMOST_FULL => 64 - 1
)
PORT MAP(
rst_in => rst_in,
clk_in => clk_in,
wr_d_in => ff_box_in_s(i),
wr_valid_in => ff_wr_valid_s(i),
almost_full_out => open,
full_out => open,
rd_d_out => ff_box_out_s(i),
rd_next_in => ff_rd_next_s(i),
almost_empty_out => open,
empty_out => ff_empty_s(i)
);
data_valid_lbl_s(i) <= valid_lbl_out_s when i = use_st_1_in_s else '0';
ff_rd_next_s(i) <= not ff_empty_s(i) when
pipe_state(to_integer(use_st_1_out_s)) = FIFO_READ
else '0';
end generate gen_boxes;
end labeling_box_arc;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/types.vhd | 1 | 5460 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file types.vhd
--! @brief Definition of global types and settings, used in more than one architecture
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library pccl_lib;
use pccl_lib.common.all;
use work.utils.all;
--! Definition of global types and settings
package types is
constant C_CAM_IF : boolean := true;
constant C_VERSION : natural := 291;
-- how many comparators?
constant C_COMP_INST : natural := 60;
-- size of error_type output of REF
CONSTANT C_ERR_REF_SIZE : natural := 1;
CONSTANT C_ERR_DUT_SIZE : natural := sp_error_type_width;
CONSTANT C_ERR_CMP_SIZE : natural := 4;
-- '1' means errors are droped if the error fifo is full
-- '0' means stall the verification process if the fifo is full
CONSTANT C_ALLOW_ERR_DRP : std_logic := '1';
-- get information from ccl_dut common_pkg.vhd
constant C_IMAGE_WIDTH : natural := image_width;
constant C_IMAGE_HEIGHT : natural := image_height;
constant C_MAX_IMAGE_WIDTH : natural := C_IMAGE_WIDTH;
constant C_MAX_IMAGE_HEIGHT : natural := C_IMAGE_HEIGHT;
-- size of error storage
CONSTANT C_ERR_BUF_SIZE : natural := 8*1024;
-- size of the error type
CONSTANT C_ERR_TYP_SIZE : natural := C_ERR_CMP_SIZE + C_ERR_REF_SIZE + C_ERR_DUT_SIZE;
CONSTANT C_ERR_TYP_SIZE_BYTE : natural := div_ceil(C_ERR_TYP_SIZE, 8);
-- defines how many clocks to wait for box outputs
-- after the hole image is written to the dut input
constant C_DUT_EXTRA_CLKS : natural := 2 * C_IMAGE_WIDTH;
--! max length of data part of send and receive data
--constant C_MAX_USE_DATA : natural := 1024;
constant C_MAX_SEND_DATA : natural := 1024;
constant C_BACKGROUND : std_logic := '0'; --! defines if the background is '0' or '1'
-- build in a counter for the distribution of the number of different labels
CONSTANT C_INCLUDE_CNT : boolean := false;
--! constants for counting number of different used labels over all images
-- change this 0 if you want to include counter
constant C_CNT_SIZE : natural := 0;--C_MAX_IMAGE_WIDTH*C_MAX_IMAGE_HEIGHT;
constant C_MAX_BOXES : natural := div_ceil(C_MAX_IMAGE_WIDTH,2)*div_ceil(C_MAX_IMAGE_WIDTH,2);
constant C_CNT_SIZE_BYTE : natural := div_ceil(C_CNT_SIZE*C_MAX_BOXES, 8);
--! the max number of lables are log2(IMAGE_WIDTH*IMAGE_HEIGHT/2/2)
-- worst case: one lines with the toggeling input one 0 the next 1...
-- you need line_width/2 different labels
subtype T_LABEL is
unsigned(log2_ceil(div_ceil(C_MAX_IMAGE_WIDTH,2)*div_ceil(C_MAX_IMAGE_HEIGHT,2)+1)-1 downto 0); --! type to store lables
type T_EQUI is array (0 to 1) of T_LABEL;
subtype T_BOX is unsigned(2*log2_ceil(C_MAX_IMAGE_HEIGHT) + 2*log2_ceil(C_MAX_IMAGE_WIDTH) - 1 downto 0);
subtype T_X_START is natural range 2*log2_ceil(C_MAX_IMAGE_WIDTH) + 2*log2_ceil(C_MAX_IMAGE_HEIGHT) - 1 downto log2_ceil(C_MAX_IMAGE_WIDTH) + 2*log2_ceil(C_MAX_IMAGE_HEIGHT);
subtype T_Y_START is natural range log2_ceil(C_MAX_IMAGE_WIDTH) + 2*log2_ceil(C_MAX_IMAGE_HEIGHT) - 1 downto log2_ceil(C_MAX_IMAGE_WIDTH) + log2_ceil(C_MAX_IMAGE_HEIGHT);
subtype T_X_END is natural range log2_ceil(C_MAX_IMAGE_WIDTH) + log2_ceil(C_MAX_IMAGE_HEIGHT) - 1 downto log2_ceil(C_MAX_IMAGE_HEIGHT);
subtype T_Y_END is natural range log2_ceil(C_MAX_IMAGE_HEIGHT) - 1 downto 0;
--! Defines the unlabeld value
constant C_UNLABELD : T_LABEL := (others => '0');
SUBTYPE T_ERROR is UNSIGNED(C_ERR_TYP_SIZE-1 downto 0);
type T_CAM_POS is record
row : unsigned(log2_ceil(C_MAX_IMAGE_HEIGHT+1)-1 downto 0);
col : unsigned(log2_ceil(C_MAX_IMAGE_WIDTH+1) -1 downto 0);
val : std_logic;
end record;
type T_CAM_ERR is array (0 to 9) of T_CAM_POS;
end package types;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/communication/udp_ip_stack/trunk/rtl/vhdl/arp_types.vhd | 1 | 2060 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
-- Revision 0.02 - Added type definitions (store and network) for arpv2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package arp_types is
-- arp lookup types
type arp_req_req_type is
record
lookup_req : std_logic; -- set high when wanting mac adr for the requested IP
ip : std_logic_vector (31 downto 0);
end record;
type arp_req_rslt_type is
record
got_mac : std_logic; -- indicates that we got the mac
mac : std_logic_vector (47 downto 0);
got_err : std_logic; -- indicates that we got an error (prob a timeout)
end record;
type arp_entry_t is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
end record;
type arp_control_type is
record
clear_cache : std_logic;
end record;
-- arp store types
type arp_store_rslt_t is (IDLE,BUSY,SEARCHING,FOUND,NOT_FOUND);
type arp_store_rdrequest_t is
record
req : std_logic; -- request to lookup
ip : std_logic_vector(31 downto 0); -- contains ip to lookup
end record;
type arp_store_wrrequest_t is
record
req : std_logic; -- request to store
entry : arp_entry_t; -- ip,mac to store
end record;
type arp_store_result_t is
record
status : arp_store_rslt_t; -- status of the request
entry : arp_entry_t; -- contains ip,mac if found
end record;
-- arp network types
type arp_nwk_rslt_t is (IDLE,REQUESTING,RECEIVED,ERROR);
type arp_nwk_request_t is
record
req : std_logic; -- request to resolve IP addr
ip : std_logic_vector(31 downto 0); -- IP to request
end record;
type arp_nwk_result_t is
record
status : arp_nwk_rslt_t; -- status of request
entry : arp_entry_t; -- the result
end record;
end arp_types;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/counter.vhd | 1 | 3192 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file counter.vhd
--! @brief A Simple counter it increments its value by G_INC_VALUE
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-07-08
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
--! @brief Counter increments the cnt_out when clk_in rises and inc_in is high
entity counter is
generic(
--! Defines the Size of the Counter
G_CNT_LENGTH : NATURAL := T_LABEL'LENGTH;
--! Defines the value to increment
G_INC_VALUE : NATURAL := 1;
--! Defines a offset between the internal and the output value
G_OFFSET : UNSIGNED(63 downto 0) := x"0000000000000001"
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! If high the counter will be incremented
inc_in : in STD_LOGIC;
--! Outputs the currenct counter value
cnt_out : out UNSIGNED (G_CNT_LENGTH - 1 downto 0)
);
end entity counter;
--! @brief Simple Counter
--! @details Counts
architecture counter_arc of counter is
-- Counter value
signal cnt_s : UNSIGNED(G_CNT_LENGTH - 1 downto 0);
begin
cnt_out <= resize(cnt_s + G_OFFSET, G_CNT_LENGTH) when inc_in='0' else resize(cnt_s + G_OFFSET + G_INC_VALUE, G_CNT_LENGTH);
p_cnt_inc : process(rst_in, clk_in, inc_in)
begin
if rst_in = '1' then
cnt_s <= (others => '0');
elsif rst_in = '0' and rising_edge(clk_in) and inc_in = '1' then
cnt_s <= cnt_s + G_INC_VALUE;
end if;
end process p_cnt_inc;
end counter_arc;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/tb_labeling.vhd | 1 | 5622 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file tb_labeling.vhd
--! @brief testbench for the whole connected component labeling
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
--! Use numeric std
use IEEE.numeric_std.all;
use work.pbm_package.all;
use work.types.all;
use work.utils.all;
--! Reads in a PPM file an use it as input for connected component labeling
entity tb_labeling is
end tb_labeling;
architecture Behavioral of tb_labeling is
constant infile : String := "../../img/sim_in.pbm";
constant half_period : Time := 20 ns;
constant C_IDLE_MIN : Natural := 50;
Signal clk_in_s : STD_LOGIC := '0';
Signal rst_in_s : STD_LOGIC := '1';
Signal px_in_s : STD_LOGIC;
Signal stall_out_s : STD_LOGIC;
Signal img_width_in_s : STD_LOGIC_VECTOR(log2_ceil(C_MAX_IMAGE_WIDTH) downto 0);
Signal img_height_in_s : STD_LOGIC_VECTOR(log2_ceil(C_MAX_IMAGE_HEIGHT) downto 0);
Signal data_valid_out_s : STD_LOGIC;
Signal last_lbl_out_s : STD_LOGIC;
Signal last_lbl_out_d_s : STD_LOGIC := '0';
Signal label_out_s : STD_LOGIC_VECTOR(T_LABEL'HIGH downto T_LABEL'LOW);
Signal data_valid_in_s : STD_LOGIC;
-- used to turn the clock off after simulation
Signal clk_en_s : STD_LOGIC := '1';
begin
dut_labeling : entity work.labeling PORT MAP(
clk_in => clk_in_s,
rst_in => rst_in_s,
stall_out => stall_out_s,
stall_in => '0',
px_in => px_in_s,
img_width_in => img_width_in_s,
img_height_in => img_height_in_s,
data_valid_out => data_valid_out_s,
data_valid_in => data_valid_in_s,
last_lbl_out => last_lbl_out_s,
label_out => label_out_s
);
rst_in_s <= '1' after 50 ns, '0' after 100 ns; -- generate initial reset
clk_p : process
begin
while clk_en_s = '1' loop
clk_in_s <= not clk_in_s;
wait for half_period;
end loop;
wait;
end process clk_p;
last_lbl_out_d_s <= last_lbl_out_s after half_period * 2;
test_p : process
variable img_width : natural;
variable img_height : natural;
variable image : image_type;
variable first : boolean := true;
variable x_v : natural;
variable y_v : natural;
variable lbl_cnt : natural := 0;
variable stop_cnt : natural := C_IDLE_MIN;
begin
read_pbm(infile, image, img_width, img_height);
data_valid_in_s <= '0';
assert img_width <= C_MAX_IMAGE_WIDTH report "Image bigger than max width" severity error;
assert img_height <= C_MAX_IMAGE_HEIGHT report "Image bigger than max height" severity error;
--px_in_s <= '0';
--img_width_in_s <= (others => '0');
--img_height_in_s <= (others => '0');
--wait until rst_in_s = '0';
wait for 150 ns;
img_width_in_s <= std_logic_vector(to_unsigned(img_width, img_width_in_s'length));
img_height_in_s <= std_logic_vector(to_unsigned(img_height, img_height_in_s'length));
wait until clk_in_s = '1';
wait for half_period;
y_v := 1;
x_v := 1;
while last_lbl_out_d_s /= '1' loop
data_valid_in_s <= '0';
if y_v <= img_height then
px_in_s <= image(y_v)(x_v);
data_valid_in_s <= '1';
end if;
if x_v < img_width then
x_v := x_v + 1;
else
x_v := 1;
y_v := y_v + 1;
end if;
wait for half_period*2;
if data_valid_out_s = '1' then
report "Label: " & INTEGER'IMAGE(TO_INTEGER(unsigned(label_out_s)));
--report "Lbl_cnt: " & INTEGER'IMAGE(lbl_cnt + 1);
lbl_cnt := lbl_cnt + 1;
end if;
end loop;
while stop_cnt > 0 loop
wait for half_period*2;
stop_cnt := stop_cnt - 1;
if data_valid_out_s = '1' then
report "Label: " & INTEGER'IMAGE(TO_INTEGER(unsigned(label_out_s)));
--report "Lbl_cnt: " & INTEGER'IMAGE(lbl_cnt + 1);
lbl_cnt := lbl_cnt + 1;
stop_cnt := C_IDLE_MIN;
end if;
end loop;
wait for half_period*2;
clk_en_s <= '0';
wait;
end process test_p;
end architecture Behavioral;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/utils.vhd | 1 | 3266 | --------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file utils.vhd
--! @brief often used procedures and functions
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-08-12
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
package utils is
--! calculates the log2 and ceil the result
--! @param val value to calculate log2
--! @return log2 of val and round to the next integer bigger or equals the exact result
function log2_ceil (val : natural) return natural;
--! divides val1/val2
--! @param val1 dividend
--! @param val2 divider
--! @return the result of division rount to next integer bigger or equals the exact result
function div_ceil (val1 : natural; val2 : natural) return natural;
end package utils;
package body utils is
function log2_ceil (val : natural) return natural is
begin
if val = 0 then
assert false report "Value log2(0) is -infinity" severity failure; return 0; -- some tools complain if no return value is present
elsif val <= 2 then
return 1;
else
if val mod 2 = 0 then
return 1 + log2_ceil(val/2);
else
return 1 + log2_ceil(val/2+1);
end if;
end if;
end function log2_ceil;
function div_ceil (val1 : natural; val2 : natural) return natural is
begin
return natural(ceil(real(val1)/real(val2)));
end function div_ceil;
--function log2_ceil (val : natural) return natural is
-- variable tmp : real := real(val);
-- variable res : natural = 0;
--begin
-- while tmp >= 1.0 loop
-- tmp := tmp / 2;
-- res := res + 1;
-- end loop;
-- if 2**res < val then
-- return res + 1;
-- else
-- return res;
-- end if;
--end function log2_ceil;
end package body utils;
| bsd-2-clause |
nihospr01/OpenSpeechPlatform-UCSD | Firmware/FPGA/src/tl_test.vhd | 1 | 650 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OSP_DJB_Basic_Test is
port(
db_clk: in std_logic;
db_reset: in std_logic;
db_switches: in unsigned(3 downto 0);
db_leds: out unsigned(7 downto 0)
);
end entity;
architecture a of OSP_DJB_Basic_Test is
signal counter: unsigned(22 downto 0);
begin
db_leds(7 downto 4) <= db_switches(3 downto 0);
process(db_clk, db_reset) is begin
if db_reset = '0' then
counter <= (others => '0');
elsif rising_edge(db_clk) then
counter <= counter + 1;
end if;
db_leds(3 downto 0) <= counter(22 downto 19);
end process;
end architecture; | bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/communication/udp_ip_stack/trunk/bench/vhdl/IP_av2_complete_nomac_tb .vhd | 1 | 17279 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:32 06/04/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
ENTITY IP_av2_complete_nomac_tb IS
END IP_av2_complete_nomac_tb;
--configuration main of IP_av2_complete_nomac_tb is
-- for behavior
-- for uut : IP_complete_nomac
-- use configuration work.IP_complete_nomac.multi_slot_arp;
-- end for;
-- end for;
--end main;
ARCHITECTURE behavior OF IP_av2_complete_nomac_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_tready : std_logic := '0';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
signal control : ip_control_type;
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal ip_rx_start : std_logic;
signal ip_rx : ipv4_rx_type;
signal arp_pkt_count : std_logic_vector(7 downto 0);
signal mac_tx_tdata : std_logic_vector(7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tfirst : std_logic;
signal mac_tx_tlast : std_logic;
signal mac_rx_tready : std_logic;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IP_complete_nomac PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => clk,
tx_clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control,
arp_pkt_count => arp_pkt_count,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 80 ns;
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
control.arp_controls.clear_cache <= '0';
ip_tx_start <= '0';
mac_tx_tready <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
mac_tx_tready <= '1';
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"00"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- user data
mac_rx_tdata <= x"24"; wait for clk_period;
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '1' report "T1: ip_rx_start not set";
assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
mac_rx_tdata <= x"25"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
------------
-- TEST 2 -- respond with IP TX
------------
report "T2: respond with IP TX";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
-- need to wait for ARP tx to complete
wait for clk_period*50;
assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
-- now create the ARP response (rx)
-- Send the reply
-- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"02"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"34"; wait for clk_period;
mac_rx_tdata <= x"78"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
ip_tx.data.data_out <= x"5a"; wait for clk_period;
ip_tx.data.data_out <= x"5b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T2: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be SENT";
wait for clk_period*10;
------------
-- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached
------------
report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"81"; wait for clk_period;
ip_tx.data.data_out <= x"83"; wait for clk_period;
ip_tx.data.data_out <= x"85"; wait for clk_period;
ip_tx.data.data_out <= x"87"; wait for clk_period;
ip_tx.data.data_out <= x"89"; wait for clk_period;
ip_tx.data.data_out <= x"8b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T3: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be SENT";
wait for clk_period*2;
report "-- end of tests --";
wait;
end process;
END;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/labeling_p1.vhd | 1 | 7718 | -------------------------------------------------------
--! @file labeling_p1.vhd
--! @brief Common Component Labeling first pass with lookup generation
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
--! The first pass of the labeling algorithm
entity labeling_p1 is
generic(
--! Max image width
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image height
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Output if the chain resolution stalls
stall_out : out STD_LOGIC;
--! Input if the lookup_table stalls
stall_in : in STD_LOGIC;
--! Pixel input 0 => background, 1=> foreground
px_in : in STD_LOGIC;
--! Pixel px_in is valid
px_valid_in : in STD_LOGIC;
--! width of the image at the input
img_width_in : in UNSIGNED(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in UNSIGNED(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
--! if last label of image this signal rises
last_lbl_out : out STD_LOGIC;
--! if second last label of image this signal rises
slast_lbl_out : out STD_LOGIC;
--! Value of next new label
next_lable_in : in T_LABEL;
--! tell the lookup table to generate a new label
gen_lable_out : out STD_LOGIC;
--! send the lookup table a new equivalent pair
equi_out : out T_EQUI;
--! Signal to set equivalent pair as valid
equi_valid_out : out STD_LOGIC;
--! output of labeled image
label_out : out T_LABEL
);
end entity labeling_p1;
--! @brief arc description
--! @details more detailed description
architecture labeling_p1_arc of labeling_p1 is
-- Stores the last row of the input image
type T_ROW_BUFFER is array (C_MAX_IMAGE_WIDTH-3 downto 0) of T_LABEL;
signal row_buffer_s : T_ROW_BUFFER;
-- Labels of the neighborhood
signal d, c, b, a : T_LABEL;
signal label_out_s : T_LABEL;
-- col_cnt needs to be one bigger since the counter is one ahead
signal col_cnt : unsigned(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
signal row_cnt : unsigned(log2_ceil(G_MAX_IMG_HEIGHT)-1 downto 0);
signal last_lbl_s : std_logic;
attribute ram_style : string;
attribute ram_style of row_buffer_s : signal is "auto"; --"{auto|block|distributed|pipe_distributed|block_power1|block_power2}";
begin
label_out <= label_out_s;
last_lbl_s <= '1' when resize(col_cnt, col_cnt'length) + 1 = img_width_in and resize(row_cnt, row_cnt'length + 1) + 1 = img_height_in else '0';
slast_lbl_out <= last_lbl_s;
p_col_cnt : process(rst_in, clk_in, stall_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
col_cnt <= (others => '0');
row_cnt <= (others => '0');
else
if stall_in = '0' then
if px_valid_in = '1' then
if resize (col_cnt, col_cnt'length) + 1 = img_width_in then
col_cnt <= (others => '0');
if last_lbl_s = '1' then
-- autoreset
row_cnt <= (others => '0');
else
row_cnt <= row_cnt + 1;
end if;
else
col_cnt <= col_cnt + 1;
end if;
end if;
end if;
end if;
end if;
end process p_col_cnt;
p_buffer: process(rst_in, clk_in) is
begin
if rst_in = '1' then
--row_buffer_s <= (others => C_UNLABELD);
null;
elsif rising_edge(clk_in) and rst_in = '0' then
if stall_in = '0' and px_valid_in = '1' then
row_buffer_s <= row_buffer_s(row_buffer_s'high-1 downto 0) & label_out_s;
end if;
end if; -- clk
end process p_buffer;
p_lable_selection : process(rst_in, clk_in, px_in)
begin
if rst_in = '1' then
--! reset signals
d <= C_UNLABELD;
gen_lable_out <= '0';
equi_valid_out <= '0';
label_out_s <= C_UNLABELD;
last_lbl_out <= '0';
stall_out <= '1';
elsif rising_edge(clk_in) and rst_in = '0' then
--! default settings
gen_lable_out <= '0';
equi_valid_out <= '0';
last_lbl_out <= last_lbl_s;
if stall_in = '0' and px_valid_in = '1' then
stall_out <= stall_in;
if px_in = C_BACKGROUND then
d <= C_UNLABELD;
label_out_s <= C_UNLABELD;
else
-- No one is labeled in the neighborhood generate new label
if a = C_UNLABELD and b = C_UNLABELD and c = C_UNLABELD and d = C_UNLABELD then
d <= next_lable_in;
label_out_s <= next_lable_in;
gen_lable_out <= '1';
else
if b /= C_UNLABELD then
-- no merging the selected label doesn't matter,
-- since the second pass will fix this
d <= b;
label_out_s <= b;
if d /= C_UNLABELD and b > d then
d <= d;
label_out_s <= d;
end if;
if c /= C_UNLABELD and b > c then
d <= c;
label_out_s <= c;
end if;
if a /= C_UNLABELD and b > a then
d <= a;
label_out_s <= a;
end if;
else
if a /= C_UNLABELD and c /= C_UNLABELD and a /= c then
if a < c then
d <= a;
label_out_s <= a;
equi_out(0) <= c;
equi_out(1) <= a;
equi_valid_out <= '1';
else
d <= c;
label_out_s <= c;
equi_out(0) <= a;
equi_out(1) <= c;
equi_valid_out <= '1';
end if;
end if;
if d /= C_UNLABELD and c /= C_UNLABELD and d /= c then
if d < c then
d <= d;
label_out_s <= d;
equi_out(0) <= c;
equi_out(1) <= d;
equi_valid_out <= '1';
else
d <= c;
label_out_s <= c;
equi_out(0) <= d;
equi_out(1) <= c;
equi_valid_out <= '1';
end if;
end if;
--no merge
if a /= C_UNLABELD and c /= C_UNLABELD and b = C_UNLABELD and d = C_UNLABELD and a = c then
d <= a;
label_out_s <= a;
end if;
if a /= C_UNLABELD and c = C_UNLABELD then
d <= a;
label_out_s <= a;
end if;
if d /= C_UNLABELD and c = C_UNLABELD then
d <= d;
label_out_s <= d;
end if;
if a = C_UNLABELD and b = C_UNLABELD and d = C_UNLABELD and c /= C_UNLABELD then
d <= c;
label_out_s <= c;
end if;
end if;
end if; -- b /= C_UNLABELD
end if;
if col_cnt = img_width_in - 1 or last_lbl_s = '1' then
d <= C_UNLABELD;
end if;
end if; -- stall
end if; --clk
end process p_lable_selection;
p_neighbor: process(clk_in, rst_in) is
begin
if rst_in = '1' then
a <= C_UNLABELD;
b <= C_UNLABELD;
c <= C_UNLABELD;
elsif rst_in = '0' and rising_edge(clk_in) then
if stall_in = '0' and px_valid_in = '1' then
a <= b;
b <= c;
-- c needs to be zero in the first line but on the last col of the first
-- line the label of the next line needs to be loaded
if col_cnt = img_width_in-2 or (row_cnt = 0 and col_cnt /= img_width_in-1) then
c <= C_UNLABELD;
else
c <=
row_buffer_s(row_buffer_s'high-1-to_integer(G_MAX_IMG_WIDTH-img_width_in));
end if;
-- on new line
if col_cnt = img_width_in - 1 then
b <= row_buffer_s(row_buffer_s'high-to_integer(G_MAX_IMG_WIDTH-img_width_in));
a <= C_UNLABELD;
end if;
if last_lbl_s = '1' then
--auto reset
a <= C_UNLABELD;
b <= C_UNLABELD;
c <= C_UNLABELD;
end if;
end if; --stall and valid
end if; --clk
end process p_neighbor;
end labeling_p1_arc;
| bsd-2-clause |
nihospr01/OpenSpeechPlatform-UCSD | Firmware/FPGA/car_field_v6_fmexg/._Real_._Math_.vhd | 6 | 90116 |
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
| bsd-2-clause |
nihospr01/OpenSpeechPlatform-UCSD | Firmware/FPGA/src/car_core.vhd | 1 | 3177 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity car_core is
port(
main_clk, reset, seq_reset, i2s_ws: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_sclk: out std_logic;
i2s_dspk: in std_logic;
i2s_dmic: out std_logic;
--
spi_sck: in std_logic;
spi_mosi: in std_logic;
spi_miso: out std_logic;
spi_cs0: in std_logic;
spi_cs1: in std_logic;
--
fmexg_mic_sync: in std_logic;
muted: in std_logic;
--
test_lrst_pre, test_djb_present: out std_logic
);
end entity;
architecture a of car_core is
component car_sequencer is
port(
main_clk, reset: in std_logic;
i2s_lr_st: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_spkr_dat: in std_logic;
i2s_spkr_sh, i2s_spkr_ld: out std_logic;
i2s_mic_ld, i2s_mic_sh, i2s_mic_dat: out std_logic;
--
spi_sck, spi_mosi, spi_cs0_n, spi_cs1_n: in std_logic;
spi_miso: out std_logic;
--
fmexg_mic_sync: in std_logic;
muted: in std_logic;
--
test_djb_present: out std_logic
);
end component;
component i2s_dio_2 is
port(
main_clk, reset, seq_reset: in std_logic;
--
i2s_out_dat, i2s_out_sh, i2s_out_ld: in std_logic;
i2s_in_ld, i2s_in_sh: in std_logic;
i2s_in_dat: out std_logic;
i2s_lr_st: in std_logic;
--
i2s_sclk: out std_logic;
i2s_ws: out std_logic;
i2s_din: in std_logic;
i2s_dout: out std_logic
);
end component;
---------------------------------------------------------------------------
signal i2s_spkr_dat, i2s_spkr_sh, i2s_spkr_ld: std_logic;
signal i2s_mic_ld, i2s_mic_sh, i2s_mic_dat: std_logic;
signal i2s_lr_st_pre, i2s_lr_st: std_logic;
signal spi_cs0_n, spi_cs1_n: std_logic;
signal spi_miso_internal: std_logic;
begin
spi_cs0_n <= not spi_cs0;
spi_cs1_n <= not spi_cs1;
spi_miso <= spi_miso_internal when (spi_cs0 and spi_cs1) = '0' else 'Z';
test_lrst_pre <= i2s_lr_st;
-- Sample i2s_ws_internal to avoid race condition, it changes exactly when
-- it's read by i2s_dio (rising edge of main_clk of bit 0)
process(reset, main_clk) is begin
if reset = '1' then
i2s_lr_st_pre <= '0';
elsif falling_edge(main_clk) then
i2s_lr_st_pre <= i2s_ws;
end if;
end process;
e_car_sequencer: car_sequencer port map (
main_clk => main_clk,
reset => reset,
i2s_lr_st => i2s_lr_st,
--
lvds_io => lvds_io,
--
i2s_mic_dat => i2s_mic_dat,
i2s_mic_sh => i2s_mic_sh,
i2s_mic_ld => i2s_mic_ld,
i2s_spkr_ld => i2s_spkr_ld,
i2s_spkr_sh => i2s_spkr_sh,
i2s_spkr_dat => i2s_spkr_dat,
--
spi_sck => spi_sck,
spi_mosi => spi_mosi,
spi_cs0_n => spi_cs0_n,
spi_cs1_n => spi_cs1_n,
spi_miso => spi_miso_internal,
--
fmexg_mic_sync => fmexg_mic_sync,
muted => muted,
--
test_djb_present => test_djb_present
);
e_i2s_dio: i2s_dio_2 port map (
main_clk => main_clk, reset => reset, seq_reset => seq_reset,
i2s_out_dat => i2s_mic_dat, i2s_out_sh => i2s_mic_sh, i2s_out_ld => i2s_mic_ld,
i2s_in_ld => i2s_spkr_ld, i2s_in_sh => i2s_spkr_sh, i2s_in_dat => i2s_spkr_dat,
i2s_lr_st => i2s_lr_st_pre,
i2s_sclk => i2s_sclk, i2s_ws => i2s_lr_st, i2s_din => i2s_dspk, i2s_dout => i2s_dmic
);
end architecture;
| bsd-2-clause |
nihospr01/OpenSpeechPlatform-UCSD | Firmware/FPGA/src/tl_djb_field.vhd | 1 | 2030 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tl_djb_field is
port(
ext_clk_in: in std_logic;
codec_clk: out std_logic;
--
lvds_io: inout std_logic;
--
i2s_sck: out std_logic;
i2s_ws: out std_logic;
i2s_dmic: in std_logic;
i2s_dspk: out std_logic;
--
spi_clk: out std_logic;
spi_mosi: out std_logic;
spi_miso: in std_logic;
spi_cs0: out std_logic;
spi_cs1: out std_logic
--
);
end entity;
architecture a of tl_djb_field is
component pll_4 is
port(
CLKI, RST: in std_logic;
CLKOP: out std_logic
);
end component;
component djb_core is
port(
hr_clk, reset: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_sclk: out std_logic;
i2s_ws: out std_logic;
i2s_dmic: in std_logic;
i2s_dspk: out std_logic;
--
spi_sck: out std_logic;
spi_mosi: out std_logic;
spi_miso: in std_logic;
spi_cs0: out std_logic;
spi_cs1: out std_logic;
--
test_main_clk, test_seq_idle, test_seq_reset: out std_logic;
test_sync_early, test_sync_late: out std_logic;
test_seq_reset_internal: out std_logic;
test_sync_2, test_sync: out std_logic
);
end component;
signal hr_clk, int_reset: std_logic;
begin
codec_clk <= ext_clk_in;
int_reset <= '0';
-- 48 kHz sampling * 2 channels * 32 bits = 3.072 MHz I2S bit clock
-- LVDS bit clock = 4x I2S bit clock = 12.288 MHz
-- hr_clk = 4x LVDS bit clock = 49.152 MHz
e_pll_4: pll_4 port map (
CLKI => ext_clk_in,
RST => int_reset,
CLKOP => hr_clk
);
e_djb_core: djb_core port map (
hr_clk => hr_clk, reset => int_reset,
lvds_io => lvds_io,
i2s_sclk => i2s_sck, i2s_ws => i2s_ws, i2s_dmic => i2s_dmic, i2s_dspk => i2s_dspk,
spi_sck => spi_clk, spi_mosi => spi_mosi, spi_miso => spi_miso, spi_cs0 => spi_cs0, spi_cs1 => spi_cs1,
test_main_clk => open, test_seq_idle => open, test_seq_reset => open,
test_sync_early => open, test_sync_late => open,
test_seq_reset_internal => open,
test_sync_2 => open, test_sync => open
);
end architecture;
| bsd-2-clause |
athalonis/CCL-Verification-Environment | src/vhdl/communication/udp_ip_stack/trunk/rtl/vhdl/ml605/UDP_integration_example.vhd | 1 | 15603 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:00 06/11/2011
-- Design Name:
-- Module Name: UDP_integration_example - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_integration_example is
port (
-- System signals
------------------
reset : in std_logic; -- asynchronous reset
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
-- System controls
------------------
PBTX : in std_logic;
PB_DO_SECOND_TX : in std_logic;
DO_SECOND_TX_LED : out std_logic;
UDP_RX : out std_logic;
UDP_Start : out std_logic;
PBTX_LED : out std_logic;
TX_Started : out std_logic;
TX_Completed : out std_logic;
TX_RSLT_0 : out std_logic;
TX_RSLT_1 : out std_logic;
reset_leds : in std_logic;
display : out std_logic_vector(7 downto 0);
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end UDP_integration_example;
architecture Behavioral of UDP_integration_example is
------------------------------------------------------------------------------
-- Component Declaration for the complete UDP layer
------------------------------------------------------------------------------
component UDP_Complete
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
clk_out : out std_logic;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- GMII Interface
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end component;
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp;
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR);
type count_mode_type is (RST, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD);
-- system signals
signal clk_int : std_logic;
signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
signal udp_tx_int : udp_tx_type;
signal udp_tx_result_int : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready_int : std_logic;
signal udp_rx_int : udp_rx_type;
signal udp_tx_start_int : std_logic;
signal udp_rx_start_int : std_logic;
signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
signal ip_rx_hdr_int : ipv4_rx_header_type;
-- state signals
signal state : state_type;
signal count : unsigned (7 downto 0);
signal tx_hdr : udp_tx_header_type;
signal tx_start_reg : std_logic;
signal tx_started_reg : std_logic;
signal tx_fin_reg : std_logic;
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx
-- control signals
signal next_state : state_type;
signal set_state : std_logic;
signal set_count : count_mode_type;
signal set_hdr : std_logic;
signal set_tx_start : set_clr_type;
signal set_last : std_logic;
signal set_tx_started : set_clr_type;
signal set_tx_fin : set_clr_type;
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
signal control_int : udp_control_type;
signal set_second_tx : sec_tx_ctrl_type;
begin
process (
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx,
PB_DO_SECOND_TX, do_second_tx
)
begin
-- set up our local addresses and default controls
our_ip <= x"c0a80119"; -- 192.168.1.25
our_mac <= x"002320212223";
control_int.ip_controls.arp_controls.clear_cache <= '0';
-- determine RX good and error LEDs
if udp_rx_int.hdr.is_valid = '1' then
UDP_RX <= '1';
else
UDP_RX <= '0';
end if;
UDP_Start <= udp_rx_start_int;
TX_Started <= tx_start_reg; --tx_started_reg;
TX_Completed <= tx_fin_reg;
TX_RSLT_0 <= udp_tx_result_int(0);
TX_RSLT_1 <= udp_tx_result_int(1);
DO_SECOND_TX_LED <= prime_second_tx;
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
case state is
when IDLE => display (3 downto 0) <= "0001";
when WAIT_RX_DONE => display (3 downto 0) <= "0010";
when DATA_OUT => display (3 downto 0) <= "0011";
when PAUSE => display (3 downto 0) <= "0100";
when CHECK_SECOND_TX => display (3 downto 0) <= "0101";
when SET_SEC_HDR => display (3 downto 0) <= "0110";
end case;
end process;
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
-- TX response process - COMB
tx_proc_combinatorial: process(
-- inputs
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX,
-- state
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx,
-- controls
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx
)
begin
-- set output_followers
udp_tx_int.hdr <= tx_hdr;
udp_tx_int.data.data_out_last <= set_last;
udp_tx_start_int <= tx_start_reg;
-- set control signal defaults
next_state <= IDLE;
set_state <= '0';
set_count <= HOLD;
set_hdr <= '0';
set_tx_start <= HOLD;
set_last <= '0';
set_tx_started <= HOLD;
set_tx_fin <= HOLD;
first_byte_rx <= (others => '0');
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
set_second_tx <= HOLD;
if PB_DO_SECOND_TX = '1' then
set_second_tx <= PRIME;
end if;
-- FSM
case state is
when IDLE =>
udp_tx_int.data.data_out_valid <= '0';
if udp_rx_start_int = '1' or PBTX = '1' then
if udp_rx_start_int = '1' then
first_byte_rx <= udp_rx_int.data.data_in;
else
first_byte_rx <= x"00";
end if;
set_tx_fin <= CLR;
set_count <= RST;
set_hdr <= '1';
if udp_rx_int.data.data_in_last = '1' then
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
else
next_state <= WAIT_RX_DONE;
set_state <= '1';
end if;
end if;
when WAIT_RX_DONE =>
-- wait until RX pkt fully received
if udp_rx_int.data.data_in_last = '1' then
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
end if;
when DATA_OUT =>
if udp_tx_result_int = UDPTX_RESULT_ERR then
-- have an error from the IP TX layer, clear down the TX
set_tx_start <= CLR;
set_tx_fin <= SET;
set_tx_started <= CLR;
set_second_tx <= CLR;
next_state <= IDLE;
set_state <= '1';
else
if udp_tx_result_int = UDPTX_RESULT_SENDING then
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
end if;
if ip_rx_hdr_int.is_broadcast = '1' then
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
else
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
end if;
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
if udp_tx_data_out_ready_int = '1' then
if unsigned(count) = x"03" then
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= PAUSE;
set_state <= '1';
else
set_count <= INCR;
end if;
end if;
end if;
when PAUSE =>
next_state <= CHECK_SECOND_TX;
set_state <= '1';
when CHECK_SECOND_TX =>
if prime_second_tx = '1' then
set_second_tx <= DO;
next_state <= SET_SEC_HDR;
set_state <= '1';
else
set_second_tx <= CLR;
next_state <= IDLE;
set_state <= '1';
end if;
when SET_SEC_HDR =>
set_hdr <= '1';
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
end case;
end process;
-- TX response process - SEQ
tx_proc_sequential: process(clk_int)
begin
if rising_edge(clk_int) then
if reset = '1' then
-- reset state variables
state <= IDLE;
count <= x"00";
tx_start_reg <= '0';
tx_hdr.dst_ip_addr <= (others => '0');
tx_hdr.dst_port <= (others => '0');
tx_hdr.src_port <= (others => '0');
tx_hdr.data_length <= (others => '0');
tx_hdr.checksum <= (others => '0');
tx_started_reg <= '0';
tx_fin_reg <= '0';
PBTX_LED <= '0';
do_second_tx <= '0';
prime_second_tx <= '0';
else
PBTX_LED <= PBTX;
-- Next rx_state processing
if set_state = '1' then
state <= next_state;
else
state <= state;
end if;
-- count processing
case set_count is
when RST => count <= x"00";
when INCR => count <= count + 1;
when HOLD => count <= count;
end case;
-- set tx hdr
if set_hdr = '1' then
-- select the dst addr of the tx:
-- if do_second_tx, to solaris box
-- otherwise control according to first byte of received data:
-- B = broadcast
-- C = to dummy address to test timeout
-- D to solaris box
-- otherwise, direct to sender
if do_second_tx = '1' then
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
elsif first_byte_rx = x"42" then
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
elsif first_byte_rx = x"43" then
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
elsif first_byte_rx = x"44" then
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
else
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
end if;
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
tx_hdr.data_length <= x"0004";
tx_hdr.checksum <= x"0000";
else
tx_hdr <= tx_hdr;
end if;
-- set tx start signal
case set_tx_start is
when SET => tx_start_reg <= '1';
when CLR => tx_start_reg <= '0';
when HOLD => tx_start_reg <= tx_start_reg;
end case;
-- set tx started signal
case set_tx_started is
when SET => tx_started_reg <= '1';
when CLR => tx_started_reg <= '0';
when HOLD => tx_started_reg <= tx_started_reg;
end case;
-- set tx finished signal
case set_tx_fin is
when SET => tx_fin_reg <= '1';
when CLR => tx_fin_reg <= '0';
when HOLD => tx_fin_reg <= tx_fin_reg;
end case;
-- set do_second_tx
case set_second_tx is
when PRIME =>
prime_second_tx <= '1';
when DO =>
prime_second_tx <= '0';
do_second_tx <= '1';
when CLR =>
prime_second_tx <= '0';
do_second_tx <= '0';
when HOLD =>
prime_second_tx <= prime_second_tx;
do_second_tx <= do_second_tx;
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Instantiate the UDP layer
------------------------------------------------------------------------------
UDP_block : UDP_Complete
generic map (
ARP_TIMEOUT => 10 -- timeout in seconds
)
PORT MAP (
-- UDP interface
udp_tx_start => udp_tx_start_int,
udp_txi => udp_tx_int,
udp_tx_result => udp_tx_result_int,
udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
udp_rx_start => udp_rx_start_int,
udp_rxo => udp_rx_int,
-- IP RX signals
ip_rx_hdr => ip_rx_hdr_int,
-- System interface
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
clk_out => clk_int,
reset => reset,
our_ip_address => our_ip,
our_mac_address => our_mac,
control => control_int,
-- status signals
arp_pkt_count => arp_pkt_count_int,
ip_pkt_count => ip_pkt_count_int,
-- GMII Interface
-----------------
phy_resetn => phy_resetn,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_col => gmii_col,
gmii_crs => gmii_crs,
mii_tx_clk => mii_tx_clk
);
end Behavioral;
| bsd-2-clause |
cr1901/HDMI2USB-litex-firmware | gateware/encoder/vhdl/ZZ_TOP.vhd | 5 | 9816 | -------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause |
cr1901/HDMI2USB-litex-firmware | gateware/encoder/vhdl/RAM.vhd | 5 | 4964 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RAM --
-- Design : MDCT --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : RAM.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:3 row select
-- 2:0 col select
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
entity RAM is
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end RAM;
architecture RTL of RAM is
type mem_type is array ((2**RAMADRR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL; | bsd-2-clause |
HackLinux/CPU-Design | cpu/work/dmemory/_primary.vhd | 4 | 302 | library verilog;
use verilog.vl_types.all;
entity dmemory is
port(
address : in vl_logic_vector(31 downto 0);
data : inout vl_logic_vector(31 downto 0);
read : in vl_logic;
write : in vl_logic
);
end dmemory;
| bsd-2-clause |
HackLinux/CPU-Design | cpu/work/clock/_primary.vhd | 4 | 129 | library verilog;
use verilog.vl_types.all;
entity clock is
port(
clk : out vl_logic
);
end clock;
| bsd-2-clause |
mpownby/emucore | new_hardware/williams_special_chip/vhdl/WilliamsSC/main.vhd | 1 | 3521 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:19:40 08/05/2014
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port (
AH : out std_logic_vector(15 downto 8);
AL : inout std_logic_vector(7 downto 0);
BA_BS_N : in std_logic;
CS_N : in std_logic;
D : inout std_logic_vector(7 downto 0);
E_N : in std_logic;
HALT_N : in std_logic;
HTCF_N : out std_logic;
CLK_4MHZ : in std_logic;
R_WN : inout std_logic;
RESET_N : in std_logic;
TCF_N : in std_logic;
U_LN : in std_logic;
WINH_N : out std_logic);
end main;
architecture Behavioral of main is
--mode bits
signal srcstride : std_logic;
signal dststride : std_logic;
signal synce : std_logic;
signal transparency : std_logic;
signal solid : std_logic;
signal shift : std_logic;
signal inhl : std_logic;
signal inhu : std_logic;
--registers
signal color : std_logic_vector(7 downto 0);
signal src : std_logic_vector(15 downto 0);
signal dst : std_logic_vector(15 downto 0);
signal width : std_logic_vector(7 downto 0);
signal height : std_logic_vector(7 downto 0);
signal reqhalt : std_logic := '0';
signal doblit : std_logic := '0';
signal csqueued : std_logic := '0';
begin
AH(15 downto 8) <= "11111111";
--AL(7 downto 0) <= "11111111";
--D(7 downto 0) <= "11111111";
HTCF_N <= '1';
--R_WN <= '1';
WINH_N <= '1';
watch_cs : process(E_N,RESET_N)
begin
if (RESET_N='0') then
-- todo
else
if (falling_edge(E_N)) then
if (CS_N='0') then
csqueued <= '1';
end if;
end if;
end if;
end process;
loadreg: process(CLK_4MHZ,RESET_N)
begin
if(RESET_N='0') then
doblit<='0';
else
if(rising_edge(CLK_4MHZ)) then
if (csqueued = '1') then
case AL(2 downto 0) IS
when "000" =>
--set mode bits
srcstride <= D(0);
dststride <= D(1);
synce <= D(2);
transparency <= D(3);
solid <= D(4);
shift <= D(5);
inhl <= D(6);
inhu <= D(7);
--start blit
doblit <= '1';
when "001" =>
--set color replacement
color <= D;
when "010" =>
--set src high
src(15 downto 8) <= D;
when "011" =>
--set src low
src(7 downto 0) <= D;
when "100" =>
--set dest high
dst(15 downto 8) <= D;
when "101" =>
--set dest low
dst(7 downto 0) <= D;
when "110" =>
--set width
width <= D xor "00000100";
when "111" =>
--set height
height <= D xor "00000100";
when others =>
end case;
-- wait for CS to be lowered again
csqueued <= '0';
end if; -- CS was lowered
end if; -- rising edge of CLK_4MHZ
end if; -- else if RESET_N is not low
end process;
end Behavioral;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/QUANTIZER.vhd | 5 | 7248 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : DCT QUANTIZER --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : QUANTIZER.VHD --
-- Created : Sun Aug 27 2006 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity quantizer is
generic
(
SIZE_C : INTEGER := 12;
RAMQADDR_W : INTEGER := 7;
RAMQDATA_W : INTEGER := 8
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
divalid : in STD_LOGIC;
qdata : in std_logic_vector(7 downto 0);
qwaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic;
cmp_idx : in unsigned(2 downto 0);
do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
dovalid : out STD_LOGIC
);
end quantizer;
architecture rtl of quantizer is
constant INTERN_PIPE_C : INTEGER := 3;
signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0):=(others => '0');
signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0):=(others => '0');
signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0):=(others => '0');
signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal round_s : STD_LOGIC:='0';
signal di_d1 : std_logic_vector(SIZE_C-1 downto 0):=(others => '0');
signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0):=(others => '0');
signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0):=(others => '0');
signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal table_select : std_logic:='0';
begin
----------------------------
-- RAMQ
----------------------------
U_RAMQ : entity work.RAMZ
generic map
(
RAMADDR_W => RAMQADDR_W,
RAMDATA_W => RAMQDATA_W
)
port map
(
d => qdata,
waddr => qwaddr,
raddr => slv_romaddr_s,
we => qwren,
clk => CLK,
q => romdatao_s
);
divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
r_divider : entity work.r_divider
port map
(
rst => rst,
clk => clk,
a => di_d1,
d => romdatao_s,
q => do_s
) ;
do <= do_s;
slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
------------------------------
-- Quantization sub table select
------------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
table_select <= '0';
else
-- luminance table select
if cmp_idx < 2 then
table_select <= '0';
-- chrominance table select
else
table_select <= '1';
end if;
end if;
end if;
end process;
----------------------------
-- address incrementer
----------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
romaddr_s <= (others => '0');
pipeline_reg <= (OTHERS => '0');
di_d1 <= (OTHERS => '0');
sign_bit_pipe <= (others => '0');
else
if divalid = '1' then
romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
end if;
pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
di_d1 <= di;
sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
end if;
end if;
end process;
dovalid <= pipeline_reg(pipeline_reg'high);
end rtl;
-------------------------------------------------------------------------------- | bsd-2-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/linkport_v1_00_a/hdl/vhdl/aurora_tx_ctrl.vhd | 4 | 1007 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aurora_tx_ctrl is
port (
tx_ff_empty: in std_logic;
tx_ff_rd :out std_logic;
tx_ff_rdata : in std_logic_vector(17 downto 0);
aur_tx_sof_1 : out std_logic;
aur_tx_eof_1: out std_logic ;
aur_tx_data : out std_logic_vector(15 downto 0);
aur_tx_rem: out std_logic ;
aur_tx_src_rdy_1: out std_logic ;
aur_tx_dst_rdy_1: in std_logic
);
end aurora_tx_ctrl;
architecture aurora_tx_ctrl_b1 of aurora_tx_ctrl is
signal flag :std_logic_vector(1 downto 0);
signal tx_ff_rd_1: std_logic;
begin
tx_ff_rd_1 <= (not tx_ff_empty) and (not aur_tx_dst_rdy_1) ;
aur_tx_rem <= '1' ;
flag <= tx_ff_rdata(17 downto 16) ;
aur_tx_data <= tx_ff_rdata (15 downto 0) ;
aur_tx_sof_1 <= not (flag(0) and tx_ff_rd_1) ;
aur_tx_eof_1 <= not (flag(1) and tx_ff_rd_1) ;
aur_tx_src_rdy_1 <= not tx_ff_rd_1 ;
tx_ff_rd <=tx_ff_rd_1;
end aurora_tx_ctrl_b1;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rgbfifo/simulation/rgbfifo_rng.vhd | 3 | 3884 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rgbfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rgbfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/ddr2ram/user_design/rtl/mcb_soft_calibration_top.vhd | 19 | 21926 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
| bsd-2-clause |
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