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Stederr/ESCOM | Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/shiftr00.vhd | 1 | 1394 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shiftr00 is
port(
clkcshr: in std_logic ;
codopcshr: in std_logic_vector ( 3 downto 0 );
portAcshr: in std_logic_vector ( 7 downto 0 );
inFlagcshr: in std_logic;
outcshr: out std_logic_vector ( 7 downto 0 );
outFlagcshr: out std_logic );
end;
architecture shiftr0 of shiftr00 is
begin
pshr: process(codopcshr, portAcshr)
begin
if(codopcshr = "1010") then
outcshr(7) <= '0';
outcshr(6 downto 0) <= portAcshr(7 downto 1);
outFlagcshr <= '1';
else
outcshr <= (others => 'Z');
outFlagcshr <= 'Z';
end if;
end process pshr;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end shiftr0;
| apache-2.0 |
dm-urievich/afc-smm | software/third-patry/dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_8_x_8.vhd | 2 | 3208 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | apache-2.0 |
dm-urievich/afc-smm | software/third-patry/uart2bus/trunk/vhdl/rtl/uartParser.vhd | 3 | 26664 | -----------------------------------------------------------------------------------------
-- uart parser module
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
entity uartParser is
generic ( -- parameters
AW : integer := 8);
port ( -- global signals
clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
-- transmit and receive internal interface signals from uart interface
txBusy : in std_logic; -- signs that transmitter is busy
rxData : in std_logic_vector(7 downto 0); -- data byte received
newRxData : in std_logic; -- signs that a new byte was received
txData : out std_logic_vector(7 downto 0); -- data byte to transmit
newTxData : out std_logic; -- asserted to indicate that there is a new data byte for transmission
-- internal bus to register file
intReq : out std_logic; --
intGnt : in std_logic; --
intRdData : in std_logic_vector(7 downto 0); -- data read from register file
intAddress : out std_logic_vector(AW - 1 downto 0); -- address bus to register file
intWrData : out std_logic_vector(7 downto 0); -- write data to register file
intWrite : out std_logic; -- write control to register file
intRead : out std_logic); -- read control to register file
end uartParser;
architecture Behavioral of uartParser is
-- internal constants
-- main (receive) state machine states
signal mainSm : std_logic_vector(3 downto 0); -- main state machine
constant mainIdle : std_logic_vector(mainSm'range) := "0000";
constant mainWhite1 : std_logic_vector(mainSm'range) := "0001";
constant mainData : std_logic_vector(mainSm'range) := "0010";
constant mainWhite2 : std_logic_vector(mainSm'range) := "0011";
constant mainAddr : std_logic_vector(mainSm'range) := "0100";
constant mainEol : std_logic_vector(mainSm'range) := "0101";
-- binary mode extension states
constant mainBinCmd : std_logic_vector(mainSm'range) := "1000";
constant mainBinAdrh : std_logic_vector(mainSm'range) := "1001";
constant mainBinAdrl : std_logic_vector(mainSm'range) := "1010";
constant mainBinLen : std_logic_vector(mainSm'range) := "1011";
constant mainBinData : std_logic_vector(mainSm'range) := "1100";
-- transmit state machine
signal txSm : std_logic_vector(2 downto 0); -- transmit state machine
constant txIdle : std_logic_vector(txSm'range) := "000";
constant txHiNib : std_logic_vector(txSm'range) := "001";
constant txLoNib : std_logic_vector(txSm'range) := "100";
constant txCharCR : std_logic_vector(txSm'range) := "101";
constant txCharLF : std_logic_vector(txSm'range) := "110";
-- define characters used by the parser
constant charNul : std_logic_vector(7 downto 0) := x"00";
constant charTab : std_logic_vector(7 downto 0) := x"09";
constant charLF : std_logic_vector(7 downto 0) := x"0A";
constant charCR : std_logic_vector(7 downto 0) := x"0D";
constant charSpace : std_logic_vector(7 downto 0) := x"20";
constant charZero : std_logic_vector(7 downto 0) := x"30";
constant charOne : std_logic_vector(7 downto 0) := x"31";
constant charTwo : std_logic_vector(7 downto 0) := x"32";
constant charThree : std_logic_vector(7 downto 0) := x"33";
constant charFour : std_logic_vector(7 downto 0) := x"34";
constant charFive : std_logic_vector(7 downto 0) := x"35";
constant charSix : std_logic_vector(7 downto 0) := x"36";
constant charSeven : std_logic_vector(7 downto 0) := x"37";
constant charEight : std_logic_vector(7 downto 0) := x"38";
constant charNine : std_logic_vector(7 downto 0) := x"39";
constant charAHigh : std_logic_vector(7 downto 0) := x"41";
constant charBHigh : std_logic_vector(7 downto 0) := x"42";
constant charCHigh : std_logic_vector(7 downto 0) := x"43";
constant charDHigh : std_logic_vector(7 downto 0) := x"44";
constant charEHigh : std_logic_vector(7 downto 0) := x"45";
constant charFHigh : std_logic_vector(7 downto 0) := x"46";
constant charRHigh : std_logic_vector(7 downto 0) := x"52";
constant charWHigh : std_logic_vector(7 downto 0) := x"57";
constant charALow : std_logic_vector(7 downto 0) := x"61";
constant charBLow : std_logic_vector(7 downto 0) := x"62";
constant charCLow : std_logic_vector(7 downto 0) := x"63";
constant charDLow : std_logic_vector(7 downto 0) := x"64";
constant charELow : std_logic_vector(7 downto 0) := x"65";
constant charFLow : std_logic_vector(7 downto 0) := x"66";
constant charRLow : std_logic_vector(7 downto 0) := x"72";
constant charWLow : std_logic_vector(7 downto 0) := x"77";
-- binary extension mode commands - the command is indicated by bits 5:4 of the command byte
constant binCmdNop : std_logic_vector(1 downto 0) := "00";
constant binCmdRead : std_logic_vector(1 downto 0) := "01";
constant binCmdWrite : std_logic_vector(1 downto 0) := "10";
signal dataInHexRange : std_logic; -- indicates that the received data is in the range of hex number
signal binLastByte : std_logic; -- last byte flag indicates that the current byte in the command is the last
signal txEndP : std_logic; -- transmission end pulse
signal readOp : std_logic; -- read operation flag
signal writeOp : std_logic; -- write operation flag
signal binReadOp : std_logic; -- binary mode read operation flag
signal binWriteOp : std_logic; -- binary mode write operation flag
signal sendStatFlag : std_logic; -- send status flag
signal addrAutoInc : std_logic; -- address auto increment mode
signal dataParam : std_logic_vector(7 downto 0); -- operation data parameter
signal dataNibble : std_logic_vector(3 downto 0); -- data nibble from received character
signal addrParam : std_logic_vector(15 downto 0); -- operation address parameter
signal addrNibble : std_logic_vector(3 downto 0); -- data nibble from received character
signal binByteCount : std_logic_vector(7 downto 0); -- binary mode byte counter
signal iIntAddress : std_logic_vector(intAddress'range); --
signal iWriteReq : std_logic; --
signal iIntWrite : std_logic; --
signal readDone : std_logic; -- internally generated read done flag
signal readDoneS : std_logic; -- sampled read done
signal readDataS : std_logic_vector(7 downto 0); -- sampled read data
signal iReadReq : std_logic; --
signal iIntRead : std_logic; --
signal txChar : std_logic_vector(7 downto 0); -- transmit byte from nibble to character conversion
signal sTxBusy : std_logic; -- sampled tx_busy for falling edge detection
signal txNibble : std_logic_vector(3 downto 0); -- nibble value for transmission
-- module implementation
-- main state machine
begin
process (clr, clk)
begin
if (clr = '1') then
mainSm <= mainIdle;
elsif (rising_edge(clk)) then
if (newRxData = '1') then
case mainSm is
-- wait for a read ('r') or write ('w') command
-- binary extension - an all zeros byte enabled binary commands
when mainIdle =>
-- check received character
if (rxData = charNul) then
-- an all zeros received byte enters binary mode
mainSm <= mainBinCmd;
elsif ((rxData = charRLow) or (rxData = charRHigh)) then
-- on read wait to receive only address field
mainSm <= mainWhite2;
elsif ((rxData = charWLow) or (rxData = charWHigh)) then
-- on write wait to receive data and address
mainSm <= mainWhite1;
elsif ((rxData = charCR) or (rxData = charLF)) then
-- on new line sta in idle
mainSm <= mainIdle;
else
-- any other character wait to end of line (EOL)
mainSm <= mainEol;
end if;
-- wait for white spaces till first data nibble
when mainWhite1 =>
-- wait in this case until any white space character is received. in any
-- valid character for data value switch to data state. a new line or carriage
-- return should reset the state machine to idle.
-- any other character transitions the state machine to wait for EOL.
if ((rxData = charSpace) or (rxData = charTab)) then
mainSm <= mainWhite1;
elsif (dataInHexRange = '1') then
mainSm <= mainData;
elsif ((rxData = charCR) or (rxData = charLF)) then
mainSm <= mainIdle;
else
mainSm <= mainEol;
end if;
-- receive data field
when mainData =>
-- wait while data in hex range. white space transition to wait white 2 state.
-- CR and LF resets the state machine. any other value cause state machine to
-- wait til end of line.
if (dataInHexRange = '1') then
mainSm <= mainData;
elsif ((rxData = charSpace) or (rxData = charTab)) then
mainSm <= mainWhite2;
elsif ((rxData = charCR) or (rxData = charLF)) then
mainSm <= mainIdle;
else
mainSm <= mainEol;
end if;
-- wait for white spaces till first address nibble
when mainWhite2 =>
-- similar to MAIN_WHITE1
if ((rxData = charSpace) or (rxData = charTab)) then
mainSm <= mainWhite2;
elsif (dataInHexRange = '1') then
mainSm <= mainAddr;
elsif ((rxData = charCR) or (rxData = charLF)) then
mainSm <= mainIdle;
else
mainSm <= mainEol;
end if;
-- receive address field
when mainAddr =>
-- similar to MAIN_DATA
if (dataInHexRange = '1') then
mainSm <= mainAddr;
elsif ((rxData = charCR) or (rxData = charLF)) then
mainSm <= mainIdle;
else
mainSm <= mainEol;
end if;
-- wait to EOL
when mainEol =>
-- wait for CR or LF to move back to idle
if ((rxData = charCR) or (rxData = charLF)) then
mainSm <= mainIdle;
end if;
-- binary extension
-- wait for command - one byte
when mainBinCmd =>
-- check if command is a NOP command
if (rxData(5 downto 4) = binCmdNop) then
-- if NOP command then switch back to idle state
mainSm <= mainIdle;
else
-- not a NOP command, continue receiving parameters
mainSm <= mainBinAdrh;
end if;
-- wait for address parameter - two bytes
-- high address byte
when mainBinAdrh =>
-- switch to next state
mainSm <= mainBinAdrl;
-- low address byte
when mainBinAdrl =>
-- switch to next state
mainSm <= mainBinLen;
-- wait for length parameter - one byte
when mainBinLen =>
-- check if write command else command reception ended
if (binWriteOp = '1') then
-- wait for write data
mainSm <= mainBinData;
else
-- command reception has ended
mainSm <= mainIdle;
end if;
-- on write commands wait for data till end of buffer as specified by length parameter
when mainBinData =>
-- if this is the last data byte then return to idle
if (binLastByte = '1') then
mainSm <= mainIdle;
end if;
-- go to idle
when others =>
mainSm <= mainIdle;
end case;
end if;
end if;
end process;
-- read operation flag
-- write operation flag
-- binary mode read operation flag
-- binary mode write operation flag
process (clr, clk)
begin
if (clr = '1') then
readOp <= '0';
writeOp <= '0';
binReadOp <= '0';
binWriteOp <= '0';
elsif (rising_edge(clk)) then
if ((mainSm = mainIdle) and (newRxData = '1')) then
-- the read operation flag is set when a read command is received in idle state and cleared
-- if any other character is received during that state.
if ((rxData = charRLow) or (rxData = charRHigh)) then
readOp <= '1';
else
readOp <= '0';
end if;
-- the write operation flag is set when a write command is received in idle state and cleared
-- if any other character is received during that state.
if ((rxData = charWLow) or (rxData = charWHigh)) then
writeOp <= '1';
else
writeOp <= '0';
end if;
end if;
if ((mainSm = mainBinCmd) and (newRxData = '1') and (rxData(5 downto 4) = binCmdRead)) then
-- read command is started on reception of a read command
binReadOp <= '1';
elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '1')) then
-- read command ends on transmission of the last byte read
binReadOp <= '0';
end if;
if ((mainSm = mainBinCmd) and (newRxData = '1') and (rxData(5 downto 4) = binCmdWrite)) then
-- write command is started on reception of a write command
binWriteOp <= '1';
elsif ((mainSm = mainBinData) and (newRxData = '1') and (binLastByte = '1')) then
binWriteOp <= '0';
end if;
end if;
end process;
-- send status flag - used only in binary extension mode
-- address auto increment - used only in binary extension mode
process (clr, clk)
begin
if (clr = '1') then
sendStatFlag <= '0';
addrAutoInc <= '0';
elsif (rising_edge(clk)) then
if ((mainSm = mainBinCmd) and (newRxData = '1')) then
-- check if a status byte should be sent at the end of the command
sendStatFlag <= rxData(0);
-- check if address should be automatically incremented or not.
-- Note that when rx_data[1] is set, address auto increment is disabled.
addrAutoInc <= not(rxData(1));
end if;
end if;
end process;
-- operation data parameter
process (clr, clk)
begin
if (clr = '1') then
dataParam <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainWhite1) and (newRxData = '1') and (dataInHexRange = '1')) then
dataParam <= "0000" & dataNibble;
elsif ((mainSm = mainData) and (newRxData = '1') and (dataInHexRange = '1')) then
dataParam <= dataParam(3 downto 0) & dataNibble;
end if;
end if;
end process;
-- operation address parameter
process (clr, clk)
begin
if (clr = '1') then
addrParam <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainWhite2) and (newRxData = '1') and (dataInHexRange = '1')) then
addrParam <= x"000" & dataNibble;
elsif ((mainSm = mainAddr) and (newRxData = '1') and (dataInHexRange = '1')) then
addrParam <= addrParam(11 downto 0) & dataNibble;
-- binary extension
elsif (mainSm = mainBinAdrh) then
addrParam(15 downto 8) <= rxData;
elsif (mainSm = mainBinAdrl) then
addrParam(7 downto 0) <= rxData;
end if;
end if;
end process;
-- binary mode command byte counter is loaded with the length parameter and counts down to zero.
-- NOTE: a value of zero for the length parameter indicates a command of 256 bytes.
process (clr, clk)
begin
if (clr = '1') then
binByteCount <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainBinLen) and (newRxData = '1')) then
binByteCount <= rxData;
elsif (((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) or ((binReadOp = '1') and (txEndP = '1'))) then
-- byte counter is updated on every new data received in write operations and for every
-- byte transmitted for read operations.
binByteCount <= binByteCount - 1;
end if;
end if;
end process;
-- internal write control and data
-- internal read control
process (clr, clk)
begin
if (clr = '1') then
iReadReq <= '0';
iIntRead <= '0';
iWriteReq <= '0';
iIntWrite <= '0';
intWrData <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainAddr) and (writeOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iWriteReq <= '1';
intWrData <= dataParam;
-- binary extension mode
elsif ((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) then
iWriteReq <= '1';
intWrData <= rxData;
elsif ((intGnt = '1') and (iWriteReq = '1')) then
iWriteReq <= '0';
iIntWrite <= '1';
else
iIntWrite <= '0';
end if;
if ((mainSm = mainAddr) and (readOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iReadReq <= '1';
-- binary extension
elsif ((mainSm = mainBinLen) and (binReadOp = '1') and (newRxData = '1')) then
-- the first read request is issued on reception of the length byte
iReadReq <= '1';
elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) then
-- the next read requests are issued after the previous read value was transmitted and
-- this is not the last byte to be read.
iReadReq <= '1';
elsif ((intGnt = '1') and (iReadReq = '1')) then
iReadReq <= '0';
iIntRead <= '1';
else
iIntRead <= '0';
end if;
end if;
end process;
-- internal address
process (clr, clk)
begin
if (clr = '1') then
iIntAddress <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainAddr) and (newRxData = '1') and (dataInHexRange = '0')) then
iIntAddress <= addrParam(AW - 1 downto 0);
-- binary extension
elsif ((mainSm = mainBinLen) and (newRxData = '1')) then
-- sample address parameter on reception of length byte
iIntAddress <= addrParam(AW - 1 downto 0);
elsif ((addrAutoInc = '1') and (((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) or ((binWriteOp = '1') and (iIntWrite = '1')))) then
-- address is incremented on every read or write if enabled
iIntAddress <= iIntAddress + 1;
end if;
end if;
end process;
-- read done flag and sampled data read
process (clr, clk)
begin
if (clr = '1') then
readDone <= '0';
readDoneS <= '0';
readDataS <= (others => '0');
elsif (rising_edge(clk)) then
-- read done flag
readDone <= iIntRead;
-- sampled read done
readDoneS <= readDone;
-- sampled data read
if (readDone = '1') then
readDataS <= intRdData;
end if;
end if;
end process;
-- transmit state machine and control
process (clr, clk)
begin
if (clr = '1') then
txSm <= txIdle;
txData <= (others => '0');
newTxData <= '0';
elsif (rising_edge(clk)) then
case txSm is
-- wait for read done indication
when txIdle =>
-- on end of every read operation check how the data read should be transmitted
-- according to read type: ascii or binary.
if (readDoneS = '1') then
-- on binary mode read transmit byte value
if (binReadOp = '1') then
-- note that there is no need to change state
txData <= readDataS;
newTxData <= '1';
else
txSm <= txHiNib;
txData <= txChar;
newTxData <= '1';
end if;
-- check if status byte should be transmitted
elsif (((sendStatFlag = '1') and (binReadOp = '1') and (txEndP = '1') and (binLastByte = '1')) or ((sendStatFlag = '1') and (binWriteOp = '1') and (newRxData = '1') and (binLastByte = '1')) or ((mainSm = mainBinCmd) and (newRxData = '1') and (rxData(5 downto 4) = binCmdNop))) then
-- send status byte - currently a constant
txData <= x"5A";
newTxData <= '1';
else
newTxData <= '0';
end if;
when txHiNib =>
-- wait for transmit to end
if (txEndP = '1') then
txSm <= txLoNib;
txData <= txChar;
newTxData <= '1';
else
newTxData <= '0';
end if;
-- wait for transmit to end
when txLoNib =>
if (txEndP = '1') then
txSm <= txCharCR;
txData <= charCR;
newTxData <= '1';
else
newTxData <= '0';
end if;
-- wait for transmit to end
when txCharCR =>
if (txEndP = '1') then
txSm <= txCharLF;
txData <= charLF;
newTxData <= '1';
else
newTxData <= '0';
end if;
-- wait for transmit to end
when txCharLF =>
if (txEndP = '1') then
txSm <= txIdle;
end if;
-- clear tx new data flag
newTxData <= '0';
-- return to idle
when others =>
txSm <= txIdle;
end case;
end if;
end process;
-- sampled tx_busy
process (clr, clk)
begin
if (clr = '1') then
sTxBusy <= '1';
elsif (rising_edge(clk)) then
sTxBusy <= txBusy;
end if;
end process;
-- indicates that the received data is in the range of hex number
dataInHexRange <= '1' when (((rxData >= charZero) and (rxData <= charNine)) or
((rxData >= charAHigh) and (rxData <= charFHigh)) or
((rxData >= charALow) and (rxData <= charFLow))) else '0';
-- last byte in command flag
binLastByte <= '1' when (binByteCount = x"01") else '0';
-- select the nibble to the nibble to character conversion
txNibble <= readDataS(3 downto 0) when (txSm = txHiNib) else readDataS(7 downto 4);
-- tx end pulse
txEndP <= '1' when ((txBusy = '0') and (sTxBusy = '1')) else '0';
-- character to nibble conversion
with rxData select
dataNibble <= x"0" when charZero,
x"1" when charOne,
x"2" when charTwo,
x"3" when charThree,
x"4" when charFour,
x"5" when charFive,
x"6" when charSix,
x"7" when charSeven,
x"8" when charEight,
x"9" when charNine,
x"A" when charALow,
x"A" when charAHigh,
x"B" when charBLow,
x"B" when charBHigh,
x"C" when charCLow,
x"C" when charCHigh,
x"D" when charDLow,
x"D" when charDHigh,
x"E" when charELow,
x"E" when charEHigh,
x"F" when charFLow,
x"F" when charFHigh,
x"F" when others;
-- nibble to character conversion
with txNibble select
txChar <= charZero when x"0",
charOne when x"1",
charTwo when x"2",
charThree when x"3",
charFour when x"4",
charFive when x"5",
charSix when x"6",
charSeven when x"7",
charEight when x"8",
charNine when x"9",
charAHigh when x"A",
charBHigh when x"B",
charCHigh when x"C",
charDHigh when x"D",
charEHigh when x"E",
charFHigh when x"F",
charFHigh when others;
intAddress <= iIntAddress;
intWrite <= iIntWrite;
intRead <= iIntRead;
intReq <= '1' when (iReadReq = '1') else
'1' when (iWriteReq = '1') else '0';
end Behavioral;
| apache-2.0 |
parthpower/aes-fpga | aes_Encrypt_FSM.vhd | 1 | 5495 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.aes_types.all;
entity aes_Encrypt_FSM is
port(
key_in : in matrix(3 downto 0, 3 downto 0);
data_block_in : in matrix(3 downto 0, 3 downto 0);
data_block_out : out matrix(3 downto 0, 3 downto 0);
key_load : in std_logic;
start : in std_logic;
done : out std_logic;
busy : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity aes_Encrypt_FSM;
architecture RTL of aes_Encrypt_FSM is
component aes_KeySchedule_FSM
port(key_in : in matrix(3 downto 0, 3 downto 0);
keychain_out : out matrix_128(10 downto 0);
start : in std_logic;
done : out std_logic;
clk : in std_logic;
rst : in std_logic);
end component aes_KeySchedule_FSM;
component aes_SubBytes_ShiftRows
port(data_in : in matrix(3 downto 0, 3 downto 0);
data_out : out matrix(3 downto 0, 3 downto 0);
start : in std_logic;
done : out std_logic;
clk : in std_logic;
rst : in std_logic);
end component aes_SubBytes_ShiftRows;
component aes_MixColumns
port(data_in : in matrix(3 downto 0, 3 downto 0);
data_out : out matrix(3 downto 0, 3 downto 0);
start : in std_logic;
done : out std_logic;
clk : in std_logic;
rst : in std_logic);
end component aes_MixColumns;
component aes_AddRoundKey
port(data_in : in matrix(3 downto 0, 3 downto 0);
key_in : in matrix(3 downto 0, 3 downto 0);
data_out : out matrix(3 downto 0, 3 downto 0);
clk : in std_logic;
rst : in std_logic);
end component aes_AddRoundKey;
signal latched_data_in, round_data_out, round_data_in, round_key, latched_key_in : matrix(3 downto 0, 3 downto 0);
signal ss_data_in, ss_data_out, mc_data_in, mc_data_out : matrix(3 downto 0, 3 downto 0);
signal mc_start, mc_done, ss_done, ss_start : std_logic;
signal keychain : matrix_128(10 downto 0);
signal round_counter : integer range 1 to 10 := 1;
signal ks_start, ks_done : std_logic;
type state is (IDLE, KEYSCHEDULE, INITIAL_ROUND, MAIN_ROUND, ENC_OUTPUT);
signal current_state : state := IDLE;
begin
Inst_aes_KeySchedule_FSM : aes_KeySchedule_FSM
port map(
key_in => latched_key_in,
keychain_out => keychain,
start => ks_start,
done => ks_done,
clk => clk,
rst => rst
);
Inst_aes_SubBytes_ShiftRows : aes_SubBytes_ShiftRows
port map(
data_in => ss_data_in,
data_out => ss_data_out,
done => ss_done,
start => ss_start,
clk => clk,
rst => rst
);
Inst_aes_MixColumns : aes_MixColumns
port map(
data_in => mc_data_in,
data_out => mc_data_out,
start => mc_start,
done => mc_done,
clk => clk,
rst => rst
);
state_proc : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
current_state <= IDLE;
for i in 0 to 3 loop
for j in 0 to 3 loop
round_data_in(i, j) <= (others => '0');
round_data_out(i, j) <= (others => '0');
latched_key_in(i, j) <= (others => '0');
round_counter <= 1;
end loop;
end loop;
else
if (start = '1') then
latched_data_in <= data_block_in;
if (key_load = '1') then
latched_key_in <= key_in;
current_state <= KEYSCHEDULE;
else
latched_key_in <= latched_key_in;
current_state <= INITIAL_ROUND;
end if;
else
latched_key_in <= latched_key_in;
current_state <= current_state;
end if;
case current_state is
when IDLE =>
null;
when KEYSCHEDULE =>
if (ks_done = '1') then
current_state <= INITIAL_ROUND;
ks_start <= '0';
else
current_state <= current_state;
ks_start <= '1';
end if;
when INITIAL_ROUND =>
round_key <= keychain(0);
round_data_in <= round_data_out;
round_data_out <= latched_data_in XOR round_key;
current_state <= MAIN_ROUND;
done <= '0';
when MAIN_ROUND =>
round_key <= keychain(round_counter);
if (round_counter = 10) then
ss_data_in <= round_data_in;
round_data_out <= ss_data_in XOR round_data_out;
ss_start <= '1';
if (ss_done = '1') then
current_state <= ENC_OUTPUT;
round_counter <= 1;
else
current_state <= current_state;
end if;
else
ss_data_in <= round_data_in;
mc_data_in <= ss_data_out;
round_data_out <= mc_data_out XOR round_key;
ss_start <= '1';
if (ss_done = '1') then
mc_start <= '1';
else
mc_start <= '0';
end if;
if (mc_done = '1') then
round_counter <= round_counter + 1;
round_data_in <= round_data_out;
end if;
current_state <= current_state;
end if;
done <= '0';
when ENC_OUTPUT =>
done <= '1';
data_block_out <= round_data_out;
current_state <= IDLE;
end case;
end if;
end if;
end process state_proc;
end architecture RTL;
| apache-2.0 |
dm-urievich/afc-smm | software/third-patry/spi_master_slave/trunk/rtl/spi_master_slave/spi_master.vhd | 2 | 43690 | -----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity spi_master is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5); -- for a 100MHz sclk_i, yields a 10MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_master;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert PREFETCH >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert SPI_2X_CLK_DIV > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
begin
if sclk_i'event and sclk_i = '1' then
if clk_cnt = SPI_2X_CLK_DIV-1 then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_ce_gen_proc;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
core_clock_gen_proc : process (sclk_i) is
begin
if sclk_i'event and sclk_i = '1' then
if spi_2x_ce = '1' then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process core_clock_gen_proc;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc: if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc: if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc: if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc: if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc: if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc: if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
end process rx_bit_proc;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D ) is
begin
if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
begin
-- registered data input, input register with clock enable
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if pclk_i'event and pclk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if sclk_i'event and sclk_i = '1' then
if rst_i = '1' then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if sclk_i'event and sclk_i = '1' then
if sck_ena_ce = '1' then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy' and stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_i
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
do_o_proc: do_o <= do_buffer_reg; -- parallel data out
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if sck_ena_reg = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
core_clk_o_proc: core_clk_o <= core_clk;
core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
core_ce_o_proc: core_ce_o <= core_ce;
core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
end architecture rtl;
| apache-2.0 |
dm-urievich/afc-smm | software/third-patry/dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_8.vhd | 2 | 43894 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | apache-2.0 |
mapr/hue | tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
srohrer32/beamformer | hdl/testbench_nearfield.vhd | 1 | 5540 | ----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- This is the testbench used for ISim models --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testbench_nearfield is
generic(
sample_divisor : integer := 11
);
port(
--sys_clock : in std_logic; -- system clk signal
--swt_distance : in std_logic_vector (4 downto 0); -- switch 0 to 4
--but_reset : in std_logic ; --Button D
pin_dataout : out std_logic_vector (7 downto 0); -- JA 0 to 7
pin_channel : out std_logic_vector (4 downto 0); -- JB 0 to 4
--pin_datain_r : in std_logic_vector (7 downto 0); -- JC 0 to 7
--pin_datain_l : in std_logic_vector (7 downto 0); -- JD 0 to 7
--pin_int : in std_logic; -- JB5
pin_speaker_enable : out std_logic; --JB7
pin_rd : out std_logic --JB6
);
end testbench_nearfield;
architecture Behavioral of testbench_nearfield is
--******************* Signal Processing ***************--
component nearfield_processing is
generic(
divisor : integer := 50; -- difference between system clock 1 us
speed_sound : integer := 13397; -- in inches/second
speaker_distance : integer := 2; -- in inches
sample_period : integer := 22
);
port(
i_datain_r : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_datain_l : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_clock : in std_logic; --
i_distance : in std_logic_vector (4 downto 0); -- Switches determine distance
i_reset : in std_logic ; -- To reset the entire system
i_sampleclock : in std_logic ; -- Rate at which the music is playing
o_speaker_enable : out std_logic; --LDAC enable
o_dataout : out std_logic_vector (7 downto 0); -- 8 bit to be multiplexed
o_channel : out std_logic_vector (4 downto 0); -- 5 bit to select which DAC to enable
o_us_clock : out std_logic
);
end component;
--**************** User Signals ***************--
-- To mimic the input ports
signal test_datain_r : std_logic_vector (7 downto 0) := X"00";
signal test_datain_l : std_logic_vector (7 downto 0) := X"00";
signal sys_clock : std_logic;
signal but_reset : std_logic;
signal pin_int : std_logic;
signal swt_distance : std_logic_vector (4 downto 0) :="00000";
-- Normal signals needed
signal clockpulses : integer range 0 to 2200;
signal us_clockpulses : integer range 0 to 12;
signal sample_clock : std_logic;
signal us_clock : std_logic;
signal sig_datain_r : std_logic_vector (7 downto 0);
signal sig_datain_l : std_logic_vector (7 downto 0);
--**************** End User Signals ***********--
begin
--*************** User Processes **************--
but_reset <= '0', '1' after 100 ns, '0' after 1000 ns;
pin_int <= '0';
swt_distance <= "11000";
-- *************** Test Data Being Generated **********--
generate_data: process (sample_clock)
begin
if (rising_edge(sample_clock)) then
test_datain_r <= test_datain_r + X"11";
test_datain_l <= test_datain_l + X"11";
end if;
end process;
-- **************************************************** --
clock: process
begin
sys_clock <= '0';
wait for 5 ns;
sys_clock <= '1';
wait for 5 ns;
end process;
sampleclock_division : process(but_reset, us_clock)
begin
if (but_reset = '1') then
us_clockpulses <= 0;
sample_clock <= '0';
elsif(rising_edge(us_clock)) then
us_clockpulses <= us_clockpulses + 1 ;
if(us_clockpulses = (sample_divisor-1)) then
sample_clock <= Not sample_clock;
us_clockpulses <= 0;
end if;
end if;
end process;
rd_control : process (but_reset, sys_clock, clockpulses, sample_clock)
begin
if (but_reset = '1' ) then
pin_rd <= '1';
clockpulses <= 0;
elsif (rising_edge(sys_clock)) then
clockpulses <= clockpulses + 1;
if (clockpulses = 0) then
pin_rd <= '0';
elsif (clockpulses = 250) then
pin_rd <= '1';
elsif(pin_int = '0') then
sig_datain_r <= test_datain_r;
sig_datain_l <= test_datain_l;
elsif(rising_edge(sample_clock)) then
clockpulses <= 0;
end if;
end if;
end process;
--*************** End User Processes **********--
--**************** Signal Processing Port Map ***********--
fpga : nearfield_processing
generic map(
divisor => 50,
speed_sound => 13397,
speaker_distance => 2,
sample_period => 22
)
port map(
i_datain_r => sig_datain_r,
i_datain_l => sig_datain_l,
i_clock => sys_clock,
i_distance => swt_distance,
i_reset => but_reset,
i_sampleclock => sample_clock,
o_speaker_enable => pin_speaker_enable,
o_dataout => pin_dataout,
o_channel => pin_channel,
o_us_clock => us_clock
);
end Behavioral; | apache-2.0 |
xuefei1/ElectronicEngineControl | electronic_engine_control.vhd | 1 | 8513 |
-- This file is modified from lab1 top level vhdl file provided in eclass
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE0_CONSTANTS.all;
entity electronic_engine_control is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (3 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LED : out DE0_LED_GREEN;
-- SDRAM on board
DRAM_ADDR : out DE0_SDRAM_ADDR_BUS;
DRAM_BA : out DE0_DRAM_BA;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout DE0_SDRAM_DATA_BUS;
DRAM_DQM : out DE0_SDRAM_DQM;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
GPIO_0 : out std_logic_vector (35 downto 0);
GPIO_2 : in std_logic_vector (7 downto 0);
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic
);
end electronic_engine_control;
architecture structure of electronic_engine_control is
-- Declarations (optional)
component niosII_system is
port (
clk_0 : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE0_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE0_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_out : out std_logic; -- clk
out_port_from_the_green_leds : out DE0_LED_GREEN; -- led out
in_port_to_the_switch : in std_logic_vector(3 downto 0) := (others => 'X'); -- export switch
adc_sclk_from_the_de0_nano_adc_0 : out std_logic; -- adc_sclk
adc_cs_n_from_the_de0_nano_adc_0 : out std_logic; -- adc_cs_n
adc_dout_to_the_de0_nano_adc_0 : in std_logic := 'X'; -- adc_dout
adc_din_from_the_de0_nano_adc_0 : out std_logic; -- adc_din
pwm_generator_tps_out_pwm_out_export : out std_logic := '0'; -- pwm_out_tps_val
rs232_0_external_interface_RXD : in std_logic := 'X'; -- RXD
rs232_0_external_interface_TXD : out std_logic; -- TXD
solenoid_out_external_connection_export : out std_logic_vector(7 downto 0) := "00000000"; -- export solenid drivin pins
pwm_generator_throttle_close_pwm_out_export : out std_logic; -- export pwm throttle close
pwm_generator_throttle_open_pwm_out_export : out std_logic; -- export pwm throttle open
buttons_external_connection_export : in std_logic_vector(7 downto 0) := "00000000"; -- export buttons
pwm_generator_test_pwm_out_export : out std_logic; -- export pwm test
curr_gear_out_external_connection_export : out std_logic_vector(1 downto 0); -- export current gear info
pwm_generator_engine_sound_out_pwm_out_export : out std_logic := '0'; -- export pwm engine sound
rpm_pwm_decoder_conduit_end_export : in std_logic := '0' -- export rpm pwm in
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA(1) <= BA(1);
DRAM_BA(0) <= BA(0);
DRAM_DQM(1) <= DQM(1);
DRAM_DQM(0) <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_0 => CLOCK_50,
reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_out => DRAM_CLK,
out_port_from_the_green_leds => LED,
in_port_to_the_switch => SW,
adc_sclk_from_the_de0_nano_adc_0 => ADC_SCLK,
adc_cs_n_from_the_de0_nano_adc_0 => ADC_CS_N,
adc_dout_to_the_de0_nano_adc_0 => ADC_SDAT,
adc_din_from_the_de0_nano_adc_0 => ADC_SADDR,
pwm_generator_test_pwm_out_export => GPIO_0(0),
pwm_generator_throttle_open_pwm_out_export => GPIO_0(8),
pwm_generator_throttle_close_pwm_out_export => GPIO_0(9),
pwm_generator_tps_out_pwm_out_export => GPIO_0(1),
solenoid_out_external_connection_export(2) => GPIO_0(2),
solenoid_out_external_connection_export(3) => GPIO_0(3),
buttons_external_connection_export(2) => GPIO_2(2),
buttons_external_connection_export(3) => GPIO_2(3),
rs232_0_external_interface_TXD => GPIO_0(7),
curr_gear_out_external_connection_export(0) => GPIO_0(10),
curr_gear_out_external_connection_export(1) => GPIO_0(11),
rs232_0_external_interface_RXD => GPIO_2(4),
pwm_generator_engine_sound_out_pwm_out_export => GPIO_0(12),
rpm_pwm_decoder_conduit_end_export => GPIO_2(7)
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE0_CONSTANTS is
type DE0_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE0_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE0_SDRAM_DQM is array(1 downto 0) of std_logic;
type DE0_LED_GREEN is array(7 downto 0) of std_logic;
type DE0_DRAM_BA is array(1 downto 0) of std_logic;
end DE0_CONSTANTS;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_trans/work/transmit_test_model/_primary.vhd | 2 | 496 | library verilog;
use verilog.vl_types.all;
entity transmit_test_model is
port(
clk_100M : in vl_logic;
reset_n : in vl_logic;
Line_Num : out vl_logic_vector(7 downto 0);
Focus_Num : out vl_logic_vector(1 downto 0);
Pr_Gate : out vl_logic;
RX_Gate : out vl_logic;
End_Gate : out vl_logic;
Envelop : out vl_logic
);
end transmit_test_model;
| apache-2.0 |
airhdl/spi-to-axi-bridge | tb/tb_spi2axi_operation.vhd | 1 | 9604 | -------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge, test controller entity declaration
--
-- Description:
-- Normal operation testcase
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
use osvvm.ScoreboardPkg_slv.all;
library osvvm_axi4;
use osvvm_axi4.Axi4OptionsPkg.all;
architecture operation of tb_spi2axi_testctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant SPI_PACKET_LENGTH_BYTES : natural := 11;
-------------------------------------------------------------------------------
-- Aliases
-------------------------------------------------------------------------------
alias TxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
alias RxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
begin
------------------------------------------------------------
-- ControlProc
-- Set up AlertLog and wait for end of test
------------------------------------------------------------
ControlProc : process
procedure spi_process(tx_bytes : integer_vector; rx_bytes : out integer_vector) is
variable num_bytes : integer;
variable valid : boolean;
variable rx_byte : std_logic_vector(7 downto 0);
variable bytes_to_send : integer;
begin
-- Push TX bytes to SPI VC
PushBurst(TxBurstFifo, tx_bytes, 8);
SendBurst(SpiRec, tx_bytes'length);
-- Fetch RX bytes from SPI VC
GetBurst(SpiRec, num_bytes);
AlertIfNot(num_bytes = tx_bytes'length, "unexpected number of received bytes");
for i in 0 to num_bytes - 1 loop
PopWord(RxBurstFifo, valid, rx_byte, bytes_to_send);
AlertIfNot(valid, "invalid receive data");
Log("RX byte: " & to_string(rx_byte), DEBUG);
rx_bytes(i) := to_integer(unsigned(rx_byte));
end loop;
end procedure;
-- Write an AXI4 register over SPI
procedure spi_write(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 0; -- write
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(unsigned(data(i * 8 + 7 downto i * 8)));
tx_byte_idx := tx_byte_idx + 1;
end loop;
tx_bytes(tx_byte_idx) := 0; -- a dummy byte to allow writing the data word
tx_byte_idx := tx_byte_idx + 1;
tx_bytes(tx_byte_idx) := 0; -- AXI4 write response
tx_byte_idx := tx_byte_idx + 1;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
-- Read an AXI4 register over SPI
procedure spi_read(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 1; -- read
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 0 to 5 loop
tx_bytes(tx_byte_idx) := 0; -- don't care
tx_byte_idx := tx_byte_idx + 1;
end loop;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
data(31 downto 24) := std_logic_vector(to_unsigned(rx_bytes(6), 8));
data(23 downto 16) := std_logic_vector(to_unsigned(rx_bytes(7), 8));
data(15 downto 8) := std_logic_vector(to_unsigned(rx_bytes(8), 8));
data(7 downto 0) := std_logic_vector(to_unsigned(rx_bytes(9), 8));
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
variable addr : unsigned(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable mem_reg : std_logic_vector(31 downto 0);
variable status : std_logic_vector(7 downto 0);
alias s_axi_awvalid_mask is << signal .tb_spi2axi.s_axi_awvalid_mask : std_logic >>;
alias s_axi_arvalid_mask is << signal .tb_spi2axi.s_axi_arvalid_mask : std_logic >>;
begin
-- Initialization of test
SetAlertLogName("tb_spi2axi_operation");
SetLogEnable(INFO, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(FindAlertLogID("Axi4LiteMemory"), INFO, FALSE, TRUE);
-- Wait for testbench initialization
wait for 0 ns;
-- Wait for Design Reset
wait until nReset = '1';
ClearAlerts;
SetCPHA(SpiRec, SPI_CPHA);
SetCPOL(SpiRec, SPI_CPOL);
wait for 1 us;
Log("Testing normal SPI write");
addr := x"76543210";
wdata := x"12345678";
spi_write(addr, wdata, status);
AffirmIfEqual(status(2), '0', "timeout");
AffirmIfEqual(status(1 downto 0), "00", "write response");
Read(Axi4MemRec, std_logic_vector(addr), mem_reg);
AffirmIfEqual(mem_reg, wdata, "memory data word");
Log("Testing SPI write with SLVERR response");
addr := x"76543210";
wdata := x"12345678";
SetAxi4Options(Axi4MemRec, BRESP, 2); -- SLVERR
spi_write(addr, wdata, status);
AffirmIfEqual(status(2), '0', "Timeout");
AffirmIfEqual(status(1 downto 0), "10", "Write response");
SetAxi4Options(Axi4MemRec, BRESP, 0);
Log("Testing SPI write timeout");
s_axi_awvalid_mask <= force '0';
addr := x"76543210";
wdata := x"12345678";
spi_write(addr, wdata, status);
AffirmIfEqual('1', status(2), "timeout");
s_axi_awvalid_mask <= release;
Log("Testing normal SPI read");
addr := x"12345678";
wdata := x"12345678";
Write(Axi4MemRec, std_logic_vector(addr), wdata);
spi_read(addr, rdata, status);
AffirmIfEqual(rdata, wdata, "read data");
AffirmIfEqual('0', status(2), "timeout");
AffirmIfEqual("00", status(1 downto 0), "read response");
Log("Testing SPI read with DECERR response");
addr := x"12345678";
wdata := x"12345678";
SetAxi4Options(Axi4MemRec, RRESP, 3); -- DECERR
spi_read(addr, rdata, status);
AffirmIfEqual(rdata, wdata, "read data");
AffirmIfEqual('0', status(2), "timeout");
AffirmIfEqual("11", status(1 downto 0), "read response");
SetAxi4Options(Axi4MemRec, RRESP, 0);
Log("Testing SPI read timeout");
s_axi_arvalid_mask <= force '0';
spi_read(addr, rdata, status);
AffirmIfEqual('1', status(2), "timeout");
s_axi_arvalid_mask <= release;
wait for 1 us;
EndOfTestReports;
std.env.stop;
wait;
end process ControlProc;
end architecture operation;
configuration tb_spi2axi_operation of tb_spi2axi is
for TestHarness
for testctrl_inst : tb_spi2axi_testctrl
use entity work.tb_spi2axi_testctrl(operation);
end for;
end for;
end tb_spi2axi_operation;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_trans/work/lf/_primary.vhd | 2 | 588 | library verilog;
use verilog.vl_types.all;
entity lf is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
ast_sink_error : in vl_logic_vector(1 downto 0);
ast_source_data : out vl_logic_vector(30 downto 0);
ast_sink_ready : out vl_logic;
ast_source_valid: out vl_logic;
ast_source_error: out vl_logic_vector(1 downto 0)
);
end lf;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_rec/work/lf/_primary.vhd | 2 | 588 | library verilog;
use verilog.vl_types.all;
entity lf is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
ast_sink_error : in vl_logic_vector(1 downto 0);
ast_source_data : out vl_logic_vector(30 downto 0);
ast_sink_ready : out vl_logic;
ast_source_valid: out vl_logic;
ast_source_error: out vl_logic_vector(1 downto 0)
);
end lf;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_trans/work/@d@i@v27_19/_primary.vhd | 2 | 387 | library verilog;
use verilog.vl_types.all;
entity DIV27_19 is
port(
clock : in vl_logic;
denom : in vl_logic_vector(34 downto 0);
numer : in vl_logic_vector(42 downto 0);
quotient : out vl_logic_vector(42 downto 0);
remain : out vl_logic_vector(34 downto 0)
);
end DIV27_19;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_rec/work/receive_data_gen/_primary.vhd | 1 | 1037 | library verilog;
use verilog.vl_types.all;
entity receive_data_gen is
port(
clk_50M : in vl_logic;
clk_100M : in vl_logic;
reset_n : in vl_logic;
Data_A : out vl_logic_vector(11 downto 0);
Data_B : out vl_logic_vector(11 downto 0);
Data_C : out vl_logic_vector(11 downto 0);
Data_D : out vl_logic_vector(11 downto 0);
Data_E : out vl_logic_vector(11 downto 0);
Data_F : out vl_logic_vector(11 downto 0);
Data_G : out vl_logic_vector(11 downto 0);
Data_H : out vl_logic_vector(11 downto 0);
Line_Num : out vl_logic_vector(7 downto 0);
Focus_Num : out vl_logic_vector(1 downto 0);
Pr_Gate : out vl_logic;
RX_Gate : out vl_logic;
Sample_Gate : out vl_logic;
End_Gate : out vl_logic
);
end receive_data_gen;
| apache-2.0 |
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_rec/work/receive_top_module_tb/_primary.vhd | 1 | 102 | library verilog;
use verilog.vl_types.all;
entity receive_top_module_tb is
end receive_top_module_tb;
| apache-2.0 |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_wb.vhd | 1 | 1248 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:52 05/21/2017
-- Design Name:
-- Module Name: mux_pc1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_wb is
Port(
regsrc : in STD_LOGIC_VECTOR(1 downto 0);
input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0)
);
end mux_wb;
architecture Behavioral of mux_wb is
begin
process(regsrc)
begin
case regsrc is
when "00"=>output<=input1;
when "01"=>output<=input2;
when others => null;
end case;
end process;
end Behavioral;
| apache-2.0 |
wsoltys/AtomFpga | src/AVR8/spi_mod/spi_slv_sel.vhd | 4 | 2193 | --**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
entity spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end spi_slv_sel;
architecture RTL of spi_slv_sel is
constant SPISlvDcd_Address : integer := PINF_Address;
signal SlvSelRg_Current : std_logic_vector(num_of_slvs-1 downto 0);
signal SlvSelRg_Next : std_logic_vector(num_of_slvs-1 downto 0);
begin
RegWrSeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SlvSelRg_Current <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
SlvSelRg_Current <= SlvSelRg_Next;
end if;
end process;
RegWrComb:process(adr,iowe,dbus_in,SlvSelRg_Current)
begin
SlvSelRg_Next <= SlvSelRg_Current;
if(fn_to_integer(adr)=SPISlvDcd_Address and iowe='1') then
SlvSelRg_Next <= dbus_in(num_of_slvs-1 downto 0);
end if;
end process;
slv_sel_n <= not SlvSelRg_Current(slv_sel_n'range);
out_en <= '1' when (fn_to_integer(adr)=SPISlvDcd_Address and iore='1') else '0';
dbus_out(num_of_slvs-1 downto 0) <= SlvSelRg_Current;
UnusedBits:if(num_of_slvs<8) generate
dbus_out(dbus_out'high downto num_of_slvs) <= (others => '0');
end generate;
end RTL;
| apache-2.0 |
wsoltys/AtomFpga | src/AtomGodilVideo/src/SID/sid_6581.vhd | 1 | 14159 | -------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
signal voice1_signed : signed(12 downto 0);
signal voice2_signed : signed(12 downto 0);
signal voice3_signed : signed(12 downto 0);
constant ext_in_signed : signed(12 downto 0) := to_signed(0,13);
signal filtered_audio : signed(18 downto 0);
signal tick_q1, tick_q2 : std_logic;
signal input_valid : std_logic;
signal unsigned_audio : std_logic_vector(17 downto 0);
signal unsigned_filt : std_logic_vector(18 downto 0);
signal ff1 : std_logic;
-------------------------------------------------------------------------------
begin
digital_to_analog: entity work.pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => unsigned_audio(17 downto 8),
dac_o => audio_out
);
paddle_x: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid <= '1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed("0" & voice_1) - 2048;
voice2_signed <= signed("0" & voice_2) - 2048;
voice3_signed <= signed("0" & voice_3) - 2048;
filters: entity work.sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/adc_pll.vhd | 1 | 18077 | -- megafunction wizard: %Altera PLL v14.0%
-- GENERATION: XML
-- adc_pll.vhd
-- Generated using ACDS version 14.0 200 at 2015.06.18.16:00:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adc_pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic -- outclk1.clk
);
end entity adc_pll;
architecture rtl of adc_pll is
component adc_pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component adc_pll_0002;
begin
adc_pll_inst : component adc_pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
outclk_1 => outclk_1, -- outclk1.clk
locked => open -- (terminated)
);
end architecture rtl; -- of adc_pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="14.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="8" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="240.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="normal" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="false" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="2" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- IPFS_FILES : adc_pll.vho
-- RELATED_FILES: adc_pll.vhd, adc_pll_0002.v
| apache-2.0 |
wsoltys/AtomFpga | src/AVR8/Memory/XPM4Kx16.vhd | 1 | 8512 | --************************************************************************************************
-- 4Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok modified by Jack Gassett for use with Spartan 3E
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM4Kx16;
architecture RTL of XPM4Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C005B940C",
INIT_01 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C007E940C",
INIT_02 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C009D940C",
INIT_03 => X"0404040404040030003600000000003200350038000000000031003700000000",
INIT_04 => X"0804020120100804020180402010080402010303030303030202020202020404",
INIT_05 => X"BFDEE0DFEFCFBE1F241100000000000000000604030000010200070000002010",
INIT_06 => X"07B136A2F3C89631920D95D8C004BF0B9503EF0FE0F3E2ECE0B0E6A0E010BFCD",
INIT_07 => X"0000940C0194940C018D940EF7E107B136AB921DC001E0B0E6A2E010BE1BF7C9",
INIT_08 => X"0151940EE0600060918000F5940EE090E080E070E0610151940EE06100609180",
INIT_09 => X"B60F920F921F95080129940EE06100609180950800F5940EE090E080E070E061",
INIT_0A => X"006791300066912093BF93AF939F938F937F936F935F934F933F932F2411920F",
INIT_0B => X"376D5F6A2F671DB11DA196022F822F932FA42FB5006A91700069915000689140",
INIT_0C => X"93A00067939000669380006A93601DB11DA196032F822F932FA42FB5576DF040",
INIT_0D => X"006293801DB11DA19601006591B0006491A00063919000629180006993B00068",
INIT_0E => X"912F913F914F915F916F917F918F919F91AF91BF006593B0006493A000639390",
INIT_0F => X"914094F8B78F2F192F082EF72EE6931F930F92FF92EF9518901F900FBE0F900F",
INIT_10 => X"006891A0006791900066918094F8B72FBF8F0069917000689160006791500066",
INIT_11 => X"90EF90FF910F911FF760071B070A06F916E80BB70BA60B951B84BF2F006991B0",
INIT_12 => X"2FE84F9F57822F932F82E0302F289508BF876081B787BF836084B78394789508",
INIT_13 => X"5AE01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE24F3F58262D9095C82FF9",
INIT_14 => X"938C2B89918C9508938C23899590918CF42923662DB095C896312DA095C84FFF",
INIT_15 => X"2FE84F9F57822F952F842D2095C82FF92FE84F9F558E2F952F84E0502F489508",
INIT_16 => X"B58FF4193023F0512322F10923332D3095C82FF52FE44F5F58462D9095C82FF9",
INIT_17 => X"96312DA095C84FFF59E81FFF0FEEE0F02FE3BD8F7D8FB58FF4193024C004778F",
INIT_18 => X"940E0121940E9508938C2B89918C9508938C23899590918CF42923662DB095C8",
INIT_19 => X"000000000000000000000000000000000000000DCFFF94F8CFFD0080940E0097",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map(
DO => RAMBlDOut(i)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;
| apache-2.0 |
rauenzi/VHDL-Communications | i2c_master.vhd | 1 | 14232 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
signal data_clk_m : std_logic;
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
busy<='0'; --modified
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
busy <= '1';
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
data_clk_m<=data_clk_prev and data_clk;
WITH state SELECT
sda_ena_n <= data_clk WHEN start, --generate start condition
NOT data_clk_m WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic; | apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/driver/pulse.vhd | 1 | 4889 | --*****************************************************************************
-- @Copyright 2010 by guyoubao, All rights reserved.
-- Module name : Pulse control
-- Call by :
-- Description :
-- IC : EP3C16F484C6
-- Version : A
-- Note: :
-- Author : guyoubao
-- Date : 2010.08.28
-- Update :
-- 160MHz-- 38M peak, 11-68M -6dB
-- O_trig(0-1) -- A1
-- O_trig(14-15) -- A8
--
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port
(
I_clk : in std_logic;
I_reset_n : in std_logic;
I_pulse_trig : in std_logic;
O_pulse : out std_logic_vector(3 downto 0)
);
end pulse;
architecture ARC_pulse of pulse is
signal S_cnt : std_logic_vector(7 downto 0);
signal s_case : std_logic_vector(1 downto 0);
signal s_pulse_buf : std_logic;
signal s_pulse : std_logic_vector(3 downto 0);
begin
O_pulse <= s_pulse;
process(I_reset_n,I_clk)
begin
if I_reset_n = '0' then
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
s_pulse(2) <= '0';
s_pulse_buf <= '0';
elsif rising_edge(I_clk) then
s_pulse_buf <= I_pulse_trig;
case s_case is
when "00" =>
if(s_pulse_buf = '0' and I_pulse_trig = '1')then --rise
s_case <= "01";
S_cnt <= S_cnt + '1';
else
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '0';
s_pulse(2) <= '0';
end if;
when "01" => -- 60M时钟，5M发射，6个N6个P6个拉回零，可结合TC8220的发射时序，6个N+6个P=12个周期，60/12=5M，即为发射频率。
S_cnt <= S_cnt + '1';
if(S_cnt >= 5 and S_cnt <= 10)then
s_pulse(0) <= '1';
else
s_pulse(0) <= '0';
end if;
if(S_cnt >= 11 and S_cnt <= 16)then --monocycle, positive first
s_pulse(1) <= '1';
else
s_pulse(1) <= '0';
end if;
if(S_cnt >= 17 and S_cnt <= 22)then
s_pulse(2) <= '1';
else
s_pulse(2) <= '0';
end if;
if(S_cnt = 0)then
s_case <= (others=>'0');
end if;
when others =>
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '0';
s_pulse(2) <= '0';
end case;
end if;
end process;
--process(I_reset,I_clk)
--begin
-- if I_reset = '0' then
-- s_case <= (others=>'0');
-- S_cnt <= (others=>'0');
-- s_pulse(0) <= '0';
-- s_pulse(1) <= '1';
-- s_pulse_buf <= '0';
-- elsif rising_edge(I_clk) then
--
-- s_pulse_buf <= I_pulse_trig;
--
-- case s_case is
-- when "00" =>
-- if(s_pulse_buf = '0' and I_pulse_trig = '1')then
-- s_case <= "01";
-- S_cnt <= S_cnt + '1';
-- else
-- s_case <= (others=>'0');
-- S_cnt <= (others=>'0');
-- s_pulse(0) <= '0';
-- s_pulse(1) <= '1';
-- end if;
--
-- when "01" =>
-- S_cnt <= S_cnt + '1';
-- if(S_cnt >= 4 and S_cnt <= 5)then --monocycle, positive first 35MHz at 300MHz clk
-- s_pulse(1) <= '0';
-- else
-- s_pulse(1) <= '1';
-- end if;
--
-- if(S_cnt >= 2 and S_cnt <= 3)then
-- s_pulse(0) <= '1';
-- else
-- s_pulse(0) <= '0';
-- end if;
--
-- if(S_cnt = 0)then
-- s_case <= (others=>'0');
-- end if;
--
-- when others =>
-- s_case <= (others=>'0');
-- S_cnt <= (others=>'0');
-- s_pulse(0) <= '0';
-- s_pulse(1) <= '1';
--
-- end case;
--
-- end if;
--end process;
end ARC_pulse; | apache-2.0 |
yansyaf/cmake-verilog-vhdl-fpga-template | src/xilinx/fifo.vhd | 2 | 10044 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synthesis translate_off
COMPONENT wrapped_fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 1022,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1021,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END fifo_a;
| apache-2.0 |
wsoltys/AtomFpga | src/AtomGodilVideo/src/mouse/mouse_controller.vhd | 1 | 42573 | ------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zolt�n
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller is a client for the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- read - input pin, from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - input pin, from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - input pin, 8 bits, from ps2interface
-- - the byte received from the mouse.
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
-- tx_data - output pin, 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write - output pin, to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
--use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity mouse_controller is
port(
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end mouse_controller;
architecture Behavioral of mouse_controller is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(9 downto 0) := "1001111111";
-- 639
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(9 downto 0) := "0111011111";
-- 479
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(10 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max,y_max: std_logic_vector(9 downto 0) := (others => '0');
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
begin
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(9 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(9 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= '0' & value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended x_inc
inc := "111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(10) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended x_inc
inc := "000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= '0' & x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= '0' & value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended y_inc
inc := "111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(10) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended y_inc
inc := "000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > ('0' & y_max)) then
y_pos <= '0' & y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral; | apache-2.0 |
ntb-ch/pathos | FPGA/EIMBusToggle/src/pintoggler.vhd | 1 | 2049 | library ieee;
use ieee.std_logic_1164.all;
entity pintoggler is
port (
clk_50 : in std_logic;
data : out std_logic_vector(15 downto 0);
addr : out std_logic_vector(15 downto 0);
div : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of pintoggler is
signal counter : integer := 0;
signal toggler : std_logic_vector(15 downto 0) := (others => '0');
constant clk_ticks : integer := 5000000;
begin
data <= toggler;
addr <= toggler;
count: process (clk_50)
begin
if (rising_edge(clk_50)) then
if ((counter mod clk_ticks) = 0) then toggler(0) <= not toggler(0); end if;
if ((counter mod (clk_ticks/2)) = 0) then toggler(1) <= not toggler(1); end if;
if ((counter mod (clk_ticks/4)) = 0) then toggler(2) <= not toggler(2); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(3) <= not toggler(3); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(4) <= not toggler(4); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(5) <= not toggler(5); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(6) <= not toggler(6); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(7) <= not toggler(7); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(8) <= not toggler(8); end if;
if ((counter mod (clk_ticks/512)) = 0) then toggler(9) <= not toggler(9); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(10) <= not toggler(10); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(11) <= not toggler(11); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(12) <= not toggler(12); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(13) <= not toggler(13); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(14) <= not toggler(14); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(15) <= not toggler(15); end if;
if (counter > clk_ticks) then
counter <= 0;
else
counter <= (counter + 1);
end if;
end if;
end process;
end architecture;
| apache-2.0 |
wsoltys/AtomFpga | src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd | 4 | 3224 | --**********************************************************************************************
-- Constants for OCD and "Flash" controller for AVR Core
-- Version 0.31
-- Modified 04.06.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGPack is
constant CInstrLength : positive := 4;
-- JTAG instructions
constant C_BYPASS : std_logic_vector(CInstrLength-1 downto 0) := x"F";
constant C_SAMPLE_PRELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"2";
constant C_EXTEST : std_logic_vector(CInstrLength-1 downto 0) := x"0";
constant C_IDCODE : std_logic_vector(CInstrLength-1 downto 0) := x"1";
constant C_AVR_RESET : std_logic_vector(CInstrLength-1 downto 0) := x"C";
-- Program
constant C_PROG_ENABLE : std_logic_vector(CInstrLength-1 downto 0) := x"4";
constant C_PROG_COMMANDS : std_logic_vector(CInstrLength-1 downto 0) := x"5";
constant C_PROG_PAGELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"6";
constant C_PROG_PAGEREAD : std_logic_vector(CInstrLength-1 downto 0) := x"7";
-- OCD (Private)
constant C_FORCE_BREAK : std_logic_vector(CInstrLength-1 downto 0) := x"8";
constant C_RUN : std_logic_vector(CInstrLength-1 downto 0) := x"9";
constant C_EX_INST : std_logic_vector(CInstrLength-1 downto 0) := x"A";
constant C_OCD_ACCESS : std_logic_vector(CInstrLength-1 downto 0) := x"B";
constant C_UNUSED_3 : std_logic_vector(CInstrLength-1 downto 0) := x"3";
constant C_UNUSED_D : std_logic_vector(CInstrLength-1 downto 0) := x"D";
constant C_UNUSED_E : std_logic_vector(CInstrLength-1 downto 0) := x"E";
constant CInitInstrRegVal : std_logic_vector(CInstrLength-1 downto 0) := C_IDCODE; -- May be C_IDCODE or C_BYPASS
-- IDCODE register fields
--constant CVersion : std_logic_vector(3 downto 0) := x"E"; -- Version Number (ATmega16)
--constant CPartNumber : std_logic_vector(15 downto 0) := x"9403"; -- Part Number (ATmega16)
constant CVersion : std_logic_vector(3 downto 0) := x"6"; -- Version Number (ATmega128)
constant CPartNumber : std_logic_vector(15 downto 0) := x"9702"; -- Part Number (ATmega128)
constant CManufacturerId : std_logic_vector(10 downto 0) := "000"&x"1F"; -- Manufacturer ID(Atmel)
constant C_ProgEnableVect : std_logic_vector(15 downto 0) := x"A370";
-- OCD register addresses
constant C_OCDPSB0Adr : std_logic_vector(3 downto 0) := x"0";
constant C_OCDPSB1Adr : std_logic_vector(3 downto 0) := x"1";
constant C_OCDPDMSBAdr : std_logic_vector(3 downto 0) := x"2";
constant C_OCDPDSBAdr : std_logic_vector(3 downto 0) := x"3";
constant C_OCDBCRAdr : std_logic_vector(3 downto 0) := x"8";
constant C_OCDBSRAdr : std_logic_vector(3 downto 0) := x"9";
constant C_OCDOCDRAdr : std_logic_vector(3 downto 0) := x"C";
constant C_OCDCSRAdr : std_logic_vector(3 downto 0) := x"D";
constant C_AVRBreakInst : std_logic_vector(15 downto 0) := x"9598";
constant C_MaxEraseAdr : std_logic_vector(15 downto 0) := x"FFFF";
end JTAGPack;
| apache-2.0 |
its2mc/PCFG | buffer.vhd | 1 | 374 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity buffer is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC);
end buffer;
architecture Behavioral of buffer is
begin
dout <= din when (en='0') else
"ZZZZZZZZ" when (en='1') else
"ZZZZZZZZ";
end Behavioral;
| apache-2.0 |
its2mc/PCFG | mux_4.vhd | 1 | 613 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4 is
Port ( din0 : in STD_LOGIC_VECTOR (7 downto 0);
din1 : in STD_LOGIC_VECTOR (7 downto 0);
din2 : in STD_LOGIC_VECTOR (7 downto 0);
din3 : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0));
end mux_4;
architecture Behavioral of mux_4 is
begin
dout <= din0 when (sel="00") else
din1 when (sel="01") else
din2 when (sel="10") else
din3 when (sel="11") else
"XXXXXXXX";
end Behavioral; | apache-2.0 |
its2mc/PCFG | addr_decoder.vhd | 1 | 1360 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addr_decoder is
Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
pcs_addr : out STD_LOGIC;
reset_addr : out STD_LOGIC;
pc_ram0_addr : out STD_LOGIC;
pc_ram1_addr : out STD_LOGIC;
data_transfer_addr : out STD_LOGIC;
da_start_addr : out STD_LOGIC;
da_stop_addr : out STD_LOGIC;
ad_ram0_addr : out STD_LOGIC;
multiplication_addr : out STD_LOGIC);
end addr_decoder;
architecture Behavioral of addr_decoder is
begin
pcs_addr <= '1' when (addr = "01000000") else
'1' when (addr = "01000001") else
'1' when (addr = "01000010") else
'1' when (addr = "01000011") else
'0';
reset_addr <= '1' when (addr = "10000000") else
'0';
pc_ram0_addr <= '1' when (addr = "10000010") else
'0';
pc_ram1_addr <= '1' when (addr = "10000100") else
'0';
data_transfer_addr <= '1' when (addr = "01100000") else
'0';
da_start_addr <= '1' when (addr = "01100010") else
'0';
da_stop_addr <= '1' when (addr = "01100100") else
'0';
ad_ram0_addr <= '1' when (addr = "01100110") else
'0';
multiplication_addr <= '1' when (addr = "01110000") else
'0';
end Behavioral;
| apache-2.0 |
its2mc/PCFG | pcfg/downCounter.vhd | 1 | 1408 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:32:46 11/21/2016
-- Design Name:
-- Module Name: downCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module will down count to 0 from 8. Initial value is 8
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity downCounter is
Port ( reset : in STD_LOGIC;
tc : out STD_LOGIC;
cs : in STD_LOGIC;
count_en : in STD_LOGIC);
end downCounter;
architecture Behavioral of downCounter is
shared variable counter: std_logic_vector:= "1000";
begin
main: process (cs,reset,count_en)
begin
if reset='1' then
tc<='0';
counter := "1000";
elsif clk ='1' and clk'event then
if(counter="0000") then
tc <= '1';
counter:="1000";
else
counter := counter or "1111";
end if;
end if;
end process;
end Behavioral;
| apache-2.0 |
open-power/snap | actions/hdl_example/hw/action_axi_slave.vhd | 1 | 25493 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016,2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity action_axi_slave is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
reg_0x10_i : in std_logic_vector(31 downto 0);
reg_0x14_i : in std_logic_vector(31 downto 0);
reg_0x20_o : out std_logic_vector(31 downto 0);
reg_0x30_o : out std_logic_vector(31 downto 0);
reg_0x34_o : out std_logic_vector(31 downto 0);
reg_0x38_o : out std_logic_vector(31 downto 0);
reg_0x3c_o : out std_logic_vector(31 downto 0);
reg_0x40_o : out std_logic_vector(31 downto 0);
reg_0x44_o : out std_logic_vector(31 downto 0);
int_enable_o : out std_logic;
app_start_o : out std_logic;
app_done_i : in std_logic;
app_ready_i : in std_logic;
app_idle_i : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- -- Write channel Protection type. This signal indicates the
-- -- privilege and security level of the transaction, and whether
-- -- the transaction is a data access or an instruction access.
-- S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- -- Protection type. This signal indicates the privilege
-- -- and security level of the transaction, and whether the
-- -- transaction is a data access or an instruction access.
-- S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end action_axi_slave;
architecture action_axi_slave of action_axi_slave is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 5;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 16
signal slv_reg0 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg0_new : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal idle_q : std_logic;
signal app_start_q : std_logic;
signal app_done_q : std_logic;
signal slv_reg0_bit0_q : std_logic;
begin
-- I/O Connections assignments
int_enable_o <= slv_reg1(0);
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg8 <= slv_reg8;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
end case;
end if;
if app_start_q = '1' then
slv_reg0(0) <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0_new, slv_reg1, slv_reg2, slv_reg3, reg_0x10_i, reg_0x14_i, slv_reg8, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, axi_araddr)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0_new; -- 0x00
when b"00001" =>
reg_data_out <= slv_reg1; -- 0x04
when b"00010" =>
reg_data_out <= slv_reg2; -- 0x08
when b"00011" =>
reg_data_out <= slv_reg3; -- 0x0c
when b"00100" =>
reg_data_out <= reg_0x10_i; -- 0x10
when b"00101" =>
reg_data_out <= reg_0x14_i; -- 0x14
when b"01000" =>
reg_data_out <= slv_reg8; -- 0x20
when b"01100" =>
reg_data_out <= slv_reg12; -- 0x30
when b"01101" =>
reg_data_out <= slv_reg13; -- 0x34
when b"01110" =>
reg_data_out <= slv_reg14; -- 0x38
when b"01111" =>
reg_data_out <= slv_reg15; -- 0x3c
when b"10000" =>
reg_data_out <= slv_reg16; -- 0x40
when b"10001" =>
reg_data_out <= slv_reg17; -- 0x44
when b"10010" =>
reg_data_out <= slv_reg18; -- 0x48
when b"10011" =>
reg_data_out <= slv_reg19; -- 0x4c
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Reiner
app_start_o <= app_start_q;
reg_0x20_o <= slv_reg8;
reg_0x30_o <= slv_reg12;
reg_0x34_o <= slv_reg13;
reg_0x38_o <= slv_reg14;
reg_0x3c_o <= slv_reg15;
reg_0x40_o <= slv_reg16;
reg_0x44_o <= slv_reg17;
process( S_AXI_ACLK ) is
variable app_done_i_q : std_logic;
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0);
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
app_start_q <= '0';
app_done_q <= '0';
app_done_i_q := '0';
slv_reg0_bit0_q <= '0';
idle_q <= '0';
else
idle_q <= app_idle_i;
slv_reg0_bit0_q <= slv_reg0(0);
app_done_i_q := app_done_i;
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB);
-- clear ap_done bit when register is read
if slv_reg_rden = '1'and loc_addr = "00000" then
app_done_q <= '0';
end if;
if (app_done_i_q = '0' and app_done_i = '1') then
app_done_q <= '1';
end if;
if slv_reg0_bit0_q = '0' and slv_reg0(0) = '1' then
app_start_q <= '1';
end if;
if idle_q = '1' and app_idle_i = '0' then
app_start_q <= '0';
end if;
end if;
end if;
end process;
slv_reg0_new <= slv_reg0 (31 downto 4) & app_ready_i & idle_q & app_done_q & app_start_q ;
-- User logic ends
end action_axi_slave;
| apache-2.0 |
open-power/snap | actions/hdl_example/hw/action_axi_master.vhd | 1 | 12078 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity action_axi_master is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Thread ID Width
C_M_AXI_ID_WIDTH : integer := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : integer := 64;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : integer := 512;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : integer := 0;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : integer := 0;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : integer := 0;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : integer := 0;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
dma_rd_req_i : in std_logic;
dma_rd_addr_i : in std_logic_vector(C_M_AXI_ADDR_WIDTH -1 downto 0);
dma_rd_len_i : in std_logic_vector( 7 downto 0);
dma_rd_req_ack_o : out std_logic;
dma_rd_data_o : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
dma_rd_data_valid_o : out std_logic;
dma_rd_data_last_o : out std_logic;
dma_rd_data_taken_i : in std_logic;
dma_rd_context_id : in std_logic_vector(C_M_AXI_ARUSER_WIDTH - 1 downto 0);
dma_wr_req_i : in std_logic;
dma_wr_addr_i : in std_logic_vector( C_M_AXI_ADDR_WIDTH - 1 downto 0);
dma_wr_len_i : in std_logic_vector( 7 downto 0);
dma_wr_req_ack_o : out std_logic;
dma_wr_data_i : in std_logic_vector(C_M_AXI_DATA_WIDTH -1 downto 0);
dma_wr_data_strobe_i: in std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
dma_wr_data_last_i : in std_logic;
dma_wr_ready_o : out std_logic;
dma_wr_bready_i : in std_logic;
dma_wr_done_o : out std_logic;
dma_wr_context_id : in std_logic_vector(C_M_AXI_AWUSER_WIDTH - 1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end action_axi_master;
architecture action_axi_master of action_axi_master is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
function or_reduce (signal arg : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for i in arg'low to arg'high loop
result := result or arg(i);
end loop; -- i
return result;
end or_reduce;
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
signal axi_awlen : std_logic_vector(7 downto 0);
signal axi_arlen : std_logic_vector(7 downto 0);
signal wr_req_wait_cycle : std_logic;
signal rd_req_wait_cycle : std_logic;
signal rd_req_ack : std_logic;
signal wr_req_ack : std_logic;
begin
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= axi_awaddr;
M_AXI_AWLEN <= axi_awlen;
M_AXI_AWSIZE <= std_logic_vector( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= (others => '0');
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= dma_wr_context_id;
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= axi_wstrb;
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARLEN <= axi_arlen;
M_AXI_ARSIZE <= std_logic_vector( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= (others => '0');
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= dma_rd_context_id;
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
axi_w: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
dma_wr_req_ack_o <= '0';
dma_wr_done_o <= '0';
if M_AXI_ARESETN = '0' then
axi_awvalid <= '0';
axi_bready <= '0';
wr_req_wait_cycle <= '0';
else
wr_req_wait_cycle <= '0';
if dma_wr_req_i = '1' and wr_req_wait_cycle = '0' then
axi_awaddr <= dma_wr_addr_i;
axi_awlen <= dma_wr_len_i;
axi_awvalid <= '1';
end if;
if axi_awvalid = '1' and M_AXI_AWREADY = '1' then
dma_wr_req_ack_o <= '1';
axi_awvalid <= '0';
wr_req_wait_cycle <= '1';
end if;
axi_bready <= dma_wr_bready_i;
if M_AXI_BVALID = '1' then
dma_wr_done_o <= '1';
end if;
end if;
end if;
end process;
axi_rready <= dma_rd_data_taken_i;
dma_rd_data_last_o <= M_AXI_RLAST;
dma_rd_data_valid_o <= M_AXI_RVALID;
dma_rd_data_o <= M_AXI_RDATA;
axi_write_buffer:
process(M_AXI_ACLK,M_AXI_WREADY, axi_wvalid )
begin
if (rising_edge (M_AXI_ACLK)) then
if M_AXI_ARESETN = '0' then
axi_wvalid <= '0';
else
if M_AXI_WREADY = '1' or axi_wvalid = '0' then
axi_wdata <= dma_wr_data_i;
axi_wvalid <= or_reduce(dma_wr_data_strobe_i);
axi_wstrb <= dma_wr_data_strobe_i;
axi_wlast <= dma_wr_data_last_i;
end if;
end if;
end if;
dma_wr_ready_o <= '1';
if M_AXI_WREADY = '0' and axi_wvalid = '1' then
dma_wr_ready_o <= '0';
end if;
end process;
axi_r: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
dma_rd_req_ack_o <= '0';
if (M_AXI_ARESETN = '0' ) then
axi_arvalid <= '0';
rd_req_wait_cycle <= '0';
else
rd_req_wait_cycle <= '0';
if dma_rd_req_i = '1' and rd_req_wait_cycle = '0' then
axi_arvalid <= '1';
axi_araddr <= dma_rd_addr_i;
axi_arlen <= dma_rd_len_i;
end if;
if axi_arvalid = '1' and M_AXI_ARREADY = '1' then
axi_arvalid <= '0';
dma_rd_req_ack_o <= '1';
rd_req_wait_cycle <= '1';
end if;
end if;
end if;
end process;
end action_axi_master;
| apache-2.0 |
VLSI-EDA/PoC-Examples | src/mem/sdram/memtest_de0.vhdl | 1 | 7478 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory Controller Test for Altera DE0 Board
--
-- Description:
-- ------------------------------------
-- Top-Level of Memory Controller Test for Altera DE0 Board
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.fifo.all;
entity memtest_de0 is
port (
clk_in : in std_logic;
btn : in std_logic_vector(2 downto 2);
led : out std_logic_vector(9 downto 0);
sd_ck : out std_logic;
sd_cke : out std_logic;
sd_cs : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sd_we : out std_logic;
sd_ba : out std_logic_vector(1 downto 0);
sd_a : out std_logic_vector(11 downto 0);
sd_ldm : out std_logic;
sd_udm : out std_logic;
sd_dq : inout std_logic_vector(15 downto 0));
end memtest_de0;
architecture rtl of memtest_de0 is
signal clk_sys : std_logic;
signal clk_mem : std_logic;
signal clk_memout : std_logic;
signal rst_sys : std_logic;
signal rst_mem : std_logic;
signal locked : std_logic;
signal clk_tb : std_logic;
signal rst_tb : std_logic;
signal cf_put : std_logic;
signal cf_full : std_logic;
signal cf_din : std_logic_vector(22 downto 0);
signal cf_dout : std_logic_vector(22 downto 0);
signal cf_valid : std_logic;
signal cf_got : std_logic;
signal wf_put : std_logic;
signal wf_full : std_logic;
signal wf_din : std_logic_vector(15 downto 0);
signal wf_dout : std_logic_vector(15 downto 0);
signal wf_valid : std_logic;
signal wf_got : std_logic;
signal mem_rdy : std_logic;
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(15 downto 0);
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(21 downto 0);
signal mem_wdata : std_logic_vector(15 downto 0);
signal fsm_status : std_logic_vector(2 downto 0);
signal rf_put : std_logic;
signal rf_din : std_logic_vector(15 downto 0);
begin -- rtl
pll: entity work.memtest_de0_pll
port map (
inclk0 => clk_in,
c0 => clk_sys,
c1 => clk_mem,
c2 => clk_memout,
locked => locked);
rst_sync : block
signal do_rst : std_logic;
signal rst_sys_r : std_logic_vector(4 downto 0);
signal rst_mem_r : std_logic_vector(4 downto 0);
begin -- block clockgen
-- reset synchronizer
do_rst <= not locked or not btn(2);
rst_sys_r <= rst_sys_r(rst_sys_r'left-1 downto 0) & do_rst
when rising_edge(clk_sys);
rst_mem_r <= rst_mem_r(rst_mem_r'left-1 downto 0) & do_rst
when rising_edge(clk_mem);
rst_sys <= rst_sys_r(rst_sys_r'left);
rst_mem <= rst_mem_r(rst_mem_r'left);
end block rst_sync;
-- Testbench clock selection
-- Also update chipscope configuration.
-- clk_tb <= clk_mem;
-- rst_tb <= rst_mem;
clk_tb <= clk_sys;
rst_tb <= rst_sys;
-- uses default configuration, see entity declaration
mem_ctrl: entity poc.sdram_ctrl_de0
generic map (
CLK_PERIOD => 7.5,
CL => 2,
BL => 1)
port map (
clk => clk_mem,
clkout => clk_memout,
rst => rst_mem,
user_cmd_valid => cf_valid,
user_wdata_valid => wf_valid,
user_write => cf_dout(cf_dout'left),
user_addr => cf_dout(cf_dout'left-1 downto 0),
user_wdata => wf_dout,
user_got_cmd => cf_got,
user_got_wdata => wf_got,
user_rdata => rf_din,
user_rstb => rf_put,
sd_ck => sd_ck,
sd_cke => sd_cke,
sd_cs => sd_cs,
sd_ras => sd_ras,
sd_cas => sd_cas,
sd_we => sd_we,
sd_ba => sd_ba,
sd_a => sd_a,
sd_dq => sd_dq);
sd_ldm <= '0';
sd_udm <= '0';
cmd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 23,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => cf_put,
din => cf_din,
full => cf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => cf_got,
valid => cf_valid,
dout => cf_dout);
wr_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => wf_put,
din => wf_din,
full => wf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => wf_got,
valid => wf_valid,
dout => wf_dout);
-- The size fo this FIFO depends on the latency between write and read
-- clock domain
rd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_mem,
rst_wr => rst_mem,
put => rf_put,
din => rf_din,
full => open, -- can't stall
clk_rd => clk_tb,
rst_rd => rst_tb,
got => mem_rstb,
valid => mem_rstb,
dout => mem_rdata);
fsm: entity work.memtest_fsm
generic map (
A_BITS => 22,
D_BITS => 16)
port map (
clk => clk_tb,
rst => rst_tb,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => fsm_status);
-- Signal mem_ctrl ready only if both FIFOs are not full.
mem_rdy <= cf_full nor wf_full;
-- Word aligned access to memory.
-- Parallel "put" to both FIFOs.
cf_put <= mem_req and mem_rdy;
wf_put <= mem_req and mem_write and mem_rdy;
cf_din <= mem_write & std_logic_vector(mem_addr);
wf_din <= mem_wdata;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
led(9) <= locked;
led(8 downto 3) <= (others => '0');
led(2 downto 0) <= fsm_status;
end rtl;
| apache-2.0 |
VLSI-EDA/PoC-Examples | src/common/my_config_VC707.vhdl | 1 | 1787 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx VC707 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
| apache-2.0 |
VLSI-EDA/PoC-Examples | src/common/my_config_KC705.vhdl | 1 | 1790 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx KC705 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
| apache-2.0 |
VLSI-EDA/PoC-Examples | src/io/FanControl/top_FanControl_ML605.vhdl | 1 | 7206 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Top-Module: FanControl example design for a ML605 board
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library PoC;
use PoC.physical.all;
entity top_FanControl_ML605 is
port (
ML605_SystemClock_200MHz_p : in STD_LOGIC;
ML605_SystemClock_200MHz_n : in STD_LOGIC;
ML605_GPIO_LED : out STD_LOGIC_VECTOR(7 downto 0);
ML605_FanControl_PWM : out STD_LOGIC;
ML605_FanControl_Tacho : in STD_LOGIC
);
end entity;
architecture top of top_FanControl_ML605 is
attribute KEEP : BOOLEAN;
-- ===========================================================================
-- configurations
-- ===========================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant SYS_CLOCK_FREQ : FREQ := 200 MHz;
-- ClockNetwork configuration
-- ===========================================================================
constant SYSTEM_CLOCK_FREQ : FREQ := SYS_CLOCK_FREQ / 2;
-- ===========================================================================
-- signal declarations
-- ===========================================================================
-- clock and reset signals
signal System_RefClock_200MHz : STD_LOGIC;
signal ClkNet_Reset : STD_LOGIC;
signal ClkNet_ResetDone : STD_LOGIC;
signal SystemClock_200MHz : STD_LOGIC;
signal SystemClock_100MHz : STD_LOGIC;
signal SystemClock_Stable_200MHz : STD_LOGIC;
signal SystemClock_Stable_100MHz : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_Reset : STD_LOGIC;
attribute KEEP of System_Clock : signal is TRUE;
attribute KEEP of System_Reset : signal is TRUE;
begin
-- ===========================================================================
-- assert statements
-- ===========================================================================
assert FALSE report "FanControl configuration:" severity NOTE;
assert FALSE report " SYS_CLOCK_FREQ: " & to_string(SYS_CLOCK_FREQ, 3) severity note;
-- ===========================================================================
-- Input/output buffers
-- ===========================================================================
IBUFGDS_SystemClock : IBUFGDS
port map (
I => ML605_SystemClock_200MHz_p,
IB => ML605_SystemClock_200MHz_n,
O => System_RefClock_200MHz
);
-- ==========================================================================================================================================================
-- ClockNetwork
-- ==========================================================================================================================================================
ClkNet_Reset <= '0';
ClkNet : entity PoC.clknet_ClockNetwork_ML605
generic map (
CLOCK_IN_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockIn_200MHz => System_RefClock_200MHz,
ClockNetwork_Reset => ClkNet_Reset,
ClockNetwork_ResetDone => ClkNet_ResetDone,
Control_Clock_200MHz => open,
Clock_250MHz => open,
Clock_200MHz => SystemClock_200MHz,
Clock_125MHz => open,
Clock_100MHz => SystemClock_100MHz,
Clock_10MHz => open,
Clock_Stable_250MHz => open,
Clock_Stable_200MHz => SystemClock_Stable_200MHz,
Clock_Stable_125MHz => open,
Clock_Stable_100MHz => SystemClock_Stable_100MHz,
Clock_Stable_10MHz => open
);
-- system signals
System_Clock <= SystemClock_100MHz;
System_Reset <= not SystemClock_Stable_100MHz;
-- ==========================================================================================================================================================
-- General Purpose I/O
-- ==========================================================================================================================================================
blkGPIO : block
signal GPIO_LED : STD_LOGIC_VECTOR(7 downto 0);
signal GPIO_LED_d : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
GPIO_LED <= "0000000" & ClkNet_ResetDone;
GPIO_LED_d <= GPIO_LED when rising_edge(System_Clock);
ML605_GPIO_LED <= GPIO_LED_d;
end block;
-- ==========================================================================================================================================================
-- Fan Control
-- ==========================================================================================================================================================
blkFanControl : block
signal FanControl_PWM : STD_LOGIC;
signal FanControl_PWM_d : STD_LOGIC := '0';
signal FanControl_Tacho_async : STD_LOGIC;
signal FanControl_Tacho_sync : STD_LOGIC;
begin
FanControl_Tacho_async <= ML605_FanControl_Tacho;
sync : entity PoC.sync_Bits
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => FanControl_Tacho_async, -- Data to be synchronized
Output(0) => FanControl_Tacho_sync -- synchronized data
);
Fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ -- 100 MHz
)
port map (
Clock => System_Clock,
Reset => System_Reset,
Fan_PWM => FanControl_PWM,
Fan_Tacho => FanControl_Tacho_sync,
TachoFrequency => open
);
-- IOB-FF
FanControl_PWM_d <= FanControl_PWM when rising_edge(System_Clock);
ML605_FanControl_PWM <= FanControl_PWM_d;
end block;
end architecture;
| apache-2.0 |
VLSI-EDA/PoC-Examples | tb/mem/mem_model.vhdl | 1 | 5008 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Model of pipelined memory with "mem" interface.
--
-- Description:
-- ------------------------------------
-- To be used for simulation as a replacement for a real memory controller.
--
-- Generic parameters:
--
-- * A_BITS: number of word address bits.
-- * D_BTIS: width of data bus.
-- * LATENCY: the latency of the pipelined read.
--
-- License:
-- ============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
-------------------------------------------------------------------------------
-- Naming Conventions:
-- (Based on: Keating and Bricaud: "Reuse Methodology Manual")
--
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: all UPPERCASE
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- output of a register: "*_r"
-- asynchronous signal: "*_a"
-- pipelined or register delay signals: "*_p#"
-- data before being registered into register with the same name: "*_nxt"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- tristate internal signal "*_z"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_model is
generic (
A_BITS : positive;
D_BITS : positive;
LATENCY : positive
);
port (
clk : in std_logic;
rst : in std_logic;
mem_req : in std_logic;
mem_write : in std_logic;
mem_addr : in unsigned(A_BITS-1 downto 0);
mem_wdata : in std_logic_vector(D_BITS-1 downto 0);
mem_rdy : out std_logic;
mem_rstb : out std_logic;
mem_rdata : out std_logic_vector(D_BITS-1 downto 0));
end entity mem_model;
architecture sim of mem_model is
-- data types
type RAM_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal ram : RAM_T(0 to 2**A_BITS-1);
-- read pipeline
type RDATA_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal rdata_p : RDATA_T(1 to LATENCY);
signal rstb_p : std_logic_vector(1 to LATENCY) := (others => '0');
-- ready control logic
type FSM_TYPE is (RESET, READY);
signal fsm_cs : FSM_TYPE;
begin -- architecture sim
-- TODO: implement some logic / FSM which introduces wait states
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
fsm_cs <= RESET;
else
fsm_cs <= READY;
end if;
end if;
end process;
-- Memory and Read Pipeline
process(clk)
begin
if rising_edge(clk) then
rstb_p(1) <= '0'; -- default
-- access memory only when ready, ignore requests otherwise
if fsm_cs = READY then
if mem_req = '1' then
if mem_write = '1' then
if Is_X(std_logic_vector(mem_addr)) then
report "Invalid address during write." severity error;
else
ram(to_integer(mem_addr)) <= mem_wdata;
end if;
elsif mem_write = '0' then -- read
if Is_X(std_logic_vector(mem_addr)) then
report "Invalid address during read." severity error;
else
rdata_p(1) <= ram(to_integer(mem_addr));
rstb_p(1) <= '1';
end if;
else
report "Invalid write/read command." severity error;
end if;
elsif mem_req /= '0' then
report "Invalid request." severity error;
end if;
end if;
-- read pipeline
if LATENCY > 1 then
rstb_p (2 to LATENCY) <= rstb_p (1 to LATENCY-1);
rdata_p(2 to LATENCY) <= rdata_p(1 to LATENCY-1);
end if;
-- reset only read strobe
if rst = '1' then
rstb_p <= (others => '0');
end if;
end if;
end process;
-- Read Pipeline
--gReadPipe: if LATENCY > 1 generate
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- end if;
-- end process;
--end generate gReadPipe;
-- Outputs
mem_rdy <= '1' when fsm_cs = READY else '0';
mem_rdata <= rdata_p(LATENCY);
mem_rstb <= rstb_p (LATENCY);
end architecture sim;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/reg_2_out-behaviour.vhdl | 1 | 1728 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_2_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:09:21 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with two tri-state outputs.
--
architecture behaviour of reg_2_out is
begin
reg: process (d, latch_en, out_en1, out_en2)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en1 = '1' then
q1 <= latched_value after Tpd;
else
q1 <= null after Tpd;
end if;
if out_en2 = '1' then
q2 <= latched_value after Tpd;
else
q2 <= null after Tpd;
end if;
end process reg;
end behaviour;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/bv_arithmetic.vhdl | 1 | 8151 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_arithmetic.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:10:41 $
--
--------------------------------------------------------------------------
--
-- Bit vector arithmetic package specification.
--
-- Does arithmetic and logical operations on bit vectors, treating them
-- as either unsigned or signed (2's complement) integers. Leftmost bit
-- is most significant or sign bit, rightmost bit is least significant
-- bit. Dyadic operations need the two arguments to be of the same
-- length, however their index ranges and directions may differ. Results
-- must be of the same length as the operands.
--
--------------------------------------------------------------------------
use std.textio.line;
package bv_arithmetic is
----------------------------------------------------------------
-- Type conversions
----------------------------------------------------------------
-- Convert bit vector encoded unsigned integer to natural.
function bv_to_natural (bv : in bit_vector) return natural;
-- Convert natural to bit vector encoded unsigned integer.
-- (length is used as the size of the result.)
function natural_to_bv (nat : in natural;
length : in natural) return bit_vector;
-- Convert bit vector encoded signed integer to integer
function bv_to_integer (bv : in bit_vector) return integer;
-- Convert integer to bit vector encoded signed integer.
-- (length is used as the size of the result.)
function integer_to_bv (int : in integer;
length : in natural) return bit_vector;
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
-- Signed addition with overflow detection
procedure bv_add (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Signed addition without overflow detection
function "+" (bv1, bv2 : in bit_vector) return bit_vector;
-- Signed subtraction with overflow detection
procedure bv_sub (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Signed subtraction without overflow detection
function "-" (bv1, bv2 : in bit_vector) return bit_vector;
-- Unsigned addition with overflow detection
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Unsigned addition without overflow detection
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector);
-- Unsigned subtraction with overflow detection
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Unsigned subtraction without overflow detection
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector);
-- Signed negation with overflow detection
procedure bv_neg (bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Signed negation without overflow detection
function "-" (bv : in bit_vector) return bit_vector;
-- Signed multiplication with overflow detection
procedure bv_mult (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Signed multiplication without overflow detection
function "*" (bv1, bv2 : in bit_vector) return bit_vector;
-- Unsigned multiplication with overflow detection
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean);
-- Unsigned multiplication without overflow detection
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector);
-- Signed division with divide by zero and overflow detection
procedure bv_div (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean);
-- Signed division without divide by zero and overflow detection
function "/" (bv1, bv2 : in bit_vector) return bit_vector;
-- Unsigned division with divide by zero detection
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean);
-- Unsigned division without divide by zero detection
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector);
----------------------------------------------------------------
-- Logical operators
-- (Provided for VHDL-87, built in for VHDL-93)
----------------------------------------------------------------
-- Shift left logical (fill with '0' bits)
function bv_sll (bv : in bit_vector;
shift_count : in natural) return bit_vector;
-- Shift right logical (fill with '0' bits)
function bv_srl (bv : in bit_vector;
shift_count : in natural) return bit_vector;
-- Shift right arithmetic (fill with copy of sign bit)
function bv_sra (bv : in bit_vector;
shift_count : in natural) return bit_vector;
-- Rotate left
function bv_rol (bv : in bit_vector;
rotate_count : in natural) return bit_vector;
-- Rotate right
function bv_ror (bv : in bit_vector;
rotate_count : in natural) return bit_vector;
----------------------------------------------------------------
-- Arithmetic comparison operators.
-- Perform comparisons on bit vector encoded signed integers.
-- (For unsigned integers, built in lexical comparison does
-- the required operation.)
----------------------------------------------------------------
-- Signed less than comparison
function bv_lt (bv1, bv2 : in bit_vector) return boolean;
-- Signed less than or equal comparison
function bv_le (bv1, bv2 : in bit_vector) return boolean;
-- Signed greater than comparison
function bv_gt (bv1, bv2 : in bit_vector) return boolean;
-- Signed greater than or equal comparison
function bv_ge (bv1, bv2 : in bit_vector) return boolean;
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
-- Sign extension - replicate the sign bit of the operand into
-- the most significant bits of the result. Length parameter
-- determines size of result. If length < bv'length, result is
-- rightmost length bits of bv.
function bv_sext (bv : in bit_vector;
length : in natural) return bit_vector;
-- Zero extension - replicate zero bits into the most significant
-- bits of the result. Length parameter determines size of result.
-- If length < bv'length, result is rightmost length bits of bv.
function bv_zext (bv : in bit_vector;
length : in natural) return bit_vector;
end bv_arithmetic;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/images.vhdl | 1 | 2010 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: images.vhdl,v $ $Revision: 1.1 $ $Date: 1993/10/25 20:45:45 $
--
--------------------------------------------------------------------------
--
-- Images package specification.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string;
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string;
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string;
end images;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/images_test-bench.vhdl | 1 | 2882 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: images_test-bench.vhdl,v $ $Revision: 1.1 $ $Date: 1993/10/25 20:47:40 $
--
--------------------------------------------------------------------------
--
-- Architecture declaration for test bench for images package
--
use std.textio.all;
use work.images.all;
architecture bench of images_test is
begin
process
variable L : line;
begin
----------------------------------------------------------------
-- Test binary image of a bit vector
----------------------------------------------------------------
write(L, image(b"01"));
writeline(output, L);
write(L, image(b"01011010"));
writeline(output, L);
----------------------------------------------------------------
-- Test octal image of a bit vector
----------------------------------------------------------------
write(L, image_octal(o"05"));
writeline(output, L);
write(L, image_octal(o"370"));
writeline(output, L);
write(L, image_octal(b"1"));
writeline(output, L);
write(L, image_octal(b"11000"));
writeline(output, L);
----------------------------------------------------------------
-- Test hex image of a bit vector
----------------------------------------------------------------
write(L, image_hex(x"0C"));
writeline(output, L);
write(L, image_hex(x"F1"));
writeline(output, L);
write(L, image_hex("1"));
writeline(output, L);
write(L, image_hex(b"1001000"));
writeline(output, L);
----------------------------------------------------------------
-- Add further tests here ...
----------------------------------------------------------------
----------------------------------------------------------------
-- end of tests
----------------------------------------------------------------
wait;
end process;
end bench;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/reg_file-behaviour.vhdl | 1 | 2259 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_file-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:16:52 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register file.
--
architecture behaviour of reg_file is
begin
reg: process (a1, a2, a3, d3, write_en)
use work.bv_arithmetic.bv_to_natural;
constant all_zeros : dlx_word := X"0000_0000";
type register_array is array (reg_index range 1 to 31) of dlx_word;
variable register_file : register_array;
variable reg_index1, reg_index2, reg_index3 : reg_index;
begin
-- do write first if enabled
--
if write_en = '1' then
reg_index3 := bv_to_natural(a3);
if reg_index3 /= 0 then
register_file(reg_index3) := d3;
end if;
end if;
--
-- read port 1
--
reg_index1 := bv_to_natural(a1);
if reg_index1 /= 0 then
q1 <= register_file(reg_index1) after Tac;
else
q1 <= all_zeros after Tac;
end if;
--
-- read port 2
--
reg_index2 := bv_to_natural(a2);
if reg_index2 /= 0 then
q2 <= register_file(reg_index2) after Tac;
else
q2 <= all_zeros after Tac;
end if;
end process reg;
end behaviour;
| apache-2.0 |
sergev/vak-opensource | hardware/vhd2vl/examples/bigfile.vhd | 1 | 20863 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
-- CONNECTIVITY DEFINITION
entity bigfile is
port (
-- from external pins
sysclk : in std_logic;
g_zaq_in : in std_logic_vector(31 downto 0);
g_aux : in std_logic_vector(31 downto 0);
scanb : in std_logic;
g_wrb : in std_logic;
g_rdb : in std_logic;
g_noop_clr : in std_logic_vector(31 downto 0);
swe_ed : in std_logic;
swe_lv : in std_logic;
din : in std_logic_vector(63 downto 0);
g_dout_w0x0f : in std_logic_vector(4 downto 0);
n9_bit_write : in std_logic;
-- from reset_gen block
reset : in std_logic;
alu_u : in std_logic_vector(31 downto 0);
debct_ping : in std_logic;
g_sys_in : out std_logic_vector(31 downto 0);
g_zaq_in_rst_hold : out std_logic_vector(31 downto 0);
g_zaq_hhh_enb : out std_logic_vector(31 downto 0);
g_zaq_out : out std_logic_vector(31 downto 0);
g_dout : out std_logic_vector(31 downto 0);
g_zaq_ctl : out std_logic_vector(31 downto 0);
g_zaq_qaz_hb : out std_logic_vector(31 downto 0);
g_zaq_qaz_lb : out std_logic_vector(31 downto 0);
gwerth : out std_logic_vector(31 downto 0);
g_noop : out std_logic_vector(31 downto 0);
g_vector : out std_logic_vector(8*32-1 downto 0);
swe_qaz1 : out std_logic_vector(31 downto 0)
);
end bigfile;
-- IMPLEMENTATION
architecture rtl of bigfile is
-- constants
constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000";
constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001";
constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010";
constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011";
constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100";
constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101";
constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110";
constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111";
constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000";
constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001";
constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010";
constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011";
constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100";
constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101";
constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110";
constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111";
constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000";
constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001";
constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010";
constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011";
constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100";
constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101";
constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110";
constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111";
-- comment
signal g_t_klim_dout : std_logic_vector(31 downto 0);
signal g_t_u_dout : std_logic_vector(31 downto 0);
signal g_t_l_dout : std_logic_vector(31 downto 0);
signal g_t_hhh_l_dout : std_logic_vector(31 downto 0);
signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0);
signal g_secondary_t_l_dout : std_logic_vector(31 downto 0);
signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used
signal g_e_z_dout : std_logic_vector(31 downto 0);
signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0);
signal g_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_klim_dout : std_logic_vector(31 downto 0);
signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_t_y_dout : std_logic_vector(31 downto 0);
signal g_n_l_dout : std_logic_vector(31 downto 0);
signal g_n_vfr_dout : std_logic_vector(31 downto 0);
signal g_e_n_r_dout : std_logic_vector(31 downto 0);
signal g_n_r_bne_dout : std_logic;
signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0);
signal g_alu_l_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0);
signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0);
-- other
signal q_g_zaq_in : std_logic_vector(31 downto 0);
signal q2_g_zaq_in : std_logic_vector(31 downto 0);
signal q3_g_zaq_in : std_logic_vector(31 downto 0);
signal q_g_zaq_in_cd : std_logic_vector(3 downto 0);
signal q_g_style_vfr_dout : std_logic_vector(31 downto 0);
signal q_g_unzq : std_logic_vector(3 downto 0);
-- i
signal g_n_active : std_logic_vector(31 downto 0);
-- inter
signal g_zaq_in_y : std_logic_vector(31 downto 0);
signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0);
signal g_zaq_out_i : std_logic_vector(31 downto 0);
signal g_zaq_ctl_i : std_logic_vector(31 downto 0);
signal g_sys_in_i : std_logic_vector(31 downto 0);
signal g_sys_in_ii : std_logic_vector(31 downto 0);
signal g_dout_i : std_logic_vector(31 downto 0);
begin
-- qaz out
g_zaq_out_i <=
-- if secondary
(g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or
-- if alu
(g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or
-- otherwise
(not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout);
-- Changed
g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout;
-- qaz
-- JLB
g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or
(g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i));
-- mux
--vnavigatoroff
g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000";
--vnavigatoron
g_zaq_hhh_enb <= not(g_t_hhh_l_dout);
g_zaq_qaz_hb <= g_t_qaz_mult_high_dout;
g_zaq_qaz_lb <= g_t_qaz_mult_low_dout;
-- Dout
g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else
g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else
g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else
g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else
g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else
g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else
("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else
g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else
g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else
g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else
g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else
g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else
g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else
g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else
g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else
g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else
("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else
g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else
g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else
g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else
g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else
gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else
g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else
gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else
"00000000000000000000000000000000";
g_dout <= g_dout_i when g_rdb = '0' else (others => '1');
-- this can be used to use zzz1
g_style_main_reset_hold_dout_proc :
process(sysclk)
begin
if( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
if( reset = '1' ) then
g_style_main_reset_hold_dout <= g_zaq_in;
end if;
--vnavigatoroff
else
g_style_main_reset_hold_dout <= q2_g_zaq_in;
end if;
--vnavigatoron
end if;
end process;
-- qaz
g_zaq_in_rst_hold <= g_style_main_reset_hold_dout;
-- Din
g_doutister_proc :
process(reset, sysclk)
variable g_dout_w0x0f_v : std_logic_vector(4 downto 0);
begin
if( reset /= '0' ) then
g_t_klim_dout <= (others => '0');
g_t_u_dout <= (others => '0');
g_t_l_dout <= (others => '0');
g_t_hhh_l_dout <= (others => '0');
g_t_jkl_sink_l_dout <= (others => '0');
g_secondary_t_l_dout <= (others => '0');
g_style_c_l_dout <= (others => '0');
g_e_z_dout <= (others => '0');
g_n_both_qbars_l_dout <= (others => '0');
g_style_klim_dout <= (others => '0');
g_style_t_y_dout <= (others => '0');
g_n_l_dout <= (others => '0');
g_e_n_r_dout <= (others => '0');
g_n_r_bne_dout <= '0';
g_n_div_rebeq_dout <= (others => '1');
g_alu_l_dout <= (others => '0');
g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low
g_t_qaz_mult_high_dout <= (others => '0');
gwerthernal_style_u_dout <= (others => '0');
gwerthernal_style_l_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
-- clear
g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr;
if( g_wrb = '0' ) then
-- because we now...
for i in 0 to 1 loop
if( i = 0 ) then
g_dout_w0x0f_v := g_dout_w0x0f;
elsif( i = 1 ) then
if( n9_bit_write = '1' ) then
-- set
g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
else
exit;
end if;
--vnavigatoroff
else
-- not possible but added for code coverage's sake
end if;
--vnavigatoron
case g_dout_w0x0f_v is
when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32);
when g_t_u_w0x0f =>
-- output klim
for j in 0 to 31 loop
if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then
g_t_u_dout(j) <= din(32*i+j);
end if;
end loop;
when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32);
when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32);
when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32);
when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32);
when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32);
when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32);
when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32);
when g_style_vfr_w0x0f => null; -- read-only register
when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32);
when g_unklimed_style_vfr_w0x0f => null; -- read-only register
when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32);
when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32);
when g_n_vfr_w0x0f => null; -- writes
when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32);
when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32);
when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or
g_n_div_rebeq_dout; -- a '1' writes
when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32);
--vnavigatoroff
when others => null;
--vnavigatoron
end case;
end loop;
end if;
end if;
end process;
-- sample
g_zaq_in_sample_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_zaq_in <= (others => '0');
q2_g_zaq_in <= (others => '0');
q3_g_zaq_in <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
q_g_zaq_in <= g_zaq_in;
q2_g_zaq_in <= q_g_zaq_in;
q3_g_zaq_in <= g_zaq_in_y;
end if;
end process;
-- vfr register
g_unklimed_style_vfr_dout <= q2_g_zaq_in;
-- switch
g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in;
-- qaz
g_style_vfr_dout <= -- top 2
(g_zaq_in_y(31 downto 4) &
-- FSM
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0))));
-- in scan mode
g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1'
--vnavigatoroff
else g_style_t_y_dout;
--vnavigatoron
g_sys_in_i <= (-- top 28
(g_zaq_in_y_no_dout(31 downto 4) &
-- is enabled
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0)))));
g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout );
g_sys_in <= g_sys_in_ii;
lpq_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_zaq_in_cd <= (others => '0');
q_g_unzq <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
-- sample
if( debct_ping = '1') then
-- taken
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
else
if( q_g_unzq(i) = '0' ) then
q_g_zaq_in_cd(i) <= g_zaq_in_y(i);
else
q_g_unzq(i) <= '0';
end if;
end if;
end loop;
else
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
-- generate lqqs
sample_forwerth_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_style_vfr_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
q_g_style_vfr_dout <= g_style_vfr_dout;
--vnavigatoroff
else
-- in scan
q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii;
end if;
--vnavigatoron
end if;
end process;
-- generate
g_n_active <= -- 1 to 0
(((q_g_style_vfr_dout and not g_style_vfr_dout) or
-- get this
(not q_g_style_vfr_dout and g_style_vfr_dout and
g_n_both_qbars_l_dout))) and
-- must be
g_n_l_dout;
-- check for lqq active and set lqq vfr register
-- also clear
n_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
g_n_vfr_dout <= (others => '0');
gwerth <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
for i in 0 to 31 loop
-- lqq
-- vfr matches
if( g_n_active(i) = '1' ) then
gwerth(i) <= '1';
if( g_e_z_dout(i) = '1' ) then
-- lqq
g_n_vfr_dout(i) <= '1';
else
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i);
end if;
else
-- clear
if( g_e_z_dout(i) = '0' ) then
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign
-- in both
if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then
gwerth(i) <= '0';
end if;
else
-- write
if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then
gwerth(i) <= '0';
g_n_vfr_dout(i) <= '0';
end if;
end if;
end if;
end loop;
end if;
end process;
----
-- Create the Lqq
createwerth_vec_proc :
process( g_n_r_bne_dout, g_e_n_r_dout)
variable imod8, idiv8 : integer;
begin
for i in 0 to 31 loop
imod8 := i mod 8;
idiv8 := i / 8;
if( g_n_r_bne_dout = '0' ) then
-- non-unique
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
-- unique
if( imod8 = 0 ) then
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) +
to_unsigned(imod8, 8));
end if;
end if;
end loop;
end process;
----
-- Qaz
g_noop <= g_n_div_rebeq_dout;
create_g_ack_bne_proc :
process( swe_ed,swe_lv,g_e_z_dout)
begin
for i in 0 to 31 loop
if( g_e_z_dout(i) = '1') then
swe_qaz1(i) <= swe_ed;
else
swe_qaz1(i) <= swe_lv;
end if;
end loop;
end process;
end rtl;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/dlx-instrumented.vhdl | 1 | 26403 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-instrumented.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:36:01 $
--
--------------------------------------------------------------------------
--
-- Instrumented behavioural architecture for DLX, that generates
-- a files of instruction execution frequencies for a program.
--
use work.dlx_instr.all,
work.bv_arithmetic.all,
std.textio.all;
architecture instrumented of dlx is
begin -- instrumented
interpreter: process
type reg_array is array (reg_index) of dlx_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_word;
variable user_mode : boolean;
variable overflow, div_by_zero : boolean;
constant PC_incr : dlx_word := X"0000_0004";
variable IR : dlx_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr : dlx_address;
variable mem_data : dlx_word;
subtype ls_2_addr_bits is bit_vector(1 downto 0);
file data : text is out "dlx_instruction_counts";
variable L : line;
---------------------------------------------------------------------------
-- instrumentation: array of counters, one per instruction
---------------------------------------------------------------------------
type opcode_count_array is array (dlx_opcode_num) of natural;
type sp_func_count_array is array (dlx_sp_func_num) of natural;
type fp_func_count_array is array (dlx_fp_func_num) of natural;
variable op_count : opcode_count_array := (others => 0);
variable sp_func_count : sp_func_count_array := (others => 0);
variable fp_func_count : fp_func_count_array := (others => 0);
variable instr_count : natural := 0;
---------------------------------------------------------------------------
-- instrumentation: procedure to dump counter values
---------------------------------------------------------------------------
procedure instrumentation_dump is
variable L : line;
begin
for op in dlx_opcode_num loop
write(L, opcode_names(op));
write(L, ' ');
write(L, op_count(op));
writeline(data, L);
end loop;
for sp_func in dlx_sp_func_num loop
write(L, sp_func_names(sp_func));
write(L, ' ');
write(L, sp_func_count(sp_func));
writeline(data, L);
end loop;
for fp_func in dlx_fp_func_num loop
write(L, fp_func_names(fp_func));
write(L, ' ');
write(L, fp_func_count(fp_func));
writeline(data, L);
end loop;
end instrumentation_dump;
---------------------------------------------------------------------------
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction fetch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure bus_read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction eftch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end bus_read;
begin -- interpreter
--
-- reset the processor
--
d <= null;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
user_mode := false;
--
-- fetch-decode-execute loop
--
loop
--
-- fetch next instruction
--
if debug then
write(L, tag);
write(L, string'(": fetching instruction..."));
writeline(output, L);
end if;
--
bus_read(PC, width_word, true, IR,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
--
-- increment the PC to point to the following instruction
--
if debug then
write(L, tag);
write(L, string'(": incrementing PC..."));
writeline(output, L);
end if;
--
bv_add(PC, PC_incr, PC, overflow);
--
-- decode the instruction
--
if debug then
write(L, tag);
write(L, string'(": decoding instruction..."));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
--
-------------------------------------------------------------------------
-- instrumentation: increment counter for decoded instruction
-------------------------------------------------------------------------
--
op_count(IR_opcode_num) := op_count(IR_opcode_num) + 1;
if IR_opcode = op_special then
sp_func_count(IR_sp_func_num) := sp_func_count(IR_sp_func_num) + 1;
elsif IR_opcode = op_fparith then
fp_func_count(IR_fp_func_num) := fp_func_count(IR_fp_func_num) + 1;
end if;
instr_count := instr_count + 1;
--
-------------------------------------------------------------------------
--
-- exectute
--
if debug then
write(L, tag);
write(L, string'(": executing instruction..."));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
WHEN sp_func_nop =>
null;
when sp_func_sll =>
reg(Rtype_rd) := bv_sll(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_srl =>
reg(Rtype_rd) := bv_srl(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sra =>
reg(Rtype_rd) := bv_sra(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sequ =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sneu =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sltu =>
if reg(rs1) < reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgtu =>
if reg(rs1) > reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sleu =>
if reg(rs1) <= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgeu =>
if reg(rs1) >= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_seq =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sne =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_slt =>
if bv_lt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgt =>
if bv_gt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sle =>
if bv_le(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sge =>
if bv_ge(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
reg(Rtype_rd) := fp_reg(rs1);
when sp_func_movi2fp =>
fp_reg(Rtype_rd) := reg(rs1);
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_mult =>
bv_mult(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_multu =>
bv_multu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_div =>
bv_div(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero, overflow);
when fp_func_divu =>
bv_divu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero);
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_jal =>
reg(link_reg) := PC;
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := bv_sll(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srli =>
reg(Itype_rd) := bv_srl(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srai =>
reg(Itype_rd) := bv_sra(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
halt <= '1' after Tpd_clk_out;
---------------------------------------------------------------------
-- instrumentation: dump counters
---------------------------------------------------------------------
instrumentation_dump;
---------------------------------------------------------------------
wait until reset = '1';
exit;
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_seqi =>
if reg(rs1) = bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_snei =>
if reg(rs1) /= bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slti =>
if bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgti =>
if bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slei =>
if bv_le(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgei =>
if bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_lb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_sext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_sext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_sext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_sext(mem_data(24 to 31), 32);
end case;
when op_lh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_sext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(mem_data(16 to 31), 32);
end if;
when op_lw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_word, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
reg(Itype_rd) := mem_data;
when op_lbu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_zext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_zext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_zext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_zext(mem_data(24 to 31), 32);
end case;
when op_lhu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_zext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_zext(mem_data(16 to 31), 32);
end if;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
mem_data(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
if mem_addr(1) = '0' then
mem_data(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := reg(Itype_rd);
write(mem_addr, width_word, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi =>
if reg(rs1) = bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sneui =>
if reg(rs1) /= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sltui =>
if reg(rs1) < bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgtui =>
if reg(rs1) > bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sleui =>
if reg(rs1) <= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgeui =>
if reg(rs1) >= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
-- fix up R0 in case it was overwritten
--
reg(0) := X"0000_0000";
--
if debug then
write(L, tag);
write(L, string'(": end of execution"));
writeline(output, L);
end if;
if instr_count mod 100 = 0 then
write(L, tag);
write(L, string'(": executed "));
write(L, instr_count);
write(L, string'(" instructions"));
writeline(output, L);
end if;
--
end loop;
--
-- loop is only exited when reset active: wait until it goes inactive
--
assert reset = '1'
report "reset code reached with reset = '0'" severity error;
wait until phi2 = '0' and reset = '0';
--
-- process interpreter now starts again from beginning
--
end process interpreter;
end instrumented;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/bv_test.vhdl | 1 | 1294 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_test.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:12:11 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for test bench for bit vector arithmetic package.
--
entity bv_test is
begin
end bv_test;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/dlx_test.vhdl | 1 | 1260 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_test.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:39:49 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for test bench for DLX
--
entity dlx_test is
end dlx_test;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/mem_types.vhdl | 1 | 1321 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: mem_types.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:39:06 $
--
--------------------------------------------------------------------------
--
-- Types package for memory model
--
package mem_types is
type mem_width is (width_byte, width_halfword, width_word);
end mem_types;
| apache-2.0 |
sergev/vak-opensource | hardware/vhd2vl/examples/gh_fifo_async16_sr.vhd | 1 | 5969 | ---------------------------------------------------------------------
-- Filename: gh_fifo_async16_sr.vhd
--
--
-- Description:
-- an Asynchronous FIFO
--
-- Copyright (c) 2006 by George Huber
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 12/17/06 h lefevre Initial revision
--
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity gh_fifo_async16_sr is
GENERIC (data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC);
end entity;
architecture a of gh_fifo_async16_sr is
type ram_mem_type is array (15 downto 0)
of STD_LOGIC_VECTOR (data_width-1 downto 0);
signal ram_mem : ram_mem_type;
signal iempty : STD_LOGIC;
signal ifull : STD_LOGIC;
signal add_WR_CE : std_logic;
signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM
signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare
signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags
signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk
signal add_RD_CE : std_logic;
signal add_RD : std_logic_vector(4 downto 0);
signal add_RD_GC : std_logic_vector(4 downto 0);
signal add_RD_GCwc : std_logic_vector(4 downto 0);
signal n_add_RD : std_logic_vector(4 downto 0);
signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk
signal srst_w : STD_LOGIC;
signal isrst_w : STD_LOGIC;
signal srst_r : STD_LOGIC;
signal isrst_r : STD_LOGIC;
begin
--------------------------------------------
------- memory -----------------------------
--------------------------------------------
process (clk_WR)
begin
if (rising_edge(clk_WR)) then
if ((WR = '1') and (ifull = '0')) then
ram_mem(CONV_INTEGER(add_WR(3 downto 0))) <= D;
end if;
end if;
end process;
Q <= ram_mem(CONV_INTEGER(add_RD(3 downto 0)));
-----------------------------------------
----- Write address counter -------------
-----------------------------------------
add_WR_CE <= '0' when (ifull = '1') else
'0' when (WR = '0') else
'1';
n_add_WR <= add_WR + x"1";
process (clk_WR,rst)
begin
if (rst = '1') then
add_WR <= (others => '0');
add_RD_WS <= "11000";
add_WR_GC <= (others => '0');
elsif (rising_edge(clk_WR)) then
add_RD_WS <= add_RD_GCwc;
if (srst_w = '1') then
add_WR <= (others => '0');
add_WR_GC <= (others => '0');
elsif (add_WR_CE = '1') then
add_WR <= n_add_WR;
add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1);
add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2);
add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3);
add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4);
add_WR_GC(4) <= n_add_WR(4);
else
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end if;
end if;
end process;
full <= ifull;
ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000"
'0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000"
'1';
-----------------------------------------
----- Read address counter --------------
-----------------------------------------
add_RD_CE <= '0' when (iempty = '1') else
'0' when (RD = '0') else
'1';
n_add_RD <= add_RD + x"1";
process (clk_RD,rst)
begin
if (rst = '1') then
add_RD <= (others => '0');
add_WR_RS <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (rising_edge(clk_RD)) then
add_WR_RS <= add_WR_GC;
if (srst_r = '1') then
add_RD <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (add_RD_CE = '1') then
add_RD <= n_add_RD;
add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4);
add_RD_GC(4) <= n_add_RD(4);
add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4));
add_RD_GCwc(4) <= (not n_add_RD(4));
else
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end if;
end if;
end process;
empty <= iempty;
iempty <= '1' when (add_WR_RS = add_RD_GC) else
'0';
----------------------------------
--- sync rest stuff --------------
--- srst is sync with clk_WR -----
--- srst_r is sync with clk_RD ---
----------------------------------
process (clk_WR,rst)
begin
if (rst = '1') then
srst_w <= '0';
isrst_r <= '0';
elsif (rising_edge(clk_WR)) then
isrst_r <= srst_r;
if (srst = '1') then
srst_w <= '1';
elsif (isrst_r = '1') then
srst_w <= '0';
end if;
end if;
end process;
process (clk_RD,rst)
begin
if (rst = '1') then
srst_r <= '0';
isrst_w <= '0';
elsif (rising_edge(clk_RD)) then
isrst_w <= srst_w;
if (isrst_w = '1') then
srst_r <= '1';
else
srst_r <= '0';
end if;
end if;
end process;
end architecture;
| apache-2.0 |
sergev/vak-opensource | hardware/dlx/dlx_instr.vhdl | 1 | 11479 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_instr.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:34:41 $
--
--------------------------------------------------------------------------
--
-- Package specification for DLX instructions
--
use std.textio.line,
work.dlx_types.all;
package dlx_instr is
-- A dlx instruction is 32 bits wide. There are three instruction formats:
--
-- I-type:
-- 0 5 6 10 11 15 16 31
-- +----------------------------------------------------------------+
-- | opcode | rs1 | rd | immed16 |
-- +----------------------------------------------------------------+
--
-- R-type:
-- 0 5 6 10 11 15 16 20 21 25 26 31
-- +----------------------------------------------------------------+
-- | opcode | rs1 | rs2 | rd | | func |
-- +----------------------------------------------------------------+
--
-- J-type:
-- 0 5 6 31
-- +----------------------------------------------------------------+
-- | opcode | immed26 |
-- +----------------------------------------------------------------+
--
subtype dlx_opcode is bit_vector(0 to 5);
subtype dlx_sp_func is bit_vector(0 to 5);
subtype dlx_fp_func is bit_vector(0 to 4);
subtype dlx_reg_addr is bit_vector(0 to 4);
subtype dlx_immed16 is bit_vector(0 to 15);
subtype dlx_immed26 is bit_vector(0 to 25);
constant op_special : dlx_opcode := B"000000";
constant op_fparith : dlx_opcode := B"000001";
constant op_j : dlx_opcode := B"000010";
constant op_jal : dlx_opcode := B"000011";
constant op_beqz : dlx_opcode := B"000100";
constant op_bnez : dlx_opcode := B"000101";
constant op_bfpt : dlx_opcode := B"000110";
constant op_bfpf : dlx_opcode := B"000111";
constant op_addi : dlx_opcode := B"001000";
constant op_addui : dlx_opcode := B"001001";
constant op_subi : dlx_opcode := B"001010";
constant op_subui : dlx_opcode := B"001011";
constant op_andi : dlx_opcode := B"001100";
constant op_ori : dlx_opcode := B"001101";
constant op_xori : dlx_opcode := B"001110";
constant op_lhi : dlx_opcode := B"001111";
constant op_rfe : dlx_opcode := B"010000";
constant op_trap : dlx_opcode := B"010001";
constant op_jr : dlx_opcode := B"010010";
constant op_jalr : dlx_opcode := B"010011";
constant op_slli : dlx_opcode := B"010100";
constant op_undef_15 : dlx_opcode := B"010101";
constant op_srli : dlx_opcode := B"010110";
constant op_srai : dlx_opcode := B"010111";
constant op_seqi : dlx_opcode := B"011000";
constant op_snei : dlx_opcode := B"011001";
constant op_slti : dlx_opcode := B"011010";
constant op_sgti : dlx_opcode := B"011011";
constant op_slei : dlx_opcode := B"011100";
constant op_sgei : dlx_opcode := B"011101";
constant op_undef_1E : dlx_opcode := B"011110";
constant op_undef_1F : dlx_opcode := B"011111";
constant op_lb : dlx_opcode := B"100000";
constant op_lh : dlx_opcode := B"100001";
constant op_undef_22 : dlx_opcode := B"100010";
constant op_lw : dlx_opcode := B"100011";
constant op_lbu : dlx_opcode := B"100100";
constant op_lhu : dlx_opcode := B"100101";
constant op_lf : dlx_opcode := B"100110";
constant op_ld : dlx_opcode := B"100111";
constant op_sb : dlx_opcode := B"101000";
constant op_sh : dlx_opcode := B"101001";
constant op_undef_2A : dlx_opcode := B"101010";
constant op_sw : dlx_opcode := B"101011";
constant op_undef_2C : dlx_opcode := B"101100";
constant op_undef_2D : dlx_opcode := B"101101";
constant op_sf : dlx_opcode := B"101110";
constant op_sd : dlx_opcode := B"101111";
constant op_sequi : dlx_opcode := B"110000";
constant op_sneui : dlx_opcode := B"110001";
constant op_sltui : dlx_opcode := B"110010";
constant op_sgtui : dlx_opcode := B"110011";
constant op_sleui : dlx_opcode := B"110100";
constant op_sgeui : dlx_opcode := B"110101";
constant op_undef_36 : dlx_opcode := B"110110";
constant op_undef_37 : dlx_opcode := B"110111";
constant op_undef_38 : dlx_opcode := B"111000";
constant op_undef_39 : dlx_opcode := B"111001";
constant op_undef_3A : dlx_opcode := B"111010";
constant op_undef_3B : dlx_opcode := B"111011";
constant op_undef_3C : dlx_opcode := B"111100";
constant op_undef_3D : dlx_opcode := B"111101";
constant op_undef_3E : dlx_opcode := B"111110";
constant op_undef_3F : dlx_opcode := B"111111";
constant sp_func_nop : dlx_sp_func := B"000000";
constant sp_func_undef_01 : dlx_sp_func := B"000001";
constant sp_func_undef_02 : dlx_sp_func := B"000010";
constant sp_func_undef_03 : dlx_sp_func := B"000011";
constant sp_func_sll : dlx_sp_func := B"000100";
constant sp_func_undef_05 : dlx_sp_func := B"000101";
constant sp_func_srl : dlx_sp_func := B"000110";
constant sp_func_sra : dlx_sp_func := B"000111";
constant sp_func_undef_08 : dlx_sp_func := B"001000";
constant sp_func_undef_09 : dlx_sp_func := B"001001";
constant sp_func_undef_0A : dlx_sp_func := B"001010";
constant sp_func_undef_0B : dlx_sp_func := B"001011";
constant sp_func_undef_0C : dlx_sp_func := B"001100";
constant sp_func_undef_0D : dlx_sp_func := B"001101";
constant sp_func_undef_0E : dlx_sp_func := B"001110";
constant sp_func_undef_0F : dlx_sp_func := B"001111";
constant sp_func_sequ : dlx_sp_func := B"010000";
constant sp_func_sneu : dlx_sp_func := B"010001";
constant sp_func_sltu : dlx_sp_func := B"010010";
constant sp_func_sgtu : dlx_sp_func := B"010011";
constant sp_func_sleu : dlx_sp_func := B"010100";
constant sp_func_sgeu : dlx_sp_func := B"010101";
constant sp_func_undef_16 : dlx_sp_func := B"010110";
constant sp_func_undef_17 : dlx_sp_func := B"010111";
constant sp_func_undef_18 : dlx_sp_func := B"011000";
constant sp_func_undef_19 : dlx_sp_func := B"011001";
constant sp_func_undef_1A : dlx_sp_func := B"011010";
constant sp_func_undef_1B : dlx_sp_func := B"011011";
constant sp_func_undef_1C : dlx_sp_func := B"011100";
constant sp_func_undef_1D : dlx_sp_func := B"011101";
constant sp_func_undef_1E : dlx_sp_func := B"011110";
constant sp_func_undef_1F : dlx_sp_func := B"011111";
constant sp_func_add : dlx_sp_func := B"100000";
constant sp_func_addu : dlx_sp_func := B"100001";
constant sp_func_sub : dlx_sp_func := B"100010";
constant sp_func_subu : dlx_sp_func := B"100011";
constant sp_func_and : dlx_sp_func := B"100100";
constant sp_func_or : dlx_sp_func := B"100101";
constant sp_func_xor : dlx_sp_func := B"100110";
constant sp_func_undef_27 : dlx_sp_func := B"100111";
constant sp_func_seq : dlx_sp_func := B"101000";
constant sp_func_sne : dlx_sp_func := B"101001";
constant sp_func_slt : dlx_sp_func := B"101010";
constant sp_func_sgt : dlx_sp_func := B"101011";
constant sp_func_sle : dlx_sp_func := B"101100";
constant sp_func_sge : dlx_sp_func := B"101101";
constant sp_func_undef_2E : dlx_sp_func := B"101110";
constant sp_func_undef_2F : dlx_sp_func := B"101111";
constant sp_func_movi2s : dlx_sp_func := B"110000";
constant sp_func_movs2i : dlx_sp_func := B"110001";
constant sp_func_movf : dlx_sp_func := B"110010";
constant sp_func_movd : dlx_sp_func := B"110011";
constant sp_func_movfp2i : dlx_sp_func := B"110100";
constant sp_func_movi2fp : dlx_sp_func := B"110101";
constant sp_func_undef_36 : dlx_sp_func := B"110110";
constant sp_func_undef_37 : dlx_sp_func := B"110111";
constant sp_func_undef_38 : dlx_sp_func := B"111000";
constant sp_func_undef_39 : dlx_sp_func := B"111001";
constant sp_func_undef_3A : dlx_sp_func := B"111010";
constant sp_func_undef_3B : dlx_sp_func := B"111011";
constant sp_func_undef_3C : dlx_sp_func := B"111100";
constant sp_func_undef_3D : dlx_sp_func := B"111101";
constant sp_func_undef_3E : dlx_sp_func := B"111110";
constant sp_func_undef_3F : dlx_sp_func := B"111111";
constant fp_func_addf : dlx_fp_func := B"00000";
constant fp_func_subf : dlx_fp_func := B"00001";
constant fp_func_multf : dlx_fp_func := B"00010";
constant fp_func_divf : dlx_fp_func := B"00011";
constant fp_func_addd : dlx_fp_func := B"00100";
constant fp_func_subd : dlx_fp_func := B"00101";
constant fp_func_multd : dlx_fp_func := B"00110";
constant fp_func_divd : dlx_fp_func := B"00111";
constant fp_func_cvtf2d : dlx_fp_func := B"01000";
constant fp_func_cvtf2i : dlx_fp_func := B"01001";
constant fp_func_cvtd2f : dlx_fp_func := B"01010";
constant fp_func_cvtd2i : dlx_fp_func := B"01011";
constant fp_func_cvti2f : dlx_fp_func := B"01100";
constant fp_func_cvti2d : dlx_fp_func := B"01101";
constant fp_func_mult : dlx_fp_func := B"01110";
constant fp_func_div : dlx_fp_func := B"01111";
constant fp_func_eqf : dlx_fp_func := B"10000";
constant fp_func_nef : dlx_fp_func := B"10001";
constant fp_func_ltf : dlx_fp_func := B"10010";
constant fp_func_gtf : dlx_fp_func := B"10011";
constant fp_func_lef : dlx_fp_func := B"10100";
constant fp_func_gef : dlx_fp_func := B"10101";
constant fp_func_multu : dlx_fp_func := B"10110";
constant fp_func_divu : dlx_fp_func := B"10111";
constant fp_func_eqd : dlx_fp_func := B"11000";
constant fp_func_ned : dlx_fp_func := B"11001";
constant fp_func_ltd : dlx_fp_func := B"11010";
constant fp_func_gtd : dlx_fp_func := B"11011";
constant fp_func_led : dlx_fp_func := B"11100";
constant fp_func_ged : dlx_fp_func := B"11101";
constant fp_func_undef_1E : dlx_fp_func := B"11110";
constant fp_func_undef_1F : dlx_fp_func := B"11111";
subtype dlx_opcode_num is natural range 0 to 63;
subtype dlx_sp_func_num is natural range 0 to 63;
subtype dlx_fp_func_num is natural range 0 to 31;
subtype instr_name is string(1 to 8);
type opcode_name_array is array (dlx_opcode_num) of instr_name;
type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
constant opcode_names : opcode_name_array;
constant sp_func_names : sp_func_name_array;
constant fp_func_names : fp_func_name_array;
type immed_size is (immed_size_16, immed_size_26);
subtype reg_index is natural range 0 to 31;
constant link_reg : reg_index := 31;
procedure write_instr (L : inout line; instr : in dlx_word);
end dlx_instr;
| apache-2.0 |
Cognoscan/BoostDSP | vhdl/src/basic_tb/strobed_file_sink_tb.vhd | 1 | 2733 | --! @file strobed_file_sink_tb.vhd
--! @brief Data Strobed File Sink testbench
--! @author Scott Teal ([email protected])
--! @date 2013-12-13
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE Library
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_float_types.all;
library boostdsp;
use boostdsp.fixed_pkg.all;
use boostdsp.basic_pkg;
--! Tests the fixed-point strobed-data file sink with a cosine generator.
entity file_sink_tb is
generic (
FILE_NAME : string := string'("file_sink_tb.txt") --! File to dump to
);
end entity;
architecture sim of file_sink_tb is
constant clk_p : time := 10 ns;
constant clk_hp : time := clk_p / 2;
signal clk : std_logic := '0'; --! Ssytem clock
signal rst : std_logic := '1'; --! Reset for system
signal din : sfixed(1 downto -6); --! Data to dump to file
signal strobe_in : std_logic := '0'; --! Data strobe
signal sine : sfixed(1 downto -6); --! Unused sine output.
--! Angle to drive trig_table.
signal angle : ufixed(-1 downto -7) := to_ufixed(0.0, -1, -7);
begin
--! File Sink to test.
uut : basic_pkg.strobed_file_sink
generic map (
FILE_NAME => FILE_NAME
)
port map (
clk => clk,
rst => rst,
din => din,
strobe_in => strobe_in
);
--! Sin & Cos lookup table.
cosine_test : basic_pkg.trig_table
port map (
clk => clk,
rst => rst,
angle => angle,
sine => sine,
cosine => din
);
--! Clock generator
clk_proc : process
begin
wait for clk_hp;
clk <= not clk;
end process;
--! Reset generator
rst_proc : process
begin
wait for clk_hp * 4;
rst <= '0';
wait;
end process;
--! Process to run test.
test_proc : process
begin
wait for clk_p;
angle <= resize(angle + to_ufixed(1.0/100.0, angle), angle'high, angle'low,
fixed_wrap, fixed_truncate);
end process;
--! Process to strobe data. Should cut the data rate to 1/3 the original.
strobe_proc : process
begin
wait for clk_p * 2;
strobe_in <= '1';
wait for clk_p;
strobe_in <= '0';
end process;
end sim;
| apache-2.0 |
Cognoscan/BoostDSP | vhdl/src/rf_blocks/frame_tx_ea.vhd | 1 | 9282 | --! @file frame_tx_ea.vhd
--! @brief frame-based transmitter
--! @author Scott Teal ([email protected])
--! @date 2013-11-05
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
--! Local version of the fixed point package
use work.fixed_pkg.all;
--! Basic design elements
use work.basic_pkg;
--! Creates a buffer that can be read and written to, and provides functionality
--! to convert the buffer into a series of symbols. It does *not* map the
--! symbols or generate any kind of waveform.
--!
--! The frame buffer is addressable by frame_addr. The buffer is sized so that
--! every possible address exists in the buffer (so buffer size is
--! 2^frame_addr'length).
--!
--! Frame_tx will iterate through the buffer from 0 to frame_size to create the
--! symbols after the start line has been strobed high. It can be stopped early
--! by strobing the abort line high. Once it is finished, frame_tx_complete is
--! asserted. The frame_tx_complete line is high so long as it is not
--! transmitting symbols.
--!
--! Finally, when transmitting symbols, frame_tx will dwell on each symbol for
--! a set number of clock cycles. The number of clock cycles is set by
--! clks_per_symbol.
entity frame_tx is
port (
clk : in std_logic; --! System clock
rst : in std_logic; --! System reset
frame_size : in unsigned; --! Size of frame to transmit
clks_per_symbol : in unsigned; --! Clock cycles per symbol transmitted
start : in std_logic; --! Strobe high to start transmitting.
abort : in std_logic; --! Strobe high to abort transmitting.
frame_tx_complete : out std_logic; --! High when not transmitting.
buffer_addr : in std_logic_vector; --! Address to read/write to.
buffer_we : in std_logic; --! High when write, low when read.
buffer_write_data : in std_logic_vector; --! Data to write.
buffer_read_data : out std_logic_vector; --! Data read from address.
buffer_strobe : in std_logic; --! Strobe high to cycle bus.
buffer_done : out std_logic; --! Strobe high when read/write complete.
symbol_out : out std_logic_vector --! Symbol output
);
end entity;
architecture rtl of frame_tx is
--! The frame buffer std_logic_vector array type
type frame_buffer_type is array ((2**buffer_addr'length-1) downto 0) of
std_logic_vector(buffer_write_data'range);
--! The frame buffer. Initialized to 0 on configuration of device.
signal frame_buffer : frame_buffer_type := (others => (others => '0'));
--! Register holding data read back from frame buffer
signal buffer_read_data_internal : std_logic_vector(buffer_read_data'range);
--! Stores current address of data moving to symbolizer.
signal out_counter : unsigned(frame_size'range);
--! Counter to drive fetch_symbol
signal symbol_counter : unsigned(clks_per_symbol'range);
--! Data to write to symbolizer
signal data_to_symbolizer : std_logic_vector(buffer_write_data'range);
--! Busy signal from symbolizer
signal busy : std_logic;
--! Data valid signal to symbolizer
signal data_valid : std_logic;
--! Fetch_symbol signal to symbolizer, strobed based on clks_per_symbol
signal fetch_symbol : std_logic;
--! Internal signal is high when transmitting. Used to track state of frame_tx
--! within the symbolizer_interface process.
signal active_tx : std_logic;
begin
-- Verify assumptions first
assert buffer_write_data'length = buffer_read_data'length
report "Write bus and read bus not same length"
severity error;
assert frame_size'length = buffer_addr'length
report "frame_size cannot be full size of transmit buffer"
severity error;
-- Create symbolizer.
make_symbolizer_even : if (buffer_write_data'length mod symbol_out'length)
= 0 generate
symbolizer_1 : basic_pkg.symbolizer_even
port map(
clk => clk,
rst => rst,
data_in => data_to_symbolizer,
busy => busy,
data_valid => data_valid,
fetch_symbol => fetch_symbol,
symbol_out => symbol_out
);
end generate;
make_symbolizer : if (buffer_write_data'length mod symbol_out'length)
/= 0 generate
symbolizer_1 : basic_pkg.symbolizer
port map(
clk => clk,
rst => rst,
data_in => data_to_symbolizer,
busy => busy,
data_valid => data_valid,
fetch_symbol => fetch_symbol,
symbol_out => symbol_out
);
end generate;
--! Interface for reading/writing to frame buffer. Very straightforward, and
--! takes one cycle to read/write. It just checks for buffer_strobe and
--! either reads or writes depending on buffer_we.
buffer_interface : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
buffer_read_data_internal <= (others => '0');
buffer_done <= '1';
else
buffer_done <= '0';
-- Only take action when the bus is strobed (cycled).
if buffer_strobe = '1' then
buffer_done <= '1';
if buffer_we = '1' then
frame_buffer(to_integer(unsigned(buffer_addr))) <=
buffer_write_data;
else
buffer_read_data_internal <=
frame_buffer(to_integer(unsigned(buffer_addr)));
end if; -- read/write check
end if; -- strobe check
end if; -- rst
end if; -- clk
end process;
buffer_read_data <= buffer_read_data_internal;
--! Interface for providing data to the symbolizer
symbolizer_interface : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
data_valid <= '0';
active_tx <= '0';
out_counter <= to_unsigned(0, out_counter'length);
data_to_symbolizer <= (others => '0');
else
data_valid <= '0';
-- Actively transmitting?
if active_tx = '1' then
-- Load next whenever symbolizer not busy
if busy = '0' and data_valid = '0' then
-- Abort / all data transmitted?
if abort = '1' or out_counter = (frame_size + 1) then
active_tx <= '0';
out_counter <= to_unsigned(0, out_counter'length);
else
out_counter <= out_counter + 1;
data_valid <= '1';
data_to_symbolizer <= frame_buffer(to_integer(out_counter));
end if;
end if;
else
-- Wait for start indicator
if start = '1' then
active_tx <= '1';
out_counter <= out_counter + 1;
data_valid <= '1';
data_to_symbolizer <= frame_buffer(to_integer(out_counter));
end if;
end if; -- active_tx
end if; -- rst
end if; -- clk
end process;
--! Fetches symbols from the symbolizer every clks_per_symbol by using
--! a counter. This can run constantly.
symbol_fetcher : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
fetch_symbol <= '0';
symbol_counter <= to_unsigned(1, symbol_counter'length);
else
if symbol_counter = clks_per_symbol then
symbol_counter <= to_unsigned(1, symbol_counter'length);
fetch_symbol <= '1';
else
symbol_counter <= symbol_counter + 1;
fetch_symbol <= '0';
end if; -- counter
end if; -- rst
end if; -- clk
end process;
--! Frame_tx_complete when active_tx = 0 AND the last of the data has been
--! turned into symbols AND the last symbol has been active for
--! clks_per_symbol clock cycles.
complete_indicate : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
frame_tx_complete <= '1';
else
if frame_tx_complete = '0' then
if active_tx = '0' and fetch_symbol = '1' then
frame_tx_complete <= '1';
end if; -- fetch_symbol and active_tx
else
if active_tx = '1' then
frame_tx_complete <= '0';
end if;
end if; -- frame_tx_complete
end if; -- rst
end if; -- clk
end process;
end rtl;
| apache-2.0 |
Cognoscan/BoostDSP | vhdl/src/basic/file_source_ea.vhd | 1 | 2297 | --! @file file_source_ea.vhd
--! @brief Reads fixed-point data from a file.
--! @author Scott Teal ([email protected])
--! @date 2013-12-14
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Need standard file I/O package
use std.textio.all;
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
--! Reads fixed-point values from a file. Outputs data one line at a time, and
--! does so on the rising edge of clk, provided that rst is low. When the end of
--! the file is reached, it loops around to the beginning.
entity file_source is
generic (
FILE_NAME : string --! File to read data from
);
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
dout : out sfixed --! Fixed-point data output
);
end entity;
--! Uses Textio to read data line by line from a file. It assumes data is stored
--! as human-readable real values, separated by newline characters.
architecture sim of file_source is
file in_file : text open read_mode is FILE_NAME; --! File source
begin
--! Read data from file on rising clock edge
read_data : process (clk, rst)
variable buf : line; --! Text buffer between file input and data
variable data : real; --! Data temporarily stored as a real
begin
if rising_edge(clk) and (rst = '0') then
-- Reload file if out of data.
if endfile(in_file) then
file_close(in_file);
file_open(in_file, FILE_NAME, read_mode);
end if;
readline(in_file, buf); -- Read line by line
read(buf, data); -- Read string into a real
dout <= to_sfixed(data ,dout); -- Convert to fixed-point
end if;
end process;
end sim;
| apache-2.0 |
Cognoscan/BoostDSP | vhdl/src/DNU/lfsr_pkg.vhd | 1 | 2531 | library ieee;
use ieee.std_logic_1164.all;
package lfsr_pkg is
function Maximal_Polynomial(size : positive) return std_logic_vector;
end package;
package body lfsr_pkg is
function Maximal_Polynomial(size : positive) return std_logic_vector is
variable polynomial : std_logic_vector((size - 1) downto 0);
begin
-- Polynomials taken from Xilinx App Note XAPP 052. Covers up to 168 bits.
-- Only the first 32 maximal-length polynomials are recorded here.
-- Retrieved on Aug 14, 2013 from
-- http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
-- TODO: Add all polynomials up to 168 bits, and verify completeness.
case size is
when 1 => polynomial := "1";
when 2 => polynomial := "11";
when 3 => polynomial := "110";
when 4 => polynomial := "1100";
when 5 => polynomial := "10100";
when 6 => polynomial := "110000";
when 7 => polynomial := "1100000";
when 8 => polynomial := "10111000";
when 9 => polynomial := "100010000";
when 10 => polynomial := "1001000000";
when 11 => polynomial := "10100000000";
when 12 => polynomial := "100000101001";
when 13 => polynomial := "1000000001101";
when 14 => polynomial := "10000000010101";
when 15 => polynomial := "110000000000000";
when 16 => polynomial := "1101000000001000";
when 17 => polynomial := "10010000000000000";
when 18 => polynomial := "100010000000000000";
when 19 => polynomial := "1000000000000100011";
when 20 => polynomial := "10010000000000000000";
when 21 => polynomial := "101000000000000000000";
when 22 => polynomial := "1100000000000000000000";
when 23 => polynomial := "10010000000000000000000";
when 24 => polynomial := "111000010000000000000000";
when 25 => polynomial := "1001000000000000000000000";
when 26 => polynomial := "10000000000000000000100011";
when 27 => polynomial := "100000000000000000000010011";
when 28 => polynomial := "1001000000000000000000000000";
when 29 => polynomial := "10100000000000000000000000000";
when 30 => polynomial := "100000000000000000000000101001";
when 31 => polynomial := "1001000000000000000000000000000";
when 32 => polynomial := "10000000001000000000000000000011";
when others =>
polynomial := (others => '0');
assert false report "No polynomial for given size" severity error;
end case;
return polynomial;
end function;
end package body;
| apache-2.0 |
Cognoscan/BoostDSP | vhdl/src/basic/symbolizer_even_ea.vhd | 1 | 3988 | --! @file symbolizer_even_ea.vhd
--! @brief Takes a parallel bus and maps it to symbols
--! @author Scott Teal ([email protected])
--! @date 2013-11-05
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
--! Takes parallel data and outputs it as shorter length data (symbols), for use
--! in passing to a symbol mapper. This symbolizer is built such that the length
--! of the parallel data should be a multiple of the symbol data length. If the
--! system does not adhere to this, then the entity "symbolizer" should be used
--! instead.
--!
--! When driving the fetch_symbol signal, allow at least three clock cycles
--! between each rising edge.
--!
--! Both data_valid and fetch_symbol are expected to be single clock cycle
--! strobes.
entity symbolizer_even is
port (
clk : in std_logic; --! System clock
rst : in std_logic; --! System reset
data_in : in std_logic_vector; --! Incoming data
busy : out std_logic; --! Busy (cannot fetch data)
data_valid : in std_logic; --! Strobe when data_in valid
fetch_symbol : in std_logic; --! System fetching next symbol
symbol_out : out std_logic_vector --! Outgoing symbol
);
end entity;
architecture rtl of symbolizer_even is
signal data_buffer : std_logic_vector(data_in'range);
signal symbol_buffer : std_logic_vector(symbol_out'range);
constant symbols_per_chunk : positive := data_in'length / symbol_out'length;
constant symbol_counter_length : positive :=
get_counter_width(symbols_per_chunk);
signal symbol_counter : unsigned((symbol_counter_length - 1) downto 0);
begin
-- Always state assumptions first
assert data_in'length mod symbol_out'length = 0
report "data_in's length must be a multiple of symbol_out's length"
severity error;
symbol_out <= symbol_buffer;
data_pipeline : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
symbol_buffer <= (others => '0');
data_buffer <= (others => '0');
symbol_counter <= to_unsigned(symbols_per_chunk, symbol_counter'length);
busy <= '0';
else
-- Pull symbols as required
if fetch_symbol = '1' then
-- The next symbol is unfetchable. Supply with 0.
if symbol_counter = to_unsigned(symbols_per_chunk,
symbol_counter'length) then
busy <= '0';
symbol_buffer <= (others => '0');
else
busy <= '1';
symbol_buffer <= data_buffer(((to_integer(symbol_counter) + 1)
* symbol_out'length - 1) downto
to_integer(symbol_counter) * symbol_out'length);
symbol_counter <= symbol_counter + 1;
end if;
else
-- The next symbol is unfetchable. More data needed.
if symbol_counter = to_unsigned(symbols_per_chunk,
symbol_counter'length) then
busy <= '0';
if data_valid = '1' then
data_buffer <= data_in;
busy <= '1';
symbol_counter <= to_unsigned(0, symbol_counter'length);
end if;
end if; -- unfetchable?
end if; -- symbol fetching
end if; -- rst
end if; -- clk
end process;
end rtl;
| apache-2.0 |
yoer/hue | tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
AntonMause/tcl4soc | g4rt/brdConst_pkg.vhd | 1 | 1624 |
----------------------------------------------------------------------
-- brdConst_pkg (for RTG4-ES & non ES)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '1';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
| apache-2.0 |
AntonMause/tcl4soc | g4rt/brdRstClkEs.vhd | 1 | 1779 |
----------------------------------------------------------------------
-- brdRstClk (for RTG4-ES)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- All chips but this one Sync up o_rst_n to fit to rising o_clk edge.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library rtg4;
use rtg4.all;
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic);
end brdRstClk;
----------------------------------------------------------------------
architecture rtl of brdRstClk is
component SYSRESET
port( DEVRST_N : in std_logic;
POWER_ON_RESET_N : out std_logic );
end component;
signal s_tgl, s_dly_n, s_rst_n : std_logic;
begin
SYSRESET_0 : SYSRESET
port map(
DEVRST_N => i_rst_n,
POWER_ON_RESET_N => s_rst_n );
-- Special for RT4G-ES AsyncReset SyncUp.
-- This silicon revision has only one async reset domain.
-- So this reset sync unit can not use async reset
process(i_clk)
begin
if (i_clk'event and i_clk = '1') then
if s_rst_n = '0' then
s_dly_n <= '0';
o_rst_n <= '0';
else
s_dly_n <= '1';
o_rst_n <= s_dly_n;
end if;
end if;
end process;
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
o_clk <= i_clk; -- 50MHz, direct
--o_clk <= s_tgl; -- 25MHz, divided
end rtl;
----------------------------------------------------------------------
| apache-2.0 |
AntonMause/tcl4soc | g4craft/brdConst_pkg.vhd | 1 | 1631 |
----------------------------------------------------------------------
-- brdConst_pkg (for EmCraft SoC FG484 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
| apache-2.0 |
AntonMause/tcl4soc | g3scs/brdRstClk.vhd | 1 | 2601 |
----------------------------------------------------------------------
-- brdRstClk (for SCS Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- Sync up o_rst_n to fit to rising edge of o_clk.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- 000000000000000000000000111111111111111111111111
-- 111110000011111000001111000001111100000111110000
--
-- 0 1 2 3 4 5 6 7 8 9
-- 024680246802468024680246802468024680246802468024
-- 135791357913579135791357913579135791357913579135
--
-- 1.1.1.1.1.0.0.0.0.0.1.1.1.1.1.0.0.0.0.0.1.1.1.1.
-- .1.1.1.1.1.0.0.0.0.0.1.1.1.1.0.0.0.0.0.1.1.1.1.1
-- 111111111100000000001111111110000000000111111111
-- 0 1 2 3 4
-- 012345678901234567890123456789012345678901234567
-- 0 1 2
-- 0.1.2.3.4.5.6.7.8.9.0.1.2.3.4.5.6.7.8.9.0.1.2.3.
--
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end brdRstClk;
----------------------------------------------------------------------
architecture rtl of brdRstClk is
signal s_tgl, s_dly_n, s_clk, s_rst_n, s_rst_one, s_rst_two : std_logic;
signal s_one, s_two : std_logic_vector(23 downto 0);
begin
process(i_clk, i_rst_n)
begin
if i_rst_n = '0' then
s_dly_n <= '0';
s_tgl <= '0';
o_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_tgl <= not s_tgl;
o_rst_n <= s_dly_n;
end if;
end process;
process(i_clk, s_rst_n)
begin
if (s_rst_n = '0') then
s_one <= "111110000011111000001111";
elsif (i_clk'event and i_clk = '1') then
s_one <= not s_one(0) & s_one(23 downto 1);
end if;
end process;
process(i_clk, s_rst_n)
begin
if (s_rst_n = '0') then
s_two <= "111110000011110000011111";
elsif (i_clk'event and i_clk = '0') then
s_two <= not s_two(0) & s_two(23 downto 1);
end if;
end process;
o_clk <= s_one(0) AND s_two(0); -- aprox 10MHz, stumbling
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
--o_clk <= i_clk; -- 48MHz, direct
--o_clk <= s_tgl; -- 24MHz, divided
end rtl;
----------------------------------------------------------------------
| apache-2.0 |
AntonMause/tcl4soc | stimulus/mySerTxd_tb.vhd | 1 | 3311 | ----------------------------------------------------------------------
-- Created by Microsemi SmartDesign Mon Apr 18 21:32:25 2016
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic
-- clock and reset pins connected. If your design has special
-- clock/reset or testbench driver requirements then you should
-- copy this file and modify it.
----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: mySerTxd_tb.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::SmartFusion2> <Die::M2S010S> <Package::144 TQ>
-- Author: <Name>
--
--------------------------------------------------------------------------------
-- for simulation, initialise vectors, edit code below in mySerTxd.vhd
-- signal bd_cur, bd_nxt : unsigned(c_bd_div_width downto 0) := (others=>'0');
-- signal s_dat, s_bsy : std_logic_vector(10 downto 0) := (others=>'0');
library ieee;
use ieee.std_logic_1164.all;
entity mySerTxd_tb is
end mySerTxd_tb;
architecture behavioral of mySerTxd_tb is
constant SYSCLK_PERIOD : time := 20 ns;
signal SYSCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal txd, busy, strobe : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := x"55";
component mySerTxd
generic (
baud : positive;
freq : positive );
port(
i_clk : in std_logic;
i_rst_n : in std_logic;
i_str : in std_logic;
i_dat : in std_logic_vector(7 downto 0);
o_bsy : out std_logic;
o_txd : out std_logic );
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 2 );
NSYSRESET <= '1';
wait for ( SYSCLK_PERIOD * 2 );
strobe <= '1';
wait for ( SYSCLK_PERIOD * 1 );
strobe <= '0';
wait for ( SYSCLK_PERIOD * 600 );
data <= x"33";
wait for ( SYSCLK_PERIOD * 1 );
strobe <= '1';
wait for ( SYSCLK_PERIOD * 1 );
strobe <= '0';
wait for ( SYSCLK_PERIOD * 600 );
data <= x"66";
wait for ( SYSCLK_PERIOD * 1 );
strobe <= '1';
wait for ( SYSCLK_PERIOD * 1 );
strobe <= '0';
wait for ( SYSCLK_PERIOD * 600 );
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
-- Instantiate Unit Under Test: mySerTxd
mySerTxd_0 : mySerTxd
generic map(
baud => 1,
freq => 32 )
port map(
i_clk => SYSCLK,
i_rst_n => NSYSRESET,
i_str => strobe,
i_dat => data,
o_bsy => busy,
o_txd => txd );
end behavioral;
| apache-2.0 |
AntonMause/tcl4soc | vhdl/OscXtlSer.vhd | 1 | 4386 |
----------------------------------------------------------------------
-- OscXtlSer
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Use External Xtal, adjust its signal to BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- Divide down to some Hz as stimulus pattern.
-- ->Send pattern via UART at 115200/921600 Baud
-- ->Receive at same rate and output BYTE to 8 LEDs.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.brdConst_pkg.all;
----------------------------------------------------------------------
entity OscXtlSer is
port( OSC_CLK : in std_logic;
DEVRST_N : in std_logic;
PB1 : in std_logic;
PB2 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
LED5 : out std_logic;
LED6 : out std_logic;
LED7 : out std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic );
end OscXtlSer;
architecture RTL of OscXtlSer is
----------------------------------------------------------------------
component brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end component;
component brdRstClk
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end component;
component myDffCnt
generic (N : Integer);
port ( i_rst_n, i_clk : in std_logic;
o_q : out std_logic_vector(N-1 downto 0) );
end component;
component mySerTxd
generic ( baud, freq : positive );
port ( i_clk : in std_logic;
i_rst_n : in std_logic;
i_str : in std_logic;
i_dat : in std_logic_vector(7 downto 0);
o_bsy : out std_logic;
o_txd : out std_logic );
end component;
component mySerRxd is
generic ( baud, freq : positive );
port (
i_clk : in std_logic;
i_rst_n : in std_logic;
i_rxd : in std_logic;
o_dat : out std_logic_vector(7 downto 0);
o_str : out std_logic );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
constant c_baud : positive := 115_200; -- default for most setups
--constant c_baud : positive := 921_600; -- maximum tested via USB
constant c_freq : positive := BRD_OSC_CLK_MHZ;
signal s_clk, s_rst_n, s_lex, s_pbx : std_logic;
signal s_cnt : std_logic_vector(28 downto 0);
signal s_dat, s_led : std_logic_vector(7 downto 0);
signal s_str, s_txd, s_one, s_two : std_logic;
begin
----------------------------------------------------------------------
brdRstClk_0 : brdRstClk
port map(
i_rst_n => DEVRST_N,
i_clk => OSC_CLK,
o_rst_n => s_rst_n,
o_clk => s_clk );
brdLexSwx_0 : brdLexSwx
port map(
o_lex => s_lex,
o_pbx => s_pbx );
myDffCnt_0 : myDffCnt
generic map( N => s_cnt'high+1 )
port map(
i_rst_n => s_rst_n,
i_clk => s_clk,
o_q => s_cnt );
process(s_clk, s_rst_n)
begin
if s_rst_n = '0' then
s_one <= '0';
s_two <= '0';
elsif (s_clk'event and s_clk = '1') then
s_one <= s_cnt(s_cnt'high -6);
s_two <= s_one;
s_str <= s_one and (not s_two);
end if;
end process;
s_dat <= "01" & s_cnt(s_cnt'high downto s_cnt'high-5);
mySerTxd_0 : mySerTxd
generic map(
baud => c_baud,
freq => c_freq )
port map( i_clk => s_clk,
i_rst_n => s_rst_n,
i_str => s_str,
i_dat => s_dat,
o_bsy => open,
o_txd => s_txd );
mySerRxd_0 : mySerRxd
generic map(
baud => c_baud,
freq => c_freq )
port map( i_clk => s_clk,
i_rst_n => s_rst_n,
i_rxd => UART_RXD,
o_dat => s_led,
o_str => open );
LED0 <= s_led(0) xor s_lex;
LED1 <= s_led(1) xor s_lex;
LED2 <= s_led(2) xor s_lex;
LED3 <= s_led(3) xor s_lex;
LED4 <= s_led(4) xor s_lex;
LED5 <= s_led(5) xor s_lex;
LED6 <= (s_led(6) xor s_lex) xor (PB2 xor s_pbx);
LED7 <= (s_led(7) xor s_lex) xor (PB1 xor s_pbx);
UART_TXD <= UART_RXD and s_txd;
end RTL; | apache-2.0 |
valptek/v586 | board_specific_files/esa11/freq_man.vhd | 1 | 2977 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity freq_man is
port
(
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
locked : out std_logic
);
end freq_man;
architecture syn of freq_man is
signal clk_in1 : std_logic;
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_int1 : std_logic;
signal clkout0b_unused : std_logic;
signal clk_int2 : std_logic;
signal clkout1b_unused : std_logic;
signal clk_int3 : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
signal psdone_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
clkin1_ibufgds : IBUFDS
port map
(O => clk_in1,
I => clk_in1_p,
IB => clk_in1_n);
iplle : PLLE2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 32,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 10.0)
port map
(
CLKFBOUT => clkfbout,
CLKOUT0 => clk_int1,
CLKOUT1 => clk_int2,
CLKOUT2 => clk_int3,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKFBIN => clkfbout,
CLKIN1 => clk_in1,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
LOCKED => locked,
PWRDWN => '0',
RST => '0');
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_int1);
clkout2_buf : BUFG
port map
(O => clk_out2,
I => clk_int2);
clkout3_buf : BUFG
port map
(O => clk_out3,
I => clk_int3);
end syn;
| apache-2.0 |
AntonMause/tcl4soc | g3afs/brdLexSwxAdv.vhd | 1 | 914 |
----------------------------------------------------------------------
-- brdLexSwx (for Fusion Advanced Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '1';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; | apache-2.0 |
AntonMause/tcl4soc | g3scs/brdLexSwx.vhd | 1 | 897 |
----------------------------------------------------------------------
-- brdLexSwx (for SCS Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; | apache-2.0 |
AntonMause/tcl4soc | g3afs/brdConstEmb_pkg.vhd | 1 | 1710 |
----------------------------------------------------------------------
-- brdConst_pkg (for Fusion Embeded Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
--constant BRD_OSC_CLK_MHZ : positive := 100_000_000; -- OnChp Osc
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct Xtl
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided Xtl
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '1';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '0';
end brdConst_pkg;
----------------------------------------------------------------------
| apache-2.0 |
AntonMause/tcl4soc | g3sfeva/brdLexSwx.vhd | 1 | 919 |
----------------------------------------------------------------------
-- brdLexSwx (for SmartFusion(1) Evaluation Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; | apache-2.0 |
AntonMause/tcl4soc | vhdl/mySerTxd.vhd | 1 | 2202 |
----------------------------------------------------------------------
-- mySerTxd.vhd
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- My simple fixed speed UART serial transmitter.
--
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
----------------------------------------------------------------------
entity mySerTxd is
generic (
baud : positive := 115_200;
freq : positive := 50_000_000);
port (
i_clk : in std_logic;
i_rst_n : in std_logic;
i_str : in std_logic;
i_dat : in std_logic_vector(7 downto 0);
o_bsy : out std_logic;
o_txd : out std_logic );
end mySerTxd;
----------------------------------------------------------------------
architecture rtl of mySerTxd is
constant c_bd_div : integer := ((freq / baud)-2);
constant c_bd_div_width : integer := integer(log2(real(c_bd_div))) + 1;
signal bd_cur, bd_nxt : unsigned(c_bd_div_width downto 0);
signal s_dat, s_bsy : std_logic_vector(10 downto 0);
signal s_tck : std_logic;
begin
process(i_clk) -- clock divider
begin
if (i_clk'event and i_clk = '1') then
if (bd_nxt(bd_nxt'length-1) = '1') then
bd_nxt <= to_unsigned(c_bd_div,bd_cur'length);
else
bd_nxt <= bd_nxt -1;
end if;
end if;
end process;
s_tck <= bd_nxt(bd_nxt'length-1);
process(i_clk,i_rst_n) -- transmitter
begin
if (i_rst_n='0') then
s_dat <= (others => '1');
s_bsy <= (others => '0');
elsif (i_clk'event and i_clk = '1') then
s_dat <= s_dat;
s_bsy <= s_bsy;
if (s_bsy(0) = '0') then
if (i_str = '1') then
s_dat <= '1' & i_dat & "01";
s_bsy <= (others => '1');
end if;
else
if (s_tck = '1') then
s_dat <= '1' & s_dat(s_dat'length-1 downto 1);
s_bsy <= '0' & s_bsy(s_bsy'length-1 downto 1);
end if;
end if;
end if;
end process;
o_bsy <= s_tck;
o_txd <= s_dat(0);
end rtl;
----------------------------------------------------------------------
| apache-2.0 |
AndrewSallans/osf.io | mfr/renderer/tabular/fixtures/test.vhd | 12226531 | 0 | apache-2.0 |
|
HackLinux/THCO-MIPS-CPU | src/MUX_2.vhd | 2 | 1322 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:42:26 11/25/2013
-- Design Name:
-- Module Name: MUX_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_2 is
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
end MUX_2;
architecture Behavioral of MUX_2 is
begin
process(SRC_1, SRC_2, SELEC)
begin
case SELEC is
when '0' =>
OUTPUT <= SRC_1;
when '1' =>
OUTPUT <= SRC_2;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
| apache-2.0 |
HackLinux/THCO-MIPS-CPU | src/Hazard_Detector.vhd | 2 | 27703 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:38:59 11/23/2013
-- Design Name:
-- Module Name: Hazard_Detector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Hazard_Detector is
Port ( STALL_OR_NOT_FU : in STD_LOGIC := STALL_NO;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0) := NOP_INST(15 downto 11);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(10 downto 8);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(7 downto 5);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(4 downto 2);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0):= NOP_INST(1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0) := HIGH_RESIST;
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0) := WRITE_DM_DATA_SRC_Z;
JUMP_OR_NOT : in STD_LOGIC := JUMP_FALSE;
WRITE_PC_OR_NOT : out STD_LOGIC := WRITE_PC_YES;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
WRITE_IR_OR_NOT : out STD_LOGIC := WRITE_IR_YES;
WRITE_IR_SRC_SELEC : out STD_LOGIC := WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC := COMMAND_ORIGIN;
DM_DATA_RESULT_SELEC : out STD_LOGIC := DM_DATA_RESULT_DM ;
IM_ADDR_SELEC : out STD_LOGIC := IM_ADDR_PC;
IM_DATA_SELEC : out STD_LOGIC := IM_DATA_Z;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0) := MEM_READ
);
end Hazard_Detector;
architecture Behavioral of Hazard_Detector is
signal never_used_pin : std_logic;
begin
never_used_pin <= STALL_OR_NOT_FU;
process (CUR_INST_CODE, CUR_INST_RS, CUR_INST_RT, CUR_INST_RD, CUR_INST_FUNC,
LAST_WRITE_REGS_OR_NOT, LAST_WRITE_REGS_TARGET, LAST_VISIT_DM_OR_NOT,
LAST_LAST_WRITE_REGS_OR_NOT, LAST_LAST_WRITE_REGS_TARGET,
LAST_LAST_VISIT_DM_OR_NOT, LAST_LAST_DM_VISIT_ADDR, CUR_DM_READ_WRITE, CUR_DM_WRITE_DATA_SRC, JUMP_OR_NOT)
variable inst_rd_func : std_logic_vector(4 downto 0);
variable stall_or_not : boolean := False;
variable write_dm_or_not : boolean := False;
variable write_data_a_flag : boolean := False;
variable write_data_b_flag : boolean := False;
variable write_a_flag : boolean := False;
variable write_b_flag : boolean := False;
variable a_conflict_flag : boolean := False;
variable b_conflict_flag : boolean := False;
begin
inst_rd_func(4 downto 2) := CUR_INST_RD;
inst_rd_func(1 downto 0) := CUR_INST_FUNC;
write_dm_or_not := (CUR_DM_READ_WRITE = MEM_WRITE) and (CUR_DM_READ_WRITE = MEM_WRITE);
write_data_a_flag := CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_A;
write_data_b_flag := CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_B;
write_a_flag := (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS);
write_b_flag := (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RT) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RT);
a_conflict_flag := write_data_a_flag and write_a_flag;
b_conflict_flag := write_data_b_flag and write_b_flag;
stall_or_not := write_dm_or_not and (a_conflict_flag or b_conflict_flag);
-- if forward unit call for stall, stop PC, IR, set CMD NOP
-- if (STALL_OR_NOT_FU = STALL_YES) then
-- WRITE_PC_OR_NOT <= WRITE_PC_NO ;
-- NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
-- WRITE_IR_OR_NOT <= WRITE_IR_NO ;
-- WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
-- COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- 暂且无谓暂停也无所谓
if (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and
(LAST_WRITE_REGS_TARGET = CUR_INST_RS or LAST_WRITE_REGS_TARGET = CUR_INST_RT) and
LAST_VISIT_DM_OR_NOT = MEM_READ) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- SW型指令要直接用到A或B的值，有可能存在数据冲突，若有，暂停
elsif (CUR_DM_READ_WRITE = MEM_WRITE and
((CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_A and
((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)))
or (CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_B and
((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RT) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RT))))) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
case CUR_INST_CODE is
-- B inst, must jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
when INST_CODE_B =>
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
when INST_CODE_BEQZ =>
-- BEQZ inst, if has data conflict, stall, stop PC, stop IR, set CMD to NOP
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
elsif (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
end if;
when INST_CODE_BNEZ =>
-- BNEZ inst, if has data conflict, stall, stop PC, stop IR, set CMD to NOP
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
elsif (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when INST_CODE_ADDSP_BTEQZ_MTSP =>
if (CUR_INST_RS = INST_RS_BTEQZ ) then
-- BTEQZ inst, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
if (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when INST_CODE_AND_TO_SLT =>
if (inst_rd_func = INST_RD_FUNC_JALR_JR_MFPC ) then
case CUR_INST_RT is
-- JALR inst, jump, set PC to reg A, set IR to NOP, keep CMD as origin
when INST_RT_JALR =>
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
-- JR inst, jump, set PC to reg A, set IR to NOP, keep CMD as origin
when INST_RT_JR =>
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when others =>
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end case;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when others =>
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end case;
end if;
end process;
end Behavioral;
| apache-2.0 |
HackLinux/THCO-MIPS-CPU | src/MEM_WB_Register.vhd | 2 | 2412 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:26:22 11/22/2013
-- Design Name:
-- Module Name: MEM_WB_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB_Register is
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
REGS_READ_WRITE_IN : in STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
REGS_READ_WRITE_OUT : out STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT
);
end MEM_WB_Register;
architecture Behavioral of MEM_WB_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
NEW_PC_OUT <= NEW_PC_IN;
WRITE_REGS_NUM_OUT <= WRITE_REGS_NUM_IN;
ALU_RESULT_OUT <= ALU_RESULT_IN;
IH_REG_OUT <= IH_REG_IN;
DM_DATA_OUT <= DM_DATA_IN;
REGS_READ_WRITE_OUT <= REGS_READ_WRITE_IN;
REGS_WRITE_DATA_SRC_OUT <= REGS_WRITE_DATA_SRC_IN;
end if;
end process;
end Behavioral;
| apache-2.0 |
HackLinux/THCO-MIPS-CPU | src/CLK_MODULE.vhd | 2 | 1465 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:32:35 11/22/2013
-- Design Name:
-- Module Name: MUX_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLK_MODULE is
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC := '1'
);
end CLK_MODULE;
architecture Behavioral of CLK_MODULE is
signal count : std_logic_vector(29 downto 0) := "000000000000000000000000000000";
begin
process (CLK_IN)
begin
if (CLK_IN'event and CLK_IN = '0') then
count <= count + 1;
--if (count = "000001010110001001011010000000") then
if (count = "000000000000000000000000000011") then
CLK <= not CLK;
count <= "000000000000000000000000000000";
end if;
end if;
end process;
end Behavioral;
| apache-2.0 |
HackLinux/THCO-MIPS-CPU | src/Special_Register.vhd | 2 | 2319 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:35 11/23/2013
-- Design Name:
-- Module Name: Special_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Special_Register is
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
RA_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
IH_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
SP_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO
);
end Special_Register;
architecture Behavioral of Special_Register is
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (T_cmd_write = WRITE_T_YES) then
if (T_cmd_src = T_SRC_IS_SF) then
if (T_src_SF = '1') then
T_value <= FFFF;
else
T_value <= ZERO;
end if;
elsif (T_cmd_src = T_SRC_IS_NOT_ZF) then
if (T_src_ZF = '0') then
T_value <= FFFF;
else
T_Value <= ZERO;
end if;
else
NULL;
end if;
end if;
if (RA_cmd_write = WRITE_RA_YES) then
RA_value <= RA_src;
end if;
if (IH_cmd_write = WRITE_IH_YES) then
IH_value <= IH_src;
end if;
if (SP_cmd_write = WRITE_SP_YES) then
SP_value <= SP_src;
end if;
end if;
end process;
end Behavioral; | apache-2.0 |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_infrared_test.vhdl | 1 | 5255 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2014
-- Description : This example awaits an interrupt from the
-- infra-red receiver, then displays the received
-- 8 bit on two hex displays (data is also send
-- to usb)
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
begin
process(ir_irq_rx, ir_din)
begin
-- default
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
-- on interrupt
if ir_irq_rx = '1' then
-- get rx-data
ir_cs <= '1';
ir_wr <= '0';
ir_addr <= CV_ADDR_IR_DATA;
ir_dout <= (others => '0');
-- ack interrupt
ir_ack_rx <= '1';
-- display rx-data on hex displays
sevenseg_cs <= '1';
sevenseg_wr <= '1';
sevenseg_addr <= CV_ADDR_SEVENSEG_HEX5 or CV_ADDR_SEVENSEG_HEX4;
sevenseg_dout(7 downto 0) <= ir_din(7 downto 0);
end if;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 |
Fju/LeafySan | src/vhdl/testbench/io_model.vhdl | 1 | 2497 | ---------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : simple filebased model for GP-In, Switches & Pushbuttons
-- Last update : 27.04.2015
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity io_model is
generic(
-- file containing static bit-settings for io's
FILE_NAME_SET : string := "io.txt"
);
port(
-- io's
gpio : inout std_logic_vector(15 downto 0);
switch : out std_ulogic_vector(17 downto 0);
key : out std_ulogic_vector(2 downto 0)
);
end io_model;
architecture sim of io_model is
-- file containing static bit-settings for io's
-- order of bits: gp_in(0) ... gp_in(15), switch(0) ... switch(17), key_n(0) ... key_n(2)
file file_set : text open read_mode is FILE_NAME_SET;
begin
process
variable active_line : line;
variable neol : boolean := false;
variable char_value : character := '0';
variable cnt : natural := 0;
begin
-- preset io's
switch <= (others => 'U');
key <= (others => 'U');
-- read bit-settings file
while not endfile(file_set) loop
-- read line
readline(file_set, active_line);
-- loop until end of line
loop
-- read integer from line
read(active_line, char_value, neol);
-- exit when line has ended
exit when not neol;
-- chancel when enough data is read
exit when cnt = 16 + 18 + 3;
-- write data to output
if cnt < 16 then
-- gpio
if char_value = '1' then
gpio(cnt) <= '1';
elsif char_value = '0' then
gpio(cnt) <= '0';
elsif char_value = 'Z' then
gpio(cnt) <= 'Z';
else
gpio(cnt) <= 'U';
end if;
elsif cnt < 16 + 18 then
-- switch
if char_value = '1' then
switch(cnt-16) <= '1';
elsif char_value = '0' then
switch(cnt-16) <= '0';
else
switch(cnt-16) <= 'U';
end if;
else
-- key
if char_value = '1' then
key(cnt-16-18) <= '1';
elsif char_value = '0' then
key(cnt-16-18) <= '0';
else
key(cnt-16-18) <= 'U';
end if;
end if;
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_set);
wait;
end process;
end sim;
| apache-2.0 |
Fju/LeafySan | src/vhdl/interfaces/seven_seg.vhdl | 1 | 7673 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : 7-Segment Display
-- Author : Jan Dürre
-- Last update : 22.07.2014
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity seven_seg is
port(
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- 7-Seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0)
);
end seven_seg;
architecture rtl of seven_seg is
-- array for easier use of hex0_n to hex7_n
type seg_t is array (0 to 3) of std_ulogic_vector(6 downto 0);
signal hex_seg, dec_seg : seg_t;
-- 7-Segment Displays
-- [][] [][] | [][][][]
-- hex-display | decimal-display (-999 to 999)
-- A4A3A2A1 | A0
-- +-----+
-- | 0 |
-- | 5 1 |
-- | 6 |
-- | 4 2 |
-- | 3 |
-- +-----+
-- register for each hex-display
type hex_display_t is array (0 to 3) of std_ulogic_vector(3 downto 0);
signal hex_display, hex_display_nxt : hex_display_t;
-- register for decimal-display and sign-symbol
signal dec_display, dec_display_nxt : std_ulogic_vector(to_log2(1000)-1 downto 0); -- 0...999
signal dec_sign, dec_sign_nxt : std_ulogic;
-- register to active 7-seg-displays
signal display_active, display_active_nxt : std_ulogic_vector(4 downto 0);
begin
-- connect and invert signal seg to output
hex0_n <= not dec_seg(0);
hex1_n <= not dec_seg(1);
hex2_n <= not dec_seg(2);
hex3_n <= not dec_seg(3);
hex4_n <= not hex_seg(0);
hex5_n <= not hex_seg(1);
hex6_n <= not hex_seg(2);
hex7_n <= not hex_seg(3);
-- sequential process
process(clock, reset_n)
begin
-- async reset
if reset_n = '0' then
hex_display <= (others => (others => '0'));
dec_display <= (others => '0');
dec_sign <= '0';
display_active <= (others =>'0');
elsif rising_edge(clock) then
hex_display <= hex_display_nxt;
dec_display <= dec_display_nxt;
dec_sign <= dec_sign_nxt;
display_active <= display_active_nxt;
end if;
end process;
-- bus interface
process(hex_display, dec_display, dec_sign, iobus_cs, iobus_addr, iobus_din, iobus_wr, display_active)
begin
-- standard: hold register values
hex_display_nxt <= hex_display;
dec_display_nxt <= dec_display;
dec_sign_nxt <= dec_sign;
display_active_nxt <= display_active;
-- dout always "0..0", no readable registers available
iobus_dout <= (others => '0');
-- chip select
if iobus_cs = '1' then
-- write (no read allowed)
if iobus_wr = '1' then
-- decode LSB: choose if hex_display or dec_display is changed
if iobus_addr(0) = '1' then
-- dec
-- check MSB for positive or negative number
if iobus_din(iobus_din'length-1) = '0' then
dec_display_nxt <= iobus_din(dec_display'length-1 downto 0);
dec_sign_nxt <= '0';
else
-- save positive value
dec_display_nxt <= std_ulogic_vector(-signed(iobus_din(dec_display'length-1 downto 0)));
dec_sign_nxt <= '1';
end if;
-- activate dec-display
display_active_nxt(0) <= '1';
else
-- hex
-- check bits 1 to 4 of iobus_addr
for i in 0 to 3 loop
-- check if register should be changed
if iobus_addr(i+1) = '1' then
-- write date to array
hex_display_nxt(i) <= iobus_din(i*4 + 3 downto i*4);
-- activate display
display_active_nxt(i+1) <= '1';
end if;
end loop;
end if;
end if;
end if;
end process;
-- decode LUT for hex-displays
process(hex_display, display_active)
begin
-- for each hex-display
for i in 0 to 3 loop
-- check if display is active / has been written to
if display_active(i+1) = '1' then
case hex_display(i) is
when "0000" => hex_seg(i) <= "0111111"; -- 0
when "0001" => hex_seg(i) <= "0000110"; -- 1
when "0010" => hex_seg(i) <= "1011011"; -- 2
when "0011" => hex_seg(i) <= "1001111"; -- 3
when "0100" => hex_seg(i) <= "1100110"; -- 4
when "0101" => hex_seg(i) <= "1101101"; -- 5
when "0110" => hex_seg(i) <= "1111101"; -- 6
when "0111" => hex_seg(i) <= "0000111"; -- 7
when "1000" => hex_seg(i) <= "1111111"; -- 8
when "1001" => hex_seg(i) <= "1101111"; -- 9
when "1010" => hex_seg(i) <= "1110111"; -- A
when "1011" => hex_seg(i) <= "1111100"; -- b
when "1100" => hex_seg(i) <= "0111001"; -- C
when "1101" => hex_seg(i) <= "1011110"; -- d
when "1110" => hex_seg(i) <= "1111001"; -- E
when "1111" => hex_seg(i) <= "1110001"; -- F
when others => hex_seg(i) <= "1111001"; -- wrong value: display E
end case;
-- deactivate display
else
hex_seg(i) <= (others => '0');
end if;
end loop;
end process;
-- decode LUT for dec-display
process(dec_display, dec_sign, display_active)
variable bcd : std_ulogic_vector(11 downto 0);
begin
-- check if display is active / has been written to
if display_active(0) = '1' then
-- if value is too big
if unsigned(dec_display) > to_unsigned(999, dec_display'length) then
-- display E (for "Error")
dec_seg(0) <= "1111001";
dec_seg(1) <= "0000000";
dec_seg(2) <= "0000000";
dec_seg(3) <= "0000000";
else
-- convert binary to bcd
bcd := to_bcd(dec_display, 3);
-- for each bcd digit
for i in 0 to 2 loop
if bcd((i+1)*4 -1 downto i*4) = "0000" then dec_seg(i) <= "0111111"; -- 0
elsif bcd((i+1)*4 -1 downto i*4) = "0001" then dec_seg(i) <= "0000110"; -- 1
elsif bcd((i+1)*4 -1 downto i*4) = "0010" then dec_seg(i) <= "1011011"; -- 2
elsif bcd((i+1)*4 -1 downto i*4) = "0011" then dec_seg(i) <= "1001111"; -- 3
elsif bcd((i+1)*4 -1 downto i*4) = "0100" then dec_seg(i) <= "1100110"; -- 4
elsif bcd((i+1)*4 -1 downto i*4) = "0101" then dec_seg(i) <= "1101101"; -- 5
elsif bcd((i+1)*4 -1 downto i*4) = "0110" then dec_seg(i) <= "1111101"; -- 6
elsif bcd((i+1)*4 -1 downto i*4) = "0111" then dec_seg(i) <= "0000111"; -- 7
elsif bcd((i+1)*4 -1 downto i*4) = "1000" then dec_seg(i) <= "1111111"; -- 8
elsif bcd((i+1)*4 -1 downto i*4) = "1001" then dec_seg(i) <= "1101111"; -- 9
else dec_seg(i) <= "1111001"; -- wrong value: display E
end if;
end loop;
-- sign-symbol
if dec_sign = '1' then
dec_seg(3) <= "1000000";
else
-- turn off sign-symbol
dec_seg(3) <= (others => '0');
end if;
end if;
-- deactivate display
else
dec_seg(0) <= (others => '0');
dec_seg(1) <= (others => '0');
dec_seg(2) <= (others => '0');
dec_seg(3) <= (others => '0');
end if;
end process;
end rtl; | apache-2.0 |
Fju/LeafySan | src/vhdl/testbench/uart_model.vhdl | 1 | 5319 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART-Model for Simulation
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity uart_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
-- file with data to be send to fpga
FILE_NAME_COMMAND : string := "command.txt";
-- file for dump of data, received by pc
FILE_NAME_DUMP : string := "dump.txt";
-- communication speed for uart-link
BAUD_RATE : natural := 9600;
SIMULATION : boolean := true
);
port (
-- global signals
end_simulation : in std_ulogic;
-- uart-pins (pc side)
rx : in std_ulogic;
tx : out std_ulogic
);
end uart_model;
architecture sim of uart_model is
constant MAX_NO_OF_BYTES : natural := 128;
constant UART_BIT_TIME : time := 1 us * 1000000/BAUD_RATE;
file file_command : text open read_mode is FILE_NAME_COMMAND;
file file_dump : text open write_mode is FILE_NAME_DUMP;
type bytelist_t is array (0 to MAX_NO_OF_BYTES-1) of std_ulogic_vector(7 downto 0);
begin
-- send data to fpga
uart_send : process
variable commandlist : bytelist_t;
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer;
variable cnt : natural := 0;
begin
-- set line to "no data"
tx <= '1';
-- preload list with undefined
commandlist := (others => (others => 'U'));
-- read preload file
while not endfile(file_command) loop
-- read line
readline(file_command, active_line);
-- loop until end of line
loop
read(active_line, data_value, neol);
exit when not neol;
-- write command to array
commandlist(cnt) := std_ulogic_vector(to_signed(data_value, 8));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_command);
-- send data to fpga
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if byte is valid, else stop
if commandlist(i)(0) /= 'U' then
-- uart send procedure
-- wait some cycles before start
wait for 10*SYSTEM_CYCLE_TIME;
-- start bit
tx <= '0';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- loop over data
for j in 0 to 7 loop
tx <= commandlist(i)(j);
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- stop bit
tx <= '1';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
write(active_line, string'("[UART] Sent "));
write(active_line, to_integer(unsigned(commandlist(i))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(commandlist(i)));
write(active_line, string'(") to FPGA."));
writeline(output, active_line);
-- wait for some cycles before continuing
wait for 10*SYSTEM_CYCLE_TIME;
end if;
end loop;
-- wait forever
wait;
end process uart_send;
-- receive data from fpga
uart_receive : process
variable receivelist : bytelist_t;
variable cnt : integer;
variable active_line : line;
begin
-- initialize receive buffer
receivelist := (others => (others => 'U'));
cnt := 0;
-- always detect in the centre of a bit
if SIMULATION = false then wait for UART_BIT_TIME*0.5;
else wait for SYSTEM_CYCLE_TIME*16*0.5;
end if;
loop
-- stop when simulation is ended
exit when end_simulation = '1';
-- check if space in receive buffer is available, else break
exit when cnt = MAX_NO_OF_BYTES;
-- startbit detected
if rx = '0' then
--wait for first data bit
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- receive 8 bit
for i in 0 to 7 loop
receivelist(cnt)(i) := rx;
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- receive stop bit
if rx /= '1' then
-- stopbit not received!
write(active_line, string'("[UART] Expected Stop-Bit!"));
writeline(output, active_line);
else
write(active_line, string'("[UART] Received "));
write(active_line, to_integer(unsigned(receivelist(cnt))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(receivelist(cnt)));
write(active_line, string'(") from FPGA."));
writeline(output, active_line);
end if;
-- inc counter
cnt := cnt + 1;
else
-- wait a cycle
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
-- loop over max number of bytes
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if recieved byte is valid, else stop
if receivelist(i)(0) /= 'U' then
-- add value to line (will result in one value per line)
write(active_line, to_integer(unsigned(receivelist(i))));
-- write line to file
writeline(file_dump, active_line);
end if;
end loop;
file_close(file_dump);
-- wait forever
wait;
end process uart_receive;
end sim; | apache-2.0 |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_lcd_test_printout_text.vhdl | 1 | 6784 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : This example sends a predefined text to the LCD
-- display.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_WAIT_KEY, S_PRINT_TO_LCD, S_FINISH);
signal state, state_nxt : state_t;
-- Define a constant array with the hex-codes of every single character to print them on the LC-Display
constant lcd_commands : lcd_commands_t(0 to 24) := lcd_cmd( asciitext(" Invent A Chip! ") & lcd_cursor_pos(1,4) & asciitext("IMS 2015") );
-- Define a counter to count the printed characters
signal count, count_nxt : unsigned(4 downto 0);
begin
-- Sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
count <= (others => '0');
state <= S_WAIT_KEY;
elsif rising_edge(clock) then
count <= count_nxt;
state <= state_nxt;
end if;
end process;
-- Combinational process contains logic only
process(state, lcd_irq_rdy, key, count)
begin
-- Default assignment for the green LEDs (not used in this example)
led_green <= (others => '0');
-- Default assignment for all red LEDs (not used in this example)
led_red <= (others => '0');
-- Set default values for the internal bus -> zero on all signals means, nothing will happen
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- Hold previous values of all registers
count_nxt <= count;
state_nxt <= state;
case state is
-- Wait until KEY0 is triggered
when S_WAIT_KEY =>
led_green(0) <= '1';
if key(0) = '1' then
state_nxt <= S_PRINT_TO_LCD;
end if;
-- Read value from ADC and save it into the led_out-register
when S_PRINT_TO_LCD =>
led_green(1) <= '1';
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Enable the Write-Select signal
lcd_wr <= '1';
-- Take the new data from character array, the position is given by the character counter
lcd_dout(7 downto 0) <= lcd_commands(to_integer(count));
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Increment the counter to count the printed characters
count_nxt <= count + to_unsigned(1, count'length);
-- The next state depends on the counter or on how many characters got already printed
if count = to_unsigned(lcd_commands'length-1, count'length) then
state_nxt <= S_FINISH;
end if;
end if;
-- Endless loop -> never leave this state
when S_FINISH =>
led_green(2) <= '1';
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_lcd_test_switch_commands.vhdl | 1 | 6072 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : With this example it is possible to generate
-- control-commands for the LCD-Display by using
-- switch 0 to 7. The command is send by pressing
-- key 0.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_WAIT_KEY_PRESS, S_SEND_DATA, S_WAIT_KEY_RELEASE);
signal state, state_nxt : state_t;
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state <= S_WAIT_KEY_PRESS;
elsif rising_edge(clock) then
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, lcd_irq_rdy, key, switch)
begin
-- set default values for the internal bus -> zero on all signals means, nothing will happen
lcd_cs <= '0';
lcd_wr <= '0';
lcd_dout <= (others => '0');
lcd_addr <= (others => '0');
lcd_ack_rdy <= '0';
-- hold previous values of all registers
state_nxt <= state;
case state is
-- Wait until KEY0 is triggered
when S_WAIT_KEY_PRESS =>
if key(0) = '1' then
-- next state
state_nxt <= S_SEND_DATA;
end if;
-- Read value from ADC and save it into the led_out-register
when S_SEND_DATA =>
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Enable the Write-Select signal
lcd_wr <= '1';
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Take the new data from the first eight switches (SW0 to SW7)
lcd_dout(7 downto 0) <= switch(7 downto 0);
-- next state
state_nxt <= S_WAIT_KEY_RELEASE;
end if;
-- Wait until KEY0 is released
when S_WAIT_KEY_RELEASE =>
if key(0) = '0' then
-- next state
state_nxt <= S_WAIT_KEY_PRESS;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 |
hoglet67/AtomFpga | src/common/AVR8/resync/rsnc_l_bit.vhd | 4 | 1624 | --**********************************************************************************************
-- Resynchronizer (for bit) with latch
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_l_bit is generic(
tech : integer := 0;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end rsnc_l_bit;
architecture rtl of rsnc_l_bit is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic;
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
-- Latch
latch_prc:process(clk)
begin
if(clk='0') then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
-- Latch
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
| apache-2.0 |
hoglet67/AtomFpga | src/common/AVR8/Core/pm_fetch_dec.vhd | 4 | 70670 | --************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe outputs
-- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
-- SLEEP and CLRWDT instructions support was added
-- V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
-- V-flag bug fixed (ADIW/SBIW)
-- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
-- Output alu_data_d_in[7..0] was removed.
-- Gloabal clock enable(cp2en) was added
-- cpu_busy(push/pop) + irq bug was fixed 14.07.05
-- BRXX+IRQ interaction was modified -> cpu_busy
-- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity pm_fetch_dec is port(
-- Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep
sleepi : out std_logic;
irqok : out std_logic;
--Watchdog
wdri : out std_logic;
-- ALU interface(Data inputs)
alu_data_r_in : out std_logic_vector(7 downto 0);
-- ALU interface(Instruction inputs)
idc_add_out : out std_logic;
idc_adc_out : out std_logic;
idc_adiw_out : out std_logic;
idc_sub_out : out std_logic;
idc_subi_out : out std_logic;
idc_sbc_out : out std_logic;
idc_sbci_out : out std_logic;
idc_sbiw_out : out std_logic;
adiw_st_out : out std_logic;
sbiw_st_out : out std_logic;
idc_and_out : out std_logic;
idc_andi_out : out std_logic;
idc_or_out : out std_logic;
idc_ori_out : out std_logic;
idc_eor_out : out std_logic;
idc_com_out : out std_logic;
idc_neg_out : out std_logic;
idc_inc_out : out std_logic;
idc_dec_out : out std_logic;
idc_cp_out : out std_logic;
idc_cpc_out : out std_logic;
idc_cpi_out : out std_logic;
idc_cpse_out : out std_logic;
idc_lsr_out : out std_logic;
idc_ror_out : out std_logic;
idc_asr_out : out std_logic;
idc_swap_out : out std_logic;
-- ALU interface(Data output)
alu_data_out : in std_logic_vector(7 downto 0);
-- ALU interface(Flag outputs)
alu_c_flag_out : in std_logic;
alu_z_flag_out : in std_logic;
alu_n_flag_out : in std_logic;
alu_v_flag_out : in std_logic;
alu_s_flag_out : in std_logic;
alu_h_flag_out : in std_logic;
-- General purpose register file interface
reg_rd_in : out std_logic_vector (7 downto 0);
reg_rd_out : in std_logic_vector (7 downto 0);
reg_rd_adr : out std_logic_vector (4 downto 0);
reg_rr_out : in std_logic_vector (7 downto 0);
reg_rr_adr : out std_logic_vector (4 downto 0);
reg_rd_wr : out std_logic;
post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : out std_logic;
reg_h_out : in std_logic_vector (15 downto 0);
reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z
reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
-- I/O register file interface
sreg_fl_in : out std_logic_vector(7 downto 0);
globint : in std_logic; -- SREG I flag
sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : in std_logic_vector(7 downto 0);
-- Bit processor interface
bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT
branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
sbi_st_out : out std_logic;
cbi_st_out : out std_logic;
idc_bst_out : out std_logic;
idc_bset_out : out std_logic;
idc_bclr_out : out std_logic;
idc_sbic_out : out std_logic;
idc_sbis_out : out std_logic;
idc_sbrs_out : out std_logic;
idc_sbrc_out : out std_logic;
idc_brbs_out : out std_logic;
idc_brbc_out : out std_logic;
idc_reti_out : out std_logic);
end pm_fetch_dec;
architecture RTL of pm_fetch_dec is
-- COPIES OF OUTPUTS
signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL
signal irqack_int : std_logic;
signal irqackad_int : std_logic_vector(irqackad'range);
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
-- NEW SIGNALS
signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
signal ram_adr_int : std_logic_vector (15 downto 0);
constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
--constant const_ram_to_io_c : std_logic_vector := "0001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x1FFF
constant const_ram_to_io_c : std_logic_vector := "0010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x2000 0x2FFF -> change by Zvonimir Bandic
constant const_ram_to_io_d : std_logic_vector := "00100000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x1000 0x3FFF
-- LD/LDD/ST/STD SIGNALS
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
-- PROGRAM COUNTER SIGNALS
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
signal program_counter : std_logic_vector (15 downto 0);
signal program_counter_in : std_logic_vector (15 downto 0);
signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
signal pc_low : std_logic_vector (7 downto 0);
signal pc_high : std_logic_vector (7 downto 0);
signal pc_low_en : std_logic;
signal pc_high_en : std_logic;
signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED
signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED
signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT
signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE
signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE
-- STATE MACHINES SIGNALS
signal irq_start : std_logic;
signal nirq_st0 : std_logic;
signal irq_st1 : std_logic;
signal irq_st2 : std_logic;
signal irq_st3 : std_logic;
signal ncall_st0 : std_logic;
signal call_st1 : std_logic;
signal call_st2 : std_logic;
signal call_st3 : std_logic;
signal nrcall_st0 : std_logic;
signal rcall_st1 : std_logic;
signal rcall_st2 : std_logic;
signal nicall_st0 : std_logic;
signal icall_st1 : std_logic;
signal icall_st2 : std_logic;
signal njmp_st0 : std_logic;
signal jmp_st1 : std_logic;
signal jmp_st2 : std_logic;
signal ijmp_st : std_logic;
signal rjmp_st : std_logic;
signal nret_st0 : std_logic;
signal ret_st1 : std_logic;
signal ret_st2 : std_logic;
signal ret_st3 : std_logic;
signal nreti_st0 : std_logic;
signal reti_st1 : std_logic;
signal reti_st2 : std_logic;
signal reti_st3 : std_logic;
signal brxx_st : std_logic; -- BRANCHES
signal adiw_st : std_logic;
signal sbiw_st : std_logic;
signal nskip_inst_st0 : std_logic;
signal skip_inst_st1 : std_logic;
signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
signal skip_inst_start : std_logic;
signal nlpm_st0 : std_logic;
signal lpm_st1 : std_logic;
signal lpm_st2 : std_logic;
signal nelpm_st0 : std_logic;
signal elpm_st1 : std_logic;
signal elpm_st2 : std_logic;
--signal nsts_st0 : std_logic;
--signal sts_st1 : std_logic;
--signal sts_st2 : std_logic;
signal sts_st : std_logic;
--signal nlds_st0 : std_logic;
--signal lds_st1 : std_logic;
--signal lds_st2 : std_logic;
signal lds_st : std_logic;
signal st_st : std_logic;
signal ld_st : std_logic;
signal sbi_st : std_logic;
signal cbi_st : std_logic;
signal push_st : std_logic;
signal pop_st : std_logic;
-- INTERNAL STATE MACHINES
signal nop_insert_st : std_logic;
signal cpu_busy : std_logic;
-- INTERNAL COPIES OF OUTPUTS
signal pc_int : std_logic_vector (15 downto 0);
signal adr_int : std_logic_vector (15 downto 0);
signal iore_int : std_logic;
signal iowe_int : std_logic;
signal ramadr_int : std_logic_vector (15 downto 0);
signal ramre_int : std_logic;
signal ramwe_int : std_logic;
signal dbusout_int : std_logic_vector (7 downto 0);
-- COMMAND REGISTER
signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
signal instruction_reg_ena : std_logic; -- CLOCK ENABLE
-- IRQ INTERNAL LOGIC
signal irq_int : std_logic;
signal irq_vector_adr : std_logic_vector(15 downto 0);
-- INTERRUPT RELATING REGISTERS
signal pc_for_interrupt : std_logic_vector(15 downto 0);
-- DATA EXTRACTOR SIGNALS
signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT
signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD
signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS
signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET
signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> .......
signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ......
signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
-- INSTRUCTIONS DECODER SIGNALS
signal idc_adc : std_logic; -- INSTRUCTION ADC
signal idc_add : std_logic; -- INSTRUCTION ADD
signal idc_adiw : std_logic; -- INSTRUCTION ADIW
signal idc_and : std_logic; -- INSTRUCTION AND
signal idc_andi : std_logic; -- INSTRUCTION ANDI
signal idc_asr : std_logic; -- INSTRUCTION ASR
signal idc_bclr : std_logic; -- INSTRUCTION BCLR
signal idc_bld : std_logic; -- INSTRUCTION BLD
signal idc_brbc : std_logic; -- INSTRUCTION BRBC
signal idc_brbs : std_logic; -- INSTRUCTION BRBS
signal idc_bset : std_logic; -- INSTRUCTION BSET
signal idc_bst : std_logic; -- INSTRUCTION BST
signal idc_call : std_logic; -- INSTRUCTION CALL
signal idc_cbi : std_logic; -- INSTRUCTION CBI
signal idc_com : std_logic; -- INSTRUCTION COM
signal idc_cp : std_logic; -- INSTRUCTION CP
signal idc_cpc : std_logic; -- INSTRUCTION CPC
signal idc_cpi : std_logic; -- INSTRUCTION CPI
signal idc_cpse : std_logic; -- INSTRUCTION CPSE
signal idc_dec : std_logic; -- INSTRUCTION DEC
signal idc_elpm : std_logic; -- INSTRUCTION ELPM
signal idc_eor : std_logic; -- INSTRUCTION EOR
signal idc_icall : std_logic; -- INSTRUCTION ICALL
signal idc_ijmp : std_logic; -- INSTRUCTION IJMP
signal idc_in : std_logic; -- INSTRUCTION IN
signal idc_inc : std_logic; -- INSTRUCTION INC
signal idc_jmp : std_logic; -- INSTRUCTION JMP
signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q
signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q
signal idc_ldi : std_logic; -- INSTRUCTION LDI
signal idc_lds : std_logic; -- INSTRUCTION LDS
signal idc_lpm : std_logic; -- INSTRUCTION LPM
signal idc_lsr : std_logic; -- INSTRUCTION LSR
signal idc_mov : std_logic; -- INSTRUCTION MOV
signal idc_mul : std_logic; -- INSTRUCTION MUL
signal idc_neg : std_logic; -- INSTRUCTION NEG
signal idc_nop : std_logic; -- INSTRUCTION NOP
signal idc_or : std_logic; -- INSTRUCTION OR
signal idc_ori : std_logic; -- INSTRUCTION ORI
signal idc_out : std_logic; -- INSTRUCTION OUT
signal idc_pop : std_logic; -- INSTRUCTION POP
signal idc_push : std_logic; -- INSTRUCTION PUSH
signal idc_rcall : std_logic; -- INSTRUCTION RCALL
signal idc_ret : std_logic; -- INSTRUCTION RET
signal idc_reti : std_logic; -- INSTRUCTION RETI
signal idc_rjmp : std_logic; -- INSTRUCTION RJMP
signal idc_ror : std_logic; -- INSTRUCTION ROR
signal idc_sbc : std_logic; -- INSTRUCTION SBC
signal idc_sbci : std_logic; -- INSTRUCTION SBCI
signal idc_sbi : std_logic; -- INSTRUCTION SBI
signal idc_sbic : std_logic; -- INSTRUCTION SBIC
signal idc_sbis : std_logic; -- INSTRUCTION SBIS
signal idc_sbiw : std_logic; -- INSTRUCTION SBIW
signal idc_sbrc : std_logic; -- INSTRUCTION SBRC
signal idc_sbrs : std_logic; -- INSTRUCTION SBRS
signal idc_sleep : std_logic; -- INSTRUCTION SLEEP
signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx
signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx
signal idc_sts : std_logic; -- INSTRUCTION STS
signal idc_sub : std_logic; -- INSTRUCTION SUB
signal idc_subi : std_logic; -- INSTRUCTION SUBI
signal idc_swap : std_logic; -- INSTRUCTION SWAP
signal idc_wdr : std_logic; -- INSTRUCTION WDR
-- ADDITIONAL SIGNALS
signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS
-- ##################################################
-- SREG FLAGS WRITE ENABLE SIGNALS
alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0);
alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1);
alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2);
alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3);
alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4);
alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5);
alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6);
alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7);
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
signal sreg_adr_eq : std_logic;
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
begin
-- INSTRUCTION FETCH
instruction_reg_ena <= '1'; -- FOR TEST
instruction_fetch:process(cp2,ireset)
begin
if ireset='0' then -- RESET
instruction_reg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if instruction_reg_ena='1' then
instruction_reg <= inst;
end if;
end if;
end if;
end process;
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
two_word_inst <= '1' when
((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or -- CALL
(instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or -- JMP
(instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS
(instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000") -- STS
else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
dex_adr12mem_s <= instruction_reg(11 downto 0);
dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0);
dex_adr5port <= instruction_reg(7 downto 3);
dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0);
dex_condition <= instruction_reg(2 downto 0);
dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
dex_bitnum_sreg <= instruction_reg(6 downto 4);
dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0);
dex_adrreg_d <= instruction_reg(8 downto 4);
dex_brxx_offset <= instruction_reg(9 downto 3); -- OFFSET FOR BRBC/BRBS
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
--dex_adrindreg <= instruction_reg(3 downto 2);
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
latcht_rd_adr:process(cp2,ireset)
begin
if ireset ='0' then
dex_adrreg_d_latched <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or
idc_pop)='1' then
dex_adrreg_d_latched <= dex_adrreg_d;
end if;
end if;
end if;
end process;
-- +++++++++++++++++++++++++++++++++++++++++++++++++
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
adiw_sbiw_high_reg_adr:process(cp2,ireset)
begin
if ireset ='0' then
adiw_sbiw_encoder_mux_out <= (others=>'0');
elsif(cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1;
end if;
end if;
end process;
-- ##########################
-- NOP INSERTION
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
instruction_reg; -- Instruction
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
idc_add <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
idc_and <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
idc_asr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
idc_bld <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
idc_bst <= '1' when instruction_code_reg(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
idc_cbi <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
idc_com <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
idc_dec <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000
idc_eor <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
idc_in <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
idc_inc <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
idc_jmp <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
-- LD,LDD
idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0';
idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0';
idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0';
idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
-- ######
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000
idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
idc_mov <= '1' when instruction_code_reg(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
idc_or <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
idc_sbi <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
idc_sleep<= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
-- ST,STD
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
-- ######
idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
idc_wdr <= '1' when instruction_code_reg(15 downto 5)&instruction_code_reg(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
-- ADDITIONAL SIGNALS
idc_psinc <= '1' when (instruction_code_reg(1 downto 0) = "01" and
(idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and
(idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
-- ##########################################################################################################
-- WRITE ENABLE SIGNALS FOR ramadr_reg
ramadr_reg_en <= idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or idc_lds or -- LD/LDD/LDS(two cycle execution)
idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or idc_sts or -- ST/STS/STS(two cycle execution)
idc_push or idc_pop or
idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or -- RCALL/ICALL
call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ
idc_ret or (ret_st1 and not cpuwait ) or idc_reti or (reti_st1 and not cpuwait); -- RET/RETI -- ??
-- RAMADR MUX
ramadr_reg_in <= sph_out&spl_out when
(idc_rcall or (rcall_st1 and not cpuwait)or idc_icall or (icall_st1 and not cpuwait)or -- RCALL/ICALL
call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait) or -- CALL/IRQ
idc_push )='1' else -- PUSH
(sph_out&spl_out)+1 when (idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or idc_pop)='1' else -- RET/RETI/POP
inst when (idc_lds or idc_sts) ='1' else -- LDS/STS (two cycle execution)
reg_h_out when (idc_ld_x or idc_ld_y or idc_ld_z or idc_st_x or idc_st_y or idc_st_z)='1' else -- LD/ST
(reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD
-- ADDRESS REGISTER
ramadr_reg:process(cp2,ireset)
begin
if ireset='0' then
ramadr_int <= (others => '0');
elsif(cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if (ramadr_reg_en='1') then
ramadr_int <= ramadr_reg_in;
end if;
end if;
end if;
end process;
ramadr <= ramadr_int;
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
gp_reg_adr:process(cp2,ireset)
begin
if ireset='0' then
reg_file_adr_space <='0';
elsif(cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if (ramadr_reg_en='1') then
if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then
reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
else
reg_file_adr_space <= '0';
end if;
end if;
end if;
end if;
end process;
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
io_reg_adr:process(cp2,ireset)
begin
if ireset='0' then io_file_adr_space<='0';
elsif(cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if (ramadr_reg_en='1') then
if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b or ramadr_reg_in(15 downto 12)=const_ram_to_io_c) then
io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F) and ADRESS RANGE 0x1000-0x1FFF -> I/O PORTS (0x0FE0-0x1FDF) User Ports
else
io_file_adr_space <= '0';
end if;
end if;
end if;
end if;
end process;
-- ##########################################################################################################
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
-- WRITE ENABLE FOR Rd REGISTERS
alu_reg_wr <= idc_adc or idc_add or idc_adiw or adiw_st or idc_sub or idc_subi or idc_sbc or idc_sbci or
idc_sbiw or sbiw_st or idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or
idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or idc_swap;
reg_rd_wr <= idc_in or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
(pop_st or ld_st or lds_st)or -- POP/LD/LDD/LDS INSTRUCTIONS
((st_st or sts_st) and reg_file_adr_space)or -- ST/STD/STS INSTRUCTION
lpm_st2 or idc_ldi or idc_mov; -- LPM/LDI/MOV INSTRUCTION
reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
"00000" when lpm_st2='1' else
adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else
adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
dex_adrreg_d;
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
dex_adrreg_r;
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
reg_rd_in <= dbusin when (idc_in or ((lds_st or ld_st)and not reg_file_adr_space) or pop_st)='1' else -- FROM INPUT DATA BUS
reg_rr_out when ((lds_st or ld_st) and reg_file_adr_space)='1' else
gp_reg_tmp when ((st_st or sts_st) and reg_file_adr_space)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE)
bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND
reg_rr_out when (idc_mov='1')else -- FOR MOV INSTRUCTION
instruction_reg(15 downto 8) when (lpm_st2='1' and reg_z_out(0)='1') else -- LPM/ELPM
instruction_reg(7 downto 0) when (lpm_st2='1' and reg_z_out(0)='0') else -- LPM/ELPM
dex_dat8_immed when idc_ldi='1' else
alu_data_out; -- FROM ALU DATA OUT
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space); -- IN/SBI/CBI
iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or
((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
-- adr[5..0] BUS MULTIPLEXER
adr_int <= "0000000000"&dex_adr6port when (idc_in or idc_out) = '1' else -- IN/OUT INSTRUCTIONS
"0000000000"&'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC
"0000000000"&'0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else -- CBI/SBI (WRITE PHASE)
ramadr_int-x"20"; --(6)&ramadr_int(4 downto 0); -- LD/LDS/LDD/ST/STS/STD
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
-- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/
-- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI
DataMemoryRead:process(cp2,ireset)
begin
if ireset='0' then -- Reset
ramre_int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock enable
case ramre_int is
when '0' =>
if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and
ramadr_reg_in(15 downto 5)/=const_ram_to_reg and
(idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or -- LD/LDD instruction
idc_lds or -- LDS instruction(two cycle execution)
idc_pop or -- POP instruction
idc_ret or -- RET instruction
idc_reti)='1') -- RETI instruction
then ramre_int <='1';
end if;
when '1' =>
if ((ld_st or lds_st or pop_st or ret_st2 or reti_st2)and not cpuwait)='1' then
ramre_int <='0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
-- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
-- icall_st1 or icall_st2 or -- ICALL
-- call_st2 or call_st3 or -- CALL
-- irq_st2 or irq_st3); -- INTERRUPT
DataMemoryWrite:process(cp2,ireset)
begin
if ireset='0' then -- Reset
ramwe_int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock enable
case ramwe_int is
when '0' =>
if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
ramadr_reg_in(15 downto 12)/=const_ram_to_io_c and
ramadr_reg_in(15 downto 5)/=const_ram_to_reg and
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or -- ST/STD instruction
idc_sts or -- STS instruction (two cycle execution)
idc_push or -- PUSH instruction
idc_rcall or -- RCALL instruction
idc_icall or -- ICALL instruction
call_st1 or -- CALL instruction
irq_st1)='1') -- Interrupt
then ramwe_int <='1';
end if;
when '1' =>
if ((st_st or sts_st or push_st or rcall_st2 or
icall_st2 or call_st3 or irq_st3)and not cpuwait)='1' then ramwe_int <='0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- DBUSOUT MULTIPLEXER
dbusout_mux_logic: for i in dbusout_int'range generate
dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
(gp_reg_tmp(i) and (st_st or sts_st))or -- NEW
(bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
(program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
(program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
(pc_for_interrupt(i) and irq_st1) or
(pc_for_interrupt(i+8) and irq_st2) or
(reg_rd_out(i) and idc_out); -- OUT
end generate;
-- ALU CONNECTION
-- ALU Rr INPUT MUX
alu_data_r_in <= dex_dat8_immed when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else
"00"&dex_dat6_immed when (idc_adiw or idc_sbiw) ='1' else
"00000000" when (adiw_st or sbiw_st) ='1' else
reg_rr_out;
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
gp_registers_trig:process(cp2,ireset)
begin
if (ireset='0') then
gp_reg_tmp <= (others=>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
-- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE
if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or idc_sts)='1' then -- CLOCK ENABLE
gp_reg_tmp <= reg_rd_out;
end if;
end if;
end if;
end process;
-- **********************************************************************************************************
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
program_counter_high_store:process(cp2,ireset)
begin
if ireset='0' then -- RESET
program_counter_high_fr <=(others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if (idc_rcall or idc_icall or call_st1 or irq_st1) ='1' then
program_counter_high_fr <= program_counter(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
end if;
end if;
end if;
end process;
program_counter_for_lpm_elpm:process(cp2,ireset)
begin
if ireset='0' then -- RESET
program_counter_tmp<=(others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if (idc_lpm or idc_elpm) ='1' then
program_counter_tmp <= program_counter;
end if;
end if;
end if;
end process;
pa15_pm <= rampz_out(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
"1111111111"&dex_brxx_offset(5 downto 0); -- -
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- +
"11111"&dex_adr12mem_s(10 downto 0); -- -
program_counter <= pc_high&pc_low;
program_counter_in <= program_counter + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS
program_counter + offset_rxx when (idc_rjmp or idc_rcall)='1'else -- RJMP/RCALL
reg_z_out when (idc_ijmp or idc_icall)='1'else -- IJMP/ICALL
pa15_pm®_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM
instruction_reg when (jmp_st1 or call_st1)='1'else -- JMP/CALL
"0000000000"&irqackad_int&'0' when irq_st1 ='1' else -- INTERRUPT
dbusin&"00000000" when (ret_st1 or reti_st1)='1' else -- RET/RETI -> PC HIGH BYTE
"00000000"&dbusin when (ret_st2 or reti_st2)='1' else -- RET/RETI -> PC LOW BYTE
program_counter_tmp when (lpm_st1)='1' -- AFTER LPM/ELPM INSTRUCTION
else program_counter+1; -- THE MOST USUAL CASE
pc_low_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or
idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or
((sts_st or lds_st) and cpuwait)or
idc_adiw or idc_sbiw or
idc_push or idc_pop or
idc_cbi or idc_sbi or
rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or
ret_st1 or reti_st1);
pc_high_en <= not (idc_ld_x or idc_ld_y or idc_ld_z or idc_ldd_y or idc_ldd_z or
idc_st_x or idc_st_y or idc_st_z or idc_std_y or idc_std_z or
((sts_st or lds_st) and cpuwait) or
idc_adiw or idc_sbiw or
idc_push or idc_pop or
idc_cbi or idc_sbi or
rcall_st1 or icall_st1 or call_st2 or irq_st2 or cpuwait or
ret_st2 or reti_st2);
program_counter_low:process(cp2,ireset)
begin
if ireset='0' then -- RESET
pc_low<=(others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if pc_low_en ='1' then
pc_low <= program_counter_in(7 downto 0);
end if;
end if;
end if;
end process;
program_counter_high:process(cp2,ireset)
begin
if ireset='0' then -- RESET
pc_high<=(others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if pc_high_en ='1' then
pc_high <= program_counter_in(15 downto 8);
end if;
end if;
end if;
end process;
pc <= program_counter;
program_counter_for_interrupt:process(cp2,ireset)
begin
if ireset='0' then -- RESET
pc_for_interrupt <=(others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
if irq_start ='1' then
pc_for_interrupt <= program_counter;
end if;
end if;
end if;
end process;
-- END OF PROGRAM COUNTER
-- STATE MACHINES
skip_inst_start <= ((idc_sbrc or idc_sbrs or idc_sbic or idc_sbis) and bit_test_op_out)or
(idc_cpse and alu_z_flag_out);
skip_instruction_sm:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nskip_inst_st0 <= '0';
skip_inst_st1 <= '0';
skip_inst_st2 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nskip_inst_st0 <= (not nskip_inst_st0 and skip_inst_start) or
(nskip_inst_st0 and not((skip_inst_st1 and not two_word_inst) or skip_inst_st2));
skip_inst_st1 <= (not skip_inst_st1 and not nskip_inst_st0 and skip_inst_start);
skip_inst_st2 <= not skip_inst_st2 and skip_inst_st1 and two_word_inst;
end if;
end if;
end process;
alu_state_machines:process(cp2,ireset)
begin
if ireset='0' then -- RESET
adiw_st <= '0';
sbiw_st <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
adiw_st <= not adiw_st and idc_adiw;
sbiw_st <= not sbiw_st and idc_sbiw;
end if;
end if;
end process;
lpm_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nlpm_st0 <= '0';
lpm_st1 <= '0';
lpm_st2 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nlpm_st0 <= (not nlpm_st0 and (idc_lpm or idc_elpm)) or (nlpm_st0 and not lpm_st2);
lpm_st1 <= (not lpm_st1 and not nlpm_st0 and (idc_lpm or idc_elpm)); -- ??
lpm_st2 <= not lpm_st2 and lpm_st1;
end if;
end if;
end process;
lds_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
lds_st <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
lds_st <= (not lds_st and idc_lds) or (lds_st and cpuwait);
end if;
end if;
end process;
sts_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
sts_st <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
sts_st <= (not sts_st and idc_sts) or (sts_st and cpuwait);
end if;
end if;
end process;
jmp_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
njmp_st0 <= '0';
jmp_st1 <= '0';
jmp_st2 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
njmp_st0 <= (not njmp_st0 and idc_jmp) or (njmp_st0 and not jmp_st2);
jmp_st1 <= not jmp_st1 and not njmp_st0 and idc_jmp; -- ??
jmp_st2 <= not jmp_st2 and jmp_st1;
end if;
end if;
end process;
rcall_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nrcall_st0 <= '0';
rcall_st1 <= '0';
rcall_st2 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nrcall_st0 <= (not nrcall_st0 and idc_rcall) or (nrcall_st0 and not (rcall_st2 and not cpuwait));
rcall_st1 <= (not rcall_st1 and not nrcall_st0 and idc_rcall) or (rcall_st1 and cpuwait);
rcall_st2 <= (not rcall_st2 and rcall_st1 and not cpuwait) or (rcall_st2 and cpuwait);
end if;
end if;
end process;
icall_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nicall_st0 <= '0';
icall_st1 <= '0';
icall_st2 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nicall_st0 <= (not nicall_st0 and idc_icall) or (nicall_st0 and not (icall_st2 and not cpuwait));
icall_st1 <= (not icall_st1 and not nicall_st0 and idc_icall) or (icall_st1 and cpuwait);
icall_st2 <= (not icall_st2 and icall_st1 and not cpuwait) or (icall_st2 and cpuwait);
end if;
end if;
end process;
call_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
ncall_st0 <= '0';
call_st1 <= '0';
call_st2 <= '0';
call_st3 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
ncall_st0 <= (not ncall_st0 and idc_call) or (ncall_st0 and not( call_st3 and not cpuwait));
call_st1 <= not call_st1 and not ncall_st0 and idc_call;
call_st2 <= (not call_st2 and call_st1) or (call_st2 and cpuwait);
call_st3 <= (not call_st3 and call_st2 and not cpuwait) or (call_st3 and cpuwait);
end if;
end if;
end process;
ret_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nret_st0 <= '0';
ret_st1 <= '0';
ret_st2 <= '0';
ret_st3 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nret_st0 <= (not nret_st0 and idc_ret) or (nret_st0 and not ret_st3);
ret_st1 <= (not ret_st1 and not nret_st0 and idc_ret) or (ret_st1 and cpuwait);
ret_st2 <= (not ret_st2 and ret_st1 and not cpuwait) or (ret_st2 and cpuwait) ;
ret_st3 <= not ret_st3 and ret_st2 and not cpuwait;
end if;
end if;
end process;
reti_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nreti_st0 <= '0';
reti_st1 <= '0';
reti_st2 <= '0';
reti_st3 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nreti_st0 <= (not nreti_st0 and idc_reti) or (nreti_st0 and not reti_st3);
reti_st1 <= (not reti_st1 and not nreti_st0 and idc_reti) or (reti_st1 and cpuwait);
reti_st2 <= (not reti_st2 and reti_st1 and not cpuwait) or (reti_st2 and cpuwait) ;
reti_st3 <= not reti_st3 and reti_st2 and not cpuwait;
end if;
end if;
end process;
-- INTERRUPT LOGIC AND STATE MACHINE
irq_int <= '0' when irqlines="00000000000000000000000" else '1';
irq_vector_adr(15 downto 6)<=(others => '0');
irq_vector_adr(0) <= '0';
-- PRIORITY ENCODER
irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002
"00010" when irqlines(1)='1' else -- 0x0004
"00011" when irqlines(2)='1' else -- 0x0006
"00100" when irqlines(3)='1' else -- 0x0008
"00101" when irqlines(4)='1' else -- 0x000A
"00110" when irqlines(5)='1' else -- 0x000C
"00111" when irqlines(6)='1' else -- 0x000E
"01000" when irqlines(7)='1' else -- 0x0010
"01001" when irqlines(8)='1' else -- 0x0012
"01010" when irqlines(9)='1' else -- 0x0014
"01011" when irqlines(10)='1' else -- 0x0016
"01100" when irqlines(11)='1' else -- 0x0018
"01101" when irqlines(12)='1' else -- 0x001A
"01110" when irqlines(13)='1' else -- 0x001C
"01111" when irqlines(14)='1' else -- 0x001E
"10000" when irqlines(15)='1' else -- 0x0020
"10001" when irqlines(16)='1' else -- 0x0022
"10010" when irqlines(17)='1' else -- 0x0024
"10011" when irqlines(18)='1' else -- 0x0026
"10100" when irqlines(19)='1' else -- 0x0028
"10101" when irqlines(20)='1' else -- 0x002A
"10110" when irqlines(21)='1' else -- 0x002C
"10111" when irqlines(22)='1' else -- 0x002E
"00000";
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
cpu_busy <= idc_adiw or idc_sbiw or idc_cbi or idc_sbi or
idc_rjmp or idc_ijmp or
idc_jmp or jmp_st1 or
-- idc_brbs or idc_brbc or -- Old variant
((idc_brbc or idc_brbs) and bit_test_op_out) or
idc_lpm or lpm_st1 or
skip_inst_start or (skip_inst_st1 and two_word_inst) or
idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z or (ld_st and cpuwait) or
idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z or (st_st and cpuwait) or
idc_lds or (lds_st and cpuwait) or
idc_sts or (sts_st and cpuwait) or
idc_rcall or rcall_st1 or (rcall_st2 and cpuwait) or -- RCALL
idc_icall or icall_st1 or (icall_st2 and cpuwait) or -- ICALL
idc_call or call_st1 or call_st2 or (call_st3 and cpuwait) or -- CALL
idc_push or (push_st and cpuwait) or -- PUSH (added 14.07.05)
idc_pop or (pop_st and cpuwait) or -- POP (added 14.07.05)
(idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI
(iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
nirq_st0 or
-- idc_ret or nret_st0 or -- Old variant
idc_ret or ret_st1 or ret_st2 or
-- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt.
idc_reti or reti_st1 or reti_st2;
sreg_adr_eq <= '1' when adr_int=SREG_Address else '0';
--irq_start <= irq_int and not cpu_busy and globint;
irq_start <= irq_int and not cpu_busy and globint;
irq_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
nirq_st0 <= '0';
irq_st1 <= '0';
irq_st2 <= '0';
irq_st3 <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
nirq_st0 <= (not nirq_st0 and irq_start) or (nirq_st0 and not (irq_st3 and not cpuwait));
irq_st1 <= (not irq_st1 and not nirq_st0 and irq_start);
irq_st2 <= (not irq_st2 and irq_st1) or (irq_st2 and cpuwait);
irq_st3 <= (not irq_st3 and irq_st2 and not cpuwait) or (irq_st3 and cpuwait);
end if;
end if;
end process;
irqack_reg:process(cp2,ireset)
begin
if ireset='0' then -- RESET
irqack_int<='0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
irqack_int<= not irqack_int and irq_start;
end if;
end if;
end process;
irqack <= irqack_int;
irqackad_reg:process(cp2,ireset)
begin
if ireset='0' then -- RESET
irqackad_int<=(others=>'0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
irqackad_int<=irq_vector_adr(5 downto 1);
end if;
end if;
end process;
irqackad <= irqackad_int;
-- *******************************************************************************************
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
rjmp_st <= '0';
ijmp_st <= '0';
push_st <= '0';
pop_st <= '0';
brxx_st <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
rjmp_st <= idc_rjmp; -- ??
ijmp_st <= idc_ijmp;
push_st <= (not push_st and idc_push) or (push_st and cpuwait);
pop_st <= (not pop_st and idc_pop) or (pop_st and cpuwait);
brxx_st <= not brxx_st and (idc_brbc or idc_brbs) and bit_test_op_out;
end if;
end if;
end process;
-- LD/LDD/ST/STD
ld_st_state_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
ld_st <= '0';
st_st <= '0';
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
ld_st <= (not ld_st and (idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z)) or (ld_st and cpuwait);
st_st <= (not st_st and (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)) or (st_st and cpuwait);
end if;
end if;
end process;
-- SBI/CBI
sbi_cbi_machine:process(cp2,ireset)
begin
if ireset='0' then -- RESET
sbi_st <= '0';
cbi_st <= '0';
cbi_sbi_io_adr_tmp <= (others => '0');
cbi_sbi_bit_num_tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- CLOCK
if (cp2en='1') then -- Clock enable
sbi_st <= not sbi_st and idc_sbi;
cbi_st <= not cbi_st and idc_cbi;
cbi_sbi_io_adr_tmp <= dex_adr5port;
cbi_sbi_bit_num_tmp <= dex_bitop_bitnum;
end if;
end if;
end process;
-- ########################################################################################
-- SREG FLAGS WRITE ENABLE LOGIC
bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
end generate;
sreg_c_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or
idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_com or idc_neg or
idc_cp or idc_cpc or idc_cpi or
idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(0);
sreg_z_wr_en <= idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or
idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or
idc_cp or idc_cpc or idc_cpi or
idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or
idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(1);
sreg_n_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or
idc_sbc or idc_sbci or sbiw_st or
idc_cp or idc_cpc or idc_cpi or
idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or
idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(2);
sreg_v_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or -- idc_adiw
idc_sbc or idc_sbci or sbiw_st or idc_neg or idc_com or -- idc_sbiw
idc_inc or idc_dec or
idc_cp or idc_cpc or idc_cpi or
idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(3) or
idc_and or idc_andi or idc_or or idc_ori or idc_eor; -- V-flag bug fixing
sreg_s_wr_en <= idc_add or idc_adc or adiw_st or idc_sub or idc_subi or
idc_sbc or idc_sbci or sbiw_st or
idc_cp or idc_cpc or idc_cpi or
idc_and or idc_andi or idc_or or idc_ori or idc_eor or idc_com or idc_neg or
idc_inc or idc_dec or idc_lsr or idc_ror or idc_asr or sreg_bop_wr_en(4);
sreg_h_wr_en <= idc_add or idc_adc or idc_sub or idc_subi or
idc_cp or idc_cpc or idc_cpi or
idc_sbc or idc_sbci or idc_neg or sreg_bop_wr_en(5);
sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6);
sreg_i_wr_en <= irq_st1 or reti_st3 or sreg_bop_wr_en(7); -- WAS "irq_start"
sreg_fl_in <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG
reti_st3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out;
-- #################################################################################################################
-- *********************************************************************************************
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS ****************************
-- *********************************************************************************************
-- FOR ALU
idc_add_out <= idc_add;
idc_adc_out <= idc_adc;
idc_adiw_out <= idc_adiw;
idc_sub_out <= idc_sub;
idc_subi_out <= idc_subi;
idc_sbc_out <= idc_sbc;
idc_sbci_out <= idc_sbci;
idc_sbiw_out <= idc_sbiw;
adiw_st_out <= adiw_st;
sbiw_st_out <= sbiw_st;
idc_and_out <= idc_and;
idc_andi_out <= idc_andi;
idc_or_out <= idc_or;
idc_ori_out <= idc_ori;
idc_eor_out <= idc_eor;
idc_com_out <= idc_com;
idc_neg_out <= idc_neg;
idc_inc_out <= idc_inc;
idc_dec_out <= idc_dec;
idc_cp_out <= idc_cp;
idc_cpc_out <= idc_cpc;
idc_cpi_out <= idc_cpi;
idc_cpse_out <= idc_cpse;
idc_lsr_out <= idc_lsr;
idc_ror_out <= idc_ror;
idc_asr_out <= idc_asr;
idc_swap_out <= idc_swap;
-- FOR THE BIT PROCESSOR
sbi_st_out <= sbi_st;
cbi_st_out <= cbi_st;
idc_bst_out <= idc_bst;
idc_bset_out <= idc_bset;
idc_bclr_out <= idc_bclr;
idc_sbic_out <= idc_sbic;
idc_sbis_out <= idc_sbis;
idc_sbrs_out <= idc_sbrs;
idc_sbrc_out <= idc_sbrc;
idc_brbs_out <= idc_brbs;
idc_brbc_out <= idc_brbc;
idc_reti_out <= idc_reti;
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
post_inc <= idc_psinc;
pre_dec <= idc_prdec;
reg_h_wr <= (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z) and (idc_psinc or idc_prdec);
reg_h_adr(0)<= idc_st_x or idc_ld_x;
reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y;
reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z;
-- STACK POINTER CONTROL
sp_ndown_up <= idc_pop or idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait); -- ?????????
sp_en <= idc_push or idc_pop or idc_rcall or (rcall_st1 and not cpuwait) or idc_icall or (icall_st1 and not cpuwait) or
idc_ret or (ret_st1 and not cpuwait) or idc_reti or (reti_st1 and not cpuwait) or
call_st1 or (call_st2 and not cpuwait) or irq_st1 or (irq_st2 and not cpuwait); --????????
branch <= dex_condition;
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
adr <= adr_int;
ramre <= ramre_int;
ramwe <= ramwe_int;
iore <= iore_int;
iowe <= iowe_int;
dbusout <= dbusout_int;
-- Sleep Control
sleepi <= idc_sleep;
irqok <= irq_int;
-- Watchdog
wdri <= idc_wdr;
-- ************************** JTAG OCD support ************************************
-- Change of flow
change_flow <= '0';
valid_instr <= '0';
end RTL;
| apache-2.0 |
hoglet67/AtomFpga | src/common/CpuWrapper.vhd | 1 | 2811 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CpuWrapper is
generic (
CImplDebugger : boolean := false;
CImplCpu65c02 : boolean := false
);
port (
clk_main : in std_logic;
clk_avr : in std_logic;
cpu_clken : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
RST_n : in std_logic;
PRST_n : in std_logic;
SO : in std_logic;
RDY : in std_logic;
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
R_W_n : out std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
avr_RxD : in std_logic;
avr_TxD : out std_logic
);
end CpuWrapper;
architecture BEHAVIORAL of CpuWrapper is
signal Addr_us : unsigned(15 downto 0);
signal Dout_us : unsigned(7 downto 0);
signal Din_us : unsigned(7 downto 0);
begin
---------------------------------------------------------------------
-- 6502 CPU (using T65 core)
---------------------------------------------------------------------
nmos: if not CImplCpu65c02 generate
cpu : entity work.T65 port map (
Mode => "00",
Abort_n => '1',
SO_n => SO,
Res_n => RST_n,
Enable => cpu_clken,
Clk => clk_main,
Rdy => RDY,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
R_W_n => R_W_n,
Sync => Sync,
A(23 downto 16) => open,
A(15 downto 0) => Addr(15 downto 0),
DI(7 downto 0) => Din(7 downto 0),
DO(7 downto 0) => Dout(7 downto 0)
);
avr_TxD <= '1';
end generate;
---------------------------------------------------------------------
-- 65C02 CPU (using AlanD core)
---------------------------------------------------------------------
-- TODO: Need to add RDY
cmos: if CImplCpu65c02 generate
inst_r65c02: entity work.r65c02 port map (
reset => RST_n,
clk => clk_main,
enable => cpu_clken,
nmi_n => NMI_n,
irq_n => IRQ_n,
di => Din_us,
do => Dout_us,
addr => Addr_us,
nwe => R_W_n,
sync => Sync
);
Din_us <= unsigned(Din);
Dout <= std_logic_vector(Dout_us);
Addr <= std_logic_vector(Addr_us);
avr_TxD <= '1';
end generate;
end BEHAVIORAL;
| apache-2.0 |
hoglet67/AtomFpga | src/common/T6502/T65_MCode.vhd | 1 | 44547 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
| apache-2.0 |
hoglet67/AtomFpga | src/xilinx/DCM/dcm3.vhd | 2 | 2057 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm3 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm3;
architecture BEHAVIORAL of dcm3 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.000 = 16MHz * 10 / 5
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 62.5,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 |
hoglet67/AtomFpga | src/xilinx/AtomFpga_OlimexModVGA.vhd | 1 | 8532 | --------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_OlimexModVGA.vhd
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_OlimexModVGA
--Device: spartan3A
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_OlimexModVGA is
port (clk_25M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
CE1 : out std_logic;
RAMWRn : out std_logic;
RAMOEn : out std_logic;
RamA : out std_logic_vector (15 downto 0);
RamD : inout std_logic_vector (15 downto 0);
audiol : out std_logic;
audioR : out std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic);
end AtomFpga_OlimexModVGA;
architecture behavioral of AtomFpga_OlimexModVGA is
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal Phi2 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(15 downto 0);
signal RAM_A : std_logic_vector(18 downto 0);
signal RAM_Din : std_logic_vector(7 downto 0);
signal RAM_Dout : std_logic_vector(7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector(18 downto 0);
signal ExternDin : std_logic_vector(7 downto 0);
signal ExternDout : std_logic_vector(7 downto 0);
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- TODO: The user_ values below are a hack
-- specifying 030000/008000 did not work, although it should!
-- there seems to be something different about the way the AT45DB041D is addressed
-- but that's not obvious in the data sheet
-- https://www.adestotech.com/wp-content/uploads/doc3595.pdf
-- start address of user data in FLASH as obtained from bitmerge.py
constant user_address : std_logic_vector(23 downto 0) := x"000000";
-- lenth of user data in FLASH = 32KB (8x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"038000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
inst_dcm2 : entity work.dcm2 port map(
CLKIN_IN => clk_25M00,
CLK0_OUT => clock_25,
CLKFX_OUT => clock_16);
inst_dcm3 : entity work.dcm3 port map (
CLKIN_IN => clock_16,
CLK0_OUT => clock_32,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => true,
CImplAtoMMC2 => false,
CImplGraphicsExt => false,
CImplSoftChar => false,
CImplSID => false,
CImplVGA80x40 => false,
CImplHWScrolling => false,
CImplMouse => false,
CImplUart => false,
CImplDoubleVideo => false,
CImplRamRomNone => true,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_main => clock_16,
clk_avr => clock_16,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
Phi2 => Phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => '1',
uart_TxD => open,
avr_RxD => '1',
avr_TxD => open,
LED1 => open,
LED2 => open,
charSet => '0'
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_16)
begin
if rising_edge(clock_16) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= ERSTn and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
gated_write => false,
user_length => user_length
)
port map(
clock => clock_16,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => RamOEn,
SRAM_nWE => RamWRn,
SRAM_nCS => CE1,
SRAM_A(20 downto 16) => open,
SRAM_A(15 downto 0) => RamA,
SRAM_D => RamD(7 downto 0),
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
RamD(15 downto 8) <= (others => 'Z');
MemProcess : process (clock_16)
begin
if rising_edge(clock_16) then
RAM_A <= ExternA xor ("000" & x"8000");
RAM_nCS <= not ExternCE;
RAM_nOE <= not ((not ExternWE) and ExternCE);
RAM_nWE <= not (ExternWE and ExternCE and phi2);
RAM_Din <= ExternDin;
end if;
end process;
ExternDout <= RAM_Dout;
end behavioral;
| apache-2.0 |
hoglet67/AtomFpga | src/common/AVR8/MemArbAndMux/MemAccessCompPack.vhd | 4 | 1997 | -- *****************************************************************************************
--
-- Version 0.1
-- Modified 24.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
package MemAccessCompPack is
component ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end component;
component MemRdMux is port(
slv_outs : in SlavesOutBus_Type;
ram_sel : in std_logic; -- Data RAM selection(optional input)
ram_dout : in std_logic_vector(7 downto 0); -- Data memory output
dout : out std_logic_vector(7 downto 0) -- Data output
);
end component;
component RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end component;
end MemAccessCompPack;
| apache-2.0 |
msiddalingaiah/TTA | VHDL/ArithmeticUnit.vhd | 1 | 4508 | --------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Entity: ArithmeticUnit
-- Date: 2014-12-02
-- Author: user
--
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Avoid using ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ArithmeticUnit is
generic (
DATA_WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 3;
DEPTH : natural := 32
);
port (
reset : in std_logic;
clock : in std_logic;
address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
read_enable : in std_logic;
write_enable : in std_logic;
busy : out std_logic
);
end ArithmeticUnit;
architecture arch of ArithmeticUnit is
type StackType is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal stack : StackType;
signal s0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sp : std_logic_vector(10-1 downto 0);
-- sp minus 1, avoids sp predecriment delay
signal spm1 : std_logic_vector(10-1 downto 0);
begin
data_out <= s0;
statemachine: block
type state_type is (IDLE, RUNNING, DONE);
signal state : state_type := IDLE;
begin
process(clock, reset)
begin
if reset = '1' then
state <= IDLE;
sp <= (others => '0');
spm1 <= (others => '1');
s0 <= (others => '0');
elsif rising_edge(clock) then
case state is
when IDLE =>
state <= RUNNING;
when RUNNING =>
if read_enable = '1' then
case to_integer(unsigned(address)) is
-- pop
when 0 =>
s0 <= stack(to_integer(unsigned(spm1)));
sp <= sp - 1;
spm1 <= spm1 - 1;
when others =>
end case;
elsif write_enable = '1' then
case to_integer(unsigned(address)) is
-- push
when 0 =>
s0 <= data_in;
stack(to_integer(unsigned(sp))) <= s0;
sp <= sp + 1;
spm1 <= spm1 + 1;
-- operation
when 1 =>
case to_integer(unsigned(data_in)) is
-- add
when 0 =>
s0 <= stack(to_integer(unsigned(spm1))) + s0;
sp <= sp - 1;
spm1 <= spm1 - 1;
-- subtract
when 1 =>
s0 <= stack(to_integer(unsigned(spm1))) - s0;
sp <= sp - 1;
spm1 <= spm1 - 1;
when others =>
end case;
when others =>
end case;
end if;
when DONE =>
state <= IDLE;
when others =>
state <= IDLE;
end case;
end if;
end process;
end block;
end arch; | apache-2.0 |
hoglet67/AtomFpga | src/common/AVR8/Core/reg_file.vhd | 4 | 10644 | --**********************************************************************************************
-- General purpose register file for the AVR Core
-- Version 1.4 (Special version for the JTAG OCD)
-- Modified 22.04.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
entity reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
reg_rd_in : in std_logic_vector(7 downto 0);
reg_rd_out : out std_logic_vector(7 downto 0);
reg_rd_adr : in std_logic_vector(4 downto 0);
reg_rr_out : out std_logic_vector(7 downto 0);
reg_rr_adr : in std_logic_vector(4 downto 0);
reg_rd_wr : in std_logic;
post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : in std_logic;
reg_h_out : out std_logic_vector(15 downto 0);
reg_h_adr : in std_logic_vector(2 downto 0); -- x,y,z
reg_z_out : out std_logic_vector(15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
);
end reg_file;
architecture RTL of reg_file is
type register_file_type is array(0 to 25) of std_logic_vector(7 downto 0);
type register_mux_type is array(0 to 31) of std_logic_vector(7 downto 0);
signal register_file : register_file_type;
signal r26h : std_logic_vector(7 downto 0);
signal r27h : std_logic_vector(7 downto 0);
signal r28h : std_logic_vector(7 downto 0);
signal r29h : std_logic_vector(7 downto 0);
signal r30h : std_logic_vector(7 downto 0);
signal r31h : std_logic_vector(7 downto 0);
signal register_wr_en : std_logic_vector(31 downto 0);
signal sg_rd_decode : std_logic_vector (31 downto 0);
signal sg_rr_decode : std_logic_vector (31 downto 0);
signal sg_tmp_rd_data : register_mux_type;
signal sg_tmp_rr_data : register_mux_type;
signal sg_adr16_postinc : std_logic_vector (15 downto 0);
signal sg_adr16_predec : std_logic_vector (15 downto 0);
signal reg_h_in : std_logic_vector (15 downto 0);
signal sg_tmp_h_data : std_logic_vector (15 downto 0);
begin
write_decode: for i in 0 to 31 generate
register_wr_en(i) <= '1' when (i=reg_rd_adr and reg_rd_wr='1') else '0';
end generate;
rd_mux_decode: for i in 0 to 31 generate
sg_rd_decode(i) <= '1' when (reg_rd_adr=i) else '0';
end generate;
rr_mux_decode: for i in 0 to 31 generate
sg_rr_decode(i) <= '1' when (reg_rr_adr=i) else '0';
end generate;
reg_z_out <= r31h&r30h; -- R31:R30 OUTPUT FOR LPM/ELPM INSTRUCTIONS
sg_tmp_rd_data(0) <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0');
read_rd_mux: for i in 1 to 25 generate
sg_tmp_rd_data(i) <= register_file(i) when sg_rd_decode(i)='1' else sg_tmp_rd_data(i-1);
end generate;
sg_tmp_rd_data(26) <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data(25);
sg_tmp_rd_data(27) <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data(26);
sg_tmp_rd_data(28) <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data(27);
sg_tmp_rd_data(29) <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data(28);
sg_tmp_rd_data(30) <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data(29);
sg_tmp_rd_data(31) <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data(30);
reg_rd_out <= sg_tmp_rd_data(31);
sg_tmp_rr_data(0) <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0');
read_rr_mux: for i in 1 to 25 generate
sg_tmp_rr_data(i) <= register_file(i) when sg_rr_decode(i)='1' else sg_tmp_rr_data(i-1);
end generate;
sg_tmp_rr_data(26) <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data(25);
sg_tmp_rr_data(27) <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data(26);
sg_tmp_rr_data(28) <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data(27);
sg_tmp_rr_data(29) <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data(28);
sg_tmp_rr_data(30) <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data(29);
sg_tmp_rr_data(31) <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data(30);
reg_rr_out <= sg_tmp_rr_data(31);
h_dat_mux_l:for i in 0 to 7 generate
sg_tmp_h_data(i) <= (r26h(i) and reg_h_adr(0)) or (r28h(i) and reg_h_adr(1)) or (r30h(i) and reg_h_adr(2));
end generate;
h_dat_mux_h:for i in 8 to 15 generate
sg_tmp_h_data(i) <= (r27h(i-8) and reg_h_adr(0)) or (r29h(i-8) and reg_h_adr(1)) or (r31h(i-8) and reg_h_adr(2));
end generate;
sg_adr16_postinc <= sg_tmp_h_data +1;
sg_adr16_predec <= sg_tmp_h_data -1;
-- OUTPUT TO THE ADDRESS BUS
reg_h_out <= sg_adr16_predec when (pre_dec='1') else -- PREDECREMENT
sg_tmp_h_data; -- NO PREDECREMENT
-- TO REGISTERS
reg_h_in <= sg_adr16_postinc when (post_inc='1') else -- POST INC
sg_adr16_predec; -- PRE DEC
-- Register file with global reset (for simulation)
RegFileWithRst:if CResetRegFile generate
R0_R25:process(cp2,ireset)
begin
if ireset='0' then
for i in 0 to 25 loop
register_file(i) <= (others =>'0');
end loop;
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in 0 to 25 loop
if register_wr_en(i)='1' then
register_file(i) <= reg_rd_in;
end if;
end loop;
end if;
end if;
end process;
-- R26 (LOW)
R26:process(cp2,ireset)
begin
if ireset='0' then
r26h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(26)='1' then
r26h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r26h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R27 (HIGH)
R27:process(cp2,ireset)
begin
if ireset='0' then
r27h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(27)='1' then
r27h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r27h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R28 (LOW)
R28:process(cp2,ireset)
begin
if ireset='0' then
r28h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(28)='1' then
r28h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r28h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R29 (HIGH)
R29:process(cp2,ireset)
begin
if ireset='0' then
r29h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(29)='1' then
r29h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r29h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R30 (LOW)
R30:process(cp2,ireset)
begin
if ireset='0' then
r30h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(30)='1' then
r30h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r30h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R31 (HIGH)
R31:process(cp2,ireset)
begin
if ireset='0' then
r31h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(31)='1' then
r31h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r31h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
end generate;
-- Register file without global reset (for synthesis)
RegFileWithoutRst:if not CResetRegFile generate
R0_R25:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in 0 to 25 loop
if register_wr_en(i)='1' then
register_file(i) <= reg_rd_in;
end if;
end loop;
end if;
end if;
end process;
-- R26 (LOW)
R26:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(26)='1' then
r26h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r26h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R27 (HIGH)
R27:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(27)='1' then
r27h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r27h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R28 (LOW)
R28:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(28)='1' then
r28h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r28h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R29 (HIGH)
R29:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(29)='1' then
r29h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r29h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R30 (LOW)
R30:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(30)='1' then
r30h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r30h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R31 (HIGH)
R31:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(31)='1' then
r31h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r31h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
end generate;
end RTL;
| apache-2.0 |
hoglet67/AtomFpga | src/xilinx/AtomFpga_Atom2K18.vhd | 1 | 50723 | --------------------------------------------------------------------------------
-- Copyright (c) 2020 David Banks and Roland Leurs
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_Atom2K18.vhd
-- /___/ /\ Timestamp : 13/06/2020
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_Atom2K18
--Device: Spartan6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity AtomFpga_Atom2K18 is
generic (
-- Design identifier, readable after configuration from #BFFB
DESIGN_NUM : integer := 0;
-- Set CImplCpu65c02 to true to use a 65C02 core rather than a 6502
CImplCpu65c02 : boolean := false;
-- Set CImplAtoMMC to true to use an internal AtoMMC
CImplAtoMMC2 : boolean := true;
-- Set CImplDebugger to true to enable the ICE-6502 Debugger
CImplDebugger : boolean := false;
-- Set CImplDebugger to true to enable the ICE-6502 Debugger
CImplSID : boolean := true
-- NOTE: If CImplAtoMMC2 and CImplDebugger are both true, several
-- smaller features are disabled to make space in the FPGA:
-- GODIL: SID and Mouse
--
-- If you are not happy with this, then you can experiment with
-- enabling individual features in the constants section below.
);
port (
-- Clock
clk_50 : in std_logic;
-- External Bus
bus_a : out std_logic_vector(18 downto 0);
bus_d : inout std_logic_vector(7 downto 0);
bus_blk_b : out std_logic;
bus_phi2 : out std_logic;
bus_rnw : out std_logic;
bus_nrds : out std_logic;
bus_nwds : out std_logic;
bus_sync : out std_logic;
bus_nmi_n : in std_logic;
bus_irq_n : in std_logic;
bus_rst_n : inout std_logic;
bus_rdy : in std_logic;
bus_so : in std_logic;
-- External device chip selects
cs_ram_n : out std_logic;
cs_rom_n : out std_logic;
cs_via_n : out std_logic;
cs_tube_n : out std_logic;
cs_buf_n : out std_logic;
buf_dir : out std_logic;
-- Video
vga_red1 : out std_logic; -- this is the MSB
vga_red2 : out std_logic;
vga_green1 : out std_logic; -- this is the MSB
vga_green2 : out std_logic;
vga_blue1 : out std_logic; -- this is the MSB
vga_blue2 : out std_logic;
vga_vsync : out std_logic;
vga_hsync : out std_logic;
-- Audio
audio : out std_logic;
dac_cs_n : out std_logic;
dac_sdi : out std_logic;
dac_ldac_n : out std_logic;
dac_sck : out std_logic;
-- Keyboard
kbd_pa : out std_logic_vector(3 downto 0);
kbd_pb : in std_logic_vector(7 downto 0);
kbd_pc : in std_logic_vector(6 downto 6);
-- Mouse
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
-- Cassette
cas_in : in std_logic;
cas_out : out std_logic;
-- Serial
serial_tx : out std_logic;
serial_rx : in std_logic;
-- SD Card
mmc_led_red : out std_logic;
mmc_led_green : out std_logic;
mmc_clk : out std_logic;
mmc_ss : out std_logic;
mmc_mosi : out std_logic;
mmc_miso : in std_logic;
-- LEDs on FPGA Module
led : out std_logic_vector(1 to 8);
-- Switches on FPGA Module
sw : in std_logic_vector(2 downto 1);
-- USB Uart on FPGA Module
avr_tx : out std_logic;
avr_rx : in std_logic
);
end AtomFpga_Atom2K18;
architecture behavioral of AtomFpga_Atom2K18 is
------------------------------------------------------
-- Constants controlling single features
------------------------------------------------------
-- Approx resource usage
--
-- (5,720) (32)
-- LUTs RamB16
-- Baseline 1197 5.5
-- CImplCpu65C02 -47 1.5
-- CImplAtoMMC2 1325 11
-- CImplDebugger 2342 11
-- CImplVGA80x40 116
-- CImplSID 826 2
-- CImplHWScrolling 90
-- CImplMouse 250 1
-- CImplUart 167
-- CImplDoubleVideo -35 4
-- CImplVIA 254
-- CImplLEDs 131
-- CImplProfilingCounters 174
-- CImplRTC 173
-- CImplSAM 136
-- CImplPAM 28
-- CImplPalette 100
-- CImplConfig 104
-- When both AtoMMC2 and Debugger are included, we need to disable other
-- features to make space
constant CImplMakeSpace1 : boolean := CImplAtoMMC2 and CImplDebugger and CImplSID;
constant CImplMakeSpace2 : boolean := CImplAtoMMC2 and CImplDebugger and not CImplSID;
-- GODIL features
constant CImplGraphicsExt : boolean := true;
constant CImplSoftChar : boolean := true;
constant CImplVGA80x40 : boolean := true;
constant CImplHWScrolling : boolean := not CImplMakeSpace1;
constant CImplMouse : boolean := not CImplMakeSpace1 and not CImplMakeSpace2;
constant CImplUart : boolean := not CImplMakeSpace1;
constant CImplDoubleVideo : boolean := not CImplMakeSpace1;
-- Atom2K18 features
constant CImplVIA : boolean := true;
constant CImplLEDs : boolean := true;
constant CImplProfilingCounters : boolean := not CImplMakeSpace1;
constant CImplRTC : boolean := not CImplMakeSpace1;
constant CImplSAM : boolean := true;
constant CImplPAM : boolean := true;
constant CImplPalette : boolean := true;
constant CImplConfig : boolean := true;
------------------------------------------------
-- Signals
------------------------------------------------
-- Clock generation
signal clk0 : std_logic;
signal clk1 : std_logic;
signal clk2 : std_logic;
signal clkfb : std_logic;
signal clkfb_buf : std_logic;
signal clkin_buf : std_logic;
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal clock_debugger : std_logic;
-- Reset generation
signal reset_n : std_logic;
signal int_reset_n : std_logic;
signal ext_reset_n : std_logic;
signal powerup_reset_n : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
-- External bus interface
signal phi2 : std_logic;
signal rnw : std_logic;
signal sync : std_logic;
-- 16 bit address generated by the CPU
signal cpu_a : std_logic_vector(15 downto 0);
-- 19 bit external address generated by the RamRom
signal extern_a : std_logic_vector(18 downto 0);
signal extern_din : std_logic_vector(7 downto 0);
signal extern_dout : std_logic_vector(7 downto 0);
signal extern_bus : std_logic;
signal extern_ce : std_logic;
signal extern_we : std_logic;
-- Audio mixer and DAC
constant dacwidth : integer := 16; -- this needs to match the MCP4822 frame size
signal atom_audio : std_logic;
signal sid_audio : std_logic_vector(17 downto 0);
signal cycle : std_logic_vector(6 downto 0);
signal audio_l : std_logic_vector(dacwidth - 1 downto 0);
signal audio_r : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_l : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_r : std_logic_vector(dacwidth - 1 downto 0);
-- Matrix Keyboard
signal ps2_kbd_enable : std_logic;
signal ps2_kbd_clk : std_logic;
signal ps2_kbd_data : std_logic;
signal int_kbd_pb : std_logic_vector(7 downto 0);
signal int_kbd_pc : std_logic_vector(6 downto 6);
-- External devices
signal extern_rom : std_logic;
signal extern_ram : std_logic;
signal extern_tube : std_logic;
signal extern_via : std_logic;
signal extern_pam : std_logic; -- enable for #B1xx
signal extern_sam_rd : std_logic; -- enable for #BFF0
signal extern_sam_wr : std_logic; -- enable for #BFF1
-- Internal devices
signal intern_led : std_logic;
signal intern_rtc : std_logic;
signal intern_pam_reg0 : std_logic; -- enable for #BFF8
signal intern_pam_reg1 : std_logic; -- enable for #BFF9
signal intern_sam_reg : std_logic; -- enable for #BFF2
signal intern_palette : std_logic; -- enable for #BD0x
signal intern_config : std_logic; -- enable for #BFFB
-- Reconfiguration
signal config_data : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(DESIGN_NUM, 8));
-- Colour palette registers
signal palette_data : std_logic_vector(7 downto 0);
signal logical_colour : std_logic_vector(3 downto 0);
signal physical_colour : std_logic_vector(5 downto 0);
type palette_type is array (0 to 15) of std_logic_vector(5 downto 0);
signal palette : palette_type := (
0 => "000000",
1 => "000011",
2 => "000100",
3 => "000111",
4 => "001000",
5 => "001011",
6 => "001100",
7 => "001111",
8 => "110000",
9 => "110011",
10 => "110100",
11 => "110111",
12 => "111000",
13 => "111011",
14 => "111100",
15 => "111111"
);
-- Video
signal vga_blank : std_logic;
signal hsync_vga : std_logic;
signal vsync_vga : std_logic;
signal red_vga : std_logic_vector(2 downto 0);
signal green_vga : std_logic_vector(2 downto 0);
signal blue_vga : std_logic_vector(2 downto 0);
-- PAM relayed signals
signal pam_page : std_logic_vector(8 downto 0);
-- SAM related signals
signal sam_rd_addr : std_logic_vector(17 downto 0);
signal sam_rd_next : std_logic_vector(17 downto 0);
signal sam_rd_inc : std_logic;
signal sam_wr_addr : std_logic_vector(17 downto 0);
signal sam_wr_next : std_logic_vector(17 downto 0);
signal sam_wr_inc : std_logic;
signal sam_empty : std_logic;
signal sam_full : std_logic;
signal sam_underflow : std_logic;
signal sam_overflow : std_logic;
signal sam_status : std_logic_vector(7 downto 0);
-- Switch debouncing
signal sw_pressed : std_logic_vector(2 downto 1);
-- LED control/ Speedometer
signal led_ctrl_reg : std_logic_vector(7 downto 0);
signal led_data_reg : std_logic_vector(7 downto 0);
signal last_sync : std_logic;
signal instr_count : unsigned(15 downto 0);
signal led_state : unsigned(3 downto 0);
signal led_data : std_logic_vector(7 downto 0);
-- RTC
signal rtc_seconds : std_logic_vector(7 downto 0);
signal rtc_minutes : std_logic_vector(7 downto 0);
signal rtc_hours : std_logic_vector(7 downto 0);
signal rtc_day : std_logic_vector(7 downto 0) := x"01";
signal rtc_month : std_logic_vector(7 downto 0) := x"01";
signal rtc_year : std_logic_vector(7 downto 0);
signal rtc_irq_flags : std_logic_vector(7 downto 0);
signal rtc_control : std_logic_vector(7 downto 0);
signal rtc_10hz : std_logic_vector(3 downto 0);
signal rtc_cnt : std_logic_vector(21 downto 0);
signal rtc_irq_n : std_logic := '1';
signal rtc_data : std_logic_vector(7 downto 0);
-- Interrupt logic
signal irq_n : std_logic := '1';
-- Debug mode
signal remote_access : std_logic;
signal debug_mode : std_logic;
begin
------------------------------------------------
-- Clock generation
--
-- from the on-board 50MHz Oscillator
-- using a PLL for the 16/32 MHz
-- using a DCM for the 25.175 MHz (approx)
------------------------------------------------
inst_clkin_buf : IBUFG
port map (
I => clk_50,
O => clkin_buf
);
inst_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16, -- 50 * 16 = 800
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50, -- 800 / 50 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 25, -- 800 / 25 = 32MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 31, -- 800 / 31 = 25.0864MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010
)
port map (
-- Output clocks
CLKFBOUT => clkfb,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
RST => '0',
-- Input clock control
CLKFBIN => clkfb_buf,
CLKIN => clkin_buf
);
inst_clkfb_buf : BUFG
port map (
I => clkfb,
O => clkfb_buf
);
inst_clk0_buf : BUFG
port map (
I => clk0,
O => clock_16
);
inst_clk1_buf : BUFG
port map (
I => clk1,
O => clock_32
);
inst_clk2_buf : BUFG
port map (
I => clk2,
O => clock_debugger
);
inst_DCM : DCM
generic map (
CLKFX_MULTIPLY => 11,
CLKFX_DIVIDE => 14,
CLKIN_PERIOD => 31.250,
CLK_FEEDBACK => "NONE"
)
port map (
CLKIN => clock_32,
CLKFB => '0',
RST => '0',
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
CLKFX => clock_25
);
--------------------------------------------------------
-- Reset generation
--------------------------------------------------------
-- The external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by AtomGodilVideo to initialize some of the registers
process (clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= reset_counter(reset_counter'high);
-- logically or the internal and external resets, for use in this file
-- this is now synchronised to the 32MHz clock
reset_n <= ext_reset_n and int_reset_n;
end if;
end process;
-- logically or the powerup and bus resets, to pass down to the core
ext_reset_n <= powerup_reset_n and bus_rst_n;
-- Drive the external reset low when there's a power up reset, or
-- when int_reset_n (currently just F10 on the PS/2 keyboard).
-- Otherwise, it becomes and input (there's a 3K3 external pullup)
bus_rst_n <= '0' when powerup_reset_n = '0' or int_reset_n = '0' else 'Z';
------------------------------------------------
-- Atom FPGA Core
------------------------------------------------
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplCpu65c02 => CImplCpu65c02,
CImplDebugger => CImplDebugger,
CImplSDDOS => false,
CImplAtoMMC2 => CImplAtoMMC2,
CImplGraphicsExt => CImplGraphicsExt,
CImplSoftChar => CImplSoftChar,
CImplSID => CImplSID,
CImplVGA80x40 => CImplVGA80x40,
CImplHWScrolling => CImplHWScrolling,
CImplMouse => CImplMouse,
CImplUart => CImplUart,
CImplDoubleVideo => CImplDoubleVideo,
CImplRamRomNone => false,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => true,
CImplRamRomSchakelKaart => false,
CImplVIA => CImplVIA,
CImplProfilingCounters => CImplProfilingCounters,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_main => clock_32,
clk_avr => clock_32, -- this is the AtoMMC AVR clock
clk_avr_debug => clock_debugger, -- this is the ICE6502 AVR clock
clk_dac => clock_32,
clk_32M00 => clock_32,
kbd_pa => kbd_pa,
kbd_pb => int_kbd_pb,
kbd_pc => int_kbd_pc,
ps2_clk => ps2_kbd_clk,
ps2_data => ps2_kbd_data,
ps2_mouse_clk => ps2_mouse_clk,
ps2_mouse_data => ps2_mouse_data,
powerup_reset_n => powerup_reset_n,
ext_reset_n => ext_reset_n,
int_reset_n => int_reset_n,
red => red_vga,
green => green_vga,
blue => blue_vga,
vsync => vsync_vga,
hsync => hsync_vga,
blank => vga_blank,
phi2 => phi2,
sync => sync,
rnw => rnw,
rdy => bus_rdy,
so => bus_so,
irq_n => irq_n,
nmi_n => bus_nmi_n,
addr => cpu_a,
ExternBus => extern_bus, -- active high external bus select
ExternCE => extern_ce, -- active high Ram/Rom chip select
ExternWE => extern_we, -- active high Ram/Rom write
ExternA => extern_a,
ExternDin => extern_din,
ExternDout => extern_dout,
sid_audio => open,
sid_audio_d => sid_audio,
atom_audio => atom_audio,
SDMISO => mmc_miso,
SDSS => mmc_ss,
SDCLK => mmc_clk,
SDMOSI => mmc_mosi,
uart_RxD => serial_rx,
uart_TxD => serial_tx,
avr_RxD => avr_rx,
avr_TxD => avr_tx,
cas_in => cas_in,
cas_out => cas_out,
LED1 => mmc_led_green,
LED2 => mmc_led_red,
charSet => '1'
);
------------------------------------------------
-- External bus
------------------------------------------------
-- 22/4/2019
--
-- I'm not happy with the design of the external bus interface, for the
-- following reasons:
--
-- 1. extern_we and extern_ce are mediated by the pluggable RAMROM modules
-- in AtomFpga_Core. This means they are not active when external devices
-- in Bxxx are accessed.
--
-- 2. As a work around, I've exposed the 6502 RNW (rnw) signal directly,
-- which is probably the right thing to do, as Atom2K18 does have a full
-- external bus. But it's now confusing as to when to use extern_we and
-- when to use rnw.
--
-- 3. It's not clear how addresses on extern_a correspond to what the CPU
-- accessed, again because this signal is the output of a RAMROM module.
--
-- 4. It seemed wrong to have to add ExternTube and ExternVIA signals to the
-- AtomFpga_Core. It should have been possible to implement these externally
-- in the FPGA target specific wrapper. But (3) made this difficult.
--
-- 5. The NRDS and NWDS signals are currently generated from the RAMROM
-- specific extern_ce and extern_we. It would be better if they uses
-- rnw and ignored extern_ce. But this is more dangerous, so lets
-- see how the current version works before breaking things more!
--
-- What's in place currently will work (I think) for the VIA and Tube, but
-- will not currently allow any devices to be added to the bus. Need to
-- talk with Roland about how he thinks the external bus should be mapped
-- into the Atom address space.
--
-- 22/4/2019
--
-- Roland's reply:
--
-- All addresses from #B000 - #BFFF should be external except for:
-- #B000 - #B003 (8255)
-- #B400 - #B403 (AtoMMC)
-- #B800 - #B80F (6522)
-- #BD00 - #BDFF (Godil + reserved address space)
-- #BFF0 - #BFFF (control registers, some addresses are reserved)
--
-- 23/4/2019
--
-- For consistency, I ended up using a minimum of 16-byte blocks.
-- This is all implemented in AtomFpga_Core
--
-- To answer my concerns above
-- 1. This is resolved by adding a seperate ExternBus output from the core
-- 2. I'm happy exposing RNW directly
-- 3. The RamRom modules should just output the CPU address when not selected
-- 4. ExternVia and ExternTube replaced with ExternBus
-- 5. Use ExternCE/ExternWE (for RamRom) and ExternBus/rnw (for Bus)
bus_phi2 <= phi2;
bus_rnw <= rnw;
bus_sync <= sync;
-- Used on the bus to enable I/O devices in a safe manner
bus_blk_b <= not extern_bus;
bus_a <= "1" & sam_rd_addr when extern_sam_rd = '1' and rnw = '1' and CImplSAM else
"1" & sam_wr_addr when extern_sam_wr = '1' and rnw = '0' and CImplSAM else
"00" & pam_page & extern_a(7 downto 0) when extern_pam = '1' and CImplPAM else
extern_a;
-- Enable data out of the FPGA onto the 3.3V databus in the following cases:
-- case 1. all writes from the "core"
-- case 2. reads that are internal to the "core", when debug mode enables
-- case 3. reads of the led registers, when debug mode enabled
-- case 4. reads of the rtc registers, when debug mode enabled
bus_d <= extern_din when phi2 = '1' and rnw = '0' else
extern_din when phi2 = '1' and extern_ce = '0' and extern_bus = '0' and debug_mode = '1' else
led_data when phi2 = '1' and intern_led = '1' and debug_mode = '1' and CImplLEDs else
rtc_data when phi2 = '1' and intern_rtc = '1' and debug_mode = '1' and CImplRTC else
palette_data when phi2 = '1' and intern_palette = '1' and debug_mode = '1' and CImplPalette else
config_data when phi2 = '1' and intern_config = '1' and debug_mode = '1' and CImplConfig else
sam_status when phi2 = '1' and intern_sam_reg = '1' and debug_mode = '1' and CImplSAM else
pam_page(7 downto 0) when phi2 = '1' and intern_pam_reg0 = '1' and debug_mode = '1' and CImplPAM else
"0000000" & pam_page(8) when phi2 = '1' and intern_pam_reg1 = '1' and debug_mode = '1' and CImplPAM else
"ZZZZZZZZ";
bus_nrds <= '0' when extern_ce = '1' and extern_we = '0' and phi2 = '1' else -- RamRom
'0' when extern_bus = '1' and rnw = '1' and phi2 = '1' else -- Bus
'1';
bus_nwds <= '0' when extern_ce = '1' and extern_we = '1' and phi2 = '1' else -- RamRom
'0' when extern_bus = '1' and rnw = '0' and phi2 = '1' else -- Bus
'1';
-- data back into the Atom Core
extern_dout <= led_data when intern_led = '1' and CImplLEDs else
rtc_data when intern_rtc = '1' and CImplRTC else
palette_data when intern_palette = '1' and CImplPalette else
config_data when intern_config = '1' and CImplConfig else
sam_status when intern_sam_reg = '1' and CImplSAM else
pam_page(7 downto 0) when intern_pam_reg0 = '1' and CImplPAM else
"0000000" & pam_page(8) when intern_pam_reg1 = '1' and CImplPAM else
bus_d;
------------------------------------------------
-- Interrupt logic
------------------------------------------------
irq_n <= bus_irq_n and rtc_irq_n;
------------------------------------------------
-- Sequential Access Memory (SAM)
------------------------------------------------
sam_block: if CImplSAM generate
process(clock_32)
begin
if rising_edge(clock_32) then
if intern_sam_reg = '1' and rnw = '0' and phi2 = '1' then
-- a write of '1' to SAM control register bit 0 clears the overflow error
if extern_din(0) = '1' then
sam_overflow <= '0';
end if;
-- a write of '1' to SAM control register bit 1 clears the underflow error
if extern_din(1) = '1' then
sam_underflow <= '0';
end if;
-- a write of '1' to SAM control register bit 2 resets everything
if extern_din(2) = '1' then
sam_rd_inc <= '0';
sam_wr_inc <= '0';
sam_rd_addr <= (others => '0');
sam_wr_addr <= (others => '0');
sam_underflow <= '0';
sam_overflow <= '0';
end if;
elsif extern_sam_rd = '1' and rnw = '1' and phi2 = '1' then
-- a read from the SAM data register
if sam_empty = '0' then
sam_rd_inc <= '1';
else
sam_underflow <= '1';
end if;
elsif extern_sam_wr = '1' and rnw = '0' and phi2 = '1' then
-- a write to the SAM data register
if sam_full = '0' then
sam_wr_inc <= '1';
else
sam_overflow <= '1';
end if;
elsif phi2 = '0' then
-- Handle the update of the SAM addresses as soon as Phi2 goes
-- low at the start of the next bus cycle
if sam_rd_inc = '1' then
sam_rd_addr <= sam_rd_next;
end if;
if sam_wr_inc = '1' then
sam_wr_addr <= sam_wr_next;
end if;
-- clear the inc flags, so we only increment by one
sam_rd_inc <= '0';
sam_wr_inc <= '0';
end if;
end if;
end process;
-- combinatorial logic for full,empty flags
process(sam_rd_addr, sam_wr_addr)
begin
if sam_rd_addr = sam_wr_addr then
sam_empty <= '1';
else
sam_empty <= '0';
end if;
if sam_wr_next = sam_rd_addr then
sam_full <= '1';
else
sam_full <= '0';
end if;
end process;
-- combinatorial logic for next rd address
process(sam_rd_addr)
begin
sam_rd_next <= sam_rd_addr + 1;
end process;
-- combinatorial logic for next write address
process(sam_wr_addr)
begin
sam_wr_next <= sam_wr_addr + 1;
end process;
-- Status byte
sam_status <= sam_empty & sam_full & "0000" & sam_underflow & sam_overflow;
end generate;
------------------------------------------------
-- Page Access Memory (PAM)
------------------------------------------------
pam_block: if CImplPAM generate
process(clock_32)
begin
if rising_edge(clock_32) then
if rnw = '0' and phi2 = '1' then
if intern_pam_reg0 = '1' then
pam_page(7 downto 0) <= extern_din;
end if;
if intern_pam_reg1 = '1' then
pam_page(8) <= extern_din(0);
end if;
end if;
end if;
end process;
end generate;
------------------------------------------------
-- Internal device chip selects
------------------------------------------------
intern_led <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BFE" and CImplLEDs else '0';
intern_rtc <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BFD" and CImplRTC else '0';
intern_sam_reg <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF2" and CImplSAM else '0';
intern_pam_reg0 <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF8" and CImplPAM else '0';
intern_pam_reg1 <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF9" and CImplPAM else '0';
intern_palette <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BD0" and CImplPalette else '0';
intern_config <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFFB" and CImplConfig else '0';
------------------------------------------------
-- External device chip selects
------------------------------------------------
extern_rom <= '1' when extern_ce = '1' and extern_a(17) = '0' else
'0';
extern_ram <= '1' when extern_ce = '1' and extern_a(17) = '1' else
'1' when (extern_sam_rd = '1' or extern_sam_wr = '1') and CImplSAM else
'1' when extern_pam = '1' and CImplPAM else
'0';
extern_via <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"B81" else
'0';
extern_tube <= '1' when extern_bus = '1' and extern_a(15 downto 4) = x"BEE" else
'0';
extern_sam_rd <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF0" and CImplSAM else
'0';
extern_sam_wr <= '1' when extern_bus = '1' and extern_a(15 downto 0) = x"BFF1" and CImplSAM else
'0';
extern_pam <= '1' when extern_bus = '1' and extern_a(15 downto 8) = x"B1" and CImplPAM else
'0';
cs_rom_n <= not(extern_rom);
cs_ram_n <= not(extern_ram);
cs_via_n <= not(extern_via);
cs_tube_n <= not(extern_tube);
-- A remote access is to a device on the far side of the data buffers
-- The tube is on the near side of the data buffers, so exclude
-- The LED and RTC registers are internal to this module, so exclude
remote_access <= '1' when extern_bus = '1' and extern_tube = '0' and extern_sam_rd = '0' and extern_sam_wr = '0' and extern_pam = '0' and
intern_led = '0' and intern_rtc = '0' and intern_palette = '0' and intern_config = '0' and intern_sam_reg = '0' and
intern_pam_reg0 = '0' and intern_pam_reg1 = '0' else '0';
-- In normal mode, enable the data buffers only for remote accesses.
-- In debug mode, enable the data buffers all the time.
cs_buf_n <= '0' when phi2 = '1' and debug_mode = '1' else
'0' when phi2 = '1' and remote_access = '1' and debug_mode = '0' else
'1';
-- In normal mode, the direction is inward for reads, outward for writes.
-- In debug mode, the direction is inward for remote reads, outward for everything else.
buf_dir <= '1' when remote_access = '1' and rnw = '1' and debug_mode = '1' else
'0' when debug_mode = '1' else
rnw;
------------------------------------------------
-- Audio mixer
------------------------------------------------
process(atom_audio, sid_audio)
variable l : std_logic_vector(dacwidth - 1 downto 0);
variable r : std_logic_vector(dacwidth - 1 downto 0);
begin
-- Atom Audio is a single bit
if (atom_audio = '1') then
l := x"1000";
r := x"1000";
else
l := x"EFFF";
r := x"EFFF";
end if;
-- SID output is 18-bit unsigned
if CImplSID then
l := l + sid_audio(17 downto 2);
r := r + sid_audio(17 downto 2);
else
l := l + x"8000";
r := r + x"8000";
end if;
-- Currently the left and right channels are identical
audio_l <= l;
audio_r <= r;
end process;
------------------------------------------------
-- MCP4822 SPI 12-bit DAC
--
-- note: this actually takes 16-bit samples
------------------------------------------------
process(clock_16)
begin
if rising_edge(clock_16) then
cycle <= cycle + 1;
if (unsigned(cycle(5 downto 0)) < 33) then
dac_cs_n <= '0';
dac_sck <= cycle(0);
else
dac_cs_n <= '1';
dac_sck <= '0';
end if;
if (cycle(0) = '0') then
if (unsigned(cycle(5 downto 1)) = 0) then
if (cycle(6) = '0') then
dac_shift_reg_l <= audio_l;
dac_shift_reg_r <= audio_r;
end if;
dac_sdi <= cycle(6);
elsif (unsigned(cycle(5 downto 1)) < 4) then
dac_sdi <= '1';
elsif (unsigned(cycle(5 downto 1)) < 16) then
if (cycle(6) = '0') then
dac_sdi <= dac_shift_reg_l(dacwidth - 1);
dac_shift_reg_l <= dac_shift_reg_l(dacwidth - 2 downto 0) & '0';
else
dac_sdi <= dac_shift_reg_r(dacwidth - 1);
dac_shift_reg_r <= dac_shift_reg_r(dacwidth - 2 downto 0) & '0';
end if;
else
dac_sdi <= '0';
end if;
if (unsigned(cycle(6 downto 1)) = 60) then
dac_ldac_n <= '0';
else
dac_ldac_n <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------
-- Atom Audio
------------------------------------------------
audio <= atom_audio;
------------------------------------------------
-- Keyboard
------------------------------------------------
process(clock_32)
begin
if rising_edge(clock_32) then
if powerup_reset_n = '0' then
-- PC(7) linked to ground indicates a PS/2 keyboard should be used
ps2_kbd_enable <= not kbd_pc(6);
end if;
end if;
end process;
-- Enable/Disable the PS/2 keyboard
ps2_kbd_clk <= kbd_pb(6) when ps2_kbd_enable = '1' else '1';
ps2_kbd_data <= kbd_pb(7) when ps2_kbd_enable = '1' else '1';
-- Enable/Disable the Matrix keyboard
int_kbd_pb <= kbd_pb when ps2_kbd_enable = '0' else (others => '1');
int_kbd_pc <= kbd_pc when ps2_kbd_enable = '0' else (others => '1');
--------------------------------------------------------
-- LED control / speedometer
--------------------------------------------------------
leds_block: if CImplLEDs generate
inst_debounce1 : entity work.debounce
generic map (
counter_size => 20 -- 32ms @ 32MHz
)
port map (
clock => clock_32,
button => sw(1),
pressed => sw_pressed(1)
);
inst_debounce2 : entity work.debounce
generic map (
counter_size => 20 -- 32ms @ 32MHz
)
port map (
clock => clock_32,
button => sw(2),
pressed => sw_pressed(2)
);
process(clock_32)
begin
if rising_edge(clock_32) then
-- SW1/2 manually increment/decrement bits 0/1 of the LED control register
if sw_pressed(1) = '1' then
led_ctrl_reg(1 downto 0) <= led_ctrl_reg(1 downto 0) - 1;
elsif sw_pressed(2) = '1' then
led_ctrl_reg(1 downto 0) <= led_ctrl_reg(1 downto 0) + 1;
end if;
-- LED control/data registers
if intern_led = '1' and rnw = '0' and phi2 = '1' then
if extern_a(0) = '1' then
led_data_reg <= extern_din;
else
led_ctrl_reg <= extern_din;
end if;
end if;
-- LED Speedometer
last_sync <= sync;
if last_sync = '0' and sync = '1' then
instr_count <= instr_count + 1;
if instr_count = 0 then
if led_state = x"D" then
led_state <= (others => '0');
else
led_state <= led_state + 1;
end if;
end if;
end if;
-- LED driver logic
case led_ctrl_reg(1 downto 0) is
when "01" =>
case led_state is
when x"0" => led <= "01000000";
when x"1" => led <= "10000000";
when x"2" => led <= "01000000";
when x"3" => led <= "00100000";
when x"4" => led <= "00010000";
when x"5" => led <= "00001000";
when x"6" => led <= "00000100";
when x"7" => led <= "00000010";
when x"8" => led <= "00000001";
when x"9" => led <= "00000010";
when x"A" => led <= "00000100";
when x"B" => led <= "00001000";
when x"C" => led <= "00010000";
when x"D" => led <= "00100000";
when others => led <= "00000000";
end case;
when "10" =>
led <= cpu_a(15 downto 8);
when "11" =>
led <= cpu_a(7 downto 0);
when others =>
led <= led_data_reg;
end case;
end if;
end process;
led_data <= led_ctrl_reg when extern_a(0) = '0' else
led_data_reg when extern_a(1) = '1' else
x"00";
-- Enable debug mode (logic analyzer output to data bus)in address mode
-- (when the LEDs are showing the low or high address bus)
debug_mode <= led_ctrl_reg(1);
end generate;
not_leds_block: if not CImplLEDs generate
led <= x"00";
debug_mode <= '0';
end generate;
--------------------------------------------------------
-- RTC Real Time Clock
--------------------------------------------------------
rtc_block: if CImplRTC generate
process (clock_32)
begin
if rising_edge(clock_32) then
if rtc_control(7) = '0' then
if rtc_cnt = 3199999 then
rtc_cnt <= (others => '0');
rtc_10hz <= rtc_10hz + 1;
if rtc_control(0) = '1' then
rtc_irq_flags(0) <= '1';
rtc_irq_flags(7) <= '1';
end if;
else
rtc_cnt <= rtc_cnt + 1;
end if;
if rtc_10hz = 10 then
rtc_seconds <= rtc_seconds + 1;
rtc_10hz <= x"0";
if rtc_control(1) = '1' then
rtc_irq_flags(1) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
if rtc_seconds = 60 then
rtc_minutes <= rtc_minutes + 1;
rtc_seconds <= x"00";
if rtc_control(2) = '1' then
rtc_irq_flags(2) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
if rtc_minutes = 60 then
rtc_hours <= rtc_hours + 1;
rtc_minutes <= x"00";
if rtc_control(3) = '1' then
rtc_irq_flags(3) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
if rtc_hours = 24 then
rtc_day <= rtc_day + 1;
rtc_hours <= x"00";
if rtc_control(4) = '1' then
rtc_irq_flags(4) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
if (rtc_day = 31 and (rtc_month = 4 or rtc_month = 6 or rtc_month = 9 or rtc_month = 11))
or (rtc_day = 30 and rtc_month = 2 and rtc_year(1 downto 0) = "00")
or (rtc_day = 29 and rtc_month = 2 and (rtc_year(1) = '1' or rtc_year(0) = '1')) or (rtc_day = 32) then
rtc_month <= rtc_month + 1;
rtc_day <= x"01";
if rtc_control(5) = '1' then
rtc_irq_flags(5) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
if rtc_month = 13 then
rtc_year <= rtc_year + 1;
rtc_month <= x"01";
if rtc_control(6) = '1' then
rtc_irq_flags(6) <= '1';
rtc_irq_flags(7) <= '1';
end if;
end if;
end if;
-- write RTC control/data registers
if intern_rtc = '1' and rnw = '0' and phi2 = '1' then
case extern_a(2 downto 0) is
when "000" =>
rtc_year <= extern_din;
when "001" =>
rtc_month <= extern_din;
when "010" =>
rtc_day <= extern_din;
when "011" =>
rtc_hours <= extern_din;
when "100" =>
rtc_minutes <= extern_din;
when "101" =>
rtc_seconds <= extern_din;
when "110" =>
rtc_control <= extern_din;
when others =>
rtc_irq_flags <= x"00";
end case;
end if;
if reset_n = '0' then
rtc_control <= x"00";
rtc_irq_flags <= x"00";
end if;
end if;
end process;
rtc_data <= rtc_year when extern_a(2 downto 0) = "000" else
rtc_month when extern_a(2 downto 0) = "001" else
rtc_day when extern_a(2 downto 0) = "010" else
rtc_hours when extern_a(2 downto 0) = "011" else
rtc_minutes when extern_a(2 downto 0) = "100" else
rtc_seconds when extern_a(2 downto 0) = "101" else
rtc_control when extern_a(2 downto 0) = "110" else
rtc_irq_flags when extern_a(2 downto 0) = "111" else
x"00";
rtc_irq_n <= not(rtc_irq_flags(7));
end generate;
not_rtc_block: if not CImplRTC generate
rtc_data <= x"00";
rtc_irq_n <= '1';
end generate;
--------------------------------------------------------
-- Colour palette control
--------------------------------------------------------
palette_block: if CImplPalette generate
process (clock_32)
begin
if rising_edge(clock_32) then
if reset_n = '0' then
-- initializing like this mean the palette will be
-- implemented with LUTs rather than as a block RAM
palette(0) <= "000000";
palette(1) <= "000011";
palette(2) <= "000100";
palette(3) <= "000111";
palette(4) <= "001000";
palette(5) <= "001011";
palette(6) <= "001100";
palette(7) <= "001111";
palette(8) <= "110000";
palette(9) <= "110011";
palette(10) <= "110100";
palette(11) <= "110111";
palette(12) <= "111000";
palette(13) <= "111011";
palette(14) <= "111100";
palette(15) <= "111111";
else
-- write colour palette registers
if intern_palette = '1' and rnw = '0' and phi2 = '1' then
palette(conv_integer(extern_a(3 downto 0))) <= extern_din(7 downto 2);
end if;
end if;
end if;
end process;
logical_colour <= red_vga(2) & green_vga(2) & green_vga(1) & blue_vga(2);
-- Making this a synchronous process should improve the timing
-- and potentially make the pixels more defined
process (clock_25)
begin
if rising_edge(clock_25) then
if vga_blank = '1' then
physical_colour <= (others => '0');
else
physical_colour <= palette(conv_integer(logical_colour));
end if;
-- Also register hsync/vsync so they are correctly
-- aligned with the colour changes
vga_hsync <= hsync_vga;
vga_vsync <= vsync_vga;
end if;
end process;
vga_red2 <= physical_colour(5);
vga_red1 <= physical_colour(4);
vga_green2 <= physical_colour(3);
vga_green1 <= physical_colour(2);
vga_blue2 <= physical_colour(1);
vga_blue1 <= physical_colour(0);
palette_data <= palette(conv_integer(extern_a(3 downto 0))) & "00";
end generate;
not_palette_block: if not CImplPalette generate
vga_hsync <= hsync_vga;
vga_vsync <= vsync_vga;
vga_red2 <= red_vga(2);
vga_red1 <= red_vga(1);
vga_green2 <= green_vga(2);
vga_green1 <= green_vga(1);
vga_blue2 <= blue_vga(2);
vga_blue1 <= blue_vga(1);
end generate;
--------------------------------------------------------
-- Colour palette control
--------------------------------------------------------
config_block: if CImplConfig generate
process (clock_32)
begin
if rising_edge(clock_32) then
-- write RTC control/data registers
if intern_config = '1' and rnw = '0' and phi2 = '1' then
-- Bit 7 triggers the reconfiguration
-- Bits 2..0 specify the design (0..7)
config_data <= extern_din;
end if;
end if;
end process;
Inst_ICAP_core: entity work.ICAP_core port map (
fastclk => clock_32,
design_num => '0' & config_data(2 downto 0),
reconfigure => config_data(7),
powerup => '0',
sw_in => x"0"
);
end generate;
end behavioral;
| apache-2.0 |
hoglet67/AtomFpga | src/xilinx/AtomFpga_BeebAdapter.vhd | 1 | 15582 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_BeebAdapter.vhd
-- /___/ /\ Timestamp : 21/04/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_BeebAdapter
--Device: Spartan6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity AtomFpga_BeebAdapter is
port (
-- System oscillator
clk50 : in std_logic;
-- BBC 1MHZ Bus
clke : in std_logic;
rnw : in std_logic;
rst_n : in std_logic;
pgfc_n : in std_logic;
pgfd_n : in std_logic;
bus_addr : in std_logic_vector (7 downto 0);
bus_data : inout std_logic_vector (7 downto 0);
bus_data_dir : out std_logic;
bus_data_oel : out std_logic;
nmi : out std_logic;
irq : out std_logic;
-- SPI DAC
dac_cs_n : out std_logic;
dac_sck : out std_logic;
dac_sdi : out std_logic;
dac_ldac_n : out std_logic;
-- RAM
ram_addr : out std_logic_vector(18 downto 0);
ram_data : inout std_logic_vector(7 downto 0);
ram_cel : out std_logic;
ram_oel : out std_logic;
ram_wel : out std_logic;
-- UART
uart_rxd : in std_logic;
uart_txd : out std_logic;
-- Flash
flash_cs : out std_logic;
flash_ck : out std_logic;
flash_si : out std_logic;
flash_so : in std_logic;
-- Misc
pmod0 : out std_logic_vector(7 downto 0);
pmod1 : inout std_logic_vector(7 downto 0);
pmod2 : inout std_logic_vector(3 downto 0);
sw1 : in std_logic;
sw2 : in std_logic;
led : out std_logic
);
end AtomFpga_BeebAdapter;
architecture behavioral of AtomFpga_BeebAdapter is
-- Clock generation
signal clk0 : std_logic;
signal clk1 : std_logic;
-- signal clk2 : std_logic;
signal clkfb : std_logic;
signal clkfb_buf : std_logic;
signal clkin_buf : std_logic;
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal phi2 : std_logic;
signal ext_A : std_logic_vector(18 downto 0);
signal ext_Din : std_logic_vector(7 downto 0);
signal ext_Dout : std_logic_vector(7 downto 0);
signal ext_nWE : std_logic;
signal ext_nOE : std_logic;
signal ext_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
-- Audio mixer and DAC
constant dacwidth : integer := 16; -- this needs to match the MCP4822 frame size
signal atom_audio : std_logic;
signal sid_audio : std_logic_vector(17 downto 0);
signal cycle : std_logic_vector(6 downto 0);
signal audio_l : std_logic_vector(dacwidth - 1 downto 0);
signal audio_r : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_l : std_logic_vector(dacwidth - 1 downto 0);
signal dac_shift_reg_r : std_logic_vector(dacwidth - 1 downto 0);
signal mmc_clk : std_logic;
signal mmc_ss : std_logic;
signal mmc_mosi : std_logic;
signal mmc_miso : std_logic;
signal ps2_kbd_clk : std_logic;
signal ps2_kbd_data : std_logic;
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 128KB (32x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"020000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
------------------------------------------------
-- Clock generation
--
-- from the on-board 50MHz Oscillator
-- using a PLL for the 16/32 MHz
-- using a DCM for the 25.175 MHz (approx)
------------------------------------------------
inst_clkin_buf : IBUFG
port map (
I => clk50,
O => clkin_buf
);
inst_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16, -- 50 * 16 = 800
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50, -- 800 / 50 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 25, -- 800 / 25 = 32MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 32, -- 800 / 32 = 25MHz
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010
)
port map (
-- Output clocks
CLKFBOUT => clkfb,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
-- CLKOUT2 => clk2,
RST => '0',
-- Input clock control
CLKFBIN => clkfb_buf,
CLKIN => clkin_buf
);
inst_clkfb_buf : BUFG
port map (
I => clkfb,
O => clkfb_buf
);
inst_clk0_buf : BUFG
port map (
I => clk0,
O => clock_16
);
inst_clk1_buf : BUFG
port map (
I => clk1,
O => clock_32
);
-- inst_clk2_buf : BUFG
-- port map (
-- I => clk2,
-- O => clock_25
-- );
inst_DCM : DCM
generic map (
CLKFX_MULTIPLY => 11,
CLKFX_DIVIDE => 14,
CLKIN_PERIOD => 31.250,
CLK_FEEDBACK => "NONE"
)
port map (
CLKIN => clock_32,
CLKFB => '0',
RST => '0',
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
CLKFX => clock_25
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- The external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= (not SW1) and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Atom Fpga Core
--------------------------------------------------------
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => false,
CImplAtoMMC2 => true,
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => true,
CImplRamRomNone => false,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => true,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clk_vga => clock_25,
clk_main => clock_32,
clk_avr => clock_32,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_kbd_clk,
ps2_data => ps2_kbd_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
phi2 => phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => open,
sid_audio_d => sid_audio,
atom_audio => atom_audio,
SDMISO => mmc_miso,
SDSS => mmc_ss,
SDCLK => mmc_clk,
SDMOSI => mmc_mosi,
uart_RxD => uart_rxd,
uart_TxD => uart_txd,
avr_RxD => '1',
avr_TxD => open,
LED1 => led, -- Green LED
LED2 => open, -- Red LED
charSet => '1',
Joystick1 => (others => '1'),
Joystick2 => (others => '1')
);
------------------------------------------------
-- Audio mixer
------------------------------------------------
process(atom_audio, sid_audio)
variable l : std_logic_vector(dacwidth - 1 downto 0);
variable r : std_logic_vector(dacwidth - 1 downto 0);
begin
-- Atom Audio is a single bit
if (atom_audio = '1') then
l := x"1000";
r := x"1000";
else
l := x"EFFF";
r := x"EFFF";
end if;
-- SID output is 18-bit unsigned
l := l + sid_audio(17 downto 2);
r := r + sid_audio(17 downto 2);
-- Currently the left and right channels are identical
audio_l <= l;
audio_r <= r;
end process;
------------------------------------------------
-- MCP4822 SPI 12-bit DAC
--
-- note: this actually takes 16-bit samples
------------------------------------------------
process(clock_16)
begin
if rising_edge(clock_16) then
cycle <= cycle + 1;
if (unsigned(cycle(5 downto 0)) < 33) then
dac_cs_n <= '0';
dac_sck <= cycle(0);
else
dac_cs_n <= '1';
dac_sck <= '0';
end if;
if (cycle(0) = '0') then
if (unsigned(cycle(5 downto 1)) = 0) then
if (cycle(6) = '0') then
dac_shift_reg_l <= audio_l;
dac_shift_reg_r <= audio_r;
end if;
dac_sdi <= cycle(6);
elsif (unsigned(cycle(5 downto 1)) < 4) then
dac_sdi <= '1';
elsif (unsigned(cycle(5 downto 1)) < 16) then
if (cycle(6) = '0') then
dac_sdi <= dac_shift_reg_l(dacwidth - 1);
dac_shift_reg_l <= dac_shift_reg_l(dacwidth - 2 downto 0) & '0';
else
dac_sdi <= dac_shift_reg_r(dacwidth - 1);
dac_shift_reg_r <= dac_shift_reg_r(dacwidth - 2 downto 0) & '0';
end if;
else
dac_sdi <= '0';
end if;
if (unsigned(cycle(6 downto 1)) = 60) then
dac_ldac_n <= '0';
else
dac_ldac_n <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_length => user_length
)
port map(
clock => clock_32,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => ext_nOE,
RAM_nWE => ext_nWE,
RAM_nCS => ext_nCS,
RAM_A => ext_A,
RAM_Din => ext_Din,
RAM_Dout => ext_Dout,
SRAM_nOE => ram_oel,
SRAM_nWE => ram_wel,
SRAM_nCS => ram_cel,
SRAM_A(20 downto 19) => open,
SRAM_A(18 downto 0) => ram_addr,
SRAM_D => ram_data,
FLASH_CS => flash_cs,
FLASH_SI => flash_si,
FLASH_CK => flash_ck,
FLASH_SO => flash_so
);
MemProcess : process (clock_32)
begin
if rising_edge(clock_32) then
ext_A <= ExternA;
ext_nCS <= not ExternCE;
ext_nOE <= not ((not ExternWE) and ExternCE and phi2);
ext_nWE <= not (ExternWE and ExternCE and phi2);
ext_Din <= ExternDin;
end if;
end process;
ExternDout <= ext_Dout;
bus_data <= (others => 'Z');
bus_data_dir <= '1';
bus_data_oel <= '1';
nmi <= '0';
irq <= '0';
pmod0 <= blue & "0" & red & "0";
pmod1 <= "ZZ" & vsync & hsync & green & "0";
pmod2 <= "Z" & mmc_clk & mmc_mosi & mmc_ss;
ps2_kbd_clk <= pmod1(6);
ps2_kbd_data <= pmod1(7);
mmc_miso <= pmod2(3);
end behavioral;
| apache-2.0 |
astoria-d/super-duper-nes | duper_cartridge/simulation/nes2bbb_testbench.vhd | 1 | 10610 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
entity nes2bbb_testbench is
end nes2bbb_testbench;
architecture stimulus of nes2bbb_testbench is
constant powerup_time : time := 1500 ns;
constant reset_time : time := 1800 ns;
--DE1 base clock = 50 MHz
constant base_clock_time : time := 20 ns;
--i2c normal clock speed 100 KHz
constant i2c_clock_time : time := 10 us;
--i2c clock timing..
constant i2c_clk_0 : std_logic_vector(1 downto 0) := "00";
constant i2c_clk_1 : std_logic_vector(1 downto 0) := "01";
constant i2c_clk_2 : std_logic_vector(1 downto 0) := "10";
constant i2c_clk_3 : std_logic_vector(1 downto 0) := "11";
---https://wiki.nesdev.com/w/index.php/Clock_rate
--nes cpu clock = 1.789773 MHz
constant nes_clock_time : time := 558 ns;
constant bus_cycle : integer := 3;
---fifo status register
---bit
---7 always 0
---6 always 0
---5 read fifo full
---4 read fifo empty
---3 always 0
---2 always 0
---1 write fifo full
---0 write fifo empty
constant wfifo_empty_bit : integer := 0;
constant wfifo_full_bit : integer := 1;
constant rfifo_empty_bit : integer := 4;
constant rfifo_full_bit : integer := 5;
constant i2c_read : std_logic := '1';
constant i2c_write : std_logic := '0';
component duper_cartridge
port (
pi_reset_n : in std_logic;
pi_base_clk : in std_logic;
--nes side
pi_phi2 : in std_logic;
pi_prg_ce_n : in std_logic;
pi_prg_r_nw : in std_logic;
pi_prg_addr : in std_logic_vector(14 downto 0);
pio_prg_data : inout std_logic_vector(7 downto 0);
pi_chr_ce_n : in std_logic;
pi_chr_oe_n : in std_logic;
pi_chr_we_n : in std_logic;
pi_chr_addr : in std_logic_vector(12 downto 0);
po_chr_data : out std_logic_vector(7 downto 0);
--i2c side
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
--bbb gpio
po_nes_f_full : out std_logic;
po_bbb_f_empty : out std_logic;
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
end component ;
signal reset_input : std_logic;
signal base_clk : std_logic;
signal phi2 : std_logic;
signal prg_ce_n : std_logic;
signal prg_r_nw : std_logic;
signal prg_addr : std_logic_vector(14 downto 0);
signal prg_data : std_logic_vector(7 downto 0);
signal chr_ce_n : std_logic;
signal chr_oe_n : std_logic;
signal chr_we_n : std_logic;
signal chr_addr : std_logic_vector(12 downto 0);
signal chr_data : std_logic_vector(7 downto 0);
signal i2c_scl : std_logic;
signal i2c_scl_x4 : std_logic;
signal i2c_scl_type : std_logic_vector(1 downto 0);
signal i2c_sda : std_logic;
signal nes_f_full : std_logic;
signal bbb_f_empty : std_logic;
signal dbg_cnt : std_logic_vector (63 downto 0);
signal reg_rom_data : std_logic_vector(7 downto 0);
signal reg_bbb_recv : std_logic_vector (7 downto 0);
signal start_scl : std_logic;
signal step_cnt : integer range 0 to 65535 := 0;
signal stage_cnt : integer range 0 to 65535 := 0;
signal i2c_step_cnt : integer range 0 to 65535 := 0;
signal addr_index : integer range 0 to 65535 := 0;
signal data_index : integer range 0 to 65535 := 0;
begin
---chrrom side disabled..
chr_ce_n <= 'Z';
chr_oe_n <= 'Z';
chr_we_n <= 'Z';
chr_addr <= (others => 'Z');
chr_data <= (others => 'Z');
sim_board : duper_cartridge port map (
reset_input,
base_clk,
phi2,
prg_ce_n,
prg_r_nw,
prg_addr,
prg_data,
chr_ce_n,
chr_oe_n,
chr_we_n,
chr_addr,
chr_data,
i2c_scl,
i2c_sda,
nes_f_full,
bbb_f_empty,
dbg_cnt);
--- input reset.
reset_p: process
begin
reset_input <= '1';
wait for powerup_time;
reset_input <= '0';
wait for reset_time;
reset_input <= '1';
wait;
end process;
--- generate base clock.
clock_p1 : process
begin
base_clk <= '1';
wait for base_clock_time / 2;
base_clk <= '0';
wait for base_clock_time / 2;
end process;
--- phi clock.
clock_phi : process
begin
phi2 <= '1';
wait for nes_clock_time / 2;
phi2 <= '0';
wait for nes_clock_time / 2;
end process;
--- i2c base clock.
clock_i2c_base : process
begin
i2c_scl_x4 <= '1';
wait for i2c_clock_time / 8;
i2c_scl_x4 <= '0';
wait for i2c_clock_time / 8;
end process;
--- i2c clock.
clock_i2c : process (reset_input, i2c_scl_x4)
begin
if (reset_input = '0') then
i2c_scl_type <= i2c_clk_0;
i2c_scl <= '1';
elsif (rising_edge(i2c_scl_x4)) then
i2c_scl_type <= i2c_scl_type + 1;
if(start_scl = '1') then
if (i2c_scl_type = i2c_clk_0) then
i2c_scl <= '1';
elsif (i2c_scl_type = i2c_clk_2) then
i2c_scl <= '0';
end if;
else
i2c_scl <= '1';
end if;
end if;
end process;
--- cpu bus emulation...
emu_cpu : process (reset_input, phi2)
procedure mem_write
(
addr : in std_logic_vector (14 downto 0);
data : in std_logic_vector (7 downto 0)
) is
begin
prg_ce_n <= '0';
prg_r_nw <= '0';
prg_addr <= addr;
prg_data <= data;
end;
procedure bus_wait is
begin
prg_ce_n <= '1';
prg_r_nw <= 'Z';
prg_addr <= (others => 'Z');
prg_data <= (others => 'Z');
end;
begin
if (reset_input = '0') then
stage_cnt <= 0;
step_cnt <= 0;
elsif (rising_edge(phi2)) then
---stage 0: initialize....
if (stage_cnt = 0) then
if (step_cnt = 10) then
stage_cnt <= stage_cnt + 1;
step_cnt <= 0;
else
step_cnt <= step_cnt + 1;
end if;
---stage 1: rom write.....
elsif (stage_cnt = 1) then
if (step_cnt < 1300) then
if (step_cnt mod bus_cycle = 0) then
mem_write (conv_std_logic_vector(16#fff9#, 15), conv_std_logic_vector(16#de#, 8) + step_cnt);
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
else
bus_wait;
step_cnt <= step_cnt + 1;
-- step_cnt <= 0;
-- stage_cnt <= stage_cnt + 1;
end if;
end if;
end if;
end process;
--- i2c bus emulation...
i2c_cpu : process (reset_input, i2c_scl_x4)
procedure increment_cnt is
begin
if (i2c_scl_type = i2c_clk_0) then
i2c_step_cnt <= i2c_step_cnt + 1;
end if;
end;
procedure start_seq is
begin
if (i2c_scl_type = i2c_clk_1) then
i2c_sda <= '0';
end if;
end;
procedure output_addr
(
i : in integer;
addr : in std_logic_vector (6 downto 0)
) is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= addr(i);
end if;
end;
procedure set_rw
(
rw : in std_logic
) is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= rw;
end if;
end;
procedure ack_wait is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= 'Z';
end if;
end;
procedure send_ack is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= '0';
end if;
end;
procedure input_data
(
i : in integer
) is
begin
if (i2c_scl_type = i2c_clk_0 and (i >= 0 and i < 8)) then
reg_bbb_recv(i) <= i2c_sda;
end if;
end;
begin
if (reset_input = '0') then
i2c_step_cnt <= 0;
i2c_sda <= '1';
start_scl <= '0';
addr_index <= 0;
data_index <= 0;
elsif (rising_edge(i2c_scl_x4)) then
---stage 1: i2c read.....
if (stage_cnt = 1) then
increment_cnt;
if (i2c_step_cnt < 3) then
start_scl <= '1';
elsif (i2c_step_cnt = 3) then
addr_index <= i2c_step_cnt + 1;
elsif (i2c_step_cnt = addr_index) then
--start up seq...
start_seq;
--set i2c addr...
--addr output with write.....
--0x44 = 100 0101.
output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt <= addr_index + 6) then
output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt = addr_index + 7) then
set_rw(i2c_read);
elsif (i2c_step_cnt = addr_index + 8) then
--ack wait...
ack_wait;
data_index <= i2c_step_cnt + 1;
elsif (i2c_step_cnt = data_index + 9) then
if (i2c_scl_type = i2c_clk_3) then
---infinete repeat...
data_index <= data_index + 9;
i2c_sda <= 'Z';
end if;
elsif (i2c_step_cnt < data_index + 9) then
input_data(7 - i2c_step_cnt + data_index);
if (i2c_step_cnt = data_index + 8) then
send_ack;
end if;
end if;
end if;
end if;
end process;
end stimulus;
| apache-2.0 |
astoria-d/super-duper-nes | duper_cartridge/synchronizer.vhd | 1 | 3627 | library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic;
po_sync_output : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
begin
--for metastability, synchronize with two stages intermediate FF.
sync_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : std_logic_vector(2 downto 0);
begin
if (pi_rst_n = '0') then
reg_temp := (others => '0');
elsif (rising_edge(pi_base_clk)) then
--shift two stage register.
reg_temp := pi_async_input & reg_temp(2 downto 1);
po_sync_output <= reg_temp(0);
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
----------------------------------------------
----------------------------------------------
----------------------------------------------
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronized_vector is
generic (abus_size : integer := 8);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic_vector(abus_size - 1 downto 0);
po_sync_output : out std_logic_vector(abus_size - 1 downto 0)
);
end synchronized_vector;
architecture rtl of synchronized_vector is
subtype TMP_REG_T is std_logic_vector (2 downto 0);
type TMP_REG_ARRAY_T is array (0 to abus_size - 1) of TMP_REG_T;
begin
sync_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : TMP_REG_ARRAY_T;
begin
if (pi_rst_n = '0') then
for i in 0 to abus_size -1 loop
reg_temp(i) := (others => '0');
end loop;
elsif (rising_edge(pi_base_clk)) then
for i in 0 to abus_size -1 loop
--shift two stage register.
reg_temp(i) := pi_async_input(i) & reg_temp(i)(2 downto 1);
po_sync_output(i) <= reg_temp(i)(0);
end loop;
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
----------------------------------------------
----------------------------------------------
----------------------------------------------
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity edge_detecter is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_input : in std_logic;
po_rise : out std_logic;
po_fall : out std_logic
);
end edge_detecter;
architecture rtl of edge_detecter is
begin
detect_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : std_logic;
begin
if (pi_rst_n = '0') then
reg_temp := '0';
po_rise <= '0';
po_fall <= '0';
elsif (rising_edge(pi_base_clk)) then
if (reg_temp /= pi_input) then
if (pi_input = '1') then
po_rise <= '1';
po_fall <= '0';
else
po_rise <= '0';
po_fall <= '1';
end if;
else
po_rise <= '0';
po_fall <= '0';
end if;
reg_temp := pi_input;
end if;--if (pi_rst_n = '0') then
end process;
end rtl; | apache-2.0 |
five-elephants/hw-neural-sampling | top.vhdl | 1 | 2678 | library ieee;
use ieee.std_logic_1164.all;
use work.sampling.all;
use work.net_config.all;
entity top is
port (
ext_clk, async_resetb : in std_ulogic
);
end top;
architecture rtl of top is
------------------------------------------------------------
-- component declarations
------------------------------------------------------------
component clockgen is
port (
ext_clk, async_resetb : in std_ulogic;
clk, sync_reset : out std_ulogic
);
end component;
component sampling_shell is
generic (
num_samplers : integer := 4;
tau : positive := 20;
num_observers : natural := 16
);
port (
clk, reset : in std_ulogic;
observed_joints : in state_array2_t(1 to num_observers, 1 to num_samplers);
joint_counters : out joint_counter_array_t(1 to num_observers);
systime : out systime_t
);
end component;
component jtag_access is
generic (
num_samplers : integer;
num_observers : natural
);
port (
clk, reset : in std_ulogic;
joint_counters : in joint_counter_array_t(1 to num_observers);
systime : in systime_t
);
end component;
------------------------------------------------------------
-- local signals
------------------------------------------------------------
signal clk, reset : std_ulogic;
--signal observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers);
signal joint_counters : joint_counter_array_t(1 to num_observers);
signal systime : systime_t;
begin
------------------------------------------------------------
-- support logic
------------------------------------------------------------
clkgen: clockgen
port map (
ext_clk => ext_clk,
clk => clk,
async_resetb => async_resetb,
sync_reset => reset
);
------------------------------------------------------------
-- sampling related stuff
------------------------------------------------------------
sampling: sampling_shell
generic map (
num_samplers => num_samplers,
tau => tau,
num_observers => num_observers
)
port map (
clk => clk,
reset => reset,
observed_joints => observed_joints,
joint_counters => joint_counters,
systime => systime
);
------------------------------------------------------------
-- JTAG interface
------------------------------------------------------------
jtag_inst: jtag_access
generic map (
num_samplers => num_samplers,
num_observers => num_observers
)
port map (
clk => clk,
reset => reset,
joint_counters => joint_counters,
systime => systime
);
end rtl;
| apache-2.0 |
Piasy/THCO-MIPS-CPU | src/Forward_Unit.vhd | 2 | 8662 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:47:55 11/23/2013
-- Design Name:
-- Module Name: Forward_Unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Forward_Unit is
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0) := "ZZ";
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
STALL_OR_NOT : out STD_LOGIC := STALL_NO;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN
);
end Forward_Unit;
architecture Behavioral of Forward_Unit is
begin
process(CUR_RS_REG_NUM, CUR_RT_REG_NUM, CUR_ALU_A_SRC_SELECT, CUR_ALU_B_SRC_SELECT,
LAST_WRITE_REGS_OR_NOT, LAST_WRITE_REGS_TARGET, LAST_DM_READ_WRITE,
LAST_LAST_WRITE_REGS_OR_NOT, LAST_LAST_WRITE_REGS_TARGET)
begin
-- 本条指令用A B 作为ALU操作数，可能有冲突
if (CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A or CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
if (LAST_DM_READ_WRITE = MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- 上访，上写，冲突则必须停
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_YES;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_YES;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_DM_READ_WRITE = MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_NO) then
-- 上访，上不写，上上写，有冲突选旁路
if (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- A conflict, need not stall, select mem/wb reg value
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
-- B conflict, need not stall, select mem/wb reg value
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG ;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_DM_READ_WRITE /= MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- 上不访，上写，上上写，有冲突优先选EXE/MEM(优先判断上条指令)
if (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_EXE_MEM_REG ;
-- 还要判断上上条是否和B冲突
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG ;
else
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN;
end if;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_EXE_MEM_REG;
else
-- 上条指令无冲突，判断上上条指令是否冲突
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end if;
-- 上不访，上写，上上不写，有冲突选旁路
else
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_EXE_MEM_REG ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_EXE_MEM_REG ;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end if;
-- 上不访，上不写，上上写，有冲突选旁路
elsif (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
-- 上不访，上不写，上上不写，无冲突
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end process;
end Behavioral;
| apache-2.0 |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/iface/acl_iface_system/acl_iface_system_inst.vhd | 1 | 16752 | component acl_iface_system is
port (
config_clk_clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
kernel_clk_clk : out std_logic; -- clk
kernel_clk_snoop_clk : out std_logic; -- clk
kernel_mem0_waitrequest : out std_logic; -- waitrequest
kernel_mem0_readdata : out std_logic_vector(255 downto 0); -- readdata
kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
kernel_mem0_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
kernel_mem0_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
kernel_mem0_write : in std_logic := 'X'; -- write
kernel_mem0_read : in std_logic := 'X'; -- read
kernel_mem0_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
kernel_reset_reset_n : out std_logic; -- reset_n
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X' -- hps_io_gpio_inst_GPIO53
);
end component acl_iface_system;
u0 : component acl_iface_system
port map (
config_clk_clk => CONNECTED_TO_config_clk_clk, -- config_clk.clk
reset_n => CONNECTED_TO_reset_n, -- global_reset.reset_n
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
kernel_clk_snoop_clk => CONNECTED_TO_kernel_clk_snoop_clk, -- kernel_clk_snoop.clk
kernel_mem0_waitrequest => CONNECTED_TO_kernel_mem0_waitrequest, -- kernel_mem0.waitrequest
kernel_mem0_readdata => CONNECTED_TO_kernel_mem0_readdata, -- .readdata
kernel_mem0_readdatavalid => CONNECTED_TO_kernel_mem0_readdatavalid, -- .readdatavalid
kernel_mem0_burstcount => CONNECTED_TO_kernel_mem0_burstcount, -- .burstcount
kernel_mem0_writedata => CONNECTED_TO_kernel_mem0_writedata, -- .writedata
kernel_mem0_address => CONNECTED_TO_kernel_mem0_address, -- .address
kernel_mem0_write => CONNECTED_TO_kernel_mem0_write, -- .write
kernel_mem0_read => CONNECTED_TO_kernel_mem0_read, -- .read
kernel_mem0_byteenable => CONNECTED_TO_kernel_mem0_byteenable, -- .byteenable
kernel_mem0_debugaccess => CONNECTED_TO_kernel_mem0_debugaccess, -- .debugaccess
kernel_reset_reset_n => CONNECTED_TO_kernel_reset_reset_n, -- kernel_reset.reset_n
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53 -- .hps_io_gpio_inst_GPIO53
);
| apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/DE2Component.vhd | 1 | 9775 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port (
KEY : in std_logic_vector (3 downto 0); --Buttons
SW : in std_logic_vector (7 downto 0); -- Switches
CLOCK_50 : in std_logic; -- 50 MHz Clock
LEDG : out DE2_LED_GREEN; -- Green LEDs
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
--UART Connection
UART_TXD : out std_logic; --Transmitter
UART_RXD : in std_logic; --Receiver
-- USB controller
OTG_INT0 : in std_logic;
OTG_INT1 : in std_logic;
OTG_DREQ0 : in std_logic;
OTG_DREQ1 : in std_logic;
OTG_DACK0_N : out std_logic;
OTG_DACK1_N : out std_logic;
OTG_FSPEED : out std_logic;
OTG_LSPEED : out std_logic;
OTG_ADDR : out std_logic_vector(1 downto 0);
OTG_DATA : inout std_logic_vector(15 downto 0);
OTG_CS_N : out std_logic;
OTG_RD_N : out std_logic;
OTG_WR_N : out std_logic;
OTG_RST_N : out std_logic;
--Flash
FL_ADDR : out std_logic_vector (21 downto 0);
FL_CE_N : out std_logic_vector (0 downto 0);
FL_OE_N : out std_logic_vector (0 downto 0);
FL_DQ : inout std_logic_vector (7 downto 0);
FL_RST_N : out std_logic_vector (0 downto 0) := "1";
FL_WE_N : out std_logic_vector (0 downto 0)
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
altpll_0_c0_clk : out std_logic; -- clk
usb_0_external_interface_INT1 : in std_logic := 'X'; -- Interrupt1
usb_0_external_interface_INT0 : in std_logic := 'X'; -- Interrupt2
usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_0_external_interface_RST_N : out std_logic; -- reset_n
usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_0_external_interface_CS_N : out std_logic; -- CS_N
usb_0_external_interface_RD_N : out std_logic; -- RD_N
usb_0_external_interface_WR_N : out std_logic; -- WR_N
rs232_0_external_interface_RXD : in std_logic; --:= 'X'; -- RXD
rs232_0_external_interface_TXD : out std_logic; -- TXD
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
-- DACK not used
OTG_DACK0_N <= 'Z';
OTG_DACK1_N <= 'Z';
-- Speed set to Full-speed
OTG_FSPEED <= 'Z';
OTG_LSPEED <= '0';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
usb_0_external_interface_INT1 => OTG_INT1,
usb_0_external_interface_INT0 => OTG_INT0,
usb_0_external_interface_DATA => OTG_DATA,
usb_0_external_interface_RST_N => OTG_RST_N,
usb_0_external_interface_ADDR => OTG_ADDR,
usb_0_external_interface_CS_N => OTG_CS_N,
usb_0_external_interface_RD_N => OTG_RD_N,
usb_0_external_interface_WR_N => OTG_WR_N,
rs232_0_external_interface_RXD => UART_RXD,
rs232_0_external_interface_TXD => UART_TXD,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N
);
end structure;
library ieee;
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| apache-2.0 |
pgavin/carpe | hdl/tech/inferred/syncram_1r1w_inferred-rtl-sim.vhdl | 1 | 4194 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
use util.names_pkg.all;
use std.textio.all;
architecture rtl of syncram_1r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
-- fill the memory with pseudo-random (but reproduceable) data
pure function memory_init return memory_type is
constant lfsr_bits : natural := addr_bits + log2ceil(data_bits) + 1;
variable lfsr : std_ulogic_vector(lfsr_bits-1 downto 0);
constant taps : std_ulogic_vector(lfsr_bits-1 downto 0) := lfsr_taps(lfsr_bits);
variable ret : memory_type;
variable initial_bit : integer;
variable name : line;
begin
name := new string'(entity_path_name(syncram_1r1w_inferred'path_name));
for n in name.all'range loop
initial_bit := (initial_bit + character'pos(name.all(n))) mod lfsr_bits;
end loop;
deallocate(name);
lfsr := (others => '0');
lfsr(0) := '1';
lfsr(initial_bit) := '1';
for n in 0 to memory_size-1 loop
for m in data_bits-1 downto 0 loop
ret(n)(m) := lfsr(0);
lfsr(lfsr_bits-1 downto 0) := lfsr(0) & (lfsr(lfsr_bits-1 downto 1) xor ((lfsr_bits-2 downto 0 => lfsr(0)) and taps(lfsr_bits-2 downto 0)));
end loop;
end loop;
return ret;
end;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
signal memory : memory_type := memory_init;
type reg_type is record
raddr : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
begin
write_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(we) report "we is invalid" severity warning;
if we = '1' then
assert not is_x(waddr) report "waddr is invalid" severity warning;
if not is_x(waddr) then
memory(conv_addr(waddr)) <= wdata;
end if;
end if;
end if;
end process;
write_first_true_gen: if write_first generate
rdata <= memory(conv_addr(r.raddr)) when not is_x(r.raddr) else (others => 'X');
read_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
r.raddr <= raddr;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
rdata <= memory(conv_addr(raddr));
end if;
end if;
end process;
end generate;
end;
| apache-2.0 |
pgavin/carpe | hdl/tech/mul_trunc_seq.vhdl | 1 | 1732 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_trunc_seq is
generic (
latency : positive := 1;
src_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src_bits-1 downto 0);
src2 : in std_ulogic_vector(src_bits-1 downto 0);
valid : out std_ulogic;
overflow : out std_ulogic;
result : out std_ulogic_vector(src_bits-1 downto 0)
);
end;
| apache-2.0 |
pgavin/carpe | hdl/cpu/or1knd/i5/mmu/data/pass/cpu_or1knd_i5_mmu_data_pass.vhdl | 1 | 2258 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_or1knd_i5_mmu_data_pass_pkg.all;
entity cpu_or1knd_i5_mmu_data_pass is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_or1knd_i5_mmu_data_pass_ctrl_in : in cpu_or1knd_i5_mmu_data_pass_ctrl_in_type;
cpu_or1knd_i5_mmu_data_pass_dp_in : in cpu_or1knd_i5_mmu_data_pass_dp_in_type;
cpu_or1knd_i5_mmu_data_pass_ctrl_out : out cpu_or1knd_i5_mmu_data_pass_ctrl_out_type;
cpu_or1knd_i5_mmu_data_pass_dp_out : out cpu_or1knd_i5_mmu_data_pass_dp_out_type;
cpu_or1knd_i5_mmu_data_pass_ctrl_in_pipe : in cpu_or1knd_i5_mmu_data_pass_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_data_pass_dp_in_pipe : in cpu_or1knd_i5_mmu_data_pass_dp_in_pipe_type;
cpu_or1knd_i5_mmu_data_pass_ctrl_out_pipe : out cpu_or1knd_i5_mmu_data_pass_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_data_pass_dp_out_pipe : out cpu_or1knd_i5_mmu_data_pass_dp_out_pipe_type
);
end;
| apache-2.0 |
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