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TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_2/synth/bram_1024_2.vhd | 4 | 14457 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
| unlicense |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/space_shooter_demo/de2_space_shooter_demo_top.vhd | 1 | 2429 | library ieee;
use ieee.std_logic_1164.all;
-- VAGE (VHDL Advanced Game Engine) demo using the 'Space Shooter' game demo
-- and the Altera DE2 board as a hardware platform. The purpose of this file
-- is simply to instantiate the game top entity. It should not contain any -
-- gamerelated code. This is also a perfect place for vendor-specific and
-- board-specific code, such as PLLs.
entity de2_space_shooter_demo_top is
-- Port names as defined in the standard DE2 settings file.
port (
-- 50 MHz clock provided by the DE2 board
clock_50: in std_logic;
-- Input toggle switches
sw: in std_logic_vector(17 downto 0);
-- Input push-button switches, active low
key: in std_logic_vector(3 downto 0);
-- Green leds
ledg: out std_logic_vector(7 downto 0);
vga_clk: out std_logic;
vga_blank: out std_logic;
vga_hs: out std_logic;
vga_vs: out std_logic;
vga_sync: out std_logic;
vga_r: out std_logic_vector(9 downto 0);
vga_g: out std_logic_vector(9 downto 0);
vga_b: out std_logic_vector(9 downto 0)
);
end;
architecture rtl of de2_space_shooter_demo_top is
-- Component declaration for the PLL used to generate the 25 MHz pixel
-- clock from the board 50 MHz system clock
component video_pll
port(
inclk0: in std_logic := '0';
c0: out std_logic
);
end component;
signal vga_pll_clock_out: std_logic;
begin
-- Instantiate the game top entity
game: entity work.space_shooter_demo_top
port map(
clock_50_Mhz => clock_50,
reset => sw(17),
debug_bits => ledg,
vga_clock_in => vga_pll_clock_out,
vga_clock_out => vga_clk,
vga_blank => vga_blank,
vga_n_hsync => vga_hs,
vga_n_vsync => vga_vs,
vga_n_sync => vga_sync,
vga_red => vga_r,
vga_green => vga_g,
vga_blue => vga_b,
input_switches => sw(1 downto 0),
input_buttons => not key
);
-- Instantiate a PLL to generate the pixel clock frequency (~25 MHZ),
-- using the DE2 50Mhz clock as input
video_PLL_inst : video_PLL port map (
inclk0 => clock_50,
c0 => vga_pll_clock_out
);
end; | unlicense |
hgunicamp/Mips8B | src_design/mips8b_core.vhdl | 1 | 8835 | Library Ieee;
Use Ieee.Std_Logic_1164.all;
Entity Mips8B_Core is
Port(Reset_n: in Std_Logic;
Clock: in Std_Logic;
MAddr: out Std_Logic_Vector(7 downto 0);
MCmd: out Std_Logic_Vector(1 downto 0);
MData: out Std_Logic_Vector(7 downto 0);
SData: in Std_Logic_Vector(7 downto 0);
SCmdAccept: in Std_Logic);
End Entity Mips8B_Core;
Architecture struct of Mips8B_Core is
-- Interfaces dos componentes internos.
Use Work.MIPS8B_Components.all;
-- Importando biblioteca de tipos básicos.
Use Work.MIPS8B_Base.all;
-- Conexões para o PC.
Signal en_Out_PC: Std_Logic;
Signal load_PC: Std_Logic;
Signal inc_PC: Std_Logic;
Signal out_PC: Std_Logic_Vector(5 downto 0);
Signal address_PC: Std_Logic_Vector(5 downto 0);
-- Interface para o sistema de I/O.
-- Controle do endereço fornecido pelo sistema
Signal en_RMem: Std_Logic;
Signal en_RMem_Inc: Std_Logic;
Signal crt_Mux_IO: Std_Logic;
Signal crt_MEM: MemoryOP;
-- Controle dos Dados de I/O.
Signal en_RData_in: Std_Logic;
Signal en_RData_out: Std_Logic;
-- Registradores para dados de I/O.
Signal RData_in: Std_Logic_Vector(7 downto 0);
-- Interface para o controlador principal.
Signal IO_OK: Std_Logic;
Signal eq_Flag: Std_Logic;
Signal en_ROpcode: Std_Logic;
Signal Opcode: Std_Logic_Vector(4 downto 0);
-- Controle para o Registrer File.
Signal crt_RFile: Std_Logic;
Signal en_Raddress_RF: Std_Logic;
Signal address_RF: Std_Logic_Vector(2 downto 0);
-- Controle para os registradores Intermediarios.
Signal en_R1A_ULA: Std_Logic;
Signal en_R1B_ULA: Std_Logic;
Signal en_R2_ULA: Std_Logic;
Signal en_Reg_SH: Std_Logic;
-- Controle para os multiplexadores.
Signal crt_Mux_ULA: Std_Logic_Vector(1 downto 0);
Signal crt_Mux_Acc: Std_Logic;
Signal crt_Mux_RF: Std_Logic;
-- Controle das unidades funcionais.
Signal crt_ULA: Std_Logic_Vector(2 downto 0);
Signal crt_SH: Std_Logic_Vector(1 downto 0);
Signal crt_Acc: Std_Logic_Vector(1 downto 0);
-- Valor do comprimento do shift.
Signal S_SH: Std_Logic_Vector(2 downto 0);
-- Valor do campo imediato
Signal out_IMM: Std_Logic_Vector(7 downto 0);
-- Saida do resultado do Acumulador.
Signal out_Acc: Std_Logic_Vector(7 downto 0);
Begin
---------------------------------------------------------------------------
-- Processo para registrar o opcode da instrução corrente.
OPCode_PROC: Process
Begin
Wait Until Clock'event and Clock = '1';
If en_ROpcode = '1' then
Opcode <= RData_in(7 downto 3);
End If;
End Process OPCode_PROC;
---------------------------------------------------------------------------
-- Instância de PC.
PC_Unity: PC_System
Generic Map(N => 8)
Port Map(clock => Clock,
Reset_n => Reset_n,
en_Out_PC => en_Out_PC,
load_PC => load_PC,
inc_PC => inc_PC,
in_PC => out_Acc(5 downto 0),
out_PC => out_PC,
address_PC => address_PC);
---------------------------------------------------------------------------
-- Instância do sistema de I/O.
IO_System: MIPS8B_IO_System
Generic Map(N => 8)
Port Map(clock => Clock,
Reset_n => Reset_n,
-- Controle do endereço fornecido pelo sistema
en_RMem => en_RMem,
en_RMem_Inc => en_RMem_Inc,
crt_Mux_IO => crt_Mux_IO,
crt_MEM => crt_MEM,
-- Controle dos Dados de I/O.
en_RData_in => en_RData_in,
en_RData_out => en_RData_out,
-- Valores de endereço para transações de I/O.
out_PC => address_PC,
out_DPath => out_Acc,
in_Data => SData,
-- Registradores para dados de I/O.
RMem => MAddr,
RData_in => RData_in,
RData_out => MData,
-- Interface de controle.
Cmd => MCmd,
CmdAccept => SCmdAccept,
IO_OK => IO_OK);
---------------------------------------------------------------------------
-- Instância do controlador principal.
Main_Control: MIPS8B_DP_Control
Generic Map(N => 8,
SH_SIZE => 3,
RF_ADDR_SIZE => 3)
Port Map(clock => Clock,
Reset_n => Reset_n,
IO_OK => IO_OK,
eq_Flag => eq_Flag,
Opcode => Opcode,
in_Bus => RData_in,
-- Controle para o Registrer File.
crt_RFile => crt_RFile,
en_Raddress_RF => en_Raddress_RF,
address_RF => address_RF,
-- Controle para os registradores Intermediarios.
en_R1A_ULA => en_R1A_ULA,
en_R1B_ULA => en_R1B_ULA,
en_R2_ULA => en_R2_ULA,
en_Reg_SH => en_Reg_SH,
-- Controle para os multiplexadores.
crt_Mux_ULA => crt_Mux_ULA,
crt_Mux_Acc => crt_Mux_Acc,
crt_Mux_RF => crt_Mux_RF,
-- Controle das unidades funcionais.
crt_ULA => crt_ULA,
crt_SH => crt_SH,
crt_Acc => crt_Acc,
-- Controle do PC.
en_Out_PC => en_Out_PC,
load_PC => load_PC,
inc_PC => inc_PC,
-- Controle para o sistema de IO.
en_ROpcode => en_ROpcode,
en_RMem => en_RMem,
en_RMem_Inc => en_RMem_Inc,
en_RData_in => en_RData_in,
en_RData_out => en_RData_out,
crt_Mux_IO => crt_Mux_IO,
crt_MEM => crt_MEM,
-- Valor do comprimento do shift.
S_SH => S_SH,
-- Valor do campo imediato
out_IMM => out_IMM);
---------------------------------------------------------------------------
-- Instância do Datapath.
DPATH: Mips8B_DataPath
Generic Map( N => 8,
RF_SIZE => 8,
SH_SIZE => 3,
RF_ADDR_SIZE => 3)
Port Map(clock => Clock,
-- Controle dos Registradores do Shift Register.
en_Reg_SH => en_Reg_SH,
-- Controle para Shifter.
crt_SH => crt_SH,
S_SH => S_SH,
-- Controle dos Registradores da ULA.
en_R1A_ULA => en_R1A_ULA,
en_R1B_ULA => en_R1B_ULA,
en_R2_ULA => en_R2_ULA,
-- Controle para ULA.
crt_ULA => crt_ULA,
crt_Mux_ULA => crt_Mux_ULA,
-- Controle para Register File.
crt_RFile => crt_RFile,
crt_Mux_RF => crt_Mux_RF,
address_RF => address_RF,
en_Raddress_RF => en_Raddress_RF,
-- Controle para o Acumulador.
crt_Acc => crt_Acc,
crt_Mux_Acc => crt_Mux_Acc,
-- Entradas do Datapath.
in_PC => out_PC,
in_IMM => out_IMM,
-- Flag de Igualdade de Operandos.
eq_Flag => eq_Flag,
-- Saida do resultado do Acumulador.
out_Acc => out_Acc);
End Architecture struct;
Configuration Mips8B_Core_struct_conf of Mips8B_Core is
For struct
For PC_Unity: PC_System Use Entity Work.PC_System(behave);
End For;
For IO_System: MIPS8B_IO_System Use Entity Work.MIPS8B_IO_System(behave);
End For;
For Main_Control: MIPS8B_DP_Control Use Entity Work.MIPS8B_DP_Control(behave);
End For;
For DPATH: Mips8B_DataPath Use Entity Work.Mips8B_DataPath(behave);
End For;
End For;
End Configuration Mips8B_Core_struct_conf;
| unlicense |
ricardo-jasinski/vhdl-bit-matrix-lib | testbenches/tbu_assert_pkg.vhd | 1 | 4003 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
use work.tbu_text_out_pkg.all;
-- Routines to help write testbenches at a higher level of abstraction
package tbu_assert_pkg is
constant REAL_DELTA_MAX: real := 0.001;
constant FLOAT_DELTA_MAX: real := 0.001;
procedure assert_that(msg: string; expr: boolean);
procedure assert_that(msg: string; expr: std_logic);
procedure assert_that(msg: string; actual, expected: std_logic_vector);
procedure assert_that(msg: string; actual, expected: unsigned);
procedure assert_that(msg: string; actual, expected, tolerance: real := REAL_DELTA_MAX);
procedure assert_that(msg: string; actual, expected: float; tolerance: real := FLOAT_DELTA_MAX);
end;
package body tbu_assert_pkg is
procedure assert_that(msg: string; expr: boolean) is begin
assert expr report "error in test case '" & msg & "'" severity failure;
put("- " & msg);
end;
procedure assert_that(msg: string; expr: std_logic) is begin
assert_that(msg, ?? expr);
end;
function character_from_std_ulogic(value: std_ulogic) return character is
type conversion_array_type is array (std_ulogic) of character;
constant CONVERSION_ARRAY: conversion_array_type := (
'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1',
'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'
);
begin
return CONVERSION_ARRAY(value);
end;
function string_from_std_logic_vector(vector : std_logic_vector) return string is
variable vector_string : string(1 to vector'length);
begin
for i in vector'range loop
vector_string(i + 1) := character_from_std_ulogic(vector(i));
end loop;
return vector_string;
end;
procedure assert_that(msg : string; actual, expected: std_logic_vector) is
begin
put("- " & msg);
if (actual /= expected) then
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & string_from_std_logic_vector(actual) & ", " &
"expected: " & string_from_std_logic_vector(expected)
severity failure;
end if;
end procedure;
procedure assert_that(msg : string; actual, expected: unsigned) is
begin
put("- " & msg);
if (actual /= expected) then
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(actual) & ", " &
"expected: " & to_string(expected)
severity failure;
end if;
end procedure;
procedure assert_that(msg : string; actual, expected, tolerance: real := REAL_DELTA_MAX) is begin
put("- " & msg);
-- we need to check with "<=" because the default comparison result for
-- metavalues is 'false'; otherwise, whenever a value were 'X' the test would pass
if (abs(actual - expected) <= tolerance) then
return;
end if;
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(actual) & ", " &
"expected: " & to_string(expected)
severity failure;
end procedure;
procedure assert_that(msg: string; actual, expected: float; tolerance: real := FLOAT_DELTA_MAX) is begin
put("- " & msg);
-- we need to check with "<=" because the default comparison result for
-- metavalues is 'false'; otherwise, whenever a value were 'X' the test would pass
if (abs(actual - expected) <= tolerance) then
return;
end if;
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(to_real(actual)) & ", " &
"expected: " & to_string(to_real(expected))
severity failure;
end procedure;
end;
| unlicense |
krabo0om/pauloBlaze | sources/op_codes.vhd | 2 | 5423 | -- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package op_codes is
constant OP_LOAD_SX_SY : unsigned(5 downto 0) := "000000";
constant OP_LOAD_SX_KK : unsigned(5 downto 0) := "000001";
constant OP_STAR_SX_SY : unsigned(5 downto 0) := "010110";
constant OP_AND_SX_SY : unsigned(5 downto 0) := "000010";
constant OP_AND_SX_KK : unsigned(5 downto 0) := "000011";
constant OP_OR_SX_SY : unsigned(5 downto 0) := "000100";
constant OP_OR_SX_KK : unsigned(5 downto 0) := "000101";
constant OP_XOR_SX_SY : unsigned(5 downto 0) := "000110";
constant OP_XOR_SX_KK : unsigned(5 downto 0) := "000111";
constant OP_ADD_SX_SY : unsigned(5 downto 0) := "010000";
constant OP_ADD_SX_KK : unsigned(5 downto 0) := "010001";
constant OP_ADDCY_SX_SY : unsigned(5 downto 0) := "010010";
constant OP_ADDCY_SX_KK : unsigned(5 downto 0) := "010011";
constant OP_SUB_SX_SY : unsigned(5 downto 0) := "011000";
constant OP_SUB_SX_KK : unsigned(5 downto 0) := "011001";
constant OP_SUBCY_SX_SY : unsigned(5 downto 0) := "011010";
constant OP_SUBCY_SX_KK : unsigned(5 downto 0) := "011011";
constant OP_TEST_SX_SY : unsigned(5 downto 0) := "001100";
constant OP_TEST_SX_KK : unsigned(5 downto 0) := "001101";
constant OP_TESTCY_SX_SY : unsigned(5 downto 0) := "001110";
constant OP_TESTCY_SX_KK : unsigned(5 downto 0) := "001111";
constant OP_COMPARE_SX_SY : unsigned(5 downto 0) := "011100";
constant OP_COMPARE_SX_KK : unsigned(5 downto 0) := "011101";
constant OP_COMPARECY_SX_SY : unsigned(5 downto 0) := "011110";
constant OP_COMPARECY_SX_KK : unsigned(5 downto 0) := "011111";
constant OP_SL0_SX : unsigned(5 downto 0) := "010100";
constant OP_SL1_SX : unsigned(5 downto 0) := "010100";
constant OP_SLX_SX : unsigned(5 downto 0) := "010100";
constant OP_SLA_SX : unsigned(5 downto 0) := "010100";
constant OP_RL_SX : unsigned(5 downto 0) := "010100";
constant OP_SR0_SX : unsigned(5 downto 0) := "010100";
constant OP_SR1_SX : unsigned(5 downto 0) := "010100";
constant OP_SRX_SX : unsigned(5 downto 0) := "010100";
constant OP_SRA_SX : unsigned(5 downto 0) := "010100";
constant OP_RR_SX : unsigned(5 downto 0) := "010100";
constant OP_REGBANK_A : unsigned(5 downto 0) := "110111";
constant OP_REGBANK_B : unsigned(5 downto 0) := "110111";
constant OP_INPUT_SX_SY : unsigned(5 downto 0) := "001000";
constant OP_INPUT_SX_PP : unsigned(5 downto 0) := "001001";
constant OP_OUTPUT_SX_SY : unsigned(5 downto 0) := "101100";
constant OP_OUTPUT_SX_PP : unsigned(5 downto 0) := "101101";
constant OP_OUTPUTK_KK_P : unsigned(5 downto 0) := "101011";
constant OP_STORE_SX_SY : unsigned(5 downto 0) := "101110";
constant OP_STORE_SX_SS : unsigned(5 downto 0) := "101111";
constant OP_FETCH_SX_SY : unsigned(5 downto 0) := "001010";
constant OP_FETCH_SX_SS : unsigned(5 downto 0) := "001011";
constant OP_DISABLE_INTERRUPT : unsigned(5 downto 0) := "101000";
constant OP_ENABLE_INTERRUPT : unsigned(5 downto 0) := "101000";
constant OP_RETURNI_DISABLE : unsigned(5 downto 0) := "101001";
constant OP_RETURNI_ENABLE : unsigned(5 downto 0) := "101001";
constant OP_JUMP_AAA : unsigned(5 downto 0) := "100010";
constant OP_JUMP_Z_AAA : unsigned(5 downto 0) := "110010";
constant OP_JUMP_NZ_AAA : unsigned(5 downto 0) := "110110";
constant OP_JUMP_C_AAA : unsigned(5 downto 0) := "111010";
constant OP_JUMP_NC_AAA : unsigned(5 downto 0) := "111110";
constant OP_JUMP_SX_SY : unsigned(5 downto 0) := "100110";
constant OP_CALL_AAA : unsigned(5 downto 0) := "100000";
constant OP_CALL_Z_AAA : unsigned(5 downto 0) := "110000";
constant OP_CALL_NZ_AAA : unsigned(5 downto 0) := "110100";
constant OP_CALL_C_AAA : unsigned(5 downto 0) := "111000";
constant OP_CALL_NC_AAA : unsigned(5 downto 0) := "111100";
constant OP_CALL_SX_SY : unsigned(5 downto 0) := "100100";
constant OP_RETURN : unsigned(5 downto 0) := "100101";
constant OP_RETURN_Z : unsigned(5 downto 0) := "110001";
constant OP_RETURN_NZ : unsigned(5 downto 0) := "110101";
constant OP_RETURN_C : unsigned(5 downto 0) := "111001";
constant OP_RETURN_NC : unsigned(5 downto 0) := "111101";
constant OP_LOADRETURN_SX_KK : unsigned(5 downto 0) := "100001";
constant OP_HWBUILD_SX : unsigned(5 downto 0) := "010100";
end op_codes;
package body op_codes is
end op_codes;
| apache-2.0 |
kumasento/zedboard-thesis | examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_1/synth/system_axi_gpio_0_1.vhd | 1 | 9636 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_axi_gpio_0_1;
ARCHITECTURE system_axi_gpio_0_1_arch OF system_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_1_arch : ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_1_arch;
| apache-2.0 |
kumasento/zedboard-thesis | examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd | 32 | 49938 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| apache-2.0 |
kumasento/zedboard-thesis | examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/slave_attachment.vhd | 6 | 24067 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
| apache-2.0 |
h397wang/Lab1 | lab1-fans/lab1_code.vhd | 1 | 2149 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- The above libaries lines must be included in every VHDL file, before EVERY ENTITY!
--
-- Main circuit Entity: connects all wires to the FPGA IO pins.
-- PORT mapping - declare all wire connections to INput or OUTput pins.
-- Note that all signal names here are fixed by the "DE2_pins.csv" file which you must use for every lab
--
entity Lab1 is port(
key : in std_logic_vector(2 downto 0); -- 3 push buttons on the board - HIGH when not pressed
sw : in std_logic_vector(1 downto 1); -- use 1 out of 18 switches on the board LOW when down towards edge of board
ledr : out std_logic_vector(0 downto 0); -- 1 red LED, if lit, indicates brake control is on
ledg : out std_logic_vector(0 downto 0) -- 1 green LED, if lit, indicates gas control is on
);
end Lab1;
architecture CarSimulator of Lab1 is
--
-- Create the temporary variables reprensting our input signals
--
-- Signals are either a vector or not. A vector is a group of two or more signals
--
-- Note that there are two basic types and we nearly always use std_logic:
-- UNSIGNED is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal gas, clutch, brake, override: std_logic; -- four signals for inputs
signal gas_control, brake_control: std_logic; -- two signals for LED outputs (one green and one red)
-- The function of CarSimulator entity is defined here
begin
-- Associate the input signals with the corresponding engine function
gas <= not key(0);
clutch <= not key(1);
brake <= not key(2);
override <= not sw(1);
-- The outputs of gas_control and brake_control are defined with the following boolean functions
gas_control <= (not override) and (not brake) and (not clutch) and gas;
brake_control <= override or brake;
-- assign intermediate signals to output ports
ledg(0) <= gas_control;
ledr(0) <= brake_control;
end CarSimulator;
| apache-2.0 |
hoglet67/AtomFpga | src/common/AtomPL8.vhd | 2 | 7621 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity AtomPL8 is
port (
-- Atom side
clk : in std_logic;
enable : in std_logic;
nRST : in std_logic; -- Reset from 6502
RW : in std_logic; -- R/W
Addr : in std_logic_vector(2 downto 0); -- CPU Address bus
DataIn : in std_logic_vector(7 downto 0); -- CPU Data bus (in)
DataOut : out std_logic_vector(7 downto 0); -- CPU Data bus (out)
-- AVR side
AVRDataIn : in std_logic_vector(7 downto 0); -- AVR 'Data bus' PC0..7 on AVR
AVRDataOut : out std_logic_vector(7 downto 0); -- AVR 'Data bus' PC0..7 on AVR
nARD : in std_logic; -- Read strobe from AVR PB0 on AVR
nAWR : in std_logic; -- Write strobe from AVR PB1 on AVR
AVRA0 : in std_logic; -- Address line from AVR
AVRINTOut : out std_logic; -- Inturrupt to AVR PB2 on AVR
-- Test
AtomIORDOut : out std_logic;
AtomIOWROut : out std_logic
);
end AtomPL8;
architecture Behavioral of AtomPL8 is
-- Combinatorial signals
signal RDS : std_logic;
signal WDS : std_logic;
signal AtomRD : std_logic;
signal AtomWR : std_logic;
signal AtomIO : std_logic;
signal AtomIORD : std_logic;
signal AtomIOWR : std_logic;
signal AVRStatus : std_logic;
signal AVRStatusRD : std_logic;
signal AtomCMDWR : std_logic;
signal nAVRRDData : std_logic;
signal AtomDataOut : std_logic_vector(7 downto 0);
signal Test1 : std_logic;
signal Test2 : std_logic;
-- Atom to AVR and AVR to Atom registers
signal AtomToAVR : std_logic_vector(7 downto 0);
signal AVRToAtom : std_logic_vector(7 downto 0);
signal AddrLatch : std_logic_vector(2 downto 0);
signal AtomRW : std_logic;
signal AVRINT : std_logic;
-- Handshake bits
signal AtomW_AVRR : std_logic; -- Set by Atom write, cleared by AVR read.
signal AVRW_AtomR : std_logic; -- Set by AVR write, cleared by Atom read.
signal AVRBusy : std_logic; -- Set by Atom write, cleard by AVR write
-- Edge detection bits
signal AtomIORD1 : std_logic;
signal AtomIOWR1 : std_logic;
signal nAVRRDData1: std_logic;
signal AVRINT1 : std_logic;
signal nAWR1 : std_logic;
signal AtomCMDWR1 : std_logic;
begin
-- ==========================================================
-- Combinatorial logic
-- ==========================================================
-- Atom read strobes and address decodes
RDS <= RW;
WDS <= not RW;
AtomRD <= RDS and enable;
AtomWR <= WDS and enable;
AtomIO <= '1' when (Addr >= "000" and Addr <= "011") else '0';
AtomCMDWR <= '1' when (Addr = "000" and AtomWR = '1') else '0';
AVRStatus <= '1' when (Addr = "100") else '0';
Test1 <= '1' when (Addr = "101") else '0';
Test2 <= '1' when (Addr = "110") else '0';
AVRStatusRD <= AVRStatus and AtomRD;
AtomIORD <= AtomIO and AtomRD;
AtomIOWR <= AtomIO and AtomWR;
-- goes low when AVR reads data.
nAVRRDData <= nARD or AVRA0;
-- Signal to the AVR that the Atom has read or written
AVRINT <= AtomIORD or AtomIOWR;
AVRINTOut <= AVRInt;
-- Assign AtomDataOut, depending on if reading staus or data
AtomDataOut <= ("00000" & AVRW_AtomR & AtomW_AVRR & AVRBusy) when AVRStatus = '1' else
( "000" & AtomRW & "0" & AddrLatch) when Test1 = '1' else
AtomToAVR when Test2 = '1' else
AVRToAtom;
-- When the Atom reads give it the AVR data
-- Data = AtomRD ? AtomDataOut : 8'bz;
DataOut <= AtomDataOut;
-- Assign AVRDataOut, depending on if reading staus or data
AVRDataOut <= ("000" & AtomRW & "0" & AddrLatch) when AVRA0 = '1' else AtomToAVR;
AtomIORDOut <= AtomIORD;
AtomIOWROut <= AtomIOWR;
-- ==========================================================
-- Synchronous logic
-- ==========================================================
EdgeProcess : process (nRST, clk)
begin
if nRST = '0' then
AtomIORD1 <= '0';
AtomIOWR1 <= '0';
nAVRRDData1 <= '0';
AVRINT1 <= '0';
nAWR1 <= '0';
AtomCMDWR1 <= '0';
elsif rising_edge(clk) then
AtomIORD1 <= AtomIORD;
AtomIOWR1 <= AtomIOWR;
nAVRRDData1 <= nAVRRDData;
AVRINT1 <= AVRINT;
nAWR1 <= nAWR;
AtomCMDWR1 <= AtomCMDWR;
end if;
end process;
-- Capture the bottom 3 address lines on a write by the Atom.
AddrLatchProcess : process (nRST, clk)
begin
if nRST = '0' then
AddrLatch <= "000";
elsif rising_edge(clk) and (AtomIOWR = '1' and AtomIOWR1 = '0') then
AddrLatch <= Addr;
end if;
end process;
-- Latch read or write
AtomRWProcess : process (clk)
begin
if rising_edge(clk) and ((AtomIOWR = '1' and AtomIOWR1 = '0') or (AtomIORD = '1' and AtomIORD1 = '0')) then
AtomRW <= RW;
end if;
end process;
-- Latch Atom to AVR reg on atom write
-- This may be dodgy on this edge!!
AtomToAVRProcess : process (clk)
begin
if rising_edge(clk) and (AtomIOWR = '1' and AtomIOWR1 = '0') then
AtomToAVR <= DataIn;
end if;
end process;
-- Latch AVR to Atom on AVR write
AVRToAtomProcess : process (clk)
begin
if rising_edge(clk) and nAWR = '0' and nAWR1 = '1' then
AVRToAtom <= AVRDataIn;
end if;
end process;
-- Handshake lines.
-- AtomW_AVRR set by a write from the Atom, cleared by a read by the AVR.
-- Cleared on reset.
AtomW_AVRRProcess : process (nRST, clk)
begin
if nRST = '0' then
AtomW_AVRR <= '0';
elsif rising_edge(clk) then
if (AtomIOWR = '1' and AtomIOWR1 = '0') then
AtomW_AVRR <= '1';
elsif (nAVRRDData = '1' and nAVRRDData1 = '0') then
AtomW_AVRR <= '0';
end if;
end if;
end process;
-- AVRW_AtomR set by a write from the AVR, cleared by a read by the Atom.
-- Cleared on reset.
AVRW_AtomRLatch : process (nRST, clk)
begin
if nRST = '0' then
AVRW_AtomR <= '0';
elsif rising_edge(clk) then
if (AtomIORD = '1' and AtomIORD1 = '0') then
AVRW_AtomR <= '0';
elsif (nAWR = '1' and nAWR1 = '0') then
AVRW_AtomR <= '1';
end if;
end if;
end process;
-- AVRBusy set by Atom write to command register, reset by AVR write, as all
-- commands should return at least one byte (status or data)
-- We use posedge nAVRW, so that busy is not reset until the data has been written
-- by the AVR, and is ready to be read by the Atom.
AVRBusyProcess : process (nRST, clk)
begin
if nRST = '0' then
AVRBusy <= '0';
elsif rising_edge(clk) then
if (AtomCMDWR = '1' and AtomCMDWR1 = '0') then
AVRBusy <= '1';
elsif (nAWR = '1' and nAWR1 = '0') then
AVRBusy <= '0';
end if;
end if;
end process;
end Behavioral;
| apache-2.0 |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit | second_level_CLA.vhd | 1 | 1803 | -------------------------------------------------------------------------------
--
-- Title : second_level_CLA
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\second_level_CLA.vhd
-- Generated : Sun Nov 20 16:59:32 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {second_level_CLA} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity second_level_CLA is
port(
c0: in std_logic;
Pi: in std_logic_vector (3 downto 0);
Gi: in std_logic_vector (3 downto 0);
Ci: out std_logic_vector (4 downto 1);
P64bit: out std_logic;
G64bit: out std_logic
);
end second_level_CLA;
--}} End of automatically maintained section
architecture structural of second_level_CLA is
begin
Ci(1) <= Gi(0) or (Pi(0) and c0); --C1 = c4
Ci(2) <= Gi(1) or (Pi(1) and Gi(0)) or (Pi(1) and Pi(0) and c0); --C2 = c8
Ci(3) <= Gi(2) or (Pi(2) and Gi(1)) or (Pi(2) and Pi(1) and Gi(0)) or (Pi(2) and Pi(1) and Pi(0) and c0); --C3 == c12
Ci(4) <= Gi(3) or (Pi(3) and Gi(2)) or (Pi(3) and Pi(2) and Gi(1)) or (Pi(3) and Pi(2) and Pi(1) and Gi(0)) or (Pi(3) and Pi(2) and Pi(1) and Pi(0) and c0); --C4 ==c16
P64bit <= Pi(3) and Pi(2) and Pi(1) and Pi(0);
G64bit <= Gi(3) and Gi(2) and Gi(1) and Gi(0);
end structural;
| apache-2.0 |
daringer/schemmaker | testdata/new/circuit_bi1_0op944_2.vhdl | 2 | 3738 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_3.vhdl | 1 | 5055 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 |
daringer/schemmaker | testdata/new/circuit_bi1_0op978_13.vhdl | 1 | 5463 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net7
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_15.vhdl | 1 | 5465 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_flashspi.vhd | 1 | 18637 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end;
architecture arch_axi4_flashspi of axi4_flashspi is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_SPI_FLASH
);
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
type state_type is (idle, wsetup, rsetup, txcmd, rbyte, wbyte, rd_complete, wr_complete, wr_accept);
type page_buf_type is array (0 to 31) of std_logic_vector(31 downto 0); --128 bytes
type registers is record
scaler : std_logic_vector(31 downto 0);
scaler_cnt : std_logic_vector(31 downto 0);
state : state_type;
rready : std_logic;
wready : std_logic;
-- Access to control registers always 4 bytes only
raddr : std_logic_vector(17 downto 2);
rdata : std_logic_vector(63 downto 0);
waddr : std_logic_vector(7 downto 2);
wdata : std_logic_vector(31 downto 0);
csn : std_logic;
sck : std_logic;
op64 : std_logic;
so_shifter : std_logic_vector(31 downto 0);
si_shifter : std_logic_vector(63 downto 0);
cmdbit_cnt : integer range 0 to 31;
databyte_cnt : integer range 0 to 255;
databyte_mask : std_logic_vector(6 downto 0);
wraccess : std_logic;
bytes_received : integer range 0 to 8;
buf_addr : std_logic_vector(6 downto 0);
end record;
constant R_RESET : registers := (
(others => '0'), (others => '0'), idle, -- scaler, scaler_cnt, state
'0', '0', -- rready, wready
(others => '0'), (others => '0'), -- raddr, rdata
(others => '0'), (others => '0'), -- waddr, wdata
'1', '0', '0', -- csn, sck, op64
(others => '0'), (others => '0'), -- so_shifter, si_shifter
0, 0, -- cmdbit_cnt, databyte_cnt
(others => '0'), '0', -- databyte_mask, wraccess
0, (others => '0') -- bytes_received, buf_addr
);
signal wb_page_addr : std_logic_vector(4 downto 0);
signal wb_page_rdata0 : std_logic_vector(31 downto 0);
signal wb_page_wdata0 : std_logic_vector(31 downto 0);
signal w_page_we0 : std_logic;
signal pagebuf0 : page_buf_type;
signal wb_page_rdata1 : std_logic_vector(31 downto 0);
signal wb_page_wdata1 : std_logic_vector(31 downto 0);
signal w_page_we1 : std_logic;
signal pagebuf1 : page_buf_type;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_data_ready : std_logic;
signal r, rin : registers;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_data_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_spi, r, wb_page_rdata0, wb_page_rdata1,
w_bus_re, wb_bus_raddr, wb_bus_waddr, w_bus_we,
wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable posedge_flag : std_logic;
variable negedge_flag : std_logic;
variable vb_page_addr_mux : std_logic_vector(4 downto 0);
variable vb_page_addr : std_logic_vector(4 downto 0);
variable vb_page_wdata0 : std_logic_vector(31 downto 0);
variable v_page_we0 : std_logic;
variable vb_page_wdata1 : std_logic_vector(31 downto 0);
variable v_page_we1 : std_logic;
begin
v := r;
vb_page_addr := (others => '0');
vb_page_wdata0 := (others => '0');
v_page_we0 := '0';
vb_page_wdata1 := (others => '0');
v_page_we1 := '0';
v.rready := '0';
v.wready := '0';
w_data_ready <= r.rready or r.wready;
-- system bus clock scaler to baudrate:
posedge_flag := '0';
negedge_flag := '0';
if r.scaler /= zero32 then
if r.csn = '1' then
v.scaler_cnt := zero32;
v.sck := '0';
elsif r.scaler_cnt = (r.scaler-1) then
v.scaler_cnt := zero32;
v.sck := not r.sck;
posedge_flag := not r.sck;
negedge_flag := r.sck;
else
v.scaler_cnt := r.scaler_cnt + 1;
end if;
end if;
case r.state is
when idle =>
v.so_shifter := (others => '0');
v.csn := '1';
v.sck := '0';
when rsetup =>
v.wraccess := '0';
v.bytes_received := 0;
if r.raddr(17) = '1' then
-- Control registers:
case conv_integer(r.raddr(16 downto 2)) is
when 0 =>
v.state := rd_complete;
v.si_shifter(31 downto 0) := r.scaler;
v.si_shifter(63 downto 32) := (others => '0');
v.bytes_received := 1; -- to avoid bytes swapping
when 4 => -- Read Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"05000000";
v.si_shifter := (others => '0');
when 6 => -- Read Flash ID and Release from Deep Power-down
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0; -- Read one Byte Manufacturer ID = 0x29
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"AB000000";
v.si_shifter := (others => '0');
when others =>
v.state := rd_complete;
v.si_shifter := (others => '0');
end case;
else
-- Access to SPI
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
if r.op64 = '1' then
v.databyte_cnt := 7;
else
v.databyte_cnt := 3;
end if;
v.databyte_mask := (others => '0');
-- [31:24] - command 0x3 = READ
-- [23:17] - ignored by flash
-- [16:0] - address
v.so_shifter := X"03" & "0000000" & r.raddr(16 downto 2) & "00";
end if;
when wsetup =>
-- Only control request. Write to page buffer doesn't get here:
v.wraccess := '1';
case conv_integer(r.waddr) is
when 0 =>
v.state := wr_complete;
v.scaler := r.wdata;
when 4 => -- Write Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 15;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"01" & r.wdata(7 downto 0) & X"0000";
when 8 => -- Write Enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"06000000";
when 10 => -- Page Write
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enter 'wbyte' state
v.so_shifter := X"02" & r.wdata(23 downto 8) & X"00";
v.buf_addr := (others => '0');
when 12 => -- Write Disable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"04000000";
when 14 => -- Page Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"42" & r.wdata(23 downto 0);
when 16 => -- Sector Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"D8" & r.wdata(23 downto 0);
when 18 => -- Chip Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"C7000000";
when 20 => -- Deep Power-Down mode enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"B9000000";
when others =>
v.state := wr_complete;
end case;
when txcmd =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
if r.cmdbit_cnt = 0 then
if r.databyte_mask = "0000000" then
if r.wraccess = '1' then
v.state := wbyte;
-- Transmit 256 bytes of page buffer starting from 0 offset
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
v.buf_addr := r.buf_addr + 1;
v.databyte_cnt := 3;
else
v.state := rbyte;
end if;
else
if r.wraccess = '1' then
v.state := wr_complete;
else
v.state := rd_complete;
end if;
end if;
else
v.cmdbit_cnt := r.cmdbit_cnt - 1;
end if;
end if;
when rbyte =>
if posedge_flag = '1' then
v.si_shifter := r.si_shifter(62 downto 0) & i_spi.SDI;
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.bytes_received := r.bytes_received + 1;
if r.databyte_cnt = 0 then
v.state := rd_complete;
else
v.databyte_cnt := r.databyte_cnt - 1;
v.databyte_mask := (others => '0');
end if;
end if;
end if;
when rd_complete =>
v.rready := '1'; -- End of access wait-states
if r.bytes_received = 8 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(39 downto 32) & r.si_shifter(47 downto 40)
& r.si_shifter(55 downto 48) & r.si_shifter(63 downto 56);
elsif r.bytes_received = 4 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24);
else
v.rdata := r.si_shifter;
end if;
v.state := idle;
when wbyte =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.databyte_mask := (others => '0');
if r.databyte_cnt = 0 then
v.buf_addr := r.buf_addr + 1;
if conv_integer(r.buf_addr) = 64 then
v.state := wr_complete;
elsif r.buf_addr(0) = '1' then
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata1(7 downto 0) & wb_page_rdata1(15 downto 8)
& wb_page_rdata1(23 downto 16) & wb_page_rdata1(31 downto 24);
else
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
end if;
else
v.databyte_cnt := r.databyte_cnt - 1;
end if;
end if;
end if;
when wr_complete =>
if wait_while_write then
v.wready := '1'; -- End of access wait-states
end if;
v.state := wr_accept;
v.csn := '1';
when wr_accept =>
-- To avoid re-accept the same write request
v.state := idle;
when others =>
end case;
if w_bus_re = '1' then
v.state := rsetup;
v.raddr := wb_bus_raddr(0)(17 downto 2);
if wb_bus_raddr(0)(2) = '1' then
v.op64 := '0';
else
v.op64 := '1';
end if;
end if;
-- Wait states: Read and Write transaction takes at least 1 wait state, except
-- 0 clocks (no wait states). Writing into page buffer
-- 1 clock. Read/Write control register without access to SPI Flash (scaler, example)
-- N clocks. When access to Flash, depending length of SPI sequence and scaler.
if w_bus_we = '1' then
wstrb := wb_bus_wstrb;
if wb_bus_waddr(0)(17) = '0' then
-- Write to page buffer
v.wready := '1'; -- No wait states needed
vb_page_addr := wb_bus_waddr(0)(7 downto 3);
if wb_bus_waddr(0)(2) = '0' then
-- 4 or 8 bytes
v_page_we0 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata0 := wb_bus_wdata(31 downto 0);
v_page_we1 := wstrb(7) or wstrb(6) or wstrb(5) or wstrb(4);
vb_page_wdata1 := wb_bus_wdata(63 downto 32);
else
-- 4-bytes only
v_page_we0 := '0';
vb_page_wdata0 := (others => '0');
v_page_we1 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata1 := wb_bus_wdata(31 downto 0);
end if;
elsif r.state = idle then
if not wait_while_write then
v.wready := '1';
end if;
v.state := wsetup;
-- Only 4-bytes access to control registers:
if wb_bus_waddr(0)(2) = '0' and wstrb = X"F0" then
v.waddr := wb_bus_waddr(1)(7 downto 2);
v.wdata := wb_bus_wdata(63 downto 32);
else
v.waddr := wb_bus_waddr(0)(7 downto 2);
v.wdata := wb_bus_wdata(31 downto 0);
end if;
end if;
end if;
if r.state = txcmd or r.state = wbyte then
vb_page_addr_mux := r.buf_addr(5 downto 1);
else
vb_page_addr_mux := vb_page_addr;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_page_addr <= vb_page_addr_mux;
wb_page_wdata0 <= vb_page_wdata0;
w_page_we0 <= v_page_we0;
wb_page_wdata1 <= vb_page_wdata1;
w_page_we1 <= v_page_we1;
end process;
cfg <= xconfig;
o_spi.SDO <= r.so_shifter(31);
o_spi.SCK <= r.sck;
o_spi.nCS <= r.csn;
o_spi.nWP <= '1';
o_spi.nHOLD <= '1';
o_spi.RESET <= '0';
reg : process (nrst, clk, wb_page_addr, w_page_we0, wb_page_wdata0,
w_page_we1, wb_page_wdata1)
begin
if nrst = '0' then
pagebuf0 <= (others => (others => '1'));
pagebuf1 <= (others => (others => '1'));
elsif rising_edge(clk) then
if w_page_we0 = '1' then
pagebuf0(conv_integer(wb_page_addr)) <= wb_page_wdata0;
end if;
if w_page_we1 = '1' then
pagebuf1(conv_integer(wb_page_addr)) <= wb_page_wdata1;
end if;
end if;
end process;
wb_page_rdata0 <= pagebuf0(conv_integer(wb_page_addr));
wb_page_rdata1 <= pagebuf1(conv_integer(wb_page_addr));
-- registers:
regs : process(nrst, clk)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; | apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/rom_tech.vhd | 1 | 1686 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity Rom_tech is
generic (
memtech : integer := 0;
abits : integer;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0)
);
end;
architecture rtl of Rom_tech is
component Rom_inferred is
generic (
abits : integer;
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0)
);
end component;
begin
genrom0 : if memtech = inferred or is_fpga(memtech) /= 0 generate
infer0 : Rom_inferred generic map (abits, sim_hexfile)
port map (clk, address, data);
end generate;
end;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/dsu/axi_dsu.vhd | 1 | 9997 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief Debug Support Unit (DSU) with AXI4 interface.
--! @details DSU provides access to the internal CPU registers via
--! 'Debug port' bus interface available only on <b>RIVER</b> CPU.
--! It is also implements a set of registers collecting bus
--! utilization statistic and additional debug information.
-----------------------------------------------------------------------------
--! VHDL base library.
library ieee;
--! VHDL base types import
use ieee.std_logic_1164.all;
--! VHDL base numeric import
use ieee.numeric_std.all;
--! SoC common functionality library.
library commonlib;
--! SoC common types import
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all; -- TODO: REMOVE ME when update dsu
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity axi_dsu is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector;
-- DMI interface
i_dmi_hartsel : in std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0);
-- Platfrom run-time statistic
i_bus_util_w : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
i_bus_util_r : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end;
architecture arch_axi_dsu of axi_dsu is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_DSU
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type state_type is (
idle,
wait_write_msb,
check_request,
dmi_request,
dmi_response,
dport_request,
dport_wait_resp,
axi_response,
axi_response_msb
);
type mst_utilization_type is array (0 to CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type mst_utilization_map_type is array (0 to 2*CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type registers is record
state : state_type;
r32 : std_logic;
wdata : std_logic_vector(63 downto 0);
-- Platform statistic:
clk_cnt : std_logic_vector(63 downto 0);
util_w_cnt : mst_utilization_type;
util_r_cnt : mst_utilization_type;
addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
rdata : std_logic_vector(63 downto 0);
write : std_logic;
end record;
constant R_RESET : registers := (
idle, '0', -- state, r32
(others => '0'), -- wdata,
(others => '0'), -- clk_cnt
(others => zero64), (others => zero64),
(others => '0'), -- addr
(others => '0'), -- rdata
'0' -- write
);
signal r, rin: registers;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal w_bus_r32 : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_axi_ready : std_logic;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_axi_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => w_bus_r32,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_dporto, i_bus_util_w, i_bus_util_r, r,
i_dmi_hartsel, i_dmi_req_ready, i_dmi_resp_valid, i_dmi_rdata,
w_bus_re, w_bus_r32, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable vdporti : dport_in_vector;
variable wb_bus_util_map : mst_utilization_map_type;
variable cpuidx : integer;
variable v_axi_ready : std_logic;
variable v_dmi_req_valid : std_logic;
variable v_dmi_resp_ready : std_logic;
begin
v := r;
v_axi_ready := '0';
v_dmi_req_valid := '0';
v_dmi_resp_ready := '0';
vdporti := (others => dport_in_none);
cpuidx := conv_integer(i_dmi_hartsel);
-- Update statistic:
v.clk_cnt := r.clk_cnt + 1;
-- TODO: move out these stuffs to bus-tracer
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
if i_bus_util_w(n) = '1' then
v.util_w_cnt(n) := r.util_w_cnt(n) + 1;
end if;
if i_bus_util_r(n) = '1' then
v.util_r_cnt(n) := r.util_r_cnt(n) + 1;
end if;
end loop;
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
wb_bus_util_map(2*n) := r.util_w_cnt(n);
wb_bus_util_map(2*n+1) := r.util_r_cnt(n);
end loop;
case r.state is
when idle =>
v_axi_ready := '1';
v.addr := (others => '0');
v.wdata := (others => '0');
v.rdata := (others => '0');
if w_bus_we = '1' then
v.write := '1';
v.addr := wb_bus_waddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.wdata := wb_bus_wdata;
if wb_bus_wstrb = X"FF" then
v.state := check_request;
elsif wb_bus_wstrb(3 downto 0) = X"F" then
v.state := wait_write_msb;
else
-- shouldn't be here, it is better to generate slave error
v.state := axi_response;
end if;
elsif w_bus_re = '1' then
v.write := '0';
v.addr := wb_bus_raddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.r32 := w_bus_r32; -- burst 2 clocks (very bad style)
v.state := check_request;
end if;
when wait_write_msb =>
v_axi_ready := '1';
if w_bus_we = '1' and wb_bus_wstrb(7 downto 4) = X"F" then
v.wdata(63 downto 32) := wb_bus_wdata(63 downto 32);
v.state := check_request;
end if;
when check_request =>
v.rdata := (others => '0');
if conv_integer(r.addr) < 3*4096 then -- 0x3000 on 3 banks
v.state := dport_request;
else
v.state := dmi_request;
end if;
when dmi_request =>
v_dmi_req_valid := '1';
if i_dmi_req_ready = '1' then
v.state := dmi_response;
end if;
when dmi_response =>
v_dmi_resp_ready := '1';
if i_dmi_resp_valid = '1' then
v.rdata(31 downto 0) := i_dmi_rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when dport_request =>
vdporti(cpuidx).req_valid := '1';
vdporti(cpuidx).write := r.write;
vdporti(cpuidx).addr := r.addr;
vdporti(cpuidx).wdata := r.wdata;
if i_dporto(cpuidx).req_ready = '1' then
v.state := dport_wait_resp;
end if;
when dport_wait_resp =>
vdporti(cpuidx).resp_ready := '1';
if i_dporto(cpuidx).resp_valid = '1' then
v.rdata := i_dporto(cpuidx).rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when axi_response =>
v_axi_ready := '1';
if r.write = '0' and r.r32 = '1' then
v.state := axi_response_msb; -- burst transaction
else
v.state := idle;
end if;
when axi_response_msb =>
v_axi_ready := '1';
v.state := idle;
when others =>
end case;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_dmi_req_valid <= v_dmi_req_valid;
o_dmi_write <= r.write;
o_dmi_addr <= r.addr(6 downto 0);
o_dmi_wdata <= r.wdata(31 downto 0);
o_dmi_resp_ready <= v_dmi_resp_ready;
o_dporti <= vdporti;
w_axi_ready <= v_axi_ready;
end process;
o_cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/ambalib/axictrl_bus0.vhd | 1 | 9099 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
entity axictrl_bus0 is
generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_slvcfg : in bus0_xslv_cfg_vector;
i_slvo : in bus0_xslv_out_vector;
i_msto : in bus0_xmst_out_vector;
o_slvi : out bus0_xslv_in_vector;
o_msti : out bus0_xmst_in_vector;
o_bus_util_w : out std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
o_bus_util_r : out std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end;
architecture arch_axictrl_bus0 of axictrl_bus0 is
type nasti_master_out_vector_miss is array (0 to CFG_BUS0_XMST_TOTAL)
of axi4_master_out_type;
type nasti_master_in_vector_miss is array (0 to CFG_BUS0_XMST_TOTAL)
of axi4_master_in_type;
type nasti_slave_out_vector_miss is array (0 to CFG_BUS0_XSLV_TOTAL)
of axi4_slave_out_type;
type nasti_slave_in_vector_miss is array (0 to CFG_BUS0_XSLV_TOTAL)
of axi4_slave_in_type;
type reg_type is record
r_midx : integer range 0 to CFG_BUS0_XMST_TOTAL;
r_sidx : integer range 0 to CFG_BUS0_XSLV_TOTAL;
w_midx : integer range 0 to CFG_BUS0_XMST_TOTAL;
w_sidx : integer range 0 to CFG_BUS0_XSLV_TOTAL;
b_midx : integer range 0 to CFG_BUS0_XMST_TOTAL;
b_sidx : integer range 0 to CFG_BUS0_XSLV_TOTAL;
end record;
constant R_RESET : reg_type := (
CFG_BUS0_XMST_TOTAL, CFG_BUS0_XSLV_TOTAL,
CFG_BUS0_XMST_TOTAL, CFG_BUS0_XSLV_TOTAL,
CFG_BUS0_XMST_TOTAL, CFG_BUS0_XSLV_TOTAL);
signal rin, r : reg_type;
signal defslv_i : axi4_slave_in_type;
signal defslv_o : axi4_slave_out_type;
begin
xdef0 : axi4_defslv generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_xslvi => defslv_i,
o_xslvo => defslv_o
);
comblogic : process(i_nrst, i_slvcfg, i_msto, i_slvo, defslv_o, r)
variable v : reg_type;
variable ar_midx : integer range 0 to CFG_BUS0_XMST_TOTAL;
variable aw_midx : integer range 0 to CFG_BUS0_XMST_TOTAL;
variable ar_sidx : integer range 0 to CFG_BUS0_XSLV_TOTAL; -- +1 miss access
variable aw_sidx : integer range 0 to CFG_BUS0_XSLV_TOTAL; -- +1 miss access
variable vmsto : nasti_master_out_vector_miss;
variable vmsti : nasti_master_in_vector_miss;
variable vslvi : nasti_slave_in_vector_miss;
variable vslvo : nasti_slave_out_vector_miss;
variable aw_fire : std_logic;
variable ar_fire : std_logic;
variable w_fire : std_logic;
variable w_busy : std_logic;
variable r_fire : std_logic;
variable r_busy : std_logic;
variable b_fire : std_logic;
variable b_busy : std_logic;
-- Bus statistic signals
variable wb_bus_util_w : std_logic_vector(CFG_BUS0_XMST_TOTAL downto 0);
variable wb_bus_util_r : std_logic_vector(CFG_BUS0_XMST_TOTAL downto 0);
begin
v := r;
for m in 0 to CFG_BUS0_XMST_TOTAL-1 loop
vmsto(m) := i_msto(m);
vmsti(m) := axi4_master_in_none;
end loop;
vmsto(CFG_BUS0_XMST_TOTAL) := axi4_master_out_none;
vmsti(CFG_BUS0_XMST_TOTAL) := axi4_master_in_none;
for s in 0 to CFG_BUS0_XSLV_TOTAL-1 loop
vslvo(s) := i_slvo(s);
vslvi(s) := axi4_slave_in_none;
end loop;
vslvo(CFG_BUS0_XSLV_TOTAL) := defslv_o;
vslvi(CFG_BUS0_XSLV_TOTAL) := axi4_slave_in_none;
ar_midx := CFG_BUS0_XMST_TOTAL;
aw_midx := CFG_BUS0_XMST_TOTAL;
ar_sidx := CFG_BUS0_XSLV_TOTAL;
aw_sidx := CFG_BUS0_XSLV_TOTAL;
-- select master bus:
for m in 0 to CFG_BUS0_XMST_TOTAL-1 loop
if i_msto(m).ar_valid = '1' then
ar_midx := m;
end if;
if i_msto(m).aw_valid = '1' then
aw_midx := m;
end if;
end loop;
-- select slave interface
for s in 0 to CFG_BUS0_XSLV_TOTAL-1 loop
if i_slvcfg(s).xmask /= X"00000" and
(vmsto(ar_midx).ar_bits.addr(CFG_SYSBUS_ADDR_BITS-1 downto 12)
and i_slvcfg(s).xmask) = i_slvcfg(s).xaddr then
ar_sidx := s;
end if;
if i_slvcfg(s).xmask /= X"00000" and
(vmsto(aw_midx).aw_bits.addr(CFG_SYSBUS_ADDR_BITS-1 downto 12)
and i_slvcfg(s).xmask) = i_slvcfg(s).xaddr then
aw_sidx := s;
end if;
end loop;
-- Read Channel:
ar_fire := vmsto(ar_midx).ar_valid and vslvo(ar_sidx).ar_ready;
r_fire := vmsto(r.r_midx).r_ready and vslvo(r.r_sidx).r_valid and vslvo(r.r_sidx).r_last;
-- Write channel:
aw_fire := vmsto(aw_midx).aw_valid and vslvo(aw_sidx).aw_ready;
w_fire := vmsto(r.w_midx).w_valid and vmsto(r.w_midx).w_last and vslvo(r.w_sidx).w_ready;
-- Write confirm channel
b_fire := vmsto(r.b_midx).b_ready and vslvo(r.b_sidx).b_valid;
r_busy := '0';
if r.r_sidx /= CFG_BUS0_XSLV_TOTAL and r_fire = '0' then
r_busy := '1';
end if;
w_busy := '0';
if (r.w_sidx /= CFG_BUS0_XSLV_TOTAL and w_fire = '0')
or (r.b_sidx /= CFG_BUS0_XSLV_TOTAL and b_fire = '0') then
w_busy := '1';
end if;
b_busy := '0';
if (r.b_sidx /= CFG_BUS0_XSLV_TOTAL and b_fire = '0') then
b_busy := '1';
end if;
if ar_fire = '1' and r_busy = '0' then
v.r_sidx := ar_sidx;
v.r_midx := ar_midx;
elsif r_fire = '1' then
v.r_sidx := CFG_BUS0_XSLV_TOTAL;
v.r_midx := CFG_BUS0_XMST_TOTAL;
end if;
if aw_fire = '1' and w_busy = '0' then
v.w_sidx := aw_sidx;
v.w_midx := aw_midx;
elsif w_fire = '1' and b_busy = '0' then
v.w_sidx := CFG_BUS0_XSLV_TOTAL;
v.w_midx := CFG_BUS0_XMST_TOTAL;
end if;
if w_fire = '1' and b_busy = '0' then
v.b_sidx := r.w_sidx;
v.b_midx := r.w_midx;
elsif b_fire = '1' then
v.b_sidx := CFG_BUS0_XSLV_TOTAL;
v.b_midx := CFG_BUS0_XMST_TOTAL;
end if;
vmsti(ar_midx).ar_ready := vslvo(ar_sidx).ar_ready and not r_busy;
vslvi(ar_sidx).ar_valid := vmsto(ar_midx).ar_valid and not r_busy;
vslvi(ar_sidx).ar_bits := vmsto(ar_midx).ar_bits;
vslvi(ar_sidx).ar_id := vmsto(ar_midx).ar_id;
vslvi(ar_sidx).ar_user := vmsto(ar_midx).ar_user;
vmsti(r.r_midx).r_valid := vslvo(r.r_sidx).r_valid;
vmsti(r.r_midx).r_resp := vslvo(r.r_sidx).r_resp;
vmsti(r.r_midx).r_data := vslvo(r.r_sidx).r_data;
vmsti(r.r_midx).r_last := vslvo(r.r_sidx).r_last;
vmsti(r.r_midx).r_id := vslvo(r.r_sidx).r_id;
vmsti(r.r_midx).r_user := vslvo(r.r_sidx).r_user;
vslvi(r.r_sidx).r_ready := vmsto(r.r_midx).r_ready;
vmsti(aw_midx).aw_ready := vslvo(aw_sidx).aw_ready and not w_busy;
vslvi(aw_sidx).aw_valid := vmsto(aw_midx).aw_valid and not w_busy;
vslvi(aw_sidx).aw_bits := vmsto(aw_midx).aw_bits;
vslvi(aw_sidx).aw_id := vmsto(aw_midx).aw_id;
vslvi(aw_sidx).aw_user := vmsto(aw_midx).aw_user;
vmsti(r.w_midx).w_ready := vslvo(r.w_sidx).w_ready and not b_busy;
vslvi(r.w_sidx).w_valid := vmsto(r.w_midx).w_valid and not b_busy;
vslvi(r.w_sidx).w_data := vmsto(r.w_midx).w_data;
vslvi(r.w_sidx).w_last := vmsto(r.w_midx).w_last;
vslvi(r.w_sidx).w_strb := vmsto(r.w_midx).w_strb;
vslvi(r.w_sidx).w_user := vmsto(r.w_midx).w_user;
vmsti(r.b_midx).b_valid := vslvo(r.b_sidx).b_valid;
vmsti(r.b_midx).b_resp := vslvo(r.b_sidx).b_resp;
vmsti(r.b_midx).b_id := vslvo(r.b_sidx).b_id;
vmsti(r.b_midx).b_user := vslvo(r.b_sidx).b_user;
vslvi(r.b_sidx).b_ready := vmsto(r.b_midx).b_ready;
-- Statistic
wb_bus_util_w := (others => '0');
wb_bus_util_w(r.w_midx) := '1';
wb_bus_util_r := (others => '0');
wb_bus_util_r(r.r_midx) := '1';
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
for m in 0 to CFG_BUS0_XMST_TOTAL-1 loop
o_msti(m) <= vmsti(m);
end loop;
for s in 0 to CFG_BUS0_XSLV_TOTAL-1 loop
o_slvi(s) <= vslvi(s);
end loop;
defslv_i <= vslvi(CFG_BUS0_XSLV_TOTAL);
o_bus_util_w <= wb_bus_util_w(CFG_BUS0_XMST_TOTAL-1 downto 0);
o_bus_util_r <= wb_bus_util_r(CFG_BUS0_XMST_TOTAL-1 downto 0);
end process;
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/tagmem.vhd | 1 | 6368 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.types_mem.all;
entity tagmem is generic (
memtech : integer := 0;
async_reset : boolean := false;
wayidx : integer := 0;
abus : integer := 64; -- system bus address bus (32 or 64 bits)
ibits : integer := 7; -- lines memory addres width (usually 6..8)
lnbits : integer := 5; -- One line bits: log2(bytes_per_line)
flbits : integer := 1; -- Total flags number saved with address tag
snoop : boolean := false -- snoop channel (only with enabled L2-cache)
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_addr : in std_logic_vector(abus-1 downto 0);
i_wstrb : in std_logic_vector(2**lnbits-1 downto 0);
i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0);
i_wflags : in std_logic_vector(flbits-1 downto 0);
o_raddr : out std_logic_vector(abus-1 downto 0);
o_rdata : out std_logic_vector(8*(2**lnbits)-1 downto 0);
o_rflags : out std_logic_vector(flbits-1 downto 0);
o_hit : out std_logic;
-- L2 snoop portm active when snoop = 1
i_snoop_addr : in std_logic_vector(abus-1 downto 0);
o_snoop_flags : out std_logic_vector(flbits-1 downto 0)
);
end;
architecture arch_tagmem of tagmem is
constant TAG_BITS : integer := abus - ibits - lnbits;
constant TAG_WITH_FLAGS : integer := TAG_BITS + flbits;
signal wb_index : std_logic_vector(ibits-1 downto 0);
signal tago_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0);
signal tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0);
signal tagi_we : std_logic;
signal wb_snoop_index : std_logic_vector(ibits-1 downto 0);
signal wb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0);
signal tago_snoop_rdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0);
signal rb_tagaddr : std_logic_vector(TAG_BITS-1 downto 0);
signal rb_index : std_logic_vector(ibits-1 downto 0);
signal rb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0);
begin
-- 1-byte memory banks combining into cache line
dx : for n in 0 to 2**lnbits-1 generate
datax : ram_tech generic map (
memtech => memtech,
abits => ibits,
dbits => 8
) port map (
i_clk => i_clk,
i_addr => wb_index,
i_wena => i_wstrb(n),
i_wdata => i_wdata(8*n+7 downto 8*n),
o_rdata => o_rdata(8*n+7 downto 8*n)
);
end generate;
tag0 : ram_tech generic map (
memtech => memtech,
abits => ibits,
dbits => TAG_WITH_FLAGS
) port map (
i_clk => i_clk,
i_addr => wb_index,
i_wena => tagi_we,
i_wdata => tagi_wdata,
o_rdata => tago_rdata
);
snoopena : if snoop generate
tagsnoop0 : ram_tech generic map (
memtech => memtech,
abits => ibits,
dbits => TAG_WITH_FLAGS
) port map (
i_clk => i_clk,
i_addr => wb_snoop_index,
i_wena => tagi_we,
i_wdata => tagi_wdata,
o_rdata => tago_snoop_rdata
);
end generate;
snoopdis : if not snoop generate
tago_snoop_rdata <= (others => '0');
end generate;
comb : process(i_nrst, i_addr, i_wstrb, i_wdata, i_wflags,
tago_rdata, tago_snoop_rdata, rb_tagaddr, rb_index)
variable vb_index : std_logic_vector(ibits-1 downto 0);
variable vb_raddr : std_logic_vector(abus-1 downto 0);
variable vb_tagi_wdata : std_logic_vector(TAG_WITH_FLAGS-1 downto 0);
variable v_hit : std_logic;
variable vb_snoop_index : std_logic_vector(ibits-1 downto 0);
variable vb_snoop_tagaddr : std_logic_vector(TAG_BITS-1 downto 0);
variable vb_snoop_flags : std_logic_vector(flbits-1 downto 0);
begin
v_hit := '0';
if rb_tagaddr = tago_rdata(TAG_BITS-1 downto 0) then
v_hit := tago_rdata(TAG_BITS); -- valid bit
end if;
vb_raddr := (others => '0');
vb_raddr(abus-1 downto ibits + lnbits) := tago_rdata(TAG_BITS-1 downto 0);
vb_raddr(ibits + lnbits - 1 downto lnbits) := rb_index;
vb_index := i_addr(ibits + lnbits - 1 downto lnbits);
vb_tagi_wdata := i_wflags & i_addr(abus-1 downto ibits + lnbits);
if snoop then
vb_snoop_flags := tago_snoop_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS);
vb_snoop_index := i_snoop_addr(ibits + lnbits - 1 downto lnbits);
vb_snoop_tagaddr := i_snoop_addr(abus - 1 downto ibits + lnbits);
if or_reduce(i_wstrb) = '1' then
vb_snoop_index := vb_index;
end if;
if rb_snoop_tagaddr /= tago_snoop_rdata(TAG_BITS-1 downto 0) then
vb_snoop_flags := (others => '0');
end if;
else
vb_snoop_flags := (others => '0');
vb_snoop_index := (others => '0');
vb_snoop_tagaddr := (others => '0');
end if;
if not async_reset and i_nrst = '0' then
vb_tagi_wdata := (others => '0');
vb_index := (others => '0');
end if;
wb_index <= vb_index;
tagi_we <= or_reduce(i_wstrb);
tagi_wdata <= vb_tagi_wdata;
o_raddr <= vb_raddr;
o_rflags <= tago_rdata(TAG_WITH_FLAGS-1 downto TAG_BITS);
o_hit <= v_hit;
wb_snoop_index <= vb_snoop_index;
wb_snoop_tagaddr <= vb_snoop_tagaddr;
o_snoop_flags <= vb_snoop_flags;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
rb_tagaddr <= (others => '0');
rb_index <= (others => '0');
rb_snoop_tagaddr <= (others => '0');
elsif rising_edge(i_clk) then
rb_tagaddr <= tagi_wdata(TAG_BITS-1 downto 0);
rb_index <= wb_index;
rb_snoop_tagaddr <= wb_snoop_tagaddr;
end if;
end process;
end;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/types_eth.vhd | 1 | 35905 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
package types_eth is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
constant eth_rx_in_none : eth_rx_ahb_in_type := (
'0', '0', (others => '0'), (others => '0'), (others => '0'));
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
iotest : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type;
iotmact : in std_ulogic;
iotdata : in std_logic_vector(9 downto 0)
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type;
iotdata : out std_logic_vector(9 downto 0));
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
component eth_axi_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in axi4_master_in_type;
aximo : out axi4_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
-- ETH registers
type eth_mdio_command_type is record
valid : std_ulogic;
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
end record;
constant eth_mdio_command_none : eth_mdio_command_type := (
'0', (others => '0'), '0', '0', (others => '0')
);
type eth_mdio_status_type is record
cmd : eth_mdio_command_type;
busy : std_ulogic;
linkfail : std_ulogic;
end record;
type eth_mac_status_type is record
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
txen : std_ulogic;
rxen : std_ulogic;
tx_int : std_ulogic;
rx_int : std_ulogic;
tx_err : std_ulogic;
rx_err : std_ulogic;
edcltx_idle : std_ulogic;
edclrx_idle : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
phystat : std_ulogic;
full_duplex : std_ulogic;
speed : std_ulogic;
reset : std_ulogic;
mdio : eth_mdio_status_type;
end record;
--! Latched values set via external Bus Interface
type eth_control_type is record
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
prom : std_ulogic;
pstatirqen : std_ulogic;
mcasten : std_ulogic;
--! Enable access to the internal FIFOs via system BUS (disabled default)
ramdebugen : std_ulogic;
--! Disable EDCL access
edcldis : std_ulogic;
disableduplex : std_ulogic;
--! Physical address.
--! Can be changed in a runtime, but become actual only after system reset.
mdio_phyadr : std_logic_vector(4 downto 0);
mac_addr : std_logic_vector(47 downto 0);
--! Tx descriptor
txdesc : std_logic_vector(31 downto 10);
--! Rx descriptor
rxdesc : std_logic_vector(31 downto 10);
--! EDCL IP
edclip : std_logic_vector(31 downto 0);
--! Multicast enabling hash value
hash : std_logic_vector(63 downto 0);
emacaddr : std_logic_vector(47 downto 0);
end record;
--! @name DBG access unique IDs to the internal FIFOs blocks.
--! @{
constant DBG_ACCESS_NONE : std_logic_vector(1 downto 0) := "00";
constant DBG_ACCESS_TX_BUFFER : std_logic_vector(1 downto 0) := "01";
constant DBG_ACCESS_RX_BUFFER : std_logic_vector(1 downto 0) := "10";
constant DBG_ACCESS_EDCL_BUFFER : std_logic_vector(1 downto 0) := "11";
--! @}
--! Bus interface read/write actions transforming into these commands.
type eth_command_type is record
--! Tx/Rx can be enabled externally but they're cleared inside of MAC
--! in a case of disabled Descriptor or in a case of BUS error.
set_txena : std_ulogic;
clr_txena : std_ulogic;
set_rxena : std_ulogic;
clr_rxena : std_ulogic;
--! Set new descriptor index in the array of descriptors table
set_txdsel : std_ulogic;
set_rxdsel : std_ulogic;
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
--! The following values can be changed during initialization stage.
set_full_duplex : std_ulogic;
clr_full_duplex : std_ulogic;
set_speed : std_ulogic;
clr_speed : std_ulogic;
set_reset : std_ulogic;
clr_reset : std_ulogic;
--! Clear status bits commands:
clr_status_tx_int : std_ulogic;
clr_status_rx_int : std_ulogic;
clr_status_tx_err : std_ulogic;
clr_status_rx_err : std_ulogic;
clr_status_txahberr : std_ulogic;
clr_status_rxahberr : std_ulogic;
clr_status_toosmall : std_ulogic;
clr_status_invaddr : std_ulogic;
clr_status_phystat : std_ulogic;
--! mdi interface command
mdio_cmd : eth_mdio_command_type;
--! Request ID values:
dbg_access_id : std_logic_vector(1 downto 0);
dbg_wr_ena : std_logic;
dbg_rd_ena : std_logic;
dbg_addr : std_logic_vector(13 downto 0);
dbg_wdata : std_logic_vector(31 downto 0);
end record;
constant eth_command_none : eth_command_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0', '0', '0', eth_mdio_command_none,
DBG_ACCESS_NONE, '0', '0', (others => '0'), (others => '0')
);
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
rx_clk : std_ulogic;
tx_dv : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_en : std_ulogic;
rx_crs : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable : std_ulogic;
end record;
constant eth_in_none : eth_in_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type := (
'0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
component grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end component;
component grethaxi is
generic(
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in axi4_master_in_type;
msto : out axi4_master_out_type;
mstcfg : out axi4_master_config_type;
msto2 : out axi4_master_out_type;
mstcfg2 : out axi4_master_config_type;
slvi : in axi4_slave_in_type;
slvo : out axi4_slave_out_type;
slvcfg : out axi4_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end component;
end package;
package body types_eth is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--function calccrc_8(data : in std_logic_vector( 7 downto 0);
-- crc : in std_logic_vector(31 downto 0))
-- return std_logic_vector is
-- variable ncrc : std_logic_vector(31 downto 0);
-- variable d : std_logic_vector(7 downto 0);
--begin
-- d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
-- d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
-- ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
-- ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
-- ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
-- ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
-- ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
-- ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
-- ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
-- ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
-- ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
-- ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
-- ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
-- ncrc(20) := d(4) xor crc(12) xor crc(28);
-- ncrc(21) := d(5) xor crc(13) xor crc(29);
-- ncrc(22) := d(0) xor crc(14) xor crc(24);
-- ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
-- ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
-- ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
-- ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
-- ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
-- ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
-- ncrc(31) := d(5) xor crc(23) xor crc(29);
-- return ncrc;
--end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/sim_gnss/asic_top.vhd | 1 | 15310 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity asic_top is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! SPI Flash/ext OTP
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
-- OTP power
io_otp_gnd : inout std_logic;
io_otp_vdd : inout std_logic;
io_otp_vdd18 : inout std_logic;
io_otp_upp : inout std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end asic_top;
architecture arch_asic_top of asic_top is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ob_pwm : std_logic_vector(1 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
signal ib_flash_si : std_logic;
signal ob_flash_so : std_logic;
signal ob_flash_sck : std_logic;
signal ob_flash_csn : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal ib_clk_adc : std_logic;
signal ib_gps_I : std_logic_vector(1 downto 0);
signal ib_gps_Q : std_logic_vector(1 downto 0);
signal ib_glo_I : std_logic_vector(1 downto 0);
signal ib_glo_Q : std_logic_vector(1 downto 0);
signal ob_pps : std_logic;
signal ib_gps_ld : std_logic;
signal ib_glo_ld : std_logic;
signal ob_max_sclk : std_logic;
signal ob_max_sdata : std_logic;
signal ob_max_ncs : std_logic_vector(1 downto 0);
signal ib_antext_stat : std_logic;
signal ib_antext_detect : std_logic;
signal ob_antext_ena : std_logic;
signal ob_antint_contr : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal wb_otp_wdata : std_logic_vector(15 downto 0);
signal wb_otp_addr : std_logic_vector(11 downto 0);
signal w_otp_we : std_logic;
signal w_otp_re : std_logic;
signal wb_otp_rdata : std_logic_vector(15 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
iflshsi : ibuf_tech generic map(CFG_PADTECH) port map (ib_flash_si, i_flash_si);
oflshso : obuf_tech generic map(CFG_PADTECH) port map (o_flash_so, ob_flash_so);
oflshsck : obuf_tech generic map(CFG_PADTECH) port map (o_flash_sck, ob_flash_sck);
oflshcsn : obuf_tech generic map(CFG_PADTECH) port map (o_flash_csn, ob_flash_csn);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pwmx : for i in 0 to 1 generate
opwm0 : obuf_tech generic map(CFG_PADTECH) port map (o_pwm(i), ob_pwm(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! GNSS sub-system
iclkadc0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
adcx : for i in 0 to 1 generate
igpsi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_I(i), i_gps_I(i));
igpsq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_Q(i), i_gps_Q(i));
igloi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_I(i), i_glo_I(i));
igloq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_Q(i), i_glo_Q(i));
end generate;
opps0 : obuf_tech generic map(CFG_PADTECH) port map (o_pps, ob_pps);
igpsld0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_ld, i_gps_ld);
iglold0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_ld, i_glo_ld);
omaxclk0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sclk, ob_max_sclk);
omaxdat0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sdata, ob_max_sdata);
omaxcs0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(0), ob_max_ncs(0));
omaxcs1 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(1), ob_max_ncs(1));
iantstat0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_stat, i_antext_stat);
iantdet0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_detect, i_antext_detect);
oanten0 : obuf_tech generic map(CFG_PADTECH) port map (o_antext_ena, ob_antext_ena);
oantctr0 : obuf_tech generic map(CFG_PADTECH) port map (o_antint_contr, ob_antint_contr);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
otp0 : otp_tech generic map (
memtech => CFG_MEMTECH
) port map (
clk => w_clk_bus, -- only for FPGA
i_we => w_otp_we,
i_re => w_otp_re,
i_addr => wb_otp_addr,
i_wdata => wb_otp_wdata,
o_rdata => wb_otp_rdata,
io_gnd => io_otp_gnd,
io_vdd => io_otp_vdd,
io_vdd18 => io_otp_vdd18,
io_upp => io_otp_upp
);
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => ob_pwm,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => ib_flash_si,
o_flash_so => ob_flash_so,
o_flash_sck => ob_flash_sck,
o_flash_csn => ob_flash_csn,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => wb_otp_rdata,
o_otp_d => wb_otp_wdata,
o_otp_a => wb_otp_addr,
o_otp_we => w_otp_we,
o_otp_re => w_otp_re,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => ib_clk_adc,
i_gps_I => ib_gps_I,
i_gps_Q => ib_gps_Q,
i_glo_I => ib_glo_I,
i_glo_Q => ib_glo_Q,
o_pps => ob_pps,
i_gps_ld => ib_gps_ld,
i_glo_ld => ib_glo_ld,
o_max_sclk => ob_max_sclk,
o_max_sdata => ob_max_sdata,
o_max_ncs => ob_max_ncs,
i_antext_stat => ib_antext_stat,
i_antext_detect => ib_antext_detect,
o_antext_ena => ob_antext_ena,
o_antint_contr => ob_antint_contr
);
end arch_asic_top;
| apache-2.0 |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/romprn_tech.vhd | 1 | 1552 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific Galileo PRN ROM codes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_tech is
component RomPrn_inferred is
port (
clk : in std_ulogic;
inAdr : in std_logic_vector(12 downto 0);
outData : out std_logic_vector(31 downto 0)
);
end component;
component RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
begin
genrom0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
romprn_infer : RomPrn_inferred port map
(
i_clk,
i_address,
o_data
);
end generate;
genrom1 : if generic_tech = mikron180 generate
romprn_micr : RomPrn_micron180 port map
(
i_clk,
i_address,
o_data
);
end generate;
end;
| apache-2.0 |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/submodules/avalon_dacad5668_interface.m.vhd | 4 | 9531 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_dacad5668_interface_pkg IS
CONSTANT c_analog_output_interface_address_width : INTEGER := 5;
COMPONENT avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_dacad5668_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_dacad5668_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE avalon_dacad5668_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000;
INTERNAL_REFERENCE : STD_LOGIC := '0'; -- '0' = set to internal reference, '1' set to external reference
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_analog_output_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_analog_output_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width);
CONSTANT c_usig_resolution_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_analog_output_interface_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_dacad5668_interface;
ARCHITECTURE rtl OF avalon_dacad5668_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
set_values : t_value_regs;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
my_dacad5668 : dacad5668
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY,INTERNAL_REFERENCE)
PORT MAP (isl_clk,ri.adc_reset_n,ri.set_values,osl_LDAC_n,osl_CLR_n,osl_sclk,oslv_Ss,osl_mosi);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data)
VARIABLE vi : t_internal_register;
VARIABLE dacad5668_part_nr: INTEGER := 0;
VARIABLE address: UNSIGNED(c_analog_output_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_analog_output_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF address = c_configuration_address THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
END IF;
ELSIF address>= c_usig_value_0_address AND address< c_usig_last_address THEN
dacad5668_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
--only 16 bit are needed cause adc resolution is 16
IF islv_avs_byteenable(0) = '1' THEN
vi.set_values(dacad5668_part_nr)(7 DOWNTO 0) := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.set_values(dacad5668_part_nr)(15 DOWNTO 8) := islv_avs_write_data(15 DOWNTO 8);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_dacad5668_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_dacad5668_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_analog_output_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_value_0_address AND address < c_usig_last_address THEN
dacad5668_part_nr := to_integer(address - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(vi.set_values(dacad5668_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.set_values(i) := (OTHERS => '0');
END LOOP;
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
| apache-2.0 |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/submodules/info_device.m.vhd | 4 | 7224 | -------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE info_device_pkg IS
CONSTANT c_int_number_of_descr_register: INTEGER := 7;
CONSTANT info_device_address_width : INTEGER := 5;
COMPONENT info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT info_device_subtype_id : INTEGER := 0;
CONSTANT info_device_interface_version : INTEGER := 0;
CONSTANT c_usig_typdef_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,info_device_address_width);
CONSTANT c_usig_mem_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,info_device_address_width);
CONSTANT c_usig_unique_id_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,info_device_address_width);
CONSTANT c_usig_dev_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, info_device_address_width);
CONSTANT c_usig_description_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + 1;
CONSTANT c_usig_max_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + c_int_number_of_descr_register;
END PACKAGE info_device_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.info_device_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END ENTITY info_device;
ARCHITECTURE rtl OF info_device IS
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,isl_clk)
VARIABLE description_part: INTEGER := 0;
VARIABLE address: UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(0,info_device_address_width);
BEGIN
--type conversion
address := UNSIGNED(islv_avs_address);
--standard values
oslv_avs_read_data <= (OTHERS => '0');
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_usig_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length));
WHEN c_usig_mem_size_address =>
oslv_avs_read_data(info_device_address_width+2) <= '1';
WHEN c_usig_unique_id_address =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_dev_size_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(dev_size,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_description_address AND address <= c_usig_max_address THEN
description_part := to_integer(address - c_usig_description_address);
oslv_avs_read_data <= description(((c_int_number_of_descr_register-description_part))*32-1 DOWNTO (c_int_number_of_descr_register-description_part-1)*32);
END IF;
END CASE;
END IF;
END PROCESS comb_proc;
osl_avs_waitrequest <= '0';
END rtl;
| apache-2.0 |
rdsalemi/uvmprimer | 10_An_Object_Oriented_Testbench/tinyalu_dut/single_cycle_add_and_xor.vhd | 24 | 3045 | -- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
| apache-2.0 |
wsoltys/AtomFpga | src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd | 4 | 896 | --**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
| apache-2.0 |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MC6847/mc6847.vhd | 1 | 30331 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mc6847 is
generic
(
T1_VARIANT : boolean := false;
CVBS_NOT_VGA : boolean := false);
port
(
clk : in std_logic;
clk_ena : in std_logic;
reset : in std_logic;
da0 : out std_logic;
videoaddr : out std_logic_vector (12 downto 0);
dd : in std_logic_vector(7 downto 0);
hs_n : out std_logic;
fs_n : out std_logic;
an_g : in std_logic;
an_s : in std_logic;
intn_ext : in std_logic;
gm : in std_logic_vector(2 downto 0);
css : in std_logic;
inv : in std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
hsync : out std_logic;
vsync : out std_logic;
hblank : out std_logic;
vblank : out std_logic;
artifact_en : in std_logic;
artifact_set : in std_logic;
artifact_phase : in std_logic;
cvbs : out std_logic_vector(7 downto 0);
black_backgnd : in std_logic;
char_a : out std_logic_vector(10 downto 0);
char_d_o : in std_logic_vector(7 downto 0)
);
end mc6847;
architecture SYN of mc6847 is
constant BUILD_DEBUG : boolean := false;
constant DEBUG_AN_G : std_logic := '1';
constant DEBUG_AN_S : std_logic := '1';
constant DEBUG_INTN_EXT : std_logic := '1';
constant DEBUG_GM : std_logic_vector(2 downto 0) := "111";
constant DEBUG_CSS : std_logic := '1';
constant DEBUG_INV : std_logic := '0';
-- H_TOTAL_PER_LINE must be divisible by 16
-- so that sys_count is the same on each line when
-- the video comes out of hblank
-- so the phase relationship between char_d_o from the 6847 and character timing is maintained
-- 14.31818 MHz : 256 X 384 == 25 * 4 / 7 approx
-- constant H_FRONT_PORCH : integer := 11-1 ; --11-1+1;
-- constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 35+2;
-- constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 34+1;
-- constant H_LEFT_BORDER : integer := H_BACK_PORCH + 61+1;--+3; -- adjust for hblank de-assert @sys_count=6
-- constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER -16;
-- constant H_VIDEO : integer := H_LEFT_BORDER + 256;
-- -- constant H_RIGHT_BORDER : integer := H_VIDEO + 61+1;---3; -- "
-- constant H_RIGHT_BORDER : integer := H_VIDEO + 54;---3; -- tweak to get to 60hz exactly
-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
-- 12.5714 MHz = 32 * 11 / 28
constant H_FRONT_PORCH : integer := 8;
constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48;
constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24;
constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6
constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16;
constant H_VIDEO : integer := H_LEFT_BORDER + 256;
constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- "
constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
constant V2_FRONT_PORCH : integer := 2;
constant V2_VERTICAL_SYNC : integer := V2_FRONT_PORCH + 2;
constant V2_BACK_PORCH : integer := V2_VERTICAL_SYNC + 12;
constant V2_TOP_BORDER : integer := V2_BACK_PORCH + 27; -- + 25; -- +25 for PAL
constant V2_VIDEO : integer := V2_TOP_BORDER + 192;
constant V2_BOTTOM_BORDER : integer := V2_VIDEO + 27; -- + 25; -- +25 for PAL
constant V2_TOTAL_PER_FIELD : integer := V2_BOTTOM_BORDER;
-- internal version of control ports
signal an_g_s : std_logic;
signal an_s_s : std_logic;
signal intn_ext_s : std_logic;
signal gm_s : std_logic_vector(2 downto 0);
signal css_s : std_logic;
signal inv_s : std_logic;
-- VGA signals
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
signal vga_hblank : std_logic;
signal vga_vblank : std_logic;
signal vga_linebuf_addr : std_logic_vector(8 downto 0);
signal vga_char_d_o : std_logic_vector(7 downto 0);
signal vga_hborder : std_logic;
signal vga_vborder : std_logic;
-- CVBS signals
signal cvbs_clk_ena : std_logic; -- PAL/NTSC*2
signal cvbs_hsync : std_logic;
signal cvbs_vsync : std_logic;
signal cvbs_hblank : std_logic;
signal cvbs_vblank : std_logic;
signal cvbs_hborder : std_logic;
signal cvbs_vborder : std_logic;
signal cvbs_linebuf_we : std_logic;
signal cvbs_linebuf_addr : std_logic_vector(8 downto 0);
signal active_h_start : std_logic := '0';
signal an_s_r : std_logic;
signal inv_r : std_logic;
signal intn_ext_r : std_logic;
signal dd_r : std_logic_vector(7 downto 0);
signal pixel_char_d_o : std_logic_vector(7 downto 0);
signal cvbs_char_d_o : std_logic_vector(7 downto 0); -- CVBS char_d_o out
alias hs_int : std_logic is cvbs_hblank;
alias fs_int : std_logic is cvbs_vblank;
signal da0_int : std_logic_vector(4 downto 0);
-- character rom signals
signal cvbs_linebuf_we_r : std_logic;
signal cvbs_linebuf_addr_r : std_logic_vector(8 downto 0);
signal cvbs_linebuf_we_rr : std_logic;
signal cvbs_linebuf_addr_rr : std_logic_vector(8 downto 0);
signal lookup : std_logic_vector(5 downto 0);
signal tripletaddr : std_logic_vector(7 downto 0);
signal tripletcnt : std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
type vram_type is array (511 downto 0) of std_logic_vector (7 downto 0);
signal VRAM : vram_type := (511 downto 0 => X"FF");
attribute RAM_STYLE : string;
attribute RAM_STYLE of VRAM : signal is "BLOCK";
------------------------------------------------------------------------
-- used by both CVBS and VGA
shared variable v_count : std_logic_vector(8 downto 0);
shared variable row_v : std_logic_vector(3 downto 0);
procedure map_palette (vga_char_d_o : in std_logic_vector(7 downto 0);
r : out std_logic_vector(7 downto 0);
g : out std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0)) is
type pal_entry_t is array (0 to 2) of std_logic_vector(1 downto 0);
type pal_a is array (0 to 7) of pal_entry_t;
constant pal : pal_a :=
(
0 => (0 => "00", 1 => "11", 2=>"00"), -- green
1 => (0 => "11", 1 => "11", 2=>"00"), -- yellow
2 => (0 => "00", 1 => "00", 2=>"11"), -- blue
3 => (0 => "11", 1 => "00", 2=>"00"), -- red
4 => (0 => "11", 1 => "11", 2=>"11"), -- white
5 => (0 => "00", 1 => "11", 2=>"11"), -- cyan
6 => (0 => "11", 1 => "00", 2=>"11"), -- magenta
7 => (0 => "11", 1 => "10", 2=>"00") -- orange
--others => (others => (others => '0'))
);
alias css_v : std_logic is vga_char_d_o(6);
alias an_g_v : std_logic is vga_char_d_o(5);
alias an_s_v : std_logic is vga_char_d_o(4);
alias luma : std_logic is vga_char_d_o(3);
alias chroma : std_logic_vector(2 downto 0) is vga_char_d_o(2 downto 0);
begin
if luma = '1' then
r := pal(to_integer(unsigned(chroma)))(0) & "000000";
g := pal(to_integer(unsigned(chroma)))(1) & "000000";
b := pal(to_integer(unsigned(chroma)))(2) & "000000";
else
-- not quite black in alpha mode
if black_backgnd = '0' and an_g_v = '0' and an_s_v = '0' then
-- dark green/orange
r := '0' & css_v & "000000";
g := "01000000";
else
r := (others => '0');
g := (others => '0');
end if;
b := (others => '0');
end if;
end procedure;
begin
-- assign control inputs for debug/release build
an_g_s <= DEBUG_AN_G when BUILD_DEBUG else an_g;
an_s_s <= DEBUG_AN_S when BUILD_DEBUG else an_s;
intn_ext_s <= DEBUG_INTN_EXT when BUILD_DEBUG else intn_ext;
gm_s <= DEBUG_GM when BUILD_DEBUG else gm;
css_s <= DEBUG_CSS when BUILD_DEBUG else css;
inv_s <= DEBUG_INV when BUILD_DEBUG else inv;
-- generate the clocks
PROC_CLOCKS : process (clk, reset)
variable toggle : std_logic := '0';
begin
if reset = '1' then
toggle := '0';
cvbs_clk_ena <= '0';
elsif rising_edge(clk) then
cvbs_clk_ena <= '0'; -- default
if clk_ena = '1' then
cvbs_clk_ena <= toggle;
toggle := not toggle;
end if;
end if;
end process PROC_CLOCKS;
-- generate horizontal timing for VGA
-- generate line buffer address for reading VGA char_d_o
PROC_VGA : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable vga_vblank_r : std_logic;
begin
if reset = '1' then
h_count := 0;
vga_hsync <= '1';
vga_vsync <= '1';
vga_hblank <= '0';
elsif rising_edge (clk) and clk_ena = '1' then
-- start hsync when cvbs comes out of vblank
if vga_vblank_r = '1' and vga_vblank = '0' then
h_count := 0;
else
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
vga_hborder <= '0';
else
h_count := h_count + 1;
end if;
if h_count = H_FRONT_PORCH then
vga_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
vga_hsync <= '1';
elsif h_count = H_BACK_PORCH then
vga_hborder <= '1';
elsif h_count = H_LEFT_BORDER+1 then
vga_hblank <= '0';
elsif h_count = H_VIDEO+1 then
vga_hblank <= '1';
elsif h_count = H_RIGHT_BORDER then
vga_hborder <= '0';
end if;
if h_count = H_LEFT_BORDER then
active_h_count := (others => '1');
else
active_h_count := std_logic_vector(unsigned(active_h_count) + 1);
end if;
end if;
-- vertical syncs, blanks are the same
vga_vsync <= cvbs_vsync;
-- generate linebuffer address
-- - alternate every 2nd line
vga_linebuf_addr <= (not v_count(0)) & active_h_count;
vga_vblank_r := vga_vblank;
end if;
end process;
-- generate horizontal timing for CVBS
-- generate line buffer address for writing CVBS char_d_o
PROC_CVBS : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable cvbs_hblank_r : std_logic := '0';
--variable row_v : std_logic_vector(3 downto 0);
-- for debug only
variable active_v_count : std_logic_vector(v_count'range);
begin
if reset = '1' then
h_count := H_TOTAL_PER_LINE;
v_count := std_logic_vector(to_unsigned(V2_TOTAL_PER_FIELD, v_count'length));
active_h_count := (others => '0');
active_h_start <= '0';
cvbs_hsync <= '1';
cvbs_vsync <= '1';
cvbs_hblank <= '0';
cvbs_vblank <= '1';
vga_vblank <= '1';
da0_int <= (others => '0');
cvbs_hblank_r := '0';
row_v := (others => '0');
elsif rising_edge (clk) and cvbs_clk_ena = '1' then
active_h_start <= '0';
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
if v_count = V2_TOTAL_PER_FIELD then
v_count := (others => '0');
else
v_count := v_count + 1;
end if;
-- VGA vblank is 1 line behind CVBS
-- - because we need to fill the line buffer
vga_vblank <= cvbs_vblank;
if v_count = V2_FRONT_PORCH then
cvbs_vsync <= '0';
elsif v_count = V2_VERTICAL_SYNC then
cvbs_vsync <= '1';
elsif v_count = V2_BACK_PORCH then
cvbs_vborder <= '1';
elsif v_count = V2_TOP_BORDER then
cvbs_vblank <= '0';
row_v := (others => '0');
active_v_count := (others => '0');
tripletaddr <= (others => '0');
tripletcnt <= (others => '0');
elsif v_count = V2_VIDEO then
cvbs_vblank <= '1';
elsif v_count = V2_BOTTOM_BORDER then
cvbs_vborder <= '0';
else
if row_v = 11 then
row_v := (others => '0');
if an_g_s = '0' then
active_v_count := active_v_count + 5; -- step for alphas
else
active_v_count := active_v_count + 1; -- mode 4,4a
end if;
else
row_v := row_v + 1;
active_v_count := active_v_count + 1;
end if;
if tripletcnt = 2 then -- mode 1,1a,2a
tripletcnt <= (others => '0');
tripletaddr <= tripletaddr + 1;
else
tripletcnt <= tripletcnt + 1;
end if;
end if;
else
h_count := h_count + 1;
if h_count = H_FRONT_PORCH then
cvbs_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
cvbs_hsync <= '1';
elsif h_count = H_BACK_PORCH then
elsif h_count = H_LEFT_RSTADDR then
active_h_count := (others => '0');
elsif h_count = H_LEFT_BORDER then
cvbs_hblank <= '0';
active_h_start <= '1';
elsif h_count = H_VIDEO then
cvbs_hblank <= '1';
active_h_count := active_h_count + 1;
elsif h_count = H_RIGHT_BORDER then
null;
else
active_h_count := active_h_count + 1;
end if;
end if;
-- generate character rom address
char_a <= dd(6 downto 0) & row_v(3 downto 0);
-- DA0 high during FS
if cvbs_vblank = '1' then
da0_int <= (others => '1');
elsif cvbs_hblank = '1' then
da0_int <= (others => '0');
elsif cvbs_hblank_r = '1' and cvbs_hblank = '0' then
da0_int <= "01000";
else
da0_int <= da0_int + 1;
end if;
cvbs_linebuf_addr <= v_count(0) & active_h_count;
-- pipeline writes to linebuf because char_d_o is delayed 1 clock as well!
cvbs_linebuf_we_r <= cvbs_linebuf_we;
cvbs_linebuf_addr_r <= cvbs_linebuf_addr;
cvbs_linebuf_we_rr <= cvbs_linebuf_we_r;
cvbs_linebuf_addr_rr <= cvbs_linebuf_addr_r;
cvbs_hblank_r := cvbs_hblank;
if an_g_s = '0' then
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= "000" & active_v_count(8 downto 4) & lookup(4 downto 0);
else
case gm is --lookupaddr
when "000" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" & tripletaddr(7 downto 0) & lookup(3 downto 0);
when "001" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" & tripletaddr(7 downto 0) & lookup(3 downto 0);
when "010" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= tripletaddr(7 downto 0) & lookup(4 downto 0);
when "011" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "00" &active_v_count(7 downto 1) & lookup(3 downto 0);
when "100" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= "0" & active_v_count(7 downto 1) & lookup(4 downto 0);
when "101" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" &active_v_count(7 downto 0) & lookup(3 downto 0);
when "110" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= active_v_count(7 downto 0) & lookup(4 downto 0);
when "111" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= active_v_count(7 downto 0) & lookup(4 downto 0);
when others =>
null;
end case;
end if;
end if; -- cvbs_clk_ena
end process;
-- handle latching & shifting of character, graphics char_d_o
process (clk, reset)
variable count : std_logic_vector(3 downto 0) := (others => '0');
begin
if reset = '1' then
count := (others => '0');
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
if active_h_start = '1' then
count := (others => '0');
end if;
if an_g_s = '0' then
-- alpha-semi modes
if count(2 downto 0) = 0 then
-- handle alpha-semi latching
an_s_r <= an_s_s;
inv_r <= inv_s;
intn_ext_r <= intn_ext_s;
if an_s_s = '0' then
dd_r <= char_d_o; -- alpha mode
else
-- store luma,chroma(2..0),luma,chroma(2..0)
if intn_ext_s = '0' then -- semi-4
if row_v < 6 then
dd_r <= dd(3) & dd(6) & dd(5) & dd(4) &
dd(2) & dd(6) & dd(5) & dd(4);
else
dd_r <= dd(1) & dd(6) & dd(5) & dd(4) &
dd(0) & dd(6) & dd(5) & dd(4);
end if;
else -- semi-6
if row_v < 4 then
dd_r <= dd(5) & css_s & dd(7) & dd(6) &
dd(4) & css_s & dd(7) & dd(6);
elsif row_v < 8 then
dd_r <= dd(3) & css_s & dd(7) & dd(6) &
dd(2) & css_s & dd(7) & dd(6);
else
dd_r <= dd(1) & css_s & dd(7) & dd(6) &
dd(0) & css_s & dd(7) & dd(6);
end if;
end if;
end if;
else
-- handle alpha-semi shifting
if an_s_r = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- alpha mode
else
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-4 downto 0) & "0000"; -- semi mode
end if;
end if;
end if;
else
-- graphics modes
--if IN_SIMULATION then
an_s_r <= '0';
--end if;
case gm_s is
when "000" | "001" | "011" | "101" => -- CG1/RG1/RG2/RG3
if count(3 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "000" then
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG1
end if;
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG1/RG2/RG3
end if;
end if;
end if;
when others => -- CG2/CG3/CG6/RG6
if count(2 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "111" then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG6
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG2/CG3/CG6
end if;
end if;
end if;
end case;
end if;
count := count + 1;
end if;
end process;
-- generate pixel char_d_o
process (clk, reset)
variable luma : std_logic;
variable chroma : std_logic_vector(2 downto 0);
begin
if reset = '1' then
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
-- alpha/graphics mode
if an_g_s = '0' then
-- alphanumeric & semi-graphics mode
luma := dd_r(dd_r'left);
if an_s_r = '0' then
-- alphanumeric
if intn_ext_r = '0' then
-- internal rom
chroma := (others => css_s);
if inv_r = '1' then
luma := not luma;
end if; -- normal/inverse
else
-- external ROM?!?
end if; -- internal/external
else
chroma := dd_r(dd_r'left-1 downto dd_r'left-3);
end if; -- alphanumeric/semi-graphics
else
-- graphics mode
case gm_s is
when "000" => -- CG1 64x64x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when "001" | "011" | "101" => -- RG1/2/3 128x64/96/192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
when "010" | "100" | "110" => -- CG2/3/6 128x64/96/192x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when others => -- RG6 256x192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
end case;
end if; -- alpha/graphics mode
-- pack source char_d_o into line buffer
-- - palette lookup on output
pixel_char_d_o <= '0' & css_s & an_g_s & an_s_r & luma & chroma;
end if;
end process;
-- only write to the linebuffer during active display
cvbs_linebuf_we <= not (cvbs_vblank or cvbs_hblank);
cvbs <= '0' & cvbs_vsync & "000000" when cvbs_vblank = '1' else
'0' & cvbs_hsync & "000000" when cvbs_hblank = '1' else
cvbs_char_d_o;
-- assign outputs
hs_n <= not hs_int;
fs_n <= not fs_int;
da0 <= da0_int(4) when (gm_s = "001" or gm_s = "011" or gm_s = "101") else
da0_int(3);
-- map the palette to the pixel char_d_o
-- - we do that at the output so we can use a
-- higher colour-resolution palette
-- without using memory in the line buffer
PROC_OUTPUT : process (clk)
variable r : std_logic_vector(red'range);
variable g : std_logic_vector(green'range);
variable b : std_logic_vector(blue'range);
-- for artifacting testing only
variable p_in : std_logic_vector(vga_char_d_o'range);
variable p_out : std_logic_vector(vga_char_d_o'range);
variable count : std_logic := '0';
begin
if reset = '1' then
count := '0';
elsif rising_edge(clk) then
if CVBS_NOT_VGA then
if cvbs_clk_ena = '1' then
if cvbs_hblank = '0' and cvbs_vblank = '0' then
map_palette (vga_char_d_o, r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
else
if clk_ena = '1' then
if vga_hblank = '1' then
count := '0';
p_in := (others => '0');
end if;
if vga_hblank = '0' and vga_vblank = '0' then
-- artifacting test only --
if artifact_en = '1' and an_g_s = '1' and gm_s = "111" then
if count /= '0' then
p_out(p_out'left downto 4) := vga_char_d_o(p_out'left downto 4);
if p_in(3) = '0' and vga_char_d_o(3) = '0' then
p_out(3 downto 0) := "0000";
elsif p_in(3) = '1' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1100";
elsif p_in(3) = '0' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1011"; -- red
--p_out(3 downto 0) := "1101"; -- cyan
else
p_out(3 downto 0) := "1010"; -- blue
--p_out(3 downto 0) := "1111"; -- orange
end if;
end if;
map_palette (p_out, r, g, b);
p_in := vga_char_d_o;
else
map_palette (vga_char_d_o, r, g, b);
end if;
count := not count;
elsif an_g_s = '1' and vga_hborder = '1' and cvbs_vborder = '1' then
-- graphics mode, either green or buff (white)
map_palette ("00001" & css_s & "00", r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
end if; -- CVBS_NOT_VGA
red <= r; green <= g; blue <= b;
end if; -- rising_edge(clk)
if CVBS_NOT_VGA then
hsync <= cvbs_hsync;
vsync <= cvbs_vsync;
hblank <= cvbs_hblank;
vblank <= cvbs_vblank;
else
hsync <= vga_hsync;
vsync <= vga_vsync;
hblank <= not vga_hborder;
vblank <= not cvbs_vborder;
end if;
end process PROC_OUTPUT;
-- line buffer for scan doubler gives us vga monitor compatible output
process (clk)
begin
if rising_edge(clk) then
if cvbs_clk_ena = '1' then
if (cvbs_linebuf_we_rr = '1') then
VRAM(conv_integer(cvbs_linebuf_addr_rr(8 downto 0))) <= pixel_char_d_o;
end if;
end if;
if clk_ena = '1' then
vga_char_d_o <= VRAM(conv_integer(vga_linebuf_addr(8 downto 0)));
end if;
end if;
end process;
---- rom for char generator
-- charrom_inst : entity work.mc6847t1_ntsc_plus_keith
-- port map(
-- CLK => clk,
-- ADDR => char_a,
-- DATA => char_d_o
-- );
end SYN;
| apache-2.0 |
wsoltys/AtomFpga | src/AtomGodilVideo/src/pointer/PointerRamBlack.vhd | 2 | 6555 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PointerRamBlack is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(7 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end PointerRamBlack;
architecture BEHAVIORAL of PointerRamBlack is
-- Shared memory
type ram_type is array (0 to 255) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type := (
"11111111",
"10000010",
"10000100",
"10000100",
"10000010",
"10110001",
"11001010",
"10000100",
"11100000",
"10100000",
"11100000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00111100",
"01010010",
"10010001",
"10010001",
"10011101",
"10000001",
"01000010",
"00111100",
"11111111",
"10000001",
"10111111",
"10100000",
"10100000",
"10100000",
"10100000",
"11100000",
"00010000",
"00101000",
"01000100",
"11000110",
"01000100",
"01000100",
"01000100",
"01111100",
"01111100",
"01000100",
"01000100",
"01000100",
"11000110",
"01000100",
"00101000",
"00010000",
"00001000",
"11111100",
"10000010",
"10000001",
"10000010",
"11111100",
"00001000",
"00000000",
"00010000",
"00111111",
"01000001",
"10000001",
"01000001",
"00111111",
"00010000",
"00000000",
"00111100",
"01000110",
"10001101",
"10001101",
"10011001",
"10011001",
"01110010",
"00111100",
"00111000",
"01000100",
"01010100",
"01110100",
"00101000",
"00111000",
"00101000",
"00111000",
"01111100",
"01000100",
"01101100",
"00101000",
"00101000",
"01101100",
"01000100",
"01111100",
"00111000",
"00101000",
"11101110",
"10000010",
"11101110",
"00101000",
"00111000",
"00000000",
"01000000",
"10100000",
"10100000",
"10111110",
"10101011",
"10000001",
"11111111",
"01111110",
"01111110",
"11111111",
"10000001",
"10101011",
"10111110",
"10100000",
"10100000",
"01000000",
"01111110",
"11000001",
"11011110",
"11001000",
"11011000",
"11001000",
"11011000",
"01110000",
"01111110",
"10000011",
"01111011",
"00010011",
"00011011",
"00010011",
"00011011",
"00001110",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01000010",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01011010",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01111110",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00111100",
"01111110",
"11111111",
"11100000",
"10011000",
"01000110",
"00110001",
"01101011",
"01010101",
"00101001",
"00011110",
"00000111",
"00011001",
"01100010",
"10001100",
"11010110",
"10101010",
"10010100",
"01111000",
"00011110",
"00101001",
"01010101",
"01101011",
"00110001",
"01000110",
"10011000",
"11100000",
"01111000",
"10010100",
"10101010",
"11010110",
"10001100",
"01100010",
"00011001",
"00000111",
"01100110",
"10011001",
"10011001",
"11011101",
"11011101",
"10011001",
"10011001",
"01100110",
"01100110",
"11111111",
"11111111",
"10011001",
"10011001",
"10011001",
"10011001",
"01100110",
"01100110",
"10011001",
"10011001",
"10111011",
"10111011",
"10011001",
"10011001",
"01100110",
"01100110",
"10011001",
"10011001",
"10011001",
"10011001",
"11111111",
"11111111",
"01100110",
"11111111",
"10000010",
"10000100",
"10001000",
"10010000",
"10100000",
"11000000",
"10000000",
"10000000",
"11000000",
"10100000",
"10010000",
"10001000",
"10000100",
"10000010",
"11111111",
"00000001",
"00000011",
"00000101",
"00001001",
"00010001",
"00100001",
"01000001",
"11111111",
"11111111",
"01000001",
"00100001",
"00010001",
"00001001",
"00000101",
"00000011",
"00000001"
);
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(7 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(7 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(7 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(7 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 |
fafaldo/ethernet | ethernet4b/new_tx_fifo_control_unit.vhd | 1 | 10922 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity new_tx_fifo_control_unit is
port (
clkA : out std_logic;
clkB : out std_logic;
enA : out std_logic;
enB : out std_logic;
--weA : out std_logic := '1';
weB : out std_logic;
addrA : out std_logic_vector(11 downto 0);
addrB : out std_logic_vector(10 downto 0);
--diA : out std_logic_vector(3 downto 0);
diB : out std_logic_vector(7 downto 0);
doA : in std_logic_vector(3 downto 0);
--doB : in std_logic_vector(7 downto 0);
empty : out std_logic;
full : out std_logic;
data_in : in std_logic_vector(7 downto 0);
EOF : in std_logic;
clk : in std_logic;
Tx_Clk : in std_logic;
Tx_En : out std_logic;
Tx_D : out std_logic_vector(3 downto 0);
PUSH : in std_logic;
busy : out std_logic := '0';
start : in std_logic;
test : out std_logic_vector(7 downto 0)
);
end new_tx_fifo_control_unit;
architecture behavioral of new_tx_fifo_control_unit is
type state_type is (IDLE, TRANSMITTING, IDLE_GAP);
signal state, next_state : state_type;
signal write_address_counter : std_logic_vector(10 downto 0) := "00001101100";
signal read_address_counter : std_logic_vector(11 downto 0) := (others=>'0');
signal empty_i : std_logic := '0';
signal full_i : std_logic := '0';
signal write_add_simple : std_logic := '1';
signal write_add_temp : std_logic_vector(10 downto 0) := (others=>'0');
signal read_add_simple : std_logic := '1';
signal read_add_temp : std_logic_vector(11 downto 0) := (others=>'0');
signal read_address_counter_minus_two : std_logic_vector(11 downto 0) := "100000000001";
signal read_address_counter_minus_two_temp : std_logic_vector(11 downto 0) := (others=>'0');
signal Tx_En_i : std_logic := '0';
signal gap_counter : std_logic_vector(7 downto 0) := (others=>'0');
signal reset : std_logic := '0';
signal state_transmitting_reached : std_logic := '0';
signal cycles_in_transmitting_state : std_logic_vector(7 downto 0) := (others=>'0');
begin
-- test <= state_transmitting_reached & full_i & empty_i & "00000";
test <= "0000" & read_address_counter(3 downto 0);
--
-- PRZYPISANIA WYJÆ DO FRAME BUFFER'A
--
addrA <= read_address_counter;
addrB <= write_address_counter;
clkA <= Tx_Clk; --??????
clkB <= clk;
enB <= PUSH;
enA <= '1';
diB <= data_in;
Tx_D <= doA;
process (clk)
begin
if rising_edge(clk) then
if state = TRANSMITTING then
state_transmitting_reached <= '1';
end if;
end if;
end process;
-- process (Tx_Clk)
-- begin
-- if rising_edge(Tx_Clk) then
-- if state = TRANSMITTING then
-- cycles_in_transmitting_state <= cycles_in_transmitting_state+1;
-- end if;
-- end if;
-- end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
process (state)
begin
next_state <= state;
case (state) is
when IDLE =>
if start = '1' then
next_state <= TRANSMITTING;
end if;
when TRANSMITTING =>
if empty_i = '1' then
next_state <= IDLE_GAP;
end if;
when IDLE_GAP =>
if(gap_counter > 128) then
next_state <= IDLE;
end if;
when others =>
next_state <= IDLE;
end case;
end process;
process (clk)
begin
if state = IDLE then
busy <= '0';
else
busy <= '1';
end if;
end process;
process (clk)
begin
if state = TRANSMITTING then
Tx_En <= '1';
Tx_En_i <= '1';
else
Tx_En <= '0';
Tx_En_i <= '0';
end if;
end process;
process (Tx_Clk)
begin
if state = IDLE_GAP then
gap_counter <= gap_counter+1;
else
gap_counter <= (others=>'0');
end if;
end process;
--
-- USTAWIANIE WRITE ENABLE A
--
-- tutaj nastêpuje w³aciwe zabezpieczenie przed nadpisaniem starych danych w kolejce
--
process (clk)
begin
if rising_edge(clk) then
if (write_address_counter = 0 and read_address_counter(11 downto 1) = 0) or write_address_counter /= read_address_counter_minus_two(11 downto 1) then
weB <= '1';
-- wea_i <= '1';
else
weB <= '0';
-- wea_i <= '0';
end if;
end if;
end process;
--
-- USTAWIANIE FLAG EMPTY I FULL
--
process (clk)
begin
if rising_edge(clk) then
if write_address_counter = read_address_counter_minus_two(11 downto 1) then
full <= '1';
full_i <= '1';
else
full <= '0';
full_i <= '0';
end if;
end if;
end process;
process (Tx_Clk)
begin
if rising_edge(Tx_Clk) then
if read_address_counter(11 downto 1) = write_address_counter then
empty <= '1';
empty_i <= '1';
else
empty <= '0';
empty_i <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if PUSH = '1' and state = IDLE then
if (write_address_counter = 0 and read_address_counter(11 downto 1) = 0) or write_address_counter /= read_address_counter_minus_two(11 downto 1) then
write_add_simple <= not write_add_simple;
end if;
end if;
end if;
end process;
write_add_temp <= "10000000000" when (write_address_counter(9) = '1' and write_address_counter(8 downto 0) = "000000000") or (write_address_counter = "10000000000") else
"01000000000" when write_address_counter(8) = '1' and write_address_counter(7 downto 0) = "00000000" else
"00100000000" when write_address_counter(7) = '1' and write_address_counter(6 downto 0) = "0000000" else
"00010000000" when write_address_counter(6) = '1' and write_address_counter(5 downto 0) = "000000" else
"00001000000" when write_address_counter(5) = '1' and write_address_counter(4 downto 0) = "00000" else
"00000100000" when write_address_counter(4) = '1' and write_address_counter(3 downto 0) = "0000" else
"00000010000" when write_address_counter(3) = '1' and write_address_counter(2 downto 0) = "000" else
"00000001000" when write_address_counter(2) = '1' and write_address_counter(1 downto 0) = "00" else
"00000000100" when write_address_counter(1) = '1' and write_address_counter(0 downto 0) = "0" else
"00000000010" when write_address_counter(0) = '1' else
"00000000000";
process(clk)
begin
if rising_edge(clk) then
if PUSH = '1' and state = IDLE then
if (write_address_counter = 0 and read_address_counter(11 downto 1) = 0) or write_address_counter /= read_address_counter_minus_two(11 downto 1) then
if write_add_simple = '1' then
write_address_counter <= write_address_counter xor "00000000001";
else
write_address_counter <= write_address_counter xor write_add_temp;
end if;
end if;
end if;
end if;
end process;
process (Tx_Clk)
begin
if rising_edge(Tx_Clk) then
if (state = TRANSMITTING) then
if read_address_counter(11 downto 1) /= write_address_counter then
read_add_simple <= not read_add_simple;
end if;
end if;
end if;
end process;
read_add_temp <= "100000000000" when (read_address_counter(10) = '1' and read_address_counter(9 downto 0) = "0000000000") or (read_address_counter = "100000000000") else
"010000000000" when read_address_counter(9) = '1' and read_address_counter(8 downto 0) = "000000000" else
"001000000000" when read_address_counter(8) = '1' and read_address_counter(7 downto 0) = "00000000" else
"000100000000" when read_address_counter(7) = '1' and read_address_counter(6 downto 0) = "0000000" else
"000010000000" when read_address_counter(6) = '1' and read_address_counter(5 downto 0) = "000000" else
"000001000000" when read_address_counter(5) = '1' and read_address_counter(4 downto 0) = "00000" else
"000000100000" when read_address_counter(4) = '1' and read_address_counter(3 downto 0) = "0000" else
"000000010000" when read_address_counter(3) = '1' and read_address_counter(2 downto 0) = "000" else
"000000001000" when read_address_counter(2) = '1' and read_address_counter(1 downto 0) = "00" else
"000000000100" when read_address_counter(1) = '1' and read_address_counter(0 downto 0) = "0" else
"000000000010" when read_address_counter(0) = '1' else
"000000000000";
process(Tx_Clk)
begin
if rising_edge(Tx_Clk) then
if (Tx_En_i = '1') then
if read_address_counter(11 downto 1) /= write_address_counter then
cycles_in_transmitting_state <= cycles_in_transmitting_state+1;
if read_add_simple = '1' then
read_address_counter <= read_address_counter xor "000000000001";
else
read_address_counter <= read_address_counter xor read_add_temp;
end if;
end if;
end if;
end if;
end process;
read_address_counter_minus_two_temp <= "100000000000" when (read_address_counter_minus_two(10) = '1' and read_address_counter_minus_two(9 downto 0) = "0000000000") or (read_address_counter_minus_two = "100000000000") else
"010000000000" when read_address_counter_minus_two(9) = '1' and read_address_counter_minus_two(8 downto 0) = "000000000" else
"001000000000" when read_address_counter_minus_two(8) = '1' and read_address_counter_minus_two(7 downto 0) = "00000000" else
"000100000000" when read_address_counter_minus_two(7) = '1' and read_address_counter_minus_two(6 downto 0) = "0000000" else
"000010000000" when read_address_counter_minus_two(6) = '1' and read_address_counter_minus_two(5 downto 0) = "000000" else
"000001000000" when read_address_counter_minus_two(5) = '1' and read_address_counter_minus_two(4 downto 0) = "00000" else
"000000100000" when read_address_counter_minus_two(4) = '1' and read_address_counter_minus_two(3 downto 0) = "0000" else
"000000010000" when read_address_counter_minus_two(3) = '1' and read_address_counter_minus_two(2 downto 0) = "000" else
"000000001000" when read_address_counter_minus_two(2) = '1' and read_address_counter_minus_two(1 downto 0) = "00" else
"000000000100" when read_address_counter_minus_two(1) = '1' and read_address_counter_minus_two(0 downto 0) = "0" else
"000000000010" when read_address_counter_minus_two(0) = '1' else
"000000000000";
process(Tx_Clk)
begin
if rising_edge(Tx_Clk) then
if (state = TRANSMITTING) then
if read_address_counter(11 downto 1) /= write_address_counter then
if read_add_simple = '1' then
read_address_counter_minus_two <= read_address_counter_minus_two xor "000000000001";
else
read_address_counter_minus_two <= read_address_counter_minus_two xor read_address_counter_minus_two_temp;
end if;
end if;
end if;
end if;
end process;
end behavioral; | apache-2.0 |
fafaldo/ethernet | ethernet4b/calosc_test.vhd | 1 | 2799 | -- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\CU_test1.sch - Sat Aug 30 21:03:36 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY CU_test1_CU_test1_sch_tb IS
END CU_test1_CU_test1_sch_tb;
ARCHITECTURE behavioral OF CU_test1_CU_test1_sch_tb IS
COMPONENT CU_test1
PORT( clk : IN STD_LOGIC;
E_RX_D : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (others=>'0');
E_RX_CLK : IN STD_LOGIC;
E_RX_DV : IN STD_LOGIC;
full : OUT STD_LOGIC;
test : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
REST : IN STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL E_RX_D : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others=>'0');
SIGNAL E_RX_CLK : STD_LOGIC;
SIGNAL E_RX_DV : STD_LOGIC;
SIGNAL full : STD_LOGIC;
SIGNAL test : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL REST : STD_LOGIC;
BEGIN
UUT: CU_test1 PORT MAP(
clk => clk,
E_RX_D => E_RX_D,
E_RX_CLK => E_RX_CLK,
E_RX_DV => E_RX_DV,
full => full,
test => test,
REST => REST
);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process
begin
E_RX_CLK <= '0';
wait for 10 ns;
E_RX_CLK <= '1';
wait for 10 ns;
end process;
E_RX_DV <= '0', '1' after 50 ns, '0' after 650 ns;
E_RX_D <= x"0",
x"1" after 50 ns,
x"2" after 70 ns,
x"3" after 90 ns,
x"4" after 110 ns,
x"5" after 130 ns,
x"6" after 150 ns,
x"7" after 170 ns,
x"8" after 190 ns,
x"9" after 210 ns,
x"a" after 230 ns,
x"b" after 250 ns,
x"c" after 270 ns,
x"d" after 290 ns,
x"e" after 310 ns,
x"f" after 330 ns,
x"0" after 350 ns,
x"1" after 370 ns,
x"2" after 390 ns,
x"3" after 410 ns,
x"4" after 430 ns,
x"5" after 450 ns,
x"6" after 470 ns,
x"7" after 490 ns,
x"8" after 510 ns,
x"9" after 530 ns,
x"a" after 550 ns,
x"b" after 570 ns,
x"c" after 590 ns,
x"d" after 610 ns,
x"e" after 630 ns;
END;
| apache-2.0 |
fafaldo/ethernet | ethernet4b/test_icmp.vhd | 1 | 2069 | -- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\CU_test1.sch - Mon Aug 25 21:09:23 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY CU_test1_CU_test1_sch_tb IS
END CU_test1_CU_test1_sch_tb;
ARCHITECTURE behavioral OF CU_test1_CU_test1_sch_tb IS
COMPONENT CU_test1
PORT( clk : IN STD_LOGIC;
E_RX_D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
E_RX_CLK : IN STD_LOGIC;
E_RX_DV : IN STD_LOGIC;
full : OUT STD_LOGIC;
test : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL E_RX_D : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others=>'0');
SIGNAL E_RX_CLK : STD_LOGIC := '0';
SIGNAL E_RX_DV : STD_LOGIC := '0';
SIGNAL full : STD_LOGIC;
SIGNAL test : STD_LOGIC;
BEGIN
UUT: CU_test1 PORT MAP(
clk => clk,
E_RX_D => E_RX_D,
E_RX_CLK => E_RX_CLK,
E_RX_DV => E_RX_DV,
full => full,
test => test
);
process (clk)
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process (E_RX_CLK)
begin
E_RX_CLK <= '0';
wait for 200 ns;
E_RX_CLK <= '1';
wait for 200 ns;
end process;
E_RX_D <= "0000", "0101" after 200 ns, "1101" after 600 ns, "0011" after 1000 ns, "0011" after 1400 ns;
E_RX_DV <= '0', '1' after 200 ns, '0' after 1800 ns;
END;
| apache-2.0 |
fafaldo/ethernet | ethernet4b/display_test.vhd | 1 | 3300 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:54 03/23/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/display_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: header_display
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY display_test IS
END display_test;
ARCHITECTURE behavior OF display_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT header_display
PORT(
char : OUT std_logic_vector(7 downto 0);
char_we : OUT std_logic;
tx_busy : IN std_logic;
busy : IN std_logic;
clk : IN std_logic;
ram_clk : OUT std_logic;
ram_enable : OUT std_logic;
ram_address : OUT std_logic_vector(11 downto 0);
ram_output : IN std_logic_vector(7 downto 0);
start : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal tx_busy : std_logic := '0';
signal busy : std_logic := '0';
signal clk : std_logic := '0';
signal ram_output : std_logic_vector(7 downto 0) := (others => '0');
signal start : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal char : std_logic_vector(7 downto 0);
signal char_we : std_logic;
signal ram_clk : std_logic;
signal ram_enable : std_logic;
signal ram_address : std_logic_vector(11 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant ram_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: header_display PORT MAP (
char => char,
char_we => char_we,
tx_busy => tx_busy,
busy => busy,
clk => clk,
ram_clk => ram_clk,
ram_enable => ram_enable,
ram_address => ram_address,
ram_output => ram_output,
start => start,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ram_clk_process :process
begin
ram_clk <= '0';
wait for ram_clk_period/2;
ram_clk <= '1';
wait for ram_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| apache-2.0 |
fafaldo/ethernet | ethernet4b/header_display.vhd | 1 | 3147 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:21:45 03/21/2014
-- Design Name:
-- Module Name: header_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity header_display is
Port ( char : out STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
char_we : out STD_LOGIC := '0';
clk : in STD_LOGIC;
ram_clk : out STD_LOGIC := '0';
ram_enable : out STD_LOGIC := '1';
ram_output : in STD_LOGIC_VECTOR(3 downto 0);
start : in STD_LOGIC;
reset : in STD_LOGIC);
end header_display;
architecture Behavioral of header_display is
type state_type is (IDLE, GET_DATA, START_RISING_EDGE, START_FALLING_EDGE);
signal state, next_state : state_type;
signal busy_in : STD_LOGIC := '0';
begin
process (clk)
begin
if rising_edge(clk) then
if reset='1' then
busy_in <= '0';
elsif start = '1' then
busy_in <= '1';
elsif state = IDLE then
busy_in <= '0';
else
busy_in <= busy_in;
end if;
end if;
end process;
SYNC_PROC: process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
OUTPUT_DECODE: process (state, ram_output)
begin
if state = IDLE then
char <= (others=>'0');
char_we <= '0';
ram_clk <= '0';
ram_enable <= '0';
elsif state = GET_DATA then
char <= (others=>'0');
char_we <= '0';
ram_enable <= '1';
ram_clk <= '1'; -- zobaczymy czy zadzia³a, mo¿e byæ za póno
elsif state = START_RISING_EDGE then
ram_clk <= '0';
ram_enable <= '0';
char_we <= '1';
char <= "0000" & ram_output; -- mo¿na? zrobiæ co do przerabiania na ASCII
elsif state = START_FALLING_EDGE then
ram_clk <= '0';
ram_enable <= '0';
char_we <= '0';
char <= "0000" & ram_output;
end if;
end process;
NEXT_STATE_DECODE: process (state, start, clk)
begin
next_state <= state;
case (state) is
when IDLE =>
if start = '1' then
next_state <= GET_DATA;
end if;
when GET_DATA =>
next_state <= START_RISING_EDGE;
when START_RISING_EDGE =>
next_state <= START_FALLING_EDGE;
when START_FALLING_EDGE =>
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
| apache-2.0 |
fafaldo/ethernet | ethernet4b/test.vhd | 1 | 1021 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:58:30 03/10/2014
-- Design Name:
-- Module Name: test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
Port ( MDC : out STD_LOGIC;
MDIO : inout STD_LOGIC;
clk : in STD_LOGIC;
btn : in STD_LOGIC);
end test;
architecture Behavioral of test is
begin
end Behavioral;
| apache-2.0 |
nixdog/helloworld | vhdl.vhdl | 2 | 273 | entity hello_world is
end ;
architecture hello_world of hello_world is
begin
stimulus : PROCESS
begin
assert false report "Hello, world!"
severity note ;
wait ;
end PROCESS stimulus ;
end hello_world ;
| apache-2.0 |
Paebbels/pauloBlaze | sources/pauloBlaze.vhd | 2 | 8794 | -- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pauloBlaze is
generic (
debug : boolean := false;
hwbuild : unsigned(7 downto 0) := X"00";
interrupt_vector : unsigned(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64;
stack_depth : positive := 30
);
port (
-- control
clk : in std_logic;
reset : in std_logic;
sleep : in std_logic;
-- instruction memory
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
-- i/o ports
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
-- interrupts
interrupt : in std_logic;
interrupt_ack : out std_logic
);
end pauloBlaze;
architecture Behavioral of pauloBlaze is
signal clk2 : std_logic := '1'; -- high during 2nd clk cycle
-- used for converting from slv to my internal unsigned
signal address_u : unsigned(11 downto 0);
signal instruction_u : unsigned(17 downto 0);
signal in_port_u : unsigned(7 downto 0);
signal out_port_u : unsigned(7 downto 0);
signal port_id_u : unsigned(7 downto 0);
-- signals alu in
signal opcode : unsigned(5 downto 0);
signal opA : unsigned(3 downto 0);
signal opB : unsigned(7 downto 0);
-- signals alu out
signal carry : STD_LOGIC;
signal zero : STD_LOGIC;
-- signals pc in
signal rst_req : STD_LOGIC;
signal ret : STD_LOGIC;
signal call : STD_LOGIC;
signal jump : STD_LOGIC;
signal jmp_addr : unsigned (11 downto 0);
-- signals decoder
signal reset_int : std_logic;
signal reset_bram_en : std_logic;
signal io_op_in : std_logic;
signal io_op_out : std_logic;
signal io_op_out_pp : std_logic;
signal io_kk_en : std_logic;
signal io_kk_port : unsigned (3 downto 0);
signal io_kk_data : unsigned (7 downto 0);
signal spm_addr_ss : unsigned (7 downto 0);
signal spm_ss : std_logic;
signal spm_we : std_logic;
signal spm_rd : std_logic;
signal inter_j : std_logic;
signal sleep_int : std_logic;
signal bram_pause : std_logic;
signal clk2_reset : std_logic;
signal preserve_flags : std_logic;
signal restore_flags : std_logic;
-- general register file signals
signal reg_select : std_logic;
signal reg_star : std_logic;
signal reg_reg0 : unsigned (7 downto 0);
signal reg_reg1 : unsigned (7 downto 0);
signal reg_address : unsigned (7 downto 0);
signal reg_value : unsigned (7 downto 0);
signal reg_we : std_logic;
-- signals register file from alu
signal reg_value_a : unsigned (7 downto 0);
signal reg_we_a : std_logic;
-- signals register file from io
signal reg_value_io : unsigned (7 downto 0);
signal reg_we_io : std_logic;
begin
bram_enable <= clk2 and not bram_pause when reset_int = '0' else reset_bram_en;
-- in case of a reset there is a state where reset_bram_en will be high for one clk cycle, just before
-- the internal reset will be deasserted
clk2_gen : process (clk) begin
if (rising_edge(clk)) then
if (clk2_reset = '1') then
clk2 <= '1';
else
clk2 <= not clk2;
end if;
end if;
end process clk2_gen;
address <= std_logic_vector(address_u);
instruction_u <= unsigned(instruction);
in_port_u <= unsigned(in_port);
out_port <= std_logic_vector(out_port_u);
port_id <= std_logic_vector(port_id_u);
pc : entity work.program_counter
generic map(
interrupt_vector => interrupt_vector,
stack_depth => stack_depth
)
port map(
clk => clk,
reset => reset_int,
rst_req => rst_req,
bram_pause => bram_pause,
call => call,
ret => ret,
inter_j => inter_j,
jump => jump,
jmp_addr => jmp_addr,
address => address_u
);
-- alu
alu_inst : entity work.ALU
generic map(
hwbuild => hwbuild,
debug => debug
)
port map(
clk => clk,
clk2 => clk2,
reset => reset_int,
sleep_int => sleep_int,
opcode => opcode,
-- opA => opA,
opB => opB,
preserve_flags => preserve_flags,
restore_flags => restore_flags,
carry => carry,
zero => zero,
reg_value => reg_value_a,
reg_we => reg_we_a,
reg_reg0 => reg_reg0,
reg_reg1 => reg_reg1
);
decoder_inst : entity work.decoder
generic map(
interrupt_vector => interrupt_vector
)
port map(
clk => clk,
clk2 => clk2,
reset => reset,
reset_int => reset_int,
reset_bram_en => reset_bram_en,
rst_req => rst_req,
sleep => sleep,
sleep_int => sleep_int,
bram_pause => bram_pause,
clk2_reset => clk2_reset,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
instruction => instruction_u,
opcode => opcode,
opA => opA,
opB => opB,
reg0 => reg_reg0,
reg1 => reg_reg1,
carry => carry,
zero => zero,
call => call,
ret => ret,
inter_j => inter_j,
preserve_flags => preserve_flags,
restore_flags => restore_flags,
jmp_addr => jmp_addr,
jump => jump,
io_op_in => io_op_in,
io_op_out => io_op_out,
io_op_out_pp => io_op_out_pp,
io_kk_en => io_kk_en,
io_kk_port => io_kk_port,
io_kk_data => io_kk_data,
reg_address => reg_address,
reg_select => reg_select,
reg_star => reg_star,
spm_addr_ss => spm_addr_ss,
spm_ss => spm_ss,
spm_we => spm_we,
spm_rd => spm_rd
);
reg_value <= reg_value_io when (io_op_in or io_op_out) = '1' else reg_value_a when reg_we_a = '1' else reg_reg0;
reg_we <= reg_we_io or reg_we_a or reg_star or spm_rd;
register_file : entity work.reg_file
generic map(
scratch_pad_memory_size => scratch_pad_memory_size
)
port map(
clk => clk,
reg_address => reg_address,
reg_select => reg_select,
reg_star => reg_star,
value => reg_value,
write_en => reg_we,
reg0 => reg_reg0,
reg1 => reg_reg1,
spm_addr_ss => spm_addr_ss,
spm_ss => spm_ss,
spm_we => spm_we,
spm_rd => spm_rd
);
io_inst : entity work.io_module
port map(
clk => clk,
clk2 => clk2,
reset => reset_int,
reg_value => reg_value_io,
reg_we => reg_we_io,
reg_reg0 => reg_reg0,
reg_reg1 => reg_reg1,
out_data => opB,
io_op_in => io_op_in,
io_op_out => io_op_out,
io_op_out_pp => io_op_out_pp,
io_kk_en => io_kk_en,
io_kk_port => io_kk_port,
io_kk_data => io_kk_data,
-- actual i/o module ports
in_port => in_port_u,
port_id => port_id_u,
out_port => out_port_u,
read_strobe => read_strobe,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe
);
end Behavioral;
| apache-2.0 |
Paebbels/pauloBlaze | testbench/kcpsm6.vhd | 4 | 108754 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
-- Version 1.3 - 21st May 2014.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 |
willtmwu/vhdlExamples | Project/SPI_ctrlr_test.vhd | 1 | 5414 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_ctrlr_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Testing NRF state transitions
------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SPI_ctrlr_test IS
END SPI_ctrlr_test;
ARCHITECTURE behavior OF SPI_ctrlr_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPI_ctrlr
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
m_en : IN std_logic;
m_ready : OUT std_logic;
sTransmissionLines : in std_logic_vector(2 downto 0);
send_now : IN std_logic;
send_message : IN std_logic_vector(55 downto 0);
send_active : OUT std_logic;
recv_dtr : OUT std_logic;
recv_message : OUT std_logic_vector(55 downto 0);
recv_active : OUT std_logic;
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : in STD_LOGIC;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '1';
signal m_en : std_logic := '0';
signal send_now : std_logic := '0';
signal send_message : std_logic_vector(55 downto 0) := (others => '0');
signal hamming_err : std_logic_vector(7 downto 0) := (others => '0');
signal MISO : std_logic := '0';
signal IRQ : std_logic := '1';
signal sTransmissionLines : std_logic_vector(2 downto 0) := "010";
--Outputs
signal m_ready : std_logic;
signal send_active : std_logic;
signal recv_dtr : std_logic;
signal recv_message : std_logic_vector(55 downto 0);
signal recv_active : std_logic;
signal CE : std_logic;
signal CS : std_logic;
signal SCLK : std_logic;
signal MOSI : std_logic;
signal LED_SPI : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--Procedure should mimic NRF, will need to clock out
procedure SPI_MISO (
byte_in : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic
) is
begin
for i in 7 downto 0 loop
MISO <= byte_in(i);
wait until falling_edge(SCLK);
end loop;
end SPI_MISO;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SPI_ctrlr PORT MAP (
clk => clk,
masterReset => masterReset,
m_en => m_en,
m_ready => m_ready,
sTransmissionLines => sTransmissionLines,
send_now => send_now,
send_message => send_message,
send_active => send_active,
recv_dtr => recv_dtr,
recv_message => recv_message,
recv_active => recv_active,
hamming_err => hamming_err,
IRQ => IRQ,
CE => CE,
CS => CS,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
LED_SPI => LED_SPI
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
wait for clk_period*10;
masterReset <= '0';
m_en <= '1';
wait until M_ready = '1';
-- Module Intialised and Send
wait for clk_period*10;
wait until rising_edge(clk);
send_now <= '1';
send_message(55 downto 40) <= "1111000010100011";
wait until rising_edge(clk);
send_now <= '0';
wait until send_active = '0';
wait for clk_period*100;
-- Test Interrupt Reading
IRQ <= '0';
wait until rising_edge(clk);
IRQ <= '1';
wait until recv_active = '1';
SPI_MISO("11111101", MISO);
SPI_MISO("11000001", MISO);
wait until falling_edge(SCLK);
-- Send Through a message, In Hex, start wit basic location
SPI_MISO(x"FF", MISO); -- REG
SPI_MISO(x"00", MISO); -- 0
SPI_MISO(x"2B", MISO); -- 1
SPI_MISO(x"8E", MISO); -- 2
SPI_MISO(x"71", MISO); -- 3
SPI_MISO(x"6C", MISO); -- 4
SPI_MISO(x"5A", MISO); -- 5
SPI_MISO(x"47", MISO); -- 6
SPI_MISO(x"36", MISO); -- 7
SPI_MISO(x"2B", MISO); -- 8
SPI_MISO(x"1D", MISO); -- 9
SPI_MISO(x"2A", MISO); -- 10
SPI_MISO(x"47", MISO); -- 11
SPI_MISO(x"1D", MISO); -- 12
SPI_MISO(x"93", MISO); -- 13
SPI_MISO(x"2B", MISO); -- 14
SPI_MISO(x"36", MISO); -- 15
SPI_MISO(x"8E", MISO); -- 16
SPI_MISO(x"5A", MISO); -- 17
SPI_MISO(x"00", MISO); -- 18
SPI_MISO(x"00", MISO); -- 19
SPI_MISO(x"6C", MISO); -- 20
SPI_MISO(x"00", MISO); -- 21
SPI_MISO(x"5A", MISO); -- 22
SPI_MISO(x"00", MISO); -- 23
SPI_MISO(x"47", MISO); -- 24
SPI_MISO(x"00", MISO); -- 25
SPI_MISO(x"36", MISO); -- 26
SPI_MISO(x"00", MISO); -- 27
SPI_MISO(x"2B", MISO); -- 28
SPI_MISO(x"00", MISO); -- 29
SPI_MISO(x"1D", MISO); -- 30
SPI_MISO(x"00", MISO); -- 31
wait for clk_period*30000;
wait;
end process;
END;
| apache-2.0 |
willtmwu/vhdlExamples | Moving Averager/fetch_register.vhd | 1 | 1767 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fetch_register is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
mem_amount : in STD_LOGIC_VECTOR(4 downto 0);
--reg_val_lower : out STD_LOGIC_VECTOR(64 downto 0);
--reg_val_upper : out STD_LOGIC_VECTOR(64 downto 0);
reg_val : out STD_LOGIC_VECTOR(127 downto 0);
masterReset : in STD_LOGIC;
clk : in STD_LOGIC
);
end fetch_register;
architecture Behavioral of fetch_register is
type RAM is array (0 to 63) of integer range 0 to 255;
signal V : RAM := ( 12, 23, 222, 12, 231,42, 56, 121, 78,76,
23, 119, 12, 45, 55,100, 21, 3, 96, 34,
67, 1,1, 54, 133,55, 0, 5, 88, 64,
88, 123, 123, 24, 133,99, 25, 44, 98, 66,
200, 255, 20, 45, 255,255, 255, 255, 255, 54,
1, 251, 49, 234, 77,23, 33, 94, 66, 88,
222,12, 73, 75 );
begin
process (masterReset, clk)
variable address : integer range 0 to 64;
variable temp : std_logic_vector(127 downto 0);
begin
if (masterReset = '1') then
--reg_val_lower <= (others => '0');
--reg_val_upper <= (others => '0');
reg_val <= (others => '0');
elsif (clk'event and clk = '1') then
temp := (others => '0');
for I in 0 to conv_integer( IEEE.std_logic_arith.unsigned(mem_amount-1)) loop
--lowerAddr := 8*I;
--upperAddr := lowerAddr + 7;
address := conv_integer( IEEE.std_logic_arith.unsigned(mem_addr));
temp( (8*I + 7) downto 8*I) := std_logic_vector(IEEE.numeric_std.to_unsigned(V(address + I), 8));
--counter := counter + 1;
end loop;
reg_val <= temp;
end if;
end process;
end Behavioral; | apache-2.0 |
willtmwu/vhdlExamples | Basic Event Logic/practop_asynchro.vhd | 1 | 6165 | ----------------------------------------------------------------------------------
-- Company: University of Queensland
-- Engineer: MDS
--
-- Create Date: 25/07/2014
-- Design Name:
-- Module Name: pracTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practop_asynchro is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end practop_asynchro;
architecture Behavioral of practop_asynchro is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component clockedRegister port (
D : in STD_LOGIC_VECTOR (15 downto 0);
E : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal currentState : std_logic_vector(2 downto 0);
signal openLock : std_logic := '0';
signal closeLock : std_logic := '0';
signal correctAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal incorrectAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal displayKey : std_logic_vector(15 downto 0);
signal upperKey : std_logic_vector(7 downto 0);
signal lowerKey : std_logic_vector(7 downto 0);
signal checkKey : std_logic_vector(15 downto 0);
signal regEnable : std_logic;
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : clockedRegister port map (
D (7 downto 0) => lowerKey,
D (15 downto 8) => upperKey,
E => regEnable,
clk => clk100mhz,
reset => masterReset,
Q => checkKey
);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
logic_analyzer <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
regEnable <= '1';
process (masterReset, button1, displayKey) begin
if (masterReset = '1') then
lowerKey <= (others => '0');
displayKey(7 downto 0) <= "00000000";
elsif (button1'event and button1 = '1') then
displayKey(7 downto 0) <= slideSwitches(7 downto 0);
lowerKey <= slideSwitches(7 downto 0);
end if;
end process;
process (masterReset, button2, displayKey) begin
if (masterReset = '1') then
upperKey <= (others => '0');
displayKey (15 downto 8) <= "00000000";
elsif (button2'event and button2 = '1') then
displayKey (15 downto 8) <= slideSwitches(7 downto 0);
upperKey <= slideSwitches(7 downto 0);
end if;
end process;
--digit6 <= lowerKey(7 downto 4);
--digit5 <= lowerKey(3 downto 0);
--digit8 <= lowerKey(7 downto 4);
--digit7 <= lowerKey(3 downto 0);
process (masterReset, submitButton, button1, button2, displayKey) begin
if (masterReset = '1' or button1 = '1' or button2 = '1') then
openLock <= '0';
closeLock <= '0';
elsif (submitButton'event and submitButton = '1') then
if (lowerKey = "11111111" and upperKey = "11111110") then
openLock <= '1';
closeLock <= '0';
else
openLock <= '0';
closeLock <= '1';
end if;
end if;
end process;
process (openLock , clockScalers) begin
LEDs (15 downto 2) <= clockScalers(26 downto 13);
if(openLock = '1') then
LEDs(0) <= '0';
LEDs(1) <= '1';
else
LEDs(0) <= '1';
LEDs(1) <= '0';
end if;
end process;
digit6 <= incorrectAttempts(7 downto 4);
digit5 <= incorrectAttempts(3 downto 0);
digit8 <= correctAttempts(7 downto 4);
digit7 <= correctAttempts(3 downto 0);
process (masterReset, openlock) begin
if (masterReset = '1') then
correctAttempts <= (others => '0');
elsif (openLock'event and openLock = '1' ) then
correctAttempts <= correctAttempts + '1';
end if;
end process;
process (masterReset, closelock) begin
if (masterReset = '1') then
incorrectAttempts <= (others => '0');
elsif (closeLock'event and closeLock = '1' ) then
incorrectAttempts <= incorrectAttempts + '1';
end if;
end process;
end Behavioral;
| apache-2.0 |
zambreno/RCL | parallelCyGraph/vhdl/process3.vhd | 1 | 2567 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 3:
-- Read nodes from p2 response queue, request node CSR/Info
-- NOTE: (P2 response queue = P3 request queue + graphInfo)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process3 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 information
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end entity ; -- process3
architecture arch of process3 is
signal count : unsigned (31 downto 0);
begin
p3_count <= count;
p3 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
else
if (started = '1') then
-- Got process 2 response
if (p3_req_q_almost_full = '0' and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"02") then
-- request graphInfo + Neigh ID
p3_req_q_wr_en <= '1';
p3_req_q_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data(31 downto 0)) + unsigned(graphInfo), 64));
count <= count + 1;
else
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if;
-- Process 3 is done if process 2 is done and count = p2_count_2
if (p2_done = '1' and count = p2_count_2) then
p3_done <= '1';
end if;
else
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 3
end architecture; -- arch | apache-2.0 |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_32_32.vhd | 1 | 57406 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_32_32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 13:57:38 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_32_32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_32_32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end fifo_generator_32_32;
architecture STRUCTURE of fifo_generator_32_32 is
signal N0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44;
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"D4C4C4C4DCCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EEAAECA8AAAAA8A8"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"FF44FF0444440404"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP :
RAMB18SDP
generic map(
DO_REG => 0,
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
SRVAL => X"000000000"
)
port map (
RDCLK => clk,
WRCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
REGCE => N0,
SSR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDADDR(8) => N0,
RDADDR(7) => N0,
RDADDR(6) => N0,
RDADDR(5) => N0,
RDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
WRADDR(8) => N0,
WRADDR(7) => N0,
WRADDR(6) => N0,
WRADDR(5) => N0,
WRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED
,
WE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_1_d512.vhd | 1 | 103184 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_1_d512.vhd
-- /___/ /\ Timestamp: Mon Aug 18 13:21:56 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_1_d512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_1_d512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
din : in STD_LOGIC_VECTOR ( 0 downto 0 )
);
end fifo_generator_1_d512;
architecture STRUCTURE of fifo_generator_1_d512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal write_ctrl_187 : STD_LOGIC;
signal write_ctrl1_188 : STD_LOGIC;
signal write_ctrl2_189 : STD_LOGIC;
signal write_ctrl3_190 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109;
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl2_189,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED,
DPO => N11,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl_187,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED,
DPO => N7,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl1_188,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED,
DPO => N9,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl3_190,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED,
DPO => N13,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
inst_LPM_MUX31 : LUT6
generic map(
INIT => X"EFE5EAE04F454A40"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
I1 => N9,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I3 => N11,
I4 => N7,
I5 => N13,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"FA32F030FAF2F0F0"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
write_ctrl : LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl_187
);
write_ctrl1 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl1_188
);
write_ctrl2 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
O => write_ctrl2_189
);
write_ctrl3 : LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl3_190
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_512.vhd | 1 | 134346 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_512.vhd
-- /___/ /\ Timestamp: Wed Aug 13 01:45:08 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_512;
architecture STRUCTURE of fifo_generator_64_512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"F3A2F300FFA2FF00"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 |
vaisup/uvmprimer | 11_UVM_Test/tinyalu_dut/single_cycle_add_and_xor.vhd | 24 | 3045 | -- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
| apache-2.0 |
vaisup/uvmprimer | 23_UVM_Sequences/tinyalu_dut/single_cycle_add_and_xor.vhd | 24 | 3045 | -- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
| apache-2.0 |
google/myelin-acorn-electron-hardware | emulated_keyboard/prototype_cpld/emulated_keyboard.vhd | 1 | 8101 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This is part of a converter project that allows using a PS/2 keyboard on a BBC Master.
-- It's inspired by a similar project by Prime on the Stardot forums, which uses an MT8816
-- crosspoint switch to provide a *very* hardware-accurate emulation. This project uses
-- a CPLD instead, with knowledge of how the keyboard encoder IC on the Master works, to
-- implement it with hardware I already happen to have at home :)
-- It shouldn't be too hard to adapt this to provide a keyboard interface for an Electron,
-- which connects the keyboard directly to the address bus, connects BREAK to /RST, and
-- has four ULA inputs for the keyboard rows, plus one for CAPS LOCK.
-- The BBC Micro works slightly differently, including the keyboard encoder logic
-- on the keyboard PCB itself, so that would require some more changes.
entity emulated_keyboard is
Port (
-- nKBEN: '0' means col_idx is the column being polled, '1' means free running mode
nkben : in std_logic;
-- column index, taken straight from PL7
col_idx : in std_logic_vector(3 downto 0);
-- column inputs from keyboard encoder IC
-- On the encoder, these are open collector outputs, so they
-- need pullups, or the CPLD will see random input.
--col_input : in std_logic_vector(12 downto 0);
-- row outputs to keyboard encoder IC; these are pulled up to
-- 5V on the BBC Master motherboard
row_output : inout std_logic_vector(7 downto 0);
-- BREAK output to system /RESET (pulled up to 5V).
break_output : inout std_logic;
-- SPI pins to talk to whatever's giving us keyboard information
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic := '0'
);
end emulated_keyboard;
architecture Behavioural of emulated_keyboard is
-- SPI buffer
signal spi_buf : std_logic_vector(17 downto 0) := (others => '0');
-- SPI bit counter
signal spi_count : std_logic_vector(4 downto 0) := (others => '0');
-- value to match on the column inputs
signal col_match_1 : std_logic_vector(3 downto 0) := "0011";
signal col_match_2 : std_logic_vector(3 downto 0) := (others => '1');
-- value to output on row outputs when a match occurs
signal row_value_1 : std_logic_vector(2 downto 0) := "100";
signal row_value_2 : std_logic_vector(2 downto 0) := (others => '1');
-- '1' when SHIFT is pressed
signal shift_pressed : std_logic := '0';
-- '1' when CTRL is pressed
signal ctrl_pressed : std_logic := '0';
-- '1' when BREAK is pressed
signal break_pressed : std_logic := '0';
-- '1' when the column input matches col_match_1 or col_match_2, respectively
signal match_1 : std_logic;
signal match_2 : std_logic;
-- '1' when at least one key is pressed
signal have_keypress : std_logic;
-- index of currently strobed column
--signal col_idx : std_logic_vector(3 downto 0);
begin
-- set col_idx to the index of the column currently pulled low by the keyboard encoder, plus one.
-- one column will be low at a time, so we can just use multi-input NAND for this.
-- when no column is being strobed, col_idx will equal "0000".
-- when column 0 is being strobed, it will be "0001". for column 12, "1101".
--col_idx(3) <=
-- not (col_input(12) and col_input(11) and col_input(10) and col_input(9) and col_input(8) and col_input(7));
--col_idx(2) <=
-- not (col_input(12) and col_input(11) and col_input(6) and col_input(5) and col_input(4) and col_input(3));
--col_idx(1) <=
-- not (col_input(10) and col_input(9) and col_input(6) and col_input(5) and col_input(2) and col_input(1));
--col_idx(0) <=
-- not (col_input(12) and col_input(10) and col_input(8) and col_input(6) and col_input(4) and col_input(2) and col_input(0));
-- have_keypress = '1' when at least one key is pressed (except shift/ctrl/break)
have_keypress <= '0' when (col_match_1 = "1111" and col_match_2 = "1111") else '1';
-- match_1 and match_2 are '1' when their associated column is strobed by the keyboard encoder
match_1 <= '1' when col_idx = col_match_1 else '0';
match_2 <= '1' when col_idx = col_match_2 else '0';
-- pull row outputs low when their columns are matched
row_output(0) <= '0' when
(nkben = '1' and have_keypress = '1')
or (nkben = '0' and (
(match_1 = '1' and row_value_1 = "000") or (match_2 = '1' and row_value_2 = "000")
)
) else 'Z';
row_output(1) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "001") or (match_2 = '1' and row_value_2 = "001")
) else 'Z';
row_output(2) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "010") or (match_2 = '1' and row_value_2 = "010")
) else 'Z';
row_output(3) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "011") or (match_2 = '1' and row_value_2 = "011")
) else 'Z';
row_output(4) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "100") or (match_2 = '1' and row_value_2 = "100")
) else 'Z';
row_output(5) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "101") or (match_2 = '1' and row_value_2 = "101")
) else 'Z';
row_output(6) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "110") or (match_2 = '1' and row_value_2 = "110")
) else 'Z';
-- shift and ctrl are special; they have diodes for anti-ghosting
row_output(7) <= '0' when (col_idx = "0001" and ctrl_pressed = '1')
or (col_idx = "0000" and shift_pressed = '1') else 'Z';
-- break is handled separately
break_output <= '0' when break_pressed = '1' else 'Z';
-- SPI interface:
-- - Idle with spi_sel high
-- - Bring spi_sel low to start transaction
-- - Clock in 24 bits on spi_miso (data read on rising edge)
-- - 4 column bits (index of column to match, for key 1)
-- - 1 unused bit
-- - 3 row bits (index of row to return, for key 1)
-- - 4 column bits (index of column to match, for key 2)
-- - 1 unused bit
-- - 3 row bits (index of row to return, for key 2)
-- - SHIFT state (1 = pressed)
-- - CTRL state (1 = pressed)
-- - BREAK state (1 = pressed)
-- - 5 unused bits
-- - Data is copied into registers on 24th rising edge on spi_clk
-- - Return spi_sel high to end transaction / reset for next time
process (spi_clk)
begin
spi_miso <= '0'; -- unused
if spi_sel = '1' then
spi_count <= "00000";
elsif rising_edge(spi_clk) then
spi_buf <= spi_buf(16 downto 0) & spi_mosi;
spi_count <= std_logic_vector(unsigned(spi_count) + 1);
-- copy when we get the 19th bit
if spi_count = "10010" then
col_match_1 <= spi_buf(17 downto 14);
row_value_1 <= spi_buf(12 downto 10);
col_match_2 <= spi_buf(9 downto 6);
row_value_2 <= spi_buf(4 downto 2);
shift_pressed <= spi_buf(1);
ctrl_pressed <= spi_buf(0);
break_pressed <= spi_mosi;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 |
marzoul/PoC | src/arith/arith_convert_bin2bcd.vhdl | 2 | 5053 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Converter binary numbers to BCD encoded numbers.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library PoC;
use PoC.utils.all;
use PoC.components.all;
entity arith_convert_bin2bcd is
generic (
BITS : POSITIVE := 8;
DIGITS : POSITIVE := 3;
RADIX : POSITIVE := 2
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Start : in STD_LOGIC;
Busy : out STD_LOGIC;
Binary : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
IsSigned : in STD_LOGIC := '0';
BCDDigits : out T_BCD_VECTOR(DIGITS - 1 downto 0);
Sign : out STD_LOGIC
);
end;
architecture rtl of arith_convert_bin2bcd is
constant RADIX_BITS : POSITIVE := log2ceil(RADIX);
constant BINARY_SHIFTS : POSITIVE := div_ceil(BITS, RADIX_BITS);
constant BINARY_BITS : POSITIVE := BINARY_SHIFTS * RADIX_BITS;
subtype T_CARRY is UNSIGNED(RADIX_BITS - 1 downto 0);
type T_CARRY_VECTOR is array(NATURAL range <>) of T_CARRY;
signal Digit_Shift_rst : STD_LOGIC;
signal Digit_Shift_en : STD_LOGIC;
signal Digit_Shift_in : T_CARRY_VECTOR(DIGITS downto 0);
signal Binary_en : STD_LOGIC;
signal Binary_rl : STD_LOGIC;
signal Binary_d : STD_LOGIC_VECTOR(BINARY_BITS - 1 downto 0) := (others => '0');
signal Sign_d : STD_LOGIC := '0';
signal DelayShifter : STD_LOGIC_VECTOR(BINARY_SHIFTS downto 0) := '1' & (BINARY_SHIFTS - 1 downto 0 => '0');
function nextBCD(Value : UNSIGNED(4 downto 0)) return UNSIGNED is
constant Temp : UNSIGNED(4 downto 0) := Value - 10;
begin
if (Value > 9) then
return '1' & Temp(3 downto 0);
else
return Value;
end if;
end function;
begin
Busy <= not DelayShifter(DelayShifter'high);
Binary_en <= Start;
Binary_rl <= Start nor DelayShifter(DelayShifter'high);
Digit_Shift_rst <= Start;
Digit_Shift_en <= Start nor DelayShifter(DelayShifter'high);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Binary_d <= (others => '0');
elsif (Binary_en = '1') then
Binary_d(Binary_d'high downto Binary'high) <= (others => '0');
if ((IsSigned and Binary(Binary'high)) = '1') then
Binary_d(Binary'high downto 0) <= inc(not(Binary));
Sign_d <= '1';
else
Binary_d(Binary'high downto 0) <= Binary;
Sign_d <= '0';
end if;
DelayShifter <= (BINARY_SHIFTS downto 1 => '0') & '1';
elsif (Binary_rl = '1') then
DelayShifter <= DelayShifter(DelayShifter'high - 1 downto 0) & DelayShifter(DelayShifter'high);
Binary_d <= Binary_d(Binary_d'high - RADIX_BITS downto 0) & Binary_d(Binary_d'high downto Binary_d'high - RADIX_BITS + 1);
end if;
end if;
end process;
Sign <= Sign_d;
Digit_Shift_in(0) <= unsigned(Binary_d(Binary_d'high downto Binary_d'high - RADIX_BITS + 1));
-- generate DIGITS many systolic elements
genDigits : for i in 0 to DIGITS - 1 generate
signal Digit_nxt : UNSIGNED(3 + RADIX_BITS downto 0);
signal Digit_d : UNSIGNED(3 downto 0) := (others => '0');
begin
process(Digit_d, Digit_Shift_in)
variable Temp : UNSIGNED(4 downto 0);
begin
Temp := '0' & Digit_d;
for j in RADIX_BITS - 1 downto 0 loop
Temp := nextBCD(Temp(3 downto 0) & Digit_Shift_in(i)(j));
Digit_nxt(j + 4 downto j) <= Temp;
end loop;
end process;
Digit_Shift_in(i + 1) <= Digit_nxt(Digit_nxt'high downto Digit_nxt'high - RADIX_BITS + 1);
process(Clock)
begin
if rising_edge(Clock) then
if (Digit_Shift_rst = '1') then
Digit_d <= "0000";
elsif (Digit_Shift_en = '1') then
Digit_d <= Digit_nxt(Digit_d'range);
end if;
end if;
end process;
BCDDigits(i) <= t_bcd(std_logic_vector(Digit_d));
end generate;
end;
| apache-2.0 |
marzoul/PoC | src/arith/arith_sqrt.vhdl | 2 | 3744 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Iterative Square Root Extractor.
-- Its computation requires (N+1)/2 steps for an argument bit width of N.
--
-- Authors: Thomas B. Preußer
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity arith_sqrt is
generic (
N : positive -- := 8 -- Bit Width of Argument
);
port (
-- Global Control
rst : in std_logic; -- Reset (synchronous)
clk : in std_logic; -- Clock
-- Inputs
arg : in std_logic_vector(N-1 downto 0); -- Radicand
start : in std_logic; -- Start Strobe
-- Outputs
sqrt : out std_logic_vector((N-1)/2 downto 0); -- Result
rdy : out std_logic -- Ready / Done
);
end arith_sqrt;
architecture rtl of arith_sqrt is
-- Number of Iteration Steps = Number of Result Digits
constant STEPS : positive := (N+1)/2;
-- Intern Registers
signal Rmd : unsigned(N+STEPS-1 downto 0); -- Remainder / Result
signal Vld : unsigned(STEPS-1 downto 0); -- Result Flags
signal Res : unsigned(STEPS-1 downto 0); -- Extracted Result
-- Tentative Difference
signal diff : unsigned(STEPS+1 downto 0);
begin -- rtl
-- Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- Only clear Ready, everything else: '-'
Rmd <= (others => '-');
Vld <= (others => '-');
Vld(Vld'left) <= '0';
else
if start = '1' then
-- Initilize Computation
Rmd <= (Rmd'left downto N => '0') & unsigned(arg);
Vld <= (others => '1');
elsif Vld(Vld'left) = '1' then
-- Computation Step
-- New Residue
Rmd(N-1 downto 0) <= Rmd(N-3 downto 0) & '-' & not diff(diff'left); -- just shift lower bits
if diff(diff'left) = '1' then
-- Sub failed: just shift upper Part
Rmd(Rmd'left downto N) <= Rmd(Rmd'left-2 downto N-2);
else
-- Sub succeeded: replace by shifted Difference
Rmd(Rmd'left downto N) <= diff(diff'left-2 downto 0);
end if;
-- Validate Result Digit
Vld <= Vld(Vld'left-1 downto 0) & '0';
end if;
end if;
end if;
end process;
-- Extract Result
genRes: for i in Res'range generate
Res(i) <= Rmd(2*i) and not Vld(i);
end generate;
-- Tentative Subtraction: 4*rmd - (4*res+1)
diff <= Rmd(Rmd'left downto N-2) + ('1' & not Res(STEPS-2 downto 0) & "11");
-- Ouputs
sqrt <= std_logic_vector(Res);
rdy <= not Vld(Vld'left);
end rtl;
| apache-2.0 |
marzoul/PoC | tb/misc/sync/sync_Flag_tb.vhdl | 2 | 3109 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a flag signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Flag_tb is
end;
architecture test of sync_Flag_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal Sync_out : STD_LOGIC_VECTOR(0 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "X";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncFlag : entity PoC.sync_Flag
generic map (
BITS => 1, -- number of bit to be synchronized
INIT => "0" --
)
port map (
Clock => Clock2, -- input clock domain
Input => Sync_in, -- input bits
Output => Sync_out -- output bits
);
end;
| apache-2.0 |
pratikmallya/hue | tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/fpga/simulate/bin/work/chip_top/_primary.vhd | 2 | 452 | library verilog;
use verilog.vl_types.all;
entity chip_top is
port(
clk_ref : in vl_logic;
reset_sw : in vl_logic;
uart_rx : in vl_logic;
uart_tx : out vl_logic;
gpio_in : in vl_logic_vector(3 downto 0);
gpio_out : out vl_logic_vector(17 downto 0);
gpio_io : inout vl_logic_vector(15 downto 0)
);
end chip_top;
| apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/fpga/simulate/bin/work/bus_arbiter/_primary.vhd | 2 | 528 | library verilog;
use verilog.vl_types.all;
entity bus_arbiter is
port(
clk : in vl_logic;
reset : in vl_logic;
m0_req_n : in vl_logic;
m0_grant_n : out vl_logic;
m1_req_n : in vl_logic;
m1_grant_n : out vl_logic;
m2_req_n : in vl_logic;
m2_grant_n : out vl_logic;
m3_req_n : in vl_logic;
m3_grant_n : out vl_logic
);
end bus_arbiter;
| apache-2.0 |
TanND/Electronic | VHDL/D5_C2.vhd | 1 | 338 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D5_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D5_C2;
architecture D5_C2 of D5_C2 is
begin
process(clk)
begin
if(clk='1') then seg<="00001111";
else seg<="11110000";
end if;
end process;
end D5_C2;
-- clk=10Mhz; | apache-2.0 |
TanND/Electronic | VHDL/D10_C2.vhd | 1 | 284 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D10_C2 is
port(
clk : in STD_LOGIC;
y : out STD_LOGIC
);
end D10_C2;
architecture D10_C2 of D10_C2 is
begin
process(clk)
begin
if(clk='1') then y<='1';
else y<='0';
end if;
end process;
end D10_C2;
--clk=0.5hz | apache-2.0 |
TanND/Electronic | VHDL/D13_C1.vhd | 1 | 1225 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D13_C1 IS
PORT (
rst:in std_logic;
clk:IN STD_logic;
seg:out STD_Logic_vector(7 downto 0));
END D13_C1;
ARCHITECTURE D13_C1 of D13_C1 IS
signal temp: std_logic_vector(3 downto 0);
signal gray: std_logic_vector(3 downto 0);
begin
process (clk,rst)
begin
if(rst='1') then
temp<="0000";
gray<="0000";
elsif (rising_edge(clk)) then
if(temp="1001") then temp<="0000";
else temp <= temp+1;
end if;
gray(3)<=temp(3);
for i in 2 downto 0 loop
gray(i)<= temp(i+1) xor temp(i);
end loop;
end if;
end process;
process(gray)
begin
case gray is
when "0000" => seg<= x"C0";
when "0001" => seg<= x"F9";
when "0011" => seg<= x"A4";
when "0010" => seg<= x"B0";
when "0110" => seg<= x"99";
when "0111" => seg<= x"92";
when "0101" => seg<= x"82";
when "0100" => seg<= x"F8";
when "1100" => seg<= x"80";
when "1101" => seg<= x"90";
when others =>NULL;
end case;
end process;
end D13_C1;
--d= counter 100 ns; | apache-2.0 |
stephenlorenz/sproutstudy | sproutStudy_web/src/main/webapp/assets/components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/finalproject_cpu_jtag_debug_module_sysclk/_primary.vhd | 1 | 1102 | library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_jtag_debug_module_sysclk is
port(
clk : in vl_logic;
ir_in : in vl_logic_vector(1 downto 0);
sr : in vl_logic_vector(37 downto 0);
vs_udr : in vl_logic;
vs_uir : in vl_logic;
jdo : out vl_logic_vector(37 downto 0);
take_action_break_a: out vl_logic;
take_action_break_b: out vl_logic;
take_action_break_c: out vl_logic;
take_action_ocimem_a: out vl_logic;
take_action_ocimem_b: out vl_logic;
take_action_tracectrl: out vl_logic;
take_action_tracemem_a: out vl_logic;
take_action_tracemem_b: out vl_logic;
take_no_action_break_a: out vl_logic;
take_no_action_break_b: out vl_logic;
take_no_action_break_c: out vl_logic;
take_no_action_ocimem_a: out vl_logic;
take_no_action_tracemem_a: out vl_logic
);
end finalproject_cpu_jtag_debug_module_sysclk;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/finalproject_sdram_input_efifo_module/_primary.vhd | 1 | 620 | library verilog;
use verilog.vl_types.all;
entity finalproject_sdram_input_efifo_module is
port(
clk : in vl_logic;
rd : in vl_logic;
reset_n : in vl_logic;
wr : in vl_logic;
wr_data : in vl_logic_vector(61 downto 0);
almost_empty : out vl_logic;
almost_full : out vl_logic;
empty : out vl_logic;
full : out vl_logic;
rd_data : out vl_logic_vector(61 downto 0)
);
end finalproject_sdram_input_efifo_module;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/usb_system/altera_reset_synchronizer/_primary.vhd | 2 | 531 | library verilog;
use verilog.vl_types.all;
entity altera_reset_synchronizer is
generic(
ASYNC_RESET : integer := 1;
DEPTH : integer := 2
);
port(
reset_in : in vl_logic;
clk : in vl_logic;
reset_out : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ASYNC_RESET : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
end altera_reset_synchronizer;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/altera_avalon_mm_clock_crossing_bridge/_primary.vhd | 2 | 2332 | library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RESPONSE_FIFO_DEPTH: integer := 4;
MASTER_SYNC_DEPTH: integer := 2;
SLAVE_SYNC_DEPTH: integer := 2;
BYTEEN_WIDTH : vl_notype
);
port(
s0_clk : in vl_logic;
s0_reset : in vl_logic;
m0_clk : in vl_logic;
m0_reset : in vl_logic;
s0_waitrequest : out vl_logic;
s0_readdata : out vl_logic_vector;
s0_readdatavalid: out vl_logic;
s0_burstcount : in vl_logic_vector;
s0_writedata : in vl_logic_vector;
s0_address : in vl_logic_vector;
s0_write : in vl_logic;
s0_read : in vl_logic;
s0_byteenable : in vl_logic_vector;
s0_debugaccess : in vl_logic;
m0_waitrequest : in vl_logic;
m0_readdata : in vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_burstcount : out vl_logic_vector;
m0_writedata : out vl_logic_vector;
m0_address : out vl_logic_vector;
m0_write : out vl_logic;
m0_read : out vl_logic;
m0_byteenable : out vl_logic_vector;
m0_debugaccess : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SYMBOL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of HDL_ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BURSTCOUNT_WIDTH : constant is 1;
attribute mti_svvh_generic_type of COMMAND_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESPONSE_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of MASTER_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLAVE_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of BYTEEN_WIDTH : constant is 3;
end altera_avalon_mm_clock_crossing_bridge;
| apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/PLL/top_nto1_pll_diff_rx_and_tx.vhd | 1 | 10131 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_pll_diff_rx_and_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential input receiver and transmitter for clock and data using PLL
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_pll_diff_rx_and_tx is port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- lvds clock input
datain_p, datain_n : in std_logic_vector(5 downto 0) ; -- lvds data inputs
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end top_nto1_pll_diff_rx_and_tx ;
architecture arch_top_nto1_pll_diff_rx_and_tx of top_nto1_pll_diff_rx_and_tx is
component serdes_1_to_n_data_s8_diff generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
component serdes_1_to_n_clk_pll_s8_diff generic (
PLLD : integer := 1 ; -- Parameter to set division for PLL
CLKIN_PERIOD : real := 6.700 ; -- Set PLL multiplier
PLLX : integer := 2 ; -- Set PLL multiplier
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
BS : boolean := FALSE) ; -- Parameter to enable bitslip TRUE or FALSE
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0) ; -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic ; -- Global clock
rx_pll_lckd : out std_logic ; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic ; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic ; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end component ;
component serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 4
constant D : integer := 6 ; -- Set the number of inputs and outputs to be 6
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal clk_iserdes_data : std_logic_vector(6 downto 0) ;
signal rx_bufg_x1 : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ;
signal capture : std_logic_vector(6 downto 0) ;
signal counter : std_logic_vector(3 downto 0) ;
signal bitslip : std_logic ;
signal rst : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufpll_clk_xn : std_logic ;
signal rx_bufpll_lckd : std_logic ;
signal not_bufpll_lckd : std_logic ;
signal temp1p : std_logic_vector(0 downto 0) ;
signal temp1n : std_logic_vector(0 downto 0) ;
signal txd : std_logic_vector(DS downto 0) ;
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := "1100001" ; -- Transmit a constant to make a clock
begin
rst <= reset ; -- active high reset pin
-- Clock Input, Generate ioclocks via PLL
clkin : serdes_1_to_n_clk_pll_s8_diff generic map(
CLKIN_PERIOD => 6.700,
PLLD => 1,
PLLX => S,
S => S,
BS => TRUE) -- Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
port map (
clkin_p => clkin_p,
clkin_n => clkin_n,
rxioclk => rx_bufpll_clk_xn,
pattern1 => "1100001", -- default values for 7:1 video applications
pattern2 => "1100011",
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_pll_x1 => rx_bufg_x1,
bitslip => bitslip,
reset => rst,
datain => clk_iserdes_data,
rx_pll_lckd => open, -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs => open, -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
rx_bufpll_lckd => rx_bufpll_lckd) ;
-- Data Inputs
not_bufpll_lckd <= not rx_bufpll_lckd ;
datain : serdes_1_to_n_data_s8_diff generic map(
S => S,
D => D)
port map (
use_phase_detector => '1',
datain_p => datain_p,
datain_n => datain_n,
rxioclk => rx_bufpll_clk_xn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bitslip,
reset => not_bufpll_lckd,
debug_in => "00",
data_out => rxd,
debug => open) ;
process (rx_bufg_x1)
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
txd <= rxd ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
clkout : serdes_n_to_1_s8_diff generic map (
S => S,
D => 1)
port map (
dataout_p => temp1p,
dataout_n => temp1n,
txioclk => rx_bufpll_clk_xn,
txserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= temp1p(0) ;
clkout_n <= temp1n(0) ;
-- Instantiate Outputs and output serialisers for output data lines
dataout : serdes_n_to_1_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclk => rx_bufpll_clk_xn,
txserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_pll_diff_rx_and_tx ; | apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_n_to_1_ddr_s8_diff.vhd | 1 | 9467 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic DDR n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK parameter if required
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_ddr_s8_diff ;
architecture arch_serdes_n_to_1_ddr_s8_diff of serdes_n_to_1_ddr_s8_diff is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdataina : std_logic_vector(D*8 downto 0) ;
signal mdatainb : std_logic_vector(D*4 downto 0) ;
signal tx_data_out : std_logic_vector(D downto 0) ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate ;
end generate ;
end arch_serdes_n_to_1_ddr_s8_diff ;
| apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_se_rx.vhd | 1 | 7746 | ------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_se_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example single ended input receiver for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_se_rx is port (
reset : in std_logic ; -- reset (active high)
datain : in std_logic_vector(7 downto 0) ; -- single ended data inputs
clkin1, clkin2 : in std_logic ; -- TWO single ended clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end top_nto1_ddr_se_rx ;
architecture arch_top_nto1_ddr_se_rx of top_nto1_ddr_se_rx is
component serdes_1_to_n_clk_ddr_s8_se is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin1 : in std_logic ; -- Input from se receiver pin
clkin2 : in std_logic ; -- Input from se receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end component ;
component serdes_1_to_n_data_ddr_s8_se is generic (
USE_PD : boolean := FALSE ; -- Parameter to set generation of phase detector logic
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
-- constants for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor to 8
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ; -- Data from serdeses
signal rxr : std_logic_vector(DS downto 0); -- signalistered Data from serdeses
signal state : std_logic ;
signal bslip : std_logic ;
signal count : std_logic_vector(3 downto 0);
signal rxioclkp : std_logic ;
signal rxioclkn : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufg_x1 : std_logic ;
begin
rst <= reset ; -- active high reset pin
dummy_out <= rxr ;
-- Clock Input. Generate ioclocks via BUFIO2
inst_clkin : serdes_1_to_n_clk_ddr_s8_se generic map(
S => S)
port map (
clkin1 => clkin1,
clkin2 => clkin2,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_x1 => rx_bufg_x1);
-- Data Inputs
inst_datain : serdes_1_to_n_data_ddr_s8_se generic map(
S => S,
D => D,
USE_PD => TRUE) -- Enables use of the phase detector - will require 2 input serdes whatever the serdes ratio required
port map (
use_phase_detector => '1', -- '1' enables the phase detector logic
datain => datain,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bslip,
reset => rst,
data_out => rxd,
debug_in => "00",
debug => open);
process (rx_bufg_x1, rst) -- example bitslip logic, if required
begin
if rst = '1' then
state <= '0' ;
bslip <= '1' ;
count <= "0000" ;
elsif rx_bufg_x1'event and rx_bufg_x1 = '1' then
if state = '0' then
if rxd(63 downto 60) /= "0011" then
bslip <= '1' ; -- bitslip needed
state <= '1' ;
count <= "0000" ;
end if ;
elsif state = '1' then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "1111" then
state <= '0' ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_x1) -- process received data
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
rxr <= rxd ;
end if ;
end process ;
end arch_top_nto1_ddr_se_rx ;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/usb_system/altera_dcfifo_synchronizer_bundle/_primary.vhd | 2 | 598 | library verilog;
use verilog.vl_types.all;
entity altera_dcfifo_synchronizer_bundle is
generic(
WIDTH : integer := 1;
DEPTH : integer := 3
);
port(
clk : in vl_logic;
reset_n : in vl_logic;
din : in vl_logic_vector;
dout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of WIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
end altera_dcfifo_synchronizer_bundle;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/rtl_work/ball/_primary.vhd | 1 | 2298 | library verilog;
use verilog.vl_types.all;
entity ball is
generic(
Ball_X_Center : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_X_Right : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_X_Left : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_Y_Center : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_X_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_X_Max : vl_logic_vector(9 downto 0) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1);
Ball_Y_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_Y_Max : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1);
Ball_X_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
Ball_Y_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1)
);
port(
Reset : in vl_logic;
frame_clk : in vl_logic;
keycode : in vl_logic_vector(7 downto 0);
color : in vl_logic;
BallX : out vl_logic_vector(9 downto 0);
BallY : out vl_logic_vector(9 downto 0);
BallS : out vl_logic_vector(9 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of Ball_X_Center : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Right : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Left : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Center : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Min : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Max : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Min : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Max : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Step : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Step : constant is 2;
end ball;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/altera_avalon_st_handshake_clock_crosser/_primary.vhd | 2 | 2458 | library verilog;
use verilog.vl_types.all;
entity altera_avalon_st_handshake_clock_crosser is
generic(
DATA_WIDTH : integer := 8;
BITS_PER_SYMBOL : integer := 8;
USE_PACKETS : integer := 0;
USE_CHANNEL : integer := 0;
CHANNEL_WIDTH : integer := 1;
USE_ERROR : integer := 0;
ERROR_WIDTH : integer := 1;
VALID_SYNC_DEPTH: integer := 2;
READY_SYNC_DEPTH: integer := 2;
USE_OUTPUT_PIPELINE: integer := 1;
SYMBOLS_PER_BEAT: vl_notype;
EMPTY_WIDTH : vl_notype
);
port(
in_clk : in vl_logic;
in_reset : in vl_logic;
out_clk : in vl_logic;
out_reset : in vl_logic;
in_ready : out vl_logic;
in_valid : in vl_logic;
in_data : in vl_logic_vector;
in_channel : in vl_logic_vector;
in_error : in vl_logic_vector;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
out_ready : in vl_logic;
out_valid : out vl_logic;
out_data : out vl_logic_vector;
out_channel : out vl_logic_vector;
out_error : out vl_logic_vector;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_CHANNEL : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_ERROR : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of VALID_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of READY_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of USE_OUTPUT_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 3;
attribute mti_svvh_generic_type of EMPTY_WIDTH : constant is 3;
end altera_avalon_st_handshake_clock_crosser;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/finalproject_jtag_uart/_primary.vhd | 1 | 676 | library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart is
port(
av_address : in vl_logic;
av_chipselect : in vl_logic;
av_read_n : in vl_logic;
av_write_n : in vl_logic;
av_writedata : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
rst_n : in vl_logic;
av_irq : out vl_logic;
av_readdata : out vl_logic_vector(31 downto 0);
av_waitrequest : out vl_logic;
dataavailable : out vl_logic;
readyfordata : out vl_logic
);
end finalproject_jtag_uart;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/usb_system/usb_system_mm_interconnect_0_router/_primary.vhd | 1 | 769 | library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end usb_system_mm_interconnect_0_router;
| apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_s8_se.vhd | 1 | 15943 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with se inputs
-- Takes in 1 bit of se data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s8_se is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0) ; -- Input from se receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_s8_se ;
architecture arch_serdes_1_to_n_data_s8_se of serdes_1_to_n_data_s8_se is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal ce_data_inta : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
cal_data_slave <= cal_data_sint ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUF port map (
I => datain(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s8_se ;
| apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_sdr_s8_diff.vhd | 1 | 6818 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_sdr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors from 2 to 8 with differential inputs
-- Instantiates necessary BUFIO2 clock buffers
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_sdr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end serdes_1_to_n_clk_sdr_s8_diff ;
architecture arch_serdes_1_to_n_clk_sdr_s8_diff of serdes_1_to_n_clk_sdr_s8_diff is
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal rx_clk_in : std_logic; --
signal iob_data_in_p : std_logic; --
signal iob_data_in_n : std_logic; --
signal rx_clk_in_p : std_logic; --
signal rx_clk_in_n : std_logic; --
signal rx_bufio2_x1 : std_logic; --
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in_p) ;
iob_data_in_p <= rx_clk_in_p xor RX_SWAP_CLK ; -- Invert clock as required
-- IODELAY for the differential inputs.
--
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_p, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line to 1/2 max in this case
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
bufg_pll_x1 : BUFG port map (I => rx_bufio2_x1, O => rx_bufg_x1) ;
bufio2_2clk_inst : BUFIO2 generic map(
DIVIDE => S,
DIVIDE_BYPASS => FALSE) -- The DIVCLK divider divide-by value; default 1
port map (
I => ddly_m, -- Input source clock 0 degrees
IOCLK => rxioclk, -- Output Clock for IO
DIVCLK => rx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => rx_serdesstrobe) ; -- Output SERDES strobe (Clock Enable)
end arch_serdes_1_to_n_clk_sdr_s8_diff ;
| apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_sdr_s8_diff.vhd | 1 | 6489 | ------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_sdr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based SDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for data transmission
-- at input clock rate for one half bank using one BUFIO2, and one for
-- clock transmission at double the input clock rate (to get the
-- original clock back) using 2 BUFIO2 in the other half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_sdr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclka : out std_logic ; -- A ioclock from BUFIO2 for data transmission
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2 for data transmission
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - for clock transmission
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - for clock transmission
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - for clock transmission
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_sdr_s8_diff ;
architecture arch_clock_generator_sdr_s8_diff of clock_generator_sdr_s8_diff is
signal clkint : std_logic ; --
signal gclk_int : std_logic ; --
signal freqgen_in_p : std_logic ; --
signal tx_bufio2_x1 : std_logic ; --
begin
gclk <= gclk_int ;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclka, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => TRUE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
I_INVERT => TRUE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int) ;
end arch_clock_generator_sdr_s8_diff ; | apache-2.0 |
Jawanga/ece385final | simulation/modelsim/usb_system/usb_system_jtag_uart_scfifo_w/_primary.vhd | 1 | 578 | library verilog;
use verilog.vl_types.all;
entity usb_system_jtag_uart_scfifo_w is
port(
clk : in vl_logic;
fifo_clear : in vl_logic;
fifo_wdata : in vl_logic_vector(7 downto 0);
fifo_wr : in vl_logic;
rd_wfifo : in vl_logic;
fifo_FF : out vl_logic;
r_dat : out vl_logic_vector(7 downto 0);
wfifo_empty : out vl_logic;
wfifo_used : out vl_logic_vector(5 downto 0)
);
end usb_system_jtag_uart_scfifo_w;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/usb_system/usb_system_mm_interconnect_1/_primary.vhd | 1 | 1300 | library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_1 is
port(
clocks_c1_clk : in vl_logic;
clock_crossing_io_m0_reset_reset_bridge_in_reset_reset: in vl_logic;
clock_crossing_io_m0_address: in vl_logic_vector(21 downto 0);
clock_crossing_io_m0_waitrequest: out vl_logic;
clock_crossing_io_m0_burstcount: in vl_logic_vector(0 downto 0);
clock_crossing_io_m0_byteenable: in vl_logic_vector(3 downto 0);
clock_crossing_io_m0_read: in vl_logic;
clock_crossing_io_m0_readdata: out vl_logic_vector(31 downto 0);
clock_crossing_io_m0_readdatavalid: out vl_logic;
clock_crossing_io_m0_write: in vl_logic;
clock_crossing_io_m0_writedata: in vl_logic_vector(31 downto 0);
clock_crossing_io_m0_debugaccess: in vl_logic;
CY7C67200_IF_0_hpi_address: out vl_logic_vector(1 downto 0);
CY7C67200_IF_0_hpi_write: out vl_logic;
CY7C67200_IF_0_hpi_read: out vl_logic;
CY7C67200_IF_0_hpi_readdata: in vl_logic_vector(31 downto 0);
CY7C67200_IF_0_hpi_writedata: out vl_logic_vector(31 downto 0);
CY7C67200_IF_0_hpi_chipselect: out vl_logic
);
end usb_system_mm_interconnect_1;
| apache-2.0 |
Jawanga/ece385final | simulation/modelsim/finalproject/altera_merlin_master_translator/_primary.vhd | 1 | 4417 | library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
USE_BURSTCOUNT : integer := 1;
USE_BEGINBURSTTRANSFER: integer := 0;
USE_BEGINTRANSFER: integer := 0;
USE_CHIPSELECT : integer := 0;
USE_READ : integer := 1;
USE_READDATAVALID: integer := 1;
USE_WRITE : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_WRITERESPONSE: integer := 0;
USE_READRESPONSE: integer := 0;
AV_REGISTERINCOMINGSIGNALS: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_CONSTANT_BURST_BEHAVIOR: integer := 1;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
AV_LINEWRAPBURSTS: integer := 0;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_write : out vl_logic;
uav_read : out vl_logic;
uav_address : out vl_logic_vector;
uav_burstcount : out vl_logic_vector;
uav_byteenable : out vl_logic_vector;
uav_writedata : out vl_logic_vector;
uav_lock : out vl_logic;
uav_debugaccess : out vl_logic;
uav_clken : out vl_logic;
uav_readdata : in vl_logic_vector;
uav_readdatavalid: in vl_logic;
uav_waitrequest : in vl_logic;
uav_response : in vl_logic_vector(1 downto 0);
uav_writeresponsevalid: in vl_logic;
av_write : in vl_logic;
av_read : in vl_logic;
av_address : in vl_logic_vector;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_writedata : in vl_logic_vector;
av_begintransfer: in vl_logic;
av_beginbursttransfer: in vl_logic;
av_lock : in vl_logic;
av_chipselect : in vl_logic;
av_debugaccess : in vl_logic;
av_clken : in vl_logic;
av_readdata : out vl_logic_vector;
av_readdatavalid: out vl_logic;
av_waitrequest : out vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponsevalid: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of USE_BURSTCOUNT : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINBURSTTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_CHIPSELECT : constant is 1;
attribute mti_svvh_generic_type of USE_READ : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WRITE : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_REGISTERINCOMINGSIGNALS : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_LINEWRAPBURSTS : constant is 1;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
end altera_merlin_master_translator;
| apache-2.0 |
fabianschuiki/moore | test/vhdl/pkg_0.vhd | 1 | 421 | --@ elab pkg_a
package pkg_a is
end package;
--!@ elab pkg_b
package pkg_b is
type BYTE is range 0 to 255;
constant K : BYTE;
end package;
--!@ elab pkg_c
package pkg_c is
use work.pkg_b.BYTE;
type SHORT is range 0 to 65535;
type INT is range 0 to 4294967295;
type PTR is access BYTE;
--type KILOBYTE is array (SHORT range <>) of BYTE;
constant K0 : BYTE;
constant K1 : SHORT;
constant K2 : INT;
end package;
| apache-2.0 |
fabianschuiki/moore | test/vhdl/std_integer.vhd | 1 | 455 | entity foo is end;
architecture bar of foo is
constant xA : std.standard.INTEGER;
constant xB : INTEGER := -128;
constant xC : INTEGER := 127;
constant yA : std.standard.NATURAL;
constant yB : NATURAL := 0;
constant yC : NATURAL := 127;
constant zA : std.standard.POSITIVE;
constant zB : POSITIVE := 1;
constant zC : POSITIVE := 127;
constant uA : std.standard.INTEGER_VECTOR;
constant uB : INTEGER_VECTOR(0 to 1) := (-42, 42);
begin end;
| apache-2.0 |
fabianschuiki/moore | test/vhdl/entity_0.vhd | 1 | 91 | entity foo is
end;
architecture bar of foo is
begin
end;
-- entity @foo_bar () () {
-- }
| apache-2.0 |
fabianschuiki/moore | test/vhdl/overload_ops.vhd | 1 | 514 | package pkg is
type MVL is ('0', '1', 'Z', 'X');
type MVL_Vector is array (Natural range <>) of MVL;
function "and" (Left, Right: MVL) return MVL;
function "or" (Left, Right: MVL) return MVL;
function "not" (Value: MVL) return MVL;
function "xor" (Right: MVL_Vector) return MVL;
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
signal Q,R,S,T: MVL;
signal V: MVL_Vector(0 to 3);
begin
Q <= 'X' or '1';
R <= "or" ('0','Z');
S <= (Q and R) or not S;
T <= xor V;
end;
| apache-2.0 |
fabianschuiki/moore | test/vhdl/type_array.vhd | 1 | 1838 | package pkg is
type BIT is ('0','1');
type FIVE_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type INTEGER is range -2147483648 to 2147483647;
type NATURAL is range 0 to 4294967295;
type MY_WORD is array (0 to 31) of BIT; -- fully constrained
type BITMAP is array(BIT) of FIVE_LEVEL_LOGIC;
type DATA_IN is array (7 downto 0) of FIVE_LEVEL_LOGIC; -- fully constrained
type MEMORY is array (INTEGER range <>) of MY_WORD; -- partially constrained
type SIGNED_FXPT is array (INTEGER range <>) of BIT; -- unconstrained
type SIGNED_FXPT_VECTOR is array (NATURAL range <>) of SIGNED_FXPT; -- unconstrained
type SIGNED_FXPT_5x4 is array (1 to 5, 1 to 4) of SIGNED_FXPT; -- partially constrained
type MEMORY2 is array (INTEGER range 0 to 18) of MY_WORD;
type E is array (NATURAL range <>) of INTEGER;
type F is array (NATURAL range <>) of MY_WORD;
type T0 is array (1 to 10) of F (1 to 0);
type T1 is array (10 to 1) of F (0 to 1);
type T2 is array (1 to 10) of F (0 to 1) (4 to 8);
type T3 is array (1 to 10) of F (open);
type T4 is array (1 to 10) of F (open) (4 to 8);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
--signal a: DATA_IN;
--signal b: MEMORY (0 to 255);
--signal c: SIGNED_FXPT (3 downto -4);
--signal d: SIGNED_FXPT_VECTOR (1 to 20)(9 downto 0);
--signal e: SIGNED_FXPT_5x4 (open)(3 downto -4);
--signal f0: T0;
--signal f1: T1;
begin end;
--!@ elab foo(bar)
--| entity @foo_bar () () {
--| %a = sig [8 x n5] [.. 0]
--| %b = sig [256 x [32 x n2]] [.. [.. 0]]
--| %c = sig [8 x n2] [.. 0]
--| %d = sig [20 x [10 x n2]] [.. [.. 0]]
--| %e = sig [5 x [4 x [8 x n2]]] [.. [.. [.. 0]]]
--| %f0 = sig [10 x void] [.. void]
--| %f1 = sig void void
--| }
| apache-2.0 |
fabianschuiki/moore | test/vhdl/process_1.vhd | 1 | 371 | entity foo is
end;
architecture bar of foo is
type bit is range 0 to 1;
signal a : bit;
begin
toggle : process
begin
a <= 0;
a <= 1;
end process;
end;
--@ +elab foo(bar)
--| proc @foo_bar_toggle () (i1$ a) {
--| drv %a 0
--| drv %a 1
--| }
--|
--| entity @foo_bar () () {
--| %a = sig i1 0
--| %toggle = inst @foo_bar_toggle () (i1$ %a)
--| }
| apache-2.0 |
fabianschuiki/moore | test/vhdl/std_logic_1164.vhd | 1 | 9718 | -- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
-- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector;
-- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
| apache-2.0 |
Piasy/THCO-MIPS-CPU | src/MUX_6.vhd | 2 | 1809 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:32:35 11/22/2013
-- Design Name:
-- Module Name: MUX_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_6 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_6;
architecture Behavioral of MUX_6 is
begin
process (SRC_1, SRC_2, SRC_3, SRC_4, SRC_5, SRC_6, SELEC)
begin
case SELEC is
when "000" =>
OUTPUT <= SRC_1;
when "001" =>
OUTPUT <= SRC_2;
when "010" =>
OUTPUT <= SRC_3;
when "011" =>
OUTPUT <= SRC_4;
when "100" =>
OUTPUT <= SRC_5;
when "101" =>
OUTPUT <= SRC_6;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
| apache-2.0 |
kb3gtn/mojo_modulator | vhdl/src/databus_master.vhd | 3 | 6897 | -----------------------------------------------------------------------------
-- databus_master.vhd
-- This file provides a simple data bus master design that can
-- interface with an 8 bit command bus.
--
-- Command Formats:
--
-- The commands are 8 bits in length.
--
-- In general this is the read/write command format for the databus.
--
-- Bit 7 Bit 0
-- R/!W A7 A6 A5 A4 A3 A2 A1 A0
--
-- There are 2 exceptions:
-- 0xFF and 0x7F are idle commands (they do nothing)
--
-- this means there are 0 -> 126 address in the databus master.
-- each address addresses 8 bits of memory.
--
-- Peter Fetterer <[email protected]>
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity databus_master is
Generic (
slave_latency_max : integer := 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
);
Port (
-- clock and resets
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- db master cmd interface
i_db_cmd_in : in std_logic_vector( 7 downto 0); -- input cmd byte
i_db_cmd_wstrb : in std_logic; -- write strobe for cmd byte
o_db_cmd_rdy : out std_logic; -- '1' rdy to process next cmd, '0' busy
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- input byte if cmd is a write (with wstrb)
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- output byte if cmd was a read
-- data bus interface
o_db_addr : out std_logic_vector( 6 downto 0); -- 6 -> 0 bit address bus (7 bits)
o_db_write_data : out std_logic_vector( 7 downto 0); -- write data
i_db_read_data : in std_logic_vector( 7 downto 0); -- read data
o_db_read_strb : out std_logic; -- db_read_strobe
o_db_write_strb : out std_logic -- db_write_strobe
);
end entity;
architecture b of databus_master is
---------------------------------------------
-- Signals
---------------------------------------------
signal db_state : integer;
signal slv_latency_cntr : integer;
signal db_data_read : std_logic_vector( 7 downto 0);
signal db_data_write : std_logic_vector( 7 downto 0);
signal db_addr : std_logic_vector( 6 downto 0);
signal db_wr_active : std_logic;
signal db_rd_active : std_logic;
begin
o_db_addr <= db_addr;
o_db_write_data <= db_data_write;
o_db_write_strb <= db_wr_active;
o_db_cmd_data_out <= db_data_read;
db_state_machine : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- in reset
db_state <= 0;
o_db_cmd_rdy <= '0';
db_addr <= (others=>'0');
db_data_write <= (others=>'0');
o_db_read_strb <= '0';
db_wr_active <= '0';
slv_latency_cntr <= 0;
else
-- state mux
case db_state is
when 0 =>
-- start of cycle
-- signal ready for a new command
o_db_cmd_rdy <= '1';
db_wr_active <= '0';
o_db_read_strb <= '0';
db_state <= 1;
when 1 =>
-- wait for a command
if ( i_db_cmd_wstrb = '1' ) then
-- we have a command to process
if ( i_db_cmd_in = x"FF" ) or ( i_db_cmd_in = x"7F" ) then
-- idle command.. ignore
db_state <= 1; -- stay here, wait for next cmd
else
-- this is a real command
db_addr <= i_db_cmd_in(6 downto 0); -- get address for cmd..
-- Is it a read or a write....
if ( i_db_cmd_in(7) = '1' ) then
-- this is a read register command
-- issue read request on address
o_db_read_strb <= '1';
o_db_cmd_rdy <= '0'; -- busy
db_state <= 2;
else
-- this is a write register command
-- issue write request
db_data_write <= i_db_cmd_data_in;
db_wr_active <= '1';
o_db_cmd_rdy <= '0'; -- busy
db_state <= 4;
end if;
end if;
end if;
when 2 =>
-- read command started...
-- need to wait for slave_latency_max clock cycles
if ( slv_latency_cntr = slave_latency_max ) then
-- slave latency counter expired..
-- push down read strobe when timer expires
o_db_read_strb <= '0';
db_data_read <= i_db_read_data; -- sample read bus into local register.
slv_latency_cntr <= 0;
db_state <= 0;
else
slv_latency_cntr <= slv_latency_cntr + 1;
end if;
-- state 3 removed..
when 4 =>
-- write request wait period.
db_wr_active <= '0';
-- need to wait for slave_latency_max clock cycles
if ( slv_latency_cntr = slave_latency_max ) then
-- slave latency counter expired..
slv_latency_cntr <= 0;
-- write should be complete now..
db_state <= 0;
else
slv_latency_cntr <= slv_latency_cntr + 1;
end if;
when others =>
db_state <= 0;
end case;
end if;
end if;
end process;
end architecture;
| apache-2.0 |
sudov/options-accel | final_design/fifo.prj/sol/syn/vhdl/dut.vhd | 2 | 11938 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dut is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_fifo_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
in_fifo_V_empty_n : IN STD_LOGIC;
in_fifo_V_read : OUT STD_LOGIC;
out_fifo_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
out_fifo_V_full_n : IN STD_LOGIC;
out_fifo_V_write : OUT STD_LOGIC );
end;
architecture behav of dut is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"dut,hls_ip_2014_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.789000,HLS_SYN_LAT=12,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (3 downto 0) := "1010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (3 downto 0) := "1011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
signal tmp_3_reg_119 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal tmp_6_reg_124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_reg_129 : STD_LOGIC_VECTOR (31 downto 0);
signal full_fu_66_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal full_reg_134 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_fu_83_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_reg_139 : STD_LOGIC_VECTOR (63 downto 0);
signal data1_reg_154 : STD_LOGIC_VECTOR (31 downto 0);
signal data2_fu_111_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal data2_reg_159 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_fu_115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_52_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_52_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_56_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal full_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_reg_124_temp: signed (32-1 downto 0);
signal tmp_s_fu_72_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_fu_83_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal in_fifo_V_dout_temp: signed (32-1 downto 0);
signal grp_fu_52_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ret_fu_97_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_52_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component dut_dmul_64ns_64ns_64_6_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
dut_dmul_64ns_64ns_64_6_max_dsp_U1 : component dut_dmul_64ns_64ns_64_6_max_dsp
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_52_p0,
din1 => grp_fu_52_p1,
ce => grp_fu_52_ce,
dout => grp_fu_52_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
data1_reg_154 <= ret_fu_97_p1(63 downto 32);
data2_reg_159 <= data2_fu_111_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
full_1_reg_139 <= full_1_fu_83_p2;
full_reg_134 <= full_fu_66_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((in_fifo_V_empty_n = ap_const_logic_0)))) then
tmp_3_reg_119 <= in_fifo_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm))) then
tmp_6_reg_124 <= in_fifo_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
tmp_7_reg_129 <= in_fifo_V_dout;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (in_fifo_V_empty_n, out_fifo_V_full_n, ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
data2_fu_111_p1 <= ret_fu_97_p1(16 - 1 downto 0);
in_fifo_V_dout_temp <= signed(in_fifo_V_dout);
full_1_fu_83_p1 <= std_logic_vector(resize(in_fifo_V_dout_temp,64));
full_1_fu_83_p2 <= std_logic_vector(unsigned(tmp_s_fu_72_p3) + unsigned(full_1_fu_83_p1));
tmp_6_reg_124_temp <= signed(tmp_6_reg_124);
full_fu_66_p1 <= std_logic_vector(resize(tmp_6_reg_124_temp,64));
full_fu_66_p2 <= std_logic_vector(unsigned(tmp_4_fu_56_p3) + unsigned(full_fu_66_p1));
grp_fu_52_ce <= ap_const_logic_1;
grp_fu_52_p0 <= full_reg_134;
grp_fu_52_p1 <= full_1_reg_139;
-- in_fifo_V_read assign process. --
in_fifo_V_read_assign_proc : process(in_fifo_V_empty_n, ap_CS_fsm)
begin
if ((((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((in_fifo_V_empty_n = ap_const_logic_0))) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st5_fsm_4 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)))) then
in_fifo_V_read <= ap_const_logic_1;
else
in_fifo_V_read <= ap_const_logic_0;
end if;
end process;
-- out_fifo_V_din assign process. --
out_fifo_V_din_assign_proc : process(out_fifo_V_full_n, ap_CS_fsm, data1_reg_154, tmp_2_fu_115_p1)
begin
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
if ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
out_fifo_V_din <= tmp_2_fu_115_p1;
elsif ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
out_fifo_V_din <= data1_reg_154;
else
out_fifo_V_din <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
out_fifo_V_din <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- out_fifo_V_write assign process. --
out_fifo_V_write_assign_proc : process(out_fifo_V_full_n, ap_CS_fsm)
begin
if ((((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((out_fifo_V_full_n = ap_const_logic_0))) or (not((out_fifo_V_full_n = ap_const_logic_0)) and (ap_ST_st13_fsm_12 = ap_CS_fsm)))) then
out_fifo_V_write <= ap_const_logic_1;
else
out_fifo_V_write <= ap_const_logic_0;
end if;
end process;
ret_fu_97_p1 <= grp_fu_52_p2;
tmp_2_fu_115_p1 <= std_logic_vector(resize(unsigned(data2_reg_159),32));
tmp_4_fu_56_p3 <= (tmp_3_reg_119 & ap_const_lv32_0);
tmp_s_fu_72_p3 <= (tmp_7_reg_129 & ap_const_lv32_0);
end behav;
| apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/vhdl/src/xillydemo.vhd | 2 | 18174 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
| apache-2.0 |
zhlinh/vhdl_course | Exercise/COMPARE/COMPARE.vhd | 1 | 273 | --比较两个二进制数是否相等
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COMPARE IS
PORT(A,B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EQ:OUT STD_LOGIC);
END ENTITY COMPARE;
ARCHITECTURE ART OF COMPARE IS
BEGIN
EQ<='1' WHEN A=B ELSE '0';
END ARCHITECTURE ART; | apache-2.0 |
zhlinh/vhdl_course | Assignment/CHK_3BIT/simulation/modelsim/TB_CHK_3BIT.vhd | 1 | 1158 | LIBRARY IEEE;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
--ENTITY DECLARATION
ENTITY TB_CHK_3BIT IS
END ENTITY TB_CHK_3BIT;
--ARCHITECTURE BODY
ARCHITECTURE TEXTIO_WAY OF TB_CHK_3BIT IS
FILE INTEST : TEXT IS IN "TEST_DATA.TXT";
SIGNAL CLK : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
SIGNAL BIT3 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL DIN : STD_LOGIC;
SIGNAL DOUT : STD_LOGIC;
CONSTANT CLK_CYCLE: TIME :=10 NS;
COMPONENT CHK_3BIT
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
BIT3 :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DIN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
DUT : CHK_3BIT
PORT MAP (
CLK => CLK,
RESET => RESET,
BIT3 => BIT3,
DIN => DIN,
DOUT => DOUT
);
ALWAYS:PROCESS
VARIABLE LI: LINE;
VARIABLE CLK_V, RESET_V, DIN_V: STD_LOGIC;
VARIABLE BIT3_V:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
READLINE(INTEST, LI);
READ(LI, CLK_V);
READ(LI, RESET_V);
READ(LI, BIT3_V);
READ(LI, DIN_V);
CLK<=CLK_V;
RESET<=RESET_V;
BIT3<=BIT3_V;
DIN<=DIN_V;
WAIT FOR CLK_CYCLE/4;
IF (ENDFILE(INTEST)) THEN
WAIT;
END IF;
END PROCESS;
END ARCHITECTURE TEXTIO_WAY; | apache-2.0 |
fkolacek/FIT-VUT | INP1/fpga/sim/ledc8x8_tb.vhd | 4 | 754 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity testbench is
end testbench;
architecture behv of testbench is
component ledc8x8 is
port ( SMCLK, RESET: in std_logic;
ROW, LED: out std_logic_vector(0 to 7)
);
end component;
signal smclk: std_logic := '0';
signal reset: std_logic;
signal row, led: std_logic_vector(0 to 7);
constant period: time := 20 ns;
begin
uut: ledc8x8 port map(smclk, reset, row, led);
smclk <= not smclk after period / 2;
test: process
begin
reset <= '1';
wait until smclk'event and smclk = '1';
reset <= '0';
wait;
end process;
end behv;
| apache-2.0 |
vmax-feihu/hue | tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
hoangt/PoC | tb/common/my_config_ML505.vhdl | 4 | 1763 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| apache-2.0 |
hoangt/PoC | src/common/config.vhdl | 1 | 40254 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- ------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING8 is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING16 is STRING(1 to 16);
subtype T_BOARD_CONFIG_STRING32 is STRING(1 to 32);
-- subtype T_BOARD_CONFIG_STRING64 is STRING(1 to 64);
subtype T_DEVICE_STRING is STRING(1 to 32);
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8;
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16;
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32;
-- constant C_BOARD_CONFIG_STRING64_EMPTY : T_BOARD_CONFIG_STRING64;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
-- List of known boards
-- ---------------------------------------------------------------------------
type T_BOARD is (
BOARD_CUSTOM,
-- Spartan-3 boards
BOARD_S3SK200, BOARD_S3SK1000,
BOARD_S3ESK500, BOARD_S3ESK1600,
-- Spartan-6 boards
BOARD_ATLYS,
-- Kintex-7 boards
BOARD_KC705,
-- Virtex-5 boards
BOARD_ML505,
BOARD_ML506,
BOARD_ML507,
BOARD_XUPV5,
-- Virtex-6 boards
BOARD_ML605,
-- Virtex-7 boards
BOARD_VC707,
BOARD_VC709,
-- Zynq-7000 boards
BOARD_ZEDBOARD,
-- Cyclon III boards
BOARD_DE0,
-- Stratix II boards
BOARD_S2GXAV,
-- Stratix IV boards
BOARD_DE4,
-- Stratix V boards
BOARD_DE5
);
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
subtype vendor_t is T_VENDOR;
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, -- Xilinx.Kintex
DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, -- Altera.Cyclone
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX4, DEVICE_STRATIX5 -- Altera.Stratix
);
subtype device_t is T_DEVICE;
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
-- TODO: add Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
TRANSCEIVER_NONE
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : natural;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING16; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING16; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING16;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING8;
RS_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_Device : T_BOARD_CONFIG_STRING16;
PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING16;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
FPGADevice : T_DEVICE_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (T_BOARD) of T_BOARD_INFO;
-- QUESTION: replace archprops with DEVICE_INFO ?
type archprops_t is record
LUT_K : positive; -- LUT Fanin
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
function ARCH_PROPS return archprops_t;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING;
end package;
package body config is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := '`';
-- deferred constant
-- ===========================================================================
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32 := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
-- chr_is* function
function chr_isDigit(chr : CHARACTER) return boolean is
begin
return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or
((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
variable chr1 : CHARACTER;
variable chr2 : CHARACTER;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
chr1 := str1(i);
chr2 := str2(str2'low + (i - str1'low ));
if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (chr1 /= chr2) then
return FALSE;
elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then
return FALSE;
elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function getLocalDeviceString(DeviceString : STRING) return STRING is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : STRING := BOARD_DEVICE;
variable Result : STRING(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if (POC_VERBOSE = TRUE) then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function conf(str : string; Size : POSITIVE) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to Size);
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
function imin(arg1 : integer; arg2 : integer) return integer is begin
if arg1 < arg2 then return arg1; else return arg2; end if;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is begin
if arg1 > arg2 then return arg1; else return arg2; end if;
end function;
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL);
end if;
return Result;
end function;
function conf8(str : string) return T_BOARD_CONFIG_STRING8 is
begin
return conf(str, 8);
end function;
function conf16(str : string) return T_BOARD_CONFIG_STRING16 is
begin
return conf(str, 16);
end function;
function conf32(str : string) return T_BOARD_CONFIG_STRING32 is
begin
return conf(str, 32);
end function;
-- function conf64(str : string) return T_BOARD_CONFIG_STRING64 is
-- begin
-- return conf(str, 64);
-- end function;
function extractFirstNumber(str : STRING) return NATURAL is
variable low : integer;
variable high : integer;
variable Result : NATURAL;
variable Digit : INTEGER;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if (low = -1) then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if (high = -1) then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if (chr_isDigit(str(i)) = FALSE) then
return -1;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- predefined UART descriptions
function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf16(FlowControl);
Result.BaudRate := conf16(BaudRate);
Result.BaudRate_Max := ite((BaudRate_Max = ""), conf16(BaudRate), conf16(BaudRate_Max));
return Result;
end function;
-- IsDTE FlowControl BaudRate
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf8(IPStyle);
Result.RS_DataInterface := conf8(RS_DataInt);
Result.PHY_Device := conf16(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf8(PHY_DataInt);
Result.PHY_ManagementInterface := conf16(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- board description
-- ===========================================================================
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
-- Xilinx boards
-- =========================================================================
BOARD_S3SK200 => (
FPGADevice => conf32("XC3S200FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3SK1000 => (
FPGADevice => conf32("XC3S1000FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK500 => (
FPGADevice => conf32("XC3S500EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK1600 => (
FPGADevice => conf32("XC3S1600EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_ATLYS => (
FPGADevice => conf32("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_KC705 => (
FPGADevice => conf32("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML505 => (
FPGADevice => conf32("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML506 => (
FPGADevice => conf32("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML507 => (
FPGADevice => conf32("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_XUPV5 => (
FPGADevice => conf32("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML605 => (
FPGADevice => conf32("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_VC707 => (
FPGADevice => conf32("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_VC709 => (
FPGADevice => conf32("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_ZEDBOARD => (
FPGADevice => conf32("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Altera boards
-- =========================================================================
BOARD_DE0 => (
FPGADevice => conf32("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S2GXAV => (
FPGADevice => conf32("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_DE4 => (
FPGADevice => conf32("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),
BOARD_DE5 => (
FPGADevice => conf32("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- custom board / dummy entry
BOARD_CUSTOM => (
FPGADevice => conf32("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD is
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant MY_BRD : T_BOARD_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig, T_BOARD_STRING'length), conf(MY_BOARD, T_BOARD_STRING'length));
begin
if (POC_VERBOSE = TRUE) then
report "PoC configuration: Used board is '" & str_trim(MY_BRD) & "'" severity NOTE;
end if;
for i in T_BOARD loop
if str_imatch(T_BOARD'image(i), "BOARD_" & str_trim(MY_BRD)) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return BOARD_CUSTOM;
end function;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR : string(1 to 2) := MY_DEV(1 to 2);
begin
case VEN_STR is
when "XC" => return VENDOR_XILINX;
when "EP" => return VENDOR_ALTERA;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4);
begin
case VEN is
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 => return 7; -- all Xilinx ****7 devices share some common features: e.g. XADC
when others => return 0;
end case;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return t_device_subtype is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- work around for GHDL
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return DEVICE_SUBTYPE_NONE; -- Altera Cyclon I, II, III devices have no subtype
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 => report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when others => report "Transceiver type is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_ARTIX7 => return 6;
when DEVICE_KINTEX7 => return 6;
when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 | DEVICE_VIRTEX7 => return 6;
when DEVICE_ZYNQ7 => return 6;
when others => report "LUT fan-in is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : t_device_subtype := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
when others => report "Unknown device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
function ARCH_PROPS return archprops_t is
variable result : archprops_t;
begin
result.LUT_K := LUT_FANIN;
return result;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING is
begin
if (debug = true) then
return "gray";
else
case VENDOR is
when VENDOR_XILINX => return "auto";
when VENDOR_ALTERA => return "default";
when others => report "Unknown vendor." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end if;
end function;
end package body;
| apache-2.0 |
hoangt/PoC | src/misc/sync/sync_Bits_Altera.vhdl | 2 | 3365 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
-- Description:
-- ------------------------------------
-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs.
-- It generates 2 flip flops per input bit and notifies Quartus II, that these
-- flip flops are synchronizer flip flops. If you need a platform independent
-- version of this synchronizer, please use 'PoC.misc.sync.sync_Flag', which
-- internally instantiates this module if a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bits_Altera is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data
);
end entity;
architecture rtl of sync_Bits_Altera is
attribute PRESERVE : BOOLEAN;
attribute ALTERA_ATTRIBUTE : STRING;
-- Apply a SDC constraint to meta stable flip flop
attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin
gen : for i in 0 to BITS - 1 generate
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := INIT(i);
signal Data_sync : STD_LOGIC := INIT(i);
-- preserve both registers (no optimization, shift register extraction, ...)
attribute PRESERVE of Data_meta : signal is TRUE;
attribute PRESERVE of Data_sync : signal is TRUE;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
begin
Data_async <= Input(i);
process(Clock)
begin
if rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output(i) <= Data_sync;
end generate;
end architecture;
| apache-2.0 |
hoangt/PoC | src/common/vectors.vhdl | 4 | 29645 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
package vectors is
-- ==========================================================================
-- Type declarations
-- ==========================================================================
-- STD_LOGIC_VECTORs
subtype T_SLV_2 is STD_LOGIC_VECTOR(1 downto 0);
subtype T_SLV_3 is STD_LOGIC_VECTOR(2 downto 0);
subtype T_SLV_4 is STD_LOGIC_VECTOR(3 downto 0);
subtype T_SLV_8 is STD_LOGIC_VECTOR(7 downto 0);
subtype T_SLV_12 is STD_LOGIC_VECTOR(11 downto 0);
subtype T_SLV_16 is STD_LOGIC_VECTOR(15 downto 0);
subtype T_SLV_24 is STD_LOGIC_VECTOR(23 downto 0);
subtype T_SLV_32 is STD_LOGIC_VECTOR(31 downto 0);
subtype T_SLV_48 is STD_LOGIC_VECTOR(47 downto 0);
subtype T_SLV_64 is STD_LOGIC_VECTOR(63 downto 0);
subtype T_SLV_96 is STD_LOGIC_VECTOR(95 downto 0);
subtype T_SLV_128 is STD_LOGIC_VECTOR(127 downto 0);
subtype T_SLV_256 is STD_LOGIC_VECTOR(255 downto 0);
subtype T_SLV_512 is STD_LOGIC_VECTOR(511 downto 0);
-- STD_LOGIC_VECTOR_VECTORs
-- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
type T_SLVV_2 is array(NATURAL range <>) of T_SLV_2;
type T_SLVV_3 is array(NATURAL range <>) of T_SLV_3;
type T_SLVV_4 is array(NATURAL range <>) of T_SLV_4;
type T_SLVV_8 is array(NATURAL range <>) of T_SLV_8;
type T_SLVV_12 is array(NATURAL range <>) of T_SLV_12;
type T_SLVV_16 is array(NATURAL range <>) of T_SLV_16;
type T_SLVV_24 is array(NATURAL range <>) of T_SLV_24;
type T_SLVV_32 is array(NATURAL range <>) of T_SLV_32;
type T_SLVV_48 is array(NATURAL range <>) of T_SLV_48;
type T_SLVV_64 is array(NATURAL range <>) of T_SLV_64;
type T_SLVV_128 is array(NATURAL range <>) of T_SLV_128;
type T_SLVV_256 is array(NATURAL range <>) of T_SLV_256;
type T_SLVV_512 is array(NATURAL range <>) of T_SLV_512;
-- STD_LOGIC_MATRIXs
type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM work-around: DON'T use myMatrix'range(n) for n >= 2
-- because: myMatrix'range(2) returns always myMatrix'range(1); tested with ISE/iSIM 14.2
-- USAGE NOTES:
-- dimmension 1 => rows - e.g. Words
-- dimmension 2 => columns - e.g. Bits/Bytes in a word
-- ==========================================================================
-- Function declarations
-- ==========================================================================
-- slicing boundary calulations
function low (lenvec : T_POSVEC; index : NATURAL) return NATURAL;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL;
-- Assign procedures: assign_*
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL); -- assign vector to complete row
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL); -- assign short vector to row starting at position
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL); -- assign short vector to row in range high:low
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL); -- assign vector to complete column
-- ATTENTION: see T_SLM definition for further details and work-arounds
-- Matrix to matrix conversion: slm_slice*
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
-- Matrix to vector conversion: get_*
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix column
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR; -- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR; -- get a sub vector of a matrix row at high:low
-- Convert to vector: to_slv
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR; -- convert vector-vector to flatten vector
-- Convert flat vector to avector-vector: to_slvv_*
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4; --
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8; --
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12; --
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16; --
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32; --
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64; --
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128; --
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256; --
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512; --
-- Convert matrix to avector-vector: to_slvv_*
function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
-- Convert vector-vector to matrix: to_slm
function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
-- Change vector direction
function dir(slvv : T_SLVV_8) return T_SLVV_8;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4;
function rev(slvv : T_SLVV_8) return T_SLVV_8;
function rev(slvv : T_SLVV_12) return T_SLVV_12;
function rev(slvv : T_SLVV_16) return T_SLVV_16;
function rev(slvv : T_SLVV_32) return T_SLVV_32;
function rev(slvv : T_SLVV_64) return T_SLVV_64;
function rev(slvv : T_SLVV_128) return T_SLVV_128;
function rev(slvv : T_SLVV_256) return T_SLVV_256;
function rev(slvv : T_SLVV_512) return T_SLVV_512;
-- TODO:
function resize(slm : T_SLM; size : POSITIVE) return T_SLM;
-- to_string
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING;
end package vectors;
package body vectors is
-- slicing boundary calulations
-- ==========================================================================
function low(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index - 1 loop
pos := pos + lenvec(i);
end loop;
return pos;
end function;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index loop
pos := pos + lenvec(i);
end loop;
return pos - 1;
end function;
-- Assign procedures: assign_*
-- ==========================================================================
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL) is
variable temp : STD_LOGIC_VECTOR(Position + slv'length - 1 downto Position);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL) is
variable temp : STD_LOGIC_VECTOR(High downto Low);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'range(1));
begin
temp := slv;
for i in temp'range loop
slm(i, ColIndex) <= temp(i);
end loop;
end procedure;
-- Matrix to matrix conversion: slm_slice*
-- ==========================================================================
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM is
variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to Height - 1 loop
for j in 0 to Width - 1 loop
Result(i, j) := slm(RowIndex + i, ColIndex + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
variable Result : T_SLM(slm'range(1), High - Low downto 0) := (others => (others => '0'));
begin
for i in slm'range(1) loop
for j in 0 to High - Low loop
Result(i, j) := slm(i, low + j);
end loop;
end loop;
return Result;
end function;
-- Matrix to vector conversion: get_*
-- ==========================================================================
-- get a matrix column
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR is
begin
return get_row(slm, RowIndex, (Length - 1), 0);
end function;
-- get a sub vector of a matrix row at high:low
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(High downto Low); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 8) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 8) + 7 downto (i * 8)) := slvv(i);
end loop;
return slv;
end function;
-- Convert flat vector to a vector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from vector (4 bit)
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4 is
variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
begin
if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 4) + 3 downto (i * 4));
end loop;
return Result;
end function;
-- create vector-vector from vector (8 bit)
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8 is
variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
begin
if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 8) + 7 downto (i * 8));
end loop;
return Result;
end function;
-- create vector-vector from vector (12 bit)
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12 is
variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
begin
if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 12) + 11 downto (i * 12));
end loop;
return Result;
end function;
-- create vector-vector from vector (16 bit)
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16 is
variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
begin
if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 16) + 15 downto (i * 16));
end loop;
return Result;
end function;
-- create vector-vector from vector (32 bit)
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32 is
variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
begin
if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 32) + 31 downto (i * 32));
end loop;
return Result;
end function;
-- create vector-vector from vector (64 bit)
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64 is
variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
begin
if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 64) + 63 downto (i * 64));
end loop;
return Result;
end function;
-- create vector-vector from vector (128 bit)
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128 is
variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
begin
if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 128) + 127 downto (i * 128));
end loop;
return Result;
end function;
-- create vector-vector from vector (256 bit)
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256 is
variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
begin
if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 256) + 255 downto (i * 256));
end loop;
return Result;
end function;
-- create vector-vector from vector (512 bit)
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512 is
variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
begin
if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 512) + 511 downto (i * 512));
end loop;
return Result;
end function;
-- Convert matrix to avector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from matrix (4 bit)
function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
variable Result : T_SLVV_4(slm'range(1));
begin
if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (8 bit)
function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
variable Result : T_SLVV_8(slm'range(1));
begin
if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (12 bit)
function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
variable Result : T_SLVV_12(slm'range(1));
begin
if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (16 bit)
function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
variable Result : T_SLVV_16(slm'range(1));
begin
if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (32 bit)
function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
variable Result : T_SLVV_32(slm'range(1));
begin
if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (64 bit)
function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
variable Result : T_SLVV_64(slm'range(1));
begin
if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (128 bit)
function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
variable Result : T_SLVV_128(slm'range(1));
begin
if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (256 bit)
function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
variable Result : T_SLVV_256(slm'range);
begin
if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (512 bit)
function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
variable Result : T_SLVV_512(slm'range(1));
begin
if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- Convert vector-vector to matrix: to_slm
-- ==========================================================================
-- create matrix from vector-vector
function to_slm(slvv : T_SLVV_4) return T_SLM is
variable slm : T_SLM(slvv'range, 3 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_4'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_8) return T_SLM is
-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimmension 2
variable slm : T_SLM(slvv'range, 7 downto 0);
begin
-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
for i in slvv'range loop
for j in T_SLV_8'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_12) return T_SLM is
variable slm : T_SLM(slvv'range, 11 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_12'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_16) return T_SLM is
variable slm : T_SLM(slvv'range, 15 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_16'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_32) return T_SLM is
variable slm : T_SLM(slvv'range, 31 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_32'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_48) return T_SLM is
variable slm : T_SLM(slvv'range, 47 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_48'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_64) return T_SLM is
variable slm : T_SLM(slvv'range, 63 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_64'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_128) return T_SLM is
variable slm : T_SLM(slvv'range, 127 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_128'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_256) return T_SLM is
variable slm : T_SLM(slvv'range, 255 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_256'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_512) return T_SLM is
variable slm : T_SLM(slvv'range, 511 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_512'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
-- Change vector direction
-- ==========================================================================
function dir(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'reverse_range);
begin
Result := slvv;
return Result;
end function;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4 is
variable Result : T_SLVV_4(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_12) return T_SLVV_12 is
variable Result : T_SLVV_12(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_16) return T_SLVV_16 is
variable Result : T_SLVV_16(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_32) return T_SLVV_32 is
variable Result : T_SLVV_32(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_64) return T_SLVV_64 is
variable Result : T_SLVV_64(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_128) return T_SLVV_128 is
variable Result : T_SLVV_128(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_256) return T_SLVV_256 is
variable Result : T_SLVV_256(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_512) return T_SLVV_512 is
variable Result : T_SLVV_512(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
-- Resize functions
-- ==========================================================================
-- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
-- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
-- value-preserving resizes of the signed and unsigned data types.
function resize(slm : T_SLM; size : POSITIVE) return T_SLM is
variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0'));
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i, j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING is
constant hex_len : POSITIVE := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
variable Result : STRING(1 to hex_len) := (others => sep);
variable pos : POSITIVE := 1;
begin
for i in slvv'range loop
Result(pos to pos + 1) := to_string(slvv(i), 'h');
pos := pos + ite((sep = C_POC_NUL), 2, 3);
end loop;
return Result;
end function;
end package body;
| apache-2.0 |
kevintownsend/convey_spmv | rtl/mac/FPMultiplier_11_52_11_52_11_52_uid2.vhdl | 1 | 206136 | -- flopoco multiplier pipeline: 11 clock cycles
--TODO: verilog instantiation
--------------------------------------------------------------------------------
-- IntAdder_42_f400_uid11
-- (IntAdderClassical_42_f400_uid13)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_42_f400_uid11 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(41 downto 0);
Y : in std_logic_vector(41 downto 0);
Cin : in std_logic;
R : out std_logic_vector(41 downto 0) );
end entity;
architecture arch of IntAdder_42_f400_uid11 is
signal X_d1 : std_logic_vector(41 downto 0);
signal Y_d1 : std_logic_vector(41 downto 0);
signal Cin_d1 : std_logic;
begin
process(clk)
begin
if clk'event and clk = '1' then
X_d1 <= X;
Y_d1 <= Y;
Cin_d1 <= Cin;
end if;
end process;
--Classical
----------------Synchro barrier, entering cycle 1----------------
R <= X_d1 + Y_d1 + Cin_d1;
end architecture;
--------------------------------------------------------------------------------
-- IntMultiAdder_42_op4_f400_uid7
-- (IntCompressorTree_42_4_uid9)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca (2009-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntMultiAdder_42_op4_f400_uid7 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(41 downto 0);
X1 : in std_logic_vector(41 downto 0);
X2 : in std_logic_vector(41 downto 0);
X3 : in std_logic_vector(41 downto 0);
R : out std_logic_vector(41 downto 0) );
end entity;
architecture arch of IntMultiAdder_42_op4_f400_uid7 is
component IntAdder_42_f400_uid11 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(41 downto 0);
Y : in std_logic_vector(41 downto 0);
Cin : in std_logic;
R : out std_logic_vector(41 downto 0) );
end component;
signal l_0_s_0, l_0_s_0_d1 : std_logic_vector(41 downto 0);
signal l_0_s_1, l_0_s_1_d1 : std_logic_vector(41 downto 0);
signal l_0_s_2, l_0_s_2_d1 : std_logic_vector(41 downto 0);
signal l_0_s_3, l_0_s_3_d1 : std_logic_vector(41 downto 0);
signal sell_1_c_0_cl_0 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_0 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_1 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_1 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_2 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_2 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_3 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_3 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_4 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_4 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_5 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_5 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_6 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_6 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_7 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_7 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_8 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_8 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_9 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_9 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_10 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_10 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_11 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_11 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_12 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_12 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_13 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_13 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_14 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_14 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_15 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_15 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_16 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_16 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_17 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_17 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_18 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_18 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_19 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_19 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_20 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_20 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_21 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_21 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_22 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_22 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_23 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_23 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_24 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_24 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_25 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_25 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_26 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_26 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_27 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_27 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_28 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_28 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_29 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_29 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_30 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_30 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_31 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_31 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_32 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_32 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_33 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_33 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_34 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_34 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_35 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_35 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_36 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_36 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_37 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_37 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_38 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_38 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_39 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_39 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_40 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_40 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_41 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_1_s_0 : std_logic_vector(41 downto 0);
signal l_1_s_1 : std_logic_vector(41 downto 0);
signal l_1_s_2 : std_logic_vector(41 downto 0);
signal sell_2_c_0_cl_0 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_0 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_1 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_1 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_2 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_2 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_3 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_3 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_4 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_4 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_5 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_5 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_6 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_6 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_7 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_7 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_8 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_8 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_9 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_9 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_10 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_10 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_11 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_11 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_12 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_12 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_13 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_13 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_14 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_14 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_15 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_15 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_16 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_16 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_17 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_17 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_18 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_18 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_19 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_19 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_20 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_20 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_21 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_21 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_22 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_22 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_23 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_23 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_24 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_24 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_25 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_25 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_26 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_26 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_27 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_27 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_28 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_28 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_29 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_29 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_30 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_30 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_31 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_31 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_32 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_32 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_33 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_33 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_34 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_34 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_35 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_35 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_36 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_36 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_37 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_37 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_38 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_38 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_39 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_39 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_40 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_40 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_41 : std_logic_vector(1 downto 0);
signal l_2_s_0 : std_logic_vector(41 downto 0);
signal l_2_s_1 : std_logic_vector(41 downto 0);
signal myR : std_logic_vector(41 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
l_0_s_0_d1 <= l_0_s_0;
l_0_s_1_d1 <= l_0_s_1;
l_0_s_2_d1 <= l_0_s_2;
l_0_s_3_d1 <= l_0_s_3;
end if;
end process;
l_0_s_0 <= X0;
l_0_s_1 <= X1;
l_0_s_2 <= X2;
l_0_s_3 <= X3;
----------------Synchro barrier, entering cycle 1----------------
sell_1_c_0_cl_0 <= l_0_s_0_d1(0) & l_0_s_1_d1(0) & l_0_s_2_d1(0) & l_0_s_3_d1(0);
with sell_1_c_0_cl_0 select
l_1_c_0_cl_0 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_1 <= l_0_s_0_d1(1) & l_0_s_1_d1(1) & l_0_s_2_d1(1) & l_0_s_3_d1(1);
with sell_1_c_0_cl_1 select
l_1_c_0_cl_1 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_2 <= l_0_s_0_d1(2) & l_0_s_1_d1(2) & l_0_s_2_d1(2) & l_0_s_3_d1(2);
with sell_1_c_0_cl_2 select
l_1_c_0_cl_2 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_3 <= l_0_s_0_d1(3) & l_0_s_1_d1(3) & l_0_s_2_d1(3) & l_0_s_3_d1(3);
with sell_1_c_0_cl_3 select
l_1_c_0_cl_3 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_4 <= l_0_s_0_d1(4) & l_0_s_1_d1(4) & l_0_s_2_d1(4) & l_0_s_3_d1(4);
with sell_1_c_0_cl_4 select
l_1_c_0_cl_4 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_5 <= l_0_s_0_d1(5) & l_0_s_1_d1(5) & l_0_s_2_d1(5) & l_0_s_3_d1(5);
with sell_1_c_0_cl_5 select
l_1_c_0_cl_5 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_6 <= l_0_s_0_d1(6) & l_0_s_1_d1(6) & l_0_s_2_d1(6) & l_0_s_3_d1(6);
with sell_1_c_0_cl_6 select
l_1_c_0_cl_6 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_7 <= l_0_s_0_d1(7) & l_0_s_1_d1(7) & l_0_s_2_d1(7) & l_0_s_3_d1(7);
with sell_1_c_0_cl_7 select
l_1_c_0_cl_7 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_8 <= l_0_s_0_d1(8) & l_0_s_1_d1(8) & l_0_s_2_d1(8) & l_0_s_3_d1(8);
with sell_1_c_0_cl_8 select
l_1_c_0_cl_8 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_9 <= l_0_s_0_d1(9) & l_0_s_1_d1(9) & l_0_s_2_d1(9) & l_0_s_3_d1(9);
with sell_1_c_0_cl_9 select
l_1_c_0_cl_9 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_10 <= l_0_s_0_d1(10) & l_0_s_1_d1(10) & l_0_s_2_d1(10) & l_0_s_3_d1(10);
with sell_1_c_0_cl_10 select
l_1_c_0_cl_10 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_11 <= l_0_s_0_d1(11) & l_0_s_1_d1(11) & l_0_s_2_d1(11) & l_0_s_3_d1(11);
with sell_1_c_0_cl_11 select
l_1_c_0_cl_11 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_12 <= l_0_s_0_d1(12) & l_0_s_1_d1(12) & l_0_s_2_d1(12) & l_0_s_3_d1(12);
with sell_1_c_0_cl_12 select
l_1_c_0_cl_12 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_13 <= l_0_s_0_d1(13) & l_0_s_1_d1(13) & l_0_s_2_d1(13) & l_0_s_3_d1(13);
with sell_1_c_0_cl_13 select
l_1_c_0_cl_13 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_14 <= l_0_s_0_d1(14) & l_0_s_1_d1(14) & l_0_s_2_d1(14) & l_0_s_3_d1(14);
with sell_1_c_0_cl_14 select
l_1_c_0_cl_14 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_15 <= l_0_s_0_d1(15) & l_0_s_1_d1(15) & l_0_s_2_d1(15) & l_0_s_3_d1(15);
with sell_1_c_0_cl_15 select
l_1_c_0_cl_15 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_16 <= l_0_s_0_d1(16) & l_0_s_1_d1(16) & l_0_s_2_d1(16) & l_0_s_3_d1(16);
with sell_1_c_0_cl_16 select
l_1_c_0_cl_16 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_17 <= l_0_s_0_d1(17) & l_0_s_1_d1(17) & l_0_s_2_d1(17) & l_0_s_3_d1(17);
with sell_1_c_0_cl_17 select
l_1_c_0_cl_17 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_18 <= l_0_s_0_d1(18) & l_0_s_1_d1(18) & l_0_s_2_d1(18) & l_0_s_3_d1(18);
with sell_1_c_0_cl_18 select
l_1_c_0_cl_18 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_19 <= l_0_s_0_d1(19) & l_0_s_1_d1(19) & l_0_s_2_d1(19) & l_0_s_3_d1(19);
with sell_1_c_0_cl_19 select
l_1_c_0_cl_19 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_20 <= l_0_s_0_d1(20) & l_0_s_1_d1(20) & l_0_s_2_d1(20) & l_0_s_3_d1(20);
with sell_1_c_0_cl_20 select
l_1_c_0_cl_20 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_21 <= l_0_s_0_d1(21) & l_0_s_1_d1(21) & l_0_s_2_d1(21) & l_0_s_3_d1(21);
with sell_1_c_0_cl_21 select
l_1_c_0_cl_21 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_22 <= l_0_s_0_d1(22) & l_0_s_1_d1(22) & l_0_s_2_d1(22) & l_0_s_3_d1(22);
with sell_1_c_0_cl_22 select
l_1_c_0_cl_22 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_23 <= l_0_s_0_d1(23) & l_0_s_1_d1(23) & l_0_s_2_d1(23) & l_0_s_3_d1(23);
with sell_1_c_0_cl_23 select
l_1_c_0_cl_23 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_24 <= l_0_s_0_d1(24) & l_0_s_1_d1(24) & l_0_s_2_d1(24) & l_0_s_3_d1(24);
with sell_1_c_0_cl_24 select
l_1_c_0_cl_24 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_25 <= l_0_s_0_d1(25) & l_0_s_1_d1(25) & l_0_s_2_d1(25) & l_0_s_3_d1(25);
with sell_1_c_0_cl_25 select
l_1_c_0_cl_25 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_26 <= l_0_s_0_d1(26) & l_0_s_1_d1(26) & l_0_s_2_d1(26) & l_0_s_3_d1(26);
with sell_1_c_0_cl_26 select
l_1_c_0_cl_26 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_27 <= l_0_s_0_d1(27) & l_0_s_1_d1(27) & l_0_s_2_d1(27) & l_0_s_3_d1(27);
with sell_1_c_0_cl_27 select
l_1_c_0_cl_27 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_28 <= l_0_s_0_d1(28) & l_0_s_1_d1(28) & l_0_s_2_d1(28) & l_0_s_3_d1(28);
with sell_1_c_0_cl_28 select
l_1_c_0_cl_28 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_29 <= l_0_s_0_d1(29) & l_0_s_1_d1(29) & l_0_s_2_d1(29) & l_0_s_3_d1(29);
with sell_1_c_0_cl_29 select
l_1_c_0_cl_29 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_30 <= l_0_s_0_d1(30) & l_0_s_1_d1(30) & l_0_s_2_d1(30) & l_0_s_3_d1(30);
with sell_1_c_0_cl_30 select
l_1_c_0_cl_30 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_31 <= l_0_s_0_d1(31) & l_0_s_1_d1(31) & l_0_s_2_d1(31) & l_0_s_3_d1(31);
with sell_1_c_0_cl_31 select
l_1_c_0_cl_31 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_32 <= l_0_s_0_d1(32) & l_0_s_1_d1(32) & l_0_s_2_d1(32) & l_0_s_3_d1(32);
with sell_1_c_0_cl_32 select
l_1_c_0_cl_32 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_33 <= l_0_s_0_d1(33) & l_0_s_1_d1(33) & l_0_s_2_d1(33) & l_0_s_3_d1(33);
with sell_1_c_0_cl_33 select
l_1_c_0_cl_33 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_34 <= l_0_s_0_d1(34) & l_0_s_1_d1(34) & l_0_s_2_d1(34) & l_0_s_3_d1(34);
with sell_1_c_0_cl_34 select
l_1_c_0_cl_34 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_35 <= l_0_s_0_d1(35) & l_0_s_1_d1(35) & l_0_s_2_d1(35) & l_0_s_3_d1(35);
with sell_1_c_0_cl_35 select
l_1_c_0_cl_35 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_36 <= l_0_s_0_d1(36) & l_0_s_1_d1(36) & l_0_s_2_d1(36) & l_0_s_3_d1(36);
with sell_1_c_0_cl_36 select
l_1_c_0_cl_36 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_37 <= l_0_s_0_d1(37) & l_0_s_1_d1(37) & l_0_s_2_d1(37) & l_0_s_3_d1(37);
with sell_1_c_0_cl_37 select
l_1_c_0_cl_37 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_38 <= l_0_s_0_d1(38) & l_0_s_1_d1(38) & l_0_s_2_d1(38) & l_0_s_3_d1(38);
with sell_1_c_0_cl_38 select
l_1_c_0_cl_38 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_39 <= l_0_s_0_d1(39) & l_0_s_1_d1(39) & l_0_s_2_d1(39) & l_0_s_3_d1(39);
with sell_1_c_0_cl_39 select
l_1_c_0_cl_39 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_40 <= l_0_s_0_d1(40) & l_0_s_1_d1(40) & l_0_s_2_d1(40) & l_0_s_3_d1(40);
with sell_1_c_0_cl_40 select
l_1_c_0_cl_40 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_41 <= l_0_s_0_d1(41) & l_0_s_1_d1(41) & l_0_s_2_d1(41) & l_0_s_3_d1(41);
with sell_1_c_0_cl_41 select
l_1_c_0_cl_41 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
l_1_s_0 <= l_1_c_0_cl_41(0 downto 0) & l_1_c_0_cl_40(0 downto 0) & l_1_c_0_cl_39(0 downto 0) & l_1_c_0_cl_38(0 downto 0) & l_1_c_0_cl_37(0 downto 0) & l_1_c_0_cl_36(0 downto 0) & l_1_c_0_cl_35(0 downto 0) & l_1_c_0_cl_34(0 downto 0) & l_1_c_0_cl_33(0 downto 0) & l_1_c_0_cl_32(0 downto 0) & l_1_c_0_cl_31(0 downto 0) & l_1_c_0_cl_30(0 downto 0) & l_1_c_0_cl_29(0 downto 0) & l_1_c_0_cl_28(0 downto 0) & l_1_c_0_cl_27(0 downto 0) & l_1_c_0_cl_26(0 downto 0) & l_1_c_0_cl_25(0 downto 0) & l_1_c_0_cl_24(0 downto 0) & l_1_c_0_cl_23(0 downto 0) & l_1_c_0_cl_22(0 downto 0) & l_1_c_0_cl_21(0 downto 0) & l_1_c_0_cl_20(0 downto 0) & l_1_c_0_cl_19(0 downto 0) & l_1_c_0_cl_18(0 downto 0) & l_1_c_0_cl_17(0 downto 0) & l_1_c_0_cl_16(0 downto 0) & l_1_c_0_cl_15(0 downto 0) & l_1_c_0_cl_14(0 downto 0) & l_1_c_0_cl_13(0 downto 0) & l_1_c_0_cl_12(0 downto 0) & l_1_c_0_cl_11(0 downto 0) & l_1_c_0_cl_10(0 downto 0) & l_1_c_0_cl_9(0 downto 0) & l_1_c_0_cl_8(0 downto 0) & l_1_c_0_cl_7(0 downto 0) & l_1_c_0_cl_6(0 downto 0) & l_1_c_0_cl_5(0 downto 0) & l_1_c_0_cl_4(0 downto 0) & l_1_c_0_cl_3(0 downto 0) & l_1_c_0_cl_2(0 downto 0) & l_1_c_0_cl_1(0 downto 0) & l_1_c_0_cl_0(0 downto 0);
l_1_s_1 <= l_1_c_0_cl_40(1 downto 1) & l_1_c_0_cl_39(1 downto 1) & l_1_c_0_cl_38(1 downto 1) & l_1_c_0_cl_37(1 downto 1) & l_1_c_0_cl_36(1 downto 1) & l_1_c_0_cl_35(1 downto 1) & l_1_c_0_cl_34(1 downto 1) & l_1_c_0_cl_33(1 downto 1) & l_1_c_0_cl_32(1 downto 1) & l_1_c_0_cl_31(1 downto 1) & l_1_c_0_cl_30(1 downto 1) & l_1_c_0_cl_29(1 downto 1) & l_1_c_0_cl_28(1 downto 1) & l_1_c_0_cl_27(1 downto 1) & l_1_c_0_cl_26(1 downto 1) & l_1_c_0_cl_25(1 downto 1) & l_1_c_0_cl_24(1 downto 1) & l_1_c_0_cl_23(1 downto 1) & l_1_c_0_cl_22(1 downto 1) & l_1_c_0_cl_21(1 downto 1) & l_1_c_0_cl_20(1 downto 1) & l_1_c_0_cl_19(1 downto 1) & l_1_c_0_cl_18(1 downto 1) & l_1_c_0_cl_17(1 downto 1) & l_1_c_0_cl_16(1 downto 1) & l_1_c_0_cl_15(1 downto 1) & l_1_c_0_cl_14(1 downto 1) & l_1_c_0_cl_13(1 downto 1) & l_1_c_0_cl_12(1 downto 1) & l_1_c_0_cl_11(1 downto 1) & l_1_c_0_cl_10(1 downto 1) & l_1_c_0_cl_9(1 downto 1) & l_1_c_0_cl_8(1 downto 1) & l_1_c_0_cl_7(1 downto 1) & l_1_c_0_cl_6(1 downto 1) & l_1_c_0_cl_5(1 downto 1) & l_1_c_0_cl_4(1 downto 1) & l_1_c_0_cl_3(1 downto 1) & l_1_c_0_cl_2(1 downto 1) & l_1_c_0_cl_1(1 downto 1) & l_1_c_0_cl_0(1 downto 1) & "0";
l_1_s_2 <= l_1_c_0_cl_39(2 downto 2) & l_1_c_0_cl_38(2 downto 2) & l_1_c_0_cl_37(2 downto 2) & l_1_c_0_cl_36(2 downto 2) & l_1_c_0_cl_35(2 downto 2) & l_1_c_0_cl_34(2 downto 2) & l_1_c_0_cl_33(2 downto 2) & l_1_c_0_cl_32(2 downto 2) & l_1_c_0_cl_31(2 downto 2) & l_1_c_0_cl_30(2 downto 2) & l_1_c_0_cl_29(2 downto 2) & l_1_c_0_cl_28(2 downto 2) & l_1_c_0_cl_27(2 downto 2) & l_1_c_0_cl_26(2 downto 2) & l_1_c_0_cl_25(2 downto 2) & l_1_c_0_cl_24(2 downto 2) & l_1_c_0_cl_23(2 downto 2) & l_1_c_0_cl_22(2 downto 2) & l_1_c_0_cl_21(2 downto 2) & l_1_c_0_cl_20(2 downto 2) & l_1_c_0_cl_19(2 downto 2) & l_1_c_0_cl_18(2 downto 2) & l_1_c_0_cl_17(2 downto 2) & l_1_c_0_cl_16(2 downto 2) & l_1_c_0_cl_15(2 downto 2) & l_1_c_0_cl_14(2 downto 2) & l_1_c_0_cl_13(2 downto 2) & l_1_c_0_cl_12(2 downto 2) & l_1_c_0_cl_11(2 downto 2) & l_1_c_0_cl_10(2 downto 2) & l_1_c_0_cl_9(2 downto 2) & l_1_c_0_cl_8(2 downto 2) & l_1_c_0_cl_7(2 downto 2) & l_1_c_0_cl_6(2 downto 2) & l_1_c_0_cl_5(2 downto 2) & l_1_c_0_cl_4(2 downto 2) & l_1_c_0_cl_3(2 downto 2) & l_1_c_0_cl_2(2 downto 2) & l_1_c_0_cl_1(2 downto 2) & l_1_c_0_cl_0(2 downto 2) & "00";
sell_2_c_0_cl_0 <= l_1_s_0(0) & l_1_s_1(0) & l_1_s_2(0);
with sell_2_c_0_cl_0 select
l_2_c_0_cl_0 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_1 <= l_1_s_0(1) & l_1_s_1(1) & l_1_s_2(1);
with sell_2_c_0_cl_1 select
l_2_c_0_cl_1 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_2 <= l_1_s_0(2) & l_1_s_1(2) & l_1_s_2(2);
with sell_2_c_0_cl_2 select
l_2_c_0_cl_2 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_3 <= l_1_s_0(3) & l_1_s_1(3) & l_1_s_2(3);
with sell_2_c_0_cl_3 select
l_2_c_0_cl_3 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_4 <= l_1_s_0(4) & l_1_s_1(4) & l_1_s_2(4);
with sell_2_c_0_cl_4 select
l_2_c_0_cl_4 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_5 <= l_1_s_0(5) & l_1_s_1(5) & l_1_s_2(5);
with sell_2_c_0_cl_5 select
l_2_c_0_cl_5 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_6 <= l_1_s_0(6) & l_1_s_1(6) & l_1_s_2(6);
with sell_2_c_0_cl_6 select
l_2_c_0_cl_6 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_7 <= l_1_s_0(7) & l_1_s_1(7) & l_1_s_2(7);
with sell_2_c_0_cl_7 select
l_2_c_0_cl_7 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_8 <= l_1_s_0(8) & l_1_s_1(8) & l_1_s_2(8);
with sell_2_c_0_cl_8 select
l_2_c_0_cl_8 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_9 <= l_1_s_0(9) & l_1_s_1(9) & l_1_s_2(9);
with sell_2_c_0_cl_9 select
l_2_c_0_cl_9 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_10 <= l_1_s_0(10) & l_1_s_1(10) & l_1_s_2(10);
with sell_2_c_0_cl_10 select
l_2_c_0_cl_10 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_11 <= l_1_s_0(11) & l_1_s_1(11) & l_1_s_2(11);
with sell_2_c_0_cl_11 select
l_2_c_0_cl_11 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_12 <= l_1_s_0(12) & l_1_s_1(12) & l_1_s_2(12);
with sell_2_c_0_cl_12 select
l_2_c_0_cl_12 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_13 <= l_1_s_0(13) & l_1_s_1(13) & l_1_s_2(13);
with sell_2_c_0_cl_13 select
l_2_c_0_cl_13 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_14 <= l_1_s_0(14) & l_1_s_1(14) & l_1_s_2(14);
with sell_2_c_0_cl_14 select
l_2_c_0_cl_14 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_15 <= l_1_s_0(15) & l_1_s_1(15) & l_1_s_2(15);
with sell_2_c_0_cl_15 select
l_2_c_0_cl_15 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_16 <= l_1_s_0(16) & l_1_s_1(16) & l_1_s_2(16);
with sell_2_c_0_cl_16 select
l_2_c_0_cl_16 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_17 <= l_1_s_0(17) & l_1_s_1(17) & l_1_s_2(17);
with sell_2_c_0_cl_17 select
l_2_c_0_cl_17 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_18 <= l_1_s_0(18) & l_1_s_1(18) & l_1_s_2(18);
with sell_2_c_0_cl_18 select
l_2_c_0_cl_18 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_19 <= l_1_s_0(19) & l_1_s_1(19) & l_1_s_2(19);
with sell_2_c_0_cl_19 select
l_2_c_0_cl_19 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_20 <= l_1_s_0(20) & l_1_s_1(20) & l_1_s_2(20);
with sell_2_c_0_cl_20 select
l_2_c_0_cl_20 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_21 <= l_1_s_0(21) & l_1_s_1(21) & l_1_s_2(21);
with sell_2_c_0_cl_21 select
l_2_c_0_cl_21 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_22 <= l_1_s_0(22) & l_1_s_1(22) & l_1_s_2(22);
with sell_2_c_0_cl_22 select
l_2_c_0_cl_22 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_23 <= l_1_s_0(23) & l_1_s_1(23) & l_1_s_2(23);
with sell_2_c_0_cl_23 select
l_2_c_0_cl_23 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_24 <= l_1_s_0(24) & l_1_s_1(24) & l_1_s_2(24);
with sell_2_c_0_cl_24 select
l_2_c_0_cl_24 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_25 <= l_1_s_0(25) & l_1_s_1(25) & l_1_s_2(25);
with sell_2_c_0_cl_25 select
l_2_c_0_cl_25 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_26 <= l_1_s_0(26) & l_1_s_1(26) & l_1_s_2(26);
with sell_2_c_0_cl_26 select
l_2_c_0_cl_26 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_27 <= l_1_s_0(27) & l_1_s_1(27) & l_1_s_2(27);
with sell_2_c_0_cl_27 select
l_2_c_0_cl_27 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_28 <= l_1_s_0(28) & l_1_s_1(28) & l_1_s_2(28);
with sell_2_c_0_cl_28 select
l_2_c_0_cl_28 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_29 <= l_1_s_0(29) & l_1_s_1(29) & l_1_s_2(29);
with sell_2_c_0_cl_29 select
l_2_c_0_cl_29 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_30 <= l_1_s_0(30) & l_1_s_1(30) & l_1_s_2(30);
with sell_2_c_0_cl_30 select
l_2_c_0_cl_30 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_31 <= l_1_s_0(31) & l_1_s_1(31) & l_1_s_2(31);
with sell_2_c_0_cl_31 select
l_2_c_0_cl_31 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_32 <= l_1_s_0(32) & l_1_s_1(32) & l_1_s_2(32);
with sell_2_c_0_cl_32 select
l_2_c_0_cl_32 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_33 <= l_1_s_0(33) & l_1_s_1(33) & l_1_s_2(33);
with sell_2_c_0_cl_33 select
l_2_c_0_cl_33 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_34 <= l_1_s_0(34) & l_1_s_1(34) & l_1_s_2(34);
with sell_2_c_0_cl_34 select
l_2_c_0_cl_34 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_35 <= l_1_s_0(35) & l_1_s_1(35) & l_1_s_2(35);
with sell_2_c_0_cl_35 select
l_2_c_0_cl_35 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_36 <= l_1_s_0(36) & l_1_s_1(36) & l_1_s_2(36);
with sell_2_c_0_cl_36 select
l_2_c_0_cl_36 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_37 <= l_1_s_0(37) & l_1_s_1(37) & l_1_s_2(37);
with sell_2_c_0_cl_37 select
l_2_c_0_cl_37 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_38 <= l_1_s_0(38) & l_1_s_1(38) & l_1_s_2(38);
with sell_2_c_0_cl_38 select
l_2_c_0_cl_38 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_39 <= l_1_s_0(39) & l_1_s_1(39) & l_1_s_2(39);
with sell_2_c_0_cl_39 select
l_2_c_0_cl_39 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_40 <= l_1_s_0(40) & l_1_s_1(40) & l_1_s_2(40);
with sell_2_c_0_cl_40 select
l_2_c_0_cl_40 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_41 <= l_1_s_0(41) & l_1_s_1(41) & l_1_s_2(41);
with sell_2_c_0_cl_41 select
l_2_c_0_cl_41 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
l_2_s_0 <= l_2_c_0_cl_41(0 downto 0) & l_2_c_0_cl_40(0 downto 0) & l_2_c_0_cl_39(0 downto 0) & l_2_c_0_cl_38(0 downto 0) & l_2_c_0_cl_37(0 downto 0) & l_2_c_0_cl_36(0 downto 0) & l_2_c_0_cl_35(0 downto 0) & l_2_c_0_cl_34(0 downto 0) & l_2_c_0_cl_33(0 downto 0) & l_2_c_0_cl_32(0 downto 0) & l_2_c_0_cl_31(0 downto 0) & l_2_c_0_cl_30(0 downto 0) & l_2_c_0_cl_29(0 downto 0) & l_2_c_0_cl_28(0 downto 0) & l_2_c_0_cl_27(0 downto 0) & l_2_c_0_cl_26(0 downto 0) & l_2_c_0_cl_25(0 downto 0) & l_2_c_0_cl_24(0 downto 0) & l_2_c_0_cl_23(0 downto 0) & l_2_c_0_cl_22(0 downto 0) & l_2_c_0_cl_21(0 downto 0) & l_2_c_0_cl_20(0 downto 0) & l_2_c_0_cl_19(0 downto 0) & l_2_c_0_cl_18(0 downto 0) & l_2_c_0_cl_17(0 downto 0) & l_2_c_0_cl_16(0 downto 0) & l_2_c_0_cl_15(0 downto 0) & l_2_c_0_cl_14(0 downto 0) & l_2_c_0_cl_13(0 downto 0) & l_2_c_0_cl_12(0 downto 0) & l_2_c_0_cl_11(0 downto 0) & l_2_c_0_cl_10(0 downto 0) & l_2_c_0_cl_9(0 downto 0) & l_2_c_0_cl_8(0 downto 0) & l_2_c_0_cl_7(0 downto 0) & l_2_c_0_cl_6(0 downto 0) & l_2_c_0_cl_5(0 downto 0) & l_2_c_0_cl_4(0 downto 0) & l_2_c_0_cl_3(0 downto 0) & l_2_c_0_cl_2(0 downto 0) & l_2_c_0_cl_1(0 downto 0) & l_2_c_0_cl_0(0 downto 0);
l_2_s_1 <= l_2_c_0_cl_40(1 downto 1) & l_2_c_0_cl_39(1 downto 1) & l_2_c_0_cl_38(1 downto 1) & l_2_c_0_cl_37(1 downto 1) & l_2_c_0_cl_36(1 downto 1) & l_2_c_0_cl_35(1 downto 1) & l_2_c_0_cl_34(1 downto 1) & l_2_c_0_cl_33(1 downto 1) & l_2_c_0_cl_32(1 downto 1) & l_2_c_0_cl_31(1 downto 1) & l_2_c_0_cl_30(1 downto 1) & l_2_c_0_cl_29(1 downto 1) & l_2_c_0_cl_28(1 downto 1) & l_2_c_0_cl_27(1 downto 1) & l_2_c_0_cl_26(1 downto 1) & l_2_c_0_cl_25(1 downto 1) & l_2_c_0_cl_24(1 downto 1) & l_2_c_0_cl_23(1 downto 1) & l_2_c_0_cl_22(1 downto 1) & l_2_c_0_cl_21(1 downto 1) & l_2_c_0_cl_20(1 downto 1) & l_2_c_0_cl_19(1 downto 1) & l_2_c_0_cl_18(1 downto 1) & l_2_c_0_cl_17(1 downto 1) & l_2_c_0_cl_16(1 downto 1) & l_2_c_0_cl_15(1 downto 1) & l_2_c_0_cl_14(1 downto 1) & l_2_c_0_cl_13(1 downto 1) & l_2_c_0_cl_12(1 downto 1) & l_2_c_0_cl_11(1 downto 1) & l_2_c_0_cl_10(1 downto 1) & l_2_c_0_cl_9(1 downto 1) & l_2_c_0_cl_8(1 downto 1) & l_2_c_0_cl_7(1 downto 1) & l_2_c_0_cl_6(1 downto 1) & l_2_c_0_cl_5(1 downto 1) & l_2_c_0_cl_4(1 downto 1) & l_2_c_0_cl_3(1 downto 1) & l_2_c_0_cl_2(1 downto 1) & l_2_c_0_cl_1(1 downto 1) & l_2_c_0_cl_0(1 downto 1) & "0";
FinalAdder_CompressorTree: IntAdder_42_f400_uid11 -- pipelineDepth=1 maxInDelay=1.59336e-09
port map ( clk => clk,
rst => rst,
Cin => '0',
R => myR,
X => l_2_s_0,
Y => l_2_s_1);
----------------Synchro barrier, entering cycle 2----------------
R <= myR;
-- delay at adder output 1.634e-09
end architecture;
--------------------------------------------------------------------------------
-- LogicIntMultiplier_5_34_uid5_0
-- (LogicIntMultiplier_5_34_uid5)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Sebastian Banescu (2008-2009)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity LogicIntMultiplier_5_34_uid5_0 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(4 downto 0);
Y : in std_logic_vector(33 downto 0);
R : out std_logic_vector(38 downto 0) );
end entity;
architecture arch of LogicIntMultiplier_5_34_uid5_0 is
attribute multstyle : string;
attribute multstyle of arch : architecture is "logic";
component IntMultiAdder_42_op4_f400_uid7 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(41 downto 0);
X1 : in std_logic_vector(41 downto 0);
X2 : in std_logic_vector(41 downto 0);
X3 : in std_logic_vector(41 downto 0);
R : out std_logic_vector(41 downto 0) );
end component;
signal sX : std_logic_vector(5 downto 0);
signal sY : std_logic_vector(35 downto 0);
signal x0, x0_d1 : std_logic_vector(2 downto 0);
signal x1, x1_d1 : std_logic_vector(2 downto 0);
signal y0, y0_d1 : std_logic_vector(2 downto 0);
signal y1, y1_d1 : std_logic_vector(2 downto 0);
signal y2, y2_d1 : std_logic_vector(2 downto 0);
signal y3, y3_d1 : std_logic_vector(2 downto 0);
signal y4, y4_d1 : std_logic_vector(2 downto 0);
signal y5, y5_d1 : std_logic_vector(2 downto 0);
signal y6, y6_d1 : std_logic_vector(2 downto 0);
signal y7, y7_d1 : std_logic_vector(2 downto 0);
signal y8, y8_d1 : std_logic_vector(2 downto 0);
signal y9, y9_d1 : std_logic_vector(2 downto 0);
signal y10, y10_d1 : std_logic_vector(2 downto 0);
signal y11, y11_d1 : std_logic_vector(2 downto 0);
signal px0y0 : std_logic_vector(5 downto 0);
signal px1y0 : std_logic_vector(5 downto 0);
signal px0y1 : std_logic_vector(5 downto 0);
signal px1y1 : std_logic_vector(5 downto 0);
signal px0y2 : std_logic_vector(5 downto 0);
signal px1y2 : std_logic_vector(5 downto 0);
signal px0y3 : std_logic_vector(5 downto 0);
signal px1y3 : std_logic_vector(5 downto 0);
signal px0y4 : std_logic_vector(5 downto 0);
signal px1y4 : std_logic_vector(5 downto 0);
signal px0y5 : std_logic_vector(5 downto 0);
signal px1y5 : std_logic_vector(5 downto 0);
signal px0y6 : std_logic_vector(5 downto 0);
signal px1y6 : std_logic_vector(5 downto 0);
signal px0y7 : std_logic_vector(5 downto 0);
signal px1y7 : std_logic_vector(5 downto 0);
signal px0y8 : std_logic_vector(5 downto 0);
signal px1y8 : std_logic_vector(5 downto 0);
signal px0y9 : std_logic_vector(5 downto 0);
signal px1y9 : std_logic_vector(5 downto 0);
signal px0y10 : std_logic_vector(5 downto 0);
signal px1y10 : std_logic_vector(5 downto 0);
signal px0y11 : std_logic_vector(5 downto 0);
signal px1y11 : std_logic_vector(5 downto 0);
signal cp00 : std_logic_vector(41 downto 0);
signal cp01 : std_logic_vector(41 downto 0);
signal cp10 : std_logic_vector(41 downto 0);
signal cp11 : std_logic_vector(41 downto 0);
signal addRes : std_logic_vector(41 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x0_d1 <= x0;
x1_d1 <= x1;
y0_d1 <= y0;
y1_d1 <= y1;
y2_d1 <= y2;
y3_d1 <= y3;
y4_d1 <= y4;
y5_d1 <= y5;
y6_d1 <= y6;
y7_d1 <= y7;
y8_d1 <= y8;
y9_d1 <= y9;
y10_d1 <= y10;
y11_d1 <= y11;
end if;
end process;
sX <= X & "0";
sY <= Y & "00";
x0 <= sX(2 downto 0);
x1 <= sX(5 downto 3);
y0 <= sY(2 downto 0);
y1 <= sY(5 downto 3);
y2 <= sY(8 downto 6);
y3 <= sY(11 downto 9);
y4 <= sY(14 downto 12);
y5 <= sY(17 downto 15);
y6 <= sY(20 downto 18);
y7 <= sY(23 downto 21);
y8 <= sY(26 downto 24);
y9 <= sY(29 downto 27);
y10 <= sY(32 downto 30);
y11 <= sY(35 downto 33);
----------------Synchro barrier, entering cycle 1----------------
px0y0 <= x0_d1 * y0_d1;
px1y0 <= x1_d1 * y0_d1;
px0y1 <= x0_d1 * y1_d1;
px1y1 <= x1_d1 * y1_d1;
px0y2 <= x0_d1 * y2_d1;
px1y2 <= x1_d1 * y2_d1;
px0y3 <= x0_d1 * y3_d1;
px1y3 <= x1_d1 * y3_d1;
px0y4 <= x0_d1 * y4_d1;
px1y4 <= x1_d1 * y4_d1;
px0y5 <= x0_d1 * y5_d1;
px1y5 <= x1_d1 * y5_d1;
px0y6 <= x0_d1 * y6_d1;
px1y6 <= x1_d1 * y6_d1;
px0y7 <= x0_d1 * y7_d1;
px1y7 <= x1_d1 * y7_d1;
px0y8 <= x0_d1 * y8_d1;
px1y8 <= x1_d1 * y8_d1;
px0y9 <= x0_d1 * y9_d1;
px1y9 <= x1_d1 * y9_d1;
px0y10 <= x0_d1 * y10_d1;
px1y10 <= x1_d1 * y10_d1;
px0y11 <= x0_d1 * y11_d1;
px1y11 <= x1_d1 * y11_d1;
cp00 <= "000" & px0y11 & px0y9 & px0y7 & px0y5 & px0y3 & px0y1 & "000";
cp01 <= "" & px1y11 & px1y9 & px1y7 & px1y5 & px1y3 & px1y1 & "000000";
cp10 <= "000000" & px0y10 & px0y8 & px0y6 & px0y4 & px0y2 & px0y0 & "";
cp11 <= "000" & px1y10 & px1y8 & px1y6 & px1y4 & px1y2 & px1y0 & "000";
adder: IntMultiAdder_42_op4_f400_uid7 -- pipelineDepth=2 maxInDelay=2.5e-09
port map ( clk => clk,
rst => rst,
R => addRes,
X0 => cp00,
X1 => cp01,
X2 => cp10,
X3 => cp11);
----------------Synchro barrier, entering cycle 3----------------
R<=addRes(41 downto 3);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_26_f400_uid19
-- (IntAdderAlternative_26_f400_uid23)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_26_f400_uid19 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(25 downto 0);
Y : in std_logic_vector(25 downto 0);
Cin : in std_logic;
R : out std_logic_vector(25 downto 0) );
end entity;
architecture arch of IntAdder_26_f400_uid19 is
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
--Alternative
R <= X + Y + Cin;
end architecture;
--------------------------------------------------------------------------------
-- LogicIntMultiplier_24_2_uid17_1
-- (LogicIntMultiplier_24_2_uid17)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Sebastian Banescu (2008-2009)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity LogicIntMultiplier_24_2_uid17_1 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(1 downto 0);
R : out std_logic_vector(25 downto 0) );
end entity;
architecture arch of LogicIntMultiplier_24_2_uid17_1 is
attribute multstyle : string;
attribute multstyle of arch : architecture is "logic";
component IntAdder_26_f400_uid19 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(25 downto 0);
Y : in std_logic_vector(25 downto 0);
Cin : in std_logic;
R : out std_logic_vector(25 downto 0) );
end component;
signal R0 : std_logic_vector(25 downto 0);
signal R1 : std_logic_vector(25 downto 0);
signal RAdder : std_logic_vector(25 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
R0 <= ("00" & X) when Y(0)='1' else "00000000000000000000000000";
R1 <= ( "0" & X & "0") when Y(1)='1' else "00000000000000000000000000";
ResultAdder: IntAdder_26_f400_uid19 -- pipelineDepth=0 maxInDelay=9.7544e-10
port map ( clk => clk,
rst => rst,
Cin => '0',
R => RAdder ,
X => R0,
Y => R1);
R <= RAdder;
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_106_f400_uid29
-- (IntAdderClassical_106_f400_uid31)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 3 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_106_f400_uid29 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(105 downto 0);
Y : in std_logic_vector(105 downto 0);
Cin : in std_logic;
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntAdder_106_f400_uid29 is
signal x0 : std_logic_vector(41 downto 0);
signal y0 : std_logic_vector(41 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(21 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(21 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(42 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(22 downto 0);
signal X_d1 : std_logic_vector(105 downto 0);
signal Y_d1 : std_logic_vector(105 downto 0);
signal Cin_d1 : std_logic;
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
X_d1 <= X;
Y_d1 <= Y;
Cin_d1 <= Cin;
end if;
end process;
--Classical
----------------Synchro barrier, entering cycle 1----------------
x0 <= X_d1(41 downto 0);
y0 <= Y_d1(41 downto 0);
x1 <= X_d1(83 downto 42);
y1 <= Y_d1(83 downto 42);
x2 <= X_d1(105 downto 84);
y2 <= Y_d1(105 downto 84);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin_d1;
----------------Synchro barrier, entering cycle 2----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(42);
----------------Synchro barrier, entering cycle 3----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(21 downto 0) & sum1_d1(41 downto 0) & sum0_d2(41 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- IntMultiAdder_106_op4_f400_uid25
-- (IntCompressorTree_106_4_uid27)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca (2009-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 3 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntMultiAdder_106_op4_f400_uid25 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(105 downto 0);
X1 : in std_logic_vector(105 downto 0);
X2 : in std_logic_vector(105 downto 0);
X3 : in std_logic_vector(105 downto 0);
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntMultiAdder_106_op4_f400_uid25 is
component IntAdder_106_f400_uid29 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(105 downto 0);
Y : in std_logic_vector(105 downto 0);
Cin : in std_logic;
R : out std_logic_vector(105 downto 0) );
end component;
signal l_0_s_0 : std_logic_vector(105 downto 0);
signal l_0_s_1 : std_logic_vector(105 downto 0);
signal l_0_s_2 : std_logic_vector(105 downto 0);
signal l_0_s_3 : std_logic_vector(105 downto 0);
signal sell_1_c_0_cl_0 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_0 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_1 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_1 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_2 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_2 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_3 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_3 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_4 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_4 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_5 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_5 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_6 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_6 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_7 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_7 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_8 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_8 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_9 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_9 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_10 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_10 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_11 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_11 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_12 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_12 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_13 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_13 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_14 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_14 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_15 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_15 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_16 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_16 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_17 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_17 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_18 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_18 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_19 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_19 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_20 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_20 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_21 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_21 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_22 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_22 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_23 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_23 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_24 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_24 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_25 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_25 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_26 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_26 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_27 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_27 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_28 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_28 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_29 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_29 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_30 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_30 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_31 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_31 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_32 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_32 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_33 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_33 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_34 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_34 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_35 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_35 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_36 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_36 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_37 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_37 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_38 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_38 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_39 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_39 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_40 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_40 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_41 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_41 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_42 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_42 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_43 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_43 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_44 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_44 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_45 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_45 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_46 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_46 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_47 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_47 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_48 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_48 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_49 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_49 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_50 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_50 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_51 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_51 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_52 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_52 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_53 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_53 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_54 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_54 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_55 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_55 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_56 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_56 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_57 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_57 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_58 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_58 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_59 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_59 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_60 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_60 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_61 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_61 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_62 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_62 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_63 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_63 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_64 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_64 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_65 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_65 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_66 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_66 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_67 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_67 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_68 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_68 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_69 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_69 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_70 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_70 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_71 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_71 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_72 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_72 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_73 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_73 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_74 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_74 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_75 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_75 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_76 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_76 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_77 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_77 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_78 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_78 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_79 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_79 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_80 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_80 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_81 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_81 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_82 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_82 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_83 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_83 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_84 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_84 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_85 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_85 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_86 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_86 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_87 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_87 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_88 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_88 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_89 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_89 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_90 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_90 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_91 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_91 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_92 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_92 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_93 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_93 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_94 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_94 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_95 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_95 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_96 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_96 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_97 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_97 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_98 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_98 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_99 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_99 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_100 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_100 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_101 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_101 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_102 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_102 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_103 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_103 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_104 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_104 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_105 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_105 : std_logic_vector(2 downto 0);
signal l_1_s_0 : std_logic_vector(105 downto 0);
signal l_1_s_1 : std_logic_vector(105 downto 0);
signal l_1_s_2 : std_logic_vector(105 downto 0);
signal sell_2_c_0_cl_0 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_0 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_1 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_1 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_2 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_2 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_3 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_3 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_4 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_4 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_5 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_5 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_6 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_6 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_7 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_7 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_8 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_8 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_9 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_9 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_10 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_10 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_11 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_11 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_12 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_12 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_13 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_13 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_14 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_14 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_15 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_15 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_16 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_16 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_17 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_17 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_18 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_18 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_19 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_19 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_20 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_20 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_21 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_21 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_22 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_22 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_23 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_23 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_24 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_24 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_25 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_25 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_26 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_26 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_27 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_27 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_28 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_28 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_29 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_29 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_30 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_30 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_31 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_31 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_32 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_32 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_33 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_33 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_34 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_34 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_35 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_35 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_36 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_36 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_37 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_37 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_38 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_38 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_39 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_39 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_40 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_40 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_41 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_42 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_42 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_43 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_43 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_44 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_44 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_45 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_45 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_46 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_46 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_47 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_47 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_48 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_48 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_49 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_49 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_50 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_50 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_51 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_51 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_52 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_52 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_53 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_53 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_54 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_54 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_55 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_55 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_56 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_56 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_57 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_57 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_58 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_58 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_59 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_59 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_60 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_60 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_61 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_61 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_62 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_62 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_63 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_63 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_64 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_64 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_65 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_65 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_66 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_66 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_67 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_67 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_68 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_68 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_69 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_69 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_70 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_70 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_71 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_71 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_72 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_72 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_73 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_73 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_74 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_74 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_75 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_75 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_76 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_76 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_77 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_77 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_78 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_78 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_79 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_79 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_80 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_80 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_81 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_81 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_82 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_82 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_83 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_83 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_84 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_84 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_85 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_85 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_86 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_86 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_87 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_87 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_88 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_88 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_89 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_89 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_90 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_90 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_91 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_91 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_92 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_92 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_93 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_93 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_94 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_94 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_95 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_95 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_96 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_96 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_97 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_97 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_98 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_98 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_99 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_99 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_100 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_100 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_101 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_101 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_102 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_102 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_103 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_103 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_104 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_104 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_105 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_105 : std_logic_vector(1 downto 0);
signal l_2_s_0 : std_logic_vector(105 downto 0);
signal l_2_s_1 : std_logic_vector(105 downto 0);
signal myR : std_logic_vector(105 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
l_0_s_0 <= X0;
l_0_s_1 <= X1;
l_0_s_2 <= X2;
l_0_s_3 <= X3;
sell_1_c_0_cl_0 <= l_0_s_0(0) & l_0_s_1(0) & l_0_s_2(0) & l_0_s_3(0);
with sell_1_c_0_cl_0 select
l_1_c_0_cl_0 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_1 <= l_0_s_0(1) & l_0_s_1(1) & l_0_s_2(1) & l_0_s_3(1);
with sell_1_c_0_cl_1 select
l_1_c_0_cl_1 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_2 <= l_0_s_0(2) & l_0_s_1(2) & l_0_s_2(2) & l_0_s_3(2);
with sell_1_c_0_cl_2 select
l_1_c_0_cl_2 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_3 <= l_0_s_0(3) & l_0_s_1(3) & l_0_s_2(3) & l_0_s_3(3);
with sell_1_c_0_cl_3 select
l_1_c_0_cl_3 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_4 <= l_0_s_0(4) & l_0_s_1(4) & l_0_s_2(4) & l_0_s_3(4);
with sell_1_c_0_cl_4 select
l_1_c_0_cl_4 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_5 <= l_0_s_0(5) & l_0_s_1(5) & l_0_s_2(5) & l_0_s_3(5);
with sell_1_c_0_cl_5 select
l_1_c_0_cl_5 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_6 <= l_0_s_0(6) & l_0_s_1(6) & l_0_s_2(6) & l_0_s_3(6);
with sell_1_c_0_cl_6 select
l_1_c_0_cl_6 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_7 <= l_0_s_0(7) & l_0_s_1(7) & l_0_s_2(7) & l_0_s_3(7);
with sell_1_c_0_cl_7 select
l_1_c_0_cl_7 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_8 <= l_0_s_0(8) & l_0_s_1(8) & l_0_s_2(8) & l_0_s_3(8);
with sell_1_c_0_cl_8 select
l_1_c_0_cl_8 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_9 <= l_0_s_0(9) & l_0_s_1(9) & l_0_s_2(9) & l_0_s_3(9);
with sell_1_c_0_cl_9 select
l_1_c_0_cl_9 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_10 <= l_0_s_0(10) & l_0_s_1(10) & l_0_s_2(10) & l_0_s_3(10);
with sell_1_c_0_cl_10 select
l_1_c_0_cl_10 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_11 <= l_0_s_0(11) & l_0_s_1(11) & l_0_s_2(11) & l_0_s_3(11);
with sell_1_c_0_cl_11 select
l_1_c_0_cl_11 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_12 <= l_0_s_0(12) & l_0_s_1(12) & l_0_s_2(12) & l_0_s_3(12);
with sell_1_c_0_cl_12 select
l_1_c_0_cl_12 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_13 <= l_0_s_0(13) & l_0_s_1(13) & l_0_s_2(13) & l_0_s_3(13);
with sell_1_c_0_cl_13 select
l_1_c_0_cl_13 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_14 <= l_0_s_0(14) & l_0_s_1(14) & l_0_s_2(14) & l_0_s_3(14);
with sell_1_c_0_cl_14 select
l_1_c_0_cl_14 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_15 <= l_0_s_0(15) & l_0_s_1(15) & l_0_s_2(15) & l_0_s_3(15);
with sell_1_c_0_cl_15 select
l_1_c_0_cl_15 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_16 <= l_0_s_0(16) & l_0_s_1(16) & l_0_s_2(16) & l_0_s_3(16);
with sell_1_c_0_cl_16 select
l_1_c_0_cl_16 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_17 <= l_0_s_0(17) & l_0_s_1(17) & l_0_s_2(17) & l_0_s_3(17);
with sell_1_c_0_cl_17 select
l_1_c_0_cl_17 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_18 <= l_0_s_0(18) & l_0_s_1(18) & l_0_s_2(18) & l_0_s_3(18);
with sell_1_c_0_cl_18 select
l_1_c_0_cl_18 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_19 <= l_0_s_0(19) & l_0_s_1(19) & l_0_s_2(19) & l_0_s_3(19);
with sell_1_c_0_cl_19 select
l_1_c_0_cl_19 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_20 <= l_0_s_0(20) & l_0_s_1(20) & l_0_s_2(20) & l_0_s_3(20);
with sell_1_c_0_cl_20 select
l_1_c_0_cl_20 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_21 <= l_0_s_0(21) & l_0_s_1(21) & l_0_s_2(21) & l_0_s_3(21);
with sell_1_c_0_cl_21 select
l_1_c_0_cl_21 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_22 <= l_0_s_0(22) & l_0_s_1(22) & l_0_s_2(22) & l_0_s_3(22);
with sell_1_c_0_cl_22 select
l_1_c_0_cl_22 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_23 <= l_0_s_0(23) & l_0_s_1(23) & l_0_s_2(23) & l_0_s_3(23);
with sell_1_c_0_cl_23 select
l_1_c_0_cl_23 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_24 <= l_0_s_0(24) & l_0_s_1(24) & l_0_s_2(24) & l_0_s_3(24);
with sell_1_c_0_cl_24 select
l_1_c_0_cl_24 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_25 <= l_0_s_0(25) & l_0_s_1(25) & l_0_s_2(25) & l_0_s_3(25);
with sell_1_c_0_cl_25 select
l_1_c_0_cl_25 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_26 <= l_0_s_0(26) & l_0_s_1(26) & l_0_s_2(26) & l_0_s_3(26);
with sell_1_c_0_cl_26 select
l_1_c_0_cl_26 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_27 <= l_0_s_0(27) & l_0_s_1(27) & l_0_s_2(27) & l_0_s_3(27);
with sell_1_c_0_cl_27 select
l_1_c_0_cl_27 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_28 <= l_0_s_0(28) & l_0_s_1(28) & l_0_s_2(28) & l_0_s_3(28);
with sell_1_c_0_cl_28 select
l_1_c_0_cl_28 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_29 <= l_0_s_0(29) & l_0_s_1(29) & l_0_s_2(29) & l_0_s_3(29);
with sell_1_c_0_cl_29 select
l_1_c_0_cl_29 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_30 <= l_0_s_0(30) & l_0_s_1(30) & l_0_s_2(30) & l_0_s_3(30);
with sell_1_c_0_cl_30 select
l_1_c_0_cl_30 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_31 <= l_0_s_0(31) & l_0_s_1(31) & l_0_s_2(31) & l_0_s_3(31);
with sell_1_c_0_cl_31 select
l_1_c_0_cl_31 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_32 <= l_0_s_0(32) & l_0_s_1(32) & l_0_s_2(32) & l_0_s_3(32);
with sell_1_c_0_cl_32 select
l_1_c_0_cl_32 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_33 <= l_0_s_0(33) & l_0_s_1(33) & l_0_s_2(33) & l_0_s_3(33);
with sell_1_c_0_cl_33 select
l_1_c_0_cl_33 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_34 <= l_0_s_0(34) & l_0_s_1(34) & l_0_s_2(34) & l_0_s_3(34);
with sell_1_c_0_cl_34 select
l_1_c_0_cl_34 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_35 <= l_0_s_0(35) & l_0_s_1(35) & l_0_s_2(35) & l_0_s_3(35);
with sell_1_c_0_cl_35 select
l_1_c_0_cl_35 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_36 <= l_0_s_0(36) & l_0_s_1(36) & l_0_s_2(36) & l_0_s_3(36);
with sell_1_c_0_cl_36 select
l_1_c_0_cl_36 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_37 <= l_0_s_0(37) & l_0_s_1(37) & l_0_s_2(37) & l_0_s_3(37);
with sell_1_c_0_cl_37 select
l_1_c_0_cl_37 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_38 <= l_0_s_0(38) & l_0_s_1(38) & l_0_s_2(38) & l_0_s_3(38);
with sell_1_c_0_cl_38 select
l_1_c_0_cl_38 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_39 <= l_0_s_0(39) & l_0_s_1(39) & l_0_s_2(39) & l_0_s_3(39);
with sell_1_c_0_cl_39 select
l_1_c_0_cl_39 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_40 <= l_0_s_0(40) & l_0_s_1(40) & l_0_s_2(40) & l_0_s_3(40);
with sell_1_c_0_cl_40 select
l_1_c_0_cl_40 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_41 <= l_0_s_0(41) & l_0_s_1(41) & l_0_s_2(41) & l_0_s_3(41);
with sell_1_c_0_cl_41 select
l_1_c_0_cl_41 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_42 <= l_0_s_0(42) & l_0_s_1(42) & l_0_s_2(42) & l_0_s_3(42);
with sell_1_c_0_cl_42 select
l_1_c_0_cl_42 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_43 <= l_0_s_0(43) & l_0_s_1(43) & l_0_s_2(43) & l_0_s_3(43);
with sell_1_c_0_cl_43 select
l_1_c_0_cl_43 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_44 <= l_0_s_0(44) & l_0_s_1(44) & l_0_s_2(44) & l_0_s_3(44);
with sell_1_c_0_cl_44 select
l_1_c_0_cl_44 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_45 <= l_0_s_0(45) & l_0_s_1(45) & l_0_s_2(45) & l_0_s_3(45);
with sell_1_c_0_cl_45 select
l_1_c_0_cl_45 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_46 <= l_0_s_0(46) & l_0_s_1(46) & l_0_s_2(46) & l_0_s_3(46);
with sell_1_c_0_cl_46 select
l_1_c_0_cl_46 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_47 <= l_0_s_0(47) & l_0_s_1(47) & l_0_s_2(47) & l_0_s_3(47);
with sell_1_c_0_cl_47 select
l_1_c_0_cl_47 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_48 <= l_0_s_0(48) & l_0_s_1(48) & l_0_s_2(48) & l_0_s_3(48);
with sell_1_c_0_cl_48 select
l_1_c_0_cl_48 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_49 <= l_0_s_0(49) & l_0_s_1(49) & l_0_s_2(49) & l_0_s_3(49);
with sell_1_c_0_cl_49 select
l_1_c_0_cl_49 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_50 <= l_0_s_0(50) & l_0_s_1(50) & l_0_s_2(50) & l_0_s_3(50);
with sell_1_c_0_cl_50 select
l_1_c_0_cl_50 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_51 <= l_0_s_0(51) & l_0_s_1(51) & l_0_s_2(51) & l_0_s_3(51);
with sell_1_c_0_cl_51 select
l_1_c_0_cl_51 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_52 <= l_0_s_0(52) & l_0_s_1(52) & l_0_s_2(52) & l_0_s_3(52);
with sell_1_c_0_cl_52 select
l_1_c_0_cl_52 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_53 <= l_0_s_0(53) & l_0_s_1(53) & l_0_s_2(53) & l_0_s_3(53);
with sell_1_c_0_cl_53 select
l_1_c_0_cl_53 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_54 <= l_0_s_0(54) & l_0_s_1(54) & l_0_s_2(54) & l_0_s_3(54);
with sell_1_c_0_cl_54 select
l_1_c_0_cl_54 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_55 <= l_0_s_0(55) & l_0_s_1(55) & l_0_s_2(55) & l_0_s_3(55);
with sell_1_c_0_cl_55 select
l_1_c_0_cl_55 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_56 <= l_0_s_0(56) & l_0_s_1(56) & l_0_s_2(56) & l_0_s_3(56);
with sell_1_c_0_cl_56 select
l_1_c_0_cl_56 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_57 <= l_0_s_0(57) & l_0_s_1(57) & l_0_s_2(57) & l_0_s_3(57);
with sell_1_c_0_cl_57 select
l_1_c_0_cl_57 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_58 <= l_0_s_0(58) & l_0_s_1(58) & l_0_s_2(58) & l_0_s_3(58);
with sell_1_c_0_cl_58 select
l_1_c_0_cl_58 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_59 <= l_0_s_0(59) & l_0_s_1(59) & l_0_s_2(59) & l_0_s_3(59);
with sell_1_c_0_cl_59 select
l_1_c_0_cl_59 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_60 <= l_0_s_0(60) & l_0_s_1(60) & l_0_s_2(60) & l_0_s_3(60);
with sell_1_c_0_cl_60 select
l_1_c_0_cl_60 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_61 <= l_0_s_0(61) & l_0_s_1(61) & l_0_s_2(61) & l_0_s_3(61);
with sell_1_c_0_cl_61 select
l_1_c_0_cl_61 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_62 <= l_0_s_0(62) & l_0_s_1(62) & l_0_s_2(62) & l_0_s_3(62);
with sell_1_c_0_cl_62 select
l_1_c_0_cl_62 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_63 <= l_0_s_0(63) & l_0_s_1(63) & l_0_s_2(63) & l_0_s_3(63);
with sell_1_c_0_cl_63 select
l_1_c_0_cl_63 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_64 <= l_0_s_0(64) & l_0_s_1(64) & l_0_s_2(64) & l_0_s_3(64);
with sell_1_c_0_cl_64 select
l_1_c_0_cl_64 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_65 <= l_0_s_0(65) & l_0_s_1(65) & l_0_s_2(65) & l_0_s_3(65);
with sell_1_c_0_cl_65 select
l_1_c_0_cl_65 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_66 <= l_0_s_0(66) & l_0_s_1(66) & l_0_s_2(66) & l_0_s_3(66);
with sell_1_c_0_cl_66 select
l_1_c_0_cl_66 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_67 <= l_0_s_0(67) & l_0_s_1(67) & l_0_s_2(67) & l_0_s_3(67);
with sell_1_c_0_cl_67 select
l_1_c_0_cl_67 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_68 <= l_0_s_0(68) & l_0_s_1(68) & l_0_s_2(68) & l_0_s_3(68);
with sell_1_c_0_cl_68 select
l_1_c_0_cl_68 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_69 <= l_0_s_0(69) & l_0_s_1(69) & l_0_s_2(69) & l_0_s_3(69);
with sell_1_c_0_cl_69 select
l_1_c_0_cl_69 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_70 <= l_0_s_0(70) & l_0_s_1(70) & l_0_s_2(70) & l_0_s_3(70);
with sell_1_c_0_cl_70 select
l_1_c_0_cl_70 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_71 <= l_0_s_0(71) & l_0_s_1(71) & l_0_s_2(71) & l_0_s_3(71);
with sell_1_c_0_cl_71 select
l_1_c_0_cl_71 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_72 <= l_0_s_0(72) & l_0_s_1(72) & l_0_s_2(72) & l_0_s_3(72);
with sell_1_c_0_cl_72 select
l_1_c_0_cl_72 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_73 <= l_0_s_0(73) & l_0_s_1(73) & l_0_s_2(73) & l_0_s_3(73);
with sell_1_c_0_cl_73 select
l_1_c_0_cl_73 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_74 <= l_0_s_0(74) & l_0_s_1(74) & l_0_s_2(74) & l_0_s_3(74);
with sell_1_c_0_cl_74 select
l_1_c_0_cl_74 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_75 <= l_0_s_0(75) & l_0_s_1(75) & l_0_s_2(75) & l_0_s_3(75);
with sell_1_c_0_cl_75 select
l_1_c_0_cl_75 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_76 <= l_0_s_0(76) & l_0_s_1(76) & l_0_s_2(76) & l_0_s_3(76);
with sell_1_c_0_cl_76 select
l_1_c_0_cl_76 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_77 <= l_0_s_0(77) & l_0_s_1(77) & l_0_s_2(77) & l_0_s_3(77);
with sell_1_c_0_cl_77 select
l_1_c_0_cl_77 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_78 <= l_0_s_0(78) & l_0_s_1(78) & l_0_s_2(78) & l_0_s_3(78);
with sell_1_c_0_cl_78 select
l_1_c_0_cl_78 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_79 <= l_0_s_0(79) & l_0_s_1(79) & l_0_s_2(79) & l_0_s_3(79);
with sell_1_c_0_cl_79 select
l_1_c_0_cl_79 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_80 <= l_0_s_0(80) & l_0_s_1(80) & l_0_s_2(80) & l_0_s_3(80);
with sell_1_c_0_cl_80 select
l_1_c_0_cl_80 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_81 <= l_0_s_0(81) & l_0_s_1(81) & l_0_s_2(81) & l_0_s_3(81);
with sell_1_c_0_cl_81 select
l_1_c_0_cl_81 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_82 <= l_0_s_0(82) & l_0_s_1(82) & l_0_s_2(82) & l_0_s_3(82);
with sell_1_c_0_cl_82 select
l_1_c_0_cl_82 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_83 <= l_0_s_0(83) & l_0_s_1(83) & l_0_s_2(83) & l_0_s_3(83);
with sell_1_c_0_cl_83 select
l_1_c_0_cl_83 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_84 <= l_0_s_0(84) & l_0_s_1(84) & l_0_s_2(84) & l_0_s_3(84);
with sell_1_c_0_cl_84 select
l_1_c_0_cl_84 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_85 <= l_0_s_0(85) & l_0_s_1(85) & l_0_s_2(85) & l_0_s_3(85);
with sell_1_c_0_cl_85 select
l_1_c_0_cl_85 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_86 <= l_0_s_0(86) & l_0_s_1(86) & l_0_s_2(86) & l_0_s_3(86);
with sell_1_c_0_cl_86 select
l_1_c_0_cl_86 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_87 <= l_0_s_0(87) & l_0_s_1(87) & l_0_s_2(87) & l_0_s_3(87);
with sell_1_c_0_cl_87 select
l_1_c_0_cl_87 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_88 <= l_0_s_0(88) & l_0_s_1(88) & l_0_s_2(88) & l_0_s_3(88);
with sell_1_c_0_cl_88 select
l_1_c_0_cl_88 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_89 <= l_0_s_0(89) & l_0_s_1(89) & l_0_s_2(89) & l_0_s_3(89);
with sell_1_c_0_cl_89 select
l_1_c_0_cl_89 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_90 <= l_0_s_0(90) & l_0_s_1(90) & l_0_s_2(90) & l_0_s_3(90);
with sell_1_c_0_cl_90 select
l_1_c_0_cl_90 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_91 <= l_0_s_0(91) & l_0_s_1(91) & l_0_s_2(91) & l_0_s_3(91);
with sell_1_c_0_cl_91 select
l_1_c_0_cl_91 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_92 <= l_0_s_0(92) & l_0_s_1(92) & l_0_s_2(92) & l_0_s_3(92);
with sell_1_c_0_cl_92 select
l_1_c_0_cl_92 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_93 <= l_0_s_0(93) & l_0_s_1(93) & l_0_s_2(93) & l_0_s_3(93);
with sell_1_c_0_cl_93 select
l_1_c_0_cl_93 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_94 <= l_0_s_0(94) & l_0_s_1(94) & l_0_s_2(94) & l_0_s_3(94);
with sell_1_c_0_cl_94 select
l_1_c_0_cl_94 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_95 <= l_0_s_0(95) & l_0_s_1(95) & l_0_s_2(95) & l_0_s_3(95);
with sell_1_c_0_cl_95 select
l_1_c_0_cl_95 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_96 <= l_0_s_0(96) & l_0_s_1(96) & l_0_s_2(96) & l_0_s_3(96);
with sell_1_c_0_cl_96 select
l_1_c_0_cl_96 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_97 <= l_0_s_0(97) & l_0_s_1(97) & l_0_s_2(97) & l_0_s_3(97);
with sell_1_c_0_cl_97 select
l_1_c_0_cl_97 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_98 <= l_0_s_0(98) & l_0_s_1(98) & l_0_s_2(98) & l_0_s_3(98);
with sell_1_c_0_cl_98 select
l_1_c_0_cl_98 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_99 <= l_0_s_0(99) & l_0_s_1(99) & l_0_s_2(99) & l_0_s_3(99);
with sell_1_c_0_cl_99 select
l_1_c_0_cl_99 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_100 <= l_0_s_0(100) & l_0_s_1(100) & l_0_s_2(100) & l_0_s_3(100);
with sell_1_c_0_cl_100 select
l_1_c_0_cl_100 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_101 <= l_0_s_0(101) & l_0_s_1(101) & l_0_s_2(101) & l_0_s_3(101);
with sell_1_c_0_cl_101 select
l_1_c_0_cl_101 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_102 <= l_0_s_0(102) & l_0_s_1(102) & l_0_s_2(102) & l_0_s_3(102);
with sell_1_c_0_cl_102 select
l_1_c_0_cl_102 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_103 <= l_0_s_0(103) & l_0_s_1(103) & l_0_s_2(103) & l_0_s_3(103);
with sell_1_c_0_cl_103 select
l_1_c_0_cl_103 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_104 <= l_0_s_0(104) & l_0_s_1(104) & l_0_s_2(104) & l_0_s_3(104);
with sell_1_c_0_cl_104 select
l_1_c_0_cl_104 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_105 <= l_0_s_0(105) & l_0_s_1(105) & l_0_s_2(105) & l_0_s_3(105);
with sell_1_c_0_cl_105 select
l_1_c_0_cl_105 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
l_1_s_0 <= l_1_c_0_cl_105(0 downto 0) & l_1_c_0_cl_104(0 downto 0) & l_1_c_0_cl_103(0 downto 0) & l_1_c_0_cl_102(0 downto 0) & l_1_c_0_cl_101(0 downto 0) & l_1_c_0_cl_100(0 downto 0) & l_1_c_0_cl_99(0 downto 0) & l_1_c_0_cl_98(0 downto 0) & l_1_c_0_cl_97(0 downto 0) & l_1_c_0_cl_96(0 downto 0) & l_1_c_0_cl_95(0 downto 0) & l_1_c_0_cl_94(0 downto 0) & l_1_c_0_cl_93(0 downto 0) & l_1_c_0_cl_92(0 downto 0) & l_1_c_0_cl_91(0 downto 0) & l_1_c_0_cl_90(0 downto 0) & l_1_c_0_cl_89(0 downto 0) & l_1_c_0_cl_88(0 downto 0) & l_1_c_0_cl_87(0 downto 0) & l_1_c_0_cl_86(0 downto 0) & l_1_c_0_cl_85(0 downto 0) & l_1_c_0_cl_84(0 downto 0) & l_1_c_0_cl_83(0 downto 0) & l_1_c_0_cl_82(0 downto 0) & l_1_c_0_cl_81(0 downto 0) & l_1_c_0_cl_80(0 downto 0) & l_1_c_0_cl_79(0 downto 0) & l_1_c_0_cl_78(0 downto 0) & l_1_c_0_cl_77(0 downto 0) & l_1_c_0_cl_76(0 downto 0) & l_1_c_0_cl_75(0 downto 0) & l_1_c_0_cl_74(0 downto 0) & l_1_c_0_cl_73(0 downto 0) & l_1_c_0_cl_72(0 downto 0) & l_1_c_0_cl_71(0 downto 0) & l_1_c_0_cl_70(0 downto 0) & l_1_c_0_cl_69(0 downto 0) & l_1_c_0_cl_68(0 downto 0) & l_1_c_0_cl_67(0 downto 0) & l_1_c_0_cl_66(0 downto 0) & l_1_c_0_cl_65(0 downto 0) & l_1_c_0_cl_64(0 downto 0) & l_1_c_0_cl_63(0 downto 0) & l_1_c_0_cl_62(0 downto 0) & l_1_c_0_cl_61(0 downto 0) & l_1_c_0_cl_60(0 downto 0) & l_1_c_0_cl_59(0 downto 0) & l_1_c_0_cl_58(0 downto 0) & l_1_c_0_cl_57(0 downto 0) & l_1_c_0_cl_56(0 downto 0) & l_1_c_0_cl_55(0 downto 0) & l_1_c_0_cl_54(0 downto 0) & l_1_c_0_cl_53(0 downto 0) & l_1_c_0_cl_52(0 downto 0) & l_1_c_0_cl_51(0 downto 0) & l_1_c_0_cl_50(0 downto 0) & l_1_c_0_cl_49(0 downto 0) & l_1_c_0_cl_48(0 downto 0) & l_1_c_0_cl_47(0 downto 0) & l_1_c_0_cl_46(0 downto 0) & l_1_c_0_cl_45(0 downto 0) & l_1_c_0_cl_44(0 downto 0) & l_1_c_0_cl_43(0 downto 0) & l_1_c_0_cl_42(0 downto 0) & l_1_c_0_cl_41(0 downto 0) & l_1_c_0_cl_40(0 downto 0) & l_1_c_0_cl_39(0 downto 0) & l_1_c_0_cl_38(0 downto 0) & l_1_c_0_cl_37(0 downto 0) & l_1_c_0_cl_36(0 downto 0) & l_1_c_0_cl_35(0 downto 0) & l_1_c_0_cl_34(0 downto 0) & l_1_c_0_cl_33(0 downto 0) & l_1_c_0_cl_32(0 downto 0) & l_1_c_0_cl_31(0 downto 0) & l_1_c_0_cl_30(0 downto 0) & l_1_c_0_cl_29(0 downto 0) & l_1_c_0_cl_28(0 downto 0) & l_1_c_0_cl_27(0 downto 0) & l_1_c_0_cl_26(0 downto 0) & l_1_c_0_cl_25(0 downto 0) & l_1_c_0_cl_24(0 downto 0) & l_1_c_0_cl_23(0 downto 0) & l_1_c_0_cl_22(0 downto 0) & l_1_c_0_cl_21(0 downto 0) & l_1_c_0_cl_20(0 downto 0) & l_1_c_0_cl_19(0 downto 0) & l_1_c_0_cl_18(0 downto 0) & l_1_c_0_cl_17(0 downto 0) & l_1_c_0_cl_16(0 downto 0) & l_1_c_0_cl_15(0 downto 0) & l_1_c_0_cl_14(0 downto 0) & l_1_c_0_cl_13(0 downto 0) & l_1_c_0_cl_12(0 downto 0) & l_1_c_0_cl_11(0 downto 0) & l_1_c_0_cl_10(0 downto 0) & l_1_c_0_cl_9(0 downto 0) & l_1_c_0_cl_8(0 downto 0) & l_1_c_0_cl_7(0 downto 0) & l_1_c_0_cl_6(0 downto 0) & l_1_c_0_cl_5(0 downto 0) & l_1_c_0_cl_4(0 downto 0) & l_1_c_0_cl_3(0 downto 0) & l_1_c_0_cl_2(0 downto 0) & l_1_c_0_cl_1(0 downto 0) & l_1_c_0_cl_0(0 downto 0);
l_1_s_1 <= l_1_c_0_cl_104(1 downto 1) & l_1_c_0_cl_103(1 downto 1) & l_1_c_0_cl_102(1 downto 1) & l_1_c_0_cl_101(1 downto 1) & l_1_c_0_cl_100(1 downto 1) & l_1_c_0_cl_99(1 downto 1) & l_1_c_0_cl_98(1 downto 1) & l_1_c_0_cl_97(1 downto 1) & l_1_c_0_cl_96(1 downto 1) & l_1_c_0_cl_95(1 downto 1) & l_1_c_0_cl_94(1 downto 1) & l_1_c_0_cl_93(1 downto 1) & l_1_c_0_cl_92(1 downto 1) & l_1_c_0_cl_91(1 downto 1) & l_1_c_0_cl_90(1 downto 1) & l_1_c_0_cl_89(1 downto 1) & l_1_c_0_cl_88(1 downto 1) & l_1_c_0_cl_87(1 downto 1) & l_1_c_0_cl_86(1 downto 1) & l_1_c_0_cl_85(1 downto 1) & l_1_c_0_cl_84(1 downto 1) & l_1_c_0_cl_83(1 downto 1) & l_1_c_0_cl_82(1 downto 1) & l_1_c_0_cl_81(1 downto 1) & l_1_c_0_cl_80(1 downto 1) & l_1_c_0_cl_79(1 downto 1) & l_1_c_0_cl_78(1 downto 1) & l_1_c_0_cl_77(1 downto 1) & l_1_c_0_cl_76(1 downto 1) & l_1_c_0_cl_75(1 downto 1) & l_1_c_0_cl_74(1 downto 1) & l_1_c_0_cl_73(1 downto 1) & l_1_c_0_cl_72(1 downto 1) & l_1_c_0_cl_71(1 downto 1) & l_1_c_0_cl_70(1 downto 1) & l_1_c_0_cl_69(1 downto 1) & l_1_c_0_cl_68(1 downto 1) & l_1_c_0_cl_67(1 downto 1) & l_1_c_0_cl_66(1 downto 1) & l_1_c_0_cl_65(1 downto 1) & l_1_c_0_cl_64(1 downto 1) & l_1_c_0_cl_63(1 downto 1) & l_1_c_0_cl_62(1 downto 1) & l_1_c_0_cl_61(1 downto 1) & l_1_c_0_cl_60(1 downto 1) & l_1_c_0_cl_59(1 downto 1) & l_1_c_0_cl_58(1 downto 1) & l_1_c_0_cl_57(1 downto 1) & l_1_c_0_cl_56(1 downto 1) & l_1_c_0_cl_55(1 downto 1) & l_1_c_0_cl_54(1 downto 1) & l_1_c_0_cl_53(1 downto 1) & l_1_c_0_cl_52(1 downto 1) & l_1_c_0_cl_51(1 downto 1) & l_1_c_0_cl_50(1 downto 1) & l_1_c_0_cl_49(1 downto 1) & l_1_c_0_cl_48(1 downto 1) & l_1_c_0_cl_47(1 downto 1) & l_1_c_0_cl_46(1 downto 1) & l_1_c_0_cl_45(1 downto 1) & l_1_c_0_cl_44(1 downto 1) & l_1_c_0_cl_43(1 downto 1) & l_1_c_0_cl_42(1 downto 1) & l_1_c_0_cl_41(1 downto 1) & l_1_c_0_cl_40(1 downto 1) & l_1_c_0_cl_39(1 downto 1) & l_1_c_0_cl_38(1 downto 1) & l_1_c_0_cl_37(1 downto 1) & l_1_c_0_cl_36(1 downto 1) & l_1_c_0_cl_35(1 downto 1) & l_1_c_0_cl_34(1 downto 1) & l_1_c_0_cl_33(1 downto 1) & l_1_c_0_cl_32(1 downto 1) & l_1_c_0_cl_31(1 downto 1) & l_1_c_0_cl_30(1 downto 1) & l_1_c_0_cl_29(1 downto 1) & l_1_c_0_cl_28(1 downto 1) & l_1_c_0_cl_27(1 downto 1) & l_1_c_0_cl_26(1 downto 1) & l_1_c_0_cl_25(1 downto 1) & l_1_c_0_cl_24(1 downto 1) & l_1_c_0_cl_23(1 downto 1) & l_1_c_0_cl_22(1 downto 1) & l_1_c_0_cl_21(1 downto 1) & l_1_c_0_cl_20(1 downto 1) & l_1_c_0_cl_19(1 downto 1) & l_1_c_0_cl_18(1 downto 1) & l_1_c_0_cl_17(1 downto 1) & l_1_c_0_cl_16(1 downto 1) & l_1_c_0_cl_15(1 downto 1) & l_1_c_0_cl_14(1 downto 1) & l_1_c_0_cl_13(1 downto 1) & l_1_c_0_cl_12(1 downto 1) & l_1_c_0_cl_11(1 downto 1) & l_1_c_0_cl_10(1 downto 1) & l_1_c_0_cl_9(1 downto 1) & l_1_c_0_cl_8(1 downto 1) & l_1_c_0_cl_7(1 downto 1) & l_1_c_0_cl_6(1 downto 1) & l_1_c_0_cl_5(1 downto 1) & l_1_c_0_cl_4(1 downto 1) & l_1_c_0_cl_3(1 downto 1) & l_1_c_0_cl_2(1 downto 1) & l_1_c_0_cl_1(1 downto 1) & l_1_c_0_cl_0(1 downto 1) & "0";
l_1_s_2 <= l_1_c_0_cl_103(2 downto 2) & l_1_c_0_cl_102(2 downto 2) & l_1_c_0_cl_101(2 downto 2) & l_1_c_0_cl_100(2 downto 2) & l_1_c_0_cl_99(2 downto 2) & l_1_c_0_cl_98(2 downto 2) & l_1_c_0_cl_97(2 downto 2) & l_1_c_0_cl_96(2 downto 2) & l_1_c_0_cl_95(2 downto 2) & l_1_c_0_cl_94(2 downto 2) & l_1_c_0_cl_93(2 downto 2) & l_1_c_0_cl_92(2 downto 2) & l_1_c_0_cl_91(2 downto 2) & l_1_c_0_cl_90(2 downto 2) & l_1_c_0_cl_89(2 downto 2) & l_1_c_0_cl_88(2 downto 2) & l_1_c_0_cl_87(2 downto 2) & l_1_c_0_cl_86(2 downto 2) & l_1_c_0_cl_85(2 downto 2) & l_1_c_0_cl_84(2 downto 2) & l_1_c_0_cl_83(2 downto 2) & l_1_c_0_cl_82(2 downto 2) & l_1_c_0_cl_81(2 downto 2) & l_1_c_0_cl_80(2 downto 2) & l_1_c_0_cl_79(2 downto 2) & l_1_c_0_cl_78(2 downto 2) & l_1_c_0_cl_77(2 downto 2) & l_1_c_0_cl_76(2 downto 2) & l_1_c_0_cl_75(2 downto 2) & l_1_c_0_cl_74(2 downto 2) & l_1_c_0_cl_73(2 downto 2) & l_1_c_0_cl_72(2 downto 2) & l_1_c_0_cl_71(2 downto 2) & l_1_c_0_cl_70(2 downto 2) & l_1_c_0_cl_69(2 downto 2) & l_1_c_0_cl_68(2 downto 2) & l_1_c_0_cl_67(2 downto 2) & l_1_c_0_cl_66(2 downto 2) & l_1_c_0_cl_65(2 downto 2) & l_1_c_0_cl_64(2 downto 2) & l_1_c_0_cl_63(2 downto 2) & l_1_c_0_cl_62(2 downto 2) & l_1_c_0_cl_61(2 downto 2) & l_1_c_0_cl_60(2 downto 2) & l_1_c_0_cl_59(2 downto 2) & l_1_c_0_cl_58(2 downto 2) & l_1_c_0_cl_57(2 downto 2) & l_1_c_0_cl_56(2 downto 2) & l_1_c_0_cl_55(2 downto 2) & l_1_c_0_cl_54(2 downto 2) & l_1_c_0_cl_53(2 downto 2) & l_1_c_0_cl_52(2 downto 2) & l_1_c_0_cl_51(2 downto 2) & l_1_c_0_cl_50(2 downto 2) & l_1_c_0_cl_49(2 downto 2) & l_1_c_0_cl_48(2 downto 2) & l_1_c_0_cl_47(2 downto 2) & l_1_c_0_cl_46(2 downto 2) & l_1_c_0_cl_45(2 downto 2) & l_1_c_0_cl_44(2 downto 2) & l_1_c_0_cl_43(2 downto 2) & l_1_c_0_cl_42(2 downto 2) & l_1_c_0_cl_41(2 downto 2) & l_1_c_0_cl_40(2 downto 2) & l_1_c_0_cl_39(2 downto 2) & l_1_c_0_cl_38(2 downto 2) & l_1_c_0_cl_37(2 downto 2) & l_1_c_0_cl_36(2 downto 2) & l_1_c_0_cl_35(2 downto 2) & l_1_c_0_cl_34(2 downto 2) & l_1_c_0_cl_33(2 downto 2) & l_1_c_0_cl_32(2 downto 2) & l_1_c_0_cl_31(2 downto 2) & l_1_c_0_cl_30(2 downto 2) & l_1_c_0_cl_29(2 downto 2) & l_1_c_0_cl_28(2 downto 2) & l_1_c_0_cl_27(2 downto 2) & l_1_c_0_cl_26(2 downto 2) & l_1_c_0_cl_25(2 downto 2) & l_1_c_0_cl_24(2 downto 2) & l_1_c_0_cl_23(2 downto 2) & l_1_c_0_cl_22(2 downto 2) & l_1_c_0_cl_21(2 downto 2) & l_1_c_0_cl_20(2 downto 2) & l_1_c_0_cl_19(2 downto 2) & l_1_c_0_cl_18(2 downto 2) & l_1_c_0_cl_17(2 downto 2) & l_1_c_0_cl_16(2 downto 2) & l_1_c_0_cl_15(2 downto 2) & l_1_c_0_cl_14(2 downto 2) & l_1_c_0_cl_13(2 downto 2) & l_1_c_0_cl_12(2 downto 2) & l_1_c_0_cl_11(2 downto 2) & l_1_c_0_cl_10(2 downto 2) & l_1_c_0_cl_9(2 downto 2) & l_1_c_0_cl_8(2 downto 2) & l_1_c_0_cl_7(2 downto 2) & l_1_c_0_cl_6(2 downto 2) & l_1_c_0_cl_5(2 downto 2) & l_1_c_0_cl_4(2 downto 2) & l_1_c_0_cl_3(2 downto 2) & l_1_c_0_cl_2(2 downto 2) & l_1_c_0_cl_1(2 downto 2) & l_1_c_0_cl_0(2 downto 2) & "00";
sell_2_c_0_cl_0 <= l_1_s_0(0) & l_1_s_1(0) & l_1_s_2(0);
with sell_2_c_0_cl_0 select
l_2_c_0_cl_0 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_1 <= l_1_s_0(1) & l_1_s_1(1) & l_1_s_2(1);
with sell_2_c_0_cl_1 select
l_2_c_0_cl_1 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_2 <= l_1_s_0(2) & l_1_s_1(2) & l_1_s_2(2);
with sell_2_c_0_cl_2 select
l_2_c_0_cl_2 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_3 <= l_1_s_0(3) & l_1_s_1(3) & l_1_s_2(3);
with sell_2_c_0_cl_3 select
l_2_c_0_cl_3 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_4 <= l_1_s_0(4) & l_1_s_1(4) & l_1_s_2(4);
with sell_2_c_0_cl_4 select
l_2_c_0_cl_4 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_5 <= l_1_s_0(5) & l_1_s_1(5) & l_1_s_2(5);
with sell_2_c_0_cl_5 select
l_2_c_0_cl_5 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_6 <= l_1_s_0(6) & l_1_s_1(6) & l_1_s_2(6);
with sell_2_c_0_cl_6 select
l_2_c_0_cl_6 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_7 <= l_1_s_0(7) & l_1_s_1(7) & l_1_s_2(7);
with sell_2_c_0_cl_7 select
l_2_c_0_cl_7 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_8 <= l_1_s_0(8) & l_1_s_1(8) & l_1_s_2(8);
with sell_2_c_0_cl_8 select
l_2_c_0_cl_8 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_9 <= l_1_s_0(9) & l_1_s_1(9) & l_1_s_2(9);
with sell_2_c_0_cl_9 select
l_2_c_0_cl_9 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_10 <= l_1_s_0(10) & l_1_s_1(10) & l_1_s_2(10);
with sell_2_c_0_cl_10 select
l_2_c_0_cl_10 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_11 <= l_1_s_0(11) & l_1_s_1(11) & l_1_s_2(11);
with sell_2_c_0_cl_11 select
l_2_c_0_cl_11 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_12 <= l_1_s_0(12) & l_1_s_1(12) & l_1_s_2(12);
with sell_2_c_0_cl_12 select
l_2_c_0_cl_12 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_13 <= l_1_s_0(13) & l_1_s_1(13) & l_1_s_2(13);
with sell_2_c_0_cl_13 select
l_2_c_0_cl_13 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_14 <= l_1_s_0(14) & l_1_s_1(14) & l_1_s_2(14);
with sell_2_c_0_cl_14 select
l_2_c_0_cl_14 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_15 <= l_1_s_0(15) & l_1_s_1(15) & l_1_s_2(15);
with sell_2_c_0_cl_15 select
l_2_c_0_cl_15 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_16 <= l_1_s_0(16) & l_1_s_1(16) & l_1_s_2(16);
with sell_2_c_0_cl_16 select
l_2_c_0_cl_16 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_17 <= l_1_s_0(17) & l_1_s_1(17) & l_1_s_2(17);
with sell_2_c_0_cl_17 select
l_2_c_0_cl_17 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_18 <= l_1_s_0(18) & l_1_s_1(18) & l_1_s_2(18);
with sell_2_c_0_cl_18 select
l_2_c_0_cl_18 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_19 <= l_1_s_0(19) & l_1_s_1(19) & l_1_s_2(19);
with sell_2_c_0_cl_19 select
l_2_c_0_cl_19 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_20 <= l_1_s_0(20) & l_1_s_1(20) & l_1_s_2(20);
with sell_2_c_0_cl_20 select
l_2_c_0_cl_20 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_21 <= l_1_s_0(21) & l_1_s_1(21) & l_1_s_2(21);
with sell_2_c_0_cl_21 select
l_2_c_0_cl_21 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_22 <= l_1_s_0(22) & l_1_s_1(22) & l_1_s_2(22);
with sell_2_c_0_cl_22 select
l_2_c_0_cl_22 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_23 <= l_1_s_0(23) & l_1_s_1(23) & l_1_s_2(23);
with sell_2_c_0_cl_23 select
l_2_c_0_cl_23 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_24 <= l_1_s_0(24) & l_1_s_1(24) & l_1_s_2(24);
with sell_2_c_0_cl_24 select
l_2_c_0_cl_24 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_25 <= l_1_s_0(25) & l_1_s_1(25) & l_1_s_2(25);
with sell_2_c_0_cl_25 select
l_2_c_0_cl_25 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_26 <= l_1_s_0(26) & l_1_s_1(26) & l_1_s_2(26);
with sell_2_c_0_cl_26 select
l_2_c_0_cl_26 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_27 <= l_1_s_0(27) & l_1_s_1(27) & l_1_s_2(27);
with sell_2_c_0_cl_27 select
l_2_c_0_cl_27 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_28 <= l_1_s_0(28) & l_1_s_1(28) & l_1_s_2(28);
with sell_2_c_0_cl_28 select
l_2_c_0_cl_28 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_29 <= l_1_s_0(29) & l_1_s_1(29) & l_1_s_2(29);
with sell_2_c_0_cl_29 select
l_2_c_0_cl_29 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_30 <= l_1_s_0(30) & l_1_s_1(30) & l_1_s_2(30);
with sell_2_c_0_cl_30 select
l_2_c_0_cl_30 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_31 <= l_1_s_0(31) & l_1_s_1(31) & l_1_s_2(31);
with sell_2_c_0_cl_31 select
l_2_c_0_cl_31 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_32 <= l_1_s_0(32) & l_1_s_1(32) & l_1_s_2(32);
with sell_2_c_0_cl_32 select
l_2_c_0_cl_32 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_33 <= l_1_s_0(33) & l_1_s_1(33) & l_1_s_2(33);
with sell_2_c_0_cl_33 select
l_2_c_0_cl_33 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_34 <= l_1_s_0(34) & l_1_s_1(34) & l_1_s_2(34);
with sell_2_c_0_cl_34 select
l_2_c_0_cl_34 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_35 <= l_1_s_0(35) & l_1_s_1(35) & l_1_s_2(35);
with sell_2_c_0_cl_35 select
l_2_c_0_cl_35 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_36 <= l_1_s_0(36) & l_1_s_1(36) & l_1_s_2(36);
with sell_2_c_0_cl_36 select
l_2_c_0_cl_36 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_37 <= l_1_s_0(37) & l_1_s_1(37) & l_1_s_2(37);
with sell_2_c_0_cl_37 select
l_2_c_0_cl_37 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_38 <= l_1_s_0(38) & l_1_s_1(38) & l_1_s_2(38);
with sell_2_c_0_cl_38 select
l_2_c_0_cl_38 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_39 <= l_1_s_0(39) & l_1_s_1(39) & l_1_s_2(39);
with sell_2_c_0_cl_39 select
l_2_c_0_cl_39 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_40 <= l_1_s_0(40) & l_1_s_1(40) & l_1_s_2(40);
with sell_2_c_0_cl_40 select
l_2_c_0_cl_40 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_41 <= l_1_s_0(41) & l_1_s_1(41) & l_1_s_2(41);
with sell_2_c_0_cl_41 select
l_2_c_0_cl_41 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_42 <= l_1_s_0(42) & l_1_s_1(42) & l_1_s_2(42);
with sell_2_c_0_cl_42 select
l_2_c_0_cl_42 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_43 <= l_1_s_0(43) & l_1_s_1(43) & l_1_s_2(43);
with sell_2_c_0_cl_43 select
l_2_c_0_cl_43 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_44 <= l_1_s_0(44) & l_1_s_1(44) & l_1_s_2(44);
with sell_2_c_0_cl_44 select
l_2_c_0_cl_44 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_45 <= l_1_s_0(45) & l_1_s_1(45) & l_1_s_2(45);
with sell_2_c_0_cl_45 select
l_2_c_0_cl_45 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_46 <= l_1_s_0(46) & l_1_s_1(46) & l_1_s_2(46);
with sell_2_c_0_cl_46 select
l_2_c_0_cl_46 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_47 <= l_1_s_0(47) & l_1_s_1(47) & l_1_s_2(47);
with sell_2_c_0_cl_47 select
l_2_c_0_cl_47 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_48 <= l_1_s_0(48) & l_1_s_1(48) & l_1_s_2(48);
with sell_2_c_0_cl_48 select
l_2_c_0_cl_48 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_49 <= l_1_s_0(49) & l_1_s_1(49) & l_1_s_2(49);
with sell_2_c_0_cl_49 select
l_2_c_0_cl_49 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_50 <= l_1_s_0(50) & l_1_s_1(50) & l_1_s_2(50);
with sell_2_c_0_cl_50 select
l_2_c_0_cl_50 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_51 <= l_1_s_0(51) & l_1_s_1(51) & l_1_s_2(51);
with sell_2_c_0_cl_51 select
l_2_c_0_cl_51 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_52 <= l_1_s_0(52) & l_1_s_1(52) & l_1_s_2(52);
with sell_2_c_0_cl_52 select
l_2_c_0_cl_52 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_53 <= l_1_s_0(53) & l_1_s_1(53) & l_1_s_2(53);
with sell_2_c_0_cl_53 select
l_2_c_0_cl_53 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_54 <= l_1_s_0(54) & l_1_s_1(54) & l_1_s_2(54);
with sell_2_c_0_cl_54 select
l_2_c_0_cl_54 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_55 <= l_1_s_0(55) & l_1_s_1(55) & l_1_s_2(55);
with sell_2_c_0_cl_55 select
l_2_c_0_cl_55 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_56 <= l_1_s_0(56) & l_1_s_1(56) & l_1_s_2(56);
with sell_2_c_0_cl_56 select
l_2_c_0_cl_56 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_57 <= l_1_s_0(57) & l_1_s_1(57) & l_1_s_2(57);
with sell_2_c_0_cl_57 select
l_2_c_0_cl_57 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_58 <= l_1_s_0(58) & l_1_s_1(58) & l_1_s_2(58);
with sell_2_c_0_cl_58 select
l_2_c_0_cl_58 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_59 <= l_1_s_0(59) & l_1_s_1(59) & l_1_s_2(59);
with sell_2_c_0_cl_59 select
l_2_c_0_cl_59 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_60 <= l_1_s_0(60) & l_1_s_1(60) & l_1_s_2(60);
with sell_2_c_0_cl_60 select
l_2_c_0_cl_60 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_61 <= l_1_s_0(61) & l_1_s_1(61) & l_1_s_2(61);
with sell_2_c_0_cl_61 select
l_2_c_0_cl_61 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_62 <= l_1_s_0(62) & l_1_s_1(62) & l_1_s_2(62);
with sell_2_c_0_cl_62 select
l_2_c_0_cl_62 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_63 <= l_1_s_0(63) & l_1_s_1(63) & l_1_s_2(63);
with sell_2_c_0_cl_63 select
l_2_c_0_cl_63 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_64 <= l_1_s_0(64) & l_1_s_1(64) & l_1_s_2(64);
with sell_2_c_0_cl_64 select
l_2_c_0_cl_64 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_65 <= l_1_s_0(65) & l_1_s_1(65) & l_1_s_2(65);
with sell_2_c_0_cl_65 select
l_2_c_0_cl_65 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_66 <= l_1_s_0(66) & l_1_s_1(66) & l_1_s_2(66);
with sell_2_c_0_cl_66 select
l_2_c_0_cl_66 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_67 <= l_1_s_0(67) & l_1_s_1(67) & l_1_s_2(67);
with sell_2_c_0_cl_67 select
l_2_c_0_cl_67 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_68 <= l_1_s_0(68) & l_1_s_1(68) & l_1_s_2(68);
with sell_2_c_0_cl_68 select
l_2_c_0_cl_68 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_69 <= l_1_s_0(69) & l_1_s_1(69) & l_1_s_2(69);
with sell_2_c_0_cl_69 select
l_2_c_0_cl_69 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_70 <= l_1_s_0(70) & l_1_s_1(70) & l_1_s_2(70);
with sell_2_c_0_cl_70 select
l_2_c_0_cl_70 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_71 <= l_1_s_0(71) & l_1_s_1(71) & l_1_s_2(71);
with sell_2_c_0_cl_71 select
l_2_c_0_cl_71 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_72 <= l_1_s_0(72) & l_1_s_1(72) & l_1_s_2(72);
with sell_2_c_0_cl_72 select
l_2_c_0_cl_72 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_73 <= l_1_s_0(73) & l_1_s_1(73) & l_1_s_2(73);
with sell_2_c_0_cl_73 select
l_2_c_0_cl_73 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_74 <= l_1_s_0(74) & l_1_s_1(74) & l_1_s_2(74);
with sell_2_c_0_cl_74 select
l_2_c_0_cl_74 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_75 <= l_1_s_0(75) & l_1_s_1(75) & l_1_s_2(75);
with sell_2_c_0_cl_75 select
l_2_c_0_cl_75 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_76 <= l_1_s_0(76) & l_1_s_1(76) & l_1_s_2(76);
with sell_2_c_0_cl_76 select
l_2_c_0_cl_76 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_77 <= l_1_s_0(77) & l_1_s_1(77) & l_1_s_2(77);
with sell_2_c_0_cl_77 select
l_2_c_0_cl_77 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_78 <= l_1_s_0(78) & l_1_s_1(78) & l_1_s_2(78);
with sell_2_c_0_cl_78 select
l_2_c_0_cl_78 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_79 <= l_1_s_0(79) & l_1_s_1(79) & l_1_s_2(79);
with sell_2_c_0_cl_79 select
l_2_c_0_cl_79 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_80 <= l_1_s_0(80) & l_1_s_1(80) & l_1_s_2(80);
with sell_2_c_0_cl_80 select
l_2_c_0_cl_80 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_81 <= l_1_s_0(81) & l_1_s_1(81) & l_1_s_2(81);
with sell_2_c_0_cl_81 select
l_2_c_0_cl_81 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_82 <= l_1_s_0(82) & l_1_s_1(82) & l_1_s_2(82);
with sell_2_c_0_cl_82 select
l_2_c_0_cl_82 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_83 <= l_1_s_0(83) & l_1_s_1(83) & l_1_s_2(83);
with sell_2_c_0_cl_83 select
l_2_c_0_cl_83 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_84 <= l_1_s_0(84) & l_1_s_1(84) & l_1_s_2(84);
with sell_2_c_0_cl_84 select
l_2_c_0_cl_84 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_85 <= l_1_s_0(85) & l_1_s_1(85) & l_1_s_2(85);
with sell_2_c_0_cl_85 select
l_2_c_0_cl_85 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_86 <= l_1_s_0(86) & l_1_s_1(86) & l_1_s_2(86);
with sell_2_c_0_cl_86 select
l_2_c_0_cl_86 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_87 <= l_1_s_0(87) & l_1_s_1(87) & l_1_s_2(87);
with sell_2_c_0_cl_87 select
l_2_c_0_cl_87 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_88 <= l_1_s_0(88) & l_1_s_1(88) & l_1_s_2(88);
with sell_2_c_0_cl_88 select
l_2_c_0_cl_88 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_89 <= l_1_s_0(89) & l_1_s_1(89) & l_1_s_2(89);
with sell_2_c_0_cl_89 select
l_2_c_0_cl_89 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_90 <= l_1_s_0(90) & l_1_s_1(90) & l_1_s_2(90);
with sell_2_c_0_cl_90 select
l_2_c_0_cl_90 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_91 <= l_1_s_0(91) & l_1_s_1(91) & l_1_s_2(91);
with sell_2_c_0_cl_91 select
l_2_c_0_cl_91 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_92 <= l_1_s_0(92) & l_1_s_1(92) & l_1_s_2(92);
with sell_2_c_0_cl_92 select
l_2_c_0_cl_92 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_93 <= l_1_s_0(93) & l_1_s_1(93) & l_1_s_2(93);
with sell_2_c_0_cl_93 select
l_2_c_0_cl_93 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_94 <= l_1_s_0(94) & l_1_s_1(94) & l_1_s_2(94);
with sell_2_c_0_cl_94 select
l_2_c_0_cl_94 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_95 <= l_1_s_0(95) & l_1_s_1(95) & l_1_s_2(95);
with sell_2_c_0_cl_95 select
l_2_c_0_cl_95 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_96 <= l_1_s_0(96) & l_1_s_1(96) & l_1_s_2(96);
with sell_2_c_0_cl_96 select
l_2_c_0_cl_96 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_97 <= l_1_s_0(97) & l_1_s_1(97) & l_1_s_2(97);
with sell_2_c_0_cl_97 select
l_2_c_0_cl_97 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_98 <= l_1_s_0(98) & l_1_s_1(98) & l_1_s_2(98);
with sell_2_c_0_cl_98 select
l_2_c_0_cl_98 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_99 <= l_1_s_0(99) & l_1_s_1(99) & l_1_s_2(99);
with sell_2_c_0_cl_99 select
l_2_c_0_cl_99 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_100 <= l_1_s_0(100) & l_1_s_1(100) & l_1_s_2(100);
with sell_2_c_0_cl_100 select
l_2_c_0_cl_100 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_101 <= l_1_s_0(101) & l_1_s_1(101) & l_1_s_2(101);
with sell_2_c_0_cl_101 select
l_2_c_0_cl_101 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_102 <= l_1_s_0(102) & l_1_s_1(102) & l_1_s_2(102);
with sell_2_c_0_cl_102 select
l_2_c_0_cl_102 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_103 <= l_1_s_0(103) & l_1_s_1(103) & l_1_s_2(103);
with sell_2_c_0_cl_103 select
l_2_c_0_cl_103 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_104 <= l_1_s_0(104) & l_1_s_1(104) & l_1_s_2(104);
with sell_2_c_0_cl_104 select
l_2_c_0_cl_104 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_105 <= l_1_s_0(105) & l_1_s_1(105) & l_1_s_2(105);
with sell_2_c_0_cl_105 select
l_2_c_0_cl_105 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
l_2_s_0 <= l_2_c_0_cl_105(0 downto 0) & l_2_c_0_cl_104(0 downto 0) & l_2_c_0_cl_103(0 downto 0) & l_2_c_0_cl_102(0 downto 0) & l_2_c_0_cl_101(0 downto 0) & l_2_c_0_cl_100(0 downto 0) & l_2_c_0_cl_99(0 downto 0) & l_2_c_0_cl_98(0 downto 0) & l_2_c_0_cl_97(0 downto 0) & l_2_c_0_cl_96(0 downto 0) & l_2_c_0_cl_95(0 downto 0) & l_2_c_0_cl_94(0 downto 0) & l_2_c_0_cl_93(0 downto 0) & l_2_c_0_cl_92(0 downto 0) & l_2_c_0_cl_91(0 downto 0) & l_2_c_0_cl_90(0 downto 0) & l_2_c_0_cl_89(0 downto 0) & l_2_c_0_cl_88(0 downto 0) & l_2_c_0_cl_87(0 downto 0) & l_2_c_0_cl_86(0 downto 0) & l_2_c_0_cl_85(0 downto 0) & l_2_c_0_cl_84(0 downto 0) & l_2_c_0_cl_83(0 downto 0) & l_2_c_0_cl_82(0 downto 0) & l_2_c_0_cl_81(0 downto 0) & l_2_c_0_cl_80(0 downto 0) & l_2_c_0_cl_79(0 downto 0) & l_2_c_0_cl_78(0 downto 0) & l_2_c_0_cl_77(0 downto 0) & l_2_c_0_cl_76(0 downto 0) & l_2_c_0_cl_75(0 downto 0) & l_2_c_0_cl_74(0 downto 0) & l_2_c_0_cl_73(0 downto 0) & l_2_c_0_cl_72(0 downto 0) & l_2_c_0_cl_71(0 downto 0) & l_2_c_0_cl_70(0 downto 0) & l_2_c_0_cl_69(0 downto 0) & l_2_c_0_cl_68(0 downto 0) & l_2_c_0_cl_67(0 downto 0) & l_2_c_0_cl_66(0 downto 0) & l_2_c_0_cl_65(0 downto 0) & l_2_c_0_cl_64(0 downto 0) & l_2_c_0_cl_63(0 downto 0) & l_2_c_0_cl_62(0 downto 0) & l_2_c_0_cl_61(0 downto 0) & l_2_c_0_cl_60(0 downto 0) & l_2_c_0_cl_59(0 downto 0) & l_2_c_0_cl_58(0 downto 0) & l_2_c_0_cl_57(0 downto 0) & l_2_c_0_cl_56(0 downto 0) & l_2_c_0_cl_55(0 downto 0) & l_2_c_0_cl_54(0 downto 0) & l_2_c_0_cl_53(0 downto 0) & l_2_c_0_cl_52(0 downto 0) & l_2_c_0_cl_51(0 downto 0) & l_2_c_0_cl_50(0 downto 0) & l_2_c_0_cl_49(0 downto 0) & l_2_c_0_cl_48(0 downto 0) & l_2_c_0_cl_47(0 downto 0) & l_2_c_0_cl_46(0 downto 0) & l_2_c_0_cl_45(0 downto 0) & l_2_c_0_cl_44(0 downto 0) & l_2_c_0_cl_43(0 downto 0) & l_2_c_0_cl_42(0 downto 0) & l_2_c_0_cl_41(0 downto 0) & l_2_c_0_cl_40(0 downto 0) & l_2_c_0_cl_39(0 downto 0) & l_2_c_0_cl_38(0 downto 0) & l_2_c_0_cl_37(0 downto 0) & l_2_c_0_cl_36(0 downto 0) & l_2_c_0_cl_35(0 downto 0) & l_2_c_0_cl_34(0 downto 0) & l_2_c_0_cl_33(0 downto 0) & l_2_c_0_cl_32(0 downto 0) & l_2_c_0_cl_31(0 downto 0) & l_2_c_0_cl_30(0 downto 0) & l_2_c_0_cl_29(0 downto 0) & l_2_c_0_cl_28(0 downto 0) & l_2_c_0_cl_27(0 downto 0) & l_2_c_0_cl_26(0 downto 0) & l_2_c_0_cl_25(0 downto 0) & l_2_c_0_cl_24(0 downto 0) & l_2_c_0_cl_23(0 downto 0) & l_2_c_0_cl_22(0 downto 0) & l_2_c_0_cl_21(0 downto 0) & l_2_c_0_cl_20(0 downto 0) & l_2_c_0_cl_19(0 downto 0) & l_2_c_0_cl_18(0 downto 0) & l_2_c_0_cl_17(0 downto 0) & l_2_c_0_cl_16(0 downto 0) & l_2_c_0_cl_15(0 downto 0) & l_2_c_0_cl_14(0 downto 0) & l_2_c_0_cl_13(0 downto 0) & l_2_c_0_cl_12(0 downto 0) & l_2_c_0_cl_11(0 downto 0) & l_2_c_0_cl_10(0 downto 0) & l_2_c_0_cl_9(0 downto 0) & l_2_c_0_cl_8(0 downto 0) & l_2_c_0_cl_7(0 downto 0) & l_2_c_0_cl_6(0 downto 0) & l_2_c_0_cl_5(0 downto 0) & l_2_c_0_cl_4(0 downto 0) & l_2_c_0_cl_3(0 downto 0) & l_2_c_0_cl_2(0 downto 0) & l_2_c_0_cl_1(0 downto 0) & l_2_c_0_cl_0(0 downto 0);
l_2_s_1 <= l_2_c_0_cl_104(1 downto 1) & l_2_c_0_cl_103(1 downto 1) & l_2_c_0_cl_102(1 downto 1) & l_2_c_0_cl_101(1 downto 1) & l_2_c_0_cl_100(1 downto 1) & l_2_c_0_cl_99(1 downto 1) & l_2_c_0_cl_98(1 downto 1) & l_2_c_0_cl_97(1 downto 1) & l_2_c_0_cl_96(1 downto 1) & l_2_c_0_cl_95(1 downto 1) & l_2_c_0_cl_94(1 downto 1) & l_2_c_0_cl_93(1 downto 1) & l_2_c_0_cl_92(1 downto 1) & l_2_c_0_cl_91(1 downto 1) & l_2_c_0_cl_90(1 downto 1) & l_2_c_0_cl_89(1 downto 1) & l_2_c_0_cl_88(1 downto 1) & l_2_c_0_cl_87(1 downto 1) & l_2_c_0_cl_86(1 downto 1) & l_2_c_0_cl_85(1 downto 1) & l_2_c_0_cl_84(1 downto 1) & l_2_c_0_cl_83(1 downto 1) & l_2_c_0_cl_82(1 downto 1) & l_2_c_0_cl_81(1 downto 1) & l_2_c_0_cl_80(1 downto 1) & l_2_c_0_cl_79(1 downto 1) & l_2_c_0_cl_78(1 downto 1) & l_2_c_0_cl_77(1 downto 1) & l_2_c_0_cl_76(1 downto 1) & l_2_c_0_cl_75(1 downto 1) & l_2_c_0_cl_74(1 downto 1) & l_2_c_0_cl_73(1 downto 1) & l_2_c_0_cl_72(1 downto 1) & l_2_c_0_cl_71(1 downto 1) & l_2_c_0_cl_70(1 downto 1) & l_2_c_0_cl_69(1 downto 1) & l_2_c_0_cl_68(1 downto 1) & l_2_c_0_cl_67(1 downto 1) & l_2_c_0_cl_66(1 downto 1) & l_2_c_0_cl_65(1 downto 1) & l_2_c_0_cl_64(1 downto 1) & l_2_c_0_cl_63(1 downto 1) & l_2_c_0_cl_62(1 downto 1) & l_2_c_0_cl_61(1 downto 1) & l_2_c_0_cl_60(1 downto 1) & l_2_c_0_cl_59(1 downto 1) & l_2_c_0_cl_58(1 downto 1) & l_2_c_0_cl_57(1 downto 1) & l_2_c_0_cl_56(1 downto 1) & l_2_c_0_cl_55(1 downto 1) & l_2_c_0_cl_54(1 downto 1) & l_2_c_0_cl_53(1 downto 1) & l_2_c_0_cl_52(1 downto 1) & l_2_c_0_cl_51(1 downto 1) & l_2_c_0_cl_50(1 downto 1) & l_2_c_0_cl_49(1 downto 1) & l_2_c_0_cl_48(1 downto 1) & l_2_c_0_cl_47(1 downto 1) & l_2_c_0_cl_46(1 downto 1) & l_2_c_0_cl_45(1 downto 1) & l_2_c_0_cl_44(1 downto 1) & l_2_c_0_cl_43(1 downto 1) & l_2_c_0_cl_42(1 downto 1) & l_2_c_0_cl_41(1 downto 1) & l_2_c_0_cl_40(1 downto 1) & l_2_c_0_cl_39(1 downto 1) & l_2_c_0_cl_38(1 downto 1) & l_2_c_0_cl_37(1 downto 1) & l_2_c_0_cl_36(1 downto 1) & l_2_c_0_cl_35(1 downto 1) & l_2_c_0_cl_34(1 downto 1) & l_2_c_0_cl_33(1 downto 1) & l_2_c_0_cl_32(1 downto 1) & l_2_c_0_cl_31(1 downto 1) & l_2_c_0_cl_30(1 downto 1) & l_2_c_0_cl_29(1 downto 1) & l_2_c_0_cl_28(1 downto 1) & l_2_c_0_cl_27(1 downto 1) & l_2_c_0_cl_26(1 downto 1) & l_2_c_0_cl_25(1 downto 1) & l_2_c_0_cl_24(1 downto 1) & l_2_c_0_cl_23(1 downto 1) & l_2_c_0_cl_22(1 downto 1) & l_2_c_0_cl_21(1 downto 1) & l_2_c_0_cl_20(1 downto 1) & l_2_c_0_cl_19(1 downto 1) & l_2_c_0_cl_18(1 downto 1) & l_2_c_0_cl_17(1 downto 1) & l_2_c_0_cl_16(1 downto 1) & l_2_c_0_cl_15(1 downto 1) & l_2_c_0_cl_14(1 downto 1) & l_2_c_0_cl_13(1 downto 1) & l_2_c_0_cl_12(1 downto 1) & l_2_c_0_cl_11(1 downto 1) & l_2_c_0_cl_10(1 downto 1) & l_2_c_0_cl_9(1 downto 1) & l_2_c_0_cl_8(1 downto 1) & l_2_c_0_cl_7(1 downto 1) & l_2_c_0_cl_6(1 downto 1) & l_2_c_0_cl_5(1 downto 1) & l_2_c_0_cl_4(1 downto 1) & l_2_c_0_cl_3(1 downto 1) & l_2_c_0_cl_2(1 downto 1) & l_2_c_0_cl_1(1 downto 1) & l_2_c_0_cl_0(1 downto 1) & "0";
FinalAdder_CompressorTree: IntAdder_106_f400_uid29 -- pipelineDepth=3 maxInDelay=2.03808e-09
port map ( clk => clk,
rst => rst,
Cin => '0',
R => myR,
X => l_2_s_0,
Y => l_2_s_1);
----------------Synchro barrier, entering cycle 3----------------
R <= myR;
-- delay at adder output 1.174e-09
end architecture;
--------------------------------------------------------------------------------
-- IntTruncMultiplier_53_53_106_unsigned
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Sebastian Banescu, Bogdan Pasca, Radu Tudoran (2010-2011)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
library work;
entity IntTruncMultiplier_53_53_106_unsigned is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
Y : in std_logic_vector(52 downto 0);
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntTruncMultiplier_53_53_106_unsigned is
component IntMultiAdder_106_op4_f400_uid25 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(105 downto 0);
X1 : in std_logic_vector(105 downto 0);
X2 : in std_logic_vector(105 downto 0);
X3 : in std_logic_vector(105 downto 0);
R : out std_logic_vector(105 downto 0) );
end component;
component LogicIntMultiplier_24_2_uid17_1 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(1 downto 0);
R : out std_logic_vector(25 downto 0) );
end component;
component LogicIntMultiplier_5_34_uid5_0 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(4 downto 0);
Y : in std_logic_vector(33 downto 0);
R : out std_logic_vector(38 downto 0) );
end component;
signal x0_0 : std_logic_vector(17 downto 0);
signal y0_0 : std_logic_vector(24 downto 0);
signal pxy00, pxy00_d1, pxy00_d2, pxy00_d3, pxy00_d4 : std_logic_vector(42 downto 0);
signal x0_1, x0_1_d1 : std_logic_vector(17 downto 0);
signal y0_1, y0_1_d1 : std_logic_vector(24 downto 0);
signal txy01 : std_logic_vector(42 downto 0);
signal pxy01, pxy01_d1, pxy01_d2, pxy01_d3 : std_logic_vector(42 downto 0);
signal x0_2, x0_2_d1, x0_2_d2 : std_logic_vector(24 downto 0);
signal y0_2, y0_2_d1, y0_2_d2 : std_logic_vector(17 downto 0);
signal txy02 : std_logic_vector(42 downto 0);
signal pxy02, pxy02_d1, pxy02_d2 : std_logic_vector(42 downto 0);
signal x0_3, x0_3_d1, x0_3_d2, x0_3_d3 : std_logic_vector(24 downto 0);
signal y0_3, y0_3_d1, y0_3_d2, y0_3_d3 : std_logic_vector(17 downto 0);
signal txy03 : std_logic_vector(42 downto 0);
signal pxy03, pxy03_d1 : std_logic_vector(42 downto 0);
signal addOpDSP0 : std_logic_vector(105 downto 0);
signal x3_0 : std_logic_vector(24 downto 0);
signal y3_0 : std_logic_vector(17 downto 0);
signal pxy30, pxy30_d1, pxy30_d2, pxy30_d3 : std_logic_vector(42 downto 0);
signal x3_1, x3_1_d1 : std_logic_vector(24 downto 0);
signal y3_1, y3_1_d1 : std_logic_vector(17 downto 0);
signal txy31 : std_logic_vector(42 downto 0);
signal pxy31, pxy31_d1, pxy31_d2 : std_logic_vector(42 downto 0);
signal x3_2, x3_2_d1, x3_2_d2 : std_logic_vector(24 downto 0);
signal y3_2, y3_2_d1, y3_2_d2 : std_logic_vector(17 downto 0);
signal txy32 : std_logic_vector(42 downto 0);
signal pxy32, pxy32_d1 : std_logic_vector(42 downto 0);
signal addOpDSP1, addOpDSP1_d1 : std_logic_vector(105 downto 0);
signal x_0 : std_logic_vector(4 downto 0);
signal y_0 : std_logic_vector(33 downto 0);
signal result0 : std_logic_vector(38 downto 0);
signal addOpSlice0, addOpSlice0_d1 : std_logic_vector(105 downto 0);
signal x_1 : std_logic_vector(23 downto 0);
signal y_1 : std_logic_vector(1 downto 0);
signal result1 : std_logic_vector(25 downto 0);
signal addOpSlice1, addOpSlice1_d1, addOpSlice1_d2, addOpSlice1_d3, addOpSlice1_d4 : std_logic_vector(105 downto 0);
signal addRes : std_logic_vector(105 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
pxy00_d1 <= pxy00;
pxy00_d2 <= pxy00_d1;
pxy00_d3 <= pxy00_d2;
pxy00_d4 <= pxy00_d3;
x0_1_d1 <= x0_1;
y0_1_d1 <= y0_1;
pxy01_d1 <= pxy01;
pxy01_d2 <= pxy01_d1;
pxy01_d3 <= pxy01_d2;
x0_2_d1 <= x0_2;
x0_2_d2 <= x0_2_d1;
y0_2_d1 <= y0_2;
y0_2_d2 <= y0_2_d1;
pxy02_d1 <= pxy02;
pxy02_d2 <= pxy02_d1;
x0_3_d1 <= x0_3;
x0_3_d2 <= x0_3_d1;
x0_3_d3 <= x0_3_d2;
y0_3_d1 <= y0_3;
y0_3_d2 <= y0_3_d1;
y0_3_d3 <= y0_3_d2;
pxy03_d1 <= pxy03;
pxy30_d1 <= pxy30;
pxy30_d2 <= pxy30_d1;
pxy30_d3 <= pxy30_d2;
x3_1_d1 <= x3_1;
y3_1_d1 <= y3_1;
pxy31_d1 <= pxy31;
pxy31_d2 <= pxy31_d1;
x3_2_d1 <= x3_2;
x3_2_d2 <= x3_2_d1;
y3_2_d1 <= y3_2;
y3_2_d2 <= y3_2_d1;
pxy32_d1 <= pxy32;
addOpDSP1_d1 <= addOpDSP1;
addOpSlice0_d1 <= addOpSlice0;
addOpSlice1_d1 <= addOpSlice1;
addOpSlice1_d2 <= addOpSlice1_d1;
addOpSlice1_d3 <= addOpSlice1_d2;
addOpSlice1_d4 <= addOpSlice1_d3;
end if;
end process;
----------------Synchro barrier, entering cycle 0----------------
----------------Synchro barrier, entering cycle 0----------------
x0_0 <= "0" & "" & X(11 downto 0) & "00000";
y0_0 <= "0" & "" & Y(18 downto 0) & "00000";
pxy00 <= x0_0(17 downto 0) * y0_0(24 downto 0); --0
----------------Synchro barrier, entering cycle 0----------------
x0_1 <= "0" & "" & X(28 downto 12) & "";
y0_1 <= "0" & "" & Y(18 downto 0) & "00000";
----------------Synchro barrier, entering cycle 1----------------
txy01 <= x0_1_d1(17 downto 0) * y0_1_d1(24 downto 0);
pxy01 <= (txy01(42 downto 0)) + ("00000000000000000" &pxy00_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
----------------Synchro barrier, entering cycle 0----------------
x0_2 <= "0" & "" & X(28 downto 5) & "";
y0_2 <= "0" & "" & Y(35 downto 19) & "";
----------------Synchro barrier, entering cycle 2----------------
txy02 <= x0_2_d2(24 downto 0) * y0_2_d2(17 downto 0);
pxy02 <= (txy02(42 downto 0)) + ("00000000000000000" &pxy01_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
----------------Synchro barrier, entering cycle 0----------------
x0_3 <= "0" & "" & X(28 downto 5) & "";
y0_3 <= "0" & "" & Y(52 downto 36) & "";
----------------Synchro barrier, entering cycle 3----------------
txy03 <= x0_3_d3(24 downto 0) * y0_3_d3(17 downto 0);
pxy03 <= (txy03(42 downto 0)) + ("00000000000000000" &pxy02_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
addOpDSP0 <= "000000000000000000000000" & pxy03_d1(40 downto 0) & pxy02_d2(16 downto 0) & pxy01_d3(16 downto 0) & pxy00_d4(16 downto 10) & "" & "";--3 bpadX 5 bpadY 5
----------------Synchro barrier, entering cycle 0----------------
----------------Synchro barrier, entering cycle 0----------------
x3_0 <= "0" & "" & X(52 downto 29) & "";
y3_0 <= "0" & "" & Y(18 downto 2) & "";
pxy30 <= x3_0(24 downto 0) * y3_0(17 downto 0); --0
----------------Synchro barrier, entering cycle 0----------------
x3_1 <= "0" & "" & X(52 downto 29) & "";
y3_1 <= "0" & "" & Y(35 downto 19) & "";
----------------Synchro barrier, entering cycle 1----------------
txy31 <= x3_1_d1(24 downto 0) * y3_1_d1(17 downto 0);
pxy31 <= (txy31(42 downto 0)) + ("00000000000000000" &pxy30_d1(42 downto 17));
----------------Synchro barrier, entering cycle 3----------------
----------------Synchro barrier, entering cycle 0----------------
x3_2 <= "0" & "" & X(52 downto 29) & "";
y3_2 <= "0" & "" & Y(52 downto 36) & "";
----------------Synchro barrier, entering cycle 2----------------
txy32 <= x3_2_d2(24 downto 0) * y3_2_d2(17 downto 0);
pxy32 <= (txy32(42 downto 0)) + ("00000000000000000" &pxy31_d1(42 downto 17));
----------------Synchro barrier, entering cycle 3----------------
addOpDSP1 <= "" & pxy32_d1(40 downto 0) & pxy31_d2(16 downto 0) & pxy30_d3(16 downto 0) & "0000000000000000000000000000000" & "";--3 bpadX 0 bpadY 0
----------------Synchro barrier, entering cycle 0----------------
x_0 <= X(4 downto 0);
y_0 <= Y(52 downto 19);
Mult0: LogicIntMultiplier_5_34_uid5_0 -- pipelineDepth=3 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => result0,
X => x_0,
Y => y_0);
----------------Synchro barrier, entering cycle 3----------------
addOpSlice0 <= "000000000000000000000000000000000000000000000000" & result0 & "0000000000000000000";
----------------Synchro barrier, entering cycle 0----------------
x_1 <= X(52 downto 29);
y_1 <= Y(1 downto 0);
Mult1: LogicIntMultiplier_24_2_uid17_1 -- pipelineDepth=0 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => result1,
X => x_1,
Y => y_1);
addOpSlice1 <= "000000000000000000000000000000000000000000000000000" & result1 & "00000000000000000000000000000";
----------------Synchro barrier, entering cycle 4----------------
adder: IntMultiAdder_106_op4_f400_uid25 -- pipelineDepth=3 maxInDelay=4.4472e-10
port map ( clk => clk,
rst => rst,
R => addRes,
X0 => addOpDSP0,
X1 => addOpDSP1_d1,
X2 => addOpSlice0_d1,
X3 => addOpSlice1_d4);
----------------Synchro barrier, entering cycle 7----------------
R <= addRes(105 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_65_f400_uid35
-- (IntAdderClassical_65_f400_uid37)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_65_f400_uid35 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(64 downto 0);
Y : in std_logic_vector(64 downto 0);
Cin : in std_logic;
R : out std_logic_vector(64 downto 0) );
end entity;
architecture arch of IntAdder_65_f400_uid35 is
signal x0 : std_logic_vector(10 downto 0);
signal y0 : std_logic_vector(10 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(11 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(11 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(11 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(12 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(10 downto 0);
y0 <= Y(10 downto 0);
x1 <= X(52 downto 11);
y1 <= Y(52 downto 11);
x2 <= X(64 downto 53);
y2 <= Y(64 downto 53);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(11);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(11 downto 0) & sum1_d1(41 downto 0) & sum0_d2(10 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPMultiplier_11_52_11_52_11_52_uid2
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin 2008-2011
--------------------------------------------------------------------------------
-- Pipeline depth: 11 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPMultiplier_11_52_11_52_11_52_uid2 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(11+52+2 downto 0);
Y : in std_logic_vector(11+52+2 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of FPMultiplier_11_52_11_52_11_52_uid2 is
component IntAdder_65_f400_uid35 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(64 downto 0);
Y : in std_logic_vector(64 downto 0);
Cin : in std_logic;
R : out std_logic_vector(64 downto 0) );
end component;
component IntTruncMultiplier_53_53_106_unsigned is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
Y : in std_logic_vector(52 downto 0);
R : out std_logic_vector(105 downto 0) );
end component;
signal sign, sign_d1, sign_d2, sign_d3, sign_d4, sign_d5, sign_d6, sign_d7, sign_d8, sign_d9, sign_d10, sign_d11 : std_logic;
signal expX : std_logic_vector(10 downto 0);
signal expY : std_logic_vector(10 downto 0);
signal expSumPreSub, expSumPreSub_d1 : std_logic_vector(12 downto 0);
signal bias, bias_d1 : std_logic_vector(12 downto 0);
signal expSum, expSum_d1, expSum_d2, expSum_d3, expSum_d4, expSum_d5, expSum_d6, expSum_d7 : std_logic_vector(12 downto 0);
signal sigX : std_logic_vector(52 downto 0);
signal sigY : std_logic_vector(52 downto 0);
signal sigProd : std_logic_vector(105 downto 0);
signal excSel : std_logic_vector(3 downto 0);
signal exc, exc_d1, exc_d2, exc_d3, exc_d4, exc_d5, exc_d6, exc_d7, exc_d8, exc_d9, exc_d10, exc_d11 : std_logic_vector(1 downto 0);
signal norm, norm_d1 : std_logic;
signal expPostNorm : std_logic_vector(12 downto 0);
signal sigProdExt, sigProdExt_d1, sigProdExt_d2 : std_logic_vector(105 downto 0);
signal expSig, expSig_d1 : std_logic_vector(64 downto 0);
signal sticky, sticky_d1 : std_logic;
signal guard : std_logic;
signal round : std_logic;
signal expSigPostRound : std_logic_vector(64 downto 0);
signal excPostNorm : std_logic_vector(1 downto 0);
signal finalExc : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
sign_d1 <= sign;
sign_d2 <= sign_d1;
sign_d3 <= sign_d2;
sign_d4 <= sign_d3;
sign_d5 <= sign_d4;
sign_d6 <= sign_d5;
sign_d7 <= sign_d6;
sign_d8 <= sign_d7;
sign_d9 <= sign_d8;
sign_d10 <= sign_d9;
sign_d11 <= sign_d10;
expSumPreSub_d1 <= expSumPreSub;
bias_d1 <= bias;
expSum_d1 <= expSum;
expSum_d2 <= expSum_d1;
expSum_d3 <= expSum_d2;
expSum_d4 <= expSum_d3;
expSum_d5 <= expSum_d4;
expSum_d6 <= expSum_d5;
expSum_d7 <= expSum_d6;
exc_d1 <= exc;
exc_d2 <= exc_d1;
exc_d3 <= exc_d2;
exc_d4 <= exc_d3;
exc_d5 <= exc_d4;
exc_d6 <= exc_d5;
exc_d7 <= exc_d6;
exc_d8 <= exc_d7;
exc_d9 <= exc_d8;
exc_d10 <= exc_d9;
exc_d11 <= exc_d10;
norm_d1 <= norm;
sigProdExt_d1 <= sigProdExt;
sigProdExt_d2 <= sigProdExt_d1;
expSig_d1 <= expSig;
sticky_d1 <= sticky;
end if;
end process;
sign <= X(63) xor Y(63);
expX <= X(62 downto 52);
expY <= Y(62 downto 52);
expSumPreSub <= ("00" & expX) + ("00" & expY);
bias <= CONV_STD_LOGIC_VECTOR(1023,13);
----------------Synchro barrier, entering cycle 1----------------
expSum <= expSumPreSub_d1 - bias_d1;
----------------Synchro barrier, entering cycle 0----------------
sigX <= "1" & X(51 downto 0);
sigY <= "1" & Y(51 downto 0);
SignificandMultiplication: IntTruncMultiplier_53_53_106_unsigned -- pipelineDepth=7 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => sigProd,
X => sigX,
Y => sigY);
----------------Synchro barrier, entering cycle 7----------------
----------------Synchro barrier, entering cycle 0----------------
excSel <= X(65 downto 64) & Y(65 downto 64);
with excSel select
exc <= "00" when "0000" | "0001" | "0100",
"01" when "0101",
"10" when "0110" | "1001" | "1010" ,
"11" when others;
----------------Synchro barrier, entering cycle 7----------------
norm <= sigProd(105);
----------------Synchro barrier, entering cycle 8----------------
-- exponent update
expPostNorm <= expSum_d7 + ("000000000000" & norm_d1);
----------------Synchro barrier, entering cycle 7----------------
-- significand normalization shift
sigProdExt <= sigProd(104 downto 0) & "0" when norm='1' else
sigProd(103 downto 0) & "00";
----------------Synchro barrier, entering cycle 8----------------
expSig <= expPostNorm & sigProdExt_d1(105 downto 54);
sticky <= sigProdExt_d1(53);
----------------Synchro barrier, entering cycle 9----------------
guard <= '0' when sigProdExt_d2(52 downto 0)="00000000000000000000000000000000000000000000000000000" else '1';
round <= sticky_d1 and ( (guard and not(sigProdExt_d2(54))) or (sigProdExt_d2(54) )) ;
RoundingAdder: IntAdder_65_f400_uid35 -- pipelineDepth=2 maxInDelay=1.57344e-09
port map ( clk => clk,
rst => rst,
Cin => round,
R => expSigPostRound ,
X => expSig_d1,
Y => "00000000000000000000000000000000000000000000000000000000000000000");
----------------Synchro barrier, entering cycle 11----------------
with expSigPostRound(64 downto 63) select
excPostNorm <= "01" when "00",
"10" when "01",
"00" when "11"|"10",
"11" when others;
with exc_d11 select
finalExc <= exc_d11 when "11"|"10"|"00",
excPostNorm when others;
R <= finalExc & sign_d11 & expSigPostRound(62 downto 0);
end architecture;
| apache-2.0 |
hoangt/PoC | tb/common/my_config_XUPV5.vhdl | 1 | 1645 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- XUPV5
--
--
-- License:
-- ===========================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
constant MY_BOARD : string := "XUPV5";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := false;
end my_config;
| apache-2.0 |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl_hs/CipherCore.vhd | 1 | 2944 | -------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @brief Cipher core template module
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
entity CipherCore is
generic (
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
begin
end structure; | apache-2.0 |
hoangt/PoC | src/mem/ocram/altera/ocram_sp_altera.vhdl | 2 | 3813 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiate single-port memory on Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- Quartus synthesis does not infer this RAM type correctly.
-- Instead, altsyncram is instantiated directly.
--
-- For further documentation see module "ocram_sp"
-- (src/mem/ocram/ocram_sp.vhdl).
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sp_altera is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocram_sp_altera is
component altsyncram
generic (
address_aclr_a : STRING;
indata_aclr_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL;
wrcontrol_aclr_a : STRING
);
port (
clocken0 : in STD_LOGIC;
wren_a : in STD_LOGIC;
clock0 : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0);
q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0);
data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0)
);
end component;
constant DEPTH : positive := 2**A_BITS;
constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME);
signal a_sl : std_logic_vector(A_BITS-1 downto 0);
begin
a_sl <= std_logic_vector(a);
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => "Stratix",
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
end architecture;
| apache-2.0 |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_tb/AEAD_TB.vhd | 1 | 22868 | -------------------------------------------------------------------------------
--! @file AEAD_TB.vhd
--! @brief Testbench for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.0b1
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity AEAD_TB IS
generic (
G_ASYNC_RSTN : boolean := False;
--! Test parameters
G_STOP_AT_FAULT : boolean := True;
G_TEST_MODE : integer := 0;
G_TEST_ISTALL : integer := 10;
G_TEST_OSTALL : integer := 10;
G_LOG2_FIFODEPTH : integer := 8;
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_PERIOD : time := 10 ns;
G_FNAME_PDI : string := "pdi.txt";
G_FNAME_SDI : string := "sdi.txt";
G_FNAME_DO : string := "do.txt";
G_FNAME_LOG : string := "log.txt";
G_FNAME_RESULT : string := "result.txt"
);
end AEAD_TB;
architecture behavior of AEAD_TB is
--! =================== --
--! SIGNALS DECLARATION --
--! =================== --
--! simulation signals (used by ATHENa script, ignore if not used)
signal simulation_fails : std_logic := '0';
signal stop_clock : boolean := False;
--! error check signal
signal global_stop : std_logic := '1';
--! globals
signal clk : std_logic := '0';
signal io_clk : std_logic := '0';
signal rst : std_logic := '0';
--! pdi
signal fpdi_din : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
signal fpdi_din_valid : std_logic := '0';
signal fpdi_din_ready : std_logic;
signal fpdi_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fpdi_dout_valid : std_logic;
signal fpdi_dout_ready : std_logic;
signal pdi_delayed : std_logic_vector(G_PWIDTH-1 downto 0);
signal pdi_valid : std_logic;
signal pdi_valid_selected : std_logic;
signal pdi_ready : std_logic;
--! sdi
signal fsdi_din : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
signal fsdi_din_valid : std_logic := '0';
signal fsdi_din_ready : std_logic;
signal fsdi_dout : std_logic_vector(G_SWIDTH-1 downto 0);
signal fsdi_dout_valid : std_logic;
signal fsdi_dout_ready : std_logic;
signal sdi_delayed : std_logic_vector(G_SWIDTH-1 downto 0);
signal sdi_valid : std_logic;
signal sdi_valid_selected : std_logic;
signal sdi_ready : std_logic;
--! do
signal do : std_logic_vector(G_PWIDTH-1 downto 0);
signal do_valid : std_logic;
signal do_ready : std_logic;
signal do_ready_selected : std_logic;
signal fdo_din_ready : std_logic;
signal fdo_din_valid : std_logic;
signal fdo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fdo_dout_valid : std_logic;
signal fdo_dout_ready : std_logic := '0';
--! Verification signals
signal stall_pdi_valid : std_logic := '0';
signal stall_sdi_valid : std_logic := '0';
signal stall_do_full : std_logic := '0';
------------- clock constant ------------------
constant clk_period : time := G_PERIOD;
constant io_clk_period : time := clk_period;
----------- end of clock constant -------------
------------- string constant ------------------
--! constant
constant cons_ins_out : string(1 to 6) := "# INS:";
constant cons_ins : string(1 to 6) := "INS = ";
constant cons_hdr : string(1 to 6) := "HDR = ";
constant cons_dat : string(1 to 6) := "DAT = ";
constant cons_stt : string(1 to 6) := "STT = ";
--! Shared constant
constant cons_eof : string(1 to 6) := "###EOF";
----------- end of string constant -------------
------------- debug constant ------------------
constant debug_input : boolean := False;
constant debug_output : boolean := False;
----------- end of clock constant -------------
-- ================= --
-- FILES DECLARATION --
-- ================= --
--------------- input / output files -------------------
file pdi_file : text open read_mode is G_FNAME_PDI;
file sdi_file : text open read_mode is G_FNAME_SDI;
file do_file : text open read_mode is G_FNAME_DO;
file log_file : text open write_mode is G_FNAME_LOG;
file result_file : text open write_mode is G_FNAME_RESULT;
------------- end of input files --------------------
begin
genClk: process
begin
if (not stop_clock and global_stop = '1') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process genClk;
genIOclk: process
begin
if ((not stop_clock) and (global_stop = '1')) then
io_clk <= '1';
wait for io_clk_period/2;
io_clk <= '0';
wait for io_clk_period/2;
else
wait;
end if;
end process genIOclk;
--! ============ --
--! PORT MAPPING --
--! ============ --
genPDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fpdi_din,
din_valid => fpdi_din_valid,
din_ready => fpdi_din_ready,
dout => fpdi_dout,
dout_valid => fpdi_dout_valid,
dout_ready => fpdi_dout_ready
);
fpdi_dout_ready <= '0' when stall_pdi_valid = '1' else pdi_ready;
pdi_valid_selected <= '1' when stall_pdi_valid = '1' else fpdi_dout_valid;
pdi_valid <= pdi_valid_selected after 1/4*clk_period;
pdi_delayed <= fpdi_dout after 1/4*clk_period;
genSDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_SWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fsdi_din,
din_valid => fsdi_din_valid,
din_ready => fsdi_din_ready,
dout => fsdi_dout,
dout_valid => fsdi_dout_valid,
dout_ready => fsdi_dout_ready
);
fsdi_dout_ready <= '0' when stall_sdi_valid = '1' else sdi_ready;
sdi_valid_selected <= '1' when stall_sdi_valid = '1' else fsdi_dout_valid;
sdi_valid <= sdi_valid_selected after 1/4*clk_period;
sdi_delayed <= fsdi_dout after 1/4*clk_period;
genDOfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => do,
din_valid => fdo_din_valid,
din_ready => fdo_din_ready,
dout => fdo_dout,
dout_valid => fdo_dout_valid,
dout_ready => fdo_dout_ready
);
fdo_din_valid <= '0' when stall_do_full = '1' else do_valid;
do_ready_selected <= '1' when stall_do_full = '1' else fdo_din_ready;
do_ready <= do_ready_selected after 1/4*clk_period;
uut: entity work.AEAD(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_SW => G_SWIDTH
)
port map (
rst => rst,
clk => clk,
pdi_data => pdi_delayed,
pdi_ready => pdi_ready,
pdi_valid => pdi_valid,
sdi_data => sdi_delayed,
sdi_ready => sdi_ready,
sdi_valid => sdi_valid,
do_data => do,
do_valid => do_valid,
do_ready => do_ready
);
--! =================== --
--! END OF PORT MAPPING --
--! =================== --
--! =======================================================================
--! ==================== DATA POPULATION FOR PUBLIC DATA ==================
tb_read_pdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
if (not G_ASYNC_RSTN) then
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
else
rst <= '0'; wait for 5*clk_period;
rst <= '1'; wait for clk_period;
end if;
--! read header
while ( not endfile (pdi_file)) and ( loop_enable = '1' ) loop
if endfile (pdi_file) then
loop_enable := '0';
end if;
readline(pdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( pdi_file ) loop
--! if the fifo is full, wait ...
fpdi_din_valid <= '1';
if ( fpdi_din_ready = '0' ) then
fpdi_din_valid <= '0';
wait until fpdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fpdi_din_valid <= '1';
end if;
hreadnew( line_data, word_block, read_result );
while (((read_result = False) or (valid_line = False))
and (not endfile( pdi_file )))
loop
readline(pdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fpdi_din_valid <= '1';
else
valid_line := False;
fpdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fpdi_din <= word_block;
wait for io_clk_period;
end loop;
fpdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! ==================== DATA POPULATION FOR SECRET DATA ==================
tb_read_sdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
--! Wait until reset is done
wait for 7*clk_period;
--! read header
while (not endfile (sdi_file)) and (loop_enable = '1') loop
if endfile (sdi_file) then
loop_enable := '0';
end if;
readline(sdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( sdi_file ) loop
--! if the fifo is full, wait ...
fsdi_din_valid <= '1';
if ( fsdi_din_ready = '0' ) then
fsdi_din_valid <= '0';
wait until fsdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fsdi_din_valid <= '1';
end if;
hreadnew(line_data, word_block, read_result);
while (((read_result = False) or (valid_line = False))
and (not endfile(sdi_file)))
loop
readline(sdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fsdi_din_valid <= '1';
else
valid_line := False;
fsdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fsdi_din <= word_block;
wait for io_clk_period;
end loop;
fsdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== DATA VERIFICATION =================================
tb_verifydata : process
variable line_no : integer := 0;
variable line_data : line;
variable logMsg : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
variable word_count : integer := 1;
variable word_pass : integer := 1;
variable instr : boolean := False;
variable force_exit : boolean := False;
variable msgid : integer;
variable keyid : integer ;
variable isEncrypt : boolean := False;
variable opcode : std_logic_vector(3 downto 0);
variable my_line : line; -- type 'line' comes from textio
begin
wait for 6*clk_period;
while (not endfile (do_file) and valid_line and (not force_exit)) loop
--! Keep reading new line until a valid line is found
hreadnew( line_data, word_block, read_result );
while ((read_result = False or valid_line = False)
and (not endfile(do_file)))
loop
readline(do_file, line_data);
line_no := line_no + 1;
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_hdr
or temp_read = cons_dat
or temp_read = cons_stt)
then
valid_line := True;
word_count := 1;
else
valid_line := False;
if (temp_read = cons_ins_out) then
instr := True;
end if;
end if;
if (temp_read = cons_eof) then
force_exit := True;
end if;
hreadnew(line_data, word_block, read_result); --! read data
if (instr = True) then
instr := False;
read_result := False;
opcode := word_block(G_PWIDTH-1 downto G_PWIDTH-4);
keyid := to_integer(unsigned(
word_block(G_PWIDTH+5-10 downto G_PWIDTH-10)));
msgid := to_integer(unsigned(
word_block(G_PWIDTH+5-16 downto G_PWIDTH-16)));
isEncrypt := False;
if ((opcode = OP_DEC or opcode = OP_ENC)
or (opcode = STAT_SUCCESS or opcode = STAT_FAILURE))
then
write(logMsg, string'("[Log] == Verifying msg ID #")
& integer'image(msgid)
& string'(" with key ID #") & integer'image(keyid));
if (opcode = OP_ENC) then
isEncrypt := True;
write(logMsg, string'(" for ENC"));
else
write(logMsg, string'(" for DEC"));
end if;
writeline(log_file,logMsg);
end if;
report "---------Started verifying message number "
& integer'image(msgid) & " at "
& time'image(now) severity note;
end if;
end loop;
--! if the core is slow in outputting the digested message, wait ...
if ( valid_line ) then
fdo_dout_ready <= '1';
if ( fdo_dout_valid = '0') then
fdo_dout_ready <= '0';
wait until fdo_dout_valid = '1';
wait for io_clk_period/2;
fdo_dout_ready <= '1';
end if;
word_pass := 1;
for i in G_PWIDTH-1 downto 0 loop
if fdo_dout(i) /= word_block(i)
and word_block(i) /= 'X'
then
word_pass := 0;
end if;
end loop;
if word_pass = 0 then
simulation_fails <= '1';
write(logMsg, string'("[Log] Msg ID #")
& integer'image(msgid)
& string'(" fails at line #") & integer'image(line_no)
& string'(" word #") & integer'image(word_count));
writeline(log_file,logMsg);
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout));
writeline(log_file,logMsg);
--! Stop the simulation right away when an error is detected
report "---------Data line #" & integer'image(line_no)
& " Msg ID #" & integer'image(msgid)
& " Key ID #" & integer'image(keyid)
& " Word #" & integer'image(word_count)
& " at " & time'image(now) & " FAILS T_T --------"
severity note;
report "Expected: " & to_hstring(word_block)
& " Actual: " & to_hstring(fdo_dout) severity note;
write(result_file, "fail");
if (G_STOP_AT_FAULT = True) then
force_exit := True;
else
if isEncrypt = False then
report "---------Skip to the next instruction"
& " at " & time'image(now) severity note;
write(logMsg,
string'("[Log] ...skips to next message ID"));
writeline(log_file, logMsg);
end if;
end if;
else
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout));
writeline(log_file,logMsg);
end if;
wait for io_clk_period;
word_count := word_count + 1;
end if;
end loop;
fdo_dout_ready <= '0';
wait for io_clk_period;
if (simulation_fails = '1') then
report "FAIL (1): SIMULATION FINISHED || Input/Output files :: T_T"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity error;
write(result_file, "1");
else
report "PASS (0): SIMULATION FINISHED || Input/Output files :: ^0^"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity note;
write(result_file, "0");
end if;
write(logMsg, string'("[Log] Done"));
writeline(log_file,logMsg);
stop_clock <= True;
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== Test MODE =========================================
genInputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
wait until rising_edge( pdi_ready );
wait for io_clk_period;
stall_pdi_valid <= '1';
stall_sdi_valid <= '1';
wait for io_clk_period*G_TEST_ISTALL;
stall_pdi_valid <= '0';
stall_sdi_valid <= '0';
else
wait;
end if;
end process;
genOutputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
wait until rising_edge( do_valid );
wait for io_clk_period;
stall_do_full <= '1';
wait for io_clk_period*G_TEST_OSTALL;
stall_do_full <= '0';
else
wait;
end if;
end process;
end;
| apache-2.0 |
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