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chiggs/oc_mkjpeg | design/JFIFGen/JFIFGen.vhd | 2 | 10100 | -------------------------------------------------------------------------------
-- File Name : JFIFGen.vhd
--
-- Project : JPEG_ENC
--
-- Module : JFIFGen
--
-- Content : JFIF Header Generator
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090309: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JFIFGen is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start : in std_logic;
ready : out std_logic;
eoi : in std_logic;
-- ByteStuffer
num_enc_bytes : in std_logic_vector(23 downto 0);
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JFIFGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JFIFGen is
constant C_SIZE_Y_H : integer := 25;
constant C_SIZE_Y_L : integer := 26;
constant C_SIZE_X_H : integer := 27;
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
signal hr_data : std_logic_vector(7 downto 0);
signal hr_waddr : std_logic_vector(9 downto 0);
signal hr_raddr : std_logic_vector(9 downto 0);
signal hr_we : std_logic;
signal hr_q : std_logic_vector(7 downto 0);
signal size_wr_cnt : unsigned(2 downto 0);
signal size_wr : std_logic;
signal rd_cnt : unsigned(9 downto 0);
signal rd_en : std_logic;
signal rd_en_d1 : std_logic;
signal rd_cnt_d1 : unsigned(rd_cnt'range);
signal rd_cnt_d2 : unsigned(rd_cnt'range);
signal eoi_cnt : unsigned(1 downto 0);
signal eoi_wr : std_logic;
signal eoi_wr_d1 : std_logic;
component HeaderRam is
port
(
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Header RAM
-------------------------------------------------------------------
U_Header_RAM : HeaderRam
port map
(
d => hr_data,
waddr => hr_waddr,
raddr => hr_raddr,
we => hr_we,
clk => CLK,
q => hr_q
);
hr_raddr <= std_logic_vector(rd_cnt);
-------------------------------------------------------------------
-- Host programming
-------------------------------------------------------------------
p_host_wr : process(CLK, RST)
begin
if RST = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '0';
hr_we <= '0';
hr_data <= (others => '0');
hr_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
hr_we <= '0';
if image_size_reg_wr = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '1';
end if;
-- write image size
if size_wr = '1' then
if size_wr_cnt = 4 then
size_wr_cnt <= (others => '0');
size_wr <= '0';
else
size_wr_cnt <= size_wr_cnt + 1;
hr_we <= '1';
case size_wr_cnt is
-- height H byte
when "000" =>
hr_data <= image_size_reg(15 downto 8);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
-- height L byte
when "001" =>
hr_data <= image_size_reg(7 downto 0);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
-- width H byte
when "010" =>
hr_data <= image_size_reg(31 downto 24);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
-- width L byte
when "011" =>
hr_data <= image_size_reg(23 downto 16);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
when others =>
null;
end case;
end if;
-- write Quantization table
elsif qwren = '1' then
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
end if;
end process;
-------------------------------------------------------------------
-- CTRL
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ready <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_cnt_d2 <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_en_d1 <= '0';
eoi_wr_d1 <= '0';
eoi_wr <= '0';
eoi_cnt <= (others => '0');
ram_wren <= '0';
ram_byte <= (others => '0');
ram_wraddr <= (others => '0');
elsif CLK'event and CLK = '1' then
ready <= '0';
rd_cnt_d1 <= rd_cnt;
rd_cnt_d2 <= rd_cnt_d1;
rd_en_d1 <= rd_en;
eoi_wr_d1 <= eoi_wr;
-- defaults: encoded data write
ram_wren <= rd_en_d1;
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
ram_byte <= hr_q;
-- start JFIF
if start = '1' and eoi = '0' then
rd_cnt <= (others => '0');
rd_en <= '1';
elsif start = '1' and eoi = '1' then
eoi_wr <= '1';
eoi_cnt <= (others => '0');
end if;
-- read JFIF Header
if rd_en = '1' then
if rd_cnt = C_HDR_SIZE-1 then
rd_en <= '0';
ready <= '1';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- EOI MARKER write
if eoi_wr = '1' then
if eoi_cnt = 2 then
eoi_cnt <= (others => '0');
eoi_wr <= '0';
ready <= '1';
else
eoi_cnt <= eoi_cnt + 1;
ram_wren <= '1';
if eoi_cnt = 0 then
ram_byte <= C_EOI(15 downto 8);
ram_wraddr <= num_enc_bytes;
elsif eoi_cnt = 1 then
ram_byte <= C_EOI(7 downto 0);
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
to_unsigned(1,ram_wraddr'length));
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 |
chiggs/oc_mkjpeg | tb/vhdl/GPL_V2_Image_pkg.vhd | 2 | 10277 | -----------------------------------------------------------------
-- Copyright (c) 1997 Ben Cohen. All rights reserved.
-- email: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation; either version 2 of the License,
-- or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
-- UPDATE: 8/22/02
-- Add to HexImage the supply of hex 'Z'
-- in the case statement when a binary set of 4 bits = "ZZZZ"
---------------------------------------------------------------
-- Note: 2006.08.11: (FB): modified package name to fit the structure of the
-- project and to highlight the license.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_TextIO.all;
use ieee.numeric_std.all;
-- use IEEE.Std_Logic_Arith.all;
library Std;
use STD.TextIO.all;
--package Image_Pkg is
package GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String;
function Image(In_Image : Bit) return String;
function Image(In_Image : Bit_Vector) return String;
function Image(In_Image : Integer) return String;
function Image(In_Image : Real) return String;
function Image(In_Image : Std_uLogic) return String;
function Image(In_Image : Std_uLogic_Vector) return String;
function Image(In_Image : Std_Logic_Vector) return String;
function Image(In_Image : Signed) return String;
function Image(In_Image : UnSigned) return String;
function HexImage(InStrg : String) return String;
function HexImage(In_Image : Bit_Vector) return String;
function HexImage(In_Image : Std_uLogic_Vector) return String;
function HexImage(In_Image : Std_Logic_Vector) return String;
function HexImage(In_Image : Signed) return String;
function HexImage(In_Image : UnSigned) return String;
function DecImage(In_Image : Bit_Vector) return String;
function DecImage(In_Image : Std_uLogic_Vector) return String;
function DecImage(In_Image : Std_Logic_Vector) return String;
function DecImage(In_Image : Signed) return String;
function DecImage(In_Image : UnSigned) return String;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
--package body Image_Pkg is
package body GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String is
variable L : Line; -- access type
variable W : String(1 to 14) := (others => ' ');
-- Long enough to hold a time string
begin
-- the WRITE procedure creates an object with "NEW".
-- L is passed as an output of the procedure.
Std.TextIO.WRITE(L, in_image);
-- Copy L.all onto W
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Integer) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Real) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_Logic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Signed) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function Image(In_Image : UnSigned) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function HexImage(InStrg : String) return String is
subtype Int03_Typ is Integer range 0 to 3;
variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
(others => '0');
variable StrTo4 : string(1 to Result'length * 4) :=
(others => '0');
variable MTspace : Int03_Typ; -- Empty space to fill in
variable Str4 : String(1 to 4);
variable Group_v : Natural := 0;
begin
MTspace := Result'length * 4 - InStrg'length;
StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
Cnvrt_Lbl : for I in Result'range loop
Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
case Str4 is
when "0000" => Result(I) := '0';
when "0001" => Result(I) := '1';
when "0010" => Result(I) := '2';
when "0011" => Result(I) := '3';
when "0100" => Result(I) := '4';
when "0101" => Result(I) := '5';
when "0110" => Result(I) := '6';
when "0111" => Result(I) := '7';
when "1000" => Result(I) := '8';
when "1001" => Result(I) := '9';
when "1010" => Result(I) := 'A';
when "1011" => Result(I) := 'B';
when "1100" => Result(I) := 'C';
when "1101" => Result(I) := 'D';
when "1110" => Result(I) := 'E';
when "1111" => Result(I) := 'F';
when "ZZZZ" => Result(I) := 'Z'; -- added 8/23/02
when others => Result(I) := 'X';
end case; -- Str4
end loop Cnvrt_Lbl;
return Result;
end HexImage;
function HexImage(In_Image : Bit_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_uLogic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_Logic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Signed) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : UnSigned) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function DecImage(In_Image : Bit_Vector) return String is
variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer
(Unsigned(To_StdLogicVector
(In_Image_v(31 downto 1)))));
else
return Image(To_integer(Unsigned(To_StdLogicVector(In_Image))));
end if;
end DecImage;
function DecImage(In_Image : Std_uLogic_Vector) return String is
variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Std_Logic_Vector) return String is
variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Signed) return String is
variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
function DecImage(In_Image : UnSigned) return String is
variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
| lgpl-3.0 |
Steve-Teal/1802-pico-basic | tiny_basic.vhd | 1 | 18578 | ---------------------------------------------------------------------------------------------------
-- TinyBasic ROM image as listed in MPM-203 "Evaluation Kit Manual for the RCA CDP1802"
-- Author: Tom Pittman
-- TinyBasic interpreter Copyright 1976 Itty Bitty Computers, used by permission
-- http://www.ittybittycomputers.com/IttyBitty/TinyBasic/
-- http://www.retrotechnology.com/memship/mship_tbasic.html
---------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tiny_basic is
port(
clock: in std_logic;
cs_n: in std_logic;
rd_n: in std_logic;
address: in std_logic_vector(10 downto 0);
data_out: out std_logic_vector(7 downto 0));
end tiny_basic;
architecture rtl of tiny_basic is
type rom_type is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom : rom_type := (
(X"01"),(X"30"),(X"B0"),(X"C0"),(X"00"),(X"ED"),(X"C0"),(X"06"),
(X"6F"),(X"C0"),(X"06"),(X"76"),(X"C0"),(X"06"),(X"66"),(X"5F"),
(X"18"),(X"82"),(X"80"),(X"20"),(X"30"),(X"22"),(X"30"),(X"20"),
(X"58"),(X"D5"),(X"06"),(X"81"),(X"08"),(X"C8"),(X"00"),(X"08"),
(X"48"),(X"38"),(X"97"),(X"BA"),(X"48"),(X"D5"),(X"C0"),(X"06"),
(X"51"),(X"D3"),(X"BF"),(X"E2"),(X"86"),(X"73"),(X"96"),(X"73"),
(X"83"),(X"A6"),(X"93"),(X"B6"),(X"46"),(X"B3"),(X"46"),(X"A3"),
(X"9F"),(X"30"),(X"29"),(X"D3"),(X"BF"),(X"E2"),(X"96"),(X"B3"),
(X"86"),(X"A3"),(X"12"),(X"42"),(X"B6"),(X"02"),(X"A6"),(X"9F"),
(X"30"),(X"3B"),(X"D3"),(X"43"),(X"AD"),(X"F8"),(X"08"),(X"BD"),
(X"4D"),(X"ED"),(X"30"),(X"4A"),(X"01"),(X"98"),(X"01"),(X"A0"),
(X"02"),(X"1F"),(X"01"),(X"DD"),(X"01"),(X"F0"),(X"01"),(X"D4"),
(X"04"),(X"81"),(X"02"),(X"49"),(X"00"),(X"ED"),(X"04"),(X"4E"),
(X"01"),(X"04"),(X"05"),(X"A2"),(X"01"),(X"D3"),(X"01"),(X"D3"),
(X"04"),(X"AA"),(X"01"),(X"D3"),(X"01"),(X"D3"),(X"02"),(X"C5"),
(X"02"),(X"D5"),(X"03"),(X"03"),(X"02"),(X"79"),(X"03"),(X"18"),
(X"05"),(X"3C"),(X"01"),(X"D3"),(X"04"),(X"29"),(X"03"),(X"6C"),
(X"03"),(X"CB"),(X"03"),(X"A7"),(X"03"),(X"98"),(X"03"),(X"9B"),
(X"04"),(X"0E"),(X"04"),(X"60"),(X"04"),(X"6D"),(X"05"),(X"81"),
(X"01"),(X"B6"),(X"02"),(X"67"),(X"03"),(X"48"),(X"03"),(X"4B"),
(X"01"),(X"D3"),(X"01"),(X"D3"),(X"01"),(X"C9"),(X"01"),(X"C5"),
(X"02"),(X"4E"),(X"02"),(X"44"),(X"02"),(X"41"),(X"01"),(X"D3"),
(X"F8"),(X"B3"),(X"A3"),(X"F8"),(X"00"),(X"B3"),(X"D3"),(X"BA"),
(X"F8"),(X"1C"),(X"AA"),(X"4A"),(X"B2"),(X"4A"),(X"A2"),(X"4A"),
(X"BD"),(X"F8"),(X"00"),(X"AD"),(X"0D"),(X"BF"),(X"E2"),(X"12"),
(X"F0"),(X"AF"),(X"FB"),(X"FF"),(X"52"),(X"F3"),(X"ED"),(X"C6"),
(X"9F"),(X"F3"),(X"FC"),(X"FF"),(X"8F"),(X"52"),(X"3B"),(X"C6"),
(X"22"),(X"0A"),(X"BD"),(X"F8"),(X"23"),(X"AD"),(X"82"),(X"73"),
(X"92"),(X"73"),(X"2A"),(X"2A"),(X"0A"),(X"73"),(X"8D"),(X"FB"),
(X"12"),(X"3A"),(X"E3"),(X"F6"),(X"C8"),(X"FF"),(X"00"),(X"F8"),
(X"F2"),(X"A3"),(X"F8"),(X"00"),(X"B3"),(X"D3"),(X"B4"),(X"B5"),
(X"B7"),(X"F8"),(X"2A"),(X"A4"),(X"F8"),(X"3C"),(X"A5"),(X"F8"),
(X"4B"),(X"A7"),(X"33"),(X"1A"),(X"D7"),(X"20"),(X"BB"),(X"4D"),
(X"AB"),(X"97"),(X"5B"),(X"1B"),(X"5B"),(X"D7"),(X"16"),(X"8B"),
(X"F4"),(X"BF"),(X"D7"),(X"24"),(X"9F"),(X"73"),(X"9B"),(X"7C"),
(X"00"),(X"73"),(X"D7"),(X"22"),(X"B2"),(X"4D"),(X"A2"),(X"D7"),
(X"26"),(X"82"),(X"73"),(X"92"),(X"73"),(X"D4"),(X"02"),(X"CC"),
(X"D7"),(X"1E"),(X"B9"),(X"4D"),(X"A9"),(X"E2"),(X"49"),(X"FF"),
(X"30"),(X"33"),(X"4B"),(X"FD"),(X"D7"),(X"33"),(X"85"),(X"FE"),
(X"FC"),(X"B0"),(X"A6"),(X"F8"),(X"2D"),(X"22"),(X"22"),(X"73"),
(X"93"),(X"73"),(X"97"),(X"B6"),(X"46"),(X"52"),(X"46"),(X"A6"),
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(X"DE"),(X"24"),(X"93"),(X"E0"),(X"23"),(X"1D"),(X"91"),(X"49"),
(X"C6"),(X"30"),(X"D0"),(X"31"),(X"1F"),(X"30"),(X"D0"),(X"84"),
(X"54"),(X"48"),(X"45"),(X"CE"),(X"1C"),(X"1D"),(X"38"),(X"0B"),
(X"9B"),(X"49"),(X"CE"),(X"83"),(X"50"),(X"55"),(X"D4"),(X"A0"),
(X"10"),(X"E7"),(X"24"),(X"3F"),(X"20"),(X"91"),(X"27"),(X"E1"),
(X"59"),(X"81"),(X"AC"),(X"30"),(X"D0"),(X"13"),(X"11"),(X"82"),
(X"AC"),(X"4D"),(X"E0"),(X"1D"),(X"8A"),(X"52"),(X"45"),(X"D4"),
(X"83"),(X"55"),(X"52"),(X"CE"),(X"E0"),(X"15"),(X"1D"),(X"85"),
(X"45"),(X"4E"),(X"C4"),(X"E0"),(X"2D"),(X"87"),(X"52"),(X"55"),
(X"CE"),(X"10"),(X"11"),(X"38"),(X"0A"),(X"84"),(X"4E"),(X"45"),
(X"D7"),(X"2B"),(X"9F"),(X"4C"),(X"49"),(X"53"),(X"D4"),(X"E7"),
(X"0A"),(X"00"),(X"01"),(X"0A"),(X"7F"),(X"FF"),(X"65"),(X"30"),
(X"D0"),(X"30"),(X"CB"),(X"E0"),(X"24"),(X"00"),(X"00"),(X"00"),
(X"00"),(X"00"),(X"00"),(X"0A"),(X"80"),(X"1F"),(X"24"),(X"93"),
(X"23"),(X"1D"),(X"84"),(X"52"),(X"45"),(X"CD"),(X"1D"),(X"A0"),
(X"80"),(X"BD"),(X"38"),(X"2A"),(X"82"),(X"AC"),(X"62"),(X"0B"),
(X"2F"),(X"85"),(X"AD"),(X"30"),(X"E6"),(X"17"),(X"64"),(X"81"),
(X"AB"),(X"30"),(X"E6"),(X"85"),(X"AB"),(X"30"),(X"E6"),(X"18"),
(X"5A"),(X"93"),(X"AD"),(X"30"),(X"E6"),(X"19"),(X"54"),(X"30"),
(X"F5"),(X"85"),(X"AA"),(X"30"),(X"F5"),(X"1A"),(X"5A"),(X"85"),
(X"AF"),(X"30"),(X"F5"),(X"1B"),(X"54"),(X"2F"),(X"88"),(X"52"),
(X"4E"),(X"44"),(X"A8"),(X"31"),(X"15"),(X"39"),(X"44"),(X"8E"),
(X"55"),(X"53"),(X"52"),(X"A8"),(X"30"),(X"D0"),(X"30"),(X"CB"),
(X"30"),(X"CB"),(X"31"),(X"1C"),(X"2E"),(X"2F"),(X"A2"),(X"12"),
(X"2F"),(X"C1"),(X"2F"),(X"80"),(X"A8"),(X"65"),(X"30"),(X"D0"),
(X"0B"),(X"80"),(X"AC"),(X"30"),(X"D0"),(X"80"),(X"A9"),(X"2F"),
(X"84"),(X"BD"),(X"09"),(X"02"),(X"2F"),(X"83"),(X"3C"),(X"BE"),
(X"74"),(X"85"),(X"3C"),(X"BD"),(X"09"),(X"03"),(X"2F"),(X"84"),
(X"BC"),(X"09"),(X"01"),(X"2F"),(X"85"),(X"3E"),(X"BD"),(X"09"),
(X"06"),(X"2F"),(X"85"),(X"3E"),(X"BC"),(X"09"),(X"05"),(X"2F"),
(X"80"),(X"BE"),(X"09"),(X"04"),(X"2F"),(X"19"),(X"17"),(X"0A"),
(X"00"),(X"01"),(X"18"),(X"09"),(X"80"),(X"09"),(X"80"),(X"12"),
(X"0A"),(X"09"),(X"29"),(X"1A"),(X"0A"),(X"1A"),(X"85"),(X"18"),
(X"08"),(X"13"),(X"09"),(X"80"),(X"12"),(X"03"),(X"01"),(X"02"),
(X"31"),(X"6A"),(X"31"),(X"75"),(X"1B"),(X"1A"),(X"19"),(X"31"),
(X"75"),(X"18"),(X"2F"),(X"0B"),(X"01"),(X"05"),(X"01"),(X"04"),
(X"0B"),(X"01"),(X"07"),(X"01"),(X"06"),(X"2F"),(X"0B"),(X"09"),
(X"06"),(X"0A"),(X"00"),(X"00"),(X"1C"),(X"17"),(X"2F"),(X"00"));
begin
process(clock)
begin
if(rising_edge(clock))then
if(rd_n = '0' and cs_n = '0')then
data_out <= rom(to_integer(unsigned(address)));
else
data_out <= "00000000";
end if;
end if;
end process;
end rtl;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/@e@x_@m@e@m/_primary.vhd | 1 | 1569 | library verilog;
use verilog.vl_types.all;
entity EX_MEM is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
Branch_addr_EX : in vl_logic_vector(31 downto 0);
op_EX : in vl_logic_vector(5 downto 0);
Condition_EX : in vl_logic_vector(2 downto 0);
Branch_EX : in vl_logic;
MemWrite_EX : in vl_logic;
RegWrite_EX : in vl_logic;
MemRead_EX : in vl_logic;
MemData_EX : in vl_logic_vector(31 downto 0);
WBData_EX : in vl_logic_vector(31 downto 0);
Less_EX : in vl_logic;
Zero_EX : in vl_logic;
Overflow_EX : in vl_logic;
Rd_EX : in vl_logic_vector(4 downto 0);
Branch_addr_MEM : out vl_logic_vector(31 downto 0);
op_MEM : out vl_logic_vector(5 downto 0);
Condition_MEM : out vl_logic_vector(2 downto 0);
Branch_MEM : out vl_logic;
MemWrite_MEM : out vl_logic;
RegWrite_MEM : out vl_logic;
MemRead_MEM : out vl_logic;
MemData_MEM : out vl_logic_vector(31 downto 0);
WBData_MEM : out vl_logic_vector(31 downto 0);
Less_MEM : out vl_logic;
Zero_MEM : out vl_logic;
Overflow_MEM : out vl_logic;
Rd_MEM : out vl_logic_vector(4 downto 0)
);
end EX_MEM;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/select2_5/_primary.vhd | 1 | 323 | library verilog;
use verilog.vl_types.all;
entity select2_5 is
port(
in1 : in vl_logic_vector(4 downto 0);
in2 : in vl_logic_vector(4 downto 0);
choose : in vl_logic;
\out\ : out vl_logic_vector(4 downto 0)
);
end select2_5;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/@f@o@r@w@a@r@d/_primary.vhd | 1 | 901 | library verilog;
use verilog.vl_types.all;
entity FORWARD is
port(
Rs_ID_EX : in vl_logic_vector(4 downto 0);
Rt_ID_EX : in vl_logic_vector(4 downto 0);
Rd_EX_MEM : in vl_logic_vector(4 downto 0);
Rs_IF_ID : in vl_logic_vector(4 downto 0);
Rt_IF_ID : in vl_logic_vector(4 downto 0);
Rd_MEM_REG : in vl_logic_vector(4 downto 0);
RegWrite_EX_MEM : in vl_logic;
RegWrite_MEM_REG: in vl_logic;
Rd_write_byte_en: in vl_logic_vector(3 downto 0);
loaduse : in vl_logic;
RsOut_sel : out vl_logic_vector(3 downto 0);
RtOut_sel : out vl_logic_vector(3 downto 0);
A_in_sel : out vl_logic_vector(7 downto 0);
B_in_sel : out vl_logic_vector(7 downto 0)
);
end FORWARD;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/select5_32/_primary.vhd | 1 | 536 | library verilog;
use verilog.vl_types.all;
entity select5_32 is
port(
in1 : in vl_logic_vector(31 downto 0);
in2 : in vl_logic_vector(31 downto 0);
in3 : in vl_logic_vector(31 downto 0);
in4 : in vl_logic_vector(31 downto 0);
in5 : in vl_logic_vector(31 downto 0);
choose : in vl_logic_vector(2 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
end select5_32;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/@i@f_@i@d/_primary.vhd | 1 | 1085 | library verilog;
use verilog.vl_types.all;
entity IF_ID is
port(
clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
PC_4_IF : in vl_logic_vector(31 downto 0);
op_IF : in vl_logic_vector(5 downto 0);
Rs_IF : in vl_logic_vector(4 downto 0);
Rt_IF : in vl_logic_vector(4 downto 0);
Rd_IF : in vl_logic_vector(4 downto 0);
Shamt_IF : in vl_logic_vector(4 downto 0);
Func_IF : in vl_logic_vector(5 downto 0);
PC_4_ID : out vl_logic_vector(31 downto 0);
op_ID : out vl_logic_vector(5 downto 0);
Rs_ID : out vl_logic_vector(4 downto 0);
Rt_ID : out vl_logic_vector(4 downto 0);
Rd_ID : out vl_logic_vector(4 downto 0);
Shamt_ID : out vl_logic_vector(4 downto 0);
Func_ID : out vl_logic_vector(5 downto 0)
);
end IF_ID;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/@p@c/_primary.vhd | 1 | 249 | library verilog;
use verilog.vl_types.all;
entity PC is
port(
PC_in : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
PC_out : out vl_logic_vector(31 downto 0)
);
end PC;
| lgpl-3.0 |
Jam-G/MIPS | simulation/modelsim/rtl_work/@m@e@m_@w@r/_primary.vhd | 1 | 896 | library verilog;
use verilog.vl_types.all;
entity MEM_WR is
port(
clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
MemData_Mem : in vl_logic_vector(31 downto 0);
Rd_write_byte_en_Mem: in vl_logic_vector(3 downto 0);
WBData_Mem : in vl_logic_vector(31 downto 0);
MemRead_Mem : in vl_logic;
RegWrite_Mem : in vl_logic;
Rd_Mem : in vl_logic_vector(4 downto 0);
MemData_Wr : out vl_logic_vector(31 downto 0);
Rd_write_byte_en_Wr: out vl_logic_vector(3 downto 0);
WBData_Wr : out vl_logic_vector(31 downto 0);
MemRead_Wr : out vl_logic;
RegWrite_Wr : out vl_logic;
Rd_Wr : out vl_logic_vector(4 downto 0)
);
end MEM_WR;
| lgpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/dma_fifo.vhd | 2 | 1812 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of dma_fifo is
constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1;
type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0);
signal data_fifo : MEM;
signal wr_addr : natural range 0 to FIFO_MAX;
signal rd_addr : natural range 0 to FIFO_MAX;
signal not_full, not_empty : Boolean;
begin
in_ack <= '1' when not_full else '0';
out_stb <= '1' when not_empty else '0';
out_data <= data_fifo(rd_addr);
fifo_data: process (clk) is
begin
if rising_edge(clk) then
if not_full then
data_fifo(wr_addr) <= in_data;
end if;
end if;
end process;
fifo_ctrl: process (clk) is
variable free_cnt : integer range 0 to FIFO_MAX + 1;
begin
if rising_edge(clk) then
if (resetn = '0') or (fifo_reset = '1') then
wr_addr <= 0;
rd_addr <= 0;
free_cnt := FIFO_MAX + 1;
not_empty <= False;
not_full <= True;
else
if in_stb = '1' and not_full then
wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt - 1;
end if;
if out_ack = '1' and not_empty then
rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt + 1;
end if;
not_full <= not (free_cnt = 0);
not_empty <= not (free_cnt = FIFO_MAX + 1);
end if;
end if;
end process;
end;
| lgpl-3.0 |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/GeneralGenerate.vhd | 1 | 659 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GeneralGenerate is
Port ( G_ik : in STD_LOGIC;
P_ik : in STD_LOGIC;
G_km1_j : in STD_LOGIC;
G_ij : out STD_LOGIC);
end GeneralGenerate;
architecture Behavioral of GeneralGenerate is
begin
G_ij <= G_ik OR (P_ik AND G_km1_j);
end Behavioral;
| lgpl-3.0 |
sandrosalvato94/System-Design-Project | VHDLs/constants.vhd | 1 | 568 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package CONSTANTS is
constant NUM_IPS : integer := 1;
constant DATA_WIDTH : integer := 16;
constant ADD_WIDTH : integer := 6;
type data_array is array (0 to NUM_IPS - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
type add_array is array (0 to NUM_IPS - 1) of std_logic_vector(ADD_WIDTH-1 downto 0);
constant INT_POS : integer := 13;
constant BE_POS : integer := 12;
constant IPADD_POS : integer := 11; -- downto 0
end package CONSTANTS;
| lgpl-3.0 |
sandrosalvato94/System-Design-Project | VHDLs/IPManager_HardwareGroup.vhd | 2 | 5201 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_MANAGER is
port(
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector (DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector (DATA_WIDTH-1 downto 0);
add : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
interrupt : out std_logic;
row_0 : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_in_IPs : in data_array;
data_out_IPs : out data_array;
add_IPs : in add_array;
W_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
R_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
generic_en_IPs : in std_logic_vector(0 to NUM_IPS-1);
enable_IPs : out std_logic_vector(0 to NUM_IPS-1);
ack_IPs : out std_logic_vector(0 to NUM_IPS-1);
interrupt_IPs : in std_logic_vector(0 to NUM_IPS-1)
);
end IP_MANAGER;
architecture BEHAVIOURAL of IP_MANAGER is
begin
-- PROC_1 manages the behavior of the IPMANAGER.
PROC_1: process (clk, rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
enable_IPs <= (others => '0');
ack_IPs <= (others => '0');
interrupt <= '0';
elsif Clk'event and Clk = '1' then -- rising clock edge
-- NOT configuration mode:
if (conv_integer(row_0(IPADD_POS downto 0)) /= 0 ) then
-- Assuring that only one IPs is enable in case the cpu decides to change the IP core without properly ending the transaction
enable_IPs <= (others => '0');
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
ack_IPs <= (others => '0');
-- Releasing interrupt:
if (row_0(INT_POS) = '1' AND row_0(BE_POS) = '1' )then
interrupt <= '0';
ack_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
end if;
-- Begin ( or continue ) transaction:
if row_0(BE_POS) = '1' then
enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
data_in <= data_in_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
data_out_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= data_out ;
add <= add_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
W_enable <= W_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
R_enable <= R_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
generic_en <= generic_en_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
-- Interrupt mode:
-- If some IPs raise the interrupt and there is no current transaction
elsif (row_0(BE_POS) = '0' and conv_integer(interrupt_IPs) /= 0 ) then
for I in (NUM_IPS-1) downto 0 loop -- scan from the lower priority IP to the higher (this avoid to insert a break statement, that is not synthesizable)
if (interrupt_IPs(I) = '1') then -- check if it rises the interrupt signal and the transaction with the Master is ended
--Write in row_0 the address of the ip with the highest priority
add <= (others => '0');
data_in <= row_0(DATA_WIDTH-1 downto 12) & conv_std_logic_vector(I+1, IPADD_POS+1);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
-- Signal the cpu that one interrupt request must be served
interrupt <= '1';
end if;
end loop;
end if;
---- TODO : Future feature
---- Manager configuration mode:
-- else
end if;
end if;
end process PROC_1;
end architecture; | lgpl-3.0 |
lunod/lt24_ctrl | rtl/rom_init_lt24.vhd | 1 | 9638 | ---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
-- Sources :
-- * Altera single port ROM template : https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/vhd-single-port-rom.html
-- * Terrasic LT24 exemple C code for Nios/2 (LT24 C initialization sequence
-- converted to hardware ROM)
-- * TFT LCD Display + Camera (René Beuchat, EPFL) : additional comments in
-- ROM initialization (comments ending with "*1" in rom_init_lt24.vhd) :
-- http://moodle.epfl.ch/pluginfile.php/1589089/mod_resource/content/3/TFT%20LCD%20Display-Camera_2a.pdf
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity rom_init_lt24 is
port(addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
q : out std_logic_vector(16 downto 0));
end entity;
---------------------------------------------------------------------------
architecture rtl of rom_init_lt24 is
-- Build a 2-D array type for the ROM
-- word size = q size, number of words = 2^nbits(addr)
subtype word_t is std_logic_vector(q'range);
type memory_t is array(0 to (2**addr'length) - 1) of word_t;
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
begin
-- Q[16]='1' if Q[15..0] destination is LT24 command register
-- Q[16]='0' if Q[15..0] destination is LT24 data register
-- Exit Sleep
tmp(000) := '0' & x"0011"; -- LCD_WR_REG(0x0011);
-- Power Control B *1
tmp(001) := '0' & x"00CF"; -- LCD_WR_REG(0x00CF);
tmp(002) := '1' & x"0000"; -- LCD_WR_DATA(0x0000); // Always 0x00 *1
tmp(003) := '1' & x"0081"; -- LCD_WR_DATA(0x0081);
tmp(004) := '1' & x"00C9"; -- LCD_WR_DATA(0X00c0);
-- Power on sequence control *1
tmp(005) := '0' & x"00ED"; -- LCD_WR_REG(0x00ED);
tmp(006) := '1' & x"0064"; -- LCD_WR_DATA(0x0064); // Soft Start keep 1
tmp(007) := '1' & x"0003"; -- LCD_WR_DATA(0x0003); // frame *1
tmp(008) := '1' & x"0012"; -- LCD_WR_DATA(0X0012);
tmp(009) := '1' & x"0081"; -- LCD_WR_DATA(0X0081);
-- TODO : Why 2 times ? Only once should be enough => test if need to optimize
-- (just one call in *1)
tmp(010) := '0' & x"00ED"; -- LCD_WR_REG(0x00ED);
tmp(011) := '1' & x"0064"; -- LCD_WR_DATA(0x0064);
tmp(012) := '1' & x"0003"; -- LCD_WR_DATA(0x0003);
tmp(013) := '1' & x"0012"; -- LCD_WR_DATA(0X0012);
tmp(014) := '1' & x"0081"; -- LCD_WR_DATA(0X0081);
-- Driver timing control A *1
tmp(015) := '0' & x"00E8"; -- LCD_WR_REG(0x00E8);
tmp(016) := '1' & x"0085"; -- LCD_WR_DATA(0x0085);
tmp(017) := '1' & x"0001"; -- LCD_WR_DATA(0x0001);
tmp(018) := '1' & x"0798"; -- LCD_WR_DATA(0x00798);
-- Power control A *1
tmp(019) := '0' & x"00CB"; -- LCD_WR_REG(0x00CB);
tmp(020) := '1' & x"0039"; -- LCD_WR_DATA(0x0039);
tmp(021) := '1' & x"002C"; -- LCD_WR_DATA(0x002C);
tmp(022) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(023) := '1' & x"0034"; -- LCD_WR_DATA(0x0034);
tmp(024) := '1' & x"0002"; -- LCD_WR_DATA(0x0002);
-- Pump ratio control *1
tmp(025) := '0' & x"00F7"; -- LCD_WR_REG(0x00F7);
tmp(026) := '1' & x"0020"; -- LCD_WR_DATA(0x0020);
-- Driver timming control B *1
tmp(027) := '0' & x"00EA"; -- LCD_WR_REG(0x00EA);
tmp(028) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(029) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
-- Frame control (in normal mode) *1
tmp(030) := '0' & x"00B1"; -- LCD_WR_REG(0x00B1);
tmp(031) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(032) := '1' & x"001b"; -- LCD_WR_DATA(0x001b);
-- Display function control *1
tmp(033) := '0' & x"00B6"; -- LCD_WR_REG(0x00B6);
tmp(034) := '1' & x"000A"; -- LCD_WR_DATA(0x000A);
tmp(035) := '1' & x"00A2"; -- LCD_WR_DATA(0x00A2);
-- Power control 1
tmp(036) := '0' & x"00C0"; -- LCD_WR_REG(0x00C0);
tmp(037) := '1' & x"0005"; -- LCD_WR_DATA(0x0005); // VRH[5:0]
-- Power control 2
tmp(038) := '0' & x"00C1"; -- LCD_WR_REG(0x00C1);
tmp(039) := '1' & x"0011"; -- LCD_WR_DATA(0x0011); // SAP[2:0]";BT[3:0]
-- VCM control 1
tmp(040) := '0' & x"00C5"; -- LCD_WR_REG(0x00C5);
tmp(041) := '1' & x"0045"; -- LCD_WR_DATA(0x0045); // 3F
tmp(042) := '1' & x"0045"; -- LCD_WR_DATA(0x0045); // 3C
-- VCM control 2
tmp(043) := '0' & x"00C7"; -- LCD_WR_REG(0x00C7);
tmp(044) := '1' & x"00a2"; -- LCD_WR_DATA(0X00a2);
-- Memory Access Control
tmp(045) := '0' & x"0036"; -- LCD_WR_REG(0x0036);
tmp(046) := '1' & x"0008"; -- LCD_WR_DATA(0x0008); // BGR order *1
-- Enable 3G *1
tmp(047) := '0' & x"00F2"; -- LCD_WR_REG(0x00F2); // 3Gamma Function Disable
tmp(048) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
-- Gama set *1
tmp(049) := '0' & x"0026"; -- LCD_WR_REG(0x0026); // Gamma curve selected
tmp(050) := '1' & x"0001"; -- LCD_WR_DATA(0x0001);
-- Positive gamma correction, set gamma *1
tmp(051) := '0' & x"00E0"; -- LCD_WR_REG(0x00E0);
tmp(052) := '1' & x"000F"; -- LCD_WR_DATA(0x000F);
tmp(053) := '1' & x"0026"; -- LCD_WR_DATA(0x0026);
tmp(054) := '1' & x"0024"; -- LCD_WR_DATA(0x0024);
tmp(055) := '1' & x"000b"; -- LCD_WR_DATA(0x000b);
tmp(056) := '1' & x"000E"; -- LCD_WR_DATA(0x000E);
tmp(057) := '1' & x"0008"; -- LCD_WR_DATA(0x0008);
tmp(058) := '1' & x"004b"; -- LCD_WR_DATA(0x004b);
TMP(059) := '1' & x"00a8"; -- LCD_WR_DATA(0X00a8);
tmp(060) := '1' & x"003b"; -- LCD_WR_DATA(0x003b);
tmp(061) := '1' & x"000a"; -- LCD_WR_DATA(0x000a);
tmp(062) := '1' & x"0014"; -- LCD_WR_DATA(0x0014);
tmp(063) := '1' & x"0006"; -- LCD_WR_DATA(0x0006);
tmp(064) := '1' & x"0010"; -- LCD_WR_DATA(0x0010);
tmp(065) := '1' & x"0009"; -- LCD_WR_DATA(0x0009);
tmp(066) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
-- Negative gamma correction, set gamma *1
tmp(067) := '0' & X"00E1"; -- LCD_WR_REG(0X00E1); // Set Gamma
tmp(068) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(069) := '1' & x"001c"; -- LCD_WR_DATA(0x001c);
tmp(070) := '1' & x"0020"; -- LCD_WR_DATA(0x0020);
tmp(071) := '1' & x"0004"; -- LCD_WR_DATA(0x0004);
tmp(072) := '1' & x"0010"; -- LCD_WR_DATA(0x0010);
tmp(073) := '1' & x"0008"; -- LCD_WR_DATA(0x0008);
tmp(074) := '1' & x"0034"; -- LCD_WR_DATA(0x0034);
tmp(075) := '1' & x"0047"; -- LCD_WR_DATA(0x0047);
tmp(076) := '1' & x"0044"; -- LCD_WR_DATA(0x0044);
tmp(077) := '1' & x"0005"; -- LCD_WR_DATA(0x0005);
tmp(078) := '1' & x"000b"; -- LCD_WR_DATA(0x000b);
tmp(079) := '1' & x"0009"; -- LCD_WR_DATA(0x0009);
tmp(080) := '1' & x"002f"; -- LCD_WR_DATA(0x002f);
tmp(081) := '1' & x"0036"; -- LCD_WR_DATA(0x0036);
tmp(082) := '1' & x"000f"; -- LCD_WR_DATA(0x000f);
-- Column address set *1
tmp(083) := '0' & x"002A"; -- LCD_WR_REG(0x002A);
tmp(084) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(085) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(086) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(087) := '1' & x"00ef"; -- LCD_WR_DATA(0x00ef);
-- Page address set *1
tmp(088) := '0' & x"002B"; -- LCD_WR_REG(0x002B);
tmp(089) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(090) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
tmp(091) := '1' & x"0001"; -- LCD_WR_DATA(0x0001);
tmp(092) := '1' & x"003f"; -- LCD_WR_DATA(0x003f);
-- COLMOD: pixel format set *1
tmp(093) := '0' & x"003A"; -- LCD_WR_REG(0x003A);
tmp(094) := '1' & x"0055"; -- LCD_WR_DATA(0x0055);
-- Interface control *1
tmp(095) := '0' & x"00f6"; -- LCD_WR_REG(0x00f6);
tmp(096) := '1' & x"0001"; -- LCD_WR_DATA(0x0001);
tmp(097) := '1' & x"0030"; -- LCD_WR_DATA(0x0030);
tmp(098) := '1' & x"0000"; -- LCD_WR_DATA(0x0000);
-- display on
tmp(099) := '0' & x"0029"; -- LCD_WR_REG(0x0029);
-- 0x2C
tmp(100) := '0' & x"002c"; -- LCD_WR_REG(0x002c);
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(to_integer(unsigned(addr)));
end if;
end process;
end rtl;
---------------------------------------------------------------------------
| lgpl-3.0 |
lunod/lt24_ctrl | rtl/lt24ctrl.vhd | 1 | 5713 | ---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
-- Remarks :
-- * LT24 is a 320x240 LCD screen but the integrated controller considers
-- a 240x320 display with x=0 and y=0 the pixel on the top left when the
-- screen is held vertically with PCB text "terasic LT24" on the right
-- side.
-- Hence the choice to provide an interface with y=320 lines of x=240
-- pixels.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------------------------
entity lt24ctrl is
generic(system_frequency: real := 50_000_000.0;
tmin_cycles : natural := 1);
port (
clk : in std_logic;
resetn : in std_logic;
x : out std_logic_vector(7 downto 0); -- 0 .. 239 => 8 bits
y : out std_logic_vector(8 downto 0); -- 0 .. 319 => 9 bits
c : in std_logic_vector(15 downto 0); -- couleurs 16 bits
lt24_reset_n: out std_logic;
lt24_cs_n : out std_logic;
lt24_rs : out std_logic;
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_d : out std_logic_vector(15 downto 0);
lt24_lcd_on : out std_logic);
end entity lt24ctrl;
---------------------------------------------------------------------------
architecture inst of lt24ctrl is
signal rom_addr : std_logic_vector(6 downto 0);
signal rom_data : std_logic_vector(16 downto 0);
signal clr_cptdelay, tick_1ms, tick_10ms,
tick_120ms, tick_tmin : std_logic;
signal clr_init_rom_addr, inc_init_rom_addr,
end_init_rom : std_logic;
signal clr_cptpix, inc_cptpix, end_cptpix : std_logic;
signal lt24_reset_n_noreg, lt24_cs_n_noreg,
lt24_rs_noreg, lt24_rd_n_noreg,
lt24_wr_n_noreg, lt24_lcd_on_noreg : std_logic;
signal lt24_d_noreg : std_logic_vector(lt24_d'range);
begin
rom: entity work.rom_init_lt24
port map(
clk => clk,
addr => rom_addr,
q => rom_data);
cpt_timming: entity work.cpt_delay
generic map(system_frequency => system_frequency,
tmin_cycles => tmin_cycles)
port map(clk => clk,
resetn => resetn,
clr_cptdelay => clr_cptdelay,
tick_1ms => tick_1ms,
tick_10ms => tick_10ms,
tick_120ms => tick_120ms,
tick_tmin => tick_tmin);
cpt_address: entity work.cpt_addr_rom
port map(clk => clk,
resetn => resetn,
clr_init_rom_addr => clr_init_rom_addr,
inc_init_rom_addr => inc_init_rom_addr,
end_init_rom => end_init_rom,
address => rom_addr);
cpt_pixels: entity work.cpt_pix
port map(clk => clk,
resetn => resetn,
clr_cptpix => clr_cptpix,
inc_cptpix => inc_cptpix,
end_cptpix => end_cptpix,
x => x,
y => y);
fsm: entity work.lt24_fsm
port map(clk => clk,
resetn => resetn,
tick_1ms => tick_1ms,
tick_10ms => tick_10ms,
tick_120ms => tick_120ms,
tick_tmin => tick_tmin,
clr_cptdelay => clr_cptdelay,
clr_init_rom_addr => clr_init_rom_addr,
inc_init_rom_addr => inc_init_rom_addr,
end_init_rom => end_init_rom,
init_rom_data => rom_data,
clr_cptpix => clr_cptpix,
inc_cptpix => inc_cptpix,
end_cptpix => end_cptpix,
color => c,
lt24_reset_n => lt24_reset_n_noreg,
lt24_lcd_on => lt24_lcd_on_noreg,
lt24_cs_n => lt24_cs_n_noreg,
lt24_rs => lt24_rs_noreg,
lt24_rd_n => lt24_rd_n_noreg,
lt24_wr_n => lt24_wr_n_noreg,
lt24_d => lt24_d_noreg);
-- Register outputs to relax timming delays and have clean/glitchless
-- outputs from the FPGA to LT24
sync_out:process(clk)
begin
if rising_edge(clk) then
lt24_reset_n <= lt24_reset_n_noreg;
lt24_cs_n <= lt24_cs_n_noreg;
lt24_rs <= lt24_rs_noreg;
lt24_rd_n <= lt24_rd_n_noreg;
lt24_wr_n <= lt24_wr_n_noreg;
lt24_d <= lt24_d_noreg;
lt24_lcd_on <= lt24_lcd_on_noreg;
end if;
end process;
end architecture inst;
---------------------------------------------------------------------------
| lgpl-3.0 |
LaNoC-UFC/Phoenix | outputModule.vhd | 2 | 3392 | library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
entity outputModule is
generic(
address: regflit
);
port(
clock: in std_logic;
tx: in std_logic;
data: in regflit;
currentTime: in unsigned(4*TAM_FLIT-1 downto 0)
);
end;
architecture outputModule of outputModule is
begin
process(clock)
variable current_flit_index : integer := 0;
variable package_size : unsigned(TAM_FLIT-1 downto 0) := (others=>'0');
file file_pointer : TEXT;
variable fstatus: file_open_status := STATUS_ERROR;
variable current_line : LINE;
variable desired_input_time: unsigned ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable actual_input_time: unsigned ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable tail_arrival_time: unsigned ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable package_latency: integer;
variable is_control_package: std_logic;
begin
if (clock'event and clock = '0') then
if tx = '1' then
-- head
if (current_flit_index = 0) then
write(current_line, string'(to_hstring(data)) & " ");
is_control_package := data(TAM_FLIT-1);
-- size
elsif (current_flit_index = 1) then
write(current_line, string'(to_hstring(data)) & " ");
package_size := unsigned(data) + 2;
-- payload
elsif (current_flit_index < package_size - 1) then
if (current_flit_index >= 3 and current_flit_index <= 6 and is_control_package = '0') then
desired_input_time((TAM_FLIT*(7-current_flit_index)-1) downto (TAM_FLIT*(6-current_flit_index))) := unsigned(data);
end if;
if (current_flit_index >= 9 and current_flit_index <= 12 and is_control_package = '0') then
actual_input_time((TAM_FLIT*(13-current_flit_index)-1) downto (TAM_FLIT*(12-current_flit_index))) := unsigned(data);
end if;
if (current_flit_index = 2 or current_flit_index = 7 or current_flit_index = 8) then
write(current_line, string'(to_hstring(data)) & " ");
end if;
-- tail
else
if (is_control_package = '0') then
tail_arrival_time := currentTime;
write(current_line, " " & string'(integer'image(to_integer(signed(actual_input_time)))));
package_latency := to_integer(signed(tail_arrival_time-desired_input_time));
write(current_line, " " & string'(integer'image(package_latency)));
if(fstatus /= OPEN_OK) then
file_open(fstatus, file_pointer,"Out/out"&to_hstring(address)&".txt",WRITE_MODE);
end if;
writeline(file_pointer, current_line);
end if;
current_flit_index := -1;
end if;
current_flit_index := current_flit_index + 1;
end if;
end if;
end process;
end outputModule;
| lgpl-3.0 |
LaNoC-UFC/Phoenix | tests/fault_injector_test.vhd | 2 | 1836 | library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
entity fault_injector_test is
end;
architecture fault_injector_test of fault_injector_test is
constant NUMBER_ITERACTIONS : integer := 1000;
signal clock: std_logic := '0';
signal reset: std_logic;
signal tx: regNport := (others=>'0');
signal data_in: arrayNport_regphit := (others=>(others=>'0'));
signal data_out: arrayNport_regphit;
signal credit: regNport := (others=>'0');
begin
reset <= '1', '0' after CLOCK_PERIOD/4;
clock <= not clock after CLOCK_PERIOD/2;
UUT : entity work.FaultInjector
generic map(address => ADDRESS_FROM_INDEX(0))
port map(
clock => clock,
reset => reset,
tx => tx,
data_in => data_in,
data_out => data_out,
credit => credit
);
process
variable fault_count : integer := 0;
file file_pointer : text;
variable port_line : LINE;
begin
-- write file with desired fault rate
file_open(file_pointer, "fault_" & to_hstring(ADDRESS_FROM_INDEX(0)) & ".txt", WRITE_MODE);
write(port_line, string'("0.03 EAST"));
writeline(file_pointer, port_line);
file_close(file_pointer);
tx(EAST) <= '1';
credit(EAST) <= '1';
wait until reset = '0';
for i in 1 to NUMBER_ITERACTIONS loop
wait until clock'event and clock = '1';
if data_in(EAST) /= data_out(EAST) then
fault_count := fault_count + 1;
end if;
end loop;
report "Percentage of fault = " & real'image((real(fault_count)*100.0)/real(NUMBER_ITERACTIONS)) & "%.";
wait;
end process;
end fault_injector_test;
| lgpl-3.0 |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/config_pkg.vhd | 1 | 3976 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : config_pkg.vhd
-- Design name : config_pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package config_pkg is
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
constant CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
constant CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
constant CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2;
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_pkg;
| lgpl-3.0 |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/gprf.vhd | 1 | 2990 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
begin
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
end arch;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.vhd | 3 | 9502 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/sample_buffer_if_ap_fifo.vhd | 2 | 2831 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/sample_buffer_if_plb_master_if.vhd | 4 | 36941 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if_plb_master_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_forward_buckets_if.vhd | 2 | 27928 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_forward_buckets_if is
component nfa_forward_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_forward_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_forward_buckets_if_plb_master_if: component nfa_forward_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_forward_buckets_if_rd_data_user_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if.vhd | 2 | 21298 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_initials_buckets_if OF nfa_initials_buckets_if IS
component nfa_initials_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_initials_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_initials_buckets_if_req_fifo: component nfa_initials_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_initials_buckets_if_rsp_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_initials_buckets_if_rd_fifo: component nfa_initials_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_initials_buckets_if_rd_user_fifo: component nfa_initials_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_initials_buckets_if;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_forward_buckets_if_async_fifo.vhd | 1 | 5843 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nfa_forward_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : in std_logic;
clk_r : in std_logic;
reset : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_full_n : out std_logic;
if_write_ce: in std_logic := '1';
if_write : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic := '1';
if_read : in std_logic);
function calc_addr_width(x : integer) return integer is
begin
if (x < 1) then
return 1;
else
return x;
end if;
end function;
end entity;
architecture rtl of nfa_forward_buckets_if_async_fifo is
constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH);
constant REAL_DEPTH : integer := 2 ** DEPTH_BITS;
constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1');
constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1));
type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal full : std_logic := '0';
signal empty : std_logic := '1';
signal full_next : std_logic;
signal empty_next : std_logic;
signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of mem : signal is "block";
begin
if_full_n <= not full;
if_empty_n <= not empty;
if_dout <= dout_buf;
full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0';
empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0';
wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0);
rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0);
wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin;
rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin;
wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1);
rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1);
-- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2
-- @ clk_w domain
process(clk_w, reset) begin
if (reset = '1') then
full <= '0';
wraddr_bin <= (others => '0');
wraddr_gray_sync0 <= (others => '0');
rdaddr_gray_sync1 <= (others => '0');
rdaddr_gray_sync2 <= (others => '0');
elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then
full <= full_next;
wraddr_bin <= wraddr_bin_next;
wraddr_gray_sync0 <= wraddr_gray_next;
rdaddr_gray_sync1 <= rdaddr_gray_sync0;
rdaddr_gray_sync2 <= rdaddr_gray_sync1;
end if;
end process;
-- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2
-- @ clk_r domain
process(clk_r, reset) begin
if (reset = '1') then
empty <= '1';
rdaddr_bin <= (others => '0');
rdaddr_gray_sync0 <= (others => '0');
wraddr_gray_sync1 <= (others => '0');
wraddr_gray_sync2 <= (others => '0');
elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then
empty <= empty_next;
rdaddr_bin <= rdaddr_bin_next;
rdaddr_gray_sync0 <= rdaddr_gray_next;
wraddr_gray_sync1 <= wraddr_gray_sync0;
wraddr_gray_sync2 <= wraddr_gray_sync1;
end if;
end process;
-- write mem
process(clk_w) begin
if (clk_w'event and clk_w = '1' and if_write_ce = '1') then
if (full = '0' and if_write = '1') then
mem(to_integer(unsigned(wraddr))) <= if_din;
end if;
end if;
end process;
-- read mem
process(clk_r) begin
if (clk_r'event and clk_r = '1' and if_read_ce = '1') then
dout_buf <= mem(to_integer(unsigned(rdaddr)));
end if;
end process;
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_sram_wrapper.vhd | 1 | 18426 | -------------------------------------------------------------------------------
-- system_sram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc_v3_01_a.all;
entity system_sram_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Mem_DQ_I : in std_logic_vector(0 to 31);
Mem_DQ_O : out std_logic_vector(0 to 31);
Mem_DQ_T : out std_logic_vector(0 to 31);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 3);
Mem_BEN : out std_logic_vector(0 to 3);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_sram_wrapper : entity is "xps_mch_emc_v3_01_a";
end system_sram_wrapper;
architecture STRUCTURE of system_sram_wrapper is
component xps_mch_emc is
generic (
C_FAMILY : STRING;
C_NUM_BANKS_MEM : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_PRIORITY_MODE : INTEGER;
C_INCLUDE_PLB_IPIF : INTEGER;
C_INCLUDE_WRBUF : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MCH_SPLB_AWIDTH : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_MCH_NATIVE_DWIDTH : INTEGER;
C_MCH_SPLB_CLK_PERIOD_PS : INTEGER;
C_MEM0_BASEADDR : std_logic_vector;
C_MEM0_HIGHADDR : std_logic_vector;
C_MEM1_BASEADDR : std_logic_vector;
C_MEM1_HIGHADDR : std_logic_vector;
C_MEM2_BASEADDR : std_logic_vector;
C_MEM2_HIGHADDR : std_logic_vector;
C_MEM3_BASEADDR : std_logic_vector;
C_MEM3_HIGHADDR : std_logic_vector;
C_PAGEMODE_FLASH_0 : INTEGER;
C_PAGEMODE_FLASH_1 : INTEGER;
C_PAGEMODE_FLASH_2 : INTEGER;
C_PAGEMODE_FLASH_3 : INTEGER;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_SYNCH_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_SYNCH_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_SYNCH_MEM_3 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_MCH0_PROTOCOL : INTEGER;
C_MCH0_ACCESSBUF_DEPTH : INTEGER;
C_MCH0_RDDATABUF_DEPTH : INTEGER;
C_MCH1_PROTOCOL : INTEGER;
C_MCH1_ACCESSBUF_DEPTH : INTEGER;
C_MCH1_RDDATABUF_DEPTH : INTEGER;
C_MCH2_PROTOCOL : INTEGER;
C_MCH2_ACCESSBUF_DEPTH : INTEGER;
C_MCH2_RDDATABUF_DEPTH : INTEGER;
C_MCH3_PROTOCOL : INTEGER;
C_MCH3_ACCESSBUF_DEPTH : INTEGER;
C_MCH3_RDDATABUF_DEPTH : INTEGER;
C_XCL0_LINESIZE : INTEGER;
C_XCL0_WRITEXFER : INTEGER;
C_XCL1_LINESIZE : INTEGER;
C_XCL1_WRITEXFER : INTEGER;
C_XCL2_LINESIZE : INTEGER;
C_XCL2_WRITEXFER : INTEGER;
C_XCL3_LINESIZE : INTEGER;
C_XCL3_WRITEXFER : INTEGER
);
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1));
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
begin
SRAM : xps_mch_emc
generic map (
C_FAMILY => "virtex5",
C_NUM_BANKS_MEM => 1,
C_NUM_CHANNELS => 0,
C_PRIORITY_MODE => 0,
C_INCLUDE_PLB_IPIF => 1,
C_INCLUDE_WRBUF => 1,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_P2P => 0,
C_SPLB_DWIDTH => 64,
C_MCH_SPLB_AWIDTH => 32,
C_SPLB_SMALLEST_MASTER => 32,
C_MCH_NATIVE_DWIDTH => 32,
C_MCH_SPLB_CLK_PERIOD_PS => 8000,
C_MEM0_BASEADDR => X"9af00000",
C_MEM0_HIGHADDR => X"9affffff",
C_MEM1_BASEADDR => X"ffffffff",
C_MEM1_HIGHADDR => X"00000000",
C_MEM2_BASEADDR => X"ffffffff",
C_MEM2_HIGHADDR => X"00000000",
C_MEM3_BASEADDR => X"ffffffff",
C_MEM3_HIGHADDR => X"00000000",
C_PAGEMODE_FLASH_0 => 0,
C_PAGEMODE_FLASH_1 => 0,
C_PAGEMODE_FLASH_2 => 0,
C_PAGEMODE_FLASH_3 => 0,
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_MEM0_WIDTH => 32,
C_MEM1_WIDTH => 32,
C_MEM2_WIDTH => 32,
C_MEM3_WIDTH => 32,
C_MAX_MEM_WIDTH => 32,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 0,
C_SYNCH_MEM_0 => 1,
C_SYNCH_PIPEDELAY_0 => 2,
C_TCEDV_PS_MEM_0 => 0,
C_TAVDV_PS_MEM_0 => 0,
C_TPACC_PS_FLASH_0 => 25000,
C_THZCE_PS_MEM_0 => 0,
C_THZOE_PS_MEM_0 => 0,
C_TWC_PS_MEM_0 => 0,
C_TWP_PS_MEM_0 => 0,
C_TLZWE_PS_MEM_0 => 0,
C_SYNCH_MEM_1 => 0,
C_SYNCH_PIPEDELAY_1 => 2,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_SYNCH_MEM_2 => 0,
C_SYNCH_PIPEDELAY_2 => 2,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_SYNCH_MEM_3 => 0,
C_SYNCH_PIPEDELAY_3 => 2,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_MCH0_PROTOCOL => 0,
C_MCH0_ACCESSBUF_DEPTH => 16,
C_MCH0_RDDATABUF_DEPTH => 16,
C_MCH1_PROTOCOL => 0,
C_MCH1_ACCESSBUF_DEPTH => 16,
C_MCH1_RDDATABUF_DEPTH => 16,
C_MCH2_PROTOCOL => 0,
C_MCH2_ACCESSBUF_DEPTH => 16,
C_MCH2_RDDATABUF_DEPTH => 16,
C_MCH3_PROTOCOL => 0,
C_MCH3_ACCESSBUF_DEPTH => 16,
C_MCH3_RDDATABUF_DEPTH => 16,
C_XCL0_LINESIZE => 4,
C_XCL0_WRITEXFER => 1,
C_XCL1_LINESIZE => 4,
C_XCL1_WRITEXFER => 1,
C_XCL2_LINESIZE => 4,
C_XCL2_WRITEXFER => 1,
C_XCL3_LINESIZE => 4,
C_XCL3_WRITEXFER => 1
)
port map (
MCH_SPLB_Clk => MCH_SPLB_Clk,
RdClk => RdClk,
MCH_SPLB_Rst => MCH_SPLB_Rst,
MCH0_Access_Control => MCH0_Access_Control,
MCH0_Access_Data => MCH0_Access_Data,
MCH0_Access_Write => MCH0_Access_Write,
MCH0_Access_Full => MCH0_Access_Full,
MCH0_ReadData_Control => MCH0_ReadData_Control,
MCH0_ReadData_Data => MCH0_ReadData_Data,
MCH0_ReadData_Read => MCH0_ReadData_Read,
MCH0_ReadData_Exists => MCH0_ReadData_Exists,
MCH1_Access_Control => MCH1_Access_Control,
MCH1_Access_Data => MCH1_Access_Data,
MCH1_Access_Write => MCH1_Access_Write,
MCH1_Access_Full => MCH1_Access_Full,
MCH1_ReadData_Control => MCH1_ReadData_Control,
MCH1_ReadData_Data => MCH1_ReadData_Data,
MCH1_ReadData_Read => MCH1_ReadData_Read,
MCH1_ReadData_Exists => MCH1_ReadData_Exists,
MCH2_Access_Control => MCH2_Access_Control,
MCH2_Access_Data => MCH2_Access_Data,
MCH2_Access_Write => MCH2_Access_Write,
MCH2_Access_Full => MCH2_Access_Full,
MCH2_ReadData_Control => MCH2_ReadData_Control,
MCH2_ReadData_Data => MCH2_ReadData_Data,
MCH2_ReadData_Read => MCH2_ReadData_Read,
MCH2_ReadData_Exists => MCH2_ReadData_Exists,
MCH3_Access_Control => MCH3_Access_Control,
MCH3_Access_Data => MCH3_Access_Data,
MCH3_Access_Write => MCH3_Access_Write,
MCH3_Access_Full => MCH3_Access_Full,
MCH3_ReadData_Control => MCH3_ReadData_Control,
MCH3_ReadData_Data => MCH3_ReadData_Data,
MCH3_ReadData_Read => MCH3_ReadData_Read,
MCH3_ReadData_Exists => MCH3_ReadData_Exists,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Mem_DQ_I => Mem_DQ_I,
Mem_DQ_O => Mem_DQ_O,
Mem_DQ_T => Mem_DQ_T,
Mem_A => Mem_A,
Mem_RPN => Mem_RPN,
Mem_CEN => Mem_CEN,
Mem_OEN => Mem_OEN,
Mem_WEN => Mem_WEN,
Mem_QWEN => Mem_QWEN,
Mem_BEN => Mem_BEN,
Mem_CE => Mem_CE,
Mem_ADV_LDN => Mem_ADV_LDN,
Mem_LBON => Mem_LBON,
Mem_CKEN => Mem_CKEN,
Mem_RNW => Mem_RNW
);
end architecture STRUCTURE;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan3/impl/vhdl/nfa_accept_samples_generic_hw_add_32ns_32ns_32_8.vhd | 6 | 15868 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
s: out std_logic_vector(31 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(31 downto 0);
signal b_reg : std_logic_vector(31 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(15 downto 12);
signal b3_cb : std_logic_vector(15 downto 12);
signal a4_cb : std_logic_vector(19 downto 16);
signal b4_cb : std_logic_vector(19 downto 16);
signal a5_cb : std_logic_vector(23 downto 20);
signal b5_cb : std_logic_vector(23 downto 20);
signal a6_cb : std_logic_vector(27 downto 24);
signal b6_cb : std_logic_vector(27 downto 24);
signal a7_cb : std_logic_vector(31 downto 28);
signal b7_cb : std_logic_vector(31 downto 28);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal a4_cb_regi4 : ramtypei3;
signal b4_cb_regi4 : ramtypei3;
type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal a5_cb_regi5 : ramtypei4;
signal b5_cb_regi5 : ramtypei4;
type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal a6_cb_regi6 : ramtypei5;
signal b6_cb_regi6 : ramtypei5;
type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal a7_cb_regi7 : ramtypei6;
signal b7_cb_regi7 : ramtypei6;
-- wires for each full adder sum
signal fas : std_logic_vector(31 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout4_co4 : std_logic_vector (0 downto 0);
signal faccout5_co5 : std_logic_vector (0 downto 0);
signal faccout6_co6 : std_logic_vector (0 downto 0);
signal faccout7_co7 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
signal faccout3_co3_reg : std_logic_vector (0 downto 0);
signal faccout4_co4_reg : std_logic_vector (0 downto 0);
signal faccout5_co5_reg : std_logic_vector (0 downto 0);
signal faccout6_co6_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo6;
type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo5;
type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo4;
type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal s3_ca_rego3 : ramtypeo3;
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s4_ca_rego4 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s5_ca_rego5 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s6_ca_rego6 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(31 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(15 downto 12);
b3_cb <= b_reg(15 downto 12);
a4_cb <= a_reg(19 downto 16);
b4_cb <= b_reg(19 downto 16);
a5_cb <= a_reg(23 downto 20);
b5_cb <= b_reg(23 downto 20);
a6_cb <= a_reg(27 downto 24);
b6_cb <= b_reg(27 downto 24);
a7_cb <= a_reg(31 downto 28);
b7_cb <= b_reg(31 downto 28);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a4_cb_regi4 (0) <= a4_cb;
b4_cb_regi4 (0) <= b4_cb;
a5_cb_regi5 (0) <= a5_cb;
b5_cb_regi5 (0) <= b5_cb;
a6_cb_regi6 (0) <= a6_cb;
b6_cb_regi6 (0) <= b6_cb;
a7_cb_regi7 (0) <= a7_cb;
b7_cb_regi7 (0) <= b7_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a4_cb_regi4 (1) <= a4_cb_regi4 (0);
b4_cb_regi4 (1) <= b4_cb_regi4 (0);
a5_cb_regi5 (1) <= a5_cb_regi5 (0);
b5_cb_regi5 (1) <= b5_cb_regi5 (0);
a6_cb_regi6 (1) <= a6_cb_regi6 (0);
b6_cb_regi6 (1) <= b6_cb_regi6 (0);
a7_cb_regi7 (1) <= a7_cb_regi7 (0);
b7_cb_regi7 (1) <= b7_cb_regi7 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
a4_cb_regi4 (2) <= a4_cb_regi4 (1);
b4_cb_regi4 (2) <= b4_cb_regi4 (1);
a5_cb_regi5 (2) <= a5_cb_regi5 (1);
b5_cb_regi5 (2) <= b5_cb_regi5 (1);
a6_cb_regi6 (2) <= a6_cb_regi6 (1);
b6_cb_regi6 (2) <= b6_cb_regi6 (1);
a7_cb_regi7 (2) <= a7_cb_regi7 (1);
b7_cb_regi7 (2) <= b7_cb_regi7 (1);
a4_cb_regi4 (3) <= a4_cb_regi4 (2);
b4_cb_regi4 (3) <= b4_cb_regi4 (2);
a5_cb_regi5 (3) <= a5_cb_regi5 (2);
b5_cb_regi5 (3) <= b5_cb_regi5 (2);
a6_cb_regi6 (3) <= a6_cb_regi6 (2);
b6_cb_regi6 (3) <= b6_cb_regi6 (2);
a7_cb_regi7 (3) <= a7_cb_regi7 (2);
b7_cb_regi7 (3) <= b7_cb_regi7 (2);
a5_cb_regi5 (4) <= a5_cb_regi5 (3);
b5_cb_regi5 (4) <= b5_cb_regi5 (3);
a6_cb_regi6 (4) <= a6_cb_regi6 (3);
b6_cb_regi6 (4) <= b6_cb_regi6 (3);
a7_cb_regi7 (4) <= a7_cb_regi7 (3);
b7_cb_regi7 (4) <= b7_cb_regi7 (3);
a6_cb_regi6 (5) <= a6_cb_regi6 (4);
b6_cb_regi6 (5) <= b6_cb_regi6 (4);
a7_cb_regi7 (5) <= a7_cb_regi7 (4);
b7_cb_regi7 (5) <= b7_cb_regi7 (4);
a7_cb_regi7 (6) <= a7_cb_regi7 (5);
b7_cb_regi7 (6) <= b7_cb_regi7 (5);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
faccout3_co3_reg <= faccout3_co3;
faccout4_co4_reg <= faccout4_co4;
faccout5_co5_reg <= faccout5_co5;
faccout6_co6_reg <= faccout6_co6;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(15 downto 12),
facout => faccout3_co3);
u4 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a4_cb_regi4(3),
fab => b4_cb_regi4(3),
facin => faccout3_co3_reg,
fas => fas(19 downto 16),
facout => faccout4_co4);
u5 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a5_cb_regi5(4),
fab => b5_cb_regi5(4),
facin => faccout4_co4_reg,
fas => fas(23 downto 20),
facout => faccout5_co5);
u6 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
port map
(faa => a6_cb_regi6(5),
fab => b6_cb_regi6(5),
facin => faccout5_co5_reg,
fas => fas(27 downto 24),
facout => faccout6_co6);
u7 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f
port map
(faa => a7_cb_regi7(6),
fab => b7_cb_regi7(6),
facin => faccout6_co6_reg,
fas => fas(31 downto 28),
facout => faccout7_co7);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s3_ca_rego3 (0) <= fas(15 downto 12);
s4_ca_rego4 (0) <= fas(19 downto 16);
s5_ca_rego5 (0) <= fas(23 downto 20);
s6_ca_rego6 (0) <= fas(27 downto 24);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s0_ca_rego0 (3) <= s0_ca_rego0 (2);
s0_ca_rego0 (4) <= s0_ca_rego0 (3);
s0_ca_rego0 (5) <= s0_ca_rego0 (4);
s0_ca_rego0 (6) <= s0_ca_rego0 (5);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
s1_ca_rego1 (2) <= s1_ca_rego1 (1);
s1_ca_rego1 (3) <= s1_ca_rego1 (2);
s1_ca_rego1 (4) <= s1_ca_rego1 (3);
s1_ca_rego1 (5) <= s1_ca_rego1 (4);
s2_ca_rego2 (1) <= s2_ca_rego2 (0);
s2_ca_rego2 (2) <= s2_ca_rego2 (1);
s2_ca_rego2 (3) <= s2_ca_rego2 (2);
s2_ca_rego2 (4) <= s2_ca_rego2 (3);
s3_ca_rego3 (1) <= s3_ca_rego3 (0);
s3_ca_rego3 (2) <= s3_ca_rego3 (1);
s3_ca_rego3 (3) <= s3_ca_rego3 (2);
s4_ca_rego4 (1) <= s4_ca_rego4 (0);
s4_ca_rego4 (2) <= s4_ca_rego4 (1);
s5_ca_rego5 (1) <= s5_ca_rego5 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(6);
s_tmp(7 downto 4) <= s1_ca_rego1(5);
s_tmp(11 downto 8) <= s2_ca_rego2(4);
s_tmp(15 downto 12) <= s3_ca_rego3(3);
s_tmp(19 downto 16) <= s4_ca_rego4(2);
s_tmp(23 downto 20) <= s5_ca_rego5(1);
s_tmp(27 downto 24) <= s6_ca_rego6(0);
s_tmp(31 downto 28) <= fas(31 downto 28);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 is
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_U : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/bitset_next.vhd | 1 | 25480 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_true : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal reg_123 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_fu_143_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_1_fu_148_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_fu_153_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_bit_read_reg_196 : STD_LOGIC_VECTOR (7 downto 0);
signal p_read_1_reg_202 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_202_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_210 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_210_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_216 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_bus_assign_reg_216_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_1_reg_227 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_reg_231 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_163_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_158_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_168_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_113 : BOOLEAN;
signal ap_sig_bdd_104 : BOOLEAN;
signal ap_sig_bdd_121 : BOOLEAN;
signal ap_sig_bdd_125 : BOOLEAN;
signal ap_sig_bdd_61 : BOOLEAN;
signal ap_sig_bdd_73 : BOOLEAN;
signal ap_sig_bdd_59 : BOOLEAN;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
begin
grp_p_bsf32_hw_fu_118 : component p_bsf32_hw
port map (
bus_r => grp_p_bsf32_hw_fu_118_bus_r,
ap_return => grp_p_bsf32_hw_fu_118_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= r_bit_read_reg_196;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_const_lv2_2;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_61) then
if (ap_sig_bdd_125) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= p_read_1_reg_202;
elsif (ap_sig_bdd_121) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_const_lv32_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_bus_assign_reg_216_pp0_it1 <= bus_assign_reg_216;
ap_reg_ppstg_p_read_1_reg_202_pp0_it1 <= p_read_1_reg_202;
ap_reg_ppstg_tmp_reg_210_pp0_it1 <= tmp_reg_210;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
bus_assign_reg_216 <= bus_assign_fu_137_p2;
p_read_1_reg_202 <= p_read;
r_bit_read_reg_196 <= r_bit;
tmp_reg_210 <= tmp_fu_127_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and (tmp_5_fu_143_p2 = ap_const_lv1_0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2)))) then
reg_123 <= grp_p_bsf32_hw_fu_118_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)))) then
tmp_11_1_reg_231 <= tmp_11_1_fu_153_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
tmp_5_reg_223 <= tmp_5_fu_143_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)))) then
tmp_9_1_reg_227 <= tmp_9_1_fu_148_p2;
end if;
end if;
end process;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2(0) <= '1';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- agg_result_bit_write_assign_phi_fu_107_p8 assign process. --
agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(tmp_5_reg_223, agg_result_bit_write_assign_trunc3_ext_fu_163_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2, agg_result_bit_write_assign_trunc_ext_fu_158_p1, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_158_p1;
elsif (ap_sig_bdd_113) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_163_p1;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2;
end if;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_163_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bit_write_assign_trunc_ext_fu_158_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bucket_index_write_assign_cast_fu_168_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_210_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_210_pp0_it1;
elsif (ap_sig_bdd_113) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2;
end if;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_202_pp0_it1, ap_reg_ppstg_bus_assign_reg_216_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_216_pp0_it1;
elsif (ap_sig_bdd_113) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_202_pp0_it1;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2;
end if;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_73_p8 assign process. --
agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = tmp_5_reg_223)))) then
agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_1;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_168_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8;
-- ap_sig_bdd_104 assign process. --
ap_sig_bdd_104_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2)
begin
ap_sig_bdd_104 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2));
end process;
-- ap_sig_bdd_113 assign process. --
ap_sig_bdd_113_assign_proc : process(tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231)
begin
ap_sig_bdd_113 <= (not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231));
end process;
-- ap_sig_bdd_121 assign process. --
ap_sig_bdd_121_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2)
begin
ap_sig_bdd_121 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2));
end process;
-- ap_sig_bdd_125 assign process. --
ap_sig_bdd_125_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2)
begin
ap_sig_bdd_125 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2)));
end process;
-- ap_sig_bdd_59 assign process. --
ap_sig_bdd_59_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1)
begin
ap_sig_bdd_59 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1));
end process;
-- ap_sig_bdd_61 assign process. --
ap_sig_bdd_61_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce)
begin
ap_sig_bdd_61 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_73 assign process. --
ap_sig_bdd_73_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2)
begin
ap_sig_bdd_73 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
bus_assign_fu_137_p2 <= (tmp_3_fu_131_p2 and r_bucket);
-- grp_p_bsf32_hw_fu_118_bus_r assign process. --
grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(tmp_5_fu_143_p2, p_read_1_reg_202, bus_assign_reg_216, ap_sig_bdd_73, ap_sig_bdd_59)
begin
if (ap_sig_bdd_59) then
if (ap_sig_bdd_73) then
grp_p_bsf32_hw_fu_118_bus_r <= p_read_1_reg_202;
elsif ((tmp_5_fu_143_p2 = ap_const_lv1_0)) then
grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_216;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
tmp_11_1_fu_153_p2 <= "1" when (p_read_1_reg_202 = ap_const_lv32_0) else "0";
tmp_3_fu_131_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF));
tmp_5_fu_143_p2 <= "1" when (bus_assign_reg_216 = ap_const_lv32_0) else "0";
tmp_9_1_fu_148_p2 <= "1" when (tmp_reg_210 = ap_const_lv2_0) else "0";
tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0);
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/sim/vhdl/sample_iterator_get_offset.vhd | 1 | 30918 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal i_sample_read_reg_131 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_begin_addr_reg_136 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_148 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_163 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_8_cast_fu_122_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4
generic map (
ID => 0,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_116_p0,
din1 => grp_fu_116_p1,
ce => grp_fu_116_ce,
dout => grp_fu_116_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_131_pp0_it1 <= i_sample_read_reg_131;
ap_reg_ppstg_i_sample_read_reg_131_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_131_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_131_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_131_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it4;
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(0) <= indices_begin_addr_reg_136(0);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(1) <= indices_begin_addr_reg_136(1);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(2) <= indices_begin_addr_reg_136(2);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(3) <= indices_begin_addr_reg_136(3);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(4) <= indices_begin_addr_reg_136(4);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(5) <= indices_begin_addr_reg_136(5);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(6) <= indices_begin_addr_reg_136(6);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(7) <= indices_begin_addr_reg_136(7);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(8) <= indices_begin_addr_reg_136(8);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(9) <= indices_begin_addr_reg_136(9);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(10) <= indices_begin_addr_reg_136(10);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(11) <= indices_begin_addr_reg_136(11);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(12) <= indices_begin_addr_reg_136(12);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(13) <= indices_begin_addr_reg_136(13);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(14) <= indices_begin_addr_reg_136(14);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(15) <= indices_begin_addr_reg_136(15);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(0);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(1);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(2);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(3);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(4);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(5);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(6);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(7);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(8);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(9);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(10);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(11);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(12);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(13);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(14);
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_131 <= i_sample;
indices_begin_addr_reg_136(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0);
indices_begin_addr_reg_136(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1);
indices_begin_addr_reg_136(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2);
indices_begin_addr_reg_136(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3);
indices_begin_addr_reg_136(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4);
indices_begin_addr_reg_136(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5);
indices_begin_addr_reg_136(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6);
indices_begin_addr_reg_136(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7);
indices_begin_addr_reg_136(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8);
indices_begin_addr_reg_136(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9);
indices_begin_addr_reg_136(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10);
indices_begin_addr_reg_136(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11);
indices_begin_addr_reg_136(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12);
indices_begin_addr_reg_136(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13);
indices_begin_addr_reg_136(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14);
indices_begin_addr_reg_136(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_163 <= indices_begin_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_148 <= indices_stride_datain;
end if;
end if;
end process;
indices_begin_addr_reg_136(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it8 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= std_logic_vector(unsigned(tmp_8_cast_fu_122_p1) + unsigned(indices_begin_addr_read_reg_163));
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_116_ce assign process. --
grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_116_ce <= ap_const_logic_1;
else
grp_fu_116_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0);
grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_131_pp0_it5),24));
grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0);
grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_148),24));
indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0);
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_8_cast_fu_122_p1 <= std_logic_vector(resize(unsigned(grp_fu_116_p2),32));
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan3/syn/vhdl/bitset_next.vhd | 2 | 25988 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_true : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal reg_123 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_3_reg_232 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_1_reg_236 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_1_reg_240 : STD_LOGIC_VECTOR (0 downto 0);
signal r_bucket_read_reg_194 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal r_bit_read_reg_200 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 : STD_LOGIC_VECTOR (7 downto 0);
signal p_read_1_reg_206 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_206_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it3 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it6 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it7 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it9 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_214_pp0_it10 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_220 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_bus_assign_reg_225_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_bus_assign_reg_225_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_141_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_3_reg_232_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_1_fu_146_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_1_fu_151_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_118_ap_ce : STD_LOGIC;
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_161_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_156_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_131_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_166_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_131_ce : STD_LOGIC;
signal ap_sig_bdd_139 : BOOLEAN;
signal ap_sig_bdd_143 : BOOLEAN;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_p_bsf32_hw_fu_118 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_118_bus_r,
ap_return => grp_p_bsf32_hw_fu_118_ap_return,
ap_ce => grp_p_bsf32_hw_fu_118_ap_ce);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_U11 : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8
generic map (
ID => 11,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_131_p0,
din1 => grp_fu_131_p1,
ce => grp_fu_131_ce,
dout => grp_fu_131_p2);
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240))))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it9;
elsif ((ap_const_logic_1 = ap_ce)) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240))))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_const_lv2_2;
elsif ((ap_const_logic_1 = ap_ce)) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_143) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9;
elsif (ap_sig_bdd_139) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_const_lv32_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
ap_reg_ppstg_bus_assign_reg_225_pp0_it10 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it9;
ap_reg_ppstg_bus_assign_reg_225_pp0_it9 <= bus_assign_reg_225;
ap_reg_ppstg_p_read_1_reg_206_pp0_it1 <= p_read_1_reg_206;
ap_reg_ppstg_p_read_1_reg_206_pp0_it10 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9;
ap_reg_ppstg_p_read_1_reg_206_pp0_it2 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it1;
ap_reg_ppstg_p_read_1_reg_206_pp0_it3 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it2;
ap_reg_ppstg_p_read_1_reg_206_pp0_it4 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it3;
ap_reg_ppstg_p_read_1_reg_206_pp0_it5 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it4;
ap_reg_ppstg_p_read_1_reg_206_pp0_it6 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it5;
ap_reg_ppstg_p_read_1_reg_206_pp0_it7 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it6;
ap_reg_ppstg_p_read_1_reg_206_pp0_it8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it7;
ap_reg_ppstg_p_read_1_reg_206_pp0_it9 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 <= r_bit_read_reg_200;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it1;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it2;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it3;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it4;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it5;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it6;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it7;
ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it8;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 <= r_bucket_read_reg_194;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5;
ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6;
ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10 <= tmp_24_1_reg_236;
ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10 <= tmp_26_1_reg_240;
ap_reg_ppstg_tmp_3_reg_232_pp0_it10 <= tmp_3_reg_232;
ap_reg_ppstg_tmp_reg_214_pp0_it1 <= tmp_reg_214;
ap_reg_ppstg_tmp_reg_214_pp0_it10 <= ap_reg_ppstg_tmp_reg_214_pp0_it9;
ap_reg_ppstg_tmp_reg_214_pp0_it2 <= ap_reg_ppstg_tmp_reg_214_pp0_it1;
ap_reg_ppstg_tmp_reg_214_pp0_it3 <= ap_reg_ppstg_tmp_reg_214_pp0_it2;
ap_reg_ppstg_tmp_reg_214_pp0_it4 <= ap_reg_ppstg_tmp_reg_214_pp0_it3;
ap_reg_ppstg_tmp_reg_214_pp0_it5 <= ap_reg_ppstg_tmp_reg_214_pp0_it4;
ap_reg_ppstg_tmp_reg_214_pp0_it6 <= ap_reg_ppstg_tmp_reg_214_pp0_it5;
ap_reg_ppstg_tmp_reg_214_pp0_it7 <= ap_reg_ppstg_tmp_reg_214_pp0_it6;
ap_reg_ppstg_tmp_reg_214_pp0_it8 <= ap_reg_ppstg_tmp_reg_214_pp0_it7;
ap_reg_ppstg_tmp_reg_214_pp0_it9 <= ap_reg_ppstg_tmp_reg_214_pp0_it8;
bus_assign_reg_225 <= bus_assign_fu_137_p2;
p_read_1_reg_206 <= p_read;
r_bit_read_reg_200 <= r_bit;
r_bucket_read_reg_194 <= r_bucket;
tmp_1_reg_220 <= grp_fu_131_p2;
tmp_3_reg_232 <= tmp_3_fu_141_p2;
tmp_reg_214 <= tmp_fu_127_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_ce) and (tmp_3_reg_232 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and (ap_const_lv1_0 = tmp_26_1_reg_240)))) then
reg_123 <= grp_p_bsf32_hw_fu_118_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)))) then
tmp_24_1_reg_236 <= tmp_24_1_fu_146_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)))) then
tmp_26_1_reg_240 <= tmp_26_1_fu_151_p2;
end if;
end if;
end process;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11(0) <= '1';
-- agg_result_bit_write_assign_phi_fu_107_p8 assign process. --
agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, agg_result_bit_write_assign_trunc3_ext_fu_161_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11, agg_result_bit_write_assign_trunc_ext_fu_156_p1)
begin
if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_156_p1;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_161_p1;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_161_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bit_write_assign_trunc_ext_fu_156_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bucket_index_write_assign_cast_fu_166_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_214_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11)
begin
if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_214_pp0_it10;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it10, ap_reg_ppstg_bus_assign_reg_225_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11)
begin
if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it10;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it10;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_73_p8 assign process. --
agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10)))) then
agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 <= ap_const_lv1_1;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_166_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8;
-- ap_sig_bdd_139 assign process. --
ap_sig_bdd_139_assign_proc : process(tmp_3_reg_232, tmp_24_1_reg_236)
begin
ap_sig_bdd_139 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236));
end process;
-- ap_sig_bdd_143 assign process. --
ap_sig_bdd_143_assign_proc : process(tmp_3_reg_232, tmp_24_1_reg_236, tmp_26_1_reg_240)
begin
ap_sig_bdd_143 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240)));
end process;
bus_assign_fu_137_p2 <= (tmp_1_reg_220 and ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7);
-- grp_fu_131_ce assign process. --
grp_fu_131_ce_assign_proc : process(ap_ce)
begin
if (not((ap_const_logic_1 = ap_ce))) then
grp_fu_131_ce <= ap_const_logic_0;
else
grp_fu_131_ce <= ap_const_logic_1;
end if;
end process;
grp_fu_131_p0 <= r_bucket;
grp_fu_131_p1 <= ap_const_lv32_FFFFFFFF;
-- grp_p_bsf32_hw_fu_118_ap_ce assign process. --
grp_p_bsf32_hw_fu_118_ap_ce_assign_proc : process(ap_ce, tmp_3_reg_232, tmp_24_1_reg_236, tmp_26_1_reg_240, tmp_3_fu_141_p2, tmp_24_1_fu_146_p2, tmp_26_1_fu_151_p2)
begin
if (((ap_const_logic_1 = ap_ce) and ((tmp_3_reg_232 = ap_const_lv1_0) or (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and (ap_const_lv1_0 = tmp_26_1_reg_240)) or (ap_const_lv1_0 = tmp_3_fu_141_p2) or (not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_26_1_fu_151_p2))))) then
grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_0;
end if;
end process;
-- grp_p_bsf32_hw_fu_118_bus_r assign process. --
grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it8, bus_assign_reg_225, tmp_3_fu_141_p2, tmp_24_1_fu_146_p2, tmp_26_1_fu_151_p2)
begin
if ((not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_26_1_fu_151_p2))) then
grp_p_bsf32_hw_fu_118_bus_r <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8;
elsif ((ap_const_lv1_0 = tmp_3_fu_141_p2)) then
grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_225;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
tmp_24_1_fu_146_p2 <= "1" when (ap_reg_ppstg_tmp_reg_214_pp0_it8 = ap_const_lv2_0) else "0";
tmp_26_1_fu_151_p2 <= "1" when (ap_reg_ppstg_p_read_1_reg_206_pp0_it8 = ap_const_lv32_0) else "0";
tmp_3_fu_141_p2 <= "1" when (bus_assign_reg_225 = ap_const_lv32_0) else "0";
tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0);
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/syn/vhdl/nfa_accept_samples_generic_hw_add_64ns_64ns_64_16.vhd | 6 | 35870 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(15 downto 12);
signal b3_cb : std_logic_vector(15 downto 12);
signal a4_cb : std_logic_vector(19 downto 16);
signal b4_cb : std_logic_vector(19 downto 16);
signal a5_cb : std_logic_vector(23 downto 20);
signal b5_cb : std_logic_vector(23 downto 20);
signal a6_cb : std_logic_vector(27 downto 24);
signal b6_cb : std_logic_vector(27 downto 24);
signal a7_cb : std_logic_vector(31 downto 28);
signal b7_cb : std_logic_vector(31 downto 28);
signal a8_cb : std_logic_vector(35 downto 32);
signal b8_cb : std_logic_vector(35 downto 32);
signal a9_cb : std_logic_vector(39 downto 36);
signal b9_cb : std_logic_vector(39 downto 36);
signal a10_cb : std_logic_vector(43 downto 40);
signal b10_cb : std_logic_vector(43 downto 40);
signal a11_cb : std_logic_vector(47 downto 44);
signal b11_cb : std_logic_vector(47 downto 44);
signal a12_cb : std_logic_vector(51 downto 48);
signal b12_cb : std_logic_vector(51 downto 48);
signal a13_cb : std_logic_vector(55 downto 52);
signal b13_cb : std_logic_vector(55 downto 52);
signal a14_cb : std_logic_vector(59 downto 56);
signal b14_cb : std_logic_vector(59 downto 56);
signal a15_cb : std_logic_vector(63 downto 60);
signal b15_cb : std_logic_vector(63 downto 60);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal a4_cb_regi4 : ramtypei3;
signal b4_cb_regi4 : ramtypei3;
type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal a5_cb_regi5 : ramtypei4;
signal b5_cb_regi5 : ramtypei4;
type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal a6_cb_regi6 : ramtypei5;
signal b6_cb_regi6 : ramtypei5;
type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal a7_cb_regi7 : ramtypei6;
signal b7_cb_regi7 : ramtypei6;
type ramtypei7 is array (7 downto 0) of std_logic_vector(3 downto 0);
signal a8_cb_regi8 : ramtypei7;
signal b8_cb_regi8 : ramtypei7;
type ramtypei8 is array (8 downto 0) of std_logic_vector(3 downto 0);
signal a9_cb_regi9 : ramtypei8;
signal b9_cb_regi9 : ramtypei8;
type ramtypei9 is array (9 downto 0) of std_logic_vector(3 downto 0);
signal a10_cb_regi10 : ramtypei9;
signal b10_cb_regi10 : ramtypei9;
type ramtypei10 is array (10 downto 0) of std_logic_vector(3 downto 0);
signal a11_cb_regi11 : ramtypei10;
signal b11_cb_regi11 : ramtypei10;
type ramtypei11 is array (11 downto 0) of std_logic_vector(3 downto 0);
signal a12_cb_regi12 : ramtypei11;
signal b12_cb_regi12 : ramtypei11;
type ramtypei12 is array (12 downto 0) of std_logic_vector(3 downto 0);
signal a13_cb_regi13 : ramtypei12;
signal b13_cb_regi13 : ramtypei12;
type ramtypei13 is array (13 downto 0) of std_logic_vector(3 downto 0);
signal a14_cb_regi14 : ramtypei13;
signal b14_cb_regi14 : ramtypei13;
type ramtypei14 is array (14 downto 0) of std_logic_vector(3 downto 0);
signal a15_cb_regi15 : ramtypei14;
signal b15_cb_regi15 : ramtypei14;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout4_co4 : std_logic_vector (0 downto 0);
signal faccout5_co5 : std_logic_vector (0 downto 0);
signal faccout6_co6 : std_logic_vector (0 downto 0);
signal faccout7_co7 : std_logic_vector (0 downto 0);
signal faccout8_co8 : std_logic_vector (0 downto 0);
signal faccout9_co9 : std_logic_vector (0 downto 0);
signal faccout10_co10 : std_logic_vector (0 downto 0);
signal faccout11_co11 : std_logic_vector (0 downto 0);
signal faccout12_co12 : std_logic_vector (0 downto 0);
signal faccout13_co13 : std_logic_vector (0 downto 0);
signal faccout14_co14 : std_logic_vector (0 downto 0);
signal faccout15_co15 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
signal faccout3_co3_reg : std_logic_vector (0 downto 0);
signal faccout4_co4_reg : std_logic_vector (0 downto 0);
signal faccout5_co5_reg : std_logic_vector (0 downto 0);
signal faccout6_co6_reg : std_logic_vector (0 downto 0);
signal faccout7_co7_reg : std_logic_vector (0 downto 0);
signal faccout8_co8_reg : std_logic_vector (0 downto 0);
signal faccout9_co9_reg : std_logic_vector (0 downto 0);
signal faccout10_co10_reg : std_logic_vector (0 downto 0);
signal faccout11_co11_reg : std_logic_vector (0 downto 0);
signal faccout12_co12_reg : std_logic_vector (0 downto 0);
signal faccout13_co13_reg : std_logic_vector (0 downto 0);
signal faccout14_co14_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo14 is array (14 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo14;
type ramtypeo13 is array (13 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo13;
type ramtypeo12 is array (12 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo12;
type ramtypeo11 is array (11 downto 0) of std_logic_vector(3 downto 0);
signal s3_ca_rego3 : ramtypeo11;
type ramtypeo10 is array (10 downto 0) of std_logic_vector(3 downto 0);
signal s4_ca_rego4 : ramtypeo10;
type ramtypeo9 is array (9 downto 0) of std_logic_vector(3 downto 0);
signal s5_ca_rego5 : ramtypeo9;
type ramtypeo8 is array (8 downto 0) of std_logic_vector(3 downto 0);
signal s6_ca_rego6 : ramtypeo8;
type ramtypeo7 is array (7 downto 0) of std_logic_vector(3 downto 0);
signal s7_ca_rego7 : ramtypeo7;
type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal s8_ca_rego8 : ramtypeo6;
type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal s9_ca_rego9 : ramtypeo5;
type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal s10_ca_rego10 : ramtypeo4;
type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal s11_ca_rego11 : ramtypeo3;
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s12_ca_rego12 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s13_ca_rego13 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s14_ca_rego14 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(15 downto 12);
b3_cb <= b_reg(15 downto 12);
a4_cb <= a_reg(19 downto 16);
b4_cb <= b_reg(19 downto 16);
a5_cb <= a_reg(23 downto 20);
b5_cb <= b_reg(23 downto 20);
a6_cb <= a_reg(27 downto 24);
b6_cb <= b_reg(27 downto 24);
a7_cb <= a_reg(31 downto 28);
b7_cb <= b_reg(31 downto 28);
a8_cb <= a_reg(35 downto 32);
b8_cb <= b_reg(35 downto 32);
a9_cb <= a_reg(39 downto 36);
b9_cb <= b_reg(39 downto 36);
a10_cb <= a_reg(43 downto 40);
b10_cb <= b_reg(43 downto 40);
a11_cb <= a_reg(47 downto 44);
b11_cb <= b_reg(47 downto 44);
a12_cb <= a_reg(51 downto 48);
b12_cb <= b_reg(51 downto 48);
a13_cb <= a_reg(55 downto 52);
b13_cb <= b_reg(55 downto 52);
a14_cb <= a_reg(59 downto 56);
b14_cb <= b_reg(59 downto 56);
a15_cb <= a_reg(63 downto 60);
b15_cb <= b_reg(63 downto 60);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a4_cb_regi4 (0) <= a4_cb;
b4_cb_regi4 (0) <= b4_cb;
a5_cb_regi5 (0) <= a5_cb;
b5_cb_regi5 (0) <= b5_cb;
a6_cb_regi6 (0) <= a6_cb;
b6_cb_regi6 (0) <= b6_cb;
a7_cb_regi7 (0) <= a7_cb;
b7_cb_regi7 (0) <= b7_cb;
a8_cb_regi8 (0) <= a8_cb;
b8_cb_regi8 (0) <= b8_cb;
a9_cb_regi9 (0) <= a9_cb;
b9_cb_regi9 (0) <= b9_cb;
a10_cb_regi10 (0) <= a10_cb;
b10_cb_regi10 (0) <= b10_cb;
a11_cb_regi11 (0) <= a11_cb;
b11_cb_regi11 (0) <= b11_cb;
a12_cb_regi12 (0) <= a12_cb;
b12_cb_regi12 (0) <= b12_cb;
a13_cb_regi13 (0) <= a13_cb;
b13_cb_regi13 (0) <= b13_cb;
a14_cb_regi14 (0) <= a14_cb;
b14_cb_regi14 (0) <= b14_cb;
a15_cb_regi15 (0) <= a15_cb;
b15_cb_regi15 (0) <= b15_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a4_cb_regi4 (1) <= a4_cb_regi4 (0);
b4_cb_regi4 (1) <= b4_cb_regi4 (0);
a5_cb_regi5 (1) <= a5_cb_regi5 (0);
b5_cb_regi5 (1) <= b5_cb_regi5 (0);
a6_cb_regi6 (1) <= a6_cb_regi6 (0);
b6_cb_regi6 (1) <= b6_cb_regi6 (0);
a7_cb_regi7 (1) <= a7_cb_regi7 (0);
b7_cb_regi7 (1) <= b7_cb_regi7 (0);
a8_cb_regi8 (1) <= a8_cb_regi8 (0);
b8_cb_regi8 (1) <= b8_cb_regi8 (0);
a9_cb_regi9 (1) <= a9_cb_regi9 (0);
b9_cb_regi9 (1) <= b9_cb_regi9 (0);
a10_cb_regi10 (1) <= a10_cb_regi10 (0);
b10_cb_regi10 (1) <= b10_cb_regi10 (0);
a11_cb_regi11 (1) <= a11_cb_regi11 (0);
b11_cb_regi11 (1) <= b11_cb_regi11 (0);
a12_cb_regi12 (1) <= a12_cb_regi12 (0);
b12_cb_regi12 (1) <= b12_cb_regi12 (0);
a13_cb_regi13 (1) <= a13_cb_regi13 (0);
b13_cb_regi13 (1) <= b13_cb_regi13 (0);
a14_cb_regi14 (1) <= a14_cb_regi14 (0);
b14_cb_regi14 (1) <= b14_cb_regi14 (0);
a15_cb_regi15 (1) <= a15_cb_regi15 (0);
b15_cb_regi15 (1) <= b15_cb_regi15 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
a4_cb_regi4 (2) <= a4_cb_regi4 (1);
b4_cb_regi4 (2) <= b4_cb_regi4 (1);
a5_cb_regi5 (2) <= a5_cb_regi5 (1);
b5_cb_regi5 (2) <= b5_cb_regi5 (1);
a6_cb_regi6 (2) <= a6_cb_regi6 (1);
b6_cb_regi6 (2) <= b6_cb_regi6 (1);
a7_cb_regi7 (2) <= a7_cb_regi7 (1);
b7_cb_regi7 (2) <= b7_cb_regi7 (1);
a8_cb_regi8 (2) <= a8_cb_regi8 (1);
b8_cb_regi8 (2) <= b8_cb_regi8 (1);
a9_cb_regi9 (2) <= a9_cb_regi9 (1);
b9_cb_regi9 (2) <= b9_cb_regi9 (1);
a10_cb_regi10 (2) <= a10_cb_regi10 (1);
b10_cb_regi10 (2) <= b10_cb_regi10 (1);
a11_cb_regi11 (2) <= a11_cb_regi11 (1);
b11_cb_regi11 (2) <= b11_cb_regi11 (1);
a12_cb_regi12 (2) <= a12_cb_regi12 (1);
b12_cb_regi12 (2) <= b12_cb_regi12 (1);
a13_cb_regi13 (2) <= a13_cb_regi13 (1);
b13_cb_regi13 (2) <= b13_cb_regi13 (1);
a14_cb_regi14 (2) <= a14_cb_regi14 (1);
b14_cb_regi14 (2) <= b14_cb_regi14 (1);
a15_cb_regi15 (2) <= a15_cb_regi15 (1);
b15_cb_regi15 (2) <= b15_cb_regi15 (1);
a4_cb_regi4 (3) <= a4_cb_regi4 (2);
b4_cb_regi4 (3) <= b4_cb_regi4 (2);
a5_cb_regi5 (3) <= a5_cb_regi5 (2);
b5_cb_regi5 (3) <= b5_cb_regi5 (2);
a6_cb_regi6 (3) <= a6_cb_regi6 (2);
b6_cb_regi6 (3) <= b6_cb_regi6 (2);
a7_cb_regi7 (3) <= a7_cb_regi7 (2);
b7_cb_regi7 (3) <= b7_cb_regi7 (2);
a8_cb_regi8 (3) <= a8_cb_regi8 (2);
b8_cb_regi8 (3) <= b8_cb_regi8 (2);
a9_cb_regi9 (3) <= a9_cb_regi9 (2);
b9_cb_regi9 (3) <= b9_cb_regi9 (2);
a10_cb_regi10 (3) <= a10_cb_regi10 (2);
b10_cb_regi10 (3) <= b10_cb_regi10 (2);
a11_cb_regi11 (3) <= a11_cb_regi11 (2);
b11_cb_regi11 (3) <= b11_cb_regi11 (2);
a12_cb_regi12 (3) <= a12_cb_regi12 (2);
b12_cb_regi12 (3) <= b12_cb_regi12 (2);
a13_cb_regi13 (3) <= a13_cb_regi13 (2);
b13_cb_regi13 (3) <= b13_cb_regi13 (2);
a14_cb_regi14 (3) <= a14_cb_regi14 (2);
b14_cb_regi14 (3) <= b14_cb_regi14 (2);
a15_cb_regi15 (3) <= a15_cb_regi15 (2);
b15_cb_regi15 (3) <= b15_cb_regi15 (2);
a5_cb_regi5 (4) <= a5_cb_regi5 (3);
b5_cb_regi5 (4) <= b5_cb_regi5 (3);
a6_cb_regi6 (4) <= a6_cb_regi6 (3);
b6_cb_regi6 (4) <= b6_cb_regi6 (3);
a7_cb_regi7 (4) <= a7_cb_regi7 (3);
b7_cb_regi7 (4) <= b7_cb_regi7 (3);
a8_cb_regi8 (4) <= a8_cb_regi8 (3);
b8_cb_regi8 (4) <= b8_cb_regi8 (3);
a9_cb_regi9 (4) <= a9_cb_regi9 (3);
b9_cb_regi9 (4) <= b9_cb_regi9 (3);
a10_cb_regi10 (4) <= a10_cb_regi10 (3);
b10_cb_regi10 (4) <= b10_cb_regi10 (3);
a11_cb_regi11 (4) <= a11_cb_regi11 (3);
b11_cb_regi11 (4) <= b11_cb_regi11 (3);
a12_cb_regi12 (4) <= a12_cb_regi12 (3);
b12_cb_regi12 (4) <= b12_cb_regi12 (3);
a13_cb_regi13 (4) <= a13_cb_regi13 (3);
b13_cb_regi13 (4) <= b13_cb_regi13 (3);
a14_cb_regi14 (4) <= a14_cb_regi14 (3);
b14_cb_regi14 (4) <= b14_cb_regi14 (3);
a15_cb_regi15 (4) <= a15_cb_regi15 (3);
b15_cb_regi15 (4) <= b15_cb_regi15 (3);
a6_cb_regi6 (5) <= a6_cb_regi6 (4);
b6_cb_regi6 (5) <= b6_cb_regi6 (4);
a7_cb_regi7 (5) <= a7_cb_regi7 (4);
b7_cb_regi7 (5) <= b7_cb_regi7 (4);
a8_cb_regi8 (5) <= a8_cb_regi8 (4);
b8_cb_regi8 (5) <= b8_cb_regi8 (4);
a9_cb_regi9 (5) <= a9_cb_regi9 (4);
b9_cb_regi9 (5) <= b9_cb_regi9 (4);
a10_cb_regi10 (5) <= a10_cb_regi10 (4);
b10_cb_regi10 (5) <= b10_cb_regi10 (4);
a11_cb_regi11 (5) <= a11_cb_regi11 (4);
b11_cb_regi11 (5) <= b11_cb_regi11 (4);
a12_cb_regi12 (5) <= a12_cb_regi12 (4);
b12_cb_regi12 (5) <= b12_cb_regi12 (4);
a13_cb_regi13 (5) <= a13_cb_regi13 (4);
b13_cb_regi13 (5) <= b13_cb_regi13 (4);
a14_cb_regi14 (5) <= a14_cb_regi14 (4);
b14_cb_regi14 (5) <= b14_cb_regi14 (4);
a15_cb_regi15 (5) <= a15_cb_regi15 (4);
b15_cb_regi15 (5) <= b15_cb_regi15 (4);
a7_cb_regi7 (6) <= a7_cb_regi7 (5);
b7_cb_regi7 (6) <= b7_cb_regi7 (5);
a8_cb_regi8 (6) <= a8_cb_regi8 (5);
b8_cb_regi8 (6) <= b8_cb_regi8 (5);
a9_cb_regi9 (6) <= a9_cb_regi9 (5);
b9_cb_regi9 (6) <= b9_cb_regi9 (5);
a10_cb_regi10 (6) <= a10_cb_regi10 (5);
b10_cb_regi10 (6) <= b10_cb_regi10 (5);
a11_cb_regi11 (6) <= a11_cb_regi11 (5);
b11_cb_regi11 (6) <= b11_cb_regi11 (5);
a12_cb_regi12 (6) <= a12_cb_regi12 (5);
b12_cb_regi12 (6) <= b12_cb_regi12 (5);
a13_cb_regi13 (6) <= a13_cb_regi13 (5);
b13_cb_regi13 (6) <= b13_cb_regi13 (5);
a14_cb_regi14 (6) <= a14_cb_regi14 (5);
b14_cb_regi14 (6) <= b14_cb_regi14 (5);
a15_cb_regi15 (6) <= a15_cb_regi15 (5);
b15_cb_regi15 (6) <= b15_cb_regi15 (5);
a8_cb_regi8 (7) <= a8_cb_regi8 (6);
b8_cb_regi8 (7) <= b8_cb_regi8 (6);
a9_cb_regi9 (7) <= a9_cb_regi9 (6);
b9_cb_regi9 (7) <= b9_cb_regi9 (6);
a10_cb_regi10 (7) <= a10_cb_regi10 (6);
b10_cb_regi10 (7) <= b10_cb_regi10 (6);
a11_cb_regi11 (7) <= a11_cb_regi11 (6);
b11_cb_regi11 (7) <= b11_cb_regi11 (6);
a12_cb_regi12 (7) <= a12_cb_regi12 (6);
b12_cb_regi12 (7) <= b12_cb_regi12 (6);
a13_cb_regi13 (7) <= a13_cb_regi13 (6);
b13_cb_regi13 (7) <= b13_cb_regi13 (6);
a14_cb_regi14 (7) <= a14_cb_regi14 (6);
b14_cb_regi14 (7) <= b14_cb_regi14 (6);
a15_cb_regi15 (7) <= a15_cb_regi15 (6);
b15_cb_regi15 (7) <= b15_cb_regi15 (6);
a9_cb_regi9 (8) <= a9_cb_regi9 (7);
b9_cb_regi9 (8) <= b9_cb_regi9 (7);
a10_cb_regi10 (8) <= a10_cb_regi10 (7);
b10_cb_regi10 (8) <= b10_cb_regi10 (7);
a11_cb_regi11 (8) <= a11_cb_regi11 (7);
b11_cb_regi11 (8) <= b11_cb_regi11 (7);
a12_cb_regi12 (8) <= a12_cb_regi12 (7);
b12_cb_regi12 (8) <= b12_cb_regi12 (7);
a13_cb_regi13 (8) <= a13_cb_regi13 (7);
b13_cb_regi13 (8) <= b13_cb_regi13 (7);
a14_cb_regi14 (8) <= a14_cb_regi14 (7);
b14_cb_regi14 (8) <= b14_cb_regi14 (7);
a15_cb_regi15 (8) <= a15_cb_regi15 (7);
b15_cb_regi15 (8) <= b15_cb_regi15 (7);
a10_cb_regi10 (9) <= a10_cb_regi10 (8);
b10_cb_regi10 (9) <= b10_cb_regi10 (8);
a11_cb_regi11 (9) <= a11_cb_regi11 (8);
b11_cb_regi11 (9) <= b11_cb_regi11 (8);
a12_cb_regi12 (9) <= a12_cb_regi12 (8);
b12_cb_regi12 (9) <= b12_cb_regi12 (8);
a13_cb_regi13 (9) <= a13_cb_regi13 (8);
b13_cb_regi13 (9) <= b13_cb_regi13 (8);
a14_cb_regi14 (9) <= a14_cb_regi14 (8);
b14_cb_regi14 (9) <= b14_cb_regi14 (8);
a15_cb_regi15 (9) <= a15_cb_regi15 (8);
b15_cb_regi15 (9) <= b15_cb_regi15 (8);
a11_cb_regi11 (10) <= a11_cb_regi11 (9);
b11_cb_regi11 (10) <= b11_cb_regi11 (9);
a12_cb_regi12 (10) <= a12_cb_regi12 (9);
b12_cb_regi12 (10) <= b12_cb_regi12 (9);
a13_cb_regi13 (10) <= a13_cb_regi13 (9);
b13_cb_regi13 (10) <= b13_cb_regi13 (9);
a14_cb_regi14 (10) <= a14_cb_regi14 (9);
b14_cb_regi14 (10) <= b14_cb_regi14 (9);
a15_cb_regi15 (10) <= a15_cb_regi15 (9);
b15_cb_regi15 (10) <= b15_cb_regi15 (9);
a12_cb_regi12 (11) <= a12_cb_regi12 (10);
b12_cb_regi12 (11) <= b12_cb_regi12 (10);
a13_cb_regi13 (11) <= a13_cb_regi13 (10);
b13_cb_regi13 (11) <= b13_cb_regi13 (10);
a14_cb_regi14 (11) <= a14_cb_regi14 (10);
b14_cb_regi14 (11) <= b14_cb_regi14 (10);
a15_cb_regi15 (11) <= a15_cb_regi15 (10);
b15_cb_regi15 (11) <= b15_cb_regi15 (10);
a13_cb_regi13 (12) <= a13_cb_regi13 (11);
b13_cb_regi13 (12) <= b13_cb_regi13 (11);
a14_cb_regi14 (12) <= a14_cb_regi14 (11);
b14_cb_regi14 (12) <= b14_cb_regi14 (11);
a15_cb_regi15 (12) <= a15_cb_regi15 (11);
b15_cb_regi15 (12) <= b15_cb_regi15 (11);
a14_cb_regi14 (13) <= a14_cb_regi14 (12);
b14_cb_regi14 (13) <= b14_cb_regi14 (12);
a15_cb_regi15 (13) <= a15_cb_regi15 (12);
b15_cb_regi15 (13) <= b15_cb_regi15 (12);
a15_cb_regi15 (14) <= a15_cb_regi15 (13);
b15_cb_regi15 (14) <= b15_cb_regi15 (13);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
faccout3_co3_reg <= faccout3_co3;
faccout4_co4_reg <= faccout4_co4;
faccout5_co5_reg <= faccout5_co5;
faccout6_co6_reg <= faccout6_co6;
faccout7_co7_reg <= faccout7_co7;
faccout8_co8_reg <= faccout8_co8;
faccout9_co9_reg <= faccout9_co9;
faccout10_co10_reg <= faccout10_co10;
faccout11_co11_reg <= faccout11_co11;
faccout12_co12_reg <= faccout12_co12;
faccout13_co13_reg <= faccout13_co13;
faccout14_co14_reg <= faccout14_co14;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(15 downto 12),
facout => faccout3_co3);
u4 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a4_cb_regi4(3),
fab => b4_cb_regi4(3),
facin => faccout3_co3_reg,
fas => fas(19 downto 16),
facout => faccout4_co4);
u5 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a5_cb_regi5(4),
fab => b5_cb_regi5(4),
facin => faccout4_co4_reg,
fas => fas(23 downto 20),
facout => faccout5_co5);
u6 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a6_cb_regi6(5),
fab => b6_cb_regi6(5),
facin => faccout5_co5_reg,
fas => fas(27 downto 24),
facout => faccout6_co6);
u7 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a7_cb_regi7(6),
fab => b7_cb_regi7(6),
facin => faccout6_co6_reg,
fas => fas(31 downto 28),
facout => faccout7_co7);
u8 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a8_cb_regi8(7),
fab => b8_cb_regi8(7),
facin => faccout7_co7_reg,
fas => fas(35 downto 32),
facout => faccout8_co8);
u9 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a9_cb_regi9(8),
fab => b9_cb_regi9(8),
facin => faccout8_co8_reg,
fas => fas(39 downto 36),
facout => faccout9_co9);
u10 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a10_cb_regi10(9),
fab => b10_cb_regi10(9),
facin => faccout9_co9_reg,
fas => fas(43 downto 40),
facout => faccout10_co10);
u11 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a11_cb_regi11(10),
fab => b11_cb_regi11(10),
facin => faccout10_co10_reg,
fas => fas(47 downto 44),
facout => faccout11_co11);
u12 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a12_cb_regi12(11),
fab => b12_cb_regi12(11),
facin => faccout11_co11_reg,
fas => fas(51 downto 48),
facout => faccout12_co12);
u13 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a13_cb_regi13(12),
fab => b13_cb_regi13(12),
facin => faccout12_co12_reg,
fas => fas(55 downto 52),
facout => faccout13_co13);
u14 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder
port map
(faa => a14_cb_regi14(13),
fab => b14_cb_regi14(13),
facin => faccout13_co13_reg,
fas => fas(59 downto 56),
facout => faccout14_co14);
u15 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f
port map
(faa => a15_cb_regi15(14),
fab => b15_cb_regi15(14),
facin => faccout14_co14_reg,
fas => fas(63 downto 60),
facout => faccout15_co15);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s3_ca_rego3 (0) <= fas(15 downto 12);
s4_ca_rego4 (0) <= fas(19 downto 16);
s5_ca_rego5 (0) <= fas(23 downto 20);
s6_ca_rego6 (0) <= fas(27 downto 24);
s7_ca_rego7 (0) <= fas(31 downto 28);
s8_ca_rego8 (0) <= fas(35 downto 32);
s9_ca_rego9 (0) <= fas(39 downto 36);
s10_ca_rego10 (0) <= fas(43 downto 40);
s11_ca_rego11 (0) <= fas(47 downto 44);
s12_ca_rego12 (0) <= fas(51 downto 48);
s13_ca_rego13 (0) <= fas(55 downto 52);
s14_ca_rego14 (0) <= fas(59 downto 56);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s0_ca_rego0 (3) <= s0_ca_rego0 (2);
s0_ca_rego0 (4) <= s0_ca_rego0 (3);
s0_ca_rego0 (5) <= s0_ca_rego0 (4);
s0_ca_rego0 (6) <= s0_ca_rego0 (5);
s0_ca_rego0 (7) <= s0_ca_rego0 (6);
s0_ca_rego0 (8) <= s0_ca_rego0 (7);
s0_ca_rego0 (9) <= s0_ca_rego0 (8);
s0_ca_rego0 (10) <= s0_ca_rego0 (9);
s0_ca_rego0 (11) <= s0_ca_rego0 (10);
s0_ca_rego0 (12) <= s0_ca_rego0 (11);
s0_ca_rego0 (13) <= s0_ca_rego0 (12);
s0_ca_rego0 (14) <= s0_ca_rego0 (13);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
s1_ca_rego1 (2) <= s1_ca_rego1 (1);
s1_ca_rego1 (3) <= s1_ca_rego1 (2);
s1_ca_rego1 (4) <= s1_ca_rego1 (3);
s1_ca_rego1 (5) <= s1_ca_rego1 (4);
s1_ca_rego1 (6) <= s1_ca_rego1 (5);
s1_ca_rego1 (7) <= s1_ca_rego1 (6);
s1_ca_rego1 (8) <= s1_ca_rego1 (7);
s1_ca_rego1 (9) <= s1_ca_rego1 (8);
s1_ca_rego1 (10) <= s1_ca_rego1 (9);
s1_ca_rego1 (11) <= s1_ca_rego1 (10);
s1_ca_rego1 (12) <= s1_ca_rego1 (11);
s1_ca_rego1 (13) <= s1_ca_rego1 (12);
s2_ca_rego2 (1) <= s2_ca_rego2 (0);
s2_ca_rego2 (2) <= s2_ca_rego2 (1);
s2_ca_rego2 (3) <= s2_ca_rego2 (2);
s2_ca_rego2 (4) <= s2_ca_rego2 (3);
s2_ca_rego2 (5) <= s2_ca_rego2 (4);
s2_ca_rego2 (6) <= s2_ca_rego2 (5);
s2_ca_rego2 (7) <= s2_ca_rego2 (6);
s2_ca_rego2 (8) <= s2_ca_rego2 (7);
s2_ca_rego2 (9) <= s2_ca_rego2 (8);
s2_ca_rego2 (10) <= s2_ca_rego2 (9);
s2_ca_rego2 (11) <= s2_ca_rego2 (10);
s2_ca_rego2 (12) <= s2_ca_rego2 (11);
s3_ca_rego3 (1) <= s3_ca_rego3 (0);
s3_ca_rego3 (2) <= s3_ca_rego3 (1);
s3_ca_rego3 (3) <= s3_ca_rego3 (2);
s3_ca_rego3 (4) <= s3_ca_rego3 (3);
s3_ca_rego3 (5) <= s3_ca_rego3 (4);
s3_ca_rego3 (6) <= s3_ca_rego3 (5);
s3_ca_rego3 (7) <= s3_ca_rego3 (6);
s3_ca_rego3 (8) <= s3_ca_rego3 (7);
s3_ca_rego3 (9) <= s3_ca_rego3 (8);
s3_ca_rego3 (10) <= s3_ca_rego3 (9);
s3_ca_rego3 (11) <= s3_ca_rego3 (10);
s4_ca_rego4 (1) <= s4_ca_rego4 (0);
s4_ca_rego4 (2) <= s4_ca_rego4 (1);
s4_ca_rego4 (3) <= s4_ca_rego4 (2);
s4_ca_rego4 (4) <= s4_ca_rego4 (3);
s4_ca_rego4 (5) <= s4_ca_rego4 (4);
s4_ca_rego4 (6) <= s4_ca_rego4 (5);
s4_ca_rego4 (7) <= s4_ca_rego4 (6);
s4_ca_rego4 (8) <= s4_ca_rego4 (7);
s4_ca_rego4 (9) <= s4_ca_rego4 (8);
s4_ca_rego4 (10) <= s4_ca_rego4 (9);
s5_ca_rego5 (1) <= s5_ca_rego5 (0);
s5_ca_rego5 (2) <= s5_ca_rego5 (1);
s5_ca_rego5 (3) <= s5_ca_rego5 (2);
s5_ca_rego5 (4) <= s5_ca_rego5 (3);
s5_ca_rego5 (5) <= s5_ca_rego5 (4);
s5_ca_rego5 (6) <= s5_ca_rego5 (5);
s5_ca_rego5 (7) <= s5_ca_rego5 (6);
s5_ca_rego5 (8) <= s5_ca_rego5 (7);
s5_ca_rego5 (9) <= s5_ca_rego5 (8);
s6_ca_rego6 (1) <= s6_ca_rego6 (0);
s6_ca_rego6 (2) <= s6_ca_rego6 (1);
s6_ca_rego6 (3) <= s6_ca_rego6 (2);
s6_ca_rego6 (4) <= s6_ca_rego6 (3);
s6_ca_rego6 (5) <= s6_ca_rego6 (4);
s6_ca_rego6 (6) <= s6_ca_rego6 (5);
s6_ca_rego6 (7) <= s6_ca_rego6 (6);
s6_ca_rego6 (8) <= s6_ca_rego6 (7);
s7_ca_rego7 (1) <= s7_ca_rego7 (0);
s7_ca_rego7 (2) <= s7_ca_rego7 (1);
s7_ca_rego7 (3) <= s7_ca_rego7 (2);
s7_ca_rego7 (4) <= s7_ca_rego7 (3);
s7_ca_rego7 (5) <= s7_ca_rego7 (4);
s7_ca_rego7 (6) <= s7_ca_rego7 (5);
s7_ca_rego7 (7) <= s7_ca_rego7 (6);
s8_ca_rego8 (1) <= s8_ca_rego8 (0);
s8_ca_rego8 (2) <= s8_ca_rego8 (1);
s8_ca_rego8 (3) <= s8_ca_rego8 (2);
s8_ca_rego8 (4) <= s8_ca_rego8 (3);
s8_ca_rego8 (5) <= s8_ca_rego8 (4);
s8_ca_rego8 (6) <= s8_ca_rego8 (5);
s9_ca_rego9 (1) <= s9_ca_rego9 (0);
s9_ca_rego9 (2) <= s9_ca_rego9 (1);
s9_ca_rego9 (3) <= s9_ca_rego9 (2);
s9_ca_rego9 (4) <= s9_ca_rego9 (3);
s9_ca_rego9 (5) <= s9_ca_rego9 (4);
s10_ca_rego10 (1) <= s10_ca_rego10 (0);
s10_ca_rego10 (2) <= s10_ca_rego10 (1);
s10_ca_rego10 (3) <= s10_ca_rego10 (2);
s10_ca_rego10 (4) <= s10_ca_rego10 (3);
s11_ca_rego11 (1) <= s11_ca_rego11 (0);
s11_ca_rego11 (2) <= s11_ca_rego11 (1);
s11_ca_rego11 (3) <= s11_ca_rego11 (2);
s12_ca_rego12 (1) <= s12_ca_rego12 (0);
s12_ca_rego12 (2) <= s12_ca_rego12 (1);
s13_ca_rego13 (1) <= s13_ca_rego13 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(14);
s_tmp(7 downto 4) <= s1_ca_rego1(13);
s_tmp(11 downto 8) <= s2_ca_rego2(12);
s_tmp(15 downto 12) <= s3_ca_rego3(11);
s_tmp(19 downto 16) <= s4_ca_rego4(10);
s_tmp(23 downto 20) <= s5_ca_rego5(9);
s_tmp(27 downto 24) <= s6_ca_rego6(8);
s_tmp(31 downto 28) <= s7_ca_rego7(7);
s_tmp(35 downto 32) <= s8_ca_rego8(6);
s_tmp(39 downto 36) <= s9_ca_rego9(5);
s_tmp(43 downto 40) <= s10_ca_rego10(4);
s_tmp(47 downto 44) <= s11_ca_rego11(3);
s_tmp(51 downto 48) <= s12_ca_rego12(2);
s_tmp(55 downto 52) <= s13_ca_rego13(1);
s_tmp(59 downto 56) <= s14_ca_rego14(0);
s_tmp(63 downto 60) <= fas(63 downto 60);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 is
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_U : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.vhd | 3 | 9512 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/syn/vhdl/nfa_accept_samples_generic_hw_add_32ns_32s_32_8.vhd | 6 | 15847 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
s: out std_logic_vector(31 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is
component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(31 downto 0);
signal b_reg : std_logic_vector(31 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(15 downto 12);
signal b3_cb : std_logic_vector(15 downto 12);
signal a4_cb : std_logic_vector(19 downto 16);
signal b4_cb : std_logic_vector(19 downto 16);
signal a5_cb : std_logic_vector(23 downto 20);
signal b5_cb : std_logic_vector(23 downto 20);
signal a6_cb : std_logic_vector(27 downto 24);
signal b6_cb : std_logic_vector(27 downto 24);
signal a7_cb : std_logic_vector(31 downto 28);
signal b7_cb : std_logic_vector(31 downto 28);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal a4_cb_regi4 : ramtypei3;
signal b4_cb_regi4 : ramtypei3;
type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal a5_cb_regi5 : ramtypei4;
signal b5_cb_regi5 : ramtypei4;
type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal a6_cb_regi6 : ramtypei5;
signal b6_cb_regi6 : ramtypei5;
type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal a7_cb_regi7 : ramtypei6;
signal b7_cb_regi7 : ramtypei6;
-- wires for each full adder sum
signal fas : std_logic_vector(31 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout4_co4 : std_logic_vector (0 downto 0);
signal faccout5_co5 : std_logic_vector (0 downto 0);
signal faccout6_co6 : std_logic_vector (0 downto 0);
signal faccout7_co7 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
signal faccout3_co3_reg : std_logic_vector (0 downto 0);
signal faccout4_co4_reg : std_logic_vector (0 downto 0);
signal faccout5_co5_reg : std_logic_vector (0 downto 0);
signal faccout6_co6_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo6;
type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo5;
type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo4;
type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal s3_ca_rego3 : ramtypeo3;
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s4_ca_rego4 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s5_ca_rego5 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s6_ca_rego6 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(31 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(15 downto 12);
b3_cb <= b_reg(15 downto 12);
a4_cb <= a_reg(19 downto 16);
b4_cb <= b_reg(19 downto 16);
a5_cb <= a_reg(23 downto 20);
b5_cb <= b_reg(23 downto 20);
a6_cb <= a_reg(27 downto 24);
b6_cb <= b_reg(27 downto 24);
a7_cb <= a_reg(31 downto 28);
b7_cb <= b_reg(31 downto 28);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a4_cb_regi4 (0) <= a4_cb;
b4_cb_regi4 (0) <= b4_cb;
a5_cb_regi5 (0) <= a5_cb;
b5_cb_regi5 (0) <= b5_cb;
a6_cb_regi6 (0) <= a6_cb;
b6_cb_regi6 (0) <= b6_cb;
a7_cb_regi7 (0) <= a7_cb;
b7_cb_regi7 (0) <= b7_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a4_cb_regi4 (1) <= a4_cb_regi4 (0);
b4_cb_regi4 (1) <= b4_cb_regi4 (0);
a5_cb_regi5 (1) <= a5_cb_regi5 (0);
b5_cb_regi5 (1) <= b5_cb_regi5 (0);
a6_cb_regi6 (1) <= a6_cb_regi6 (0);
b6_cb_regi6 (1) <= b6_cb_regi6 (0);
a7_cb_regi7 (1) <= a7_cb_regi7 (0);
b7_cb_regi7 (1) <= b7_cb_regi7 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
a4_cb_regi4 (2) <= a4_cb_regi4 (1);
b4_cb_regi4 (2) <= b4_cb_regi4 (1);
a5_cb_regi5 (2) <= a5_cb_regi5 (1);
b5_cb_regi5 (2) <= b5_cb_regi5 (1);
a6_cb_regi6 (2) <= a6_cb_regi6 (1);
b6_cb_regi6 (2) <= b6_cb_regi6 (1);
a7_cb_regi7 (2) <= a7_cb_regi7 (1);
b7_cb_regi7 (2) <= b7_cb_regi7 (1);
a4_cb_regi4 (3) <= a4_cb_regi4 (2);
b4_cb_regi4 (3) <= b4_cb_regi4 (2);
a5_cb_regi5 (3) <= a5_cb_regi5 (2);
b5_cb_regi5 (3) <= b5_cb_regi5 (2);
a6_cb_regi6 (3) <= a6_cb_regi6 (2);
b6_cb_regi6 (3) <= b6_cb_regi6 (2);
a7_cb_regi7 (3) <= a7_cb_regi7 (2);
b7_cb_regi7 (3) <= b7_cb_regi7 (2);
a5_cb_regi5 (4) <= a5_cb_regi5 (3);
b5_cb_regi5 (4) <= b5_cb_regi5 (3);
a6_cb_regi6 (4) <= a6_cb_regi6 (3);
b6_cb_regi6 (4) <= b6_cb_regi6 (3);
a7_cb_regi7 (4) <= a7_cb_regi7 (3);
b7_cb_regi7 (4) <= b7_cb_regi7 (3);
a6_cb_regi6 (5) <= a6_cb_regi6 (4);
b6_cb_regi6 (5) <= b6_cb_regi6 (4);
a7_cb_regi7 (5) <= a7_cb_regi7 (4);
b7_cb_regi7 (5) <= b7_cb_regi7 (4);
a7_cb_regi7 (6) <= a7_cb_regi7 (5);
b7_cb_regi7 (6) <= b7_cb_regi7 (5);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
faccout3_co3_reg <= faccout3_co3;
faccout4_co4_reg <= faccout4_co4;
faccout5_co5_reg <= faccout5_co5;
faccout6_co6_reg <= faccout6_co6;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(15 downto 12),
facout => faccout3_co3);
u4 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a4_cb_regi4(3),
fab => b4_cb_regi4(3),
facin => faccout3_co3_reg,
fas => fas(19 downto 16),
facout => faccout4_co4);
u5 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a5_cb_regi5(4),
fab => b5_cb_regi5(4),
facin => faccout4_co4_reg,
fas => fas(23 downto 20),
facout => faccout5_co5);
u6 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
port map
(faa => a6_cb_regi6(5),
fab => b6_cb_regi6(5),
facin => faccout5_co5_reg,
fas => fas(27 downto 24),
facout => faccout6_co6);
u7 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f
port map
(faa => a7_cb_regi7(6),
fab => b7_cb_regi7(6),
facin => faccout6_co6_reg,
fas => fas(31 downto 28),
facout => faccout7_co7);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s3_ca_rego3 (0) <= fas(15 downto 12);
s4_ca_rego4 (0) <= fas(19 downto 16);
s5_ca_rego5 (0) <= fas(23 downto 20);
s6_ca_rego6 (0) <= fas(27 downto 24);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s0_ca_rego0 (3) <= s0_ca_rego0 (2);
s0_ca_rego0 (4) <= s0_ca_rego0 (3);
s0_ca_rego0 (5) <= s0_ca_rego0 (4);
s0_ca_rego0 (6) <= s0_ca_rego0 (5);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
s1_ca_rego1 (2) <= s1_ca_rego1 (1);
s1_ca_rego1 (3) <= s1_ca_rego1 (2);
s1_ca_rego1 (4) <= s1_ca_rego1 (3);
s1_ca_rego1 (5) <= s1_ca_rego1 (4);
s2_ca_rego2 (1) <= s2_ca_rego2 (0);
s2_ca_rego2 (2) <= s2_ca_rego2 (1);
s2_ca_rego2 (3) <= s2_ca_rego2 (2);
s2_ca_rego2 (4) <= s2_ca_rego2 (3);
s3_ca_rego3 (1) <= s3_ca_rego3 (0);
s3_ca_rego3 (2) <= s3_ca_rego3 (1);
s3_ca_rego3 (3) <= s3_ca_rego3 (2);
s4_ca_rego4 (1) <= s4_ca_rego4 (0);
s4_ca_rego4 (2) <= s4_ca_rego4 (1);
s5_ca_rego5 (1) <= s5_ca_rego5 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(6);
s_tmp(7 downto 4) <= s1_ca_rego1(5);
s_tmp(11 downto 8) <= s2_ca_rego2(4);
s_tmp(15 downto 12) <= s3_ca_rego3(3);
s_tmp(19 downto 16) <= s4_ca_rego4(2);
s_tmp(23 downto 20) <= s5_ca_rego5(1);
s_tmp(27 downto 24) <= s6_ca_rego6(0);
s_tmp(31 downto 28) <= fas(31 downto 28);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_32ns_32s_32_8 is
component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_U : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_get_initials.vhd | 4 | 15083 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_sig_bdd_67 : BOOLEAN;
signal ap_sig_bdd_135 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_read_reg_63 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it2 , ap_reg_ppiten_pp0_it3 , nfa_initials_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_63;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_135 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_136 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_67 assign process. --
ap_sig_bdd_67_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_67 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_sig_bdd_136, ap_sig_bdd_67, ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
if (ap_sig_bdd_67) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_136) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan6/syn/vhdl/sample_iterator_get_offset.vhd | 1 | 35975 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_145 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_165 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_110_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_1_reg_170 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_110_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_110_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_110_ce : STD_LOGIC;
signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_110_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_110_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4
generic map (
ID => 0,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_110_p0,
din1 => grp_fu_110_p1,
ce => grp_fu_110_ce,
dout => grp_fu_110_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_125_p0,
din1 => grp_fu_125_p1,
ce => grp_fu_125_ce,
dout => grp_fu_125_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_tmp_reg_135_pp0_it1(0) <= tmp_reg_135(0);
ap_reg_ppstg_tmp_reg_135_pp0_it1(1) <= tmp_reg_135(1);
ap_reg_ppstg_tmp_reg_135_pp0_it1(2) <= tmp_reg_135(2);
ap_reg_ppstg_tmp_reg_135_pp0_it1(3) <= tmp_reg_135(3);
ap_reg_ppstg_tmp_reg_135_pp0_it1(4) <= tmp_reg_135(4);
ap_reg_ppstg_tmp_reg_135_pp0_it1(5) <= tmp_reg_135(5);
ap_reg_ppstg_tmp_reg_135_pp0_it1(6) <= tmp_reg_135(6);
ap_reg_ppstg_tmp_reg_135_pp0_it1(7) <= tmp_reg_135(7);
ap_reg_ppstg_tmp_reg_135_pp0_it1(8) <= tmp_reg_135(8);
ap_reg_ppstg_tmp_reg_135_pp0_it1(9) <= tmp_reg_135(9);
ap_reg_ppstg_tmp_reg_135_pp0_it1(10) <= tmp_reg_135(10);
ap_reg_ppstg_tmp_reg_135_pp0_it1(11) <= tmp_reg_135(11);
ap_reg_ppstg_tmp_reg_135_pp0_it1(12) <= tmp_reg_135(12);
ap_reg_ppstg_tmp_reg_135_pp0_it1(13) <= tmp_reg_135(13);
ap_reg_ppstg_tmp_reg_135_pp0_it1(14) <= tmp_reg_135(14);
ap_reg_ppstg_tmp_reg_135_pp0_it1(15) <= tmp_reg_135(15);
ap_reg_ppstg_tmp_reg_135_pp0_it2(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(0);
ap_reg_ppstg_tmp_reg_135_pp0_it2(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(1);
ap_reg_ppstg_tmp_reg_135_pp0_it2(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(2);
ap_reg_ppstg_tmp_reg_135_pp0_it2(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(3);
ap_reg_ppstg_tmp_reg_135_pp0_it2(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(4);
ap_reg_ppstg_tmp_reg_135_pp0_it2(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(5);
ap_reg_ppstg_tmp_reg_135_pp0_it2(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(6);
ap_reg_ppstg_tmp_reg_135_pp0_it2(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(7);
ap_reg_ppstg_tmp_reg_135_pp0_it2(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(8);
ap_reg_ppstg_tmp_reg_135_pp0_it2(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(9);
ap_reg_ppstg_tmp_reg_135_pp0_it2(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(10);
ap_reg_ppstg_tmp_reg_135_pp0_it2(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(11);
ap_reg_ppstg_tmp_reg_135_pp0_it2(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(12);
ap_reg_ppstg_tmp_reg_135_pp0_it2(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(13);
ap_reg_ppstg_tmp_reg_135_pp0_it2(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(14);
ap_reg_ppstg_tmp_reg_135_pp0_it2(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(15);
ap_reg_ppstg_tmp_reg_135_pp0_it3(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(0);
ap_reg_ppstg_tmp_reg_135_pp0_it3(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(1);
ap_reg_ppstg_tmp_reg_135_pp0_it3(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(2);
ap_reg_ppstg_tmp_reg_135_pp0_it3(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(3);
ap_reg_ppstg_tmp_reg_135_pp0_it3(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(4);
ap_reg_ppstg_tmp_reg_135_pp0_it3(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(5);
ap_reg_ppstg_tmp_reg_135_pp0_it3(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(6);
ap_reg_ppstg_tmp_reg_135_pp0_it3(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(7);
ap_reg_ppstg_tmp_reg_135_pp0_it3(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(8);
ap_reg_ppstg_tmp_reg_135_pp0_it3(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(9);
ap_reg_ppstg_tmp_reg_135_pp0_it3(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(10);
ap_reg_ppstg_tmp_reg_135_pp0_it3(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(11);
ap_reg_ppstg_tmp_reg_135_pp0_it3(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(12);
ap_reg_ppstg_tmp_reg_135_pp0_it3(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(13);
ap_reg_ppstg_tmp_reg_135_pp0_it3(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(14);
ap_reg_ppstg_tmp_reg_135_pp0_it3(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_130 <= i_sample;
tmp_reg_135(0) <= tmp_fu_93_p1(0);
tmp_reg_135(1) <= tmp_fu_93_p1(1);
tmp_reg_135(2) <= tmp_fu_93_p1(2);
tmp_reg_135(3) <= tmp_fu_93_p1(3);
tmp_reg_135(4) <= tmp_fu_93_p1(4);
tmp_reg_135(5) <= tmp_fu_93_p1(5);
tmp_reg_135(6) <= tmp_fu_93_p1(6);
tmp_reg_135(7) <= tmp_fu_93_p1(7);
tmp_reg_135(8) <= tmp_fu_93_p1(8);
tmp_reg_135(9) <= tmp_fu_93_p1(9);
tmp_reg_135(10) <= tmp_fu_93_p1(10);
tmp_reg_135(11) <= tmp_fu_93_p1(11);
tmp_reg_135(12) <= tmp_fu_93_p1(12);
tmp_reg_135(13) <= tmp_fu_93_p1(13);
tmp_reg_135(14) <= tmp_fu_93_p1(14);
tmp_reg_135(15) <= tmp_fu_93_p1(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_165 <= indices_begin_datain;
tmp_1_reg_170 <= grp_fu_110_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_145 <= indices_stride_datain;
end if;
end if;
end process;
tmp_reg_135(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it2(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it3(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it5 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it13, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= grp_fu_125_p2;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_110_ce assign process. --
grp_fu_110_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_110_ce <= ap_const_logic_1;
else
grp_fu_110_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_110_p0 <= grp_fu_110_p00(16 - 1 downto 0);
grp_fu_110_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1),24));
grp_fu_110_p1 <= grp_fu_110_p10(8 - 1 downto 0);
grp_fu_110_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_145),24));
-- grp_fu_125_ce assign process. --
grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_125_ce <= ap_const_logic_1;
else
grp_fu_125_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_1_reg_170),32));
grp_fu_125_p1 <= indices_begin_addr_read_reg_165;
indices_begin_address <= ap_reg_ppstg_tmp_reg_135_pp0_it3;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),32));
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/vhdl/bitset_next.vhd | 2 | 20856 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal tmp_fu_131_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0);
signal bus_assign_fu_141_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_147_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_225 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_165_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_25_1_fu_153_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_1_fu_159_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_p_bsf32_hw_fu_120_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i1_p_bsf32_hw_fu_120_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_i_p_bsf32_hw_fu_126_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_p_bsf32_hw_fu_126_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_74_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_93_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_109_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_169_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_135_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_174_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
begin
tmp_i1_p_bsf32_hw_fu_120 : component p_bsf32_hw
port map (
bus_r => tmp_i1_p_bsf32_hw_fu_120_bus_r,
ap_return => tmp_i1_p_bsf32_hw_fu_120_ap_return);
tmp_i_p_bsf32_hw_fu_126 : component p_bsf32_hw
port map (
bus_r => tmp_i_p_bsf32_hw_fu_126_bus_r,
ap_return => tmp_i_p_bsf32_hw_fu_126_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= r_bit;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= agg_result_bit_write_assign_trunc3_ext_fu_165_p1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_const_lv2_2;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_const_lv2_1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_const_lv32_0;
elsif ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= p_read;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_0;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
bus_assign_reg_219 <= bus_assign_fu_141_p2;
tmp_3_reg_225 <= tmp_3_fu_147_p2;
tmp_reg_214 <= tmp_fu_131_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- agg_result_bit_write_assign_phi_fu_109_p8 assign process. --
agg_result_bit_write_assign_phi_fu_109_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1, agg_result_bit_write_assign_trunc_ext_fu_169_p1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bit_write_assign_phi_fu_109_p8 <= agg_result_bit_write_assign_trunc_ext_fu_169_p1;
else
agg_result_bit_write_assign_phi_fu_109_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_165_p1 <= std_logic_vector(resize(unsigned(tmp_i1_p_bsf32_hw_fu_120_ap_return),8));
agg_result_bit_write_assign_trunc_ext_fu_169_p1 <= std_logic_vector(resize(unsigned(tmp_i_p_bsf32_hw_fu_126_ap_return),8));
agg_result_bucket_index_write_assign_cast_fu_174_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_93_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_93_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_93_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_reg_214, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bucket_index_write_assign_phi_fu_93_p8 <= tmp_reg_214;
else
agg_result_bucket_index_write_assign_phi_fu_93_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, bus_assign_reg_219, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= bus_assign_reg_219;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_74_p8 assign process. --
agg_result_end_write_assign_phi_fu_74_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_3_reg_225, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_end_write_assign_phi_fu_74_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_74_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0 <= ap_const_lv1_1;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_109_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_174_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_74_p8;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
bus_assign_fu_141_p2 <= (tmp_1_fu_135_p2 and r_bucket);
tmp_1_fu_135_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF));
tmp_25_1_fu_153_p2 <= "1" when (tmp_fu_131_p1 = ap_const_lv2_0) else "0";
tmp_27_1_fu_159_p2 <= "1" when (p_read = ap_const_lv32_0) else "0";
tmp_3_fu_147_p2 <= "1" when (bus_assign_fu_141_p2 = ap_const_lv32_0) else "0";
tmp_fu_131_p1 <= r_bucket_index(2 - 1 downto 0);
tmp_i1_p_bsf32_hw_fu_120_bus_r <= p_read;
tmp_i_p_bsf32_hw_fu_126_bus_r <= bus_assign_reg_219;
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_finals_buckets_if.vhd | 2 | 21268 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_finals_buckets_if OF nfa_finals_buckets_if IS
component nfa_finals_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_finals_buckets_if_rd_fifo: component nfa_finals_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_finals_buckets_if_rd_user_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_finals_buckets_if;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_finals_buckets_if.vhd | 2 | 21268 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_finals_buckets_if OF nfa_finals_buckets_if IS
component nfa_finals_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_finals_buckets_if_rd_fifo: component nfa_finals_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_finals_buckets_if_rd_user_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_finals_buckets_if;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_initials_buckets_if.vhd | 2 | 27940 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_initials_buckets_if is
component nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_initials_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_initials_buckets_if_req_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_initials_buckets_if_plb_master_if: component nfa_initials_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_initials_buckets_if_rsp_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_initials_buckets_if_rd_data_user_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_single/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd | 1 | 37679 | ------------------------------------------------------------------------------
-- C:/Users/JairoAndres/Documents/Vivado/oil_plainc_hls/impl/impl_test_single/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "virtex5" ;
C_DEVICE : string := "5vlx50t";
C_PACKAGE : string := "ff1136";
C_SPEEDGRADE : string := "-2";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 12,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 24,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 1,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0,
C_CLKOUT2_DIVIDE => 1,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0,
C_CLKOUT3_DIVIDE => 1,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1;
-- wrapper of clkout : CLKOUT2
SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2;
-- wrapper of clkout : CLKOUT3
SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3;
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = virtex5
-- C_DEVICE = 5vlx50t
-- C_PACKAGE = ff1136
-- C_SPEEDGRADE = -2
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 50000000
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "virtex5"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "virtex5"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "virtex5"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "virtex5"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 12
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 24
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0000
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 0
-- C_PLL0_FAMILY = "virtex5"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "virtex5"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "virtex5"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "virtex5"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "virtex5"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "virtex5"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_dlmb_cntlr_wrapper.vhd | 1 | 18331 | -------------------------------------------------------------------------------
-- system_dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end system_dlmb_cntlr_wrapper;
architecture STRUCTURE of system_dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan3/impl/vhdl/nfa_accept_sample.vhd | 1 | 69807 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
signal reg_378 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_585 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_cast_fu_390_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_cast_reg_600 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_405_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_605 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_410_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_609 : STD_LOGIC_VECTOR (15 downto 0);
signal sample_addr_1_reg_614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_fu_428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_i_reg_620 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_422_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_reg_624 : STD_LOGIC_VECTOR (63 downto 0);
signal sym_reg_629 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_1_i_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_1_i_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_reg_638 : STD_LOGIC_VECTOR (4 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bucket_index1_ph_cast_fu_444_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_448_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_i_cast_fu_452_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_i_cast_reg_658 : STD_LOGIC_VECTOR (13 downto 0);
signal j_end_phi_fu_316_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_673 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_i_reg_688 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_693 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_698 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_703 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_708 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_490_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_8_i_reg_713 : STD_LOGIC_VECTOR (13 downto 0);
signal next_buckets_0_1_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_731 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_552_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_reg_756 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_761 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_580_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_766 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_ce : STD_LOGIC;
signal i_reg_138 : STD_LOGIC_VECTOR (15 downto 0);
signal any_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal p_01_rec_reg_150 : STD_LOGIC_VECTOR (63 downto 0);
signal next_buckets_1_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_reg_172 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_182 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_194 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_207 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_220 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_231 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_242 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_269 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_282 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_293 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_303 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal any_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_336 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_fu_400_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_i_cast_fu_517_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_i_cast_fu_535_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_410_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_410_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_422_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_422_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_fu_455_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_471_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_484_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_490_p0 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_490_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_4_i_fu_510_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_9_i_fu_528_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_400_ce : STD_LOGIC;
signal grp_fu_410_ce : STD_LOGIC;
signal grp_fu_422_ce : STD_LOGIC;
signal grp_fu_471_ce : STD_LOGIC;
signal grp_fu_484_ce : STD_LOGIC;
signal grp_fu_490_ce : STD_LOGIC;
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal grp_fu_484_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_484_p10 : STD_LOGIC_VECTOR (13 downto 0);
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (5 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (13 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_348 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
p_read => grp_bitset_next_fu_348_p_read,
r_bit => grp_bitset_next_fu_348_r_bit,
r_bucket_index => grp_bitset_next_fu_348_r_bucket_index,
r_bucket => grp_bitset_next_fu_348_r_bucket,
ap_return_0 => grp_bitset_next_fu_348_ap_return_0,
ap_return_1 => grp_bitset_next_fu_348_ap_return_1,
ap_return_2 => grp_bitset_next_fu_348_ap_return_2,
ap_return_3 => grp_bitset_next_fu_348_ap_return_3,
ap_ce => grp_bitset_next_fu_348_ap_ce);
grp_nfa_get_initials_fu_360 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_360_ap_start,
ap_done => grp_nfa_get_initials_fu_360_ap_done,
ap_idle => grp_nfa_get_initials_fu_360_ap_idle,
ap_ready => grp_nfa_get_initials_fu_360_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_360_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_360_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_fu_360_ap_ce,
ap_return_0 => grp_nfa_get_initials_fu_360_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_360_ap_return_1);
grp_nfa_get_finals_fu_366 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_366_ap_start,
ap_done => grp_nfa_get_finals_fu_366_ap_done,
ap_idle => grp_nfa_get_finals_fu_366_ap_idle,
ap_ready => grp_nfa_get_finals_fu_366_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_366_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_366_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_fu_366_ap_ce,
ap_return_0 => grp_nfa_get_finals_fu_366_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_366_ap_return_1);
grp_p_bsf32_hw_fu_372 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_372_bus_r,
ap_return => grp_p_bsf32_hw_fu_372_ap_return,
ap_ce => grp_p_bsf32_hw_fu_372_ap_ce);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U17 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 17,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_400_p0,
din1 => grp_fu_400_p1,
ce => grp_fu_400_ce,
dout => grp_fu_400_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 18,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_410_p0,
din1 => grp_fu_410_p1,
ce => grp_fu_410_ce,
dout => grp_fu_410_p2);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U19 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 19,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_422_p0,
din1 => grp_fu_422_p1,
ce => grp_fu_422_ce,
dout => grp_fu_422_p2);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2
generic map (
ID => 20,
NUM_STAGE => 2,
din0_WIDTH => 6,
din1_WIDTH => 6,
dout_WIDTH => 6)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_471_p0,
din1 => grp_fu_471_p1,
ce => grp_fu_471_ce,
dout => grp_fu_471_p2);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9
generic map (
ID => 21,
NUM_STAGE => 9,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_484_p0,
din1 => grp_fu_484_p1,
ce => grp_fu_484_ce,
dout => grp_fu_484_p2);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4
generic map (
ID => 22,
NUM_STAGE => 4,
din0_WIDTH => 14,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_490_p0,
din1 => grp_fu_490_p1,
ce => grp_fu_490_ce,
dout => grp_fu_490_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_336;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_366_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st24_fsm_23 = ap_NS_fsm) and (ap_ST_st23_fsm_22 = ap_CS_fsm) and (tmp_s_reg_605 = ap_const_lv1_0))) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_366_ap_ready)) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_194 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_1;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_reg_323 assign process. --
any_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_182 assign process. --
bus_assign_reg_182_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_1_reg_162;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_0_reg_172;
end if;
end if;
end process;
-- i_reg_138 assign process. --
i_reg_138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
i_reg_138 <= i_1_reg_609;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
i_reg_138 <= ap_const_lv16_0;
end if;
end if;
end process;
-- j_bit1_reg_303 assign process. --
j_bit1_reg_303_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit1_ph_cast_fu_448_p1;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit_reg_693;
end if;
end if;
end process;
-- j_bucket1_ph_reg_207 assign process. --
j_bucket1_ph_reg_207_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket1_ph_reg_207 <= bus_assign_reg_182;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket1_ph_reg_207 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_282 assign process. --
j_bucket1_reg_282_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket1_ph_reg_207;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket_reg_703;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_220 assign process. --
j_bucket_index1_ph_reg_220_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_220 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket_index1_ph_reg_220 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_293 assign process. --
j_bucket_index1_reg_293_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index1_ph_cast_fu_444_p1;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index_reg_698;
end if;
end if;
end process;
-- j_end_ph_reg_242 assign process. --
j_end_ph_reg_242_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_end_ph_reg_242 <= ap_const_lv1_0;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_end_ph_reg_242 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_313 assign process. --
j_end_reg_313_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_end_reg_313 <= j_end_ph_reg_242;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_end_reg_313 <= p_s_reg_708;
end if;
end if;
end process;
-- next_buckets_0_reg_172 assign process. --
next_buckets_0_reg_172_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_0_reg_172 <= tmp_buckets_0_3_reg_269;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_0_reg_172 <= current_buckets_0_reg_585;
end if;
end if;
end process;
-- next_buckets_1_reg_162 assign process. --
next_buckets_1_reg_162_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_1_reg_162 <= tmp_buckets_1_3_reg_256;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_1_reg_162 <= current_buckets_1_reg_590;
end if;
end if;
end process;
-- p_01_rec_reg_150 assign process. --
p_01_rec_reg_150_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
p_01_rec_reg_150 <= p_rec_reg_624;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
p_01_rec_reg_150 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_336 assign process. --
p_0_reg_336_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
p_0_reg_336 <= ap_const_lv1_0;
elsif ((ap_ST_st77_fsm_76 = ap_CS_fsm)) then
p_0_reg_336 <= tmp_2_reg_766;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_269 assign process. --
tmp_buckets_0_3_reg_269_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= ap_const_lv32_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= next_buckets_0_1_reg_731;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_256 assign process. --
tmp_buckets_1_3_reg_256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= ap_const_lv32_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= next_buckets_1_1_fu_552_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st74_fsm_73 = ap_CS_fsm)) then
current_buckets_0_1_reg_751 <= current_buckets_0_1_fu_566_p2;
current_buckets_1_1_reg_756 <= current_buckets_1_1_fu_571_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
current_buckets_0_reg_585 <= grp_nfa_get_initials_fu_360_ap_return_0;
current_buckets_1_reg_590 <= grp_nfa_get_initials_fu_360_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
i_1_reg_609 <= grp_fu_410_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bit1_ph_reg_231 <= r_bit_reg_638;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then
j_bit_reg_693 <= grp_bitset_next_fu_348_ap_return_0;
j_bucket_index_reg_698 <= grp_bitset_next_fu_348_ap_return_1;
j_bucket_reg_703 <= grp_bitset_next_fu_348_ap_return_2;
p_s_reg_708 <= grp_bitset_next_fu_348_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm))) then
next_buckets_0_1_reg_731 <= next_buckets_0_1_fu_546_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
p_rec_reg_624 <= grp_fu_422_p2;
sym_reg_629 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
r_bit_reg_638 <= grp_p_bsf32_hw_fu_372_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st65_fsm_64 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm)))) then
reg_378 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
sample_addr_1_reg_614 <= grp_fu_400_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
state_reg_673 <= grp_fu_471_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
tmp_14_cast_reg_600(0) <= tmp_14_cast_fu_390_p1(0);
tmp_14_cast_reg_600(1) <= tmp_14_cast_fu_390_p1(1);
tmp_14_cast_reg_600(2) <= tmp_14_cast_fu_390_p1(2);
tmp_14_cast_reg_600(3) <= tmp_14_cast_fu_390_p1(3);
tmp_14_cast_reg_600(4) <= tmp_14_cast_fu_390_p1(4);
tmp_14_cast_reg_600(5) <= tmp_14_cast_fu_390_p1(5);
tmp_14_cast_reg_600(6) <= tmp_14_cast_fu_390_p1(6);
tmp_14_cast_reg_600(7) <= tmp_14_cast_fu_390_p1(7);
tmp_14_cast_reg_600(8) <= tmp_14_cast_fu_390_p1(8);
tmp_14_cast_reg_600(9) <= tmp_14_cast_fu_390_p1(9);
tmp_14_cast_reg_600(10) <= tmp_14_cast_fu_390_p1(10);
tmp_14_cast_reg_600(11) <= tmp_14_cast_fu_390_p1(11);
tmp_14_cast_reg_600(12) <= tmp_14_cast_fu_390_p1(12);
tmp_14_cast_reg_600(13) <= tmp_14_cast_fu_390_p1(13);
tmp_14_cast_reg_600(14) <= tmp_14_cast_fu_390_p1(14);
tmp_14_cast_reg_600(15) <= tmp_14_cast_fu_390_p1(15);
tmp_14_cast_reg_600(16) <= tmp_14_cast_fu_390_p1(16);
tmp_14_cast_reg_600(17) <= tmp_14_cast_fu_390_p1(17);
tmp_14_cast_reg_600(18) <= tmp_14_cast_fu_390_p1(18);
tmp_14_cast_reg_600(19) <= tmp_14_cast_fu_390_p1(19);
tmp_14_cast_reg_600(20) <= tmp_14_cast_fu_390_p1(20);
tmp_14_cast_reg_600(21) <= tmp_14_cast_fu_390_p1(21);
tmp_14_cast_reg_600(22) <= tmp_14_cast_fu_390_p1(22);
tmp_14_cast_reg_600(23) <= tmp_14_cast_fu_390_p1(23);
tmp_14_cast_reg_600(24) <= tmp_14_cast_fu_390_p1(24);
tmp_14_cast_reg_600(25) <= tmp_14_cast_fu_390_p1(25);
tmp_14_cast_reg_600(26) <= tmp_14_cast_fu_390_p1(26);
tmp_14_cast_reg_600(27) <= tmp_14_cast_fu_390_p1(27);
tmp_14_cast_reg_600(28) <= tmp_14_cast_fu_390_p1(28);
tmp_14_cast_reg_600(29) <= tmp_14_cast_fu_390_p1(29);
tmp_14_cast_reg_600(30) <= tmp_14_cast_fu_390_p1(30);
tmp_14_cast_reg_600(31) <= tmp_14_cast_fu_390_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then
tmp_19_1_i_reg_634 <= tmp_19_1_i_fu_434_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
tmp_19_i_reg_620 <= tmp_19_i_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st75_fsm_74 = ap_CS_fsm)) then
tmp_1_reg_761 <= tmp_1_fu_576_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st76_fsm_75 = ap_CS_fsm)) then
tmp_2_reg_766 <= tmp_2_fu_580_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st55_fsm_54 = ap_CS_fsm)) then
tmp_6_i_reg_688 <= grp_fu_484_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_7_i_cast_reg_658(0) <= tmp_7_i_cast_fu_452_p1(0);
tmp_7_i_cast_reg_658(1) <= tmp_7_i_cast_fu_452_p1(1);
tmp_7_i_cast_reg_658(2) <= tmp_7_i_cast_fu_452_p1(2);
tmp_7_i_cast_reg_658(3) <= tmp_7_i_cast_fu_452_p1(3);
tmp_7_i_cast_reg_658(4) <= tmp_7_i_cast_fu_452_p1(4);
tmp_7_i_cast_reg_658(5) <= tmp_7_i_cast_fu_452_p1(5);
tmp_7_i_cast_reg_658(6) <= tmp_7_i_cast_fu_452_p1(6);
tmp_7_i_cast_reg_658(7) <= tmp_7_i_cast_fu_452_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st59_fsm_58 = ap_CS_fsm)) then
tmp_8_i_reg_713 <= grp_fu_490_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then
tmp_buckets_0_reg_741 <= grp_nfa_get_finals_fu_366_ap_return_0;
tmp_buckets_1_reg_746 <= grp_nfa_get_finals_fu_366_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
tmp_s_reg_605 <= tmp_s_fu_405_p2;
end if;
end if;
end process;
tmp_14_cast_reg_600(63 downto 32) <= "00000000000000000000000000000000";
tmp_7_i_cast_reg_658(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_605 , tmp_19_i_reg_620 , tmp_19_1_i_reg_634 , j_end_phi_fu_316_p4 , any_phi_fu_328_p4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
if ((tmp_s_reg_605 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st68_fsm_67;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
if (not((tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st41_fsm_40;
end if;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st46_fsm_45;
end if;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st66_fsm_65;
else
ap_NS_fsm <= ap_ST_st65_fsm_64;
end if;
when ap_ST_st66_fsm_65 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st67_fsm_66;
else
ap_NS_fsm <= ap_ST_st66_fsm_65;
end if;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_194),2));
any_phi_fu_328_p4 <= any_reg_323;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st78_fsm_77 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_336, ap_return_preg)
begin
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_return <= p_0_reg_336;
else
ap_return <= ap_return_preg;
end if;
end process;
current_buckets_0_1_fu_566_p2 <= (next_buckets_0_reg_172 and tmp_buckets_0_reg_741);
current_buckets_1_1_fu_571_p2 <= (next_buckets_1_reg_162 and tmp_buckets_1_reg_746);
-- grp_bitset_next_fu_348_ap_ce assign process. --
grp_bitset_next_fu_348_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_316_p4)
begin
if ((((ap_ST_st45_fsm_44 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_316_p4)) or (ap_ST_st46_fsm_45 = ap_CS_fsm) or (ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm) or (ap_ST_st48_fsm_47 = ap_CS_fsm) or (ap_ST_st49_fsm_48 = ap_CS_fsm) or (ap_ST_st50_fsm_49 = ap_CS_fsm) or (ap_ST_st51_fsm_50 = ap_CS_fsm) or (ap_ST_st52_fsm_51 = ap_CS_fsm) or (ap_ST_st53_fsm_52 = ap_CS_fsm) or (ap_ST_st54_fsm_53 = ap_CS_fsm))) then
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_1;
else
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_bitset_next_fu_348_p_read <= next_buckets_1_reg_162;
grp_bitset_next_fu_348_r_bit <= j_bit1_reg_303;
grp_bitset_next_fu_348_r_bucket <= j_bucket1_reg_282;
grp_bitset_next_fu_348_r_bucket_index <= j_bucket_index1_reg_293;
grp_fu_400_ce <= ap_const_logic_1;
grp_fu_400_p0 <= p_01_rec_reg_150;
grp_fu_400_p1 <= tmp_14_cast_reg_600;
grp_fu_410_ce <= ap_const_logic_1;
grp_fu_410_p0 <= i_reg_138;
grp_fu_410_p1 <= ap_const_lv16_1;
-- grp_fu_422_ce assign process. --
grp_fu_422_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_605)
begin
if (((ap_ST_st38_fsm_37 = ap_CS_fsm) or ((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or ((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((tmp_s_reg_605 = ap_const_lv1_0))) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm))) then
grp_fu_422_ce <= ap_const_logic_1;
else
grp_fu_422_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_422_p0 <= p_01_rec_reg_150;
grp_fu_422_p1 <= ap_const_lv64_1;
grp_fu_471_ce <= ap_const_logic_1;
grp_fu_471_p0 <= (tmp_31_fu_455_p1 & ap_const_lv5_0);
grp_fu_471_p1 <= j_bit1_reg_303(6 - 1 downto 0);
grp_fu_484_ce <= ap_const_logic_1;
grp_fu_484_p0 <= grp_fu_484_p00(8 - 1 downto 0);
grp_fu_484_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_484_p1 <= grp_fu_484_p10(6 - 1 downto 0);
grp_fu_484_p10 <= std_logic_vector(resize(unsigned(state_reg_673),14));
grp_fu_490_ce <= ap_const_logic_1;
grp_fu_490_p0 <= tmp_6_i_reg_688;
grp_fu_490_p1 <= tmp_7_i_cast_reg_658;
grp_nfa_get_finals_fu_366_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_366_ap_start <= grp_nfa_get_finals_fu_366_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_360_ap_ce <= ap_const_logic_1;
-- grp_nfa_get_initials_fu_360_ap_start assign process. --
grp_nfa_get_initials_fu_360_ap_start_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_1;
else
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_0;
end if;
end process;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
-- grp_p_bsf32_hw_fu_372_ap_ce assign process. --
grp_p_bsf32_hw_fu_372_ap_ce_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_p_bsf32_hw_fu_372_bus_r <= bus_assign_reg_182;
j_bit1_ph_cast_fu_448_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_231),8));
j_bucket_index1_ph_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_220),8));
j_end_phi_fu_316_p4 <= j_end_reg_313;
next_buckets_0_1_fu_546_p2 <= (tmp_buckets_0_3_reg_269 or reg_378);
next_buckets_1_1_fu_552_p2 <= (tmp_buckets_1_3_reg_256 or reg_378);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_4_i_cast_fu_517_p1, tmp_9_i_cast_fu_535_p1)
begin
if ((ap_ST_st61_fsm_60 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_9_i_cast_fu_535_p1(32 - 1 downto 0);
elsif ((ap_ST_st60_fsm_59 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_4_i_cast_fu_517_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st60_fsm_59 = ap_CS_fsm) or (ap_ST_st61_fsm_60 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st65_fsm_64 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_size;
sample_address <= sample_addr_1_reg_614;
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
tmp_14_cast_fu_390_p1 <= std_logic_vector(resize(unsigned(tmp_14),64));
tmp_19_1_i_fu_434_p2 <= "1" when (next_buckets_1_reg_162 = ap_const_lv32_0) else "0";
tmp_19_i_fu_428_p2 <= "1" when (next_buckets_0_reg_172 = ap_const_lv32_0) else "0";
tmp_1_fu_576_p2 <= (current_buckets_1_1_reg_756 or current_buckets_0_1_reg_751);
tmp_2_fu_580_p2 <= "0" when (tmp_1_reg_761 = ap_const_lv32_0) else "1";
tmp_31_fu_455_p1 <= j_bucket_index1_reg_293(1 - 1 downto 0);
tmp_4_i_cast_fu_517_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_510_p3),64));
tmp_4_i_fu_510_p3 <= (tmp_8_i_reg_713 & ap_const_lv1_0);
tmp_7_i_cast_fu_452_p1 <= std_logic_vector(resize(unsigned(sym_reg_629),14));
tmp_9_i_cast_fu_535_p1 <= std_logic_vector(resize(unsigned(tmp_9_i_fu_528_p3),64));
tmp_9_i_fu_528_p3 <= (tmp_8_i_reg_713 & ap_const_lv1_1);
tmp_s_fu_405_p2 <= "1" when (unsigned(i_reg_138) < unsigned(length_r)) else "0";
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4.vhd | 4 | 2896 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff1;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/syn/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 82370 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg676-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.350000,HLS_SYN_LAT=92262011,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_314 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_319 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_324 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_328 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_339 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC;
signal grp_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_343 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
empty : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_176 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_176_ap_start,
ap_done => grp_nfa_accept_sample_fu_176_ap_done,
ap_idle => grp_nfa_accept_sample_fu_176_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_176_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_176_sample_address,
sample_datain => grp_nfa_accept_sample_fu_176_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_176_sample_size,
empty => grp_nfa_accept_sample_fu_176_empty,
length_r => grp_nfa_accept_sample_fu_176_length_r,
ap_return => grp_nfa_accept_sample_fu_176_ap_return);
grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_192_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_192_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_192_i_index,
i_sample => grp_sample_iterator_get_offset_fu_192_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_192_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_192_ap_return);
grp_sample_iterator_next_fu_209 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_209_ap_start,
ap_done => grp_sample_iterator_next_fu_209_ap_done,
ap_idle => grp_sample_iterator_next_fu_209_ap_idle,
ap_ready => grp_sample_iterator_next_fu_209_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_209_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size,
i_index => grp_sample_iterator_next_fu_209_i_index,
i_sample => grp_sample_iterator_next_fu_209_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_250_p0,
din1 => grp_fu_250_p1,
ce => grp_fu_250_ce,
dout => grp_fu_250_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st26_fsm_25 = ap_NS_fsm) and ((ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_92 assign process. --
c_fu_92_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st26_fsm_25 = ap_CS_fsm) and (or_cond_reg_339 = ap_const_lv1_0))) then
c_fu_92 <= c_1_reg_343;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_92 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_144 assign process. --
i_index_reg_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_144 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_154 assign process. --
i_sample_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_154 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_164 assign process. --
p_0_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
p_0_reg_164 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_324 = ap_const_lv1_0)))) then
p_0_reg_164 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st25_fsm_24 = ap_CS_fsm)) then
c_1_reg_343 <= grp_fu_250_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_328 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
offset_reg_334 <= grp_sample_iterator_get_offset_fu_192_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then
or_cond_reg_339 <= or_cond_fu_245_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_319 <= tmp_i_10_fu_233_p2;
tmp_i_reg_314 <= tmp_i_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_324 <= tmp_i_11_fu_238_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_324 , or_cond_fu_245_p2 , grp_nfa_accept_sample_fu_176_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_324 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
if ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and (stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((or_cond_fu_245_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st26_fsm_25;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_164;
-- grp_fu_250_ce assign process. --
grp_fu_250_ce_assign_proc : process(ap_CS_fsm, stop_on_first_read_read_fu_102_p2, or_cond_fu_245_p2, grp_nfa_accept_sample_fu_176_ap_done)
begin
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) or ((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and (stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0)) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm))) then
grp_fu_250_ce <= ap_const_logic_1;
else
grp_fu_250_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_250_p0 <= c_load_reg_328;
grp_fu_250_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_176_empty <= offset_reg_334;
grp_nfa_accept_sample_fu_176_length_r <= sample_length;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144;
grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154;
grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length;
grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144;
grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154;
grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size)
begin
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size;
or_cond_fu_245_p2 <= (grp_nfa_accept_sample_fu_176_ap_return xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size;
stop_on_first_read_read_fu_102_p2 <= stop_on_first;
tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0";
tmp_i_11_fu_238_p2 <= (tmp_i_reg_314 and tmp_i_10_reg_319);
tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0";
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/impl/vhdl/sample_iterator_next.vhd | 2 | 31609 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it10 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_reg_156 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_2_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_161 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_167 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_reg_156_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it9;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
ap_reg_ppstg_i_index_read_reg_134_pp0_it8 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7;
ap_reg_ppstg_i_index_read_reg_134_pp0_it9 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it8;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it7;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_146 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_1_reg_156 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_2_reg_161 <= tmp_2_fu_99_p2;
tmp_3_reg_172 <= grp_fu_88_p2;
tmp_4_reg_167 <= grp_fu_83_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 when (tmp_2_reg_161(0) = '1') else
tmp_4_reg_167;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_3_reg_172 when (tmp_2_reg_161(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it11, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0);
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_1_reg_156_temp <= signed(tmp_1_reg_156);
tmp_2_fu_99_p1 <= std_logic_vector(resize(tmp_1_reg_156_temp,18));
tmp_2_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_2_fu_99_p1)) else "0";
tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64));
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it9),18));
end behav;
| lgpl-3.0 |
blytkerchan/BrainF | BrainF_top.vhdl | 1 | 2159 | -- BrainF* interpreter
-- Version: 20141018
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BrainF_top is
port(
resetN : in std_logic
; clock : in std_logic
; spi_miso : out std_logic
; spi_mosi : in std_logic
; spi_clock : in std_logic
; spi_slave_selectN : in std_logic
);
end entity;
architecture behavior of BrainF_top is
component BrainF is
generic(
MAX_INSTRUCTION_COUNT : positive
; MEMORY_SIZE : positive
);
port(
resetN : in std_logic
; clock : in std_logic
; load_instructions : in std_logic
; instruction_octet : in std_logic_vector(7 downto 0)
; ack_instruction : out std_logic
; program_full : out std_logic
; read_memory : in std_logic
; memory_byte : out std_logic_vector(7 downto 0)
; memory_byte_ready : out std_logic
; memory_byte_read_ack : in std_logic
; done : out std_logic
);
end component;
signal load_instructions : std_logic := '0';
signal instruction_octet : std_logic_vector(7 downto 0) := (others => '0');
begin
interpreter : BrainF
generic map(
MAX_INSTRUCTION_COUNT => 65535
, MEMORY_SIZE => 65535
)
port map(
resetN => resetN
, clock => clock
, load_instructions => load_instructions
, instruction_octet => instruction_octet
, ack_instruction => open
, program_full => open
, read_memory => '0'
, memory_byte => open
, memory_byte_ready => open
, memory_byte_read_ack => '0'
, done => open
);
end behavior;
| lgpl-3.0 |
blytkerchan/BrainF | BrainF.vhdl | 1 | 13962 | -- BrainF* interpreter
-- Version: 20141018
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BrainF is
generic(
MAX_INSTRUCTION_COUNT : positive := 65536
; MEMORY_SIZE : positive := 65536
);
port(
resetN : in std_logic
; clock : in std_logic
; load_instructions : in std_logic
; instruction_octet : in std_logic_vector(7 downto 0)
; ack_instruction : out std_logic := '0'
; program_full : out std_logic := '0'
; read_memory : in std_logic
; memory_byte : out std_logic_vector(7 downto 0) := (others => '0')
; memory_byte_ready : out std_logic := '0'
; memory_byte_read_ack : in std_logic
; done : out std_logic := '0'
);
end entity;
architecture behavior of BrainF is
type Instruction is (nop, halt, dot, plus, minus, advance, back_up, begin_loop, end_loop, zero);
type Instructions is array(0 to (MAX_INSTRUCTION_COUNT - 1)) of Instruction;
type Pipeline is array(0 to 1) of Instruction;
subtype IPointer is integer range 0 to MAX_INSTRUCTION_COUNT;
type InterpreterState is (execute_instruction, fetch_instruction);
subtype NestCount is integer range 0 to MAX_INSTRUCTION_COUNT - 1;
type Memory is array(0 to (MEMORY_SIZE - 1)) of std_logic_vector(7 downto 0);
subtype Pointer is integer range 0 to (MEMORY_SIZE - 1);
function toInstruction(i : std_logic_vector(7 downto 0)) return Instruction is
begin
case i is
when x"23" => return halt;
when x"2B" => return plus;
when x"2D" => return minus;
when x"2E" => return dot;
when x"30" => return zero;
when x"3E" => return advance;
when x"3C" => return back_up;
when x"5B" => return begin_loop;
when x"5D" => return end_loop;
when others => return nop;
end case;
end toInstruction;
function increment(b : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
if b = x"FF" then
return x"00";
else
return std_logic_vector(unsigned(b) + 1);
end if;
end increment;
function decrement(b : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
if b = x"00" then
return x"FF";
else
return std_logic_vector(unsigned(b) - 1);
end if;
end decrement;
-- produced by p_interpret
signal ptr : Pointer := 0;
signal mem : Memory := (others => (others => '0'));
signal stalled : std_logic := '0'; -- signals it's going forward in a loop. The p_fetch process will continue
-- fetching until it finds the corresponding end-of-loop and puts that in pipe(0) at that time.
-- produced by p_fetch
signal pipe : Pipeline := (others => nop);
signal iptr : IPointer := 0;
signal nest_count : NestCount := 0;
signal expect_stall : std_logic := '0';
signal should_back_up_on_stall : std_logic := '0'; -- set if we expect a stall on an end_loop instruction
-- produced by p_loadInstructions
signal program : Instructions := (others => halt);
signal prev_load_instructions : std_logic := '0';
signal instruction_step : std_logic := '0';
signal iwptr : IPointer := 0;
signal internal_program_full : std_logic := '0';
-- produced by p_readMemory
signal prev_memory_byte_read_ack : std_logic := '0';
signal prev_read_memory : std_logic := '0';
begin
p_interpret : process(resetN, clock, load_instructions, read_memory)
begin
if resetN = '0' or load_instructions = '1' then
ptr <= 0;
mem <= (others => (others => '0'));
stalled <= '0';
elsif load_instructions = '0' and read_memory = '0' then
if rising_edge(clock) then
case pipe(0) is
when dot =>
null;
when plus =>
mem(ptr) <= increment(mem(ptr));
when minus =>
mem(ptr) <= decrement(mem(ptr));
when zero =>
mem(ptr) <= x"00";
when advance =>
if ptr = MEMORY_SIZE - 1 then
ptr <= 0;
else
ptr <= ptr + 1;
end if;
when back_up =>
if ptr = 0 then
ptr <= MEMORY_SIZE - 1;
else
ptr <= ptr - 1;
end if;
when begin_loop =>
if mem(ptr) = x"00" then
stalled <= '1';
else
stalled <= '0';
end if;
when end_loop =>
if mem(ptr) /= x"00" then
stalled <= '1';
else
stalled <= '0';
end if;
when halt =>
stalled <= '1';
when nop =>
null;
end case;
end if;
end if;
end process;
p_fetch : process(resetN, clock, load_instructions, read_memory)
variable done_skipping : boolean := False;
begin
if resetN = '0' or load_instructions = '1' then
pipe <= (others => nop);
iptr <= 0;
nest_count <= 0;
done <= '0';
expect_stall <= '0';
should_back_up_on_stall <= '0';
done_skipping := False;
elsif load_instructions ='0' and read_memory = '0' then
if rising_edge(clock) then
-- if pipe(1) contains a begin_loop instruction, the p_interpret process may start stalling as soon as
-- it sees it, which we will only know one (extra) clock cycle afterwards. In that case, we don't want
-- to give it the next instruction unless we know it has had time to take a decision. Hence, if there's
-- a begin_loop instruction in pipe(1) we set the expect_stall flag. If there's a begin_loop in pipe(0)
-- and the expect_stall flag is set, we clear the flag and do nothing else. If the flag is not set, we
-- check whether the stalled signal is raised and, if so, start searching for the end of the loop. If
-- it's not set, we continue as normal.
-- if pipe(1) contains an end_loop instruction, p_interpret may also stall but if it does, we need to
-- start backing up. When pipe(1) contains an instruction, the instruction pointer (iptr) already
-- points one past the instruction, because we're getting ready to read the next instruction into
-- pipe(1). Hence, while we can anticipate our not stalling (and therefore load the next instruction
-- into pipe(1) regardless) we have to make sure that if we do stall, we start by backing up the
-- instruction pointer twice (or not count the end_loop instruction as nesting).
if (pipe(1) = begin_loop or pipe(1) = end_loop or pipe(1) = halt) and stalled /= '1' and expect_stall = '0' then
expect_stall <= '1';
done_skipping := False;
if pipe(1) = end_loop then
should_back_up_on_stall <= '1';
else
should_back_up_on_stall <= '0';
end if;
end if;
if (pipe(0) = begin_loop or pipe(0) = end_loop) and expect_stall = '1' then
expect_stall <= '0';
else
if stalled = '0' then
pipe(0) <= pipe(1);
elsif stalled = '1' and nest_count = 0 and pipe(0) = begin_loop and pipe(1) = end_loop then
-- we're done skipping over the loop!
pipe(0) <= pipe(1);
elsif stalled = '1' and nest_count = 0 and pipe(0) = end_loop and pipe(1) = begin_loop and should_back_up_on_stall = '0' then
-- we are done backing up!
pipe(0) <= pipe(1);
iptr <= iptr + 2;
done_skipping := True;
elsif stalled = '1' and pipe(0) = halt then
done <= '1';
elsif stalled = '1' and pipe(0) = pipe(1) and not done_skipping then
nest_count <= nest_count + 1;
elsif stalled = '1' and nest_count /= 0 and ((pipe(0) = begin_loop and pipe(1) = end_loop) or (pipe(0) = end_loop and pipe(1) = begin_loop)) then
nest_count <= nest_count - 1;
end if;
if stalled = '0' or (stalled = '1' and pipe(0) = begin_loop) then
if iptr = MAX_INSTRUCTION_COUNT then
pipe(1) <= dot;
done <= '1';
else
if iptr + 2 < MAX_INSTRUCTION_COUNT and program(iptr) = begin_loop and program(iptr + 1) = minus and program(iptr + 2) = end_loop then
pipe(1) <= zero;
done <= '0';
iptr <= iptr + 3;
else
pipe(1) <= program(iptr);
done <= '0';
iptr <= iptr + 1;
end if;
end if;
elsif stalled = '1' and pipe(0) = halt then
null;
elsif not done_skipping then
assert stalled = '1' and pipe(0) = end_loop report "Unexpected stall!" severity failure;
if should_back_up_on_stall = '1' then
assert iptr >= 3 report "Stalled with an invalid instruction pointer!" severity failure;
pipe(1) <= program(iptr - 3);
iptr <= iptr - 3;
should_back_up_on_stall <= '0';
else
-- this is where we start backing up
pipe(1) <= program(iptr);
done <= '0';
if iptr /= 0 then
iptr <= iptr - 1;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_loadInstructions : process(clock, resetN)
begin
if resetN = '0' then
program <= (others => halt);
prev_load_instructions <= '0';
instruction_step <= '0';
iwptr <= 0;
internal_program_full <= '0';
else
if rising_edge(clock) then
if prev_load_instructions = '0' and load_instructions ='1' then
program <= (others => halt);
iwptr <= 0;
instruction_step <= '0';
internal_program_full <= '0';
elsif prev_load_instructions = '1' and load_instructions ='1' then
if instruction_step = '0' then
if iwptr < MAX_INSTRUCTION_COUNT then
program(iwptr) <= toInstruction(instruction_octet);
iwptr <= iwptr + 1;
else
internal_program_full <= '1';
end if;
end if;
instruction_step <= not instruction_step and not internal_program_full;
else
iwptr <= 0;
instruction_step <= '0';
end if;
prev_load_instructions <= load_instructions;
end if;
end if;
end process;
ack_instruction <= instruction_step;
program_full <= internal_program_full;
p_readMemory : process(clock, resetN, read_memory)
variable rptr : integer range 0 to MEMORY_SIZE := 0;
begin
if resetN = '0' or read_memory = '0' then
rptr := 0;
memory_byte <= (others => '0');
memory_byte_ready <= '0';
else
if rising_edge(clock) then
if read_memory = '1' then
if prev_read_memory = '0' then
memory_byte <= mem(0);
memory_byte_ready <= '1';
rptr := 1;
else
if prev_memory_byte_read_ack = '0' and memory_byte_read_ack = '1' then
if rptr /= MEMORY_SIZE then
memory_byte <= mem(rptr);
rptr := rptr + 1;
else
memory_byte_ready <= '0';
end if;
end if;
end if;
prev_memory_byte_read_ack <= memory_byte_read_ack;
end if;
prev_read_memory <= read_memory;
end if;
end if;
end process;
end behavior;
| lgpl-3.0 |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/forwardRateh1.vhdl | 1 | 10652 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity forwardRateh1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end forwardRateh1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of forwardRateh1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * exp_r_exponential_result1 ),18,-2);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/component_signature.vhdl | 1 | 229 | pointCellCondBased-channelPopulation-ionChannelPassive-channelPopulation-ionChannelHH-gateHHrates-HHExpLinearRate-HHExpRate-gateHHrates-HHExpRate-HHSigmoidRate-channelPopulation-ionChannelHH-gateHHrates-HHExpLinearRate-HHExpRate- | lgpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/ARM_FIFO_in/synth/ARM_FIFO_in.vhd | 1 | 39141 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_2;
USE fifo_generator_v13_1_2.fifo_generator_v13_1_2;
ENTITY ARM_FIFO_in IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END ARM_FIFO_in;
ARCHITECTURE ARM_FIFO_in_arch OF ARM_FIFO_in IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ARM_FIFO_in_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_2 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ARM_FIFO_in_arch: ARCHITECTURE IS "fifo_generator_v13_1_2,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ARM_FIFO_in_arch : ARCHITECTURE IS "ARM_FIFO_in,fifo_generator_v13_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ARM_FIFO_in_arch: ARCHITECTURE IS "ARM_FIFO_in,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=16,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS" &
"_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_" &
"THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=8,C_INTER" &
"FACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WI" &
"DTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TY" &
"PE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_" &
"ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=1" &
"0,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1" &
"023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASS" &
"ERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_2
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 16,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 8,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END ARM_FIFO_in_arch;
| lgpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Unsigned_Mult/synth/Unsigned_Mult.vhd | 1 | 5610 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY Unsigned_Mult IS
PORT (
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END Unsigned_Mult;
ARCHITECTURE Unsigned_Mult_arch OF Unsigned_Mult IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Unsigned_Mult_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Unsigned_Mult_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Unsigned_Mult_arch : ARCHITECTURE IS "Unsigned_Mult,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Unsigned_Mult_arch: ARCHITECTURE IS "Unsigned_Mult,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintex7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=32,C_A_TYPE=0,C_B_WIDTH=32,C_B_TYPE=0,C_OUT_HIGH=63,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintex7",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 0,
C_A_WIDTH => 32,
C_A_TYPE => 0,
C_B_WIDTH => 32,
C_B_TYPE => 0,
C_OUT_HIGH => 63,
C_OUT_LOW => 0,
C_MULT_TYPE => 1,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => '1',
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END Unsigned_Mult_arch;
| lgpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Signed_Mult/synth/Signed_Mult.vhd | 1 | 5588 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY Signed_Mult IS
PORT (
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END Signed_Mult;
ARCHITECTURE Signed_Mult_arch OF Signed_Mult IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Signed_Mult_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Signed_Mult_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Signed_Mult_arch : ARCHITECTURE IS "Signed_Mult,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Signed_Mult_arch: ARCHITECTURE IS "Signed_Mult,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintex7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=32,C_A_TYPE=0,C_B_WIDTH=32,C_B_TYPE=0,C_OUT_HIGH=63,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintex7",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 0,
C_A_WIDTH => 32,
C_A_TYPE => 0,
C_B_WIDTH => 32,
C_B_TYPE => 0,
C_OUT_HIGH => 63,
C_OUT_LOW => 0,
C_MULT_TYPE => 1,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => '1',
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END Signed_Mult_arch;
| lgpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd | 3 | 163693 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
| lgpl-3.0 |
id101010/vhdl-yasg | dds_tb.vhd | 1 | 2231 | ----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:35:57 05/16/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dds_tb IS
END dds_tb;
ARCHITECTURE behavior OF dds_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dds
PORT(
clk : IN std_logic;
freq : IN unsigned(16 downto 0);
form : IN unsigned(1 downto 0);
amp : OUT unsigned(11 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal freq : unsigned(16 downto 0) := (others => '0');
signal form : unsigned(1 downto 0) := (others => '0');
--Outputs
signal amp : unsigned(11 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dds PORT MAP (
clk => clk,
freq => freq,
form => form,
amp => amp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
form <= "00";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "01";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "10";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "11";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
wait;
end process;
END;
| lgpl-3.0 |
freecores/grain | src/VHDL/test_synth/hw4_grain128.vhd | 1 | 775 | --
-- synthesis test 4:
-- * without clock enable
-- * fast
--
-- Altera EP2C-8, Quartus 8.0: (same as hw3_grain128)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw4_grain128 is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw4_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 |
Hyperion302/omega-cpu | Hardware/Open16750/uart_baudgen.vhdl | 1 | 2237 | --
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
| lgpl-3.0 |
Hyperion302/omega-cpu | Hardware/Omega/MemoryController_TB.vhd | 1 | 3945 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:38 11/03/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/MemoryController_TB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MemoryController
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MemoryController_TB IS
END MemoryController_TB;
ARCHITECTURE behavior OF MemoryController_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MemoryController
PORT(
CLK : IN std_logic;
Address : IN std_logic_vector(31 downto 0);
Enable : IN std_logic;
ToWrite : IN std_logic_vector(31 downto 0);
FromRead : OUT std_logic_vector(31 downto 0);
Instruction : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Done : OUT std_logic;
SRAM_addr : OUT std_logic_vector(20 downto 0);
SRAM_OE : OUT std_logic;
SRAM_CE : OUT std_logic;
SRAM_WE : OUT std_logic;
SRAM_data : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal Enable : std_logic := '0';
signal ToWrite : std_logic_vector(31 downto 0) := (others => '0');
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
--BiDirs
signal SRAM_data : std_logic_vector(7 downto 0);
--Outputs
signal FromRead : std_logic_vector(31 downto 0);
signal Done : std_logic;
signal SRAM_addr : std_logic_vector(20 downto 0);
signal SRAM_OE : std_logic;
signal SRAM_CE : std_logic;
signal SRAM_WE : std_logic;
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MemoryController PORT MAP (
CLK => CLK,
Address => Address,
Enable => Enable,
ToWrite => ToWrite,
FromRead => FromRead,
Instruction => Instruction,
Reset => Reset,
Done => Done,
SRAM_addr => SRAM_addr,
SRAM_OE => SRAM_OE,
SRAM_CE => SRAM_CE,
SRAM_WE => SRAM_WE,
SRAM_data => SRAM_data
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
data_proc: process
begin
sram_data <= (others => 'Z');
wait until falling_edge(SRAM_oe);
sram_data <= "00000000";
wait for 9 ns;
sram_data <= "01011010";
wait until SRAM_oe = '1';
end process data_proc;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait until SRAM_we = '1';
wait for CLK_period*10;
enable <= '1';
instruction <= "00010000000000000000000000000000";
address <= "00000000000000000000000000000100";
wait until done = '1';
enable <= '0';
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 |
Hyperion302/omega-cpu | UnitTests/Divider/divider_sequential.vhdl | 1 | 3524 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Divider_sequential is
port (
Enable : in std_logic;
Ready : out std_logic;
CLK : in std_logic;
Overflow : out std_logic;
Divisor : in std_logic_vector(31 downto 0);
Dividend : in std_logic_vector(31 downto 0);
Remainder : out std_logic_vector(31 downto 0);
Quotient : out std_logic_vector(31 downto 0);
IsSigned : in std_logic);
type machineState is (WaitingToStart,Dividing,Output);
end Divider_sequential;
architecture Behavioral of Divider_sequential is
signal Enable_S : std_logic := '0';
signal Ready_S : std_logic := '0';
signal Overflow_S : std_logic := '0';
signal Divisor_S : std_logic_vector(31 downto 0) := (others => '0');
signal Quotient_S : std_logic_vector(31 downto 0) := (others => '0');
signal Remainder_S : std_logic_vector(63 downto 0) := (others => '0');
signal Dividend_S : std_logic_vector(31 downto 0) := (others => '0');
signal is_running : integer := 0;
signal state : machineState := WaitingToStart;
begin
Enable_S <= Enable;
Ready <= Ready_S;
Overflow <= Overflow_S;
Divisor_S <= Divisor when (isSigned = '0' or Divisor(31) = '0') else std_logic_vector(-signed(Divisor));
Quotient <= Quotient_S when (isSigned = '0' or Divisor(31) = Dividend(31)) else std_logic_vector(-signed(Quotient_S));
Remainder <= Remainder_S(63 downto 32) when (isSigned = '0' or Dividend(31) = '0') else std_logic_vector(-signed(Remainder_S(63 downto 32)));
Dividend_S <= Dividend when (isSigned = '0' or Dividend(31) = '0') else std_logic_vector(-signed(Dividend));
Divide: process (CLK)
variable Remainder_V : std_logic_vector(63 downto 0) := (others => '0');
begin
if rising_edge(clk) then
case state is
when WaitingToStart =>
if enable_s = '1' then
if Divisor_S = "00000000000000000000000000000000" then
state <= Output;
Ready_S <= '1';
Overflow_S <= '1';
else
state <= Dividing;
is_running <= 1;
Ready_S <= '0';
Quotient_S <= (others => '0');
Overflow_S <= '0';
Remainder_S(63 downto 32) <= (others => '0');
Remainder_S(31 downto 0) <= Dividend_S;
end if;
end if;
when Dividing =>
if is_running <= 32 then
is_running <= is_running + 1;
Remainder_V := Remainder_S(62 downto 0) & "0";
Remainder_V(63 downto 32) := std_logic_vector(to_signed(to_integer(signed(Remainder_V(63 downto 32))) - to_integer(signed(Divisor_S)),32));
if Remainder_V(63) = '1' then
Remainder_S <= Remainder_S(62 downto 0) & "0";--Remainder_V(63 downto 32) := std_logic_vector(to_unsigned(to_integer(unsigned(Remainder_S(63 downto 32))) + to_integer(unsigned(Divisor_S)),32));
Quotient_S <= Quotient_S(30 downto 0) & "0";
else
Remainder_S <= Remainder_V;
Quotient_S <= Quotient_S(30 downto 0) & "1";
end if;
elsif is_running = 33 then
state <= Output;
end if;
when Output =>
if enable_s = '1' then
Ready_S <= '1';
else
Ready_S <= '0';
Overflow_S <= '0';
State <= WaitingToStart;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/wb_position_calc/position_calc_counters_single.vhd | 1 | 3044 | ------------------------------------------------------------------------------
-- Title : Position Calcualtion Error Counters
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2014-01-13
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple counters for errors on the DSP chain
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-13 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity position_calc_counters_single is
generic (
g_cntr_size : natural := 16
);
port (
fs_clk2x_i : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i : in std_logic;
-- Clock enable
ce_i : in std_logic;
-- Error inputs (one clock cycle long)
err1_i : in std_logic;
-- Counter clear
cntr_clr_i : in std_logic;
-- Output counter
cntr_o : out std_logic_vector(g_cntr_size-1 downto 0)
);
end position_calc_counters_single;
architecture rtl of position_calc_counters_single is
signal cntr_clr_int : std_logic;
signal cntr_int : unsigned(g_cntr_size-1 downto 0);
begin
-- Hold counter clear until it is visible by the remaing of logic with
-- clock enable
p_hold_clr : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
cntr_clr_int <= '0';
else
if cntr_clr_i = '1' then
cntr_clr_int <= '1';
elsif ce_i = '1' then
cntr_clr_int <= '0';
end if;
end if;
end if;
end process;
p_ctnr : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
cntr_int <= to_unsigned(0, cntr_int'length);
elsif ce_i = '1' then
if cntr_clr_int = '1' then
cntr_int <= to_unsigned(0, cntr_int'length);
elsif err1_i = '1' then
cntr_int <= cntr_int + 1;
end if;
end if;
end if;
end process;
-- Output counters
cntr_o <= std_logic_vector(cntr_int);
end rtl;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_2717b25e8a23e5e2.vhd | 1 | 6147 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_2717b25e8a23e5e2.vhd when simulating
-- the core, cc_cmplr_v3_0_2717b25e8a23e5e2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_2717b25e8a23e5e2 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_2717b25e8a23e5e2;
ARCHITECTURE cc_cmplr_v3_0_2717b25e8a23e5e2_a OF cc_cmplr_v3_0_2717b25e8a23e5e2 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 58,
c_c2 => 58,
c_c3 => 58,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2,
c_component_name => "cc_cmplr_v3_0_2717b25e8a23e5e2",
c_diff_delay => 2,
c_family => "virtex6",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 58,
c_i2 => 58,
c_i3 => 58,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 1120,
c_min_rate => 1120,
c_num_channels => 2,
c_num_stages => 3,
c_output_width => 58,
c_rate => 1120,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_2717b25e8a23e5e2_a;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/sw_windowing/input_conditioner.vhd | 1 | 6574 | -------------------------------------------------------------------------------
-- Title : Input Conditioner
-- Project :
-------------------------------------------------------------------------------
-- File : input_conditioner.vhd
-- Author : Gustavo BM Bruno
-- Company :
-- Created : 2014-01-30
-- Last update: 2014-02-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Define the timing for the switch at the RFFE board and apply a
-- proper window at the switch to avoid the switching noise.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-30 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
entity input_conditioner is
generic (
--g_clk_freq : real := 120.0e6; -- System clock frequency
--g_sw_freq : real := 100.0e3; -- Desired switching frequency
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
reset_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic; -- Switch position output
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end entity input_conditioner;
architecture structural of input_conditioner is
--constant c_mem_size : natural := natural(g_clk_freq/(g_sw_freq*2.0)) + 1;
constant c_mem_size : natural := g_sw_interval/2 + 1;
constant c_bus_size : natural := f_log2_size(c_mem_size);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0) := (others => '0'); -- Current index for lookup table
signal window_factor : std_logic_vector(g_window_width-1 downto 0); -- Current value of the window
-- factor, signed int
component counter is
generic (
g_mem_size : natural;
g_bus_size : natural;
g_switch_delay : natural);
port (
clk_i : in std_logic;
index_o : out std_logic_vector(c_bus_size-1 downto 0);
ce_i : in std_logic;
switch_o : out std_logic;
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
reset_n_i : in std_logic);
end component counter;
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
clk_i : in std_logic;
reset_n_i : in std_logic);
end component generic_multiplier;
begin
cmp_lut : generic_simple_dpram
generic map (
g_data_width => g_window_width,
g_size => c_mem_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
--g_init_file => "./window.nif",
g_init_file => g_window_coef_file,
g_dual_clock => false
)
port map (
rst_n_i => reset_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => window_factor
);
cmp_index : counter
generic map (
g_mem_size => c_mem_size,
g_bus_size => c_bus_size,
g_switch_delay => g_input_delay
)
port map (
clk_i => clk_i,
index_o => cur_address,
ce_i => '1',
reset_n_i => reset_n_i,
switch_delay_i => switch_delay_i,
switch_o => switch_o,
switch_en_i => switch_en_i
);
dbg_cur_address_o(dbg_cur_address_o'left downto cur_address'left+1)
<= (others =>'0');
dbg_cur_address_o(cur_address'left downto 0) <= cur_address;
cmp_multiplier_a : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_a_i,
b_i => window_factor,
p_o => a_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_b : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_b_i,
b_i => window_factor,
p_o => b_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_c : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_c_i,
b_i => window_factor,
p_o => c_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_d : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_d_i,
b_i => window_factor,
p_o => d_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
end structural;
| lgpl-3.0 |
QuickJack/logi-hard | test_bench/wishbone_double_buffer_tb.vhd | 2 | 3834 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:24:24 01/16/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/wishbone_double_buffer_tb.vhd
-- Project Name: logibone-wishbone
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: wishbone_double_buffer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY wishbone_double_buffer_tb IS
END wishbone_double_buffer_tb;
ARCHITECTURE behavior OF wishbone_double_buffer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wishbone_double_buffer
PORT(
gls_reset : IN std_logic;
gls_clk : IN std_logic;
wbs_address : IN std_logic_vector(15 downto 0);
wbs_writedata : IN std_logic_vector(15 downto 0);
wbs_readdata : OUT std_logic_vector(15 downto 0);
wbs_strobe : IN std_logic;
wbs_cycle : IN std_logic;
wbs_write : IN std_logic;
wbs_ack : OUT std_logic;
write_buffer : IN std_logic;
buffer_index : OUT std_logic;
buffer_full : OUT std_logic;
buffer_input : IN std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal gls_reset : std_logic := '0';
signal gls_clk : std_logic := '0';
signal wbs_address : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_strobe : std_logic := '0';
signal wbs_cycle : std_logic := '0';
signal wbs_write : std_logic := '0';
signal write_buffer : std_logic := '0';
signal buffer_input : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal wbs_readdata : std_logic_vector(15 downto 0);
signal wbs_ack : std_logic;
signal buffer_index : std_logic;
signal buffer_full : std_logic;
-- Clock period definitions
constant gls_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: wishbone_double_buffer PORT MAP (
gls_reset => gls_reset,
gls_clk => gls_clk,
wbs_address => wbs_address,
wbs_writedata => wbs_writedata,
wbs_readdata => wbs_readdata,
wbs_strobe => wbs_strobe,
wbs_cycle => wbs_cycle,
wbs_write => wbs_write,
wbs_ack => wbs_ack,
write_buffer => write_buffer,
buffer_index => buffer_index,
buffer_full => buffer_full,
buffer_input => buffer_input
);
-- Clock process definitions
gls_clk_process :process
begin
gls_clk <= '0';
wait for gls_clk_period/2;
gls_clk <= '1';
wait for gls_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
gls_reset <= '1' ;
wait for 100 ns;
gls_reset <= '0' ;
wait for gls_clk_period*10;
while true loop
write_buffer <= '1' ;
wait for gls_clk_period;
end loop ;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/communication/i2c_master.vhd | 2 | 8283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:10 07/01/2014
-- Design Name:
-- Module Name: i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end i2c_master;
architecture Behavioral of i2c_master is
constant clk_div : positive := ((clk_freq_hz/i2c_freq_hz)/4)-1 ;
TYPE master_state IS (IDLE, I2C_START, TX_ADDR, ACK_ADDR, TX_BYTE, RX_BYTE, ACK_BYTE, HOLDING, I2C_STOP) ;
signal cur_state, next_state : master_state ;
signal modulo_counter : std_logic_vector(15 downto 0);
signal end_modulo : std_logic ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal quarter, half, full : std_logic ;
signal transmit_buffer, receive_buffer, addr_buffer : std_logic_vector(7 downto 0);
signal bit_counter : std_logic_vector(2 downto 0);
signal write_mode : std_logic ;
signal sda_unbuf, sda_latched : std_logic ;
signal sda_shift_reg : std_logic_vector(5 downto 0);
signal is_acked : std_logic ;
begin
process(clk, reset)
begin
if reset = '1' then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif clk'event and clk = '1' then
if cur_state = IDLE then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif modulo_counter = 0 then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= cycle_counter + 1;
else
modulo_counter <= modulo_counter - 1 ;
end if ;
end if ;
end process ;
end_modulo <= '1' when modulo_counter = 0 else
'0' ;
quarter <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
half <= '1' when cycle_counter = 2 else
'0' ;
full <= '1' when cycle_counter = 3 and end_modulo = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, bit_counter, write_mode, cycle_counter, end_modulo, quarter, half, full, i2c_write, i2c_read, sda)
begin
next_state <= cur_state ;
case (cur_state) is
when IDLE =>
if i2c_write = '1' then
next_state <= I2C_START ;
elsif i2c_read = '1' then
next_state <= I2C_START ;
end if ;
when I2C_START =>
if full = '1' then
next_state <= TX_ADDR ;
end if ;
when TX_ADDR =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_ADDR ;
end if ;
when ACK_ADDR =>
if full = '1' and is_acked = '1' and write_mode = '1' then
next_state <= TX_BYTE ;
elsif full = '1' and is_acked = '1' and write_mode = '0' then
next_state <= RX_BYTE ;
elsif full = '1' and is_acked = '0' then
next_state <= I2C_STOP ;
end if ;
when TX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when RX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when ACK_BYTE =>
if full = '1' and i2c_write = '1' and is_acked = '1' then --
next_state <= TX_BYTE ;
elsif full = '1' and i2c_read = '1' then
next_state <= RX_BYTE ;
elsif full = '1' then
next_state <= I2C_STOP ;
end if ;
when I2C_STOP =>
if full = '1' then
next_state <= IDLE ;
end if ;
when others =>
end case ;
end process ;
scl <= 'Z' when cur_state = I2C_START and cycle_counter < 2 else
'0' when cur_state = I2C_START and cycle_counter >= 2 else
'Z' when cur_state = IDLE else
'0' when cycle_counter < 2 else
'Z' ;
sda_unbuf <= '0' when cur_state = I2C_START else
'0' when cur_state = I2C_STOP and cycle_counter <= 2 else
'1' when cur_state = I2C_STOP and cycle_counter > 2 else -- need to make sure its enough ...
'1' when cur_state = IDLE else
'1' when cur_state = TX_ADDR and addr_buffer(7) = '1' else
'0' when cur_state = TX_ADDR and addr_buffer(7) = '0' else
'1' when cur_state = TX_BYTE and transmit_buffer(7) = '1' else
'0' when cur_state = TX_BYTE and transmit_buffer(7) = '0' else
'0' when cur_state = ACK_BYTE and write_mode = '0' and i2c_read = '1' else
'1' ;
process(clk, reset)
begin
if reset = '1' then
sda_shift_reg <= (others => '1');
elsif clk'event and clk = '1' then
sda_shift_reg(0) <= sda_unbuf ;
sda_shift_reg(sda_shift_reg'high downto 1) <= sda_shift_reg(sda_shift_reg'high-1 downto 0);
end if ;
end process ;
sda <= 'Z' when cur_state = ACK_BYTE and write_mode = '1' else
'0' when sda_shift_reg(sda_shift_reg'high) = '0' else
'Z' ;
process(clk, reset)
begin
if reset = '1' then
is_acked <= '0' ;
elsif clk'event and clk = '1' then
if (cur_state = ACK_BYTE or cur_state = ACK_ADDR ) and sda = '0' then
is_acked <= '1' ;
elsif cur_state /= ACK_BYTE then
is_acked <= '0' ;
end if ;
end if ;
end process ;
ack <= '1' when cur_state = ACK_BYTE and is_acked = '1' and full = '1' else
'1' when cur_state = ACK_BYTE and next_state = RX_BYTE else
'1' when cur_state = ACK_ADDR and is_acked = '1' and full = '1' else
'0' ;
nack <= '1' when cur_state = ACK_BYTE and write_mode = '1' and full='1' and is_acked = '0' else
'1' when cur_state = ACK_ADDR and full='1' and is_acked = '0' else
'0' ;
busy <= '0' when cur_state = IDLE else
'1' ;
new_data <= '1' when cur_state = ACK_BYTE and write_mode = '0' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
transmit_buffer <= (others => '0') ;
receive_buffer <= (others => '0') ;
addr_buffer <= (others => '0') ;
bit_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if (cur_state = IDLE and i2c_write = '1') or i2c_read = '1' then
addr_buffer <= slave_addr & i2c_read ;
elsif cur_state = TX_ADDR and full = '1' then
addr_buffer(7 downto 1) <= addr_buffer(6 downto 0);
end if;
if cur_state = IDLE and i2c_write = '1' then
transmit_buffer <= data_in ;
elsif cur_state = TX_BYTE and full = '1' then
transmit_buffer(7 downto 1) <= transmit_buffer(6 downto 0);
transmit_buffer(0) <= '0' ;
elsif cur_state = ACK_BYTE and i2c_write = '1' and is_acked = '1' then
transmit_buffer <= data_in;
end if;
if cur_state = IDLE then
receive_buffer <= (others => '0') ;
elsif cur_state = RX_BYTE and half = '1' then
receive_buffer(7 downto 1) <= receive_buffer(6 downto 0);
receive_buffer(0) <= sda ;
end if;
if cur_state = IDLE or cur_state = ACK_BYTE or cur_state = ACK_ADDR then
bit_counter <= (others => '0') ;
elsif (cur_state = TX_ADDR or cur_state = TX_BYTE) and full = '1' then
bit_counter <= bit_counter + 1 ;
end if;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
write_mode <= '0' ;
elsif clk'event and clk = '1' then
if cur_state = IDLE and i2c_write = '1' then
write_mode <= '1' ;
elsif cur_state = I2C_STOP then
write_mode <= '0' ;
end if;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/control/ADCS7476_ctrl.vhd | 2 | 4818 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end ADCS7476_ctrl;
architecture Behavioral of ADCS7476_ctrl is
constant divider_modulo : positive := ((sclk_period_ns/clk_period_ns)/2)-1 ;
constant tick_between_samples : positive := (time_between_sample_ns/sclk_period_ns);
type com_state is (WAIT_SAMPLE, ASSERT_SS, SCLK_LOW, SCLK_HIGH, DEASSERT_SS);
signal cur_state, next_state : com_state ;
signal bit_counter : std_logic_vector(15 downto 0);
signal bit_counter_en, bit_counter_reset : std_logic ;
signal clk_divider : std_logic_vector(15 downto 0);
signal end_divider : std_logic ;
signal shift_in : std_logic ;
signal data_reg : std_logic_vector(15 downto 0);
signal ss_comb, sclk_comb, miso_latched : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
elsif clk'event and clk = '1' then
if clk_divider = 0 then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
else
clk_divider <= clk_divider - 1 ;
end if ;
end if;
end process ;
end_divider <= '1' when clk_divider = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
bit_counter <= (others => '0');
elsif clk'event and clk = '1' then
if bit_counter_reset = '1' then
bit_counter <= (others => '0');
elsif bit_counter_en = '1' then
bit_counter <= bit_counter + 1;
end if ;
end if;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
cur_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
cur_state <= next_state;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_reg <= (others => '0');
elsif clk'event and clk = '1' then
if shift_in = '1' then
data_reg(15 downto 1) <= data_reg(14 downto 0);
data_reg(0) <= miso_latched ;
end if ;
end if;
end process ;
process(cur_state, bit_counter, end_divider)
begin
next_state <= cur_state ;
case cur_state is
when WAIT_SAMPLE =>
if bit_counter = tick_between_samples and end_divider = '1' then
next_state <= ASSERT_SS ;
end if ;
when ASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when SCLK_LOW =>
if end_divider = '1' then
next_state <= SCLK_HIGH ;
end if ;
when SCLK_HIGH =>
if bit_counter = 15 and end_divider = '1' then
next_state <= DEASSERT_SS ;
elsif end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when DEASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= WAIT_SAMPLE ;
end if ;
when others => next_state <= WAIT_SAMPLE ;
end case;
end process ;
with cur_state select
bit_counter_en <= end_divider when SCLK_HIGH,
'0' when SCLK_LOW,
end_divider when others ;
bit_counter_reset <= '1' when cur_state = ASSERT_SS and next_state = SCLK_LOW else
'1' when cur_state = WAIT_SAMPLE and next_state = ASSERT_SS else
'1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'1' when cur_state = DEASSERT_SS and next_state = WAIT_SAMPLE else
'0';
shift_in <= '1' when cur_state = SCLK_LOW and next_state = SCLK_HIGH else
'0' ;
sample_valid <= '1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'0' ;
sample_out <= data_reg(12 downto 1);
ss_comb <= '1' when cur_state = WAIT_SAMPLE else
'1' when cur_state = DEASSERT_SS else
'0' ;
with cur_state select
sclk_comb <= '0' when SCLK_LOW,
'1' when others ;
process(clk, resetn)
begin
if resetn = '0' then
ss <= '1' ;
sclk <= '1' ;
miso_latched <= '0' ;
elsif clk'event and clk = '1' then
ss <= ss_comb;
sclk <= sclk_comb ;
miso_latched <= miso ;
end if;
end process ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/control/pwm.vhd | 2 | 3650 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:57:26 04/20/2013
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work ;
use work.control_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm is
generic(NB_CHANNEL : positive := 3);
port(
clk, resetn : in std_logic ;
divider : in std_logic_vector(15 downto 0);
period : in std_logic_vector(15 downto 0);
pulse_width : in slv16_array(0 to NB_CHANNEL-1) ;
pwm : out std_logic_vector(0 to NB_CHANNEL-1)
);
end pwm;
architecture Behavioral of pwm is
signal end_div : std_logic ;
signal divider_counter, period_counter: std_logic_vector(15 downto 0);
signal period_q : std_logic_vector(15 downto 0);
signal pulse_width_q : slv16_array(0 to NB_CHANNEL-1);
signal en_period_count : std_logic ;
signal pwm_d : std_logic_vector(0 to NB_CHANNEL-1) ;
begin
process(clk, resetn)
begin
if resetn = '0' then
divider_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= divider ;
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
en_period_count <= '1' when divider_counter = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
period_q <= (others => '0');
pulse_width_q <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if period_counter = 0 then
period_q <= period ;
pulse_width_q <= pulse_width ;
end if ;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
period_counter <= (others => '0');
elsif clk'event and clk = '1' then
if en_period_count = '1' then
if period_counter = period_q then
period_counter <= (others => '0');
else
period_counter <= period_counter + 1 ;
end if ;
end if ;
end if ;
end process ;
gen_outs : for i in 0 to NB_CHANNEL-1 generate
pwm_d(i) <= '1' when period_counter < pulse_width_q(i) else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
pwm(i) <= '0';
elsif clk'event and clk = '1' then
pwm(i) <= pwm_d(i) ;
end if ;
end process ;
end generate ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/control/sseg_4x.vhd | 2 | 3193 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity sseg_4x is
generic(
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port(
clk, reset : in std_logic ;
bcd_in : in std_logic_vector(15 downto 0);
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end sseg_4x;
architecture Behavioral of sseg_4x is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal divider_counter : std_logic_vector(nbit(clk_divider)-1 downto 0);
signal divider_end : std_logic ;
signal cathode_buffer : std_logic_vector(4 downto 0);
signal segs : slv8_array(0 to 3) ;
begin
gen_seg_decoder : for i in 0 to 3 generate
with bcd_in(((i+1)*4)-1 downto (i*4)) select
segs(i) <= X"3F" when "0000",
X"06" when "0001",
X"5B" when "0010",
X"4F" when "0011",
X"66" when "0100",
X"6D" when "0101",
X"7D" when "0110",
X"07" when "0111",
X"7F" when "1000",
X"6F" when "1001",
X"77" when "1010",
X"7C" when "1011",
X"39" when "1100",
X"5E" when "1101",
X"79" when "1110",
X"71" when others;
end generate ;
-- sseg logic
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cathode_buffer(0) <= '1' ;
cathode_buffer(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
cathode_buffer(4 downto 1) <= cathode_buffer(3 downto 0);
cathode_buffer(0) <= cathode_buffer(4);
end if ;
end if ;
end process ;
with cathode_buffer select
sseg_anode_out <= segs(0) when "01000",
segs(1) when "00100",
segs(2) when "00010",
segs(3) when "00001",
(others => '0') when others ;
sseg_cathode_out <= cathode_buffer ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_led_matrix_ctrl.vhd | 2 | 4165 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:28:56 07/06/2014
-- Design Name:
-- Module Name: wishbone_led_matrix_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- This controller is based on Glen Atkins work (http://bikerglen.com/projects/lighting/led-panel-1up/)
-- Minor modification on controller behavior to adapt to wishbone bus
-- Major modification on coding style to meet XST guidelines
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
use work.control_pack.all ;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_led_matrix_ctrl is
generic(wb_size : positive := 16;
clk_div : positive := 10;
-- TODO: nb_panels is untested, still need to be validated
nb_panels : positive := 1 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle : positive := 1910
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end wishbone_led_matrix_ctrl;
architecture Behavioral of wishbone_led_matrix_ctrl is
signal read_ack : std_logic ;
signal write_ack, write_pixel: std_logic ;
signal pixel_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
begin
-- wishbone related logic
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
-- ram buffer instanciation
write_pixel <= wbs_strobe and wbs_write and wbs_cycle ;
pixel_addr <= wbs_address(pixel_addr'high downto 0);
matrix_ctrl0 : rgb_32_32_matrix_ctrl
generic map(
clk_div => clk_div,
nb_panels => nb_panels,
expose_step_cycle => expose_step_cycle,
bits_per_color => bits_per_color
)
port map(
clk => gls_clk, reset => gls_reset,
pixel_addr => pixel_addr,
pixel_value_in => wbs_writedata((bits_per_color*3)-1 downto 0),
pixel_value_out => wbs_readdata((bits_per_color*3)-1 downto 0),
write_pixel => write_pixel,
SCLK_OUT => SCLK_OUT,
BLANK_OUT => BLANK_OUT,
LATCH_OUT => LATCH_OUT,
A_OUT => A_OUT,
R_out => R_OUT,
G_out => G_OUT,
B_out => B_OUT
);
wbs_readdata (15 downto (bits_per_color*3)) <= (others => '0');
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/primitive/MAC16.vhd | 2 | 1703 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 18:43:10 03/05/2012
-- Design Name:
-- Module Name: MAC16 - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MAC16 is
port(clk, sraz : in std_logic;
add_subb, reset_acc : in std_logic;
A, B : in signed(15 downto 0);
RES : out signed(31 downto 0)
);
end MAC16;
architecture Behavioral of MAC16 is
signal mult, accum: signed(31 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
if (sraz = '1') then
accum <= (others => '0');
mult <= (others => '0');
else
if reset_acc = '1' then
accum <= (others => '0');
elsif add_subb = '1' then
accum <= accum + mult;
else
accum <= accum - mult;
end if;
mult <= A * B;
end if;
end if;
end process;
RES <= accum ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_double_buffer.vhd | 2 | 5400 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:24:19 11/08/2013
-- Design Name:
-- Module Name: double_buffer - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_double_buffer is
generic( wb_add_width: positive := 16; --! width of the address bus
wb_data_width : positive := 16; --! width of the data bus
buffer_size : positive := 64 --! buffer size
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_add_width-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_add_width-1 downto 0);
wbs_readdata : out std_logic_vector( wb_add_width-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
buffer_index : out std_logic ; -- index of buffer currently in use
free_buffer : in std_logic ; -- indicate that written buffer is free to switch
write_buffer : in std_logic ;
buffer_input : in std_logic_vector(15 downto 0);
buffer_address : in std_logic_vector(15 downto 0)
);
end wishbone_double_buffer;
architecture Behavioral of wishbone_double_buffer is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
signal buffer_use : std_logic_vector(1 downto 0);
signal buffer_read_data : std_logic_vector(15 downto 0);
signal read_address, write_address : std_logic_vector(12 downto 0);
signal buffer_locked : std_logic ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
-- need to implement write to the status register somewhere
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
-- need to implement read of the status register somewhere
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0';
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
buffer_locked <= read_ack ;
wbs_readdata <= buffer_read_data ;
-- ram being used to implement the double buffer memory
ram0 : dpram_NxN
generic map(SIZE => (buffer_size*2), NBIT => wb_data_width, ADDR_WIDTH=> 13) -- need to be computed
port map(
clk => gls_clk,
we => write_buffer ,
di => buffer_input,
a => write_address ,
dpra => read_address,
spo => open,
dpo => buffer_read_data
);
-- highest bit select buffer to write to
write_address(write_address'high) <= buffer_use(1) ;
write_address(write_address'high-1 downto 0) <= buffer_address(write_address'high-1 downto 0);
read_address(read_address'high) <= buffer_use(0) ;
read_address(read_address'high-1 downto 0) <= wbs_address(read_address'high-1 downto 0);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
buffer_use <= "01" ;
elsif gls_clk'event and gls_clk = '1' then
if free_buffer = '1' and buffer_locked = '0' then -- if write and one buffer at least is available
buffer_use <= not buffer_use ;
end if ;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/utils/dram_fifo.vhd | 2 | 15305 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:13 10/16/2014
-- Design Name:
-- Module Name: dram_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
use work.logi_primitive_pack.all ;
entity dram_fifo is
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 16_777_216;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- FIFO interface
reset_fifo : in std_logic ;
write_fifo, read_fifo : in std_logic ;
nb_available : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end dram_fifo;
architecture Behavioral of dram_fifo is
type cache_controller_state is (IDLE, REFRESH, FLUSH);
constant CACHE_END_ADDRESS : std_logic_vector(sdram_address_width-2 downto 0) := CACHE_ADDRESS(sdram_address_width-2 downto 0) + (FIFO_SIZE/2);
constant cache_byte_granularity : positive := 256 ;
constant cache_index_low_fifo_side : positive := nbit(cache_byte_granularity)-1;
constant cache_index_low_sdram_side : positive := nbit(cache_byte_granularity)-2;
signal cache_current_state, cache_next_state : cache_controller_state;
signal fifo_write_address, fifo_read_address : std_logic_vector(cache_index_low_fifo_side downto 0);
signal sdram_write_address, sdram_read_address : std_logic_vector(sdram_address_width-2 downto 0);
signal cache_write_address, cache_read_address : std_logic_vector(cache_index_low_sdram_side downto 0);
signal cache_out, cache_in : std_logic_vector(31 downto 0);
signal cache_require_refresh, cache_require_flush : std_logic ;
signal cache_counter : std_logic_vector(6 downto 0);
signal cache_ready : std_logic ;
signal write_fifo_index, read_fifo_index : std_logic ;
signal refresh_done, flush_done, cache_require_flush_reset, cache_require_refresh_reset : std_logic ;
signal old_write_line_index, old_read_line_index : std_logic ;
signal write_fifo_write, write_cache_write : std_logic ;
signal fifo_wr, fifo_rd : std_logic ;
signal rd_old, wr_old, wr_data, rd_data, one_turn, latch_data : std_logic ;
signal rd_rising_edge, wr_rising_edge : std_logic ;
signal rd_falling_edge, wr_falling_edge : std_logic ;
signal fifo_nb_available_t : std_logic_vector(31 downto 0);
signal fifo_ready : std_logic ;
signal flushed_line_count : std_logic_vector(15 downto 0);
signal read_cache_init : std_logic_vector(1 downto 0);
begin
refresh_active <= '1' when cache_current_state = REFRESH else
'0' ;
flush_active <= '1' when cache_current_state = FLUSH else
'0' ;
cmd_byte_enable <= (others => '1');
-- CACHE MANAGEMENT
process(clk, reset)
begin
if reset = '1' then
cache_current_state <= IDLE; -- CACHE init state is IDLE
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
cache_current_state <= IDLE;
else
cache_current_state <= cache_next_state;
end if ;
end if ;
end process ;
process(cache_ready, cache_require_refresh, cache_require_flush, refresh_done, flush_done, cache_current_state)
begin
cache_next_state <= cache_current_state ;
case cache_current_state is
when IDLE =>
if cache_require_refresh = '1' and cache_ready = '1' then
cache_next_state <= REFRESH ; -- CACHE can only be refreshed if already flushed onces
elsif cache_require_flush = '1' then
cache_next_state <= FLUSH ;
end if ;
when REFRESH =>
if refresh_done = '1' then
cache_next_state <= IDLE ;
end if ;
when FLUSH =>
if flush_done = '1' then
cache_next_state <= IDLE ;
end if ;
when others =>
cache_next_state <= IDLE ;
end case ;
end process ;
-- CACHE REFRESH/FLUSH STRATEGY
process(clk, reset)
begin
if reset = '1' then
cache_ready <= '0' ;
cache_require_refresh <= '0' ;
cache_require_flush <= '0';
write_fifo_index <= '0';
read_fifo_index <= '0';
fifo_ready <= '0' ;
read_cache_init <= "11";
elsif clk'event and clk = '1' then
-- CACHE IS FLUSHED WHENEVER THE FIFO_INDEX BIT CHANGES
if reset_fifo = '1' then
cache_require_flush <= '0';
elsif cache_require_flush_reset = '1' then
cache_require_flush <= '0';
elsif write_fifo_index /= fifo_write_address(fifo_write_address'high) then
cache_require_flush <= '1'; -- CACHE require flush when one line of cache was written
-- fifo write address highest byte indicate cache line address
end if ;
write_fifo_index <= fifo_write_address(fifo_write_address'high) ;
-- CACHE IS REFRESHED ONCE TWICE AND THEN
-- WHENEVER THE FIFO_INDEX BIT CHANGES
if reset_fifo = '1' then
read_cache_init <= "11"; -- at reset init indicates that cache can be refreshed twice
cache_require_refresh <= '0' ;
elsif cache_require_refresh_reset = '1' then -- a refresh was performed
cache_require_refresh <= '0';
read_cache_init(1) <= '0' ;
read_cache_init(0) <= read_cache_init(1) ;
elsif read_cache_init /= 0 and flushed_line_count > 0 then -- a refresh is required as init of cache was not performed
cache_require_refresh <= '1';
elsif read_cache_init = 0 and read_fifo_index /= fifo_read_address(fifo_read_address'high) and flushed_line_count > 0 then
cache_require_refresh <= '1'; -- normal case to trigger a refresh. One line of cache was fully consumed
end if ;
read_fifo_index <= fifo_read_address(fifo_read_address'high) ;
-- CACHE IS CONSIDERED READY WHEN IT WAS ONCE FLUSHED AND REFRESHED
-- THIS LIMIT GRANULARITY OF FIFO
if reset_fifo = '1' then
cache_ready <= '0' ;
elsif cache_current_state = FLUSH and cache_next_state = IDLE then
cache_ready <= '1' ;
end if ;
--TODO: decide when cache is not ready anymore ...
-- FIFO IS CONSIDERED READY WHEN IT WAS ONCE REFRESHED
-- THIS LIMIT GRANULARITY OF FIFO
if reset_fifo = '1' then
fifo_ready <= '0' ;
elsif cache_current_state = REFRESH and cache_next_state = IDLE then
fifo_ready <= '1' ;
elsif fifo_ready = '1' and fifo_nb_available_t = 0 then
fifo_ready <= '0' ;-- fifo is fully empty the cache is not ready anymore
end if ;
end if ;
end process ;
-- SDRAM WRITE ADDRESS IS INCREMENTED WHEN CACHE IS FLUSHED
-- END OF FLUSH IS REACHED WHEN THE CACHE_LINE_INDEX CHANGES
process(clk, reset)
begin
if reset = '1' then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
old_write_line_index <= '0' ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
elsif cache_current_state = FLUSH and cmd_ready = '1' then --incrementing on falling edge of ready signal
if sdram_write_address = CACHE_END_ADDRESS then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
else
sdram_write_address <= sdram_write_address + 1 ;
end if ;
end if ;
if reset_fifo = '1' then
old_write_line_index <= '0' ;
else
old_write_line_index <= sdram_write_address(cache_index_low_sdram_side);
end if ;
end if ;
end process ;
cache_read_address <= sdram_write_address(cache_read_address'high downto 0);
flush_done <= '1' when cache_current_state = FLUSH and old_write_line_index /= sdram_write_address(cache_index_low_sdram_side) else
'0' ;
cache_require_flush_reset <= '1' when cache_current_state = FLUSH and cache_next_state=IDLE else
'0' ;
-- SDRAM_READ_ADDRESS IS INCREMENTED ON REFRESH UNTIL THE CACHE_LINE_INDEX CHANGES
process(clk, reset)
begin
if reset = '1' then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
cache_write_address <= (others => '0');
old_read_line_index <= '0' ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
elsif cache_current_state = REFRESH and refresh_done = '0' and cmd_ready = '1' and cache_write_address(cache_write_address'high) = sdram_read_address(cache_write_address'high) then
if sdram_read_address = CACHE_END_ADDRESS then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
else
sdram_read_address <= sdram_read_address + 1 ;
end if ;
end if ;
-- CACHE_WRITE_ADDRESS IS ONLY INCREMENT WHEN SDRAM PIPELINE IS INITIALIZED
if reset_fifo = '1' then
cache_write_address <= (others => '0');
elsif cache_current_state = REFRESH and sdram_data_ready = '1' then
cache_write_address <= cache_write_address + 1 ;
end if ;
if reset_fifo = '1' then
old_read_line_index <= '0' ;
else
old_read_line_index <= cache_write_address(cache_write_address'high);
end if ;
end if ;
end process ;
refresh_done <= '1' when cache_current_state = REFRESH and old_read_line_index /= cache_write_address(cache_write_address'high) else
'0';
write_cache_write <= '1' when cache_current_state = REFRESH and sdram_data_ready = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
flushed_line_count <= (others => '0');
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
flushed_line_count <= (others => '0');
elsif refresh_done = '1' and flushed_line_count > 0 then
flushed_line_count <= flushed_line_count - 1;
elsif flush_done = '1' then
flushed_line_count <= flushed_line_count + 1;
end if ;
end if ;
end process ;
cache_require_refresh_reset <= '1' when cache_current_state = REFRESH and cache_next_state=IDLE else
'0' ;
---- WRITE COMMAND IS ACTIVE ON FLUSH
--cmd_wr <= cmd_ready when cache_current_state = FLUSH else
cmd_wr <= '1' when cache_current_state = FLUSH else
'0' ;
---- CMD_ENABLE IS ACTIVE ON FLUSH AND ON REFRESH UNTIL THE SDRAM_READ_ADDRESS INDICATING CACHE_LINE_INDEX
---- CHANGES
---- THIS SEEMS TO AFFECT TIMING ...
cmd_enable <= '0' when cache_current_state = IDLE else
'1' when cache_current_state = REFRESH and cache_write_address(cache_write_address'high) = sdram_read_address(cache_write_address'high) else
'1' when cache_current_state = FLUSH else
'0';
----CMD_ADDRESS IS EITHER READ_ADDRESS OR WRITE_ADDRESS DEPENDING ON FLUSH OR REFRESH
---- THIS SEEMS TO AFFECT TIMING ...
with cache_current_state select
cmd_address <= sdram_write_address when FLUSH,
sdram_read_address when REFRESH,
(others => '0') when others ;
cache_in <= sdram_data_out ;
cmd_data_in <= cache_out ;
-- CACHE ARE INSTANTIATED IN NEXT SECTION
-- write cache is divided into two lines
-- one line is always available for write, and one line is always available
-- to be flushed to SDRAM
write_cache : tdp_bram
generic map(
DATA_A => 16,
ADDR_A => 8,
DATA_B => 32,
ADDR_B => 7
)
port map(
-- Port A
a_clk => clk,
a_wr => write_fifo_write,
a_addr => fifo_write_address,
a_din => data_in,
a_dout => open,
-- Port B
b_clk => clk,
b_wr => '0',
b_addr => cache_read_address,
b_din => (others => '0'),
b_dout => cache_out
);
-- read cache is divided into two lines
-- one line is always available for read, and one line is always available
--for refresh
read_cache : tdp_bram
generic map(
DATA_A => 16,
ADDR_A => 8,
DATA_B => 32,
ADDR_B => 7
)
port map(
-- Port A
a_clk => clk,
a_wr => '0',
a_addr => fifo_read_address,
a_din => (others => '0'),
a_dout => data_out,
-- Port B
b_clk => clk,
b_wr => write_cache_write,
b_addr => cache_write_address,
b_din => cache_in,
b_dout => open
);
-- HERE STARTS FIFO STRUCTURE
gen_async_rd : if NOT SYNC_READ generate
process(reset, clk)
begin
if reset = '1' then
rd_old <= '0' ;
elsif clk'event and clk = '1' then
rd_old <= read_fifo ;
end if ;
end process ;
rd_falling_edge <= ((NOT read_fifo) AND rd_old);
fifo_rd <= rd_falling_edge ;
end generate ;
gen_sync_rd : if SYNC_READ generate
fifo_rd <= read_fifo;
end generate ;
gen_async_wr : if NOT SYNC_WRITE generate
process(reset, clk)
begin
if reset = '1' then
wr_old <= '0' ;
elsif clk'event and clk = '1' then
wr_old <= write_fifo ;
end if ;
end process ;
wr_falling_edge <= ((NOT write_fifo) AND wr_old) ;
fifo_wr <= wr_falling_edge ;
end generate ;
gen_sync_wr : if SYNC_WRITE generate
fifo_wr <= write_fifo ;
end generate ;
write_fifo_write <= fifo_wr ;
--rd process
process(clk, reset)
begin
if reset = '1' then
fifo_read_address <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_read_address <= (others => '0') ;
elsif fifo_rd = '1' and fifo_nb_available_t /= 0 then
fifo_read_address <= fifo_read_address + 1;
end if ;
end if ;
end process ;
-- wr process
process(clk, reset)
begin
if reset = '1' then
fifo_write_address <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_write_address <= (others => '0') ;
elsif fifo_wr = '1' and fifo_nb_available_t /= FIFO_SIZE then
fifo_write_address <= fifo_write_address + 1;
end if ;
end if ;
end process ;
-- nb available process
process(clk, reset)
begin
if reset = '1' then
fifo_nb_available_t <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_nb_available_t <= (others => '0') ;
elsif fifo_wr = '1' and fifo_rd = '0' and fifo_nb_available_t /= FIFO_SIZE then
fifo_nb_available_t <= fifo_nb_available_t + 1 ;
elsif fifo_rd = '1' and fifo_wr = '0' and fifo_nb_available_t /= 0 then
fifo_nb_available_t <= fifo_nb_available_t - 1 ;
end if ;
end if ;
end process ;
nb_available <= fifo_nb_available_t when fifo_ready = '1' else
(others => '0');
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/primitive/logi_primitive_pack.vhd | 2 | 1778 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package logi_primitive_pack is
component MAC16 is
port(clk, sraz : in std_logic;
add_subb, reset_acc : in std_logic;
A, B : in signed(15 downto 0);
RES : out signed(31 downto 0)
);
end component;
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
component tdp_bram is
generic (
DATA_A : integer := 16;
ADDR_A : integer := 10;
DATA_B : integer := 16;
ADDR_B : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_A-1 downto 0);
a_din : in std_logic_vector(DATA_A-1 downto 0);
a_dout : out std_logic_vector(DATA_A-1 downto 0);
-- Port B
b_clk : in std_logic;
b_wr : in std_logic;
b_addr : in std_logic_vector(ADDR_B-1 downto 0);
b_din : in std_logic_vector(DATA_B-1 downto 0);
b_dout : out std_logic_vector(DATA_B-1 downto 0)
);
end component;
end logi_primitive_pack;
package body logi_primitive_pack is
end logi_primitive_pack;
| lgpl-3.0 |
QuickJack/logi-hard | hdl/virtual_instrument/logi_virtual_pb.vhd | 2 | 3235 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:18:41 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_pb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end logi_virtual_pb;
architecture Behavioral of logi_virtual_pb is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
pb <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
| lgpl-3.0 |
QuickJack/logi-hard | test_bench/servo_controller_tb.vhd | 2 | 3341 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:22 05/12/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-projects/AVC2013/avc_platform/servo_controller_tb.vhd
-- Project Name: avc_platform
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: servo_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY servo_controller_tb IS
END servo_controller_tb;
ARCHITECTURE behavior OF servo_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT servo_controller
PORT(
clk : IN std_logic;
rst : IN std_logic;
servo_position : IN std_logic_vector(0 to 7);
servo_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal servo_position : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal servo_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: servo_controller PORT MAP (
clk => clk,
rst => rst,
servo_position => servo_position,
servo_out => servo_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1' ;
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0' ;
servo_position <= X"80";
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 |
QuickJack/logi-hard | test_bench/encoder_interface_tb.vhd | 2 | 3625 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:14:41 05/12/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/encoder_interface_tb.vhd
-- Project Name: test_ugv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: encoder_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY encoder_interface_tb IS
END encoder_interface_tb;
ARCHITECTURE behavior OF encoder_interface_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT encoder_interface
generic(FREQ_DIV : positive := 100; SINGLE_CHANNEL : boolean := true);
PORT(
clk : IN std_logic;
reset : IN std_logic;
channel_a : IN std_logic;
channel_b : IN std_logic;
period : OUT std_logic_vector(15 downto 0);
reset_count : IN std_logic;
count : OUT std_logic_vector(15 downto 0);
pv : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal channel_a : std_logic := '0';
signal channel_b : std_logic := '0';
signal reset_count : std_logic := '0';
--Outputs
signal period : std_logic_vector(15 downto 0);
signal count : std_logic_vector(15 downto 0);
signal pv : std_logic;
signal dir : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant enc_period : time := 10 us ;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: encoder_interface
generic map(SINGLE_CHANNEL => false)
PORT MAP (
clk => clk,
reset => reset,
channel_a => channel_a,
channel_b => channel_b,
period => period,
reset_count => reset_count,
count => count,
pv => pv
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1' ;
channel_a <= '0' ;
channel_b <= '0' ;
reset_count <= '0' ;
wait for 100 ns;
reset <= '0' ;
wait for clk_period*10;
for i in 0 to 10 loop
channel_a <= '1' ;
channel_b <= '0' ;
wait for enc_period/4;
channel_b <= '1' ;
wait for enc_period/4;
channel_a <= '0' ;
wait for enc_period/4;
channel_b <= '0' ;
wait for enc_period/4;
end loop ;
wait for enc_period*2;
for i in 0 to 10 loop
channel_a <= '0' ;
channel_b <= '1' ;
wait for enc_period/4;
channel_a <= '1' ;
wait for enc_period/4;
channel_b <= '0' ;
wait for enc_period/4;
channel_a <= '0' ;
wait for enc_period/4;
end loop ;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 |
HackLinux/ION | src/testbench/ion_cpu_tb.vhdl | 1 | 15208 | --##############################################################################
-- ion_cpu_tb.vhdl -- Test bench for standalone CPU.
--
-- Simulates the CPU connected to fake memory on both buses.
-- The size and contents of the simulated memory are defined in package
-- sim_params_pkg.
--
--------------------------------------------------------------------------------
-- MEMORY MAP (except IO areas, see below):
--
-- Code ROM Data RAM
-- -----------------------------
-- Code [00000000..FFFFFFFF] : R/O
-- Data [00000000..BFBFFFFF] : R/W
-- Data [BFC00000..BFCFFFFF] : R/O
-- Data [BFD00000..FFFFFFFF] : R/W
-- -----------------------------
--
-- Note we only simulate two separate blocks, ROM for code and RAM for data.
-- Both are mirrored all over the decoded memory spaces.
-- The code ROM is accessible from the data bus so that SW constants can be
-- easily reached.
--
--------------------------------------------------------------------------------
-- FIXME no support for simulating external IRQs.
--------------------------------------------------------------------------------
-- SIMULATED IO DEVICES:
-- Apart from the fake UART implemented in package ion_tb_pkg, this test bench
-- simulates the following ports:
--
-- 20010020: Debug register 0 (R/W). -- FIXME unimplemented
-- 20010024: Debug register 1 (R/W). -- FIXME unimplemented
-- 20010028: Debug register 2 (R/W). -- FIXME unimplemented
-- 2001002c: Debug register 3 (R/W). -- FIXME unimplemented
-- 20010030: Wait states for simulated code memory accesses (W/o).
-- 20010034: Wait states for simulated data memory accesses (W/o).
--
-- NOTE: These addresses are for write accesses only. For read accesses, the
-- debug registers 0..3 are mirrored over all the io address range 2001xxxxh.
--
-- The debug registers 0 to 3 can only be used to test 32-bit i/o.
-- All of these registers can only be addressed as 32-bit words. Any other type
-- of access will yield undefined results.
--
-- These registers are only write-enabled if the generic ENABLE_DEBUG_REGISTERS
-- is TRUE.
--------------------------------------------------------------------------------
-- Console logging:
--
-- The TB implements a simple, fake console at address 0x20000000.
-- Any bytes written to that address will be logged to text file
-- "hw_sim_console_log.txt".
--
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
-- line buffering; it will not print anything until it gets a CR (0x0d), and
-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you
-- expect it.
--
--------------------------------------------------------------------------------
-- WARNING: This TB will only work on Modelsim; uses custom library SignalSpy.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
use work.ION_TB_PKG.all;
-- Simulation parameters defined in the SW makefile (generated package).
use work.SIM_PARAMS_PKG.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
entity ION_CPU_TB is
generic (
CODE_WCYCLES : integer := 1;
DATA_WCYCLES : integer := 0;
ENABLE_DEBUG_REGISTERS : boolean := false
);
end;
architecture testbench of ION_CPU_TB is
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Memory.
-- For CPU verification, we'll connect a data array to the CPU data port with no
-- intervening cache, like TCMs.
-- For the data array, we'll use the data memory size and initialization values.
constant DTCM_SIZE : integer := DATA_MEM_SIZE;
constant DTCM_ADDR_SIZE : integer := log2(DTCM_SIZE);
-- Using shared variables for big memory arrays speeds up simulation a lot;
-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
-- WARNING: I have only tested this construct with Modelsim SE 6.3.
shared variable dtcm : t_word_table(0 to DTCM_SIZE-1) := (others => X"00000000");
signal dtcm_addr : std_logic_vector(DTCM_ADDR_SIZE downto 2);
signal dtcm_data : t_word;
signal data_dtcm_ce : std_logic;
signal data_dtcm_ce_reg : std_logic;
signal data_rd_en_reg : std_logic;
signal dtcm_wait : std_logic;
signal data_ctcm_ce : std_logic;
signal data_dtcm : t_word;
signal data_ctcm : t_word;
-- For the code array, we'll use the code memory size and initialization values.
constant CTCM_SIZE : integer := CODE_MEM_SIZE;
constant CTCM_ADDR_SIZE : integer := log2(CTCM_SIZE);
shared variable ctcm : t_word_table(0 to CTCM_SIZE-1) := objcode_to_wtable(obj_code, CTCM_SIZE);
signal ctcm_addr : std_logic_vector(CTCM_ADDR_SIZE downto 2);
signal ctcm_data : t_word;
signal ctcm_wait : std_logic;
signal code_wait_ctr : integer range -2 to 63;
signal data_wait_ctr : integer range -2 to 63;
signal code_ctcm_ce_reg : std_logic;
signal code_ctcm : t_word;
--------------------------------------------------------------------------------
-- CPU interface.
signal clk : std_logic := '0';
signal clk_delayed : std_logic;
signal reset : std_logic := '1';
signal data_mosi : t_cpumem_mosi;
signal data_miso : t_cpumem_miso;
signal code_mosi : t_cpumem_mosi;
signal code_miso : t_cpumem_miso;
signal cache_mosi : t_cache_mosi;
signal icache_miso : t_cache_miso;
signal dcache_miso : t_cache_miso;
signal irq : std_logic_vector(7 downto 0);
--------------------------------------------------------------------------------
-- Debug registers.
signal debug_reg_ce : std_logic;
signal wait_states_code : unsigned(5 downto 0) := (others => '0');
signal wait_states_data : unsigned(5 downto 0) := (others => '0');
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- All the info needed by the logger is here
signal log_info : t_log_info;
--------------------------------------------------------------------------------
begin
cpu: entity work.ION_CPU
generic map (
XILINX_REGBANK => "distributed"
)
port map (
CLK_I => clk,
RESET_I => reset,
DATA_MOSI_O => data_mosi,
DATA_MISO_I => data_miso,
CODE_MOSI_O => code_mosi,
CODE_MISO_I => code_miso,
CACHE_CTRL_MOSI_O => cache_mosi,
CACHE_CTRL_MISO_I => cache_miso,
IRQ_I => irq
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
clk_delayed <= clk after 1 ns;
-- Main simulation process: reset MCU and wait for fixed period ------------
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
-- Flush console output to log console file (in case the end of the
-- simulation caught an unterminated line in the buffer)
if log_info.con_line_ix > 1 then
write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
writeline(con_file, l);
end if;
print("TB finished");
done <= '1';
wait;
end process drive_uut;
-- Data memory -------------------------------------------------------------
dtcm_addr <= data_mosi.addr(dtcm_addr'high downto 2);
data_miso.mwait <= dtcm_wait;
data_ctcm_ce <= '1' when data_mosi.addr(31 downto 20) = X"bfc" else '0';
data_dtcm_ce <= '1' when data_mosi.addr(31 downto 28) /= X"2" and
data_ctcm_ce='0'
else '0';
-- Simulated data RAM write port.
-- Note we ignore the wait states; we get the data when it's in DATA_MOSI
-- and let the CPU deal with the simulated wait states.
-- This is the behavior expected from a real ION bus slave.
simulated_dtcm_write:
process(clk)
begin
if clk'event and clk='1' then
if data_dtcm_ce='1' then
if data_mosi.wr_be(0)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(7 downto 0) := data_mosi.wr_data(7 downto 0);
end if;
if data_mosi.wr_be(1)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(15 downto 8) := data_mosi.wr_data(15 downto 8);
end if;
if data_mosi.wr_be(2)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(23 downto 16) := data_mosi.wr_data(23 downto 16);
end if;
if data_mosi.wr_be(3)='1' then
dtcm(to_integer(unsigned(dtcm_addr)))(31 downto 24) := data_mosi.wr_data(31 downto 24);
end if;
end if;
end if;
end process simulated_dtcm_write;
-- Simulated data RAM read port.
data_memory:
process(clk)
begin
if clk'event and clk='1' and data_dtcm_ce='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
--if (to_integer(wait_states_data)=0) or (data_wait_ctr = 1) then
data_dtcm <= dtcm(to_integer(unsigned(dtcm_addr)));
--end if;
end if;
end process data_memory;
-- Simulated code RAM read port connected to the data bus.
code_memory_as_data:
process(clk)
begin
if clk'event and clk='1' and data_ctcm_ce='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
if (to_integer(wait_states_data)=0) or (data_wait_ctr = 1) then
data_ctcm <= ctcm(to_integer(unsigned(dtcm_addr)));
end if;
end if;
end process code_memory_as_data;
-- Read data will come from either the code array or the data array; we
-- to drive the mux with a delayed CE, the data bus is pipelined.
-- The data abus will be driven only when the ION bus specs say so, to
-- help pinpoint bugs in the bus logic.
data_miso.rd_data <=
data_dtcm when data_dtcm_ce_reg='1' and data_wait_ctr=0 else
data_ctcm when data_dtcm_ce_reg='0' and data_wait_ctr=0 else
(others => 'Z');
-- TODO Debug IO register inputs are unimplemented.
data_mem_wait_states:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
data_wait_ctr <= -2;
elsif data_dtcm_ce='1' and (data_mosi.rd_en='1' or data_mosi.wr_be/="0000") then
data_wait_ctr <= to_integer(wait_states_data);
elsif data_wait_ctr >= -1 then
data_wait_ctr <= data_wait_ctr - 1;
else
data_wait_ctr <= -2;
end if;
data_dtcm_ce_reg <= data_dtcm_ce;
data_rd_en_reg <= data_mosi.rd_en;
end if;
end process data_mem_wait_states;
dtcm_wait <= '1' when data_wait_ctr > 0 else '0';
-- Code memory -------------------------------------------------------------
ctcm_addr <= code_mosi.addr(ctcm_addr'high downto 2);
code_miso.mwait <= ctcm_wait;
code_memory:
process(clk)
begin
if clk'event and clk='1' then
-- Update data bus the cycle after rd_en is asserted if there's no
-- wait states, or the cycle after wait goes low otherwise.
if (to_integer(wait_states_code)=0) or (code_wait_ctr = 1) then
code_ctcm <= ctcm(to_integer(unsigned(ctcm_addr)));
end if;
end if;
end process code_memory;
code_miso.rd_data <=
code_ctcm when code_wait_ctr <= 0 else
(others => 'Z');
code_mem_wait_states:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
code_wait_ctr <= -2;
elsif code_mosi.rd_en='1' then
code_wait_ctr <= to_integer(wait_states_code);
elsif code_wait_ctr >= -1 then
code_wait_ctr <= code_wait_ctr - 1;
else
code_wait_ctr <= -2;
end if;
code_ctcm_ce_reg <= code_mosi.rd_en;
end if;
end process code_mem_wait_states;
ctcm_wait <= '1' when code_wait_ctr > 0 else '0';
-- Debug registers ---------------------------------------------------------
debug_reg_ce <= '1' when data_mosi.addr(31 downto 16) = X"2001" else '0';
debug_register_writes:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
wait_states_code <= to_unsigned(CODE_WCYCLES,wait_states_code'length);
wait_states_data <= to_unsigned(DATA_WCYCLES,wait_states_data'length);
else
if debug_reg_ce='1' and data_mosi.wr_be/="0000" and
ENABLE_DEBUG_REGISTERS then
case data_mosi.addr(15 downto 0) is
when X"0030" =>
wait_states_code <= unsigned(data_mosi.wr_data(5 downto 0));
when X"0034" =>
wait_states_data <= unsigned(data_mosi.wr_data(5 downto 0));
when others => -- ignore access.
end case;
end if;
end if;
end if;
end process debug_register_writes;
-- Placeholder signals, to be completed ------------------------------------
irq <= (others => '0');
icache_miso.present <= '0';
dcache_miso.present <= '0';
-- Logging process: launch logger function ---------------------------------
log_execution:
process
begin
log_cpu_activity(clk_delayed, reset, done,
"ION_CPU_TB", "cpu",
log_info, "log_info",
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
end architecture testbench;
| lgpl-3.0 |
HackLinux/ION | src/testbench/common/txt_util.vhdl | 4 | 14508 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| lgpl-3.0 |
HackLinux/ION | src/testbench/ion_core_tb.vhdl | 1 | 18175 | --##############################################################################
-- ion_core_tb.vhdl -- Test bench for full ION core.
--
-- Simulates the full ION core, which includes TCM and caches.
--
--------------------------------------------------------------------------------
-- KNOWN BUGS AND MISSING THINGS:
--
-- WB bridge not simulated with wait states.
-- WB bridge not simulated with 8 or 16 bit accesses, only 32.
--
--------------------------------------------------------------------------------
-- SIMULATED IO DEVICES:
--
-- This TB simulates the following IO devices as support for the test SW:
--
-- Address Name Size Access Purpose
---------------------------------------------------------------------------
-- ffff8000: DbgTxD : 8 : b : Debug UART TX buffer (W/o).
-- ffff8020: DbgRW0 : 32 : w : Debug register 0 (R/W).
-- ffff8024: DbgRW1 : 32 : w : Debug register 1 (R/W).
-- ffff8018: ExitReg : 32 : w : Exit register (W/o).
--
-- (b support byte access, w support word access).
--
-- The fake UART is implemented in package ion_tb_pkg, not as a proper WB
-- register but directly on the CPU buses.
-- The exit register is another ion_tb_pkg fake-register used to terminate the
-- execution of the TB; upon writing on it, the TB will stop and a success/fail
-- message will be output (success is 0, failure anything else).
-- All other debug registers are simulated as WB registers so they can be used
-- to verify the operation of the WB bridge.
--
--------------------------------------------------------------------------------
-- SIMULATED MEMORY:
--
-- Data cache refill port
-----------------------------
-- 80000000 4KB RAM (word access only).
-- 90000000 256MB ROM (test pattern).
--
--------------------------------------------------------------------------------
-- Console logging:
--
-- Console output (at address 0xffff8000) is logged to text file
-- "hw_sim_console_log.txt".
--
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
-- line buffering; it will not print anything until it gets a CR (0x0d), and
-- will ignore LFs (0x0a). Bear this in mind if you see no output when you
-- expect it.
--
-- Console logging is done by monitoring CPU writes to the UART, NOT by looking
-- at the TxD pin. It will NOT catch baud-related problems, etc.
--------------------------------------------------------------------------------
-- WARNING: Will only work on Modelsim 6.3+; uses proprietary library SignalSpy.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
use work.ION_TB_PKG.all;
-- Simulation parameters defined in the SW makefile (generated package).
use work.SIM_PARAMS_PKG.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
entity ION_CORE_TB is
end;
architecture testbench of ION_CORE_TB is
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Core interface.
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal code_wb_mosi : t_wishbone_mosi;
signal code_wb_miso : t_wishbone_miso;
signal data_wb_mosi : t_wishbone_mosi;
signal data_wb_miso : t_wishbone_miso;
signal data_uc_wb_mosi : t_wishbone_mosi;
signal data_uc_wb_miso : t_wishbone_miso;
signal cop2_mosi : t_cop2_mosi;
signal cop2_miso : t_cop2_miso;
signal irq : std_logic_vector(5 downto 0);
--------------------------------------------------------------------------------
-- Memory refill ports.
type t_natural_table is array(natural range <>) of natural;
-- Wait states simulated by data refill port (elements used in succession).
constant DATA_WS : t_natural_table (0 to 3) := (4,1,3,2);
signal data_wait_ctr : natural;
signal data_cycle_count : natural := 0;
signal data_address : t_word;
type t_ram_table is array(natural range <>) of t_word;
shared variable ram : t_ram_table(0 to 4095);
signal code_wait_ctr : natural;
signal code_cycle_count : natural := 0;
signal code_address : t_word;
--------------------------------------------------------------------------------
-- Uncached data WB bridge.
-- Wait states simulated by uncached WB port (elements used in succession).
-- FIXME wait state simulation disabled!
constant UNCACHED_WS : t_natural_table (0 to 3) := (0,0,0,0); --(4,1,3,2);
signal uwb_wait_ctr : natural;
signal uwb_cycle_count : natural := 0;
signal uwb_address : t_word;
shared variable debug_regs: t_ram_table(0 to 3);
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- All the info needed by the logger is here
signal log_info : t_log_info;
--------------------------------------------------------------------------------
begin
core: entity work.ION_CORE
generic map (
TCM_CODE_SIZE => CODE_MEM_SIZE,
TCM_CODE_INIT => OBJ_CODE,
TCM_DATA_SIZE => DATA_MEM_SIZE,
CODE_CACHE_LINES => 128,
DATA_CACHE_LINES => 128
)
port map (
CLK_I => clk,
RESET_I => reset,
CODE_WB_MOSI_O => code_wb_mosi,
CODE_WB_MISO_I => code_wb_miso,
DATA_WB_MOSI_O => data_wb_mosi,
DATA_WB_MISO_I => data_wb_miso,
DATA_UC_WB_MOSI_O => data_uc_wb_mosi,
DATA_UC_WB_MISO_I => data_uc_wb_miso,
COP2_MOSI_O => cop2_mosi,
COP2_MISO_I => cop2_miso,
IRQ_I => irq
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
-- Main simulation process: reset MCU and wait for fixed period ------------
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
-- Flush console output to log console file (in case the end of the
-- simulation caught an unterminated line in the buffer)
if log_info.con_line_ix > 1 then
write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
writeline(con_file, l);
end if;
print("TB finished");
done <= '1';
file_close(con_file);
wait;
end process drive_uut;
-- Data refill port interface ----------------------------------------------
-- Crudely simulate a WB interface with a variable number of delay cycles.
-- The number of wait cycles is taken from a table for variety's sake, this
-- model does not approach a real WB slave but should exercise the cache
-- sufficiently to flush out major bugs.
-- Note that this interface does NOT overlap successive reads nor cycles
-- with zero wait states!
-- TODO optional simulation of overlapped reads & zero waits.
data_refill_port:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
data_wait_ctr <= DATA_WS((data_cycle_count) mod DATA_WS'length);
data_wb_miso.ack <= '0';
data_wb_miso.dat <= (others => '1');
data_address <= (others => '0');
elsif data_wb_mosi.stb = '1' then
if data_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
data_wait_ctr <= data_wait_ctr - 1;
data_wb_miso.ack <= '0';
data_address <= data_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
data_wait_ctr <= DATA_WS((data_cycle_count+1) mod DATA_WS'length);
-- ...and drive the slave WB bus.
data_wb_miso.ack <= '1';
-- Termination is different for read and write accesses:
if data_wb_mosi.we = '1' then
-- Write access: do the simulated write.
-- FIXME do address decoding.
-- FIXME support byte & halfword writes.
ram(conv_integer(data_address(13 downto 2))) := data_wb_mosi.dat;
else
-- Read access: simulate read & WB slave multiplexor.
-- For simplicity´s sake, do the address decoding
-- right here and select between RAM and ROM.
if data_address(31 downto 28) = X"9" then
-- Fake data: low 16 bits of address replicated twice.
data_wb_miso.dat <= data_wb_mosi.adr(15 downto 0) &
data_wb_mosi.adr(15 downto 0);
elsif data_address(31 downto 28) = X"8" then
-- Simulated RAM.
data_wb_miso.dat <= ram(conv_integer(data_address(13 downto 2)));
else
-- Unmapped area: read zeros.
-- TODO should raise some sort of alert.
data_wb_miso.dat <= (others => '0');
end if;
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
data_wait_ctr <= DATA_WS((data_cycle_count) mod DATA_WS'length);
data_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if data_wb_mosi.stb = '1' and data_wait_ctr = 0 then
data_cycle_count <= data_cycle_count + 1;
end if;
end if;
end process data_refill_port;
-- stall the WB bus as long as the wait counter is not zero.
data_wb_miso.stall <=
'1' when data_wb_mosi.stb = '1' and data_wait_ctr > 0 else
'0';
-- Code refill port interface ----------------------------------------------
-- We do the same as for the data refill port, except we don't need to
-- support write cycles here.
-- the memory we will be reading is the same as the data bus -- no need to
-- simulate any arbitration.
-- Also, there's no test pattern ROM in this bus.
code_refill_port:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
code_wait_ctr <= DATA_WS((code_cycle_count) mod DATA_WS'length);
code_wb_miso.ack <= '0';
code_wb_miso.dat <= (others => '1');
code_address <= (others => '0');
elsif code_wb_mosi.stb = '1' then
if code_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
code_wait_ctr <= code_wait_ctr - 1;
code_wb_miso.ack <= '0';
code_address <= code_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
code_wait_ctr <= DATA_WS((code_cycle_count+1) mod DATA_WS'length);
-- ...and drive the slave WB bus.
code_wb_miso.ack <= '1';
-- We will ignore write accesses on this bus.
-- (We are already asserting that there aren't any anyway.)
-- FIXME add assertion
if data_wb_mosi.we = '0' then
-- Read access: simulate read & WB slave multiplexor.
if code_address(31 downto 28) = X"8" then
-- Simulated RAM.
code_wb_miso.dat <= ram(conv_integer(code_address(13 downto 2)));
else
-- Cached, unmapped area: read zeros.
-- TODO should raise some sort of alert.
code_wb_miso.dat <= (others => '0');
end if;
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
code_wait_ctr <= DATA_WS((code_cycle_count) mod DATA_WS'length);
code_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if code_wb_mosi.stb = '1' and code_wait_ctr = 0 then
code_cycle_count <= code_cycle_count + 1;
end if;
end if;
end process code_refill_port;
-- stall the WB bus as long as the wait counter is not zero.
code_wb_miso.stall <=
'1' when code_wb_mosi.stb = '1' and code_wait_ctr > 0 else
'0';
-- Uncached WB port --------------------------------------------------------
-- We only have the debug register on this WB bus so we will not bother
-- decoding the address and multiplexing the MISOs, etc.
uncached_wb_port:
process(clk)
variable debug_port : natural;
begin
if clk'event and clk='1' then
if reset = '1' then
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
data_uc_wb_miso.ack <= '0';
data_uc_wb_miso.dat <= (others => '1');
uwb_address <= (others => '0');
elsif data_uc_wb_mosi.stb = '1' then
debug_port := conv_integer(data_uc_wb_mosi.adr(3 downto 2));
if uwb_wait_ctr > 0 then
-- Access in progress, decrement wait counter...
uwb_wait_ctr <= data_wait_ctr - 1;
data_uc_wb_miso.ack <= '0';
uwb_address <= data_wb_mosi.adr;
else
-- Access finished, wait counter reached zero.
-- Prepare the wait counter for the next access...
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count+1) mod UNCACHED_WS'length);
-- ...and drive the slave WB bus.
data_uc_wb_miso.ack <= '1';
-- Termination is different for read and write accesses:
if data_uc_wb_mosi.we = '1' then
-- Write access: do the simulated write.
debug_regs(debug_port) := data_uc_wb_mosi.dat;
else
-- Read access: simulate read & WB slave multiplexor.
data_uc_wb_miso.dat <= debug_regs(debug_port);
end if;
end if;
else
-- No WB access is going on: restore the wait counter to its
-- idle state and deassert ACK.
uwb_wait_ctr <= UNCACHED_WS((uwb_cycle_count) mod UNCACHED_WS'length);
data_uc_wb_miso.ack <= '0';
end if;
-- Keep track of how many accesses we have performed.
-- We use this to select a number of wait states from a table.
if data_uc_wb_mosi.stb = '1' and uwb_wait_ctr = 0 then
uwb_cycle_count <= uwb_cycle_count + 1;
end if;
end if;
end process uncached_wb_port;
-- stall the WB bus as long as the wait counter is not zero.
data_uc_wb_miso.stall <=
'1' when data_uc_wb_mosi.stb = '1' and uwb_wait_ctr > 0 else
'0';
-- Dummy COP2 for interface testing ----------------------------------------
cop2: entity work.ION_COP2_STUB
port map (
CLK_I => clk,
RESET_I => reset,
CPU_MOSI_I => cop2_mosi,
CPU_MISO_O => cop2_miso
);
-- HW interrupt simulation -------------------------------------------------
-- All we do here is "feed back" into the hardware the value of a fake
-- register implemented in ion_tb_pkg.
interrupt_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
irq <= (others => '0');
else
irq <= log_info.hw_irq;
end if;
end if;
end process interrupt_registers;
-- Logging process: launch logger function ---------------------------------
log_execution:
process
begin
log_cpu_activity(clk, reset, done,
"ION_CORE_TB", "core/cpu",
log_info, "log_info",
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
end architecture testbench;
| lgpl-3.0 |
twlostow/dsi-shield | hdl/ip_cores/local/gc_sync_ffs.vhd | 1 | 3928 | -------------------------------------------------------------------------------
-- Title : Synchronizer chain
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : gc_sync_ffs.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-14
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Synchronizer chain and edge detector.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-14 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end gc_sync_ffs;
architecture behavioral of gc_sync_ffs is
signal sync0, sync1, sync2 : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute shreg_extract of sync2 : signal is "no";
attribute keep : string;
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
begin
sync_posedge : if (g_sync_edge = "positive") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif rising_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_posedge;
sync_negedge : if(g_sync_edge = "negative") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif falling_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_negedge;
end behavioral;
| lgpl-3.0 |
twlostow/dsi-shield | hdl/ip_cores/local/generic_sync_fifo.vhd | 2 | 4536 | -------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component inferred_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_empty => g_with_empty,
g_with_full => g_with_full,
g_with_almost_empty => g_with_almost_empty,
g_with_almost_full => g_with_almost_full,
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
empty_o => empty_o,
full_o => full_o,
almost_empty_o => almost_empty_o,
almost_full_o => almost_full_o,
count_o => count_o);
end syn;
| lgpl-3.0 |
twlostow/dsi-shield | hdl/top/rev1/reset_gen.vhd | 1 | 1205 | library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_gen;
architecture behavioral of reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
| lgpl-3.0 |
twlostow/dsi-shield | hdl/ip_cores/local/gc_pulse_synchronizer.vhd | 2 | 4191 | -------------------------------------------------------------------------------
-- Title : Pulse synchronizer
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : gc_pulse_synchronizer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2012-08-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Full feedback pulse synchronizer (works independently of the
-- input/output clock domain frequency ratio)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity gc_pulse_synchronizer is
port (
-- pulse input clock
clk_in_i : in std_logic;
-- pulse output clock
clk_out_i : in std_logic;
-- system reset (clk_in_i domain)
rst_n_i : in std_logic;
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o : out std_logic;
-- pulse input (clk_in_i domain)
d_p_i : in std_logic;
-- pulse output (clk_out_i domain)
q_p_o : out std_logic);
end gc_pulse_synchronizer;
architecture rtl of gc_pulse_synchronizer is
constant c_sync_stages : integer := 3;
signal ready, d_p_d0 : std_logic;
signal in_ext, out_ext : std_logic;
signal out_feedback : std_logic;
signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
begin -- rtl
process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
d_in2out <= (others => '0');
out_ext <= '0';
elsif rising_edge(clk_out_i) then
d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
out_ext <= d_in2out(c_sync_stages-1);
end if;
end process;
process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
d_out2in <= (others => '0');
elsif rising_edge(clk_in_i) then
d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
end if;
end process;
out_feedback <= d_out2in(c_sync_stages-1);
p_input_ack : process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
d_p_d0 <= d_p_i;
if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
in_ext <= '1';
ready <= '0';
elsif(in_ext = '1' and out_feedback = '1') then
in_ext <= '0';
elsif(in_ext = '0' and out_feedback = '0') then
ready <= '1';
end if;
end if;
end process;
p_drive_output : process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
q_p_o <= '0';
elsif rising_edge(clk_out_i) then
q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
end if;
end process;
d_ready_o <= ready;
end rtl;
| lgpl-3.0 |
trondd/mkjpeg | design/mdct/DCT1D.vhd | 8 | 11974 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| lgpl-3.0 |
trondd/mkjpeg | design/iramif.vhd | 2 | 2403 | -------------------------------------------------------------------------------
-- File Name : IRamIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : IRamIF
--
-- Content : IMAGE RAM Interface
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity IRamIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- IMAGE RAM
iram_addr : out std_logic_vector(19 downto 0);
iram_rdata : in std_logic_vector(23 downto 0);
-- FDCT
jpg_iram_rden : in std_logic;
jpg_iram_rdaddr : in std_logic_vector(31 downto 0);
jpg_iram_data : out std_logic_vector(23 downto 0)
);
end entity IRamIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of IRamIF is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
jpg_iram_data <= iram_rdata;
-------------------------------------------------------------------
--
-------------------------------------------------------------------
p_if : process(CLK, RST)
begin
if RST = '1' then
iram_addr <= (others => '0');
elsif CLK'event and CLK = '1' then
-- host has access
iram_addr <= jpg_iram_rdaddr(iram_addr'range);
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_xps_central_dma_1_wrapper.vhd | 1 | 10201 | -------------------------------------------------------------------------------
-- system_xps_central_dma_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_central_dma_v2_03_a;
use xps_central_dma_v2_03_a.all;
entity system_xps_central_dma_1_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to 31);
SPLB_BE : in std_logic_vector(0 to 7);
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to 2);
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to 63);
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to 63);
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end system_xps_central_dma_1_wrapper;
architecture STRUCTURE of system_xps_central_dma_1_wrapper is
component xps_central_dma is
generic (
C_FIFO_DEPTH : INTEGER;
C_RD_BURST_SIZE : INTEGER;
C_WR_BURST_SIZE : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to (C_SPLB_AWIDTH-1));
SPLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to (C_MPLB_AWIDTH-1));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
begin
xps_central_dma_1 : xps_central_dma
generic map (
C_FIFO_DEPTH => 8,
C_RD_BURST_SIZE => 8,
C_WR_BURST_SIZE => 8,
C_BASEADDR => X"80200000",
C_HIGHADDR => X"8020ffff",
C_SPLB_DWIDTH => 64,
C_SPLB_AWIDTH => 32,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_MID_WIDTH => 3,
C_SPLB_P2P => 0,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
SPLB_ABus => SPLB_ABus,
SPLB_BE => SPLB_BE,
SPLB_UABus => SPLB_UABus,
SPLB_PAValid => SPLB_PAValid,
SPLB_SAValid => SPLB_SAValid,
SPLB_rdPrim => SPLB_rdPrim,
SPLB_wrPrim => SPLB_wrPrim,
SPLB_masterID => SPLB_masterID,
SPLB_abort => SPLB_abort,
SPLB_busLock => SPLB_busLock,
SPLB_RNW => SPLB_RNW,
SPLB_MSize => SPLB_MSize,
SPLB_size => SPLB_size,
SPLB_type => SPLB_type,
SPLB_lockErr => SPLB_lockErr,
SPLB_wrDBus => SPLB_wrDBus,
SPLB_wrBurst => SPLB_wrBurst,
SPLB_rdBurst => SPLB_rdBurst,
SPLB_wrPendReq => SPLB_wrPendReq,
SPLB_rdPendReq => SPLB_rdPendReq,
SPLB_wrPendPri => SPLB_wrPendPri,
SPLB_rdPendPri => SPLB_rdPendPri,
SPLB_reqPri => SPLB_reqPri,
SPLB_TAttribute => SPLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
MPLB_MAddrAck => MPLB_MAddrAck,
MPLB_MSSize => MPLB_MSSize,
MPLB_MRearbitrate => MPLB_MRearbitrate,
MPLB_MTimeout => MPLB_MTimeout,
MPLB_MBusy => MPLB_MBusy,
MPLB_MRdErr => MPLB_MRdErr,
MPLB_MWrErr => MPLB_MWrErr,
MPLB_MIRQ => MPLB_MIRQ,
MPLB_MRdDBus => MPLB_MRdDBus,
MPLB_MRdWdAddr => MPLB_MRdWdAddr,
MPLB_MRdDAck => MPLB_MRdDAck,
MPLB_MRdBTerm => MPLB_MRdBTerm,
MPLB_MWrDAck => MPLB_MWrDAck,
MPLB_MWrBTerm => MPLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst
);
end architecture STRUCTURE;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/syn/vhdl/nfa_get_initials.vhd | 3 | 13072 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_117 : BOOLEAN;
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_116 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_read_reg_55 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_initials_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_55;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_117 assign process. --
ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
if (ap_sig_bdd_119) then
nfa_initials_buckets_address <= ap_const_lv32_1;
elsif (ap_sig_bdd_117) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_finals_buckets_if_plb_master_if.vhd | 2 | 37001 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_finals_buckets_if_plb_master_if is
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/indices_if_ap_fifo.vhd | 2 | 2819 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of indices_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/work/system_nfa_accept_samples_generic_hw_top_0_wrapper/_primary.vhd | 1 | 11883 | library verilog;
use verilog.vl_types.all;
entity system_nfa_accept_samples_generic_hw_top_0_wrapper is
port(
aclk : in vl_logic;
aresetn : in vl_logic;
indices_MPLB_Clk: in vl_logic;
indices_MPLB_Rst: in vl_logic;
indices_M_request: out vl_logic;
indices_M_priority: out vl_logic_vector(0 to 1);
indices_M_busLock: out vl_logic;
indices_M_RNW : out vl_logic;
indices_M_BE : out vl_logic_vector(0 to 7);
indices_M_MSize : out vl_logic_vector(0 to 1);
indices_M_size : out vl_logic_vector(0 to 3);
indices_M_type : out vl_logic_vector(0 to 2);
indices_M_TAttribute: out vl_logic_vector(0 to 15);
indices_M_lockErr: out vl_logic;
indices_M_abort : out vl_logic;
indices_M_UABus : out vl_logic_vector(0 to 31);
indices_M_ABus : out vl_logic_vector(0 to 31);
indices_M_wrDBus: out vl_logic_vector(0 to 63);
indices_M_wrBurst: out vl_logic;
indices_M_rdBurst: out vl_logic;
indices_PLB_MAddrAck: in vl_logic;
indices_PLB_MSSize: in vl_logic_vector(0 to 1);
indices_PLB_MRearbitrate: in vl_logic;
indices_PLB_MTimeout: in vl_logic;
indices_PLB_MBusy: in vl_logic;
indices_PLB_MRdErr: in vl_logic;
indices_PLB_MWrErr: in vl_logic;
indices_PLB_MIRQ: in vl_logic;
indices_PLB_MRdDBus: in vl_logic_vector(0 to 63);
indices_PLB_MRdWdAddr: in vl_logic_vector(0 to 3);
indices_PLB_MRdDAck: in vl_logic;
indices_PLB_MRdBTerm: in vl_logic;
indices_PLB_MWrDAck: in vl_logic;
indices_PLB_MWrBTerm: in vl_logic;
nfa_finals_buckets_MPLB_Clk: in vl_logic;
nfa_finals_buckets_MPLB_Rst: in vl_logic;
nfa_finals_buckets_M_request: out vl_logic;
nfa_finals_buckets_M_priority: out vl_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock: out vl_logic;
nfa_finals_buckets_M_RNW: out vl_logic;
nfa_finals_buckets_M_BE: out vl_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize: out vl_logic_vector(0 to 1);
nfa_finals_buckets_M_size: out vl_logic_vector(0 to 3);
nfa_finals_buckets_M_type: out vl_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute: out vl_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr: out vl_logic;
nfa_finals_buckets_M_abort: out vl_logic;
nfa_finals_buckets_M_UABus: out vl_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus: out vl_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus: out vl_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst: out vl_logic;
nfa_finals_buckets_M_rdBurst: out vl_logic;
nfa_finals_buckets_PLB_MAddrAck: in vl_logic;
nfa_finals_buckets_PLB_MSSize: in vl_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate: in vl_logic;
nfa_finals_buckets_PLB_MTimeout: in vl_logic;
nfa_finals_buckets_PLB_MBusy: in vl_logic;
nfa_finals_buckets_PLB_MRdErr: in vl_logic;
nfa_finals_buckets_PLB_MWrErr: in vl_logic;
nfa_finals_buckets_PLB_MIRQ: in vl_logic;
nfa_finals_buckets_PLB_MRdDBus: in vl_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr: in vl_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck: in vl_logic;
nfa_finals_buckets_PLB_MRdBTerm: in vl_logic;
nfa_finals_buckets_PLB_MWrDAck: in vl_logic;
nfa_finals_buckets_PLB_MWrBTerm: in vl_logic;
nfa_forward_buckets_MPLB_Clk: in vl_logic;
nfa_forward_buckets_MPLB_Rst: in vl_logic;
nfa_forward_buckets_M_request: out vl_logic;
nfa_forward_buckets_M_priority: out vl_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock: out vl_logic;
nfa_forward_buckets_M_RNW: out vl_logic;
nfa_forward_buckets_M_BE: out vl_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize: out vl_logic_vector(0 to 1);
nfa_forward_buckets_M_size: out vl_logic_vector(0 to 3);
nfa_forward_buckets_M_type: out vl_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute: out vl_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr: out vl_logic;
nfa_forward_buckets_M_abort: out vl_logic;
nfa_forward_buckets_M_UABus: out vl_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus: out vl_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus: out vl_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst: out vl_logic;
nfa_forward_buckets_M_rdBurst: out vl_logic;
nfa_forward_buckets_PLB_MAddrAck: in vl_logic;
nfa_forward_buckets_PLB_MSSize: in vl_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate: in vl_logic;
nfa_forward_buckets_PLB_MTimeout: in vl_logic;
nfa_forward_buckets_PLB_MBusy: in vl_logic;
nfa_forward_buckets_PLB_MRdErr: in vl_logic;
nfa_forward_buckets_PLB_MWrErr: in vl_logic;
nfa_forward_buckets_PLB_MIRQ: in vl_logic;
nfa_forward_buckets_PLB_MRdDBus: in vl_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr: in vl_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck: in vl_logic;
nfa_forward_buckets_PLB_MRdBTerm: in vl_logic;
nfa_forward_buckets_PLB_MWrDAck: in vl_logic;
nfa_forward_buckets_PLB_MWrBTerm: in vl_logic;
nfa_initials_buckets_MPLB_Clk: in vl_logic;
nfa_initials_buckets_MPLB_Rst: in vl_logic;
nfa_initials_buckets_M_request: out vl_logic;
nfa_initials_buckets_M_priority: out vl_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock: out vl_logic;
nfa_initials_buckets_M_RNW: out vl_logic;
nfa_initials_buckets_M_BE: out vl_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize: out vl_logic_vector(0 to 1);
nfa_initials_buckets_M_size: out vl_logic_vector(0 to 3);
nfa_initials_buckets_M_type: out vl_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute: out vl_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr: out vl_logic;
nfa_initials_buckets_M_abort: out vl_logic;
nfa_initials_buckets_M_UABus: out vl_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus: out vl_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus: out vl_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst: out vl_logic;
nfa_initials_buckets_M_rdBurst: out vl_logic;
nfa_initials_buckets_PLB_MAddrAck: in vl_logic;
nfa_initials_buckets_PLB_MSSize: in vl_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate: in vl_logic;
nfa_initials_buckets_PLB_MTimeout: in vl_logic;
nfa_initials_buckets_PLB_MBusy: in vl_logic;
nfa_initials_buckets_PLB_MRdErr: in vl_logic;
nfa_initials_buckets_PLB_MWrErr: in vl_logic;
nfa_initials_buckets_PLB_MIRQ: in vl_logic;
nfa_initials_buckets_PLB_MRdDBus: in vl_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr: in vl_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck: in vl_logic;
nfa_initials_buckets_PLB_MRdBTerm: in vl_logic;
nfa_initials_buckets_PLB_MWrDAck: in vl_logic;
nfa_initials_buckets_PLB_MWrBTerm: in vl_logic;
sample_buffer_MPLB_Clk: in vl_logic;
sample_buffer_MPLB_Rst: in vl_logic;
sample_buffer_M_request: out vl_logic;
sample_buffer_M_priority: out vl_logic_vector(0 to 1);
sample_buffer_M_busLock: out vl_logic;
sample_buffer_M_RNW: out vl_logic;
sample_buffer_M_BE: out vl_logic_vector(0 to 7);
sample_buffer_M_MSize: out vl_logic_vector(0 to 1);
sample_buffer_M_size: out vl_logic_vector(0 to 3);
sample_buffer_M_type: out vl_logic_vector(0 to 2);
sample_buffer_M_TAttribute: out vl_logic_vector(0 to 15);
sample_buffer_M_lockErr: out vl_logic;
sample_buffer_M_abort: out vl_logic;
sample_buffer_M_UABus: out vl_logic_vector(0 to 31);
sample_buffer_M_ABus: out vl_logic_vector(0 to 31);
sample_buffer_M_wrDBus: out vl_logic_vector(0 to 63);
sample_buffer_M_wrBurst: out vl_logic;
sample_buffer_M_rdBurst: out vl_logic;
sample_buffer_PLB_MAddrAck: in vl_logic;
sample_buffer_PLB_MSSize: in vl_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate: in vl_logic;
sample_buffer_PLB_MTimeout: in vl_logic;
sample_buffer_PLB_MBusy: in vl_logic;
sample_buffer_PLB_MRdErr: in vl_logic;
sample_buffer_PLB_MWrErr: in vl_logic;
sample_buffer_PLB_MIRQ: in vl_logic;
sample_buffer_PLB_MRdDBus: in vl_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr: in vl_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck: in vl_logic;
sample_buffer_PLB_MRdBTerm: in vl_logic;
sample_buffer_PLB_MWrDAck: in vl_logic;
sample_buffer_PLB_MWrBTerm: in vl_logic;
splb_slv0_SPLB_Clk: in vl_logic;
splb_slv0_SPLB_Rst: in vl_logic;
splb_slv0_PLB_ABus: in vl_logic_vector(0 to 31);
splb_slv0_PLB_UABus: in vl_logic_vector(0 to 31);
splb_slv0_PLB_PAValid: in vl_logic;
splb_slv0_PLB_SAValid: in vl_logic;
splb_slv0_PLB_rdPrim: in vl_logic;
splb_slv0_PLB_wrPrim: in vl_logic;
splb_slv0_PLB_masterID: in vl_logic_vector(0 to 2);
splb_slv0_PLB_abort: in vl_logic;
splb_slv0_PLB_busLock: in vl_logic;
splb_slv0_PLB_RNW: in vl_logic;
splb_slv0_PLB_BE: in vl_logic_vector(0 to 7);
splb_slv0_PLB_MSize: in vl_logic_vector(0 to 1);
splb_slv0_PLB_size: in vl_logic_vector(0 to 3);
splb_slv0_PLB_type: in vl_logic_vector(0 to 2);
splb_slv0_PLB_lockErr: in vl_logic;
splb_slv0_PLB_wrDBus: in vl_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst: in vl_logic;
splb_slv0_PLB_rdBurst: in vl_logic;
splb_slv0_PLB_wrPendReq: in vl_logic;
splb_slv0_PLB_rdPendReq: in vl_logic;
splb_slv0_PLB_wrPendPri: in vl_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri: in vl_logic_vector(0 to 1);
splb_slv0_PLB_reqPri: in vl_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute: in vl_logic_vector(0 to 15);
splb_slv0_Sl_addrAck: out vl_logic;
splb_slv0_Sl_SSize: out vl_logic_vector(0 to 1);
splb_slv0_Sl_wait: out vl_logic;
splb_slv0_Sl_rearbitrate: out vl_logic;
splb_slv0_Sl_wrDAck: out vl_logic;
splb_slv0_Sl_wrComp: out vl_logic;
splb_slv0_Sl_wrBTerm: out vl_logic;
splb_slv0_Sl_rdDBus: out vl_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr: out vl_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck: out vl_logic;
splb_slv0_Sl_rdComp: out vl_logic;
splb_slv0_Sl_rdBTerm: out vl_logic;
splb_slv0_Sl_MBusy: out vl_logic_vector(0 to 6);
splb_slv0_Sl_MWrErr: out vl_logic_vector(0 to 6);
splb_slv0_Sl_MRdErr: out vl_logic_vector(0 to 6);
splb_slv0_Sl_MIRQ: out vl_logic_vector(0 to 6)
);
end system_nfa_accept_samples_generic_hw_top_0_wrapper;
| lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/impl/vhdl/nfa_accept_samples_generic_hw_add_6ns_6ns_6_2.vhd | 3 | 7081 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(5 downto 0);
b: in std_logic_vector(5 downto 0);
s: out std_logic_vector(5 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(5 downto 0);
signal b_reg : std_logic_vector(5 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(2 downto 0);
signal b0_cb : std_logic_vector(2 downto 0);
signal a1_cb : std_logic_vector(5 downto 3);
signal b1_cb : std_logic_vector(5 downto 3);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
-- wires for each full adder sum
signal fas : std_logic_vector(5 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal s0_ca_rego0 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(5 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(2 downto 0);
b0_cb <= b_reg(2 downto 0);
a1_cb <= a_reg(5 downto 3);
b1_cb <= b_reg(5 downto 3);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(2 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(5 downto 3),
facout => faccout1_co1);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(2 downto 0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(2 downto 0) <= s0_ca_rego0(0);
s_tmp(5 downto 3) <= fas(5 downto 3);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_get_finals/_primary.vhd | 1 | 2755 | library verilog;
use verilog.vl_types.all;
entity nfa_get_finals is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0);
ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0);
ap_ST_pp0_stg2_fsm_2: vl_logic_vector(0 to 1) := (Hi0, Hi1);
ap_ST_pp0_stg3_fsm_3: vl_logic_vector(0 to 1) := (Hi1, Hi1);
ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv32_0 : integer := 0;
ap_const_lv32_1 : integer := 1;
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
ap_ce : in vl_logic;
nfa_finals_buckets_req_din: out vl_logic;
nfa_finals_buckets_req_full_n: in vl_logic;
nfa_finals_buckets_req_write: out vl_logic;
nfa_finals_buckets_rsp_empty_n: in vl_logic;
nfa_finals_buckets_rsp_read: out vl_logic;
nfa_finals_buckets_address: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_finals_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_size: out vl_logic_vector(31 downto 0);
ap_return_0 : out vl_logic_vector(31 downto 0);
ap_return_1 : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg1_fsm_1 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg2_fsm_2 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg3_fsm_3 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end nfa_get_finals;
| lgpl-3.0 |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_xps_intc_0_wrapper.vhd | 1 | 6997 | -------------------------------------------------------------------------------
-- system_xps_intc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_intc_v2_01_a;
use xps_intc_v2_01_a.all;
entity system_xps_intc_0_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 5);
Intr : in std_logic_vector(1 downto 0);
Irq : out std_logic
);
end system_xps_intc_0_wrapper;
architecture STRUCTURE of system_xps_intc_0_wrapper is
component xps_intc is
generic (
C_FAMILY : STRING;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_KIND_OF_INTR : std_logic_vector(31 downto 0);
C_KIND_OF_EDGE : std_logic_vector(31 downto 0);
C_KIND_OF_LVL : std_logic_vector(31 downto 0);
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : std_logic
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0);
Irq : out std_logic
);
end component;
begin
xps_intc_0 : xps_intc
generic map (
C_FAMILY => "virtex5",
C_BASEADDR => X"81800000",
C_HIGHADDR => X"8180ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_SPLB_P2P => 0,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_NUM_INTR_INPUTS => 2,
C_KIND_OF_INTR => B"11111111111111111111111111111100",
C_KIND_OF_EDGE => B"11111111111111111111111111111111",
C_KIND_OF_LVL => B"11111111111111111111111111111111",
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1'
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ,
Intr => Intr,
Irq => Irq
);
end architecture STRUCTURE;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/wb_un_cross/cross_uncross_core/un_cross_top.vhd | 1 | 7329 | ------------------------------------------------------------------------------
-- Title : Cross and Uncross Top Entity
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design is the top which put together all cores involved
-- in cross and uncross operation in channel pairs.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-09 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity un_cross_top is
generic(
g_delay_vec_width : natural range 0 to 16 := 16;
g_swap_div_freq_vec_width : natural range 0 to 16 := 16
);
port(
-- Commom signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- inv_chs_top core signal
const_aa_i : in std_logic_vector(15 downto 0);
const_bb_i : in std_logic_vector(15 downto 0);
const_cc_i : in std_logic_vector(15 downto 0);
const_dd_i : in std_logic_vector(15 downto 0);
const_ac_i : in std_logic_vector(15 downto 0);
const_bd_i : in std_logic_vector(15 downto 0);
const_ca_i : in std_logic_vector(15 downto 0);
const_db_i : in std_logic_vector(15 downto 0);
delay1_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
delay2_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
flag1_o : out std_logic;
flag2_o : out std_logic;
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
-- Swap clock for RFFE
clk_swap_o : out std_logic;
clk_swap_en_i : in std_logic;
-- swap_cnt_top signal
mode1_i : in std_logic_vector(1 downto 0);
mode2_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
ext_clk_i : in std_logic;
ext_clk_en_i : in std_logic;
-- Output to RFFE board
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end un_cross_top;
architecture rtl of un_cross_top is
signal status1 : std_logic;
signal status2 : std_logic;
-------------------------------------------------------
-- components declaration
-------------------------------------------------------
component swap_cnt_top
generic(
g_swap_div_freq_vec_width : natural range 0 to 16 := g_swap_div_freq_vec_width
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
mode1_i : in std_logic_vector(1 downto 0);
mode2_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
ext_clk_i : in std_logic;
ext_clk_en_i : in std_logic;
clk_swap_o : out std_logic;
clk_swap_en_i : in std_logic;
status1_o : out std_logic;
status2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end component;
component inv_chs_top
generic(
g_delay_vec_width : natural range 0 to 16 := g_delay_vec_width
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
const_aa_i : in std_logic_vector(15 downto 0);
const_bb_i : in std_logic_vector(15 downto 0);
const_cc_i : in std_logic_vector(15 downto 0);
const_dd_i : in std_logic_vector(15 downto 0);
const_ac_i : in std_logic_vector(15 downto 0);
const_bd_i : in std_logic_vector(15 downto 0);
const_ca_i : in std_logic_vector(15 downto 0);
const_db_i : in std_logic_vector(15 downto 0);
delay1_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
delay2_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
status1_i : in std_logic;
status2_i : in std_logic;
status_en_i : in std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0));
end component;
begin
-------------------------------------------------------
-- components instantiation
-------------------------------------------------------
cross_component: swap_cnt_top
generic map (
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
mode1_i => mode1_i,
mode2_i => mode2_i,
swap_div_f_i => swap_div_f_i,
ext_clk_i => ext_clk_i,
ext_clk_en_i => ext_clk_en_i,
clk_swap_o => clk_swap_o,
clk_swap_en_i => clk_swap_en_i,
status1_o => status1,
status2_o => status2,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
uncross_component: inv_chs_top
generic map (
g_delay_vec_width => g_delay_vec_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
const_aa_i => const_aa_i,
const_bb_i => const_bb_i,
const_cc_i => const_cc_i,
const_dd_i => const_dd_i,
const_ac_i => const_ac_i,
const_bd_i => const_bd_i,
const_ca_i => const_ca_i,
const_db_i => const_db_i,
delay1_i => delay1_i,
delay2_i => delay2_i,
status1_i => status1,
status2_i => status2,
status_en_i => clk_swap_en_i,
--output for debugging
flag1_o => flag1_o,
flag2_o => flag2_o,
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o
);
end;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_eb3f5e21c238e176.vhd | 1 | 6993 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_eb3f5e21c238e176.vhd when simulating
-- the core, fr_cmplr_v6_3_eb3f5e21c238e176. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_eb3f5e21c238e176 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_eb3f5e21c238e176;
ARCHITECTURE fr_cmplr_v6_3_eb3f5e21c238e176_a OF fr_cmplr_v6_3_eb3f5e21c238e176 IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_eb3f5e21c238e176
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_eb3f5e21c238e176 USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "45,45",
c_accum_path_widths => "45,45",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_eb3f5e21c238e176.mif",
c_coef_file_lines => 140,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0,0",
c_coef_path_src => "0,0",
c_coef_path_widths => "16,16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "4",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_eb3f5e21c238e176",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0,0",
c_data_path_src => "0,1",
c_data_path_widths => "24,24",
c_data_width => 24,
c_datapath_memtype => 1,
c_decim_rate => 35,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 1,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 12,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 64,
c_m_data_tuser_width => 1,
c_mem_arrangement => 1,
c_num_channels => 2,
c_num_filts => 1,
c_num_madds => 4,
c_num_reload_slots => 1,
c_num_taps => 248,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25,25",
c_output_rate => 35,
c_output_width => 25,
c_oversampling_rate => 1,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 48,
c_s_data_tuser_width => 1,
c_symmetry => 1,
c_xdevicefamily => "virtex6",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_eb3f5e21c238e176
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_eb3f5e21c238e176_a;
| lgpl-3.0 |
lerwys/GitTest | hdl/modules/wb_un_cross/cross_uncross_core/dyn_mult_2chs.vhd | 1 | 4712 | ------------------------------------------------------------------------------
-- Title : Dynamic Multiplication in One Channel Pair
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design does what we call, dynamic multiplication. It
-- means that we have a specific multiplicator for each
-- different RF channel took by signal.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 jose.berkenbrock Created
-- 2013-03-17 1.1 jose.berkenbrock Output Changed
-- 2013-07-01 1.2 lucas.russo Changed to synchronous resets
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dyn_mult_2chs is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
const_11_i : in std_logic_vector(15 downto 0);
const_22_i : in std_logic_vector(15 downto 0);
const_12_i : in std_logic_vector(15 downto 0);
const_21_i : in std_logic_vector(15 downto 0);
ch1_i : in std_logic_vector(15 downto 0);
ch2_i : in std_logic_vector(15 downto 0);
ch1_o : out std_logic_vector(15 downto 0);
ch2_o : out std_logic_vector(15 downto 0)
);
end dyn_mult_2chs;
architecture rtl of dyn_mult_2chs is
signal en, en_old : std_logic;
signal flag : std_logic;
signal ch11_mult : std_logic_vector(31 downto 0);
signal ch22_mult : std_logic_vector(31 downto 0);
signal ch12_mult : std_logic_vector(31 downto 0);
signal ch21_mult : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- Component Declaration
----------------------------------------------------------------
component multiplier_u16x16_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
p : out std_logic_vector(31 downto 0)
);
end component;
begin
----------------------------------------------------------------
-- Component instantiation
----------------------------------------------------------------
mult11 : multiplier_u16x16_DSP -- Signal 1 by channel 1
port map (
clk => clk_i,
a => ch1_i,
b => const_11_i, -- UFIX_16_15
p => ch11_mult
);
mult22 : multiplier_u16x16_DSP -- Signal 2 by channel 2
port map (
clk => clk_i,
a => ch2_i,
b => const_22_i,-- UFIX_16_15
p => ch22_mult
);
mult12 : multiplier_u16x16_DSP -- Signal 1 by channel 2
port map (
clk => clk_i,
a => ch1_i,
b => const_12_i,-- UFIX_16_15
p => ch12_mult
);
mult21 : multiplier_u16x16_DSP -- Signal 2 by channel 1
port map (
clk => clk_i,
a => ch2_i,
b => const_21_i,-- UFIX_16_15
p => ch21_mult
);
reg_en_proc: process(clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
en <= '0';
en_old <= '0';
else
en <= en_i;
en_old <= en;
end if;
end if;
end process reg_en_proc;
inv_proc: process(clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
flag <= '0';
else
if ((en = '1') and (en_old = '0')) then
flag <= not flag;
end if;
end if;
end if;
end process inv_proc;
output_proc: process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= ch11_mult(31 downto 16);
ch2_o <= ch22_mult(31 downto 16);
else
if (flag = '1') then -- inverted
ch1_o <= ch12_mult(31 downto 16);
ch2_o <= ch21_mult(31 downto 16);
else
ch1_o <= ch11_mult(31 downto 16);
ch2_o <= ch22_mult(31 downto 16);
end if;
end if;
end if;
end process output_proc;
end rtl;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/communication/i2c_master.vhd | 2 | 8283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:10 07/01/2014
-- Design Name:
-- Module Name: i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end i2c_master;
architecture Behavioral of i2c_master is
constant clk_div : positive := ((clk_freq_hz/i2c_freq_hz)/4)-1 ;
TYPE master_state IS (IDLE, I2C_START, TX_ADDR, ACK_ADDR, TX_BYTE, RX_BYTE, ACK_BYTE, HOLDING, I2C_STOP) ;
signal cur_state, next_state : master_state ;
signal modulo_counter : std_logic_vector(15 downto 0);
signal end_modulo : std_logic ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal quarter, half, full : std_logic ;
signal transmit_buffer, receive_buffer, addr_buffer : std_logic_vector(7 downto 0);
signal bit_counter : std_logic_vector(2 downto 0);
signal write_mode : std_logic ;
signal sda_unbuf, sda_latched : std_logic ;
signal sda_shift_reg : std_logic_vector(5 downto 0);
signal is_acked : std_logic ;
begin
process(clk, reset)
begin
if reset = '1' then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif clk'event and clk = '1' then
if cur_state = IDLE then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif modulo_counter = 0 then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= cycle_counter + 1;
else
modulo_counter <= modulo_counter - 1 ;
end if ;
end if ;
end process ;
end_modulo <= '1' when modulo_counter = 0 else
'0' ;
quarter <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
half <= '1' when cycle_counter = 2 else
'0' ;
full <= '1' when cycle_counter = 3 and end_modulo = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, bit_counter, write_mode, cycle_counter, end_modulo, quarter, half, full, i2c_write, i2c_read, sda)
begin
next_state <= cur_state ;
case (cur_state) is
when IDLE =>
if i2c_write = '1' then
next_state <= I2C_START ;
elsif i2c_read = '1' then
next_state <= I2C_START ;
end if ;
when I2C_START =>
if full = '1' then
next_state <= TX_ADDR ;
end if ;
when TX_ADDR =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_ADDR ;
end if ;
when ACK_ADDR =>
if full = '1' and is_acked = '1' and write_mode = '1' then
next_state <= TX_BYTE ;
elsif full = '1' and is_acked = '1' and write_mode = '0' then
next_state <= RX_BYTE ;
elsif full = '1' and is_acked = '0' then
next_state <= I2C_STOP ;
end if ;
when TX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when RX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when ACK_BYTE =>
if full = '1' and i2c_write = '1' and is_acked = '1' then --
next_state <= TX_BYTE ;
elsif full = '1' and i2c_read = '1' then
next_state <= RX_BYTE ;
elsif full = '1' then
next_state <= I2C_STOP ;
end if ;
when I2C_STOP =>
if full = '1' then
next_state <= IDLE ;
end if ;
when others =>
end case ;
end process ;
scl <= 'Z' when cur_state = I2C_START and cycle_counter < 2 else
'0' when cur_state = I2C_START and cycle_counter >= 2 else
'Z' when cur_state = IDLE else
'0' when cycle_counter < 2 else
'Z' ;
sda_unbuf <= '0' when cur_state = I2C_START else
'0' when cur_state = I2C_STOP and cycle_counter <= 2 else
'1' when cur_state = I2C_STOP and cycle_counter > 2 else -- need to make sure its enough ...
'1' when cur_state = IDLE else
'1' when cur_state = TX_ADDR and addr_buffer(7) = '1' else
'0' when cur_state = TX_ADDR and addr_buffer(7) = '0' else
'1' when cur_state = TX_BYTE and transmit_buffer(7) = '1' else
'0' when cur_state = TX_BYTE and transmit_buffer(7) = '0' else
'0' when cur_state = ACK_BYTE and write_mode = '0' and i2c_read = '1' else
'1' ;
process(clk, reset)
begin
if reset = '1' then
sda_shift_reg <= (others => '1');
elsif clk'event and clk = '1' then
sda_shift_reg(0) <= sda_unbuf ;
sda_shift_reg(sda_shift_reg'high downto 1) <= sda_shift_reg(sda_shift_reg'high-1 downto 0);
end if ;
end process ;
sda <= 'Z' when cur_state = ACK_BYTE and write_mode = '1' else
'0' when sda_shift_reg(sda_shift_reg'high) = '0' else
'Z' ;
process(clk, reset)
begin
if reset = '1' then
is_acked <= '0' ;
elsif clk'event and clk = '1' then
if (cur_state = ACK_BYTE or cur_state = ACK_ADDR ) and sda = '0' then
is_acked <= '1' ;
elsif cur_state /= ACK_BYTE then
is_acked <= '0' ;
end if ;
end if ;
end process ;
ack <= '1' when cur_state = ACK_BYTE and is_acked = '1' and full = '1' else
'1' when cur_state = ACK_BYTE and next_state = RX_BYTE else
'1' when cur_state = ACK_ADDR and is_acked = '1' and full = '1' else
'0' ;
nack <= '1' when cur_state = ACK_BYTE and write_mode = '1' and full='1' and is_acked = '0' else
'1' when cur_state = ACK_ADDR and full='1' and is_acked = '0' else
'0' ;
busy <= '0' when cur_state = IDLE else
'1' ;
new_data <= '1' when cur_state = ACK_BYTE and write_mode = '0' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
transmit_buffer <= (others => '0') ;
receive_buffer <= (others => '0') ;
addr_buffer <= (others => '0') ;
bit_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if (cur_state = IDLE and i2c_write = '1') or i2c_read = '1' then
addr_buffer <= slave_addr & i2c_read ;
elsif cur_state = TX_ADDR and full = '1' then
addr_buffer(7 downto 1) <= addr_buffer(6 downto 0);
end if;
if cur_state = IDLE and i2c_write = '1' then
transmit_buffer <= data_in ;
elsif cur_state = TX_BYTE and full = '1' then
transmit_buffer(7 downto 1) <= transmit_buffer(6 downto 0);
transmit_buffer(0) <= '0' ;
elsif cur_state = ACK_BYTE and i2c_write = '1' and is_acked = '1' then
transmit_buffer <= data_in;
end if;
if cur_state = IDLE then
receive_buffer <= (others => '0') ;
elsif cur_state = RX_BYTE and half = '1' then
receive_buffer(7 downto 1) <= receive_buffer(6 downto 0);
receive_buffer(0) <= sda ;
end if;
if cur_state = IDLE or cur_state = ACK_BYTE or cur_state = ACK_ADDR then
bit_counter <= (others => '0') ;
elsif (cur_state = TX_ADDR or cur_state = TX_BYTE) and full = '1' then
bit_counter <= bit_counter + 1 ;
end if;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
write_mode <= '0' ;
elsif clk'event and clk = '1' then
if cur_state = IDLE and i2c_write = '1' then
write_mode <= '1' ;
elsif cur_state = I2C_STOP then
write_mode <= '0' ;
end if;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 |
fpga-logi/logi-hard | test_bench/spi_wishbone_wrapper_tb.vhd | 1 | 4713 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:10:51 11/21/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/spi_wishbone_wrapper_tb.vhd
-- Project Name: logipi_wishbone
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_wishbone_wrapper
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY spi_wishbone_wrapper_tb IS
END spi_wishbone_wrapper_tb;
ARCHITECTURE behavior OF spi_wishbone_wrapper_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_wishbone_wrapper
PORT(
mosi : IN std_logic;
ss : IN std_logic;
sck : IN std_logic;
miso : OUT std_logic;
gls_reset : IN std_logic;
gls_clk : IN std_logic;
wbm_address : OUT std_logic_vector(15 downto 0);
wbm_readdata : IN std_logic_vector(15 downto 0);
wbm_writedata : OUT std_logic_vector(15 downto 0);
wbm_strobe : OUT std_logic;
wbm_write : OUT std_logic;
wbm_ack : IN std_logic;
wbm_cycle : OUT std_logic
);
END COMPONENT;
--Inputs
signal mosi : std_logic := '0';
signal ss : std_logic := '0';
signal sck : std_logic := '0';
signal gls_reset : std_logic := '0';
signal gls_clk : std_logic := '0';
signal wbm_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal wbm_ack : std_logic := '0';
--Outputs
signal miso : std_logic;
signal wbm_address : std_logic_vector(15 downto 0);
signal wbm_writedata : std_logic_vector(15 downto 0);
signal wbm_strobe : std_logic;
signal wbm_write : std_logic;
signal wbm_cycle : std_logic;
-- Clock period definitions
constant gls_clk_period : time := 10 ns;
constant sck_period : time := 100 ns;
constant wr_conf : std_logic_vector(15 downto 0) := X"AA50";
constant rd_conf : std_logic_vector(15 downto 0) := X"AA53";
constant data_wr : std_logic_vector(15 downto 0) := X"BB57";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spi_wishbone_wrapper PORT MAP (
mosi => mosi,
ss => ss,
sck => sck,
miso => miso,
gls_reset => gls_reset,
gls_clk => gls_clk,
wbm_address => wbm_address,
wbm_readdata => wbm_readdata,
wbm_writedata => wbm_writedata,
wbm_strobe => wbm_strobe,
wbm_write => wbm_write,
wbm_ack => wbm_ack,
wbm_cycle => wbm_cycle
);
-- Clock process definitions
gls_clk_process :process
begin
gls_clk <= '0';
wait for gls_clk_period/2;
gls_clk <= '1';
wait for gls_clk_period/2;
end process;
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
wbm_readdata <= (others => '0');
wbm_ack <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if wbm_strobe = '1' and wbm_cycle = '1' then
wbm_readdata <= wbm_address ;
wbm_ack <= '1' ;
else
wbm_ack <= '0' ;
end if ;
end if ;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
gls_reset <= '1' ;
ss <= '1' ;
sck <= '0' ;
wait for 100 ns;
gls_reset <= '0' ;
wait for gls_clk_period*10;
ss <= '0' ;
wait for sck_period;
loop_read_addr: FOR a IN 0 TO 15 LOOP -- la variable de boucle est a de 1 à 10
sck <= '0' ;
mosi <= rd_conf(15 - a) ;
WAIT FOR sck_period/2; -- attend la valeur de pulse_time
sck <= '1' ; -- complémente clk1
WAIT FOR sck_period/2;
END LOOP loop_read_addr;
loop_read_data: FOR a IN 0 TO 64 LOOP -- la variable de boucle est a de 1 à 10
sck <= '0' ;
mosi <= '1' ;
WAIT FOR sck_period/2; -- attend la valeur de pulse_time
sck <= '1' ; -- complémente clk1
WAIT FOR sck_period/2;
END LOOP loop_read_data;
sck <= '0' ;
wait for sck_period;
ss <= '1' ;
wait;
end process;
END;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/utils/small_fifo.vhd | 2 | 2306 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end small_fifo;
architecture Behavioral of small_fifo is
type mem_array is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal fifo : mem_array ;
signal rd_ptr, wr_ptr : integer range 0 to DEPTH-1 ;
signal full_t, empty_t : std_logic ;
signal nb_available : integer range 0 to DEPTH-1 ;
begin
process(clk, resetn)
begin
if resetn = '0' then
rd_ptr <= 0 ;
wr_ptr <= 0 ;
nb_available <= 0 ;
elsif clk'event and clk = '1' then
if push = '1' and full_t = '0' then
wr_ptr <= (wr_ptr + 1) ;
fifo(wr_ptr) <= data_in ;
if pop = '0' then
nb_available <= nb_available + 1 ;
end if ;
end if ;
if pop = '1' and empty_t = '0' then
rd_ptr <= rd_ptr + 1 ;
if push = '0' then
nb_available <= nb_available - 1 ;
end if ;
end if ;
end if ;
end process ;
full_t <= '1' when nb_available = DEPTH-1 else
'0' ;
empty_t <= '1' when nb_available = 0 else
'0' ;
data_out <= fifo(rd_ptr) when empty_t = '0' else
(others => '0');
limit <= '1' when nb_available >= THRESHOLD else
'0' ;
empty <= empty_t ;
full <= full_t ;
end Behavioral;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/wishbone/wishbone_intercon.vhd | 2 | 3410 | -- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_pack.all ;
entity wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end wishbone_intercon;
architecture Behavioral of wishbone_intercon is
signal cs_vector : std_logic_vector(0 to (memory_map'length-1));
signal ack_vector : std_logic_vector(0 to (memory_map'length-1));
begin
gen_cs : for i in 0 to (memory_map'length-1) generate
cs_vector(i) <= '1' when wbs_address(wbs_address'length-1 downto find_X(memory_map(i))) = memory_map(i)(wbs_address'length-1 downto find_X(memory_map(i))) else
'0' ;
ack_vector(i) <= wbm_ack(i) and cs_vector(i) ;
wbm_address(i)(wbs_address'length-1 downto find_X(memory_map(i))) <= (others => '0') ;
wbm_address(i)(find_X(memory_map(i))-1 downto 0) <= wbs_address(find_X(memory_map(i))-1 downto 0) ;
wbm_writedata(i) <= wbs_writedata ;
wbm_write(i) <= wbs_write and cs_vector(i) ;
wbm_strobe(i) <= wbs_strobe and cs_vector(i) ;
wbm_cycle(i) <= wbs_cycle and cs_vector(i) ;
wbs_readdata <= wbm_readdata(i) when cs_vector(i) = '1' else
(others => 'Z') ;
end generate ;
wbs_ack <= '1' when ack_vector /= 0 else
'0' ;
wbs_readdata <= wbs_address when cs_vector = 0 else
(others => 'Z') ;
end Behavioral;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/wishbone/peripherals/wishbone_7seg4x.vhd | 2 | 5211 | -- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:53 12/17/2013
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description: 4 sseg slave module. Recieve 4x sseg values that will be used on LOGi-EDU board
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_7seg4x is
generic(
wb_size : natural := 16; -- Data port size for wishbone
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end wishbone_7seg4x;
architecture Behavioral of wishbone_7seg4x is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
--sseg register data
signal sseg_edu_regs: slv16_array(0 to 2);
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal divider_counter : std_logic_vector(nbit(clk_divider)-1 downto 0);
signal divider_end : std_logic ;
signal cathode_buffer : std_logic_vector(4 downto 0);
begin
wbs_ack <= read_ack or write_ack;
--WBM-WRITE
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
sseg_edu_regs <= (others => (others => '0')) ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
sseg_edu_regs(conv_integer(wbs_address(1 downto 0))) <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
--WBM-READ
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= sseg_edu_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
-- sseg logic
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
elsif gls_clk'event and gls_clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cathode_buffer(0) <= '1' ;
cathode_buffer(4 downto 1) <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if divider_end = '1' then
cathode_buffer(4 downto 1) <= cathode_buffer(3 downto 0);
cathode_buffer(0) <= cathode_buffer(4);
end if ;
end if ;
end process ;
with cathode_buffer select
sseg_anode_out <= sseg_edu_regs(0)(7 downto 0) when "00001",
sseg_edu_regs(0)(15 downto 8) when "00010",
sseg_edu_regs(1)(7 downto 0) when "00100",
sseg_edu_regs(1)(15 downto 8) when "01000",
sseg_edu_regs(2)(7 downto 0) when "10000",
(others => '0') when others ;
sseg_cathode_out <= cathode_buffer ;
end Behavioral;
| lgpl-3.0 |
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